path: root/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000761                       # Number of seconds simulated
sim_ticks                                   761298000                       # Number of ticks simulated
final_tick                                  761298000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_tick_rate                              219241825                       # Simulator tick rate (ticks/s)
host_mem_usage                                 341324                       # Number of bytes of host memory used
host_seconds                                     3.47                       # Real time elapsed on the host
system.physmem.bytes_read::cpu0                 89717                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1                 92471                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2                 92156                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3                 88405                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu4                 90559                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu5                 92920                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu6                 90802                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu7                 90403                       # Number of bytes read from this memory
system.physmem.bytes_read::total               727433                       # Number of bytes read from this memory
system.physmem.bytes_written::writebacks       479872                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0               5444                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1               5306                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu2               5518                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu3               5318                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu4               5329                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu5               5364                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu6               5370                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu7               5377                       # Number of bytes written to this memory
system.physmem.bytes_written::total            522898                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0                  11345                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1                  11075                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2                  11201                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3                  11041                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4                  11368                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5                  11335                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6                  11107                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7                  11275                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 89747                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks            7498                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0                  5444                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1                  5306                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2                  5518                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3                  5318                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4                  5329                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5                  5364                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6                  5370                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7                  5377                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                50524                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0                117847413                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1                121464919                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2                121051152                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3                116124041                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4                118953419                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5                122054701                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6                119272611                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7                118748506                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               955516762                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         630333982                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0                 7150945                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1                 6969675                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2                 7248147                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3                 6985438                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4                 6999887                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5                 7045861                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6                 7053742                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7                 7062937                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              686850616                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         630333982                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0               124998358                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1               128434595                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2               128299299                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3               123109479                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4               125953306                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5               129100562                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6               126326353                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7               125811443                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             1642367378                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                         15728                       # number of replacements
system.l2c.tagsinuse                       804.643799                       # Cycle average of tags in use
system.l2c.total_refs                          152339                       # Total number of references to valid blocks.
system.l2c.sampled_refs                         16530                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          9.215910                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks          741.658747                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0                  7.524103                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1                  7.613306                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2                  7.692083                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3                  7.940636                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu4                  7.758878                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu5                  8.184629                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu6                  8.593994                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu7                  7.677424                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.724276                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0                 0.007348                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1                 0.007435                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2                 0.007512                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3                 0.007755                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu4                 0.007577                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu5                 0.007993                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu6                 0.008393                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu7                 0.007497                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.785785                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0                   11015                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1                   10772                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2                   10969                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3                   10679                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu4                   10886                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu5                   10950                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu6                   10937                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu7                   10991                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  87199                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks           77421                       # number of Writeback hits
system.l2c.Writeback_hits::total                77421                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0                  343                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1                  333                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2                  352                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3                  370                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4                  362                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5                  336                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6                  391                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7                  398                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                2885                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0                  2096                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1                  2090                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2                  2017                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3                  2119                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4                  2028                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5                  2062                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6                  2112                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7                  2055                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                16579                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0                    13111                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1                    12862                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2                    12986                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3                    12798                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu4                    12914                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu5                    13012                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu6                    13049                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu7                    13046                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  103778                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0                   13111                       # number of overall hits
system.l2c.overall_hits::cpu1                   12862                       # number of overall hits
system.l2c.overall_hits::cpu2                   12986                       # number of overall hits
system.l2c.overall_hits::cpu3                   12798                       # number of overall hits
system.l2c.overall_hits::cpu4                   12914                       # number of overall hits
system.l2c.overall_hits::cpu5                   13012                       # number of overall hits
system.l2c.overall_hits::cpu6                   13049                       # number of overall hits
system.l2c.overall_hits::cpu7                   13046                       # number of overall hits
system.l2c.overall_hits::total                 103778                       # number of overall hits
system.l2c.ReadReq_misses::cpu0                   811                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1                   850                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2                   841                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3                   797                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu4                   822                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu5                   866                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu6                   868                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu7                   801                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 6656                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0               1904                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1               1786                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2               1883                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3               1815                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4               1890                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5               1852                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6               1884                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7               1828                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             14842                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0                4339                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1                4322                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2                4349                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3                4270                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4                4225                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5                4246                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6                4116                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7                4276                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              34143                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0                   5150                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1                   5172                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2                   5190                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3                   5067                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu4                   5047                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu5                   5112                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu6                   4984                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu7                   5077                       # number of demand (read+write) misses
system.l2c.demand_misses::total                 40799                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0                  5150                       # number of overall misses
system.l2c.overall_misses::cpu1                  5172                       # number of overall misses
system.l2c.overall_misses::cpu2                  5190                       # number of overall misses
system.l2c.overall_misses::cpu3                  5067                       # number of overall misses
system.l2c.overall_misses::cpu4                  5047                       # number of overall misses
system.l2c.overall_misses::cpu5                  5112                       # number of overall misses
system.l2c.overall_misses::cpu6                  4984                       # number of overall misses
system.l2c.overall_misses::cpu7                  5077                       # number of overall misses
system.l2c.overall_misses::total                40799                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0        67585481                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1        72673967                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2        72507473                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3        67900486                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu4        70984967                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu5        72621982                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu6        74019971                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu7        71889473                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      570183800                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0     54932462                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1     51505961                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2     54811454                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3     53694953                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4     54685961                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5     53053446                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6     55065452                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7     53902466                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    431652155                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0     247942331                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1     244706822                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2     247942337                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3     243863836                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4     241149827                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5     241354363                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6     234845330                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7     242655342                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1944460188                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0        315527812                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1        317380789                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2        320449810                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3        311764322                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4        312134794                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5        313976345                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6        308865301                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7        314544815                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      2514643988                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0       315527812                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1       317380789                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2       320449810                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3       311764322                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4       312134794                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5       313976345                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6       308865301                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7       314544815                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     2514643988                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0               11826                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1               11622                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2               11810                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3               11476                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu4               11708                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu5               11816                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu6               11805                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu7               11792                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              93855                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks        77421                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total            77421                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0             2247                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1             2119                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2             2235                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3             2185                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4             2252                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5             2188                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6             2275                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7             2226                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           17727                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0              6435                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1              6412                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2              6366                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3              6389                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4              6253                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5              6308                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6              6228                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7              6331                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            50722                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0                18261                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1                18034                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2                18176                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3                17865                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4                17961                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5                18124                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6                18033                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7                18123                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              144577                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0               18261                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1               18034                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2               18176                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3               17865                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4               17961                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5               18124                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6               18033                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7               18123                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             144577                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0           0.068578                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1           0.073137                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2           0.071211                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3           0.069449                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu4           0.070208                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu5           0.073290                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu6           0.073528                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu7           0.067927                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.070918                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0        0.847352                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1        0.842850                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2        0.842506                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3        0.830664                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4        0.839254                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5        0.846435                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6        0.828132                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7        0.821204                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.837254                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0         0.674281                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1         0.674049                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2         0.683161                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3         0.668336                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4         0.675676                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5         0.673114                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6         0.660886                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7         0.675407                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.673140                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0            0.282022                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1            0.286792                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2            0.285541                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3            0.283627                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4            0.280998                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5            0.282057                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6            0.276382                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7            0.280141                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.282196                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0           0.282022                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1           0.286792                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2           0.285541                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3           0.283627                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4           0.280998                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5           0.282057                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6           0.276382                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7           0.280141                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.282196                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0 83335.981504                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1 85498.784706                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2 86215.782402                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3 85195.089084                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu4 86356.407543                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu5 83859.101617                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu6 85276.464286                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu7 89749.654182                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 85664.633413                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0 28851.082983                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 28838.723964                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 29108.578864                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 29583.996143                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 28934.370899                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 28646.569114                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 29227.946921                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 29487.125821                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 29083.152877                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 57142.735884                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 56618.885238                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 57011.344447                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 57110.968618                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 57076.882130                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 56842.760951                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 57056.688533                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 56748.209074                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 56950.478517                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 61267.536311                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 61365.195089                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 61743.701349                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 61528.384054                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 61845.610065                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 61419.472809                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 61971.368579                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 61954.858184                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 61634.941739                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 61267.536311                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 61365.195089                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 61743.701349                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 61528.384054                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 61845.610065                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 61419.472809                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 61971.368579                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 61954.858184                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 61634.941739                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs               618                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                       94                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      6.574468                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks                7498                       # number of writebacks
system.l2c.writebacks::total                     7498                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0                  7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1                  7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2                 10                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3                  9                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu4                  7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu5                 10                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu6                 11                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu7                  3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                64                       # number of ReadReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu0               2                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu4               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::total              3                       # number of UpgradeReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu0                5                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu1                4                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu2                9                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu3                5                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu4                3                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5                4                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu7                4                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total              34                       # number of ReadExReq MSHR hits
system.l2c.demand_mshr_hits::cpu0                  12                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1                  11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2                  19                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3                  14                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4                  10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5                  14                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6                  11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7                   7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 98                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0                 12                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1                 11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2                 19                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3                 14                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4                 10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5                 14                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6                 11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7                  7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                98                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0              804                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1              843                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2              831                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3              788                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu4              815                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu5              856                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu6              857                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu7              798                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            6592                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0          1902                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1          1786                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2          1883                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3          1815                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4          1889                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5          1852                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6          1884                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7          1828                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        14839                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0           4334                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1           4318                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2           4340                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3           4265                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4           4222                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5           4242                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6           4116                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7           4272                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         34109                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0              5138                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1              5161                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2              5171                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3              5053                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4              5037                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5              5098                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6              4973                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7              5070                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            40701                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0             5138                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1             5161                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2             5171                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3             5053                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4             5037                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5             5098                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6             4973                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7             5070                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           40701                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0     57455481                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1     61467468                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2     61812473                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3     57960486                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu4     60571467                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu5     61211482                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu6     62615971                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu7     61885973                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    484980801                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0     78471422                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1     73680432                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2     77692433                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3     74790419                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4     77910437                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5     76253912                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6     77720922                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7     75415430                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    611935407                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0    195176331                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1    192089822                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2    194667337                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3    191905836                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4    189907827                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5    189746863                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6    184982830                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7    190582842                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1529059688                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0    252631812                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1    253557290                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2    256479810                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3    249866322                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4    250479294                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5    250958345                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6    247598801                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7    252468815                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   2014040489                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0    252631812                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1    253557290                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2    256479810                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3    249866322                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4    250479294                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5    250958345                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6    247598801                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7    252468815                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   2014040489                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    426624598                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    414248119                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    417125081                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    415481622                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    425535608                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    422832619                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    413879620                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    421948093                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   3357675360                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    234914484                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    229533990                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    238126486                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    230756493                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    230060497                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    233129489                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    235046492                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    235339481                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1866907412                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0    661539082                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1    643782109                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2    655251567                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3    646238115                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4    655596105                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5    655962108                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6    648926112                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7    657287574                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   5224582772                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0      0.067986                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1      0.072535                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2      0.070364                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3      0.068665                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu4      0.069611                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu5      0.072444                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu6      0.072596                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu7      0.067673                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.070236                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.846462                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.842850                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.842506                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.830664                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.838810                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.846435                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.828132                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.821204                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.837085                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.673504                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.673425                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.681747                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.667554                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.675196                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.672479                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.660886                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.674775                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.672470                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0       0.281365                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1       0.286182                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2       0.284496                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3       0.282844                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4       0.280441                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5       0.281284                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6       0.275772                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7       0.279755                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.281518                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0      0.281365                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1      0.286182                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2      0.284496                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3      0.282844                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4      0.280441                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5      0.281284                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6      0.275772                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7      0.279755                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.281518                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 71462.041045                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 72915.145907                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 74383.240674                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 73553.916244                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 74320.818405                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 71508.740654                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 73064.143524                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 77551.344612                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 73571.116657                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41257.319664                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41254.441209                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41259.921933                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41206.842424                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41244.275807                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41173.818575                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41253.143312                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41255.705689                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41238.318418                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 45033.763498                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 44485.831867                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44854.225115                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44995.506682                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44980.536949                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44730.519331                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44942.378523                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44612.088483                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 44828.628456                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 49169.289996                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 49129.488471                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 49599.653839                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 49449.103899                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 49727.872543                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 49226.823264                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 49788.618741                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 49796.610454                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 49483.808481                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 49169.289996                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 49129.488471                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 49599.653839                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 49449.103899                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 49727.872543                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 49226.823264                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 49788.618741                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 49796.610454                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 49483.808481                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cpu0.num_reads                           99935                       # number of read accesses completed
system.cpu0.num_writes                          53927                       # number of write accesses completed
system.cpu0.num_copies                              0                       # number of copy accesses completed
system.cpu0.l1c.replacements                    22552                       # number of replacements
system.cpu0.l1c.tagsinuse                  390.299440                       # Cycle average of tags in use
system.cpu0.l1c.total_refs                      13259                       # Total number of references to valid blocks.
system.cpu0.l1c.sampled_refs                    22978                       # Sample count of references to valid blocks.
system.cpu0.l1c.avg_refs                     0.577030                       # Average number of references to valid blocks.
system.cpu0.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu0.l1c.occ_blocks::cpu0           390.299440                       # Average occupied blocks per requestor
system.cpu0.l1c.occ_percent::cpu0            0.762304                       # Average percentage of cache occupancy
system.cpu0.l1c.occ_percent::total           0.762304                       # Average percentage of cache occupancy
system.cpu0.l1c.ReadReq_hits::cpu0               8650                       # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total              8650                       # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0              1121                       # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total             1121                       # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0                9771                       # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total               9771                       # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0               9771                       # number of overall hits
system.cpu0.l1c.overall_hits::total              9771                       # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0            36111                       # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total           36111                       # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0           23070                       # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total          23070                       # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0             59181                       # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total            59181                       # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0            59181                       # number of overall misses
system.cpu0.l1c.overall_misses::total           59181                       # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0   4619304150                       # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total   4619304150                       # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0   3123415012                       # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total   3123415012                       # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0   7742719162                       # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total   7742719162                       # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0   7742719162                       # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total   7742719162                       # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0          44761                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total         44761                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0         24191                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total        24191                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0           68952                       # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total          68952                       # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0          68952                       # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total         68952                       # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.806751                       # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total     0.806751                       # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.953660                       # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total     0.953660                       # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0       0.858293                       # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total      0.858293                       # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0      0.858293                       # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total     0.858293                       # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 127919.585445                       # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 127919.585445                       # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 135388.600433                       # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 135388.600433                       # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 130831.164766                       # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 130831.164766                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 130831.164766                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 130831.164766                       # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs      1413270                       # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_mshrs               64534                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_mshrs    21.899619                       # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu0.l1c.writebacks::writebacks           9856                       # number of writebacks
system.cpu0.l1c.writebacks::total                9856                       # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36111                       # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total        36111                       # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23070                       # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total        23070                       # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0        59181                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total        59181                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0        59181                       # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total        59181                       # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0   4547088150                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total   4547088150                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0   3077287012                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total   3077287012                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0   7624375162                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total   7624375162                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0   7624375162                       # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total   7624375162                       # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0   1436864073                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total   1436864073                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0    955697316                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total    955697316                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   2392561389                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total   2392561389                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.806751                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.806751                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.953660                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.953660                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.858293                       # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total     0.858293                       # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.858293                       # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total     0.858293                       # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 125919.751599                       # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 125919.751599                       # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 133389.120590                       # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 133389.120590                       # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 128831.468917                       # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 128831.468917                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 128831.468917                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 128831.468917                       # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0          inf                       # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu1.num_reads                           97805                       # number of read accesses completed
system.cpu1.num_writes                          52541                       # number of write accesses completed
system.cpu1.num_copies                              0                       # number of copy accesses completed
system.cpu1.l1c.replacements                    21861                       # number of replacements
system.cpu1.l1c.tagsinuse                  389.546383                       # Cycle average of tags in use
system.cpu1.l1c.total_refs                      12913                       # Total number of references to valid blocks.
system.cpu1.l1c.sampled_refs                    22254                       # Sample count of references to valid blocks.
system.cpu1.l1c.avg_refs                     0.580255                       # Average number of references to valid blocks.
system.cpu1.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu1.l1c.occ_blocks::cpu1           389.546383                       # Average occupied blocks per requestor
system.cpu1.l1c.occ_percent::cpu1            0.760833                       # Average percentage of cache occupancy
system.cpu1.l1c.occ_percent::total           0.760833                       # Average percentage of cache occupancy
system.cpu1.l1c.ReadReq_hits::cpu1               8526                       # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total              8526                       # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1              1045                       # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total             1045                       # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1                9571                       # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total               9571                       # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1               9571                       # number of overall hits
system.cpu1.l1c.overall_hits::total              9571                       # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1            35398                       # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total           35398                       # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1           22650                       # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total          22650                       # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1             58048                       # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total            58048                       # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1            58048                       # number of overall misses
system.cpu1.l1c.overall_misses::total           58048                       # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1   4577570179                       # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total   4577570179                       # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1   3175338798                       # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total   3175338798                       # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1   7752908977                       # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total   7752908977                       # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1   7752908977                       # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total   7752908977                       # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1          43924                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total         43924                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1         23695                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total        23695                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1           67619                       # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total          67619                       # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1          67619                       # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total         67619                       # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.805892                       # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total     0.805892                       # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.955898                       # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total     0.955898                       # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1       0.858457                       # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total      0.858457                       # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1      0.858457                       # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total     0.858457                       # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 129317.198119                       # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 129317.198119                       # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 140191.558411                       # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 140191.558411                       # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 133560.311759                       # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 133560.311759                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 133560.311759                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 133560.311759                       # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs      1404233                       # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_mshrs               62944                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_mshrs    22.309243                       # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu1.l1c.writebacks::writebacks           9603                       # number of writebacks
system.cpu1.l1c.writebacks::total                9603                       # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1        35398                       # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total        35398                       # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1        22650                       # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total        22650                       # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1        58048                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total        58048                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1        58048                       # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total        58048                       # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1   4506790179                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total   4506790179                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1   3130040798                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total   3130040798                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1   7636830977                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total   7636830977                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1   7636830977                       # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total   7636830977                       # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1   1394209419                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total   1394209419                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1    928511940                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total    928511940                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   2322721359                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total   2322721359                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.805892                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.805892                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.955898                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.955898                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.858457                       # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total     0.858457                       # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.858457                       # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total     0.858457                       # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 127317.650121                       # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 127317.650121                       # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 138191.646711                       # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 138191.646711                       # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 131560.621847                       # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 131560.621847                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 131560.621847                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 131560.621847                       # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1          inf                       # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu2.num_reads                          100000                       # number of read accesses completed
system.cpu2.num_writes                          54114                       # number of write accesses completed
system.cpu2.num_copies                              0                       # number of copy accesses completed
system.cpu2.l1c.replacements                    22990                       # number of replacements
system.cpu2.l1c.tagsinuse                  392.060782                       # Cycle average of tags in use
system.cpu2.l1c.total_refs                      13456                       # Total number of references to valid blocks.
system.cpu2.l1c.sampled_refs                    23401                       # Sample count of references to valid blocks.
system.cpu2.l1c.avg_refs                     0.575018                       # Average number of references to valid blocks.
system.cpu2.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu2.l1c.occ_blocks::cpu2           392.060782                       # Average occupied blocks per requestor
system.cpu2.l1c.occ_percent::cpu2            0.765744                       # Average percentage of cache occupancy
system.cpu2.l1c.occ_percent::total           0.765744                       # Average percentage of cache occupancy
system.cpu2.l1c.ReadReq_hits::cpu2               8750                       # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total              8750                       # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2              1243                       # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total             1243                       # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2                9993                       # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total               9993                       # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2               9993                       # number of overall hits
system.cpu2.l1c.overall_hits::total              9993                       # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2            36203                       # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total           36203                       # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2           23173                       # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total          23173                       # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2             59376                       # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total            59376                       # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2            59376                       # number of overall misses
system.cpu2.l1c.overall_misses::total           59376                       # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2   4641358719                       # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total   4641358719                       # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2   3127191782                       # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total   3127191782                       # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2   7768550501                       # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total   7768550501                       # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2   7768550501                       # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total   7768550501                       # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2          44953                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total         44953                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2         24416                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total        24416                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2           69369                       # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total          69369                       # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2          69369                       # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total         69369                       # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.805352                       # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total     0.805352                       # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.949091                       # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total     0.949091                       # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2       0.855944                       # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total      0.855944                       # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2      0.855944                       # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total     0.855944                       # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 128203.704638                       # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 128203.704638                       # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 134949.802874                       # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 134949.802874                       # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 130836.541717                       # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 130836.541717                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 130836.541717                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 130836.541717                       # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs      1392289                       # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_mshrs               64514                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_mshrs    21.581192                       # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu2.l1c.writebacks::writebacks           9991                       # number of writebacks
system.cpu2.l1c.writebacks::total                9991                       # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36203                       # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total        36203                       # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2        23173                       # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total        23173                       # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2        59376                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total        59376                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2        59376                       # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total        59376                       # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2   4568956719                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total   4568956719                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2   3080855782                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total   3080855782                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2   7649812501                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total   7649812501                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2   7649812501                       # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total   7649812501                       # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2   1362583834                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total   1362583834                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2    971805765                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total    971805765                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   2334389599                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total   2334389599                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.805352                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.805352                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.949091                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.949091                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.855944                       # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total     0.855944                       # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.855944                       # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total     0.855944                       # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 126203.815126                       # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 126203.815126                       # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 132950.234411                       # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 132950.234411                       # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 128836.777503                       # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 128836.777503                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 128836.777503                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 128836.777503                       # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2          inf                       # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu3.num_reads                           98308                       # number of read accesses completed
system.cpu3.num_writes                          52892                       # number of write accesses completed
system.cpu3.num_copies                              0                       # number of copy accesses completed
system.cpu3.l1c.replacements                    21879                       # number of replacements
system.cpu3.l1c.tagsinuse                  388.243829                       # Cycle average of tags in use
system.cpu3.l1c.total_refs                      13269                       # Total number of references to valid blocks.
system.cpu3.l1c.sampled_refs                    22290                       # Sample count of references to valid blocks.
system.cpu3.l1c.avg_refs                     0.595289                       # Average number of references to valid blocks.
system.cpu3.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu3.l1c.occ_blocks::cpu3           388.243829                       # Average occupied blocks per requestor
system.cpu3.l1c.occ_percent::cpu3            0.758289                       # Average percentage of cache occupancy
system.cpu3.l1c.occ_percent::total           0.758289                       # Average percentage of cache occupancy
system.cpu3.l1c.ReadReq_hits::cpu3               8771                       # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total              8771                       # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3              1066                       # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total             1066                       # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3                9837                       # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total               9837                       # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3               9837                       # number of overall hits
system.cpu3.l1c.overall_hits::total              9837                       # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3            35672                       # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total           35672                       # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3           22858                       # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total          22858                       # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3             58530                       # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total            58530                       # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3            58530                       # number of overall misses
system.cpu3.l1c.overall_misses::total           58530                       # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3   4705192371                       # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total   4705192371                       # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3   3092503889                       # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total   3092503889                       # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3   7797696260                       # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total   7797696260                       # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3   7797696260                       # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total   7797696260                       # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3          44443                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total         44443                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3         23924                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total        23924                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3           68367                       # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total          68367                       # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3          68367                       # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total         68367                       # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.802646                       # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total     0.802646                       # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.955442                       # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total     0.955442                       # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3       0.856115                       # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total      0.856115                       # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3      0.856115                       # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total     0.856115                       # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 131901.557832                       # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 131901.557832                       # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 135291.971695                       # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 135291.971695                       # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 133225.632325                       # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 133225.632325                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 133225.632325                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 133225.632325                       # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs      1411864                       # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_mshrs               63831                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_mshrs    22.118782                       # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu3.l1c.writebacks::writebacks           9578                       # number of writebacks
system.cpu3.l1c.writebacks::total                9578                       # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3        35672                       # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total        35672                       # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3        22858                       # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total        22858                       # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3        58530                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total        58530                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3        58530                       # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total        58530                       # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3   4633860371                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total   4633860371                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3   3046797889                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total   3046797889                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3   7680658260                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total   7680658260                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3   7680658260                       # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total   7680658260                       # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3   1383140389                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total   1383140389                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3    919277948                       # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total    919277948                       # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   2302418337                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total   2302418337                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.802646                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.802646                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.955442                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.955442                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.856115                       # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total     0.856115                       # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.856115                       # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total     0.856115                       # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 129901.894231                       # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 129901.894231                       # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 133292.409178                       # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 133292.409178                       # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 131226.008201                       # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 131226.008201                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 131226.008201                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 131226.008201                       # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average WriteReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3          inf                       # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu4.num_reads                           99646                       # number of read accesses completed
system.cpu4.num_writes                          53184                       # number of write accesses completed
system.cpu4.num_copies                              0                       # number of copy accesses completed
system.cpu4.l1c.replacements                    22486                       # number of replacements
system.cpu4.l1c.tagsinuse                  389.564427                       # Cycle average of tags in use
system.cpu4.l1c.total_refs                      13323                       # Total number of references to valid blocks.
system.cpu4.l1c.sampled_refs                    22871                       # Sample count of references to valid blocks.
system.cpu4.l1c.avg_refs                     0.582528                       # Average number of references to valid blocks.
system.cpu4.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu4.l1c.occ_blocks::cpu4           389.564427                       # Average occupied blocks per requestor
system.cpu4.l1c.occ_percent::cpu4            0.760868                       # Average percentage of cache occupancy
system.cpu4.l1c.occ_percent::total           0.760868                       # Average percentage of cache occupancy
system.cpu4.l1c.ReadReq_hits::cpu4               8662                       # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total              8662                       # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4              1144                       # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total             1144                       # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4                9806                       # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total               9806                       # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4               9806                       # number of overall hits
system.cpu4.l1c.overall_hits::total              9806                       # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4            36129                       # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total           36129                       # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4           22914                       # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total          22914                       # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4             59043                       # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total            59043                       # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4            59043                       # number of overall misses
system.cpu4.l1c.overall_misses::total           59043                       # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4   4597368029                       # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total   4597368029                       # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4   3131496490                       # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total   3131496490                       # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4   7728864519                       # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total   7728864519                       # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4   7728864519                       # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total   7728864519                       # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4          44791                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total         44791                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4         24058                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total        24058                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4           68849                       # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total          68849                       # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4          68849                       # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total         68849                       # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.806613                       # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total     0.806613                       # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.952448                       # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total     0.952448                       # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4       0.857572                       # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total      0.857572                       # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4      0.857572                       # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total     0.857572                       # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 127248.692989                       # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 127248.692989                       # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 136663.022170                       # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 136663.022170                       # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 130902.300340                       # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 130902.300340                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 130902.300340                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 130902.300340                       # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs      1409065                       # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_mshrs               64552                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_mshrs    21.828371                       # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu4.l1c.writebacks::writebacks           9768                       # number of writebacks
system.cpu4.l1c.writebacks::total                9768                       # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36129                       # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total        36129                       # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4        22914                       # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total        22914                       # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4        59043                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total        59043                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4        59043                       # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total        59043                       # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4   4525124029                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total   4525124029                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4   3085672490                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total   3085672490                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4   7610796519                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total   7610796519                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4   7610796519                       # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total   7610796519                       # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4   1426221714                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total   1426221714                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4    886330386                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total    886330386                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   2312552100                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total   2312552100                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.806613                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.806613                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.952448                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.952448                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.857572                       # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total     0.857572                       # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.857572                       # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total     0.857572                       # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 125249.080489                       # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 125249.080489                       # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 134663.196736                       # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 134663.196736                       # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 128902.605203                       # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 128902.605203                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 128902.605203                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 128902.605203                       # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4          inf                       # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu5.num_reads                           99510                       # number of read accesses completed
system.cpu5.num_writes                          53712                       # number of write accesses completed
system.cpu5.num_copies                              0                       # number of copy accesses completed
system.cpu5.l1c.replacements                    22704                       # number of replacements
system.cpu5.l1c.tagsinuse                  391.715809                       # Cycle average of tags in use
system.cpu5.l1c.total_refs                      13238                       # Total number of references to valid blocks.
system.cpu5.l1c.sampled_refs                    23109                       # Sample count of references to valid blocks.
system.cpu5.l1c.avg_refs                     0.572850                       # Average number of references to valid blocks.
system.cpu5.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu5.l1c.occ_blocks::cpu5           391.715809                       # Average occupied blocks per requestor
system.cpu5.l1c.occ_percent::cpu5            0.765070                       # Average percentage of cache occupancy
system.cpu5.l1c.occ_percent::total           0.765070                       # Average percentage of cache occupancy
system.cpu5.l1c.ReadReq_hits::cpu5               8676                       # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total              8676                       # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5              1153                       # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total             1153                       # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5                9829                       # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total               9829                       # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5               9829                       # number of overall hits
system.cpu5.l1c.overall_hits::total              9829                       # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5            36073                       # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total           36073                       # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5           23060                       # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total          23060                       # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5             59133                       # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total            59133                       # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5            59133                       # number of overall misses
system.cpu5.l1c.overall_misses::total           59133                       # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5   4612203646                       # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total   4612203646                       # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5   3154708419                       # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total   3154708419                       # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5   7766912065                       # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total   7766912065                       # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5   7766912065                       # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total   7766912065                       # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5          44749                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total         44749                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5         24213                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total        24213                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5           68962                       # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total          68962                       # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5          68962                       # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total         68962                       # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.806119                       # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total     0.806119                       # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.952381                       # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total     0.952381                       # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5       0.857472                       # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total      0.857472                       # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5      0.857472                       # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total     0.857472                       # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 127857.501344                       # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 127857.501344                       # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 136804.354683                       # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 136804.354683                       # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 131346.491215                       # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 131346.491215                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 131346.491215                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 131346.491215                       # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs      1402922                       # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_mshrs               64326                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_mshrs    21.809564                       # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu5.l1c.writebacks::writebacks           9873                       # number of writebacks
system.cpu5.l1c.writebacks::total                9873                       # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36073                       # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total        36073                       # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23060                       # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total        23060                       # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5        59133                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total        59133                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5        59133                       # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total        59133                       # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5   4540061646                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total   4540061646                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5   3108604419                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total   3108604419                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5   7648666065                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total   7648666065                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5   7648666065                       # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total   7648666065                       # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5   1397826307                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total   1397826307                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5    952355893                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total    952355893                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   2350182200                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total   2350182200                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.806119                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.806119                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.952381                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.952381                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.857472                       # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total     0.857472                       # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.857472                       # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total     0.857472                       # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 125857.612231                       # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 125857.612231                       # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 134805.048526                       # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 134805.048526                       # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 129346.829435                       # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 129346.829435                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 129346.829435                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 129346.829435                       # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5          inf                       # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu6.num_reads                           99341                       # number of read accesses completed
system.cpu6.num_writes                          53460                       # number of write accesses completed
system.cpu6.num_copies                              0                       # number of copy accesses completed
system.cpu6.l1c.replacements                    22728                       # number of replacements
system.cpu6.l1c.tagsinuse                  391.033952                       # Cycle average of tags in use
system.cpu6.l1c.total_refs                      13418                       # Total number of references to valid blocks.
system.cpu6.l1c.sampled_refs                    23126                       # Sample count of references to valid blocks.
system.cpu6.l1c.avg_refs                     0.580213                       # Average number of references to valid blocks.
system.cpu6.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu6.l1c.occ_blocks::cpu6           391.033952                       # Average occupied blocks per requestor
system.cpu6.l1c.occ_percent::cpu6            0.763738                       # Average percentage of cache occupancy
system.cpu6.l1c.occ_percent::total           0.763738                       # Average percentage of cache occupancy
system.cpu6.l1c.ReadReq_hits::cpu6               8762                       # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total              8762                       # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6              1095                       # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total             1095                       # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6                9857                       # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total               9857                       # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6               9857                       # number of overall hits
system.cpu6.l1c.overall_hits::total              9857                       # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6            35979                       # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total           35979                       # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6           23081                       # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total          23081                       # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6             59060                       # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total            59060                       # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6            59060                       # number of overall misses
system.cpu6.l1c.overall_misses::total           59060                       # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6   4670056241                       # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total   4670056241                       # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6   3140122564                       # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total   3140122564                       # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6   7810178805                       # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total   7810178805                       # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6   7810178805                       # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total   7810178805                       # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6          44741                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total         44741                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6         24176                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total        24176                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6           68917                       # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total          68917                       # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6          68917                       # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total         68917                       # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.804162                       # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total     0.804162                       # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.954707                       # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total     0.954707                       # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6       0.856973                       # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total      0.856973                       # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6      0.856973                       # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total     0.856973                       # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 129799.500848                       # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 129799.500848                       # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 136047.942637                       # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 136047.942637                       # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 132241.429140                       # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 132241.429140                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 132241.429140                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 132241.429140                       # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs      1402385                       # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_mshrs               64109                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_mshrs    21.875010                       # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu6.l1c.writebacks::writebacks           9866                       # number of writebacks
system.cpu6.l1c.writebacks::total                9866                       # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6        35979                       # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total        35979                       # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23081                       # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total        23081                       # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6        59060                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total        59060                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6        59060                       # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total        59060                       # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6   4598108241                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total   4598108241                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6   3093974564                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total   3093974564                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6   7692082805                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total   7692082805                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6   7692082805                       # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total   7692082805                       # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6   1335573448                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total   1335573448                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6    977750934                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total    977750934                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   2313324382                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total   2313324382                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.804162                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.804162                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.954707                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.954707                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.856973                       # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total     0.856973                       # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.856973                       # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total     0.856973                       # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 127799.778788                       # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 127799.778788                       # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 134048.549196                       # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 134048.549196                       # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 130241.835506                       # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 130241.835506                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 130241.835506                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 130241.835506                       # average overall mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6          inf                       # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu7.num_reads                           99191                       # number of read accesses completed
system.cpu7.num_writes                          53936                       # number of write accesses completed
system.cpu7.num_copies                              0                       # number of copy accesses completed
system.cpu7.l1c.replacements                    22510                       # number of replacements
system.cpu7.l1c.tagsinuse                  390.052988                       # Cycle average of tags in use
system.cpu7.l1c.total_refs                      13451                       # Total number of references to valid blocks.
system.cpu7.l1c.sampled_refs                    22924                       # Sample count of references to valid blocks.
system.cpu7.l1c.avg_refs                     0.586765                       # Average number of references to valid blocks.
system.cpu7.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu7.l1c.occ_blocks::cpu7           390.052988                       # Average occupied blocks per requestor
system.cpu7.l1c.occ_percent::cpu7            0.761822                       # Average percentage of cache occupancy
system.cpu7.l1c.occ_percent::total           0.761822                       # Average percentage of cache occupancy
system.cpu7.l1c.ReadReq_hits::cpu7               8796                       # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total              8796                       # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7              1169                       # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total             1169                       # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7                9965                       # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total               9965                       # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7               9965                       # number of overall hits
system.cpu7.l1c.overall_hits::total              9965                       # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7            35920                       # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total           35920                       # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7           23167                       # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total          23167                       # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7             59087                       # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total            59087                       # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7            59087                       # number of overall misses
system.cpu7.l1c.overall_misses::total           59087                       # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7   4583534857                       # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total   4583534857                       # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7   3157115869                       # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total   3157115869                       # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7   7740650726                       # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total   7740650726                       # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7   7740650726                       # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total   7740650726                       # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7          44716                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total         44716                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7         24336                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total        24336                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7           69052                       # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total          69052                       # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7          69052                       # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total         69052                       # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.803292                       # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total     0.803292                       # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.951964                       # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total     0.951964                       # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7       0.855688                       # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total      0.855688                       # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7      0.855688                       # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total     0.855688                       # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 127603.977088                       # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 127603.977088                       # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 136276.422023                       # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 136276.422023                       # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 131004.294109                       # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 131004.294109                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 131004.294109                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 131004.294109                       # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs      1403287                       # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_mshrs               64246                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_mshrs    21.842403                       # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu7.l1c.writebacks::writebacks           9883                       # number of writebacks
system.cpu7.l1c.writebacks::total                9883                       # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7        35920                       # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total        35920                       # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23167                       # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total        23167                       # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7        59087                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total        59087                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7        59087                       # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total        59087                       # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7   4511708857                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total   4511708857                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7   3110789869                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total   3110789869                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7   7622498726                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total   7622498726                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7   7622498726                       # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total   7622498726                       # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7   1423430289                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total   1423430289                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7    942416285                       # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total    942416285                       # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   2365846574                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total   2365846574                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.803292                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.803292                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.951964                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.951964                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.855688                       # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total     0.855688                       # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.855688                       # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total     0.855688                       # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 125604.366843                       # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 125604.366843                       # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 134276.767341                       # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 134276.767341                       # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 129004.666441                       # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 129004.666441                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 129004.666441                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 129004.666441                       # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average WriteReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------