path: root/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000224                       # Number of seconds simulated
sim_ticks                                   223713460                       # Number of ticks simulated
final_tick                                  223713460                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_tick_rate                                1721618                       # Simulator tick rate (ticks/s)
host_mem_usage                                 347508                       # Number of bytes of host memory used
host_seconds                                   129.94                       # Real time elapsed on the host
system.physmem.bytes_read::cpu0                 81065                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1                 82807                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2                 84800                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3                 80115                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu4                 83878                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu5                 83050                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu6                 84723                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu7                 83101                       # Number of bytes read from this memory
system.physmem.bytes_read::total               663539                       # Number of bytes read from this memory
system.physmem.bytes_written::writebacks       423360                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0               5290                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1               5393                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu2               5404                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu3               5324                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu4               5344                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu5               5398                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu6               5445                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu7               5412                       # Number of bytes written to this memory
system.physmem.bytes_written::total            466370                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0                  11135                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1                  11050                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2                  11090                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3                  11067                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4                  11176                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5                  11041                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6                  11139                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7                  11029                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 88727                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks            6615                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0                  5290                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1                  5393                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2                  5404                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3                  5324                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4                  5344                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5                  5398                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6                  5445                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7                  5412                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                49625                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0                362360852                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1                370147599                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2                379056316                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3                358114349                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4                374934973                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5                371233810                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6                378712126                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7                371461780                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              2966021803                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks        1892420778                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0                23646320                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1                24106730                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2                24155900                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3                23798300                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4                23887700                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5                24129080                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6                24339170                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7                24191660                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total             2084675638                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks        1892420778                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0               386007172                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1               394254329                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2               403212216                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3               381912648                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4               398822673                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5               395362890                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6               403051296                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7               395653440                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             5050697441                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                         13635                       # number of replacements
system.l2c.tagsinuse                       790.382632                       # Cycle average of tags in use
system.l2c.total_refs                          148986                       # Total number of references to valid blocks.
system.l2c.sampled_refs                         14447                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         10.312591                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks          735.582494                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0                  6.455373                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1                  6.652747                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2                  6.865494                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3                  6.639169                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu4                  7.152690                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu5                  7.266868                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu6                  7.044725                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu7                  6.723074                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.718342                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0                 0.006304                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1                 0.006497                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2                 0.006705                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3                 0.006484                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu4                 0.006985                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu5                 0.007097                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu6                 0.006880                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu7                 0.006566                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.771858                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0                   10736                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1                   10614                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2                   10598                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3                   10656                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu4                   10639                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu5                   10502                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu6                   10784                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu7                   10768                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  85297                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks           74602                       # number of Writeback hits
system.l2c.Writeback_hits::total                74602                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0                  364                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1                  332                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2                  337                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3                  343                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4                  366                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5                  372                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6                  359                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7                  320                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                2793                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0                  1921                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1                  1802                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2                  1826                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3                  1918                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4                  1884                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5                  1935                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6                  1883                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7                  1847                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                15016                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0                    12657                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1                    12416                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2                    12424                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3                    12574                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu4                    12523                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu5                    12437                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu6                    12667                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu7                    12615                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  100313                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0                   12657                       # number of overall hits
system.l2c.overall_hits::cpu1                   12416                       # number of overall hits
system.l2c.overall_hits::cpu2                   12424                       # number of overall hits
system.l2c.overall_hits::cpu3                   12574                       # number of overall hits
system.l2c.overall_hits::cpu4                   12523                       # number of overall hits
system.l2c.overall_hits::cpu5                   12437                       # number of overall hits
system.l2c.overall_hits::cpu6                   12667                       # number of overall hits
system.l2c.overall_hits::cpu7                   12615                       # number of overall hits
system.l2c.overall_hits::total                 100313                       # number of overall hits
system.l2c.ReadReq_misses::cpu0                   732                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1                   746                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2                   787                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3                   736                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu4                   779                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu5                   768                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu6                   802                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu7                   756                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 6106                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0               1954                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1               1934                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2               2007                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3               1961                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4               1921                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5               2008                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6               1917                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7               1898                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             15600                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0                4348                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1                4389                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2                4257                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3                4320                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4                4350                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5                4337                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6                4234                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7                4290                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              34525                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0                   5080                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1                   5135                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2                   5044                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3                   5056                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu4                   5129                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu5                   5105                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu6                   5036                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu7                   5046                       # number of demand (read+write) misses
system.l2c.demand_misses::total                 40631                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0                  5080                       # number of overall misses
system.l2c.overall_misses::cpu1                  5135                       # number of overall misses
system.l2c.overall_misses::cpu2                  5044                       # number of overall misses
system.l2c.overall_misses::cpu3                  5056                       # number of overall misses
system.l2c.overall_misses::cpu4                  5129                       # number of overall misses
system.l2c.overall_misses::cpu5                  5105                       # number of overall misses
system.l2c.overall_misses::cpu6                  5036                       # number of overall misses
system.l2c.overall_misses::cpu7                  5046                       # number of overall misses
system.l2c.overall_misses::total                40631                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0        36182301                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1        37095182                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2        38839912                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3        36320452                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu4        38654457                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu5        37981477                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu6        39913673                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu7        37420167                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      302407621                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0     51570624                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1     52824724                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2     55089368                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3     54044648                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4     51434616                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5     55447032                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6     51075446                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7     51050152                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    422536610                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0     217343370                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1     219324999                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2     212745239                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3     215838098                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4     217293309                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5     216702467                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6     211504918                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7     214216755                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1724969155                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0        253525671                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1        256420181                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2        251585151                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3        252158550                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4        255947766                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5        254683944                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6        251418591                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7        251636922                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      2027376776                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0       253525671                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1       256420181                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2       251585151                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3       252158550                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4       255947766                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5       254683944                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6       251418591                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7       251636922                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     2027376776                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0               11468                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1               11360                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2               11385                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3               11392                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu4               11418                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu5               11270                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu6               11586                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu7               11524                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              91403                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks        74602                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total            74602                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0             2318                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1             2266                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2             2344                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3             2304                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4             2287                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5             2380                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6             2276                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7             2218                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           18393                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0              6269                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1              6191                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2              6083                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3              6238                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4              6234                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5              6272                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6              6117                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7              6137                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            49541                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0                17737                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1                17551                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2                17468                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3                17630                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4                17652                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5                17542                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6                17703                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7                17661                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              140944                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0               17737                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1               17551                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2               17468                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3               17630                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4               17652                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5               17542                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6               17703                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7               17661                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             140944                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0           0.063830                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1           0.065669                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2           0.069126                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3           0.064607                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu4           0.068226                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu5           0.068146                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu6           0.069221                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu7           0.065602                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.066803                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0        0.842968                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1        0.853486                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2        0.856229                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3        0.851128                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4        0.839965                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5        0.843697                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6        0.842267                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7        0.855726                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.848149                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0         0.693572                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1         0.708932                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2         0.699819                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3         0.692530                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4         0.697786                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5         0.691486                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6         0.692169                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7         0.699039                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.696898                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0            0.286407                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1            0.292576                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2            0.288757                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3            0.286784                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4            0.290562                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5            0.291016                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6            0.284472                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7            0.285714                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.288278                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0           0.286407                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1           0.292576                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2           0.288757                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3           0.286784                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4           0.290562                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5           0.291016                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6           0.284472                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7           0.285714                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.288278                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0 49429.372951                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1 49725.445040                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2 49351.857687                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3 49348.440217                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu4 49620.612323                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu5 49455.048177                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu6 49767.672070                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu7 49497.575397                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 49526.305437                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0 26392.335722                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 27313.714581                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 27448.613852                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 27559.738909                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 26774.917231                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 27613.063745                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 26643.425143                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 26896.813488                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 27085.680128                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 49986.975621                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 49971.519481                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 49975.390886                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 49962.522685                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 49952.484828                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 49965.982707                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 49953.924894                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 49933.975524                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 49962.900941                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 49906.628150                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 49935.770399                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 49878.102895                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 49873.130934                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 49902.079548                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 49889.117336                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 49924.263503                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 49868.593341                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 49897.289656                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 49906.628150                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 49935.770399                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 49878.102895                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 49873.130934                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 49902.079548                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 49889.117336                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 49924.263503                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 49868.593341                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 49897.289656                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs             96627                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                       19                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs   5085.631579                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks                6616                       # number of writebacks
system.l2c.writebacks::total                     6616                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0                 18                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1                 10                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2                 24                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3                 23                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu4                 22                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu5                 19                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu6                 17                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu7                 24                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total               157                       # number of ReadReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu0               2                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu1               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu2               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu3               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu4               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu5               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu6               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu7               4                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::total             12                       # number of UpgradeReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu0                6                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu1               13                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu2                9                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu3                9                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu4               12                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5               11                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu6               10                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu7               15                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total              85                       # number of ReadExReq MSHR hits
system.l2c.demand_mshr_hits::cpu0                  24                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1                  23                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2                  33                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3                  32                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4                  34                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5                  30                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6                  27                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7                  39                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                242                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0                 24                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1                 23                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2                 33                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3                 32                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4                 34                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5                 30                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6                 27                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7                 39                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               242                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0              714                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1              736                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2              763                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3              713                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu4              757                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu5              749                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu6              785                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu7              732                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            5949                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0          1952                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1          1933                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2          2006                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3          1960                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4          1920                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5          2007                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6          1916                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7          1894                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        15588                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0           4342                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1           4376                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2           4248                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3           4311                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4           4338                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5           4326                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6           4224                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7           4275                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         34440                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0              5056                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1              5112                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2              5011                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3              5024                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4              5095                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5              5075                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6              5009                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7              5007                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            40389                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0             5056                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1             5112                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2             5011                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3             5024                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4             5095                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5             5075                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6             5009                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7             5007                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           40389                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0     28564754                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1     29444935                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2     30526423                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3     28524830                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu4     30284517                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu5     29963728                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu6     31404851                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu7     29284664                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    237998702                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0     78081132                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1     77281042                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2     80241204                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3     78401138                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4     76801198                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5     80241160                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6     76640992                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7     75761030                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    623448896                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0    173685720                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1    175005460                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2    169924253                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3    172445652                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4    173444745                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5    173045540                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6    168925276                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7    170965174                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1377441820                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0    202250474                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1    204450395                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2    200450676                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3    200970482                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4    203729262                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5    203009268                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6    200330127                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7    200249838                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   1615440522                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0    202250474                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1    204450395                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2    200450676                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3    200970482                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4    203729262                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5    203009268                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6    200330127                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7    200249838                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   1615440522                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    400927744                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    396406972                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    396807484                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    398767759                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    400808423                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    395927220                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    398767355                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    395367613                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   3183780570                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    211603917                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    215684252                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    216163665                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    212923402                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    213723846                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    215924115                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    217803639                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    216444289                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1720271125                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0    612531661                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1    612091224                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2    612971149                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3    611691161                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4    614532269                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5    611851335                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6    616570994                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7    611811902                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   4904051695                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0      0.062260                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1      0.064789                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2      0.067018                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3      0.062588                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu4      0.066299                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu5      0.066460                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu6      0.067754                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu7      0.063520                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.065085                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.842105                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.853045                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.855802                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.850694                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.839528                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.843277                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.841828                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.853922                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.847496                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.692614                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.706832                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.698340                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.691087                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.695861                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.689732                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.690535                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.696594                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.695182                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0       0.285054                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1       0.291265                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2       0.286867                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3       0.284969                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4       0.288636                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5       0.289306                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6       0.282946                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7       0.283506                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.286561                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0      0.285054                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1      0.291265                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2      0.286867                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3      0.284969                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4      0.288636                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5      0.289306                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6      0.282946                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7      0.283506                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.286561                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40006.658263                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40006.705163                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40008.418087                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 40006.774194                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 40005.966975                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40004.977303                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 40006.179618                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 40006.371585                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40006.505631                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40000.579918                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 39979.845835                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40000.600199                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40000.580612                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40000.623958                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 39980.647733                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40000.517745                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40000.543823                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 39995.438542                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 40001.317365                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39992.106947                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 40001.001177                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 40001.311065                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 39982.652144                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40001.280629                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 39991.779356                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 39991.853567                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 39995.407085                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 40002.071598                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 39994.208725                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 40002.130513                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 40002.086385                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 39986.116192                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 40001.826207                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 39994.036135                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 39993.976034                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 39997.041818                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 40002.071598                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 39994.208725                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 40002.130513                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 40002.086385                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 39986.116192                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 40001.826207                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 39994.036135                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 39993.976034                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 39997.041818                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cpu0.num_reads                           99016                       # number of read accesses completed
system.cpu0.num_writes                          53340                       # number of write accesses completed
system.cpu0.num_copies                              0                       # number of copy accesses completed
system.cpu0.l1c.replacements                    21906                       # number of replacements
system.cpu0.l1c.tagsinuse                  396.590239                       # Cycle average of tags in use
system.cpu0.l1c.total_refs                      13140                       # Total number of references to valid blocks.
system.cpu0.l1c.sampled_refs                    22312                       # Sample count of references to valid blocks.
system.cpu0.l1c.avg_refs                     0.588921                       # Average number of references to valid blocks.
system.cpu0.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu0.l1c.occ_blocks::cpu0           396.590239                       # Average occupied blocks per requestor
system.cpu0.l1c.occ_percent::cpu0            0.774590                       # Average percentage of cache occupancy
system.cpu0.l1c.occ_percent::total           0.774590                       # Average percentage of cache occupancy
system.cpu0.l1c.ReadReq_hits::cpu0               8561                       # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total              8561                       # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0              1051                       # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total             1051                       # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0                9612                       # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total               9612                       # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0               9612                       # number of overall hits
system.cpu0.l1c.overall_hits::total              9612                       # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0            35875                       # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total           35875                       # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0           23186                       # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total          23186                       # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0             59061                       # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total            59061                       # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0            59061                       # number of overall misses
system.cpu0.l1c.overall_misses::total           59061                       # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0    894906998                       # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total    894906998                       # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0    820039819                       # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total    820039819                       # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0   1714946817                       # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total   1714946817                       # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0   1714946817                       # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total   1714946817                       # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0          44436                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total         44436                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0         24237                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total        24237                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0           68673                       # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total          68673                       # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0          68673                       # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total         68673                       # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.807341                       # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total     0.807341                       # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.956637                       # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total     0.956637                       # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0       0.860032                       # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total      0.860032                       # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0      0.860032                       # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total     0.860032                       # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 24945.142801                       # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 24945.142801                       # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 35367.886613                       # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 35367.886613                       # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 29036.874029                       # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 29036.874029                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 29036.874029                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 29036.874029                       # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs    154642800                       # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_mshrs               53124                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_mshrs  2910.978089                       # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu0.l1c.writebacks::writebacks           9551                       # number of writebacks
system.cpu0.l1c.writebacks::total                9551                       # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0        35875                       # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total        35875                       # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23186                       # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total        23186                       # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0        59061                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total        59061                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0        59061                       # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total        59061                       # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    858892486                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total    858892486                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    796764078                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total    796764078                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1655656564                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total   1655656564                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1655656564                       # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total   1655656564                       # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    681029068                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    681029068                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0    670499371                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total    670499371                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   1351528439                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total   1351528439                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.807341                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.807341                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.956637                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.956637                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.860032                       # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total     0.860032                       # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.860032                       # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total     0.860032                       # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 23941.253965                       # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 23941.253965                       # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 34364.016130                       # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 34364.016130                       # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28032.992398                       # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28032.992398                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28032.992398                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28032.992398                       # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0          inf                       # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu1.num_reads                           99689                       # number of read accesses completed
system.cpu1.num_writes                          53832                       # number of write accesses completed
system.cpu1.num_copies                              0                       # number of copy accesses completed
system.cpu1.l1c.replacements                    21971                       # number of replacements
system.cpu1.l1c.tagsinuse                  397.434568                       # Cycle average of tags in use
system.cpu1.l1c.total_refs                      13255                       # Total number of references to valid blocks.
system.cpu1.l1c.sampled_refs                    22377                       # Sample count of references to valid blocks.
system.cpu1.l1c.avg_refs                     0.592349                       # Average number of references to valid blocks.
system.cpu1.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu1.l1c.occ_blocks::cpu1           397.434568                       # Average occupied blocks per requestor
system.cpu1.l1c.occ_percent::cpu1            0.776239                       # Average percentage of cache occupancy
system.cpu1.l1c.occ_percent::total           0.776239                       # Average percentage of cache occupancy
system.cpu1.l1c.ReadReq_hits::cpu1               8630                       # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total              8630                       # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1              1103                       # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total             1103                       # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1                9733                       # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total               9733                       # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1               9733                       # number of overall hits
system.cpu1.l1c.overall_hits::total              9733                       # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1            36139                       # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total           36139                       # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1           23155                       # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total          23155                       # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1             59294                       # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total            59294                       # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1            59294                       # number of overall misses
system.cpu1.l1c.overall_misses::total           59294                       # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1    902705787                       # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total    902705787                       # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1    819450505                       # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total    819450505                       # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1   1722156292                       # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total   1722156292                       # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1   1722156292                       # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total   1722156292                       # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1          44769                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total         44769                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1         24258                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total        24258                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1           69027                       # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total          69027                       # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1          69027                       # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total         69027                       # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.807233                       # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total     0.807233                       # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.954530                       # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total     0.954530                       # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1       0.858997                       # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total      0.858997                       # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1      0.858997                       # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total     0.858997                       # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 24978.715155                       # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 24978.715155                       # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 35389.786439                       # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 35389.786439                       # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 29044.360171                       # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 29044.360171                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 29044.360171                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 29044.360171                       # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs    155390130                       # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_mshrs               53247                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_mshrs  2918.288918                       # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu1.l1c.writebacks::writebacks           9603                       # number of writebacks
system.cpu1.l1c.writebacks::total                9603                       # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36139                       # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total        36139                       # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23155                       # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total        23155                       # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1        59294                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total        59294                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1        59294                       # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total        59294                       # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    866427236                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total    866427236                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    796207895                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total    796207895                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1662635131                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total   1662635131                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1662635131                       # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total   1662635131                       # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    674093801                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    674093801                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1    675943433                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total    675943433                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   1350037234                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total   1350037234                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.807233                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.807233                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.954530                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.954530                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.858997                       # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total     0.858997                       # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.858997                       # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total     0.858997                       # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 23974.853648                       # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 23974.853648                       # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 34386.002807                       # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 34386.002807                       # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28040.529075                       # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28040.529075                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28040.529075                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28040.529075                       # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1          inf                       # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu2.num_reads                           99864                       # number of read accesses completed
system.cpu2.num_writes                          53679                       # number of write accesses completed
system.cpu2.num_copies                              0                       # number of copy accesses completed
system.cpu2.l1c.replacements                    22117                       # number of replacements
system.cpu2.l1c.tagsinuse                  397.846327                       # Cycle average of tags in use
system.cpu2.l1c.total_refs                      13470                       # Total number of references to valid blocks.
system.cpu2.l1c.sampled_refs                    22518                       # Sample count of references to valid blocks.
system.cpu2.l1c.avg_refs                     0.598188                       # Average number of references to valid blocks.
system.cpu2.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu2.l1c.occ_blocks::cpu2           397.846327                       # Average occupied blocks per requestor
system.cpu2.l1c.occ_percent::cpu2            0.777044                       # Average percentage of cache occupancy
system.cpu2.l1c.occ_percent::total           0.777044                       # Average percentage of cache occupancy
system.cpu2.l1c.ReadReq_hits::cpu2               8720                       # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total              8720                       # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2              1090                       # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total             1090                       # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2                9810                       # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total               9810                       # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2               9810                       # number of overall hits
system.cpu2.l1c.overall_hits::total              9810                       # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2            36026                       # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total           36026                       # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2           23186                       # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total          23186                       # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2             59212                       # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total            59212                       # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2            59212                       # number of overall misses
system.cpu2.l1c.overall_misses::total           59212                       # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2    899117648                       # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total    899117648                       # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2    813653609                       # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total    813653609                       # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2   1712771257                       # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total   1712771257                       # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2   1712771257                       # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total   1712771257                       # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2          44746                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total         44746                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2         24276                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total        24276                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2           69022                       # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total          69022                       # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2          69022                       # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total         69022                       # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.805122                       # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total     0.805122                       # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.955100                       # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total     0.955100                       # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2       0.857871                       # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total      0.857871                       # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2      0.857871                       # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total     0.857871                       # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 24957.465386                       # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 24957.465386                       # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 35092.452730                       # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 35092.452730                       # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 28926.083513                       # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 28926.083513                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 28926.083513                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 28926.083513                       # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs    153072251                       # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_mshrs               52648                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_mshrs  2907.465640                       # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu2.l1c.writebacks::writebacks           9600                       # number of writebacks
system.cpu2.l1c.writebacks::total                9600                       # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36026                       # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total        36026                       # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2        23186                       # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total        23186                       # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2        59212                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total        59212                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2        59212                       # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total        59212                       # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    862954550                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total    862954550                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    790376865                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total    790376865                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1653331415                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total   1653331415                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1653331415                       # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total   1653331415                       # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    676110998                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    676110998                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2    681557695                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total    681557695                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   1357668693                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total   1357668693                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.805122                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.805122                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.955100                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.955100                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.857871                       # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total     0.857871                       # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.857871                       # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total     0.857871                       # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 23953.659857                       # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 23953.659857                       # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 34088.538989                       # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 34088.538989                       # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 27922.235611                       # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 27922.235611                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 27922.235611                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 27922.235611                       # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2          inf                       # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu3.num_reads                           98954                       # number of read accesses completed
system.cpu3.num_writes                          53519                       # number of write accesses completed
system.cpu3.num_copies                              0                       # number of copy accesses completed
system.cpu3.l1c.replacements                    21866                       # number of replacements
system.cpu3.l1c.tagsinuse                  395.683419                       # Cycle average of tags in use
system.cpu3.l1c.total_refs                      13218                       # Total number of references to valid blocks.
system.cpu3.l1c.sampled_refs                    22277                       # Sample count of references to valid blocks.
system.cpu3.l1c.avg_refs                     0.593347                       # Average number of references to valid blocks.
system.cpu3.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu3.l1c.occ_blocks::cpu3           395.683419                       # Average occupied blocks per requestor
system.cpu3.l1c.occ_percent::cpu3            0.772819                       # Average percentage of cache occupancy
system.cpu3.l1c.occ_percent::total           0.772819                       # Average percentage of cache occupancy
system.cpu3.l1c.ReadReq_hits::cpu3               8562                       # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total              8562                       # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3              1098                       # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total             1098                       # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3                9660                       # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total               9660                       # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3               9660                       # number of overall hits
system.cpu3.l1c.overall_hits::total              9660                       # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3            35996                       # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total           35996                       # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3           23029                       # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total          23029                       # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3             59025                       # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total            59025                       # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3            59025                       # number of overall misses
system.cpu3.l1c.overall_misses::total           59025                       # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3    899058428                       # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total    899058428                       # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3    817455350                       # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total    817455350                       # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3   1716513778                       # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total   1716513778                       # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3   1716513778                       # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total   1716513778                       # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3          44558                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total         44558                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3         24127                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total        24127                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3           68685                       # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total          68685                       # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3          68685                       # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total         68685                       # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.807846                       # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total     0.807846                       # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.954491                       # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total     0.954491                       # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3       0.859358                       # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total      0.859358                       # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3      0.859358                       # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total     0.859358                       # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 24976.620402                       # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 24976.620402                       # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 35496.780147                       # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 35496.780147                       # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 29081.131351                       # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 29081.131351                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 29081.131351                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 29081.131351                       # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs    155038956                       # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_mshrs               53124                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_mshrs  2918.435283                       # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu3.l1c.writebacks::writebacks           9442                       # number of writebacks
system.cpu3.l1c.writebacks::total                9442                       # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3        35996                       # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total        35996                       # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23029                       # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total        23029                       # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3        59025                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total        59025                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3        59025                       # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total        59025                       # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    862924447                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total    862924447                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    794336234                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total    794336234                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1657260681                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total   1657260681                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1657260681                       # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total   1657260681                       # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    680106792                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    680106792                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3    674669668                       # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total    674669668                       # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   1354776460                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total   1354776460                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.807846                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.807846                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.954491                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.954491                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.859358                       # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total     0.859358                       # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.859358                       # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total     0.859358                       # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 23972.787171                       # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 23972.787171                       # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 34492.866994                       # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 34492.866994                       # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28077.266938                       # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28077.266938                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28077.266938                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28077.266938                       # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average WriteReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3          inf                       # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu4.num_reads                           99591                       # number of read accesses completed
system.cpu4.num_writes                          53646                       # number of write accesses completed
system.cpu4.num_copies                              0                       # number of copy accesses completed
system.cpu4.l1c.replacements                    22293                       # number of replacements
system.cpu4.l1c.tagsinuse                  397.816545                       # Cycle average of tags in use
system.cpu4.l1c.total_refs                      13327                       # Total number of references to valid blocks.
system.cpu4.l1c.sampled_refs                    22684                       # Sample count of references to valid blocks.
system.cpu4.l1c.avg_refs                     0.587507                       # Average number of references to valid blocks.
system.cpu4.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu4.l1c.occ_blocks::cpu4           397.816545                       # Average occupied blocks per requestor
system.cpu4.l1c.occ_percent::cpu4            0.776985                       # Average percentage of cache occupancy
system.cpu4.l1c.occ_percent::total           0.776985                       # Average percentage of cache occupancy
system.cpu4.l1c.ReadReq_hits::cpu4               8743                       # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total              8743                       # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4              1036                       # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total             1036                       # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4                9779                       # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total               9779                       # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4               9779                       # number of overall hits
system.cpu4.l1c.overall_hits::total              9779                       # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4            35998                       # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total           35998                       # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4           23232                       # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total          23232                       # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4             59230                       # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total            59230                       # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4            59230                       # number of overall misses
system.cpu4.l1c.overall_misses::total           59230                       # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4    899681935                       # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total    899681935                       # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4    816003996                       # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total    816003996                       # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4   1715685931                       # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total   1715685931                       # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4   1715685931                       # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total   1715685931                       # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4          44741                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total         44741                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4         24268                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total        24268                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4           69009                       # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total          69009                       # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4          69009                       # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total         69009                       # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.804586                       # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total     0.804586                       # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.957310                       # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total     0.957310                       # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4       0.858294                       # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total      0.858294                       # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4      0.858294                       # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total     0.858294                       # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 24992.553336                       # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 24992.553336                       # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 35124.138946                       # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 35124.138946                       # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 28966.502296                       # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 28966.502296                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 28966.502296                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 28966.502296                       # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs    154355931                       # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_mshrs               53171                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_mshrs  2903.009742                       # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu4.l1c.writebacks::writebacks           9702                       # number of writebacks
system.cpu4.l1c.writebacks::total                9702                       # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4        35998                       # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total        35998                       # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23232                       # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total        23232                       # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4        59230                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total        59230                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4        59230                       # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total        59230                       # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    863541936                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total    863541936                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    792684079                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total    792684079                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1656226015                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total   1656226015                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1656226015                       # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total   1656226015                       # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    681350371                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    681350371                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4    669996228                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total    669996228                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   1351346599                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total   1351346599                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.804586                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.804586                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.957310                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.957310                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.858294                       # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total     0.858294                       # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.858294                       # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total     0.858294                       # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 23988.608700                       # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 23988.608700                       # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 34120.354640                       # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 34120.354640                       # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 27962.620547                       # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 27962.620547                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 27962.620547                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 27962.620547                       # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4          inf                       # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu5.num_reads                           99523                       # number of read accesses completed
system.cpu5.num_writes                          53948                       # number of write accesses completed
system.cpu5.num_copies                              0                       # number of copy accesses completed
system.cpu5.l1c.replacements                    22088                       # number of replacements
system.cpu5.l1c.tagsinuse                  397.555659                       # Cycle average of tags in use
system.cpu5.l1c.total_refs                      13442                       # Total number of references to valid blocks.
system.cpu5.l1c.sampled_refs                    22486                       # Sample count of references to valid blocks.
system.cpu5.l1c.avg_refs                     0.597794                       # Average number of references to valid blocks.
system.cpu5.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu5.l1c.occ_blocks::cpu5           397.555659                       # Average occupied blocks per requestor
system.cpu5.l1c.occ_percent::cpu5            0.776476                       # Average percentage of cache occupancy
system.cpu5.l1c.occ_percent::total           0.776476                       # Average percentage of cache occupancy
system.cpu5.l1c.ReadReq_hits::cpu5               8700                       # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total              8700                       # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5              1066                       # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total             1066                       # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5                9766                       # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total               9766                       # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5               9766                       # number of overall hits
system.cpu5.l1c.overall_hits::total              9766                       # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5            36016                       # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total           36016                       # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5           23333                       # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total          23333                       # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5             59349                       # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total            59349                       # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5            59349                       # number of overall misses
system.cpu5.l1c.overall_misses::total           59349                       # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5    899040098                       # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total    899040098                       # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5    826704780                       # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total    826704780                       # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5   1725744878                       # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total   1725744878                       # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5   1725744878                       # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total   1725744878                       # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5          44716                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total         44716                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5         24399                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total        24399                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5           69115                       # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total          69115                       # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5          69115                       # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total         69115                       # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.805439                       # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total     0.805439                       # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.956310                       # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total     0.956310                       # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5       0.858699                       # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total      0.858699                       # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5      0.858699                       # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total     0.858699                       # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 24962.241726                       # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 24962.241726                       # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 35430.711010                       # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 35430.711010                       # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 29077.909956                       # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 29077.909956                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 29077.909956                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 29077.909956                       # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs    155795508                       # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_mshrs               53352                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_mshrs  2920.143725                       # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu5.l1c.writebacks::writebacks           9610                       # number of writebacks
system.cpu5.l1c.writebacks::total                9610                       # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36016                       # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total        36016                       # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23333                       # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total        23333                       # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5        59349                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total        59349                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5        59349                       # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total        59349                       # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    862885041                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total    862885041                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    803284460                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total    803284460                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1666169501                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total   1666169501                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1666169501                       # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total   1666169501                       # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    674425818                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    674425818                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5    675374924                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total    675374924                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   1349800742                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total   1349800742                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.805439                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.805439                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.956310                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.956310                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.858699                       # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total     0.858699                       # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.858699                       # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total     0.858699                       # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 23958.380747                       # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 23958.380747                       # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 34426.968671                       # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 34426.968671                       # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28074.095621                       # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28074.095621                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28074.095621                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28074.095621                       # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5          inf                       # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu6.num_reads                          100000                       # number of read accesses completed
system.cpu6.num_writes                          53510                       # number of write accesses completed
system.cpu6.num_copies                              0                       # number of copy accesses completed
system.cpu6.l1c.replacements                    22177                       # number of replacements
system.cpu6.l1c.tagsinuse                  397.660479                       # Cycle average of tags in use
system.cpu6.l1c.total_refs                      13364                       # Total number of references to valid blocks.
system.cpu6.l1c.sampled_refs                    22573                       # Sample count of references to valid blocks.
system.cpu6.l1c.avg_refs                     0.592035                       # Average number of references to valid blocks.
system.cpu6.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu6.l1c.occ_blocks::cpu6           397.660479                       # Average occupied blocks per requestor
system.cpu6.l1c.occ_percent::cpu6            0.776681                       # Average percentage of cache occupancy
system.cpu6.l1c.occ_percent::total           0.776681                       # Average percentage of cache occupancy
system.cpu6.l1c.ReadReq_hits::cpu6               8760                       # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total              8760                       # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6              1035                       # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total             1035                       # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6                9795                       # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total               9795                       # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6               9795                       # number of overall hits
system.cpu6.l1c.overall_hits::total              9795                       # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6            36279                       # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total           36279                       # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6           23033                       # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total          23033                       # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6             59312                       # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total            59312                       # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6            59312                       # number of overall misses
system.cpu6.l1c.overall_misses::total           59312                       # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6    908517794                       # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total    908517794                       # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6    809582336                       # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total    809582336                       # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6   1718100130                       # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total   1718100130                       # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6   1718100130                       # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total   1718100130                       # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6          45039                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total         45039                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6         24068                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total        24068                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6           69107                       # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total          69107                       # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6          69107                       # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total         69107                       # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.805502                       # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total     0.805502                       # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.956997                       # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total     0.956997                       # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6       0.858263                       # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total      0.858263                       # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6      0.858263                       # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total     0.858263                       # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 25042.525814                       # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 25042.525814                       # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 35148.801111                       # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 35148.801111                       # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 28967.158922                       # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 28967.158922                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 28967.158922                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 28967.158922                       # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs    154185284                       # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_mshrs               52977                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_mshrs  2910.419314                       # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu6.l1c.writebacks::writebacks           9564                       # number of writebacks
system.cpu6.l1c.writebacks::total                9564                       # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36279                       # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total        36279                       # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23033                       # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total        23033                       # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6        59312                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total        59312                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6        59312                       # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total        59312                       # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    872097671                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total    872097671                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    786461211                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total    786461211                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1658558882                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total   1658558882                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1658558882                       # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total   1658558882                       # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    680107967                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    680107967                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6    681972539                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total    681972539                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   1362080506                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total   1362080506                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.805502                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.805502                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.956997                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.956997                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.858263                       # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total     0.858263                       # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.858263                       # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total     0.858263                       # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24038.635878                       # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24038.635878                       # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34144.975079                       # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34144.975079                       # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 27963.293802                       # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 27963.293802                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 27963.293802                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 27963.293802                       # average overall mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6          inf                       # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu7.num_reads                           99201                       # number of read accesses completed
system.cpu7.num_writes                          53497                       # number of write accesses completed
system.cpu7.num_copies                              0                       # number of copy accesses completed
system.cpu7.l1c.replacements                    22218                       # number of replacements
system.cpu7.l1c.tagsinuse                  396.828031                       # Cycle average of tags in use
system.cpu7.l1c.total_refs                      13271                       # Total number of references to valid blocks.
system.cpu7.l1c.sampled_refs                    22622                       # Sample count of references to valid blocks.
system.cpu7.l1c.avg_refs                     0.586641                       # Average number of references to valid blocks.
system.cpu7.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu7.l1c.occ_blocks::cpu7           396.828031                       # Average occupied blocks per requestor
system.cpu7.l1c.occ_percent::cpu7            0.775055                       # Average percentage of cache occupancy
system.cpu7.l1c.occ_percent::total           0.775055                       # Average percentage of cache occupancy
system.cpu7.l1c.ReadReq_hits::cpu7               8703                       # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total              8703                       # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7              1096                       # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total             1096                       # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7                9799                       # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total               9799                       # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7               9799                       # number of overall hits
system.cpu7.l1c.overall_hits::total              9799                       # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7            36453                       # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total           36453                       # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7           22910                       # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total          22910                       # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7             59363                       # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total            59363                       # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7            59363                       # number of overall misses
system.cpu7.l1c.overall_misses::total           59363                       # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7    908883238                       # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total    908883238                       # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7    808946616                       # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total    808946616                       # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7   1717829854                       # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total   1717829854                       # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7   1717829854                       # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total   1717829854                       # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7          45156                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total         45156                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7         24006                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total        24006                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7           69162                       # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total          69162                       # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7          69162                       # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total         69162                       # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.807268                       # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total     0.807268                       # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.954345                       # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total     0.954345                       # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7       0.858318                       # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total      0.858318                       # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7      0.858318                       # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total     0.858318                       # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 24933.016158                       # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 24933.016158                       # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 35309.760629                       # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 35309.760629                       # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 28937.719691                       # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 28937.719691                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 28937.719691                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 28937.719691                       # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs    153732048                       # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_mshrs               53029                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_mshrs  2899.018424                       # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu7.l1c.writebacks::writebacks           9581                       # number of writebacks
system.cpu7.l1c.writebacks::total                9581                       # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36453                       # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total        36453                       # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7        22910                       # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total        22910                       # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7        59363                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total        59363                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7        59363                       # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total        59363                       # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    872289420                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total    872289420                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    785947981                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total    785947981                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1658237401                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total   1658237401                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1658237401                       # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total   1658237401                       # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    674384984                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    674384984                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7    681937361                       # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total    681937361                       # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   1356322345                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total   1356322345                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.807268                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.807268                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.954345                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.954345                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.858318                       # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total     0.858318                       # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.858318                       # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total     0.858318                       # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 23929.153156                       # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 23929.153156                       # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 34305.891794                       # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 34305.891794                       # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 27933.854438                       # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 27933.854438                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 27933.854438                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 27933.854438                       # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average WriteReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------