path: root/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000757                       # Number of seconds simulated
sim_ticks                                   757091500                       # Number of ticks simulated
final_tick                                  757091500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_tick_rate                              129668365                       # Simulator tick rate (ticks/s)
host_mem_usage                                 347944                       # Number of bytes of host memory used
host_seconds                                     5.84                       # Real time elapsed on the host
system.physmem.bytes_read::cpu0                 90255                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1                 89097                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2                 89397                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3                 87447                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu4                 92253                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu5                 92127                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu6                 87941                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu7                 90122                       # Number of bytes read from this memory
system.physmem.bytes_read::total               718639                       # Number of bytes read from this memory
system.physmem.bytes_written::writebacks       466688                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0               5395                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1               5319                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu2               5314                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu3               5343                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu4               5295                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu5               5581                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu6               5197                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu7               5320                       # Number of bytes written to this memory
system.physmem.bytes_written::total            509452                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0                  11064                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1                  10977                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2                  11088                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3                  11217                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4                  11361                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5                  11298                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6                  11018                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7                  11057                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 89080                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks            7292                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0                  5395                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1                  5319                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2                  5314                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3                  5343                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4                  5295                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5                  5581                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6                  5197                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7                  5320                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                50056                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0                119212803                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1                117683265                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2                118079519                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3                115503872                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4                121851850                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5                121685424                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6                116156369                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7                119037131                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               949210234                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         616422189                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0                 7125955                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1                 7025571                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2                 7018967                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3                 7057271                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4                 6993871                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5                 7371632                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6                 6864428                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7                 7026892                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              672906775                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         616422189                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0               126338758                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1               124708836                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2               125098485                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3               122561144                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4               128845721                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5               129057056                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6               123020797                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7               126064023                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             1622117010                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                         15543                       # number of replacements
system.l2c.tagsinuse                       804.498263                       # Cycle average of tags in use
system.l2c.total_refs                          151705                       # Total number of references to valid blocks.
system.l2c.sampled_refs                         16364                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          9.270655                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks          743.034079                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0                  7.652510                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1                  7.207345                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2                  7.804802                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3                  7.584993                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu4                  7.883519                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu5                  7.822009                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu6                  7.314161                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu7                  8.194845                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.725619                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0                 0.007473                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1                 0.007038                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2                 0.007622                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3                 0.007407                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu4                 0.007699                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu5                 0.007639                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu6                 0.007143                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu7                 0.008003                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.785643                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0                   10656                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1                   10576                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2                   10855                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3                   10944                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu4                   10856                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu5                   10997                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu6                   10762                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu7                   10884                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  86530                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks           77152                       # number of Writeback hits
system.l2c.Writeback_hits::total                77152                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0                  335                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1                  345                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2                  353                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3                  387                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4                  361                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5                  367                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6                  340                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7                  332                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                2820                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0                  2056                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1                  2082                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2                  2008                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3                  2098                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4                  2081                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5                  2029                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6                  2020                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7                  2069                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                16443                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0                    12712                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1                    12658                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2                    12863                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3                    13042                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu4                    12937                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu5                    13026                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu6                    12782                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu7                    12953                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  102973                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0                   12712                       # number of overall hits
system.l2c.overall_hits::cpu1                   12658                       # number of overall hits
system.l2c.overall_hits::cpu2                   12863                       # number of overall hits
system.l2c.overall_hits::cpu3                   13042                       # number of overall hits
system.l2c.overall_hits::cpu4                   12937                       # number of overall hits
system.l2c.overall_hits::cpu5                   13026                       # number of overall hits
system.l2c.overall_hits::cpu6                   12782                       # number of overall hits
system.l2c.overall_hits::cpu7                   12953                       # number of overall hits
system.l2c.overall_hits::total                 102973                       # number of overall hits
system.l2c.ReadReq_misses::cpu0                   825                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1                   783                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2                   805                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3                   784                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu4                   818                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu5                   847                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu6                   802                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu7                   828                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 6492                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0               1871                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1               1835                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2               1867                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3               1892                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4               1828                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5               1835                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6               1851                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7               1876                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             14855                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0                4261                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1                4189                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2                4229                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3                4314                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4                4275                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5                4251                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6                4117                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7                4314                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              33950                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0                   5086                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1                   4972                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2                   5034                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3                   5098                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu4                   5093                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu5                   5098                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu6                   4919                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu7                   5142                       # number of demand (read+write) misses
system.l2c.demand_misses::total                 40442                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0                  5086                       # number of overall misses
system.l2c.overall_misses::cpu1                  4972                       # number of overall misses
system.l2c.overall_misses::cpu2                  5034                       # number of overall misses
system.l2c.overall_misses::cpu3                  5098                       # number of overall misses
system.l2c.overall_misses::cpu4                  5093                       # number of overall misses
system.l2c.overall_misses::cpu5                  5098                       # number of overall misses
system.l2c.overall_misses::cpu6                  4919                       # number of overall misses
system.l2c.overall_misses::cpu7                  5142                       # number of overall misses
system.l2c.overall_misses::total                40442                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0        68189898                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1        66156919                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2        68642411                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3        68279416                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu4        69618906                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu5        72771903                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu6        69510913                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu7        75078411                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      558248777                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0     55439380                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1     51556398                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2     53772873                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3     56810367                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4     54586881                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5     52940893                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6     52708899                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7     53996365                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    431812056                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0     243093964                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1     240130019                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2     242345503                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3     242765011                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4     244393485                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5     241342993                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6     234214460                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7     244073518                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1932358953                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0        311283862                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1        306286938                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2        310987914                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3        311044427                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4        314012391                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5        314114896                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6        303725373                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7        319151929                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      2490607730                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0       311283862                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1       306286938                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2       310987914                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3       311044427                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4       314012391                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5       314114896                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6       303725373                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7       319151929                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     2490607730                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0               11481                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1               11359                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2               11660                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3               11728                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu4               11674                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu5               11844                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu6               11564                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu7               11712                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              93022                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks        77152                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total            77152                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0             2206                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1             2180                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2             2220                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3             2279                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4             2189                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5             2202                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6             2191                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7             2208                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           17675                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0              6317                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1              6271                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2              6237                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3              6412                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4              6356                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5              6280                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6              6137                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7              6383                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            50393                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0                17798                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1                17630                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2                17897                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3                18140                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4                18030                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5                18124                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6                17701                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7                18095                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              143415                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0               17798                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1               17630                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2               17897                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3               18140                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4               18030                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5               18124                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6               17701                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7               18095                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             143415                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0           0.071858                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1           0.068932                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2           0.069039                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3           0.066849                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu4           0.070070                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu5           0.071513                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu6           0.069353                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu7           0.070697                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.069790                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0        0.848141                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1        0.841743                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2        0.840991                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3        0.830189                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4        0.835085                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5        0.833333                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6        0.844820                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7        0.849638                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.840453                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0         0.674529                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1         0.667996                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2         0.678050                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3         0.672801                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4         0.672593                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5         0.676911                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6         0.670849                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7         0.675858                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.673705                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0            0.285762                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1            0.282019                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2            0.281276                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3            0.281036                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4            0.282474                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5            0.281284                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6            0.277894                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7            0.284167                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.281993                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0           0.285762                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1           0.282019                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2           0.281276                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3           0.281036                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4           0.282474                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5           0.281284                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6           0.277894                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7           0.284167                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.281993                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0 82654.421818                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1 84491.595147                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2 85270.075776                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3 87091.091837                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu4 85108.687042                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu5 85917.240850                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu6 86671.961347                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu7 90674.409420                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 85990.261399                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0 29630.881881                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 28096.129700                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 28801.753080                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 30026.621036                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 29861.532276                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 28850.622888                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 28475.904376                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 28782.710554                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 29068.465567                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 57050.918564                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 57323.948198                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 57305.628517                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 56273.762401                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 57168.066667                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 56773.228182                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 56889.594365                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 56577.078813                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 56917.789485                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 61204.062525                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 61602.360821                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 61777.495828                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 61013.030012                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 61655.682505                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 61615.318949                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 61745.349258                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 62067.664138                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 61584.682508                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 61204.062525                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 61602.360821                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 61777.495828                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 61013.030012                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 61655.682505                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 61615.318949                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 61745.349258                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 62067.664138                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 61584.682508                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs            323471                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                       94                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs   3441.180851                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks                7293                       # number of writebacks
system.l2c.writebacks::total                     7293                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0                  7                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1                  9                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2                 11                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3                  6                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu4                  8                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu5                  9                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu6                  9                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu7                  6                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                65                       # number of ReadReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu6               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::total              1                       # number of UpgradeReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu0                5                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu1                7                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu2                3                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu3                3                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu4                1                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5                4                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu6                6                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu7                2                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total              31                       # number of ReadExReq MSHR hits
system.l2c.demand_mshr_hits::cpu0                  12                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1                  16                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2                  14                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3                   9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4                   9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5                  13                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6                  15                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7                   8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 96                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0                 12                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1                 16                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2                 14                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3                  9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4                  9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5                 13                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6                 15                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7                  8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                96                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0              818                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1              774                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2              794                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3              778                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu4              810                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu5              838                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu6              793                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu7              822                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            6427                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0          1871                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1          1835                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2          1867                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3          1892                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4          1828                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5          1835                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6          1850                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7          1876                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        14854                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0           4256                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1           4182                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2           4226                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3           4311                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4           4274                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5           4247                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6           4111                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7           4312                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         33919                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0              5074                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1              4956                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2              5020                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3              5089                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4              5084                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5              5085                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6              4904                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7              5134                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            40346                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0             5074                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1             4956                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2             5020                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3             5089                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4             5084                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5             5085                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6             4904                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7             5134                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           40346                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0     57681466                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1     55801476                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2     58516973                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3     58678465                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu4     58920974                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu5     61933964                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu6     58878980                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu7     64759967                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    475172265                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0     77326932                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1     75430964                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2     76820936                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3     77936944                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4     75295947                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5     75638458                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6     76288450                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7     77210443                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    611949074                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0    190865870                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1    188480880                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2    190796375                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3    190236368                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4    192397382                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5    189567870                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6    183778356                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7    191626863                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1517749964                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0    248547336                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1    244282356                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2    249313348                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3    248914833                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4    251318356                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5    251501834                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6    242657336                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7    256386830                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   1992922229                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0    248547336                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1    244282356                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2    249313348                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3    248914833                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4    251318356                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5    251501834                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6    242657336                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7    256386830                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   1992922229                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    413458717                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    411792191                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    414319722                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    423127681                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    423239170                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    421136201                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    414540172                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    411527705                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   3333141559                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    232000375                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    229604409                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    230860874                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    229140383                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    229719408                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    244869353                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    226374384                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    231941380                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1854510566                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0    645459092                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1    641396600                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2    645180596                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3    652268064                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4    652958578                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5    666005554                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6    640914556                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7    643469085                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   5187652125                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0      0.071248                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1      0.068140                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2      0.068096                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3      0.066337                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu4      0.069385                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu5      0.070753                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu6      0.068575                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu7      0.070184                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.069091                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.848141                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.841743                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.840991                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.830189                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.835085                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.833333                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.844363                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.849638                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.840396                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.673738                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.666879                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.677569                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.672333                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.672435                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.676274                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.669871                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.675544                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.673090                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0       0.285088                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1       0.281112                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2       0.280494                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3       0.280540                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4       0.281974                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5       0.280567                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6       0.277046                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7       0.283725                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.281323                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0      0.285088                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1      0.281112                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2      0.280494                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3      0.280540                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4      0.281974                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5      0.280567                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6      0.277046                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7      0.283725                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.281323                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 70515.239609                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 72094.930233                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 73698.958438                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 75422.191517                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 72741.943210                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 73906.878282                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 74248.398487                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 78783.414842                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 73933.758363                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41329.199359                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41106.792371                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41146.725228                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41192.887949                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41190.342998                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41219.868120                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6        41237                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41156.952559                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41197.594857                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 44846.304041                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 45069.555237                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 45148.219356                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44128.129900                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 45015.765559                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44635.712267                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44704.051569                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44440.367115                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 44746.306318                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 48984.496650                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 49290.225182                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 49664.013546                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 48912.327176                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 49433.193548                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 49459.554376                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 49481.512235                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 49939.000779                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 49395.782209                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 48984.496650                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 49290.225182                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 49664.013546                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 48912.327176                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 49433.193548                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 49459.554376                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 49481.512235                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 49939.000779                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 49395.782209                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cpu0.num_reads                           98965                       # number of read accesses completed
system.cpu0.num_writes                          53188                       # number of write accesses completed
system.cpu0.num_copies                              0                       # number of copy accesses completed
system.cpu0.l1c.replacements                    22322                       # number of replacements
system.cpu0.l1c.tagsinuse                  389.061969                       # Cycle average of tags in use
system.cpu0.l1c.total_refs                      13312                       # Total number of references to valid blocks.
system.cpu0.l1c.sampled_refs                    22723                       # Sample count of references to valid blocks.
system.cpu0.l1c.avg_refs                     0.585838                       # Average number of references to valid blocks.
system.cpu0.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu0.l1c.occ_blocks::cpu0           389.061969                       # Average occupied blocks per requestor
system.cpu0.l1c.occ_percent::cpu0            0.759887                       # Average percentage of cache occupancy
system.cpu0.l1c.occ_percent::total           0.759887                       # Average percentage of cache occupancy
system.cpu0.l1c.ReadReq_hits::cpu0               8733                       # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total              8733                       # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0              1107                       # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total             1107                       # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0                9840                       # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total               9840                       # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0               9840                       # number of overall hits
system.cpu0.l1c.overall_hits::total              9840                       # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0            35619                       # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total           35619                       # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0           23007                       # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total          23007                       # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0             58626                       # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total            58626                       # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0            58626                       # number of overall misses
system.cpu0.l1c.overall_misses::total           58626                       # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0   4549553769                       # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total   4549553769                       # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0   3145624806                       # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total   3145624806                       # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0   7695178575                       # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total   7695178575                       # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0   7695178575                       # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total   7695178575                       # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0          44352                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total         44352                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0         24114                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total        24114                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0           68466                       # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total          68466                       # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0          68466                       # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total         68466                       # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.803098                       # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total     0.803098                       # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.954093                       # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total     0.954093                       # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0       0.856279                       # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total      0.856279                       # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0      0.856279                       # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total     0.856279                       # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 127728.284595                       # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 127728.284595                       # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 136724.684053                       # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 136724.684053                       # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 131258.802835                       # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 131258.802835                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 131258.802835                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 131258.802835                       # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs    714656307                       # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_mshrs               63701                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11218.918180                       # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu0.l1c.writebacks::writebacks           9780                       # number of writebacks
system.cpu0.l1c.writebacks::total                9780                       # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0        35619                       # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total        35619                       # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23007                       # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total        23007                       # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0        58626                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total        58626                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0        58626                       # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total        58626                       # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0   4478007425                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total   4478007425                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0   3099554441                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total   3099554441                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0   7577561866                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total   7577561866                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0   7577561866                       # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total   7577561866                       # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0   1380411824                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total   1380411824                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0    995386324                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total    995386324                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   2375798148                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total   2375798148                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.803098                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.803098                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.954093                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.954093                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.856279                       # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total     0.856279                       # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.856279                       # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total     0.856279                       # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 125719.627867                       # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 125719.627867                       # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 134722.234146                       # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 134722.234146                       # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 129252.581892                       # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 129252.581892                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 129252.581892                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 129252.581892                       # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0          inf                       # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu1.num_reads                           97331                       # number of read accesses completed
system.cpu1.num_writes                          52743                       # number of write accesses completed
system.cpu1.num_copies                              0                       # number of copy accesses completed
system.cpu1.l1c.replacements                    21605                       # number of replacements
system.cpu1.l1c.tagsinuse                  388.260770                       # Cycle average of tags in use
system.cpu1.l1c.total_refs                      12987                       # Total number of references to valid blocks.
system.cpu1.l1c.sampled_refs                    21962                       # Sample count of references to valid blocks.
system.cpu1.l1c.avg_refs                     0.591340                       # Average number of references to valid blocks.
system.cpu1.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu1.l1c.occ_blocks::cpu1           388.260770                       # Average occupied blocks per requestor
system.cpu1.l1c.occ_percent::cpu1            0.758322                       # Average percentage of cache occupancy
system.cpu1.l1c.occ_percent::total           0.758322                       # Average percentage of cache occupancy
system.cpu1.l1c.ReadReq_hits::cpu1               8534                       # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total              8534                       # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1              1058                       # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total             1058                       # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1                9592                       # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total               9592                       # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1               9592                       # number of overall hits
system.cpu1.l1c.overall_hits::total              9592                       # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1            35254                       # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total           35254                       # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1           22627                       # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total          22627                       # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1             57881                       # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total            57881                       # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1            57881                       # number of overall misses
system.cpu1.l1c.overall_misses::total           57881                       # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1   4617875359                       # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total   4617875359                       # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1   3138675137                       # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total   3138675137                       # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1   7756550496                       # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total   7756550496                       # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1   7756550496                       # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total   7756550496                       # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1          43788                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total         43788                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1         23685                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total        23685                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1           67473                       # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total          67473                       # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1          67473                       # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total         67473                       # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.805106                       # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total     0.805106                       # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.955330                       # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total     0.955330                       # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1       0.857839                       # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total      0.857839                       # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1      0.857839                       # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total     0.857839                       # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 130988.692319                       # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 130988.692319                       # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 138713.710921                       # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 138713.710921                       # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 134008.577875                       # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 134008.577875                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 134008.577875                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 134008.577875                       # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs    723339270                       # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_mshrs               62977                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11485.768932                       # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu1.l1c.writebacks::writebacks           9483                       # number of writebacks
system.cpu1.l1c.writebacks::total                9483                       # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1        35254                       # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total        35254                       # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1        22627                       # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total        22627                       # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1        57881                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total        57881                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1        57881                       # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total        57881                       # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1   4547061522                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total   4547061522                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1   3093362268                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total   3093362268                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1   7640423790                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total   7640423790                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1   7640423790                       # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total   7640423790                       # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1   1364091847                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total   1364091847                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1    932992416                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total    932992416                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   2297084263                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total   2297084263                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.805106                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.805106                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.955330                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.955330                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.857839                       # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total     0.857839                       # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.857839                       # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total     0.857839                       # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 128980.017076                       # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 128980.017076                       # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 136711.109206                       # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 136711.109206                       # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 132002.276913                       # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 132002.276913                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 132002.276913                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 132002.276913                       # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1          inf                       # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu2.num_reads                           98360                       # number of read accesses completed
system.cpu2.num_writes                          53068                       # number of write accesses completed
system.cpu2.num_copies                              0                       # number of copy accesses completed
system.cpu2.l1c.replacements                    22096                       # number of replacements
system.cpu2.l1c.tagsinuse                  389.724593                       # Cycle average of tags in use
system.cpu2.l1c.total_refs                      13250                       # Total number of references to valid blocks.
system.cpu2.l1c.sampled_refs                    22502                       # Sample count of references to valid blocks.
system.cpu2.l1c.avg_refs                     0.588837                       # Average number of references to valid blocks.
system.cpu2.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu2.l1c.occ_blocks::cpu2           389.724593                       # Average occupied blocks per requestor
system.cpu2.l1c.occ_percent::cpu2            0.761181                       # Average percentage of cache occupancy
system.cpu2.l1c.occ_percent::total           0.761181                       # Average percentage of cache occupancy
system.cpu2.l1c.ReadReq_hits::cpu2               8687                       # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total              8687                       # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2              1121                       # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total             1121                       # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2                9808                       # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total               9808                       # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2               9808                       # number of overall hits
system.cpu2.l1c.overall_hits::total              9808                       # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2            35624                       # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total           35624                       # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2           22874                       # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total          22874                       # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2             58498                       # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total            58498                       # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2            58498                       # number of overall misses
system.cpu2.l1c.overall_misses::total           58498                       # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2   4545456138                       # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total   4545456138                       # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2   3151736803                       # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total   3151736803                       # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2   7697192941                       # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total   7697192941                       # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2   7697192941                       # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total   7697192941                       # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2          44311                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total         44311                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2         23995                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total        23995                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2           68306                       # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total          68306                       # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2          68306                       # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total         68306                       # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.803954                       # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total     0.803954                       # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.953282                       # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total     0.953282                       # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2       0.856411                       # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total      0.856411                       # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2      0.856411                       # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total     0.856411                       # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 127595.332865                       # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 127595.332865                       # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 137786.867317                       # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 137786.867317                       # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 131580.446186                       # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 131580.446186                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 131580.446186                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 131580.446186                       # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs    716129194                       # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_mshrs               63633                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11254.053620                       # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu2.l1c.writebacks::writebacks           9686                       # number of writebacks
system.cpu2.l1c.writebacks::total                9686                       # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2        35624                       # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total        35624                       # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2        22874                       # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total        22874                       # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2        58498                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total        58498                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2        58498                       # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total        58498                       # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2   4473878832                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total   4473878832                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2   3105924454                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total   3105924454                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2   7579803286                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total   7579803286                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2   7579803286                       # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total   7579803286                       # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2   1379555288                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total   1379555288                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2    954692892                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total    954692892                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   2334248180                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total   2334248180                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.803954                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.803954                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.953282                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.953282                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.856411                       # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total     0.856411                       # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.856411                       # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total     0.856411                       # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 125586.088929                       # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 125586.088929                       # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 135784.054123                       # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 135784.054123                       # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 129573.716811                       # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 129573.716811                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 129573.716811                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 129573.716811                       # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2          inf                       # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu3.num_reads                          100000                       # number of read accesses completed
system.cpu3.num_writes                          53600                       # number of write accesses completed
system.cpu3.num_copies                              0                       # number of copy accesses completed
system.cpu3.l1c.replacements                    22673                       # number of replacements
system.cpu3.l1c.tagsinuse                  391.747074                       # Cycle average of tags in use
system.cpu3.l1c.total_refs                      13403                       # Total number of references to valid blocks.
system.cpu3.l1c.sampled_refs                    23070                       # Sample count of references to valid blocks.
system.cpu3.l1c.avg_refs                     0.580971                       # Average number of references to valid blocks.
system.cpu3.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu3.l1c.occ_blocks::cpu3           391.747074                       # Average occupied blocks per requestor
system.cpu3.l1c.occ_percent::cpu3            0.765131                       # Average percentage of cache occupancy
system.cpu3.l1c.occ_percent::total           0.765131                       # Average percentage of cache occupancy
system.cpu3.l1c.ReadReq_hits::cpu3               8720                       # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total              8720                       # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3              1143                       # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total             1143                       # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3                9863                       # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total               9863                       # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3               9863                       # number of overall hits
system.cpu3.l1c.overall_hits::total              9863                       # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3            36203                       # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total           36203                       # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3           22978                       # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total          22978                       # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3             59181                       # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total            59181                       # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3            59181                       # number of overall misses
system.cpu3.l1c.overall_misses::total           59181                       # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3   4605371729                       # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total   4605371729                       # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3   3121949330                       # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total   3121949330                       # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3   7727321059                       # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total   7727321059                       # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3   7727321059                       # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total   7727321059                       # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3          44923                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total         44923                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3         24121                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total        24121                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3           69044                       # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total          69044                       # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3          69044                       # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total         69044                       # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.805890                       # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total     0.805890                       # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.952614                       # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total     0.952614                       # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3       0.857149                       # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total      0.857149                       # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3      0.857149                       # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total     0.857149                       # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 127209.671270                       # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 127209.671270                       # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 135866.887022                       # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 135866.887022                       # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 130570.978169                       # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 130570.978169                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 130570.978169                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 130570.978169                       # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs    721076565                       # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_mshrs               64491                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11181.041773                       # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu3.l1c.writebacks::writebacks           9961                       # number of writebacks
system.cpu3.l1c.writebacks::total                9961                       # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36203                       # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total        36203                       # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3        22978                       # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total        22978                       # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3        59181                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total        59181                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3        59181                       # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total        59181                       # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3   4532659362                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total   4532659362                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3   3075925984                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total   3075925984                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3   7608585346                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total   7608585346                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3   7608585346                       # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total   7608585346                       # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3   1393944138                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total   1393944138                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3    919834390                       # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total    919834390                       # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   2313778528                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total   2313778528                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.805890                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.805890                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.952614                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.952614                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.857149                       # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total     0.857149                       # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.857149                       # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total     0.857149                       # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 125201.208795                       # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 125201.208795                       # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 133863.956132                       # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 133863.956132                       # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 128564.663422                       # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 128564.663422                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 128564.663422                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 128564.663422                       # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average WriteReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3          inf                       # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu4.num_reads                           99186                       # number of read accesses completed
system.cpu4.num_writes                          53232                       # number of write accesses completed
system.cpu4.num_copies                              0                       # number of copy accesses completed
system.cpu4.l1c.replacements                    22556                       # number of replacements
system.cpu4.l1c.tagsinuse                  391.523203                       # Cycle average of tags in use
system.cpu4.l1c.total_refs                      13363                       # Total number of references to valid blocks.
system.cpu4.l1c.sampled_refs                    22976                       # Sample count of references to valid blocks.
system.cpu4.l1c.avg_refs                     0.581607                       # Average number of references to valid blocks.
system.cpu4.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu4.l1c.occ_blocks::cpu4           391.523203                       # Average occupied blocks per requestor
system.cpu4.l1c.occ_percent::cpu4            0.764694                       # Average percentage of cache occupancy
system.cpu4.l1c.occ_percent::total           0.764694                       # Average percentage of cache occupancy
system.cpu4.l1c.ReadReq_hits::cpu4               8704                       # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total              8704                       # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4              1177                       # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total             1177                       # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4                9881                       # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total               9881                       # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4               9881                       # number of overall hits
system.cpu4.l1c.overall_hits::total              9881                       # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4            35925                       # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total           35925                       # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4           22955                       # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total          22955                       # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4             58880                       # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total            58880                       # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4            58880                       # number of overall misses
system.cpu4.l1c.overall_misses::total           58880                       # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4   4605243494                       # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total   4605243494                       # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4   3106119837                       # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total   3106119837                       # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4   7711363331                       # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total   7711363331                       # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4   7711363331                       # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total   7711363331                       # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4          44629                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total         44629                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4         24132                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total        24132                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4           68761                       # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total          68761                       # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4          68761                       # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total         68761                       # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.804970                       # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total     0.804970                       # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.951227                       # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total     0.951227                       # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4       0.856299                       # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total      0.856299                       # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4      0.856299                       # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total     0.856299                       # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 128190.493918                       # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 128190.493918                       # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 135313.432237                       # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 135313.432237                       # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 130967.447877                       # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 130967.447877                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 130967.447877                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 130967.447877                       # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs    718630789                       # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_mshrs               64157                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_mshrs 11201.128310                       # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu4.l1c.writebacks::writebacks           9838                       # number of writebacks
system.cpu4.l1c.writebacks::total                9838                       # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4        35925                       # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total        35925                       # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4        22955                       # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total        22955                       # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4        58880                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total        58880                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4        58880                       # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total        58880                       # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4   4533093127                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total   4533093127                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4   3060147977                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total   3060147977                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4   7593241104                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total   7593241104                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4   7593241104                       # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total   7593241104                       # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4   1402247556                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total   1402247556                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4    894394941                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total    894394941                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   2296642497                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total   2296642497                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.804970                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.804970                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.951227                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.951227                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.856299                       # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total     0.856299                       # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.856299                       # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total     0.856299                       # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 126182.132971                       # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 126182.132971                       # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 133310.737399                       # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 133310.737399                       # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 128961.295924                       # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 128961.295924                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 128961.295924                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 128961.295924                       # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4          inf                       # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu5.num_reads                           99811                       # number of read accesses completed
system.cpu5.num_writes                          54122                       # number of write accesses completed
system.cpu5.num_copies                              0                       # number of copy accesses completed
system.cpu5.l1c.replacements                    22776                       # number of replacements
system.cpu5.l1c.tagsinuse                  391.477551                       # Cycle average of tags in use
system.cpu5.l1c.total_refs                      13322                       # Total number of references to valid blocks.
system.cpu5.l1c.sampled_refs                    23147                       # Sample count of references to valid blocks.
system.cpu5.l1c.avg_refs                     0.575539                       # Average number of references to valid blocks.
system.cpu5.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu5.l1c.occ_blocks::cpu5           391.477551                       # Average occupied blocks per requestor
system.cpu5.l1c.occ_percent::cpu5            0.764605                       # Average percentage of cache occupancy
system.cpu5.l1c.occ_percent::total           0.764605                       # Average percentage of cache occupancy
system.cpu5.l1c.ReadReq_hits::cpu5               8701                       # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total              8701                       # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5              1178                       # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total             1178                       # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5                9879                       # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total               9879                       # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5               9879                       # number of overall hits
system.cpu5.l1c.overall_hits::total              9879                       # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5            36192                       # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total           36192                       # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5           23103                       # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total          23103                       # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5             59295                       # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total            59295                       # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5            59295                       # number of overall misses
system.cpu5.l1c.overall_misses::total           59295                       # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5   4578113743                       # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total   4578113743                       # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5   3131851801                       # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total   3131851801                       # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5   7709965544                       # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total   7709965544                       # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5   7709965544                       # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total   7709965544                       # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5          44893                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total         44893                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5         24281                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total        24281                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5           69174                       # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total          69174                       # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5          69174                       # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total         69174                       # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.806184                       # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total     0.806184                       # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.951485                       # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total     0.951485                       # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5       0.857186                       # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total      0.857186                       # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5      0.857186                       # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total     0.857186                       # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 126495.185207                       # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 126495.185207                       # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 135560.394797                       # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 135560.394797                       # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 130027.245872                       # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 130027.245872                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 130027.245872                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 130027.245872                       # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs    718707273                       # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_mshrs               64475                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_mshrs 11147.068988                       # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu5.l1c.writebacks::writebacks          10068                       # number of writebacks
system.cpu5.l1c.writebacks::total               10068                       # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36192                       # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total        36192                       # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23103                       # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total        23103                       # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5        59295                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total        59295                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5        59295                       # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total        59295                       # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5   4505401434                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total   4505401434                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5   3085574966                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total   3085574966                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5   7590976400                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total   7590976400                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5   7590976400                       # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total   7590976400                       # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5   1396623229                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total   1396623229                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5    970059681                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total    970059681                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   2366682910                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total   2366682910                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.806184                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.806184                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.951485                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.951485                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.857186                       # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total     0.857186                       # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.857186                       # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total     0.857186                       # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 124486.113893                       # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 124486.113893                       # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 133557.328745                       # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 133557.328745                       # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 128020.514377                       # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 128020.514377                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 128020.514377                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 128020.514377                       # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5          inf                       # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu6.num_reads                           96701                       # number of read accesses completed
system.cpu6.num_writes                          52167                       # number of write accesses completed
system.cpu6.num_copies                              0                       # number of copy accesses completed
system.cpu6.l1c.replacements                    21524                       # number of replacements
system.cpu6.l1c.tagsinuse                  387.796217                       # Cycle average of tags in use
system.cpu6.l1c.total_refs                      12859                       # Total number of references to valid blocks.
system.cpu6.l1c.sampled_refs                    21936                       # Sample count of references to valid blocks.
system.cpu6.l1c.avg_refs                     0.586205                       # Average number of references to valid blocks.
system.cpu6.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu6.l1c.occ_blocks::cpu6           387.796217                       # Average occupied blocks per requestor
system.cpu6.l1c.occ_percent::cpu6            0.757414                       # Average percentage of cache occupancy
system.cpu6.l1c.occ_percent::total           0.757414                       # Average percentage of cache occupancy
system.cpu6.l1c.ReadReq_hits::cpu6               8329                       # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total              8329                       # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6              1106                       # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total             1106                       # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6                9435                       # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total               9435                       # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6               9435                       # number of overall hits
system.cpu6.l1c.overall_hits::total              9435                       # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6            35191                       # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total           35191                       # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6           22544                       # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total          22544                       # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6             57735                       # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total            57735                       # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6            57735                       # number of overall misses
system.cpu6.l1c.overall_misses::total           57735                       # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6   4508353371                       # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total   4508353371                       # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6   3154254558                       # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total   3154254558                       # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6   7662607929                       # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total   7662607929                       # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6   7662607929                       # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total   7662607929                       # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6          43520                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total         43520                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6         23650                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total        23650                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6           67170                       # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total          67170                       # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6          67170                       # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total         67170                       # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.808617                       # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total     0.808617                       # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.953235                       # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total     0.953235                       # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6       0.859536                       # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total      0.859536                       # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6      0.859536                       # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total     0.859536                       # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 128110.976414                       # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 128110.976414                       # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 139915.478974                       # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 139915.478974                       # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 132720.324396                       # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 132720.324396                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 132720.324396                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 132720.324396                       # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs    719066693                       # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_mshrs               62816                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_mshrs 11447.190095                       # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu6.l1c.writebacks::writebacks           9499                       # number of writebacks
system.cpu6.l1c.writebacks::total                9499                       # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6        35191                       # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total        35191                       # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6        22544                       # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total        22544                       # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6        57735                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total        57735                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6        57735                       # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total        57735                       # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6   4437636067                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total   4437636067                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6   3109111203                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total   3109111203                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6   7546747270                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total   7546747270                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6   7546747270                       # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total   7546747270                       # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6   1416513847                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total   1416513847                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6    907986926                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total    907986926                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   2324500773                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total   2324500773                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.808617                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.808617                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.953235                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.953235                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.859536                       # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total     0.859536                       # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.859536                       # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total     0.859536                       # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 126101.448296                       # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 126101.448296                       # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 137913.023554                       # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 137913.023554                       # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 130713.557980                       # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 130713.557980                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 130713.557980                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 130713.557980                       # average overall mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6          inf                       # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu7.num_reads                           98233                       # number of read accesses completed
system.cpu7.num_writes                          53134                       # number of write accesses completed
system.cpu7.num_copies                              0                       # number of copy accesses completed
system.cpu7.l1c.replacements                    22239                       # number of replacements
system.cpu7.l1c.tagsinuse                  390.077286                       # Cycle average of tags in use
system.cpu7.l1c.total_refs                      13228                       # Total number of references to valid blocks.
system.cpu7.l1c.sampled_refs                    22658                       # Sample count of references to valid blocks.
system.cpu7.l1c.avg_refs                     0.583811                       # Average number of references to valid blocks.
system.cpu7.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu7.l1c.occ_blocks::cpu7           390.077286                       # Average occupied blocks per requestor
system.cpu7.l1c.occ_percent::cpu7            0.761870                       # Average percentage of cache occupancy
system.cpu7.l1c.occ_percent::total           0.761870                       # Average percentage of cache occupancy
system.cpu7.l1c.ReadReq_hits::cpu7               8637                       # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total              8637                       # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7              1096                       # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total             1096                       # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7                9733                       # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total               9733                       # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7               9733                       # number of overall hits
system.cpu7.l1c.overall_hits::total              9733                       # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7            35699                       # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total           35699                       # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7           22823                       # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total          22823                       # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7             58522                       # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total            58522                       # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7            58522                       # number of overall misses
system.cpu7.l1c.overall_misses::total           58522                       # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7   4580220165                       # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total   4580220165                       # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7   3149286383                       # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total   3149286383                       # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7   7729506548                       # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total   7729506548                       # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7   7729506548                       # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total   7729506548                       # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7          44336                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total         44336                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7         23919                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total        23919                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7           68255                       # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total          68255                       # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7          68255                       # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total         68255                       # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.805192                       # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total     0.805192                       # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.954179                       # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total     0.954179                       # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7       0.857402                       # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total      0.857402                       # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7      0.857402                       # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total     0.857402                       # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 128301.077481                       # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 128301.077481                       # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 137987.397932                       # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 137987.397932                       # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 132078.646458                       # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 132078.646458                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 132078.646458                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 132078.646458                       # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs    716139762                       # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_mshrs               63505                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_mshrs 11276.903582                       # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu7.l1c.writebacks::writebacks           9791                       # number of writebacks
system.cpu7.l1c.writebacks::total                9791                       # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7        35699                       # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total        35699                       # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7        22823                       # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total        22823                       # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7        58522                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total        58522                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7        58522                       # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total        58522                       # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7   4508506825                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total   4508506825                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7   3103586023                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total   3103586023                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7   7612092848                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total   7612092848                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7   7612092848                       # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total   7612092848                       # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7   1364395277                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total   1364395277                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7    924938405                       # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total    924938405                       # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   2289333682                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total   2289333682                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.805192                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.805192                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.954179                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.954179                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.857402                       # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total     0.857402                       # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.857402                       # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total     0.857402                       # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 126292.244181                       # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 126292.244181                       # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 135985.016124                       # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 135985.016124                       # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 130072.329175                       # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 130072.329175                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 130072.329175                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 130072.329175                       # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average WriteReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------