path: root/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000520                       # Number of seconds simulated
sim_ticks                                   519755500                       # Number of ticks simulated
final_tick                                  519755500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_tick_rate                               97602781                       # Simulator tick rate (ticks/s)
host_mem_usage                                 236356                       # Number of bytes of host memory used
host_seconds                                     5.33                       # Real time elapsed on the host
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0                252685                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1                258147                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2                248443                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3                257431                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu4                256206                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu5                249786                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu6                257817                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu7                255503                       # Number of bytes read from this memory
system.physmem.bytes_read::total              2036018                       # Number of bytes read from this memory
system.physmem.bytes_written::writebacks      1421696                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0               5545                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1               5403                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu2               5468                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu3               5504                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu4               5430                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu5               5362                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu6               5562                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu7               5554                       # Number of bytes written to this memory
system.physmem.bytes_written::total           1465524                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0                  13663                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1                  13833                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2                  13579                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3                  13621                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4                  13782                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5                  13599                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6                  13692                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7                  13646                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                109415                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           22214                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0                  5545                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1                  5403                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2                  5468                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3                  5504                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4                  5430                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5                  5362                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6                  5562                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7                  5554                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66042                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0                486161282                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1                496670069                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2                477999752                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3                495292498                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4                492935621                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5                480583659                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6                496035155                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7                491583062                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              3917261097                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks        2735316894                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0                10668478                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1                10395272                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2                10520331                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3                10589595                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4                10447220                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5                10316389                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6                10701185                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7                10685794                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total             2819641158                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks        2735316894                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0               496829759                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1               507065341                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2               488520083                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3               505882093                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4               503382841                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5               490900048                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6               506736340                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7               502268855                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             6736902255                       # Total bandwidth to/from this memory (bytes/s)
system.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu0.num_reads                           99523                       # number of read accesses completed
system.cpu0.num_writes                          55175                       # number of write accesses completed
system.cpu0.l1c.tags.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu0.l1c.tags.replacements               22190                       # number of replacements
system.cpu0.l1c.tags.tagsinuse             391.732266                       # Cycle average of tags in use
system.cpu0.l1c.tags.total_refs                 13637                       # Total number of references to valid blocks.
system.cpu0.l1c.tags.sampled_refs               22577                       # Sample count of references to valid blocks.
system.cpu0.l1c.tags.avg_refs                0.604022                       # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu0.l1c.tags.occ_blocks::cpu0      391.732266                       # Average occupied blocks per requestor
system.cpu0.l1c.tags.occ_percent::cpu0       0.765102                       # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_percent::total      0.765102                       # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_task_id_blocks::1024          387                       # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::0          377                       # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
system.cpu0.l1c.tags.occ_task_id_percent::1024     0.755859                       # Percentage of cache occupancy per task id
system.cpu0.l1c.tags.tag_accesses              338094                       # Number of tag accesses
system.cpu0.l1c.tags.data_accesses             338094                       # Number of data accesses
system.cpu0.l1c.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu0.l1c.ReadReq_hits::cpu0               8745                       # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total              8745                       # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0              1203                       # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total             1203                       # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0                9948                       # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total               9948                       # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0               9948                       # number of overall hits
system.cpu0.l1c.overall_hits::total              9948                       # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0            36338                       # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total           36338                       # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0           24073                       # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total          24073                       # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0             60411                       # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total            60411                       # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0            60411                       # number of overall misses
system.cpu0.l1c.overall_misses::total           60411                       # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0    720327390                       # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total    720327390                       # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0    585363499                       # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total    585363499                       # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0   1305690889                       # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total   1305690889                       # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0   1305690889                       # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total   1305690889                       # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0          45083                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total         45083                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0         25276                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total        25276                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0           70359                       # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total          70359                       # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0          70359                       # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total         70359                       # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.806024                       # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total     0.806024                       # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.952405                       # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total     0.952405                       # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0       0.858611                       # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total      0.858611                       # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0      0.858611                       # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total     0.858611                       # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 19822.978425                       # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 19822.978425                       # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 24316.184065                       # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 24316.184065                       # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 21613.462598                       # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 21613.462598                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 21613.462598                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 21613.462598                       # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs       881814                       # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_mshrs               67116                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_mshrs    13.138655                       # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l1c.writebacks::writebacks           9797                       # number of writebacks
system.cpu0.l1c.writebacks::total                9797                       # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36338                       # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total        36338                       # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0        24073                       # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total        24073                       # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0        60411                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total        60411                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0        60411                       # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total        60411                       # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0         9869                       # number of ReadReq MSHR uncacheable
system.cpu0.l1c.ReadReq_mshr_uncacheable::total         9869                       # number of ReadReq MSHR uncacheable
system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0         5547                       # number of WriteReq MSHR uncacheable
system.cpu0.l1c.WriteReq_mshr_uncacheable::total         5547                       # number of WriteReq MSHR uncacheable
system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0        15416                       # number of overall MSHR uncacheable misses
system.cpu0.l1c.overall_mshr_uncacheable_misses::total        15416                       # number of overall MSHR uncacheable misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    683989390                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total    683989390                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    561290499                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total    561290499                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1245279889                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total   1245279889                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1245279889                       # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total   1245279889                       # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    771084187                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    771084187                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0    771084187                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total    771084187                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.806024                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.806024                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.952405                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.952405                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.858611                       # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total     0.858611                       # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.858611                       # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total     0.858611                       # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 18822.978425                       # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 18822.978425                       # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 23316.184065                       # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 23316.184065                       # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20613.462598                       # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20613.462598                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20613.462598                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20613.462598                       # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 78131.947208                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78131.947208                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 50018.434549                       # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 50018.434549                       # average overall mshr uncacheable latency
system.cpu1.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu1.num_reads                           99560                       # number of read accesses completed
system.cpu1.num_writes                          54738                       # number of write accesses completed
system.cpu1.l1c.tags.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu1.l1c.tags.replacements               22160                       # number of replacements
system.cpu1.l1c.tags.tagsinuse             392.166928                       # Cycle average of tags in use
system.cpu1.l1c.tags.total_refs                 13521                       # Total number of references to valid blocks.
system.cpu1.l1c.tags.sampled_refs               22561                       # Sample count of references to valid blocks.
system.cpu1.l1c.tags.avg_refs                0.599309                       # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu1.l1c.tags.occ_blocks::cpu1      392.166928                       # Average occupied blocks per requestor
system.cpu1.l1c.tags.occ_percent::cpu1       0.765951                       # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_percent::total      0.765951                       # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_task_id_blocks::1024          401                       # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::0          386                       # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::1           15                       # Occupied blocks per task id
system.cpu1.l1c.tags.occ_task_id_percent::1024     0.783203                       # Percentage of cache occupancy per task id
system.cpu1.l1c.tags.tag_accesses              337076                       # Number of tag accesses
system.cpu1.l1c.tags.data_accesses             337076                       # Number of data accesses
system.cpu1.l1c.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu1.l1c.ReadReq_hits::cpu1               8807                       # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total              8807                       # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1              1218                       # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total             1218                       # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1               10025                       # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total              10025                       # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1              10025                       # number of overall hits
system.cpu1.l1c.overall_hits::total             10025                       # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1            36399                       # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total           36399                       # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1           23708                       # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total          23708                       # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1             60107                       # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total            60107                       # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1            60107                       # number of overall misses
system.cpu1.l1c.overall_misses::total           60107                       # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1    728138208                       # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total    728138208                       # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1    572668423                       # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total    572668423                       # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1   1300806631                       # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total   1300806631                       # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1   1300806631                       # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total   1300806631                       # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1          45206                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total         45206                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1         24926                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total        24926                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1           70132                       # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total          70132                       # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1          70132                       # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total         70132                       # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.805181                       # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total     0.805181                       # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.951135                       # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total     0.951135                       # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1       0.857055                       # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total      0.857055                       # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1      0.857055                       # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total     0.857055                       # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 20004.346493                       # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 20004.346493                       # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 24155.070989                       # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 24155.070989                       # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 21641.516479                       # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 21641.516479                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 21641.516479                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 21641.516479                       # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs       883013                       # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_mshrs               66936                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_mshrs    13.191900                       # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l1c.writebacks::writebacks           9595                       # number of writebacks
system.cpu1.l1c.writebacks::total                9595                       # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36399                       # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total        36399                       # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23708                       # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total        23708                       # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1        60107                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total        60107                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1        60107                       # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total        60107                       # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1         9955                       # number of ReadReq MSHR uncacheable
system.cpu1.l1c.ReadReq_mshr_uncacheable::total         9955                       # number of ReadReq MSHR uncacheable
system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1         5404                       # number of WriteReq MSHR uncacheable
system.cpu1.l1c.WriteReq_mshr_uncacheable::total         5404                       # number of WriteReq MSHR uncacheable
system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1        15359                       # number of overall MSHR uncacheable misses
system.cpu1.l1c.overall_mshr_uncacheable_misses::total        15359                       # number of overall MSHR uncacheable misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    691742208                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total    691742208                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    548961423                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total    548961423                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1240703631                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total   1240703631                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1240703631                       # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total   1240703631                       # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    776683501                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    776683501                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1    776683501                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total    776683501                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.805181                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.805181                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.951135                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.951135                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.857055                       # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total     0.857055                       # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.857055                       # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total     0.857055                       # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 19004.428913                       # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 19004.428913                       # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 23155.113169                       # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 23155.113169                       # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20641.583027                       # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20641.583027                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20641.583027                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20641.583027                       # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 78019.437569                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78019.437569                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 50568.624325                       # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 50568.624325                       # average overall mshr uncacheable latency
system.cpu2.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu2.num_reads                           98983                       # number of read accesses completed
system.cpu2.num_writes                          55204                       # number of write accesses completed
system.cpu2.l1c.tags.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu2.l1c.tags.replacements               22113                       # number of replacements
system.cpu2.l1c.tags.tagsinuse             391.892697                       # Cycle average of tags in use
system.cpu2.l1c.tags.total_refs                 13532                       # Total number of references to valid blocks.
system.cpu2.l1c.tags.sampled_refs               22515                       # Sample count of references to valid blocks.
system.cpu2.l1c.tags.avg_refs                0.601022                       # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu2.l1c.tags.occ_blocks::cpu2      391.892697                       # Average occupied blocks per requestor
system.cpu2.l1c.tags.occ_percent::cpu2       0.765415                       # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_percent::total      0.765415                       # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::0          395                       # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
system.cpu2.l1c.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
system.cpu2.l1c.tags.tag_accesses              337818                       # Number of tag accesses
system.cpu2.l1c.tags.data_accesses             337818                       # Number of data accesses
system.cpu2.l1c.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu2.l1c.ReadReq_hits::cpu2               8790                       # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total              8790                       # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2              1144                       # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total             1144                       # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2                9934                       # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total               9934                       # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2               9934                       # number of overall hits
system.cpu2.l1c.overall_hits::total              9934                       # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2            36176                       # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total           36176                       # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2           24169                       # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total          24169                       # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2             60345                       # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total            60345                       # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2            60345                       # number of overall misses
system.cpu2.l1c.overall_misses::total           60345                       # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2    716181593                       # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total    716181593                       # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2    589266088                       # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total    589266088                       # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2   1305447681                       # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total   1305447681                       # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2   1305447681                       # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total   1305447681                       # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2          44966                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total         44966                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2         25313                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total        25313                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2           70279                       # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total          70279                       # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2          70279                       # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total         70279                       # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.804519                       # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total     0.804519                       # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.954806                       # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total     0.954806                       # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2       0.858649                       # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total      0.858649                       # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2      0.858649                       # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total     0.858649                       # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 19797.147086                       # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 19797.147086                       # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 24381.070297                       # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 24381.070297                       # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 21633.071191                       # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 21633.071191                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 21633.071191                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 21633.071191                       # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs       879879                       # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_mshrs               66865                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_mshrs    13.159037                       # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.l1c.writebacks::writebacks           9745                       # number of writebacks
system.cpu2.l1c.writebacks::total                9745                       # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36176                       # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total        36176                       # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2        24169                       # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total        24169                       # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2        60345                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total        60345                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2        60345                       # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total        60345                       # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2         9851                       # number of ReadReq MSHR uncacheable
system.cpu2.l1c.ReadReq_mshr_uncacheable::total         9851                       # number of ReadReq MSHR uncacheable
system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2         5469                       # number of WriteReq MSHR uncacheable
system.cpu2.l1c.WriteReq_mshr_uncacheable::total         5469                       # number of WriteReq MSHR uncacheable
system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2        15320                       # number of overall MSHR uncacheable misses
system.cpu2.l1c.overall_mshr_uncacheable_misses::total        15320                       # number of overall MSHR uncacheable misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    680005593                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total    680005593                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    565098088                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total    565098088                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1245103681                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total   1245103681                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1245103681                       # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total   1245103681                       # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    769729433                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    769729433                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2    769729433                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total    769729433                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.804519                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.804519                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.954806                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.954806                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.858649                       # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total     0.858649                       # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.858649                       # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total     0.858649                       # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 18797.147086                       # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 18797.147086                       # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 23381.111672                       # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 23381.111672                       # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20633.087762                       # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20633.087762                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20633.087762                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20633.087762                       # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 78137.187392                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78137.187392                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 50243.435574                       # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 50243.435574                       # average overall mshr uncacheable latency
system.cpu3.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu3.num_reads                          100000                       # number of read accesses completed
system.cpu3.num_writes                          55136                       # number of write accesses completed
system.cpu3.l1c.tags.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu3.l1c.tags.replacements               22201                       # number of replacements
system.cpu3.l1c.tags.tagsinuse             392.334218                       # Cycle average of tags in use
system.cpu3.l1c.tags.total_refs                 13633                       # Total number of references to valid blocks.
system.cpu3.l1c.tags.sampled_refs               22606                       # Sample count of references to valid blocks.
system.cpu3.l1c.tags.avg_refs                0.603070                       # Average number of references to valid blocks.
system.cpu3.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu3.l1c.tags.occ_blocks::cpu3      392.334218                       # Average occupied blocks per requestor
system.cpu3.l1c.tags.occ_percent::cpu3       0.766278                       # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_percent::total      0.766278                       # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_task_id_blocks::1024          405                       # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::0          397                       # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
system.cpu3.l1c.tags.occ_task_id_percent::1024     0.791016                       # Percentage of cache occupancy per task id
system.cpu3.l1c.tags.tag_accesses              339332                       # Number of tag accesses
system.cpu3.l1c.tags.data_accesses             339332                       # Number of data accesses
system.cpu3.l1c.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu3.l1c.ReadReq_hits::cpu3               8805                       # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total              8805                       # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3              1190                       # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total             1190                       # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3                9995                       # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total               9995                       # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3               9995                       # number of overall hits
system.cpu3.l1c.overall_hits::total              9995                       # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3            36852                       # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total           36852                       # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3           23757                       # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total          23757                       # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3             60609                       # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total            60609                       # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3            60609                       # number of overall misses
system.cpu3.l1c.overall_misses::total           60609                       # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3    737200497                       # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total    737200497                       # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3    577684792                       # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total    577684792                       # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3   1314885289                       # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total   1314885289                       # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3   1314885289                       # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total   1314885289                       # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3          45657                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total         45657                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3         24947                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total        24947                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3           70604                       # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total          70604                       # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3          70604                       # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total         70604                       # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.807149                       # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total     0.807149                       # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.952299                       # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total     0.952299                       # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3       0.858436                       # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total      0.858436                       # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3      0.858436                       # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total     0.858436                       # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 20004.355177                       # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 20004.355177                       # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 24316.403250                       # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 24316.403250                       # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 21694.555083                       # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 21694.555083                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 21694.555083                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 21694.555083                       # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs       880663                       # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_mshrs               67164                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_mshrs    13.112129                       # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.l1c.writebacks::writebacks           9556                       # number of writebacks
system.cpu3.l1c.writebacks::total                9556                       # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36852                       # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total        36852                       # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23757                       # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total        23757                       # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3        60609                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total        60609                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3        60609                       # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total        60609                       # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3         9752                       # number of ReadReq MSHR uncacheable
system.cpu3.l1c.ReadReq_mshr_uncacheable::total         9752                       # number of ReadReq MSHR uncacheable
system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3         5506                       # number of WriteReq MSHR uncacheable
system.cpu3.l1c.WriteReq_mshr_uncacheable::total         5506                       # number of WriteReq MSHR uncacheable
system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3        15258                       # number of overall MSHR uncacheable misses
system.cpu3.l1c.overall_mshr_uncacheable_misses::total        15258                       # number of overall MSHR uncacheable misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    700349497                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total    700349497                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    553928792                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total    553928792                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1254278289                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total   1254278289                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1254278289                       # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total   1254278289                       # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    761853080                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    761853080                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3    761853080                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total    761853080                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.807149                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.807149                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.952299                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.952299                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.858436                       # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total     0.858436                       # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.858436                       # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total     0.858436                       # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 19004.382313                       # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 19004.382313                       # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 23316.445342                       # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 23316.445342                       # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20694.588081                       # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20694.588081                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20694.588081                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20694.588081                       # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 78122.752256                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78122.752256                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 49931.385503                       # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 49931.385503                       # average overall mshr uncacheable latency
system.cpu4.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu4.num_reads                           99808                       # number of read accesses completed
system.cpu4.num_writes                          55157                       # number of write accesses completed
system.cpu4.l1c.tags.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu4.l1c.tags.replacements               22030                       # number of replacements
system.cpu4.l1c.tags.tagsinuse             392.026241                       # Cycle average of tags in use
system.cpu4.l1c.tags.total_refs                 13726                       # Total number of references to valid blocks.
system.cpu4.l1c.tags.sampled_refs               22418                       # Sample count of references to valid blocks.
system.cpu4.l1c.tags.avg_refs                0.612276                       # Average number of references to valid blocks.
system.cpu4.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu4.l1c.tags.occ_blocks::cpu4      392.026241                       # Average occupied blocks per requestor
system.cpu4.l1c.tags.occ_percent::cpu4       0.765676                       # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_percent::total      0.765676                       # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_task_id_blocks::1024          388                       # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::0          372                       # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::1           16                       # Occupied blocks per task id
system.cpu4.l1c.tags.occ_task_id_percent::1024     0.757812                       # Percentage of cache occupancy per task id
system.cpu4.l1c.tags.tag_accesses              338084                       # Number of tag accesses
system.cpu4.l1c.tags.data_accesses             338084                       # Number of data accesses
system.cpu4.l1c.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu4.l1c.ReadReq_hits::cpu4               8869                       # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total              8869                       # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4              1181                       # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total             1181                       # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4               10050                       # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total              10050                       # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4              10050                       # number of overall hits
system.cpu4.l1c.overall_hits::total             10050                       # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4            36458                       # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total           36458                       # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4           23868                       # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total          23868                       # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4             60326                       # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total            60326                       # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4            60326                       # number of overall misses
system.cpu4.l1c.overall_misses::total           60326                       # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4    723342269                       # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total    723342269                       # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4    578669341                       # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total    578669341                       # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4   1302011610                       # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total   1302011610                       # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4   1302011610                       # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total   1302011610                       # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4          45327                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total         45327                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4         25049                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total        25049                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4           70376                       # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total          70376                       # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4          70376                       # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total         70376                       # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.804333                       # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total     0.804333                       # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.952852                       # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total     0.952852                       # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4       0.857196                       # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total      0.857196                       # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4      0.857196                       # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total     0.857196                       # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 19840.426491                       # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 19840.426491                       # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 24244.567664                       # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 24244.567664                       # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 21582.926267                       # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 21582.926267                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 21582.926267                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 21582.926267                       # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs       883463                       # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_mshrs               67109                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_mshrs    13.164598                       # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu4.l1c.writebacks::writebacks           9613                       # number of writebacks
system.cpu4.l1c.writebacks::total                9613                       # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36458                       # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total        36458                       # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23868                       # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total        23868                       # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4        60326                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total        60326                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4        60326                       # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total        60326                       # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4         9934                       # number of ReadReq MSHR uncacheable
system.cpu4.l1c.ReadReq_mshr_uncacheable::total         9934                       # number of ReadReq MSHR uncacheable
system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4         5430                       # number of WriteReq MSHR uncacheable
system.cpu4.l1c.WriteReq_mshr_uncacheable::total         5430                       # number of WriteReq MSHR uncacheable
system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4        15364                       # number of overall MSHR uncacheable misses
system.cpu4.l1c.overall_mshr_uncacheable_misses::total        15364                       # number of overall MSHR uncacheable misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    686885269                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total    686885269                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    554802341                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total    554802341                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1241687610                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total   1241687610                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1241687610                       # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total   1241687610                       # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    775754665                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    775754665                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4    775754665                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total    775754665                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.804333                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.804333                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.952852                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.952852                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.857196                       # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total     0.857196                       # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.857196                       # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total     0.857196                       # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 18840.453920                       # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 18840.453920                       # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 23244.609561                       # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 23244.609561                       # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20582.959420                       # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20582.959420                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20582.959420                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20582.959420                       # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 78090.866217                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78090.866217                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 50491.712119                       # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 50491.712119                       # average overall mshr uncacheable latency
system.cpu5.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu5.num_reads                           99404                       # number of read accesses completed
system.cpu5.num_writes                          55162                       # number of write accesses completed
system.cpu5.l1c.tags.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu5.l1c.tags.replacements               22439                       # number of replacements
system.cpu5.l1c.tags.tagsinuse             391.788419                       # Cycle average of tags in use
system.cpu5.l1c.tags.total_refs                 13514                       # Total number of references to valid blocks.
system.cpu5.l1c.tags.sampled_refs               22846                       # Sample count of references to valid blocks.
system.cpu5.l1c.tags.avg_refs                0.591526                       # Average number of references to valid blocks.
system.cpu5.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu5.l1c.tags.occ_blocks::cpu5      391.788419                       # Average occupied blocks per requestor
system.cpu5.l1c.tags.occ_percent::cpu5       0.765212                       # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_percent::total      0.765212                       # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_task_id_blocks::1024          407                       # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::0          401                       # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
system.cpu5.l1c.tags.occ_task_id_percent::1024     0.794922                       # Percentage of cache occupancy per task id
system.cpu5.l1c.tags.tag_accesses              338295                       # Number of tag accesses
system.cpu5.l1c.tags.data_accesses             338295                       # Number of data accesses
system.cpu5.l1c.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu5.l1c.ReadReq_hits::cpu5               8686                       # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total              8686                       # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5              1223                       # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total             1223                       # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5                9909                       # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total               9909                       # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5               9909                       # number of overall hits
system.cpu5.l1c.overall_hits::total              9909                       # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5            36676                       # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total           36676                       # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5           23788                       # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total          23788                       # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5             60464                       # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total            60464                       # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5            60464                       # number of overall misses
system.cpu5.l1c.overall_misses::total           60464                       # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5    728782621                       # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total    728782621                       # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5    575848202                       # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total    575848202                       # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5   1304630823                       # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total   1304630823                       # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5   1304630823                       # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total   1304630823                       # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5          45362                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total         45362                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5         25011                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total        25011                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5           70373                       # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total          70373                       # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5          70373                       # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total         70373                       # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.808518                       # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total     0.808518                       # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.951102                       # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total     0.951102                       # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5       0.859193                       # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total      0.859193                       # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5      0.859193                       # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total     0.859193                       # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 19870.831634                       # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 19870.831634                       # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 24207.508071                       # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 24207.508071                       # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 21576.985032                       # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 21576.985032                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 21576.985032                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 21576.985032                       # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs       880240                       # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_mshrs               67028                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_mshrs    13.132422                       # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu5.l1c.writebacks::writebacks           9753                       # number of writebacks
system.cpu5.l1c.writebacks::total                9753                       # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36676                       # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total        36676                       # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23788                       # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total        23788                       # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5        60464                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total        60464                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5        60464                       # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total        60464                       # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5         9850                       # number of ReadReq MSHR uncacheable
system.cpu5.l1c.ReadReq_mshr_uncacheable::total         9850                       # number of ReadReq MSHR uncacheable
system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5         5362                       # number of WriteReq MSHR uncacheable
system.cpu5.l1c.WriteReq_mshr_uncacheable::total         5362                       # number of WriteReq MSHR uncacheable
system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5        15212                       # number of overall MSHR uncacheable misses
system.cpu5.l1c.overall_mshr_uncacheable_misses::total        15212                       # number of overall MSHR uncacheable misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    692108621                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total    692108621                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    552061202                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total    552061202                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1244169823                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total   1244169823                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1244169823                       # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total   1244169823                       # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    771042075                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    771042075                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5    771042075                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total    771042075                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.808518                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.808518                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.951102                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.951102                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.859193                       # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total     0.859193                       # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.859193                       # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total     0.859193                       # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 18870.886165                       # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 18870.886165                       # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 23207.550109                       # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 23207.550109                       # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20577.034649                       # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20577.034649                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20577.034649                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20577.034649                       # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 78278.383249                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78278.383249                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 50686.436695                       # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 50686.436695                       # average overall mshr uncacheable latency
system.cpu6.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu6.num_reads                           99584                       # number of read accesses completed
system.cpu6.num_writes                          55158                       # number of write accesses completed
system.cpu6.l1c.tags.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu6.l1c.tags.replacements               22137                       # number of replacements
system.cpu6.l1c.tags.tagsinuse             391.593819                       # Cycle average of tags in use
system.cpu6.l1c.tags.total_refs                 13609                       # Total number of references to valid blocks.
system.cpu6.l1c.tags.sampled_refs               22548                       # Sample count of references to valid blocks.
system.cpu6.l1c.tags.avg_refs                0.603557                       # Average number of references to valid blocks.
system.cpu6.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu6.l1c.tags.occ_blocks::cpu6      391.593819                       # Average occupied blocks per requestor
system.cpu6.l1c.tags.occ_percent::cpu6       0.764832                       # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_percent::total      0.764832                       # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_task_id_blocks::1024          411                       # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::0          399                       # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::1           12                       # Occupied blocks per task id
system.cpu6.l1c.tags.occ_task_id_percent::1024     0.802734                       # Percentage of cache occupancy per task id
system.cpu6.l1c.tags.tag_accesses              338403                       # Number of tag accesses
system.cpu6.l1c.tags.data_accesses             338403                       # Number of data accesses
system.cpu6.l1c.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu6.l1c.ReadReq_hits::cpu6               8781                       # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total              8781                       # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6              1188                       # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total             1188                       # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6                9969                       # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total               9969                       # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6               9969                       # number of overall hits
system.cpu6.l1c.overall_hits::total              9969                       # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6            36497                       # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total           36497                       # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6           23948                       # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total          23948                       # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6             60445                       # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total            60445                       # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6            60445                       # number of overall misses
system.cpu6.l1c.overall_misses::total           60445                       # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6    730258004                       # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total    730258004                       # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6    580007386                       # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total    580007386                       # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6   1310265390                       # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total   1310265390                       # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6   1310265390                       # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total   1310265390                       # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6          45278                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total         45278                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6         25136                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total        25136                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6           70414                       # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total          70414                       # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6          70414                       # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total         70414                       # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.806065                       # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total     0.806065                       # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.952737                       # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total     0.952737                       # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6       0.858423                       # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total      0.858423                       # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6      0.858423                       # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total     0.858423                       # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 20008.713155                       # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 20008.713155                       # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 24219.449891                       # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 24219.449891                       # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 21676.985524                       # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 21676.985524                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 21676.985524                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 21676.985524                       # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs       882368                       # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_mshrs               67127                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_mshrs    13.144755                       # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu6.l1c.writebacks::writebacks           9587                       # number of writebacks
system.cpu6.l1c.writebacks::total                9587                       # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36497                       # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total        36497                       # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23948                       # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total        23948                       # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6        60445                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total        60445                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6        60445                       # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total        60445                       # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6         9817                       # number of ReadReq MSHR uncacheable
system.cpu6.l1c.ReadReq_mshr_uncacheable::total         9817                       # number of ReadReq MSHR uncacheable
system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6         5564                       # number of WriteReq MSHR uncacheable
system.cpu6.l1c.WriteReq_mshr_uncacheable::total         5564                       # number of WriteReq MSHR uncacheable
system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6        15381                       # number of overall MSHR uncacheable misses
system.cpu6.l1c.overall_mshr_uncacheable_misses::total        15381                       # number of overall MSHR uncacheable misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    693763004                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total    693763004                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    556061386                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total    556061386                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1249824390                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total   1249824390                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1249824390                       # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total   1249824390                       # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    767059984                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    767059984                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6    767059984                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total    767059984                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.806065                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.806065                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.952737                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.952737                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.858423                       # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total     0.858423                       # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.858423                       # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total     0.858423                       # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 19008.767954                       # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 19008.767954                       # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 23219.533406                       # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 23219.533406                       # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20677.051700                       # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20677.051700                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20677.051700                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20677.051700                       # average overall mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 78135.885097                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78135.885097                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 49870.618555                       # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 49870.618555                       # average overall mshr uncacheable latency
system.cpu7.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu7.num_reads                           98890                       # number of read accesses completed
system.cpu7.num_writes                          55602                       # number of write accesses completed
system.cpu7.l1c.tags.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu7.l1c.tags.replacements               22121                       # number of replacements
system.cpu7.l1c.tags.tagsinuse             391.886114                       # Cycle average of tags in use
system.cpu7.l1c.tags.total_refs                 13491                       # Total number of references to valid blocks.
system.cpu7.l1c.tags.sampled_refs               22504                       # Sample count of references to valid blocks.
system.cpu7.l1c.tags.avg_refs                0.599493                       # Average number of references to valid blocks.
system.cpu7.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu7.l1c.tags.occ_blocks::cpu7      391.886114                       # Average occupied blocks per requestor
system.cpu7.l1c.tags.occ_percent::cpu7       0.765403                       # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_percent::total      0.765403                       # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_task_id_blocks::1024          383                       # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::0          374                       # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::1            9                       # Occupied blocks per task id
system.cpu7.l1c.tags.occ_task_id_percent::1024     0.748047                       # Percentage of cache occupancy per task id
system.cpu7.l1c.tags.tag_accesses              336547                       # Number of tag accesses
system.cpu7.l1c.tags.data_accesses             336547                       # Number of data accesses
system.cpu7.l1c.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.cpu7.l1c.ReadReq_hits::cpu7               8615                       # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total              8615                       # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7              1223                       # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total             1223                       # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7                9838                       # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total               9838                       # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7               9838                       # number of overall hits
system.cpu7.l1c.overall_hits::total              9838                       # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7            36077                       # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total           36077                       # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7           24110                       # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total          24110                       # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7             60187                       # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total            60187                       # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7            60187                       # number of overall misses
system.cpu7.l1c.overall_misses::total           60187                       # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7    719876948                       # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total    719876948                       # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7    591584960                       # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total    591584960                       # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7   1311461908                       # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total   1311461908                       # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7   1311461908                       # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total   1311461908                       # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7          44692                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total         44692                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7         25333                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total        25333                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7           70025                       # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total          70025                       # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7          70025                       # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total         70025                       # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.807236                       # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total     0.807236                       # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.951723                       # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total     0.951723                       # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7       0.859507                       # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total      0.859507                       # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7      0.859507                       # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total     0.859507                       # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 19953.902708                       # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 19953.902708                       # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 24536.912484                       # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 24536.912484                       # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 21789.786964                       # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 21789.786964                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 21789.786964                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 21789.786964                       # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs       881767                       # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_mshrs               66704                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_mshrs    13.219102                       # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu7.l1c.writebacks::writebacks           9764                       # number of writebacks
system.cpu7.l1c.writebacks::total                9764                       # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36077                       # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total        36077                       # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7        24110                       # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total        24110                       # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7        60187                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total        60187                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7        60187                       # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total        60187                       # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7         9808                       # number of ReadReq MSHR uncacheable
system.cpu7.l1c.ReadReq_mshr_uncacheable::total         9808                       # number of ReadReq MSHR uncacheable
system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7         5554                       # number of WriteReq MSHR uncacheable
system.cpu7.l1c.WriteReq_mshr_uncacheable::total         5554                       # number of WriteReq MSHR uncacheable
system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7        15362                       # number of overall MSHR uncacheable misses
system.cpu7.l1c.overall_mshr_uncacheable_misses::total        15362                       # number of overall MSHR uncacheable misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    683799948                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total    683799948                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    567476960                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total    567476960                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1251276908                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total   1251276908                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1251276908                       # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total   1251276908                       # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    764550984                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    764550984                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7    764550984                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total    764550984                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.807236                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.807236                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.951723                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.951723                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.859507                       # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total     0.859507                       # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.859507                       # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total     0.859507                       # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 18953.902708                       # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 18953.902708                       # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 23536.995438                       # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 23536.995438                       # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20789.820194                       # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20789.820194                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20789.820194                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20789.820194                       # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 77951.772431                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 77951.772431                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 49768.974352                       # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 49768.974352                       # average overall mshr uncacheable latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                    90719                       # number of replacements
system.l2c.tags.tagsinuse                 1018.150991                       # Cycle average of tags in use
system.l2c.tags.total_refs                     149983                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                    91743                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     1.634817                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                  9046000                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks     702.470265                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0            39.119320                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1            40.193520                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2            38.067708                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3            40.504400                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu4            39.836129                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu5            39.104490                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu6            39.067369                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu7            39.787790                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.686006                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0            0.038202                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1            0.039251                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2            0.037175                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3            0.039555                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu4            0.038902                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu5            0.038188                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu6            0.038152                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu7            0.038855                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.994288                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024         1024                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          929                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           95                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  2127679                       # Number of tag accesses
system.l2c.tags.data_accesses                 2127679                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks        76258                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total           76258                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0                  455                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1                  421                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2                  452                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3                  407                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4                  451                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5                  439                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6                  454                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7                  475                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                3554                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0                  1826                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1                  1861                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2                  1960                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3                  1829                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4                  1871                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5                  1808                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6                  1856                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7                  1881                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                14892                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0              9343                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1              9296                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2              9301                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3              9456                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu4              9362                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu5              9172                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu6              9284                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu7              9134                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total            74348                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0                    11169                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1                    11157                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2                    11261                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3                    11285                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu4                    11233                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu5                    10980                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu6                    11140                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu7                    11015                       # number of demand (read+write) hits
system.l2c.demand_hits::total                   89240                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0                   11169                       # number of overall hits
system.l2c.overall_hits::cpu1                   11157                       # number of overall hits
system.l2c.overall_hits::cpu2                   11261                       # number of overall hits
system.l2c.overall_hits::cpu3                   11285                       # number of overall hits
system.l2c.overall_hits::cpu4                   11233                       # number of overall hits
system.l2c.overall_hits::cpu5                   10980                       # number of overall hits
system.l2c.overall_hits::cpu6                   11140                       # number of overall hits
system.l2c.overall_hits::cpu7                   11015                       # number of overall hits
system.l2c.overall_hits::total                  89240                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0               1925                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1               1836                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2               1914                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3               1906                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4               1942                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5               1877                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6               1898                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7               1911                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             15209                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0                4693                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1                4629                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2                4644                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3                4614                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4                4607                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5                4628                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6                4562                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7                4784                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              37161                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0            2455                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1            2583                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2            2376                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3            2554                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu4            2482                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu5            2499                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu6            2567                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu7            2497                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          20013                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0                   7148                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1                   7212                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2                   7020                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3                   7168                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu4                   7089                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu5                   7127                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu6                   7129                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu7                   7281                       # number of demand (read+write) misses
system.l2c.demand_misses::total                 57174                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0                  7148                       # number of overall misses
system.l2c.overall_misses::cpu1                  7212                       # number of overall misses
system.l2c.overall_misses::cpu2                  7020                       # number of overall misses
system.l2c.overall_misses::cpu3                  7168                       # number of overall misses
system.l2c.overall_misses::cpu4                  7089                       # number of overall misses
system.l2c.overall_misses::cpu5                  7127                       # number of overall misses
system.l2c.overall_misses::cpu6                  7129                       # number of overall misses
system.l2c.overall_misses::cpu7                  7281                       # number of overall misses
system.l2c.overall_misses::total                57174                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0     32240808                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1     31334307                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2     31443971                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3     32481798                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4     31939294                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5     32487949                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6     32438947                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7     31458982                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    255826056                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0     205522581                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1     201589053                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2     204096506                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3     201630443                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4     202953396                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5     200092863                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6     200475342                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7     208573158                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1624933342                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0    170016591                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1    178762923                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2    164403073                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3    176363992                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu4    171439292                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu5    173166429                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu6    177285527                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu7    173293048                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total   1384730875                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0        375539172                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1        380351976                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2        368499579                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3        377994435                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4        374392688                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5        373259292                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6        377760869                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7        381866206                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      3009664217                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0       375539172                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1       380351976                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2       368499579                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3       377994435                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4       374392688                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5       373259292                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6       377760869                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7       381866206                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     3009664217                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks        76258                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total        76258                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0             2380                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1             2257                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2             2366                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3             2313                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4             2393                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5             2316                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6             2352                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7             2386                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           18763                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0              6519                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1              6490                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2              6604                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3              6443                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4              6478                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5              6436                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6              6418                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7              6665                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            52053                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0         11798                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1         11879                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2         11677                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3         12010                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu4         11844                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu5         11671                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu6         11851                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu7         11631                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total        94361                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0                18317                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1                18369                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2                18281                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3                18453                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4                18322                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5                18107                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6                18269                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7                18296                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              146414                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0               18317                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1               18369                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2               18281                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3               18453                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4               18322                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5               18107                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6               18269                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7               18296                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             146414                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0        0.808824                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1        0.813469                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2        0.808960                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3        0.824038                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4        0.811534                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5        0.810449                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6        0.806973                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7        0.800922                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.810585                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0         0.719896                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1         0.713251                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2         0.703210                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3         0.716126                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4         0.711176                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5         0.719080                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6         0.710813                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7         0.717779                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.713907                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0     0.208086                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1     0.217443                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2     0.203477                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3     0.212656                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu4     0.209558                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu5     0.214120                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu6     0.216606                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu7     0.214685                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.212090                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0            0.390239                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1            0.392618                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2            0.384005                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3            0.388446                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4            0.386912                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5            0.393605                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6            0.390224                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7            0.397956                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.390495                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0           0.390239                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1           0.392618                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2           0.384005                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3           0.388446                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4           0.386912                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5           0.393605                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6           0.390224                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7           0.397956                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.390495                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0 16748.471688                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 17066.616013                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 16428.407001                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 17041.866737                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 16446.598352                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 17308.443793                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 17091.120653                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 16462.052329                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 16820.701953                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 43793.432985                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 43549.158134                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 43948.429371                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 43699.705895                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 44053.265900                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 43235.277226                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 43944.616835                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 43598.068144                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 43726.846479                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0 69253.193890                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1 69207.480836                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2 69193.212542                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69054.029757                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu4 69073.042707                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu5 69294.289316                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu6 69063.313985                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu7 69400.499800                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 69191.569230                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 52537.656967                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 52738.765391                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 52492.817521                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 52733.598633                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 52813.187756                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 52372.567981                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 52989.320943                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 52446.944925                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 52640.434761                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 52537.656967                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 52738.765391                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 52492.817521                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 52733.598633                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 52813.187756                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 52372.567981                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 52989.320943                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 52446.944925                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 52640.434761                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs             47178                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                     7722                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      6.109557                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks               22214                       # number of writebacks
system.l2c.writebacks::total                    22214                       # number of writebacks
system.l2c.UpgradeReq_mshr_hits::cpu0               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu1               3                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu2               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu3               3                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu4               3                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu5               2                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu6               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu7               4                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::total             18                       # number of UpgradeReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu0               16                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu1               18                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu2               19                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu3               22                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu4               24                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5               19                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu6               17                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu7               18                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total             153                       # number of ReadExReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0           39                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1           35                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu2           40                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3           33                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu4           29                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu5           39                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu6           37                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu7           32                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          284                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0                  55                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1                  53                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2                  59                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3                  55                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4                  53                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5                  58                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6                  54                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7                  50                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                437                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0                 55                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1                 53                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2                 59                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3                 55                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4                 53                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5                 58                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6                 54                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7                 50                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               437                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         4803                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         4803                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0          1924                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1          1833                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2          1913                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3          1903                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4          1939                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5          1875                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6          1897                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7          1907                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        15191                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0           4677                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1           4611                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2           4625                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3           4592                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4           4583                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5           4609                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6           4545                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7           4766                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         37008                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0         2416                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1         2548                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2         2336                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3         2521                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu4         2453                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu5         2460                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu6         2530                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu7         2465                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total        19729                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0              7093                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1              7159                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2              6961                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3              7113                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4              7036                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5              7069                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6              7075                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7              7231                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            56737                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0             7093                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1             7159                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2             6961                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3             7113                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4             7036                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5             7069                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6             7075                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7             7231                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           56737                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0         9869                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1         9955                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2         9851                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3         9751                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu4         9934                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu5         9850                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu6         9817                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu7         9808                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        78835                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0         5546                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1         5403                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2         5468                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3         5504                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu4         5430                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu5         5362                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu6         5563                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu7         5554                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        43830                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0        15415                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1        15358                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2        15319                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3        15255                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu4        15364                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu5        15212                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu6        15380                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu7        15362                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       122665                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0     44370463                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1     41900556                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2     43952891                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3     43546523                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4     44916850                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5     43178222                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6     43968016                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7     43732622                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    349566143                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0    157972902                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1    154816531                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2    157133230                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3    154812258                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4    156142960                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5    152972566                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6    154139305                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7    159984433                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1247974185                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0    144081359                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1    151505606                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2    139163869                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3    149583647                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu4    145392585                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu5    146682187                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu6    150257353                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu7    146960130                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total   1173626736                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0    302054261                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1    306322137                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2    296297099                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3    304395905                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4    301535545                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5    299654753                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6    304396658                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7    306944563                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   2421600921                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0    302054261                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1    306322137                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2    296297099                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3    304395905                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4    301535545                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5    299654753                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6    304396658                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7    306944563                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   2421600921                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    562092060                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    566771491                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    561276835                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    555967979                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    566543445                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    562440249                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    559671781                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    557696401                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   4492460241                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0    562092060                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1    566771491                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2    561276835                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3    555967979                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4    566543445                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5    562440249                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6    559671781                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7    557696401                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   4492460241                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.808403                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.812140                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.808538                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.822741                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.810280                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.809585                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.806548                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.799246                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.809625                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.717441                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.710478                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.700333                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.712711                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.707471                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.716128                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.708165                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.715079                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.710968                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0     0.204780                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1     0.214496                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2     0.200051                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3     0.209908                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu4     0.207109                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu5     0.210779                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu6     0.213484                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu7     0.211934                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.209080                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0       0.387236                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1       0.389733                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2       0.380778                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3       0.385466                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4       0.384019                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5       0.390402                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6       0.387268                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7       0.395223                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.387511                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0      0.387236                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1      0.389733                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2      0.380778                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3      0.385466                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4      0.384019                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5      0.390402                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6      0.387268                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7      0.395223                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.387511                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 23061.571206                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 22859.004910                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 22975.897020                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 22883.091435                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 23164.956163                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 23028.385067                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 23177.657354                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 22932.680650                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23011.397736                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 33776.545221                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 33575.478421                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 33974.752432                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 33713.470819                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 34070.032730                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 33189.968757                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 33914.038504                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 33567.862568                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 33721.740840                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59636.324089                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 59460.598901                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59573.574058                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59335.044427                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59271.335100                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 59626.905285                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59390.258103                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59618.713996                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59487.390947                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 42584.838714                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 42788.397402                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 42565.306565                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 42794.306903                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 42856.103610                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 42389.977790                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 43024.262615                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 42448.425252                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 42681.159050                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 42584.838714                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 42788.397402                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 42565.306565                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 42794.306903                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 42856.103610                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 42389.977790                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 43024.262615                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 42448.425252                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 42681.159050                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 56955.320701                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 56933.349171                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 56976.635367                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 57016.508973                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 57030.747433                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 57100.532893                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 57010.469695                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 56861.378569                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 56985.605898                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 36463.967564                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 36903.990819                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 36639.260722                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 36444.967486                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 36874.736071                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 36973.458388                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 36389.582640                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 36303.632405                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 36623.814788                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests        164288                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       148961                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               78834                       # Transaction distribution
system.membus.trans_dist::ReadResp              98509                       # Transaction distribution
system.membus.trans_dist::WriteReq              43828                       # Transaction distribution
system.membus.trans_dist::WriteResp             43821                       # Transaction distribution
system.membus.trans_dist::WritebackDirty        22214                       # Transaction distribution
system.membus.trans_dist::CleanEvict             4965                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            52120                       # Transaction distribution
system.membus.trans_dist::ReadExReq             56238                       # Transaction distribution
system.membus.trans_dist::ReadExResp            10901                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         19680                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       431110                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 431110                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      3501537                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                 3501537                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                            56051                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            276559                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  276559    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              276559                       # Request fanout histogram
system.membus.reqLayer0.occupancy           402118445                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization              77.4                       # Layer utilization (%)
system.membus.respLayer0.occupancy          354384000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization             68.2                       # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests       665414                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       284013                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       335409                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops          85048                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops        42676                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops        42372                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED    519755500                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq              78835                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            370283                       # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate            4                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             43830                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            43821                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty        98472                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          166953                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           29477                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          29475                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           161940                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          161937                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       291468                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       133769                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       133274                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       133373                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       133750                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       133468                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       133407                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       133623                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       133404                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1068068                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1804723                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1795646                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1797908                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1798742                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1795138                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1788203                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1789204                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1803712                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               14373276                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          408427                       # Total snoops (count)
system.toL2Bus.snoopTraffic                  21069312                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples           705291                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.195765                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.989501                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 180431     25.58%     25.58% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 295517     41.90%     67.48% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 157808     22.37%     89.86% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                  56265      7.98%     97.83% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                  13098      1.86%     99.69% # Request fanout histogram
system.toL2Bus.snoop_fanout::5                   1998      0.28%     99.98% # Request fanout histogram
system.toL2Bus.snoop_fanout::6                    166      0.02%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7                      8      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             705291                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          498497896                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization             95.9                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         102236927                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization            19.7                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         101928534                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization            19.6                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         102159135                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization            19.7                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         102401165                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization            19.7                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy         102112987                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization            19.6                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy         102230994                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization            19.7                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy         102247991                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization            19.7                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy         101908995                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization            19.6                       # Layer utilization (%)

---------- End Simulation Statistics   ----------