path: root/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.001493                       # Number of seconds simulated
sim_ticks                                  1493307500                       # Number of ticks simulated
final_tick                                 1493307500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_tick_rate                              295462472                       # Simulator tick rate (ticks/s)
host_mem_usage                                 222068                       # Number of bytes of host memory used
host_seconds                                     5.05                       # Real time elapsed on the host
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0                 74794                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1                 78736                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2                 78807                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3                 78188                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu4                 77250                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu5                 74477                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu6                 79412                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu7                 78325                       # Number of bytes read from this memory
system.physmem.bytes_read::total               619989                       # Number of bytes read from this memory
system.physmem.bytes_written::writebacks       384000                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0               5518                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1               5402                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu2               5400                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu3               5514                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu4               5530                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu5               5340                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu6               5402                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu7               5377                       # Number of bytes written to this memory
system.physmem.bytes_written::total            427483                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0                  10849                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1                  10948                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2                  10767                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3                  10841                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4                  10974                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5                  10721                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6                  10994                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7                  10915                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 87009                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks            6000                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0                  5518                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1                  5402                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2                  5400                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3                  5514                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4                  5530                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5                  5340                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6                  5402                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7                  5377                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                49483                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0                 50086134                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1                 52725912                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2                 52773458                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3                 52358941                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4                 51730806                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5                 49873854                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6                 53178599                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7                 52450684                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               415178388                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         257147306                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0                 3695153                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1                 3617473                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2                 3616134                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3                 3692475                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4                 3703189                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5                 3575955                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6                 3617473                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7                 3600732                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              286265890                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         257147306                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0                53781288                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1                56343385                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2                56389592                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3                56051416                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4                55433995                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5                53449809                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6                56796072                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7                56051416                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              701444277                       # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.num_reads                           99767                       # number of read accesses completed
system.cpu0.num_writes                          55259                       # number of write accesses completed
system.cpu0.l1c.tags.replacements               22696                       # number of replacements
system.cpu0.l1c.tags.tagsinuse             395.365301                       # Cycle average of tags in use
system.cpu0.l1c.tags.total_refs                 13357                       # Total number of references to valid blocks.
system.cpu0.l1c.tags.sampled_refs               23083                       # Sample count of references to valid blocks.
system.cpu0.l1c.tags.avg_refs                0.578651                       # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu0.l1c.tags.occ_blocks::cpu0      395.365301                       # Average occupied blocks per requestor
system.cpu0.l1c.tags.occ_percent::cpu0       0.772198                       # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_percent::total      0.772198                       # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_task_id_blocks::1024          387                       # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::0          272                       # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::1          115                       # Occupied blocks per task id
system.cpu0.l1c.tags.occ_task_id_percent::1024     0.755859                       # Percentage of cache occupancy per task id
system.cpu0.l1c.tags.tag_accesses              339665                       # Number of tag accesses
system.cpu0.l1c.tags.data_accesses             339665                       # Number of data accesses
system.cpu0.l1c.ReadReq_hits::cpu0               8708                       # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total              8708                       # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0              1150                       # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total             1150                       # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0                9858                       # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total               9858                       # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0               9858                       # number of overall hits
system.cpu0.l1c.overall_hits::total              9858                       # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0            36982                       # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total           36982                       # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0           23775                       # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total          23775                       # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0             60757                       # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total            60757                       # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0            60757                       # number of overall misses
system.cpu0.l1c.overall_misses::total           60757                       # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0   2501825237                       # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total   2501825237                       # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0   1853114266                       # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total   1853114266                       # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0   4354939503                       # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total   4354939503                       # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0   4354939503                       # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total   4354939503                       # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0          45690                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total         45690                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0         24925                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total        24925                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0           70615                       # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total          70615                       # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0          70615                       # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total         70615                       # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.809411                       # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total     0.809411                       # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.953862                       # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total     0.953862                       # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0       0.860398                       # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total      0.860398                       # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0      0.860398                       # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total     0.860398                       # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 67649.809015                       # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 67649.809015                       # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 77943.817708                       # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 77943.817708                       # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 71677.987771                       # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 71677.987771                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 71677.987771                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 71677.987771                       # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs      2197094                       # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_mshrs               60506                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_mshrs    36.312002                       # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu0.l1c.writebacks::writebacks           9747                       # number of writebacks
system.cpu0.l1c.writebacks::total                9747                       # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36982                       # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total        36982                       # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23775                       # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total        23775                       # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0        60757                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total        60757                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0        60757                       # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total        60757                       # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0   2423727133                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total   2423727133                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0   1803343082                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total   1803343082                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0   4227070215                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total   4227070215                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0   4227070215                       # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total   4227070215                       # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0   1077807594                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total   1077807594                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0   4091615147                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total   4091615147                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   5169422741                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total   5169422741                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.809411                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.809411                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.953862                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.953862                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.860398                       # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total     0.860398                       # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.860398                       # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total     0.860398                       # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 65538.022092                       # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 65538.022092                       # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 75850.392513                       # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 75850.392513                       # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 69573.386030                       # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 69573.386030                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 69573.386030                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 69573.386030                       # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0          inf                       # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu1.num_reads                          100000                       # number of read accesses completed
system.cpu1.num_writes                          54988                       # number of write accesses completed
system.cpu1.l1c.tags.replacements               22397                       # number of replacements
system.cpu1.l1c.tags.tagsinuse             395.796271                       # Cycle average of tags in use
system.cpu1.l1c.tags.total_refs                 13630                       # Total number of references to valid blocks.
system.cpu1.l1c.tags.sampled_refs               22804                       # Sample count of references to valid blocks.
system.cpu1.l1c.tags.avg_refs                0.597702                       # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu1.l1c.tags.occ_blocks::cpu1      395.796271                       # Average occupied blocks per requestor
system.cpu1.l1c.tags.occ_percent::cpu1       0.773040                       # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_percent::total      0.773040                       # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_task_id_blocks::1024          407                       # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::0          269                       # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::1          138                       # Occupied blocks per task id
system.cpu1.l1c.tags.occ_task_id_percent::1024     0.794922                       # Percentage of cache occupancy per task id
system.cpu1.l1c.tags.tag_accesses              338465                       # Number of tag accesses
system.cpu1.l1c.tags.data_accesses             338465                       # Number of data accesses
system.cpu1.l1c.ReadReq_hits::cpu1               8882                       # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total              8882                       # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1              1141                       # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total             1141                       # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1               10023                       # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total              10023                       # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1              10023                       # number of overall hits
system.cpu1.l1c.overall_hits::total             10023                       # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1            36639                       # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total           36639                       # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1           23767                       # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total          23767                       # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1             60406                       # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total            60406                       # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1            60406                       # number of overall misses
system.cpu1.l1c.overall_misses::total           60406                       # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1   2485954076                       # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total   2485954076                       # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1   1862028208                       # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total   1862028208                       # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1   4347982284                       # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total   4347982284                       # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1   4347982284                       # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total   4347982284                       # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1          45521                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total         45521                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1         24908                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total        24908                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1           70429                       # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total          70429                       # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1          70429                       # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total         70429                       # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.804881                       # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total     0.804881                       # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.954191                       # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total     0.954191                       # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1       0.857686                       # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total      0.857686                       # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1      0.857686                       # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total     0.857686                       # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 67849.943394                       # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 67849.943394                       # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 78345.109101                       # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 78345.109101                       # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 71979.311393                       # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 71979.311393                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 71979.311393                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 71979.311393                       # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs      2202198                       # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_mshrs               60277                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_mshrs    36.534632                       # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu1.l1c.writebacks::writebacks           9809                       # number of writebacks
system.cpu1.l1c.writebacks::total                9809                       # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36639                       # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total        36639                       # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23767                       # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total        23767                       # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1        60406                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total        60406                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1        60406                       # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total        60406                       # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1   2408616840                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total   2408616840                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1   1812196150                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total   1812196150                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1   4220812990                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total   4220812990                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1   4220812990                       # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total   4220812990                       # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1   1084723149                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total   1084723149                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1   4036922188                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total   4036922188                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   5121645337                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total   5121645337                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.804881                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.804881                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.954191                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.954191                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.857686                       # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total     0.857686                       # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.857686                       # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total     0.857686                       # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 65739.153361                       # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 65739.153361                       # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 76248.417975                       # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 76248.417975                       # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 69874.068636                       # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 69874.068636                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 69874.068636                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 69874.068636                       # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1          inf                       # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu2.num_reads                           99645                       # number of read accesses completed
system.cpu2.num_writes                          55347                       # number of write accesses completed
system.cpu2.l1c.tags.replacements               22638                       # number of replacements
system.cpu2.l1c.tags.tagsinuse             395.541236                       # Cycle average of tags in use
system.cpu2.l1c.tags.total_refs                 13666                       # Total number of references to valid blocks.
system.cpu2.l1c.tags.sampled_refs               23033                       # Sample count of references to valid blocks.
system.cpu2.l1c.tags.avg_refs                0.593323                       # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu2.l1c.tags.occ_blocks::cpu2      395.541236                       # Average occupied blocks per requestor
system.cpu2.l1c.tags.occ_percent::cpu2       0.772541                       # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_percent::total      0.772541                       # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_task_id_blocks::1024          395                       # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::0          271                       # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::1          124                       # Occupied blocks per task id
system.cpu2.l1c.tags.occ_task_id_percent::1024     0.771484                       # Percentage of cache occupancy per task id
system.cpu2.l1c.tags.tag_accesses              339287                       # Number of tag accesses
system.cpu2.l1c.tags.data_accesses             339287                       # Number of data accesses
system.cpu2.l1c.ReadReq_hits::cpu2               8844                       # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total              8844                       # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2              1130                       # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total             1130                       # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2                9974                       # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total               9974                       # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2               9974                       # number of overall hits
system.cpu2.l1c.overall_hits::total              9974                       # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2            36761                       # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total           36761                       # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2           23865                       # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total          23865                       # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2             60626                       # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total            60626                       # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2            60626                       # number of overall misses
system.cpu2.l1c.overall_misses::total           60626                       # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2   2497854261                       # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total   2497854261                       # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2   1869962350                       # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total   1869962350                       # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2   4367816611                       # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total   4367816611                       # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2   4367816611                       # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total   4367816611                       # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2          45605                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total         45605                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2         24995                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total        24995                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2           70600                       # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total          70600                       # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2          70600                       # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total         70600                       # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.806074                       # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total     0.806074                       # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.954791                       # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total     0.954791                       # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2       0.858725                       # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total      0.858725                       # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2      0.858725                       # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total     0.858725                       # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 67948.485106                       # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 67948.485106                       # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 78355.849571                       # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 78355.849571                       # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 72045.271187                       # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 72045.271187                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 72045.271187                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 72045.271187                       # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs      2198319                       # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_mshrs               60200                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_mshrs    36.516927                       # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu2.l1c.writebacks::writebacks           9871                       # number of writebacks
system.cpu2.l1c.writebacks::total                9871                       # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36761                       # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total        36761                       # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2        23865                       # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total        23865                       # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2        60626                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total        60626                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2        60626                       # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total        60626                       # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2   2420242117                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total   2420242117                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2   1819999216                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total   1819999216                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2   4240241333                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total   4240241333                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2   4240241333                       # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total   4240241333                       # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2   1065167222                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total   1065167222                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2   3984850744                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total   3984850744                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   5050017966                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total   5050017966                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.806074                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.806074                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.954791                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.954791                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.858725                       # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total     0.858725                       # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.858725                       # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total     0.858725                       # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 65837.221974                       # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 65837.221974                       # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 76262.275969                       # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 76262.275969                       # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 69940.971415                       # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 69940.971415                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 69940.971415                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 69940.971415                       # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2          inf                       # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu3.num_reads                           98252                       # number of read accesses completed
system.cpu3.num_writes                          55235                       # number of write accesses completed
system.cpu3.l1c.tags.replacements               22381                       # number of replacements
system.cpu3.l1c.tags.tagsinuse             396.107709                       # Cycle average of tags in use
system.cpu3.l1c.tags.total_refs                 13213                       # Total number of references to valid blocks.
system.cpu3.l1c.tags.sampled_refs               22778                       # Sample count of references to valid blocks.
system.cpu3.l1c.tags.avg_refs                0.580077                       # Average number of references to valid blocks.
system.cpu3.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu3.l1c.tags.occ_blocks::cpu3      396.107709                       # Average occupied blocks per requestor
system.cpu3.l1c.tags.occ_percent::cpu3       0.773648                       # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_percent::total      0.773648                       # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_task_id_blocks::1024          397                       # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::0          282                       # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::1          115                       # Occupied blocks per task id
system.cpu3.l1c.tags.occ_task_id_percent::1024     0.775391                       # Percentage of cache occupancy per task id
system.cpu3.l1c.tags.tag_accesses              335638                       # Number of tag accesses
system.cpu3.l1c.tags.data_accesses             335638                       # Number of data accesses
system.cpu3.l1c.ReadReq_hits::cpu3               8470                       # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total              8470                       # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3              1156                       # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total             1156                       # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3                9626                       # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total               9626                       # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3               9626                       # number of overall hits
system.cpu3.l1c.overall_hits::total              9626                       # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3            36183                       # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total           36183                       # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3           23969                       # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total          23969                       # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3             60152                       # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total            60152                       # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3            60152                       # number of overall misses
system.cpu3.l1c.overall_misses::total           60152                       # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3   2454128819                       # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total   2454128819                       # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3   1887224651                       # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total   1887224651                       # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3   4341353470                       # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total   4341353470                       # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3   4341353470                       # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total   4341353470                       # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3          44653                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total         44653                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3         25125                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total        25125                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3           69778                       # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total          69778                       # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3          69778                       # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total         69778                       # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.810315                       # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total     0.810315                       # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.953990                       # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total     0.953990                       # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3       0.862048                       # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total      0.862048                       # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3      0.862048                       # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total     0.862048                       # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 67825.465522                       # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 67825.465522                       # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 78736.061204                       # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 78736.061204                       # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 72173.052766                       # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 72173.052766                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 72173.052766                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 72173.052766                       # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs      2184377                       # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_mshrs               59819                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_mshrs    36.516441                       # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu3.l1c.writebacks::writebacks           9931                       # number of writebacks
system.cpu3.l1c.writebacks::total                9931                       # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36183                       # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total        36183                       # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23969                       # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total        23969                       # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3        60152                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total        60152                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3        60152                       # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total        60152                       # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3   2377731501                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total   2377731501                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3   1837004571                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total   1837004571                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3   4214736072                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total   4214736072                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3   4214736072                       # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total   4214736072                       # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3   1072192160                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total   1072192160                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3   4016794612                       # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total   4016794612                       # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   5088986772                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total   5088986772                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.810315                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.810315                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.953990                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.953990                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.862048                       # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total     0.862048                       # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.862048                       # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total     0.862048                       # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 65714.050825                       # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 65714.050825                       # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 76640.851558                       # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 76640.851558                       # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 70068.095358                       # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 70068.095358                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 70068.095358                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 70068.095358                       # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average WriteReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3          inf                       # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu4.num_reads                           99562                       # number of read accesses completed
system.cpu4.num_writes                          54813                       # number of write accesses completed
system.cpu4.l1c.tags.replacements               22626                       # number of replacements
system.cpu4.l1c.tags.tagsinuse             395.713168                       # Cycle average of tags in use
system.cpu4.l1c.tags.total_refs                 13359                       # Total number of references to valid blocks.
system.cpu4.l1c.tags.sampled_refs               23019                       # Sample count of references to valid blocks.
system.cpu4.l1c.tags.avg_refs                0.580347                       # Average number of references to valid blocks.
system.cpu4.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu4.l1c.tags.occ_blocks::cpu4      395.713168                       # Average occupied blocks per requestor
system.cpu4.l1c.tags.occ_percent::cpu4       0.772877                       # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_percent::total      0.772877                       # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_task_id_blocks::1024          393                       # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::0          273                       # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::1          120                       # Occupied blocks per task id
system.cpu4.l1c.tags.occ_task_id_percent::1024     0.767578                       # Percentage of cache occupancy per task id
system.cpu4.l1c.tags.tag_accesses              337886                       # Number of tag accesses
system.cpu4.l1c.tags.data_accesses             337886                       # Number of data accesses
system.cpu4.l1c.ReadReq_hits::cpu4               8660                       # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total              8660                       # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4              1130                       # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total             1130                       # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4                9790                       # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total               9790                       # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4               9790                       # number of overall hits
system.cpu4.l1c.overall_hits::total              9790                       # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4            36748                       # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total           36748                       # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4           23725                       # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total          23725                       # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4             60473                       # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total            60473                       # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4            60473                       # number of overall misses
system.cpu4.l1c.overall_misses::total           60473                       # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4   2479360793                       # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total   2479360793                       # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4   1851125976                       # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total   1851125976                       # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4   4330486769                       # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total   4330486769                       # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4   4330486769                       # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total   4330486769                       # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4          45408                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total         45408                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4         24855                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total        24855                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4           70263                       # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total          70263                       # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4          70263                       # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total         70263                       # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.809285                       # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total     0.809285                       # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.954536                       # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total     0.954536                       # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4       0.860666                       # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total      0.860666                       # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4      0.860666                       # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total     0.860666                       # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 67469.271607                       # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 67469.271607                       # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 78024.277176                       # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 78024.277176                       # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 71610.251997                       # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 71610.251997                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 71610.251997                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 71610.251997                       # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs      2193235                       # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_mshrs               60223                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_mshrs    36.418561                       # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu4.l1c.writebacks::writebacks           9708                       # number of writebacks
system.cpu4.l1c.writebacks::total                9708                       # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36748                       # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total        36748                       # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23725                       # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total        23725                       # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4        60473                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total        60473                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4        60473                       # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total        60473                       # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4   2401684855                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total   2401684855                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4   1801504708                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total   1801504708                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4   4203189563                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total   4203189563                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4   4203189563                       # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total   4203189563                       # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4   1091799507                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total   1091799507                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4   4121360584                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total   4121360584                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   5213160091                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total   5213160091                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.809285                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.809285                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.954536                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.954536                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.860666                       # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total     0.860666                       # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.860666                       # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total     0.860666                       # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 65355.525607                       # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 65355.525607                       # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 75932.759031                       # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 75932.759031                       # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 69505.226514                       # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 69505.226514                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 69505.226514                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 69505.226514                       # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4          inf                       # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu5.num_reads                           98672                       # number of read accesses completed
system.cpu5.num_writes                          54809                       # number of write accesses completed
system.cpu5.l1c.tags.replacements               22472                       # number of replacements
system.cpu5.l1c.tags.tagsinuse             396.252013                       # Cycle average of tags in use
system.cpu5.l1c.tags.total_refs                 13351                       # Total number of references to valid blocks.
system.cpu5.l1c.tags.sampled_refs               22867                       # Sample count of references to valid blocks.
system.cpu5.l1c.tags.avg_refs                0.583854                       # Average number of references to valid blocks.
system.cpu5.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu5.l1c.tags.occ_blocks::cpu5      396.252013                       # Average occupied blocks per requestor
system.cpu5.l1c.tags.occ_percent::cpu5       0.773930                       # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_percent::total      0.773930                       # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_task_id_blocks::1024          395                       # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::0          261                       # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::1          134                       # Occupied blocks per task id
system.cpu5.l1c.tags.occ_task_id_percent::1024     0.771484                       # Percentage of cache occupancy per task id
system.cpu5.l1c.tags.tag_accesses              336301                       # Number of tag accesses
system.cpu5.l1c.tags.data_accesses             336301                       # Number of data accesses
system.cpu5.l1c.ReadReq_hits::cpu5               8563                       # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total              8563                       # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5              1084                       # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total             1084                       # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5                9647                       # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total               9647                       # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5               9647                       # number of overall hits
system.cpu5.l1c.overall_hits::total              9647                       # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5            36411                       # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total           36411                       # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5           23882                       # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total          23882                       # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5             60293                       # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total            60293                       # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5            60293                       # number of overall misses
system.cpu5.l1c.overall_misses::total           60293                       # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5   2486246489                       # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total   2486246489                       # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5   1881159650                       # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total   1881159650                       # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5   4367406139                       # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total   4367406139                       # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5   4367406139                       # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total   4367406139                       # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5          44974                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total         44974                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5         24966                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total        24966                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5           69940                       # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total          69940                       # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5          69940                       # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total         69940                       # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.809601                       # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total     0.809601                       # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.956581                       # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total     0.956581                       # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5       0.862067                       # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total      0.862067                       # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5      0.862067                       # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total     0.862067                       # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 68282.840048                       # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 68282.840048                       # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 78768.932669                       # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 78768.932669                       # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 72436.371370                       # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 72436.371370                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 72436.371370                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 72436.371370                       # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs      2200429                       # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_mshrs               60083                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_mshrs    36.623155                       # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu5.l1c.writebacks::writebacks           9941                       # number of writebacks
system.cpu5.l1c.writebacks::total                9941                       # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36411                       # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total        36411                       # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23882                       # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total        23882                       # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5        60293                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total        60293                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5        60293                       # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total        60293                       # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5   2409268523                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total   2409268523                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5   1831238342                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total   1831238342                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5   4240506865                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total   4240506865                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5   4240506865                       # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total   4240506865                       # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5   1068031665                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total   1068031665                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5   3938248323                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total   3938248323                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   5006279988                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total   5006279988                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.809601                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.809601                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.956581                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.956581                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.862067                       # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total     0.862067                       # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.862067                       # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total     0.862067                       # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 66168.699651                       # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 66168.699651                       # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 76678.600703                       # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 76678.600703                       # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 70331.661470                       # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 70331.661470                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 70331.661470                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 70331.661470                       # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5          inf                       # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu6.num_reads                           99484                       # number of read accesses completed
system.cpu6.num_writes                          54995                       # number of write accesses completed
system.cpu6.l1c.tags.replacements               22115                       # number of replacements
system.cpu6.l1c.tags.tagsinuse             396.164371                       # Cycle average of tags in use
system.cpu6.l1c.tags.total_refs                 13666                       # Total number of references to valid blocks.
system.cpu6.l1c.tags.sampled_refs               22491                       # Sample count of references to valid blocks.
system.cpu6.l1c.tags.avg_refs                0.607621                       # Average number of references to valid blocks.
system.cpu6.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu6.l1c.tags.occ_blocks::cpu6      396.164371                       # Average occupied blocks per requestor
system.cpu6.l1c.tags.occ_percent::cpu6       0.773759                       # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_percent::total      0.773759                       # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_task_id_blocks::1024          376                       # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::0          247                       # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::1          129                       # Occupied blocks per task id
system.cpu6.l1c.tags.occ_task_id_percent::1024     0.734375                       # Percentage of cache occupancy per task id
system.cpu6.l1c.tags.tag_accesses              338129                       # Number of tag accesses
system.cpu6.l1c.tags.data_accesses             338129                       # Number of data accesses
system.cpu6.l1c.ReadReq_hits::cpu6               8797                       # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total              8797                       # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6              1207                       # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total             1207                       # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6               10004                       # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total              10004                       # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6              10004                       # number of overall hits
system.cpu6.l1c.overall_hits::total             10004                       # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6            36456                       # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total           36456                       # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6           23912                       # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total          23912                       # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6             60368                       # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total            60368                       # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6            60368                       # number of overall misses
system.cpu6.l1c.overall_misses::total           60368                       # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6   2466938162                       # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total   2466938162                       # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6   1877191258                       # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total   1877191258                       # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6   4344129420                       # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total   4344129420                       # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6   4344129420                       # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total   4344129420                       # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6          45253                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total         45253                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6         25119                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total        25119                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6           70372                       # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total          70372                       # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6          70372                       # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total         70372                       # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.805604                       # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total     0.805604                       # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.951949                       # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total     0.951949                       # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6       0.857841                       # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total      0.857841                       # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6      0.857841                       # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total     0.857841                       # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 67668.920397                       # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 67668.920397                       # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 78504.150970                       # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 78504.150970                       # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 71960.797442                       # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 71960.797442                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 71960.797442                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 71960.797442                       # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs      2202006                       # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_mshrs               60316                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_mshrs    36.507825                       # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu6.l1c.writebacks::writebacks           9723                       # number of writebacks
system.cpu6.l1c.writebacks::total                9723                       # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36456                       # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total        36456                       # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23912                       # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total        23912                       # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6        60368                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total        60368                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6        60368                       # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total        60368                       # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6   2389944958                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total   2389944958                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6   1827130108                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total   1827130108                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6   4217075066                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total   4217075066                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6   4217075066                       # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total   4217075066                       # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6   1090860454                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total   1090860454                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6   4034817264                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total   4034817264                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   5125677718                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total   5125677718                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.805604                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.805604                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.951949                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.951949                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.857841                       # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total     0.857841                       # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.857841                       # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total     0.857841                       # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 65556.971637                       # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 65556.971637                       # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 76410.593342                       # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 76410.593342                       # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 69856.133481                       # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 69856.133481                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 69856.133481                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 69856.133481                       # average overall mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6          inf                       # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu7.num_reads                           98571                       # number of read accesses completed
system.cpu7.num_writes                          54904                       # number of write accesses completed
system.cpu7.l1c.tags.replacements               22064                       # number of replacements
system.cpu7.l1c.tags.tagsinuse             394.954913                       # Cycle average of tags in use
system.cpu7.l1c.tags.total_refs                 13425                       # Total number of references to valid blocks.
system.cpu7.l1c.tags.sampled_refs               22470                       # Sample count of references to valid blocks.
system.cpu7.l1c.tags.avg_refs                0.597463                       # Average number of references to valid blocks.
system.cpu7.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu7.l1c.tags.occ_blocks::cpu7      394.954913                       # Average occupied blocks per requestor
system.cpu7.l1c.tags.occ_percent::cpu7       0.771396                       # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_percent::total      0.771396                       # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_task_id_blocks::1024          406                       # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::0          274                       # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::1          132                       # Occupied blocks per task id
system.cpu7.l1c.tags.occ_task_id_percent::1024     0.792969                       # Percentage of cache occupancy per task id
system.cpu7.l1c.tags.tag_accesses              334895                       # Number of tag accesses
system.cpu7.l1c.tags.data_accesses             334895                       # Number of data accesses
system.cpu7.l1c.ReadReq_hits::cpu7               8604                       # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total              8604                       # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7              1157                       # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total             1157                       # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7                9761                       # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total               9761                       # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7               9761                       # number of overall hits
system.cpu7.l1c.overall_hits::total              9761                       # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7            35973                       # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total           35973                       # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7           23939                       # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total          23939                       # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7             59912                       # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total            59912                       # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7            59912                       # number of overall misses
system.cpu7.l1c.overall_misses::total           59912                       # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7   2452832630                       # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total   2452832630                       # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7   1890055104                       # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total   1890055104                       # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7   4342887734                       # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total   4342887734                       # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7   4342887734                       # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total   4342887734                       # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7          44577                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total         44577                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7         25096                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total        25096                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7           69673                       # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total          69673                       # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7          69673                       # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total         69673                       # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.806986                       # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total     0.806986                       # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.953897                       # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total     0.953897                       # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7       0.859903                       # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total      0.859903                       # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7      0.859903                       # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total     0.859903                       # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 68185.378756                       # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 68185.378756                       # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 78952.968127                       # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 78952.968127                       # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 72487.777641                       # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 72487.777641                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 72487.777641                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 72487.777641                       # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs      2195658                       # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_mshrs               59807                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_mshrs    36.712392                       # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu7.l1c.writebacks::writebacks           9796                       # number of writebacks
system.cpu7.l1c.writebacks::total                9796                       # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7        35973                       # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total        35973                       # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23939                       # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total        23939                       # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7        59912                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total        59912                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7        59912                       # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total        59912                       # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7   2376889288                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total   2376889288                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7   1839857154                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total   1839857154                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7   4216746442                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total   4216746442                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7   4216746442                       # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total   4216746442                       # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7   1084884512                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total   1084884512                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7   4029557689                       # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total   4029557689                       # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   5114442201                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total   5114442201                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.806986                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.806986                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.953897                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.953897                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.859903                       # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total     0.859903                       # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.859903                       # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total     0.859903                       # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 66074.258138                       # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 66074.258138                       # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 76856.057229                       # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 76856.057229                       # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 70382.334791                       # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 70382.334791                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 70382.334791                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 70382.334791                       # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average WriteReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                    12730                       # number of replacements
system.l2c.tags.tagsinuse                  780.951688                       # Cycle average of tags in use
system.l2c.tags.total_refs                     149721                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                    13527                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    11.068308                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks     730.352338                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0             5.728717                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1             6.680211                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2             7.211499                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3             5.648633                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu4             6.142733                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu5             5.860524                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu6             6.858945                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu7             6.468088                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.713235                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0            0.005594                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1            0.006524                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2            0.007042                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3            0.005516                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu4            0.005999                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu5            0.005723                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu6            0.006698                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu7            0.006316                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.762648                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024          797                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          372                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          424                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.778320                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  1954074                       # Number of tag accesses
system.l2c.tags.data_accesses                 1954074                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0                   10705                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1                   10659                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2                   10665                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3                   10689                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu4                   10673                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu5                   10679                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu6                   10651                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu7                   10616                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  85337                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks           75478                       # number of Writeback hits
system.l2c.Writeback_hits::total                75478                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0                  365                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1                  341                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2                  363                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3                  349                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4                  333                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5                  340                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6                  338                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7                  343                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                2772                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0                  1956                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1                  1860                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2                  1936                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3                  1874                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4                  1916                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5                  1840                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6                  1899                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7                  1911                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                15192                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0                    12661                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1                    12519                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2                    12601                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3                    12563                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu4                    12589                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu5                    12519                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu6                    12550                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu7                    12527                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  100529                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0                   12661                       # number of overall hits
system.l2c.overall_hits::cpu1                   12519                       # number of overall hits
system.l2c.overall_hits::cpu2                   12601                       # number of overall hits
system.l2c.overall_hits::cpu3                   12563                       # number of overall hits
system.l2c.overall_hits::cpu4                   12589                       # number of overall hits
system.l2c.overall_hits::cpu5                   12519                       # number of overall hits
system.l2c.overall_hits::cpu6                   12550                       # number of overall hits
system.l2c.overall_hits::cpu7                   12527                       # number of overall hits
system.l2c.overall_hits::total                 100529                       # number of overall hits
system.l2c.ReadReq_misses::cpu0                   637                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1                   698                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2                   718                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3                   649                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu4                   657                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu5                   655                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu6                   700                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu7                   686                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 5400                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0               1869                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1               1879                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2               1945                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3               1927                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4               1931                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5               2008                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6               1996                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7               1999                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             15554                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0                4360                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1                4327                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2                4376                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3                4482                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4                4415                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5                4364                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6                4427                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7                4401                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              35152                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0                   4997                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1                   5025                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2                   5094                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3                   5131                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu4                   5072                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu5                   5019                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu6                   5127                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu7                   5087                       # number of demand (read+write) misses
system.l2c.demand_misses::total                 40552                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0                  4997                       # number of overall misses
system.l2c.overall_misses::cpu1                  5025                       # number of overall misses
system.l2c.overall_misses::cpu2                  5094                       # number of overall misses
system.l2c.overall_misses::cpu3                  5131                       # number of overall misses
system.l2c.overall_misses::cpu4                  5072                       # number of overall misses
system.l2c.overall_misses::cpu5                  5019                       # number of overall misses
system.l2c.overall_misses::cpu6                  5127                       # number of overall misses
system.l2c.overall_misses::cpu7                  5087                       # number of overall misses
system.l2c.overall_misses::total                40552                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0        37351962                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1        41387952                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2        42368449                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3        38023954                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu4        38587461                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu5        38640955                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu6        40955466                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu7        40550959                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      317867158                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0     53532000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1     54034500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2     55090000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3     53743000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4     53806000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5     57327000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6     56366500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7     57375499                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    441274499                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0     232668482                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1     231079974                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2     233454479                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3     239997471                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4     235674978                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5     232806977                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6     236584974                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7     235413970                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1877681305                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0        270020444                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1        272467926                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2        275822928                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3        278021425                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4        274262439                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5        271447932                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6        277540440                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7        275964929                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      2195548463                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0       270020444                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1       272467926                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2       275822928                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3       278021425                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4       274262439                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5       271447932                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6       277540440                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7       275964929                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     2195548463                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0               11342                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1               11357                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2               11383                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3               11338                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu4               11330                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu5               11334                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu6               11351                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu7               11302                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              90737                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks        75478                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total            75478                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0             2234                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1             2220                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2             2308                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3             2276                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4             2264                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5             2348                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6             2334                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7             2342                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           18326                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0              6316                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1              6187                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2              6312                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3              6356                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4              6331                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5              6204                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6              6326                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7              6312                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            50344                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0                17658                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1                17544                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2                17695                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3                17694                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4                17661                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5                17538                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6                17677                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7                17614                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              141081                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0               17658                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1               17544                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2               17695                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3               17694                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4               17661                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5               17538                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6               17677                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7               17614                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             141081                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0           0.056163                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1           0.061460                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2           0.063077                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3           0.057241                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu4           0.057988                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu5           0.057791                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu6           0.061669                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu7           0.060697                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.059513                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0        0.836616                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1        0.846396                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2        0.842721                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3        0.846661                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4        0.852915                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5        0.855196                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6        0.855184                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7        0.853544                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.848739                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0         0.690310                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1         0.699370                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2         0.693283                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3         0.705160                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4         0.697362                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5         0.703417                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6         0.699810                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7         0.697243                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.698236                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0            0.282988                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1            0.286423                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2            0.287878                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3            0.289985                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4            0.287186                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5            0.286179                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6            0.290038                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7            0.288804                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.287438                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0           0.282988                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1           0.286423                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2           0.287878                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3           0.289985                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4           0.287186                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5           0.286179                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6           0.290038                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7           0.288804                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.287438                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0 58637.302983                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1 59295.060172                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2 59008.981894                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3 58588.526965                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu4 58732.817352                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu5 58993.824427                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu6 58507.808571                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu7 59112.185131                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 58864.288519                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0 28642.054575                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 28757.051623                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 28323.907455                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 27889.465490                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 27864.319006                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 28549.302789                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 28239.729459                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 28702.100550                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 28370.483413                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 53364.330734                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 53404.200139                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 53348.829753                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 53546.959170                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 53380.515968                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 53347.153300                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 53441.376553                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 53491.017950                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 53416.058972                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 54036.510706                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 54222.472836                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 54146.628975                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 54184.647242                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 54073.824724                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 54084.066946                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 54133.107080                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 54249.052290                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 54141.558074                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 54036.510706                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 54222.472836                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 54146.628975                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 54184.647242                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 54073.824724                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 54084.066946                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 54133.107080                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 54249.052290                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 54141.558074                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs              6543                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                      914                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      7.158643                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks                6000                       # number of writebacks
system.l2c.writebacks::total                     6000                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0                  2                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1                  3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2                  2                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3                  6                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu5                  4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu6                  2                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu7                  2                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                21                       # number of ReadReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu2               2                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu3               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu6               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::total              4                       # number of UpgradeReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu1                4                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu2                4                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu4                1                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5                1                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu6                2                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu7                2                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total              14                       # number of ReadExReq MSHR hits
system.l2c.demand_mshr_hits::cpu0                   2                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1                   7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2                   6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3                   6                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4                   1                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5                   5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6                   4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7                   4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 35                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0                  2                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1                  7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2                  6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3                  6                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4                  1                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5                  5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6                  4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7                  4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                35                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0              635                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1              695                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2              716                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3              643                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu4              657                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu5              651                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu6              698                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu7              684                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            5379                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0          1869                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1          1879                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2          1943                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3          1926                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4          1931                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5          2008                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6          1995                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7          1999                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        15550                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0           4360                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1           4323                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2           4372                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3           4482                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4           4414                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5           4363                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6           4425                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7           4399                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         35138                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0              4995                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1              5018                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2              5088                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3              5125                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4              5071                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5              5014                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6              5123                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7              5083                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            40517                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0             4995                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1             5018                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2             5088                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3             5125                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4             5071                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5             5014                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6             5123                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7             5083                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           40517                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0     29596962                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1     32869452                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2     33629449                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3     29976455                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu4     30615961                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu5     30583955                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu6     32395466                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu7     32146959                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    251814659                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0     76123000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1     76358500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2     79146000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3     78403000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4     78530000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5     81677500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6     81182000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7     81450499                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    632870499                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0    179654482                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1    178405975                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2    180144979                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3    185516471                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4    181991978                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5    179667478                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6    182702975                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7    181859470                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1449943808                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0    209251444                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1    211275427                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2    213774428                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3    215492926                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4    212607939                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5    210251433                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6    215098441                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7    214006429                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   1701758467                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0    209251444                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1    211275427                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2    213774428                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3    215492926                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4    212607939                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5    210251433                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6    215098441                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7    214006429                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   1701758467                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    401930986                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    402911994                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    395709487                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    399023483                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    405620989                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    396449489                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    404605985                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    402179993                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   3208432406                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    228006492                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    223295497                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    223196996                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    228513495                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    229209992                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    220676995                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    224532992                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    222245997                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1799678456                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0    629937478                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1    626207491                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2    618906483                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3    627536978                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4    634830981                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5    617126484                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6    629138977                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7    624425990                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   5008110862                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0      0.055987                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1      0.061196                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2      0.062901                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3      0.056712                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu4      0.057988                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu5      0.057438                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu6      0.061492                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu7      0.060520                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.059281                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.836616                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.846396                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.841854                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.846221                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.852915                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.855196                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.854756                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.853544                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.848521                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.690310                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.698723                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.692649                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.705160                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.697204                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.703256                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.699494                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.696926                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.697958                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0       0.282875                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1       0.286024                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2       0.287539                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3       0.289646                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4       0.287130                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5       0.285893                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6       0.289812                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7       0.288577                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.287190                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0      0.282875                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1      0.286024                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2      0.287539                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3      0.289646                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4      0.287130                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5      0.285893                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6      0.289812                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7      0.288577                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.287190                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 46609.388976                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 47294.175540                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 46968.504190                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 46619.681182                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 46599.636225                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 46979.961598                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 46411.842407                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 46998.478070                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 46814.400260                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40729.266988                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40637.839276                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40733.916624                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40707.684320                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40668.047644                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40676.045817                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40692.731830                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40745.622311                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40699.067460                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41205.156422                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41269.020356                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41204.249543                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41391.448237                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41230.624830                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41179.802430                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41288.807910                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41341.093430                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 41264.266834                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 41892.180981                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 42103.512754                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 42015.414308                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 42047.400195                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 41926.235259                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 41932.874551                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 41986.812610                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 42102.386189                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 42001.097490                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 41892.180981                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 42103.512754                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 42015.414308                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 42047.400195                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 41926.235259                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 41932.874551                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 41986.812610                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 42102.386189                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 42001.097490                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.snoop_filter.tot_requests        122833                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       120785                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.trans_dist::ReadReq               83923                       # Transaction distribution
system.membus.trans_dist::ReadResp              83923                       # Transaction distribution
system.membus.trans_dist::WriteReq              43483                       # Transaction distribution
system.membus.trans_dist::WriteResp             43481                       # Transaction distribution
system.membus.trans_dist::Writeback              6000                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            58661                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           47607                       # Transaction distribution
system.membus.trans_dist::ReadExReq             50527                       # Transaction distribution
system.membus.trans_dist::ReadExResp             3086                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       420691                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 420691                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1047472                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                 1047472                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                            58495                       # Total snoops (count)
system.membus.snoop_fanout::samples            122833                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  122833    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              122833                       # Request fanout histogram
system.membus.reqLayer0.occupancy           472878500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization              31.7                       # Layer utilization (%)
system.membus.respLayer0.occupancy          318922500                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization             21.4                       # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests       559080                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       259825                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       297207                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq             370692                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            370683                       # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             43483                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            43481                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback            75478                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           29380                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          29380                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           161449                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          161449                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       120700                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       120118                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       120296                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       120254                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       120627                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       119815                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       120341                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       119764                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total                961915                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1743799                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1739946                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1755311                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1759542                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1742748                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1748105                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1744654                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1747573                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               13981678                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          323561                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples           559080                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.688315                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           1.176863                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                  52722      9.43%      9.43% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 250233     44.76%     54.19% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 141253     25.27%     79.45% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                  69107     12.36%     91.81% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                  29981      5.36%     97.18% # Request fanout histogram
system.toL2Bus.snoop_fanout::5                  11505      2.06%     99.23% # Request fanout histogram
system.toL2Bus.snoop_fanout::6                   3559      0.64%     99.87% # Request fanout histogram
system.toL2Bus.snoop_fanout::7                    720      0.13%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             559080                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         1490758741                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization             99.8                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         160617515                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization            10.8                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         159518006                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization            10.7                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         159700003                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization            10.7                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         158882050                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization            10.6                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy         159826982                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization            10.7                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy         158824012                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization            10.6                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy         159298538                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization            10.7                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy         158114013                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization            10.6                       # Layer utilization (%)

---------- End Simulation Statistics   ----------