blob: 1b65661816f752b65b04ae5a6a40885fb38c971c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000730 # Number of seconds simulated
sim_ticks 729906500 # Number of ticks simulated
final_tick 729906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_tick_rate 158517498 # Simulator tick rate (ticks/s)
host_mem_usage 277860 # Number of bytes of host memory used
host_seconds 4.60 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0 76606 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1 79713 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2 76745 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3 78087 # Number of bytes read from this memory
system.physmem.bytes_read::cpu4 75189 # Number of bytes read from this memory
system.physmem.bytes_read::cpu5 77277 # Number of bytes read from this memory
system.physmem.bytes_read::cpu6 77630 # Number of bytes read from this memory
system.physmem.bytes_read::cpu7 79795 # Number of bytes read from this memory
system.physmem.bytes_read::total 621042 # Number of bytes read from this memory
system.physmem.bytes_written::writebacks 386688 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0 5350 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1 5335 # Number of bytes written to this memory
system.physmem.bytes_written::cpu2 5338 # Number of bytes written to this memory
system.physmem.bytes_written::cpu3 5543 # Number of bytes written to this memory
system.physmem.bytes_written::cpu4 5464 # Number of bytes written to this memory
system.physmem.bytes_written::cpu5 5476 # Number of bytes written to this memory
system.physmem.bytes_written::cpu6 5444 # Number of bytes written to this memory
system.physmem.bytes_written::cpu7 5451 # Number of bytes written to this memory
system.physmem.bytes_written::total 430089 # Number of bytes written to this memory
system.physmem.num_reads::cpu0 10897 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1 11106 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2 10910 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3 10803 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4 10929 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5 10812 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6 10850 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7 10810 # Number of read requests responded to by this memory
system.physmem.num_reads::total 87117 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 6042 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0 5350 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1 5335 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2 5338 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3 5543 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4 5464 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5 5476 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6 5444 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7 5451 # Number of write requests responded to by this memory
system.physmem.num_writes::total 49443 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0 104953169 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1 109209878 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2 105143604 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3 106982196 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4 103011824 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5 105872464 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6 106356088 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7 109322221 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 850851445 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 529777444 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0 7329706 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1 7309155 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2 7313265 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3 7594123 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4 7485890 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5 7502331 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6 7458490 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7 7468080 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 589238485 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 529777444 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0 112282875 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1 116519034 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2 112456869 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3 114576319 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4 110497714 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5 113374795 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6 113814578 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7 116790301 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1440089929 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.num_reads 99153 # number of read accesses completed
system.cpu0.num_writes 54942 # number of write accesses completed
system.cpu0.l1c.tags.replacements 22508 # number of replacements
system.cpu0.l1c.tags.tagsinuse 393.884164 # Cycle average of tags in use
system.cpu0.l1c.tags.total_refs 13343 # Total number of references to valid blocks.
system.cpu0.l1c.tags.sampled_refs 22908 # Sample count of references to valid blocks.
system.cpu0.l1c.tags.avg_refs 0.582460 # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.l1c.tags.occ_blocks::cpu0 393.884164 # Average occupied blocks per requestor
system.cpu0.l1c.tags.occ_percent::cpu0 0.769305 # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_percent::total 0.769305 # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::0 366 # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id
system.cpu0.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id
system.cpu0.l1c.tags.tag_accesses 337372 # Number of tag accesses
system.cpu0.l1c.tags.data_accesses 337372 # Number of data accesses
system.cpu0.l1c.ReadReq_hits::cpu0 8651 # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total 8651 # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0 1083 # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total 1083 # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0 9734 # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total 9734 # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0 9734 # number of overall hits
system.cpu0.l1c.overall_hits::total 9734 # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0 36335 # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total 36335 # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0 24086 # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total 24086 # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0 60421 # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total 60421 # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0 60421 # number of overall misses
system.cpu0.l1c.overall_misses::total 60421 # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0 1008804376 # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total 1008804376 # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0 935467464 # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total 935467464 # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0 1944271840 # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total 1944271840 # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0 1944271840 # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total 1944271840 # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0 44986 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total 44986 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0 25169 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total 25169 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0 70155 # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total 70155 # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0 70155 # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total 70155 # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807696 # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total 0.807696 # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956971 # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total 0.956971 # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0 0.861250 # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total 0.861250 # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0 0.861250 # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total 0.861250 # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 27763.984478 # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 27763.984478 # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38838.639209 # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 38838.639209 # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 32178.743152 # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 32178.743152 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 32178.743152 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 32178.743152 # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs 1068204 # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l1c.blocked::no_mshrs 61717 # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_mshrs 17.308100 # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
system.cpu0.l1c.writebacks::writebacks 9915 # number of writebacks
system.cpu0.l1c.writebacks::total 9915 # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36335 # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total 36335 # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24086 # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total 24086 # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0 60421 # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total 60421 # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0 60421 # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total 60421 # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 953224016 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total 953224016 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 898871386 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total 898871386 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1852095402 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total 1852095402 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1852095402 # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total 1852095402 # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 743740324 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 743740324 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1921383275 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1921383275 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2665123599 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2665123599 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807696 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807696 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956971 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956971 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861250 # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total 0.861250 # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861250 # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total 0.861250 # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 26234.319967 # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 26234.319967 # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37319.247115 # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37319.247115 # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 30653.173599 # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 30653.173599 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 30653.173599 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 30653.173599 # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.num_reads 100000 # number of read accesses completed
system.cpu1.num_writes 54938 # number of write accesses completed
system.cpu1.l1c.tags.replacements 22377 # number of replacements
system.cpu1.l1c.tags.tagsinuse 394.468790 # Cycle average of tags in use
system.cpu1.l1c.tags.total_refs 13456 # Total number of references to valid blocks.
system.cpu1.l1c.tags.sampled_refs 22785 # Sample count of references to valid blocks.
system.cpu1.l1c.tags.avg_refs 0.590564 # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l1c.tags.occ_blocks::cpu1 394.468790 # Average occupied blocks per requestor
system.cpu1.l1c.tags.occ_percent::cpu1 0.770447 # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_percent::total 0.770447 # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
system.cpu1.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id
system.cpu1.l1c.tags.tag_accesses 338150 # Number of tag accesses
system.cpu1.l1c.tags.data_accesses 338150 # Number of data accesses
system.cpu1.l1c.ReadReq_hits::cpu1 8709 # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total 8709 # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1 1179 # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total 1179 # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1 9888 # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total 9888 # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1 9888 # number of overall hits
system.cpu1.l1c.overall_hits::total 9888 # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1 36587 # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total 36587 # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1 23856 # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total 23856 # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1 60443 # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total 60443 # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1 60443 # number of overall misses
system.cpu1.l1c.overall_misses::total 60443 # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1 1017715976 # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total 1017715976 # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1 924313604 # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total 924313604 # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1 1942029580 # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total 1942029580 # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1 1942029580 # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total 1942029580 # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1 45296 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total 45296 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1 25035 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total 25035 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1 70331 # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total 70331 # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1 70331 # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total 70331 # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807731 # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total 0.807731 # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.952906 # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total 0.952906 # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1 0.859408 # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total 0.859408 # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1 0.859408 # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total 0.859408 # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 27816.327548 # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 27816.327548 # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38745.540074 # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 38745.540074 # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 32129.933657 # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 32129.933657 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 32129.933657 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 32129.933657 # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs 1075887 # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_mshrs 62059 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_mshrs 17.336518 # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
system.cpu1.l1c.writebacks::writebacks 9753 # number of writebacks
system.cpu1.l1c.writebacks::total 9753 # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36587 # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total 36587 # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23856 # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total 23856 # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1 60443 # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total 60443 # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1 60443 # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total 60443 # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 961736168 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total 961736168 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 888050076 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total 888050076 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1849786244 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total 1849786244 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1849786244 # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total 1849786244 # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 753708733 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 753708733 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1923800282 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1923800282 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2677509015 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2677509015 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807731 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807731 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.952906 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.952906 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859408 # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total 0.859408 # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859408 # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total 0.859408 # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 26286.281138 # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 26286.281138 # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37225.439135 # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37225.439135 # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 30603.812584 # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 30603.812584 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 30603.812584 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 30603.812584 # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.num_reads 99515 # number of read accesses completed
system.cpu2.num_writes 55356 # number of write accesses completed
system.cpu2.l1c.tags.replacements 22413 # number of replacements
system.cpu2.l1c.tags.tagsinuse 394.491739 # Cycle average of tags in use
system.cpu2.l1c.tags.total_refs 13448 # Total number of references to valid blocks.
system.cpu2.l1c.tags.sampled_refs 22815 # Sample count of references to valid blocks.
system.cpu2.l1c.tags.avg_refs 0.589437 # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.l1c.tags.occ_blocks::cpu2 394.491739 # Average occupied blocks per requestor
system.cpu2.l1c.tags.occ_percent::cpu2 0.770492 # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_percent::total 0.770492 # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
system.cpu2.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
system.cpu2.l1c.tags.tag_accesses 338294 # Number of tag accesses
system.cpu2.l1c.tags.data_accesses 338294 # Number of data accesses
system.cpu2.l1c.ReadReq_hits::cpu2 8726 # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total 8726 # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2 1175 # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total 1175 # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2 9901 # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total 9901 # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2 9901 # number of overall hits
system.cpu2.l1c.overall_hits::total 9901 # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2 36442 # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total 36442 # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2 24017 # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total 24017 # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2 60459 # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total 60459 # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2 60459 # number of overall misses
system.cpu2.l1c.overall_misses::total 60459 # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2 1013968188 # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total 1013968188 # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2 926155084 # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total 926155084 # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2 1940123272 # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total 1940123272 # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2 1940123272 # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total 1940123272 # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2 45168 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total 45168 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2 25192 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total 25192 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2 70360 # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total 70360 # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2 70360 # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total 70360 # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806810 # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total 0.806810 # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953358 # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total 0.953358 # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2 0.859281 # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total 0.859281 # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2 0.859281 # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total 0.859281 # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 27824.164096 # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 27824.164096 # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 38562.480077 # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 38562.480077 # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 32089.900131 # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 32089.900131 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 32089.900131 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 32089.900131 # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs 1067763 # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.l1c.blocked::no_mshrs 61601 # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_mshrs 17.333534 # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
system.cpu2.l1c.writebacks::writebacks 9861 # number of writebacks
system.cpu2.l1c.writebacks::total 9861 # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36442 # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total 36442 # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24017 # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total 24017 # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2 60459 # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total 60459 # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2 60459 # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total 60459 # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 958233322 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total 958233322 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 889641050 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total 889641050 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1847874372 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total 1847874372 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1847874372 # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total 1847874372 # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 744958366 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 744958366 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1919549279 # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1919549279 # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2664507645 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2664507645 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806810 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806810 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953358 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953358 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859281 # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total 0.859281 # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859281 # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total 0.859281 # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 26294.751166 # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 26294.751166 # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 37042.138902 # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 37042.138902 # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 30564.090905 # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 30564.090905 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 30564.090905 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 30564.090905 # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.num_reads 99509 # number of read accesses completed
system.cpu3.num_writes 55322 # number of write accesses completed
system.cpu3.l1c.tags.replacements 22357 # number of replacements
system.cpu3.l1c.tags.tagsinuse 394.352238 # Cycle average of tags in use
system.cpu3.l1c.tags.total_refs 13564 # Total number of references to valid blocks.
system.cpu3.l1c.tags.sampled_refs 22743 # Sample count of references to valid blocks.
system.cpu3.l1c.tags.avg_refs 0.596403 # Average number of references to valid blocks.
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.l1c.tags.occ_blocks::cpu3 394.352238 # Average occupied blocks per requestor
system.cpu3.l1c.tags.occ_percent::cpu3 0.770219 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_percent::total 0.770219 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::0 354 # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
system.cpu3.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id
system.cpu3.l1c.tags.tag_accesses 338647 # Number of tag accesses
system.cpu3.l1c.tags.data_accesses 338647 # Number of data accesses
system.cpu3.l1c.ReadReq_hits::cpu3 8763 # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total 8763 # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3 1221 # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total 1221 # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3 9984 # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total 9984 # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3 9984 # number of overall hits
system.cpu3.l1c.overall_hits::total 9984 # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3 36641 # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total 36641 # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3 23832 # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total 23832 # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3 60473 # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total 60473 # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3 60473 # number of overall misses
system.cpu3.l1c.overall_misses::total 60473 # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3 1024295614 # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total 1024295614 # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3 922064777 # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total 922064777 # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3 1946360391 # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total 1946360391 # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3 1946360391 # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total 1946360391 # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3 45404 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total 45404 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3 25053 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total 25053 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3 70457 # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total 70457 # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3 70457 # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total 70457 # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.806999 # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total 0.806999 # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.951263 # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total 0.951263 # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3 0.858297 # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total 0.858297 # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3 0.858297 # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total 0.858297 # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 27954.903360 # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 27954.903360 # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38690.197088 # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 38690.197088 # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 32185.609958 # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 32185.609958 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 32185.609958 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 32185.609958 # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs 1061792 # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.l1c.blocked::no_mshrs 61430 # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_mshrs 17.284584 # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
system.cpu3.l1c.writebacks::writebacks 9814 # number of writebacks
system.cpu3.l1c.writebacks::total 9814 # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36641 # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total 36641 # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23832 # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total 23832 # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3 60473 # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total 60473 # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3 60473 # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total 60473 # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 968238306 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total 968238306 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 885855695 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total 885855695 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1854094001 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total 1854094001 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1854094001 # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total 1854094001 # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 733819505 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 733819505 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1976786114 # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1976786114 # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2710605619 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2710605619 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806999 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806999 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.951263 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.951263 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858297 # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total 0.858297 # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858297 # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total 0.858297 # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 26424.996752 # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 26424.996752 # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37170.849908 # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37170.849908 # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 30659.864750 # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 30659.864750 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 30659.864750 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 30659.864750 # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu4.num_reads 99688 # number of read accesses completed
system.cpu4.num_writes 55538 # number of write accesses completed
system.cpu4.l1c.tags.replacements 22215 # number of replacements
system.cpu4.l1c.tags.tagsinuse 391.788113 # Cycle average of tags in use
system.cpu4.l1c.tags.total_refs 13621 # Total number of references to valid blocks.
system.cpu4.l1c.tags.sampled_refs 22618 # Sample count of references to valid blocks.
system.cpu4.l1c.tags.avg_refs 0.602219 # Average number of references to valid blocks.
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu4.l1c.tags.occ_blocks::cpu4 391.788113 # Average occupied blocks per requestor
system.cpu4.l1c.tags.occ_percent::cpu4 0.765211 # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_percent::total 0.765211 # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_task_id_blocks::1024 403 # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::0 365 # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
system.cpu4.l1c.tags.occ_task_id_percent::1024 0.787109 # Percentage of cache occupancy per task id
system.cpu4.l1c.tags.tag_accesses 338206 # Number of tag accesses
system.cpu4.l1c.tags.data_accesses 338206 # Number of data accesses
system.cpu4.l1c.ReadReq_hits::cpu4 8861 # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total 8861 # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4 1198 # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total 1198 # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4 10059 # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total 10059 # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4 10059 # number of overall hits
system.cpu4.l1c.overall_hits::total 10059 # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4 36318 # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total 36318 # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4 24000 # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total 24000 # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4 60318 # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total 60318 # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4 60318 # number of overall misses
system.cpu4.l1c.overall_misses::total 60318 # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4 1007698293 # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total 1007698293 # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4 930213172 # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total 930213172 # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4 1937911465 # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total 1937911465 # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4 1937911465 # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total 1937911465 # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4 45179 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total 45179 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4 25198 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total 25198 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4 70377 # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total 70377 # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4 70377 # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total 70377 # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.803869 # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total 0.803869 # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952457 # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total 0.952457 # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4 0.857070 # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total 0.857070 # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4 0.857070 # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total 0.857070 # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 27746.524946 # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 27746.524946 # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 38758.882167 # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 38758.882167 # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 32128.244720 # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 32128.244720 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 32128.244720 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 32128.244720 # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs 1066740 # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu4.l1c.blocked::no_mshrs 61639 # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_mshrs 17.306251 # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
system.cpu4.l1c.writebacks::writebacks 9826 # number of writebacks
system.cpu4.l1c.writebacks::total 9826 # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36318 # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total 36318 # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24000 # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total 24000 # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4 60318 # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total 60318 # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4 60318 # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total 60318 # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 952156937 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total 952156937 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 893690718 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total 893690718 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1845847655 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total 1845847655 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1845847655 # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total 1845847655 # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 748268844 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 748268844 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1945456088 # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1945456088 # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2693724932 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2693724932 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.803869 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.803869 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952457 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952457 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857070 # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total 0.857070 # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857070 # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total 0.857070 # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 26217.218377 # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 26217.218377 # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 37237.113250 # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 37237.113250 # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 30601.937316 # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 30601.937316 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 30601.937316 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 30601.937316 # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu5.num_reads 98777 # number of read accesses completed
system.cpu5.num_writes 55102 # number of write accesses completed
system.cpu5.l1c.tags.replacements 22389 # number of replacements
system.cpu5.l1c.tags.tagsinuse 394.368473 # Cycle average of tags in use
system.cpu5.l1c.tags.total_refs 13612 # Total number of references to valid blocks.
system.cpu5.l1c.tags.sampled_refs 22785 # Sample count of references to valid blocks.
system.cpu5.l1c.tags.avg_refs 0.597411 # Average number of references to valid blocks.
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu5.l1c.tags.occ_blocks::cpu5 394.368473 # Average occupied blocks per requestor
system.cpu5.l1c.tags.occ_percent::cpu5 0.770251 # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_percent::total 0.770251 # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
system.cpu5.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id
system.cpu5.l1c.tags.tag_accesses 338353 # Number of tag accesses
system.cpu5.l1c.tags.data_accesses 338353 # Number of data accesses
system.cpu5.l1c.ReadReq_hits::cpu5 8788 # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total 8788 # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5 1200 # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total 1200 # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5 9988 # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total 9988 # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5 9988 # number of overall hits
system.cpu5.l1c.overall_hits::total 9988 # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5 36608 # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total 36608 # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5 23815 # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total 23815 # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5 60423 # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total 60423 # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5 60423 # number of overall misses
system.cpu5.l1c.overall_misses::total 60423 # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5 1017800983 # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total 1017800983 # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5 926597102 # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total 926597102 # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5 1944398085 # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total 1944398085 # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5 1944398085 # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total 1944398085 # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5 45396 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total 45396 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5 25015 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total 25015 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5 70411 # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total 70411 # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5 70411 # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total 70411 # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806415 # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total 0.806415 # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952029 # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total 0.952029 # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5 0.858147 # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total 0.858147 # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5 0.858147 # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total 0.858147 # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 27802.692936 # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 27802.692936 # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 38908.129414 # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 38908.129414 # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 32179.767390 # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 32179.767390 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 32179.767390 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 32179.767390 # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs 1064852 # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu5.l1c.blocked::no_mshrs 61539 # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_mshrs 17.303694 # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
system.cpu5.l1c.writebacks::writebacks 9851 # number of writebacks
system.cpu5.l1c.writebacks::total 9851 # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36608 # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total 36608 # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23815 # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total 23815 # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5 60423 # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total 60423 # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5 60423 # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total 60423 # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 961777191 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total 961777191 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 890427492 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total 890427492 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1852204683 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total 1852204683 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1852204683 # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total 1852204683 # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 736504009 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 736504009 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1948720715 # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1948720715 # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2685224724 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2685224724 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806415 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806415 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952029 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952029 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858147 # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total 0.858147 # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858147 # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total 0.858147 # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 26272.322744 # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 26272.322744 # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 37389.355112 # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 37389.355112 # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 30653.967579 # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 30653.967579 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 30653.967579 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 30653.967579 # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu6.num_reads 99339 # number of read accesses completed
system.cpu6.num_writes 55520 # number of write accesses completed
system.cpu6.l1c.tags.replacements 22403 # number of replacements
system.cpu6.l1c.tags.tagsinuse 393.263413 # Cycle average of tags in use
system.cpu6.l1c.tags.total_refs 13582 # Total number of references to valid blocks.
system.cpu6.l1c.tags.sampled_refs 22789 # Sample count of references to valid blocks.
system.cpu6.l1c.tags.avg_refs 0.595989 # Average number of references to valid blocks.
system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu6.l1c.tags.occ_blocks::cpu6 393.263413 # Average occupied blocks per requestor
system.cpu6.l1c.tags.occ_percent::cpu6 0.768093 # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_percent::total 0.768093 # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::0 355 # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
system.cpu6.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id
system.cpu6.l1c.tags.tag_accesses 338803 # Number of tag accesses
system.cpu6.l1c.tags.data_accesses 338803 # Number of data accesses
system.cpu6.l1c.ReadReq_hits::cpu6 8815 # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total 8815 # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6 1164 # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total 1164 # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6 9979 # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total 9979 # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6 9979 # number of overall hits
system.cpu6.l1c.overall_hits::total 9979 # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6 36385 # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total 36385 # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6 24126 # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total 24126 # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6 60511 # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total 60511 # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6 60511 # number of overall misses
system.cpu6.l1c.overall_misses::total 60511 # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6 1008730718 # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total 1008730718 # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6 936995994 # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total 936995994 # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6 1945726712 # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total 1945726712 # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6 1945726712 # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total 1945726712 # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6 45200 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total 45200 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6 25290 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total 25290 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6 70490 # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total 70490 # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6 70490 # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total 70490 # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.804978 # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total 0.804978 # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953974 # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total 0.953974 # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6 0.858434 # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total 0.858434 # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6 0.858434 # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total 0.858434 # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 27723.807008 # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 27723.807008 # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 38837.602338 # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 38837.602338 # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 32154.925749 # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 32154.925749 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 32154.925749 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 32154.925749 # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs 1063684 # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu6.l1c.blocked::no_mshrs 61545 # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_mshrs 17.283029 # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
system.cpu6.l1c.writebacks::writebacks 9842 # number of writebacks
system.cpu6.l1c.writebacks::total 9842 # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36385 # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total 36385 # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24126 # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total 24126 # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6 60511 # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total 60511 # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6 60511 # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total 60511 # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 953086366 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total 953086366 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 900293024 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total 900293024 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1853379390 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total 1853379390 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1853379390 # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total 1853379390 # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 738599910 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 738599910 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1965255677 # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1965255677 # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2703855587 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2703855587 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.804978 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.804978 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953974 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953974 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858434 # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total 0.858434 # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858434 # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total 0.858434 # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 26194.485805 # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 26194.485805 # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 37316.298765 # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 37316.298765 # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 30628.801210 # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 30628.801210 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 30628.801210 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 30628.801210 # average overall mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu7.num_reads 99565 # number of read accesses completed
system.cpu7.num_writes 55051 # number of write accesses completed
system.cpu7.l1c.tags.replacements 22600 # number of replacements
system.cpu7.l1c.tags.tagsinuse 394.642544 # Cycle average of tags in use
system.cpu7.l1c.tags.total_refs 13380 # Total number of references to valid blocks.
system.cpu7.l1c.tags.sampled_refs 22986 # Sample count of references to valid blocks.
system.cpu7.l1c.tags.avg_refs 0.582093 # Average number of references to valid blocks.
system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu7.l1c.tags.occ_blocks::cpu7 394.642544 # Average occupied blocks per requestor
system.cpu7.l1c.tags.occ_percent::cpu7 0.770786 # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_percent::total 0.770786 # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::0 349 # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id
system.cpu7.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id
system.cpu7.l1c.tags.tag_accesses 338392 # Number of tag accesses
system.cpu7.l1c.tags.data_accesses 338392 # Number of data accesses
system.cpu7.l1c.ReadReq_hits::cpu7 8664 # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total 8664 # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7 1142 # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total 1142 # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7 9806 # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total 9806 # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7 9806 # number of overall hits
system.cpu7.l1c.overall_hits::total 9806 # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7 36635 # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total 36635 # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7 23923 # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total 23923 # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7 60558 # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total 60558 # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7 60558 # number of overall misses
system.cpu7.l1c.overall_misses::total 60558 # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7 1023029462 # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total 1023029462 # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7 929610099 # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total 929610099 # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7 1952639561 # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total 1952639561 # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7 1952639561 # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total 1952639561 # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7 45299 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total 45299 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7 25065 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total 25065 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7 70364 # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total 70364 # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7 70364 # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total 70364 # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.808737 # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total 0.808737 # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954438 # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total 0.954438 # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7 0.860639 # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total 0.860639 # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7 0.860639 # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total 0.860639 # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 27924.920486 # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 27924.920486 # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 38858.424905 # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 38858.424905 # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 32244.122346 # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 32244.122346 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 32244.122346 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 32244.122346 # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs 1066072 # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu7.l1c.blocked::no_mshrs 61535 # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_mshrs 17.324645 # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
system.cpu7.l1c.writebacks::writebacks 9831 # number of writebacks
system.cpu7.l1c.writebacks::total 9831 # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36635 # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total 36635 # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23923 # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total 23923 # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7 60558 # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total 60558 # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7 60558 # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total 60558 # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 966974672 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total 966974672 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 893289987 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total 893289987 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1860264659 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total 1860264659 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1860264659 # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total 1860264659 # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 731988929 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 731988929 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1960595657 # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1960595657 # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2692584586 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2692584586 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.808737 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.808737 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954438 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954438 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860639 # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total 0.860639 # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860639 # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total 0.860639 # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 26394.832046 # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 26394.832046 # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 37340.215985 # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 37340.215985 # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 30718.726824 # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 30718.726824 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 30718.726824 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 30718.726824 # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 12974 # number of replacements
system.l2c.tags.tagsinuse 782.339791 # Cycle average of tags in use
system.l2c.tags.total_refs 149980 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 13746 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 10.910810 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 728.962494 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0 6.892190 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1 7.186949 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2 6.375204 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3 6.806314 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu4 6.399875 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu5 6.389081 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu6 6.432209 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu7 6.895475 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.711877 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0 0.006731 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1 0.007019 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2 0.006226 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3 0.006647 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu4 0.006250 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu5 0.006239 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu6 0.006281 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu7 0.006734 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.764004 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 772 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 551 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 1963370 # Number of tag accesses
system.l2c.tags.data_accesses 1963370 # Number of data accesses
system.l2c.ReadReq_hits::cpu0 10704 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1 10790 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2 10626 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3 10750 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu4 10729 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu5 10684 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu6 10653 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu7 10669 # number of ReadReq hits
system.l2c.ReadReq_hits::total 85605 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 75955 # number of Writeback hits
system.l2c.Writeback_hits::total 75955 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0 335 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1 339 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2 335 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3 336 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4 340 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5 357 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6 325 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7 325 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 2692 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0 1953 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1 1945 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2 1922 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3 1952 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4 1880 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5 1895 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6 1918 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7 1918 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 15383 # number of ReadExReq hits
system.l2c.demand_hits::cpu0 12657 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1 12735 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2 12548 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3 12702 # number of demand (read+write) hits
system.l2c.demand_hits::cpu4 12609 # number of demand (read+write) hits
system.l2c.demand_hits::cpu5 12579 # number of demand (read+write) hits
system.l2c.demand_hits::cpu6 12571 # number of demand (read+write) hits
system.l2c.demand_hits::cpu7 12587 # number of demand (read+write) hits
system.l2c.demand_hits::total 100988 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0 12657 # number of overall hits
system.l2c.overall_hits::cpu1 12735 # number of overall hits
system.l2c.overall_hits::cpu2 12548 # number of overall hits
system.l2c.overall_hits::cpu3 12702 # number of overall hits
system.l2c.overall_hits::cpu4 12609 # number of overall hits
system.l2c.overall_hits::cpu5 12579 # number of overall hits
system.l2c.overall_hits::cpu6 12571 # number of overall hits
system.l2c.overall_hits::cpu7 12587 # number of overall hits
system.l2c.overall_hits::total 100988 # number of overall hits
system.l2c.ReadReq_misses::cpu0 670 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1 709 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2 686 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3 695 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu4 670 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu5 684 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu6 670 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu7 712 # number of ReadReq misses
system.l2c.ReadReq_misses::total 5496 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0 1986 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1 1941 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2 1876 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3 1923 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4 1955 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5 1959 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6 1992 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7 1968 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 15600 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0 4451 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1 4405 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2 4381 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3 4368 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4 4432 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5 4389 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6 4443 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7 4389 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 35258 # number of ReadExReq misses
system.l2c.demand_misses::cpu0 5121 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1 5114 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2 5067 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3 5063 # number of demand (read+write) misses
system.l2c.demand_misses::cpu4 5102 # number of demand (read+write) misses
system.l2c.demand_misses::cpu5 5073 # number of demand (read+write) misses
system.l2c.demand_misses::cpu6 5113 # number of demand (read+write) misses
system.l2c.demand_misses::cpu7 5101 # number of demand (read+write) misses
system.l2c.demand_misses::total 40754 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0 5121 # number of overall misses
system.l2c.overall_misses::cpu1 5114 # number of overall misses
system.l2c.overall_misses::cpu2 5067 # number of overall misses
system.l2c.overall_misses::cpu3 5063 # number of overall misses
system.l2c.overall_misses::cpu4 5102 # number of overall misses
system.l2c.overall_misses::cpu5 5073 # number of overall misses
system.l2c.overall_misses::cpu6 5113 # number of overall misses
system.l2c.overall_misses::cpu7 5101 # number of overall misses
system.l2c.overall_misses::total 40754 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0 40741945 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1 44011935 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2 41982431 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3 42625443 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu4 40765941 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu5 42066438 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu6 41647921 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu7 44074423 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 337916477 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0 57100999 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1 55902999 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2 53747499 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3 56068000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4 57148499 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5 57843500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6 58231500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7 56606999 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 452649995 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0 243244959 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1 240870461 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2 239571460 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3 239260458 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4 242194954 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5 240150463 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6 242838464 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7 239503467 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 1927634686 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0 283986904 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1 284882396 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2 281553891 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3 281885901 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4 282960895 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5 282216901 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6 284486385 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7 283577890 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 2265551163 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0 283986904 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1 284882396 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2 281553891 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3 281885901 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4 282960895 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5 282216901 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6 284486385 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7 283577890 # number of overall miss cycles
system.l2c.overall_miss_latency::total 2265551163 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0 11374 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1 11499 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2 11312 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3 11445 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu4 11399 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu5 11368 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu6 11323 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu7 11381 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 91101 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 75955 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 75955 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0 2321 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1 2280 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2 2211 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3 2259 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4 2295 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5 2316 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6 2317 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7 2293 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 18292 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0 6404 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1 6350 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2 6303 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3 6320 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4 6312 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5 6284 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6 6361 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7 6307 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 50641 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0 17778 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1 17849 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2 17615 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3 17765 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4 17711 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5 17652 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6 17684 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7 17688 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 141742 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0 17778 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1 17849 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2 17615 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3 17765 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4 17711 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5 17652 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6 17684 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7 17688 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 141742 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0 0.058906 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1 0.061658 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2 0.060644 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3 0.060725 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu4 0.058777 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu5 0.060169 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu6 0.059172 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu7 0.062560 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.060329 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0 0.855666 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1 0.851316 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2 0.848485 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3 0.851262 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4 0.851852 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5 0.845855 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6 0.859732 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7 0.858264 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.852832 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0 0.695034 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1 0.693701 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2 0.695066 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3 0.691139 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4 0.702155 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5 0.698440 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6 0.698475 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7 0.695893 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.696234 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0 0.288053 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1 0.286515 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2 0.287653 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3 0.284999 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4 0.288070 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5 0.287390 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6 0.289131 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7 0.288388 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.287522 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0 0.288053 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1 0.286515 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2 0.287653 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3 0.284999 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4 0.288070 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5 0.287390 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6 0.289131 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7 0.288388 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.287522 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0 60808.873134 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1 62076.071932 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2 61198.879009 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3 61331.572662 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu4 60844.688060 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu5 61500.640351 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu6 62161.076119 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu7 61902.279494 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 61484.075146 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0 28751.761833 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 28801.132921 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 28650.052772 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 29156.526261 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 29231.968798 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 29527.054620 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 29232.680723 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 28763.719004 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 29016.025321 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 54649.507751 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 54681.148922 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 54684.195389 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 54775.745879 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 54646.875903 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 54716.441786 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 54656.417736 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 54569.028708 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 54672.264054 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 55455.361062 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 55706.373876 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 55566.191237 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 55675.666798 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 55460.779106 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 55631.165188 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 55639.817133 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 55592.607332 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 55590.890784 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 55455.361062 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 55706.373876 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 55566.191237 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 55675.666798 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 55460.779106 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 55631.165188 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 55639.817133 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 55592.607332 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 55590.890784 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 10498 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 1439 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs 7.295344 # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 6042 # number of writebacks
system.l2c.writebacks::total 6042 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0 8 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1 4 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2 8 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3 4 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu4 7 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu5 7 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu6 8 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu7 5 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::total 3 # number of UpgradeReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu0 6 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu1 5 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu3 1 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu4 2 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5 2 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu6 2 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu7 2 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total 23 # number of ReadExReq MSHR hits
system.l2c.demand_mshr_hits::cpu0 14 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1 9 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2 11 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3 5 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4 9 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5 9 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6 10 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7 7 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0 14 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1 9 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2 11 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3 5 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4 9 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5 9 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6 10 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7 7 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0 662 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1 705 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2 678 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3 691 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu4 663 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu5 677 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu6 662 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu7 707 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 5445 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0 1985 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1 1941 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2 1876 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3 1922 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4 1955 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5 1959 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6 1992 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7 1967 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 15597 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0 4445 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1 4400 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2 4378 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3 4367 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4 4430 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5 4387 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6 4441 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7 4387 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 35235 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0 5107 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1 5105 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2 5056 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3 5058 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4 5093 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5 5064 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6 5103 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7 5094 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 40680 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0 5107 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1 5105 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2 5056 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3 5058 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4 5093 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5 5064 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6 5103 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7 5094 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 40680 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0 32455941 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1 35292936 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2 33520926 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3 34166439 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu4 32539439 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu5 33571932 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu6 33370421 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu7 35357421 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 270275455 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0 83067491 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1 81344988 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2 78653997 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3 80593493 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4 81980984 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5 82268488 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6 83402478 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7 82404992 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 653716911 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0 189131446 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1 187405945 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2 186408946 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3 186284944 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4 188429940 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5 186911948 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6 188992946 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7 186252939 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1499819054 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0 221587387 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1 222698881 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2 219929872 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3 220451383 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4 220969379 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5 220483880 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6 222363367 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7 221610360 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 1770094509 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0 221587387 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1 222698881 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2 219929872 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3 220451383 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4 220969379 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5 220483880 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6 222363367 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7 221610360 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 1770094509 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 412646911 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 419015931 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 413234441 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 407408946 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 415648431 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 408376439 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 410035928 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 406831940 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 3293198967 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 229215970 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 228786954 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 227259971 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 236423452 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 233573451 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 234334469 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 233635458 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 232899980 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 1856129705 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0 641862881 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1 647802885 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2 640494412 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3 643832398 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4 649221882 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5 642710908 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6 643671386 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7 639731920 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 5149328672 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0 0.058203 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1 0.061310 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2 0.059936 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3 0.060376 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu4 0.058163 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu5 0.059553 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu6 0.058465 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu7 0.062121 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.059769 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.855235 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.851316 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.848485 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.850819 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.851852 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.845855 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.859732 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.857828 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.852668 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.694097 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.692913 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.694590 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.690981 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.701838 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.698122 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.698161 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.695576 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.695780 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0 0.287265 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1 0.286010 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2 0.287028 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3 0.284717 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4 0.287561 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5 0.286880 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6 0.288566 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7 0.287992 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.287000 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0 0.287265 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1 0.286010 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2 0.287028 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3 0.284717 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4 0.287561 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5 0.286880 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6 0.288566 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7 0.287992 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.287000 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 49027.101208 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50060.902128 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49440.893805 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49444.918958 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49079.093514 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49589.264402 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 50408.490937 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50010.496464 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 49637.365473 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41847.602519 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41908.803709 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41926.437633 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41932.098335 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41934.007161 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41995.144461 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41868.713855 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41893.742755 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41912.990383 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 42549.256693 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 42592.260227 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42578.562357 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42657.417907 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42534.975169 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42605.869159 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 42556.394055 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42455.650558 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 42566.171534 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 43388.953789 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 43623.678942 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 43498.787975 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 43584.694148 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 43386.879835 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 43539.470774 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 43575.027827 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 43504.193168 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 43512.647714 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 43388.953789 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 43623.678942 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 43498.787975 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 43584.694148 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 43386.879835 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 43539.470774 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 43575.027827 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 43504.193168 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 43512.647714 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.snoop_filter.tot_requests 123330 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 121282 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.trans_dist::ReadReq 84079 # Transaction distribution
system.membus.trans_dist::ReadResp 84076 # Transaction distribution
system.membus.trans_dist::WriteReq 43401 # Transaction distribution
system.membus.trans_dist::WriteResp 43399 # Transaction distribution
system.membus.trans_dist::Writeback 6042 # Transaction distribution
system.membus.trans_dist::UpgradeReq 58662 # Transaction distribution
system.membus.trans_dist::UpgradeResp 47800 # Transaction distribution
system.membus.trans_dist::ReadExReq 50251 # Transaction distribution
system.membus.trans_dist::ReadExResp 3038 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 420748 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 420748 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1051128 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1051128 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 58073 # Total snoops (count)
system.membus.snoop_fanout::samples 123330 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 123330 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 123330 # Request fanout histogram
system.membus.reqLayer0.occupancy 349185814 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 47.8 # Layer utilization (%)
system.membus.respLayer0.occupancy 311191349 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 42.6 # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests 561297 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 261699 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 297550 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq 370588 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 370576 # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 43402 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 43399 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 75955 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 29152 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 29150 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 162499 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 162497 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120510 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120652 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120226 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120519 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120569 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120393 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120447 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120346 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 963662 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1766434 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1757944 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1752931 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1758190 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1756878 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1755329 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1752897 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1753790 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 14054393 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 323559 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 561297 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.683086 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 1.176196 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 53942 9.61% 9.61% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 251180 44.75% 54.36% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 141382 25.19% 79.55% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 68926 12.28% 91.83% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 30158 5.37% 97.20% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 11557 2.06% 99.26% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 3492 0.62% 99.88% # Request fanout histogram
system.toL2Bus.snoop_fanout::7 660 0.12% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 561297 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 720580520 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 98.7 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 100512947 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 13.8 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 100775889 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 13.8 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 100644932 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 13.8 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 100575951 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 13.8 # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy 100528413 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 13.8 # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy 100450921 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 13.8 # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy 100623449 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 13.8 # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy 100655480 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 13.8 # Layer utilization (%)
---------- End Simulation Statistics ----------
|