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|
---------- Begin Simulation Statistics ----------
sim_seconds 0.000541 # Number of seconds simulated
sim_ticks 540820000 # Number of ticks simulated
final_tick 540820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_tick_rate 74356212 # Simulator tick rate (ticks/s)
host_mem_usage 274932 # Number of bytes of host memory used
host_seconds 7.27 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0 88157 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1 82701 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2 84142 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3 82645 # Number of bytes read from this memory
system.physmem.bytes_read::cpu4 83993 # Number of bytes read from this memory
system.physmem.bytes_read::cpu5 79749 # Number of bytes read from this memory
system.physmem.bytes_read::cpu6 78765 # Number of bytes read from this memory
system.physmem.bytes_read::cpu7 84222 # Number of bytes read from this memory
system.physmem.bytes_read::total 664374 # Number of bytes read from this memory
system.physmem.bytes_written::writebacks 426368 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0 5567 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1 5462 # Number of bytes written to this memory
system.physmem.bytes_written::cpu2 5416 # Number of bytes written to this memory
system.physmem.bytes_written::cpu3 5447 # Number of bytes written to this memory
system.physmem.bytes_written::cpu4 5329 # Number of bytes written to this memory
system.physmem.bytes_written::cpu5 5472 # Number of bytes written to this memory
system.physmem.bytes_written::cpu6 5531 # Number of bytes written to this memory
system.physmem.bytes_written::cpu7 5421 # Number of bytes written to this memory
system.physmem.bytes_written::total 470013 # Number of bytes written to this memory
system.physmem.num_reads::cpu0 11108 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1 10881 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2 10936 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3 10951 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4 11102 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5 10890 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6 10914 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7 11079 # Number of read requests responded to by this memory
system.physmem.num_reads::total 87861 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 6662 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0 5567 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1 5462 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2 5416 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3 5447 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4 5329 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5 5472 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6 5531 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7 5421 # Number of write requests responded to by this memory
system.physmem.num_writes::total 50307 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0 163006176 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1 152917792 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2 155582264 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3 152814245 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4 155306756 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5 147459413 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6 145639954 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7 155730187 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1228456788 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 788373211 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0 10293628 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1 10099479 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2 10014423 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3 10071743 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4 9853556 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5 10117969 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6 10227063 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7 10023668 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 869074738 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 788373211 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0 173299804 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1 163017270 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2 165596687 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3 162885988 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4 165160312 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5 157577382 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6 155867017 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7 165753855 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2097531526 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.num_reads 99596 # number of read accesses completed
system.cpu0.num_writes 55268 # number of write accesses completed
system.cpu0.l1c.tags.replacements 22066 # number of replacements
system.cpu0.l1c.tags.tagsinuse 391.486377 # Cycle average of tags in use
system.cpu0.l1c.tags.total_refs 13717 # Total number of references to valid blocks.
system.cpu0.l1c.tags.sampled_refs 22459 # Sample count of references to valid blocks.
system.cpu0.l1c.tags.avg_refs 0.610757 # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.l1c.tags.occ_blocks::cpu0 391.486377 # Average occupied blocks per requestor
system.cpu0.l1c.tags.occ_percent::cpu0 0.764622 # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_percent::total 0.764622 # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id
system.cpu0.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id
system.cpu0.l1c.tags.tag_accesses 338295 # Number of tag accesses
system.cpu0.l1c.tags.data_accesses 338295 # Number of data accesses
system.cpu0.l1c.ReadReq_hits::cpu0 8878 # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total 8878 # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0 1162 # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total 1162 # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0 10040 # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total 10040 # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0 10040 # number of overall hits
system.cpu0.l1c.overall_hits::total 10040 # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0 36478 # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total 36478 # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0 23899 # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total 23899 # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0 60377 # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total 60377 # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0 60377 # number of overall misses
system.cpu0.l1c.overall_misses::total 60377 # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0 603408975 # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total 603408975 # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0 722750184 # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total 722750184 # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0 1326159159 # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total 1326159159 # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0 1326159159 # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total 1326159159 # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0 45356 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total 45356 # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0 25061 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total 25061 # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0 70417 # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total 70417 # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0 70417 # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total 70417 # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.804260 # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total 0.804260 # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953633 # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total 0.953633 # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0 0.857421 # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total 0.857421 # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0 0.857421 # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total 0.857421 # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16541.723093 # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 16541.723093 # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 30241.858823 # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 30241.858823 # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 21964.641486 # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 21964.641486 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 21964.641486 # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 21964.641486 # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs 828428 # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l1c.blocked::no_mshrs 62795 # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_mshrs 13.192579 # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
system.cpu0.l1c.writebacks::writebacks 9669 # number of writebacks
system.cpu0.l1c.writebacks::total 9669 # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36478 # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total 36478 # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23899 # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total 23899 # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0 60377 # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total 60377 # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0 60377 # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total 60377 # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9885 # number of ReadReq MSHR uncacheable
system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9885 # number of ReadReq MSHR uncacheable
system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5567 # number of WriteReq MSHR uncacheable
system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5567 # number of WriteReq MSHR uncacheable
system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15452 # number of overall MSHR uncacheable misses
system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15452 # number of overall MSHR uncacheable misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 566933975 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total 566933975 # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 698852184 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total 698852184 # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1265786159 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total 1265786159 # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1265786159 # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total 1265786159 # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 722511018 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 722511018 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 853790554 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 853790554 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1576301572 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1576301572 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.804260 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.804260 # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953633 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953633 # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.857421 # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total 0.857421 # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.857421 # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total 0.857421 # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15541.805335 # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15541.805335 # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 29241.900665 # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 29241.900665 # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20964.707736 # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20964.707736 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20964.707736 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20964.707736 # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 73091.655842 # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73091.655842 # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 153366.365008 # average WriteReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153366.365008 # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 102012.786177 # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 102012.786177 # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.num_reads 98929 # number of read accesses completed
system.cpu1.num_writes 55238 # number of write accesses completed
system.cpu1.l1c.tags.replacements 22532 # number of replacements
system.cpu1.l1c.tags.tagsinuse 392.132482 # Cycle average of tags in use
system.cpu1.l1c.tags.total_refs 13440 # Total number of references to valid blocks.
system.cpu1.l1c.tags.sampled_refs 22931 # Sample count of references to valid blocks.
system.cpu1.l1c.tags.avg_refs 0.586106 # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l1c.tags.occ_blocks::cpu1 392.132482 # Average occupied blocks per requestor
system.cpu1.l1c.tags.occ_percent::cpu1 0.765884 # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_percent::total 0.765884 # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id
system.cpu1.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id
system.cpu1.l1c.tags.tag_accesses 338385 # Number of tag accesses
system.cpu1.l1c.tags.data_accesses 338385 # Number of data accesses
system.cpu1.l1c.ReadReq_hits::cpu1 8754 # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total 8754 # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1 1152 # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total 1152 # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1 9906 # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total 9906 # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1 9906 # number of overall hits
system.cpu1.l1c.overall_hits::total 9906 # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1 36277 # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total 36277 # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1 24198 # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total 24198 # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1 60475 # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total 60475 # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1 60475 # number of overall misses
system.cpu1.l1c.overall_misses::total 60475 # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1 602891984 # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total 602891984 # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1 733995398 # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total 733995398 # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1 1336887382 # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total 1336887382 # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1 1336887382 # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total 1336887382 # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1 45031 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total 45031 # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1 25350 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total 25350 # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1 70381 # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total 70381 # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1 70381 # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total 70381 # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805601 # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total 0.805601 # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954556 # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total 0.954556 # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1 0.859252 # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total 0.859252 # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1 0.859252 # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total 0.859252 # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16619.124624 # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 16619.124624 # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 30332.895198 # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 30332.895198 # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 22106.446995 # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 22106.446995 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 22106.446995 # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 22106.446995 # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs 828861 # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_mshrs 62856 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_mshrs 13.186665 # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
system.cpu1.l1c.writebacks::writebacks 9918 # number of writebacks
system.cpu1.l1c.writebacks::total 9918 # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36277 # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total 36277 # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1 24198 # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total 24198 # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1 60475 # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total 60475 # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1 60475 # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total 60475 # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9741 # number of ReadReq MSHR uncacheable
system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9741 # number of ReadReq MSHR uncacheable
system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5463 # number of WriteReq MSHR uncacheable
system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5463 # number of WriteReq MSHR uncacheable
system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15204 # number of overall MSHR uncacheable misses
system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15204 # number of overall MSHR uncacheable misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 566614984 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total 566614984 # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 709800398 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total 709800398 # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1276415382 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total 1276415382 # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1276415382 # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total 1276415382 # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 713705140 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 713705140 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 858653101 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 858653101 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1572358241 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1572358241 # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805601 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805601 # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954556 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954556 # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859252 # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total 0.859252 # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859252 # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total 0.859252 # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15619.124624 # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15619.124624 # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 29333.019175 # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 29333.019175 # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 21106.496602 # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 21106.496602 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 21106.496602 # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 21106.496602 # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 73268.159327 # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73268.159327 # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 157176.112209 # average WriteReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157176.112209 # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 103417.406012 # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 103417.406012 # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.num_reads 99726 # number of read accesses completed
system.cpu2.num_writes 55227 # number of write accesses completed
system.cpu2.l1c.tags.replacements 22340 # number of replacements
system.cpu2.l1c.tags.tagsinuse 393.100704 # Cycle average of tags in use
system.cpu2.l1c.tags.total_refs 13463 # Total number of references to valid blocks.
system.cpu2.l1c.tags.sampled_refs 22750 # Sample count of references to valid blocks.
system.cpu2.l1c.tags.avg_refs 0.591780 # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.l1c.tags.occ_blocks::cpu2 393.100704 # Average occupied blocks per requestor
system.cpu2.l1c.tags.occ_percent::cpu2 0.767775 # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_percent::total 0.767775 # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::0 400 # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
system.cpu2.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id
system.cpu2.l1c.tags.tag_accesses 338035 # Number of tag accesses
system.cpu2.l1c.tags.data_accesses 338035 # Number of data accesses
system.cpu2.l1c.ReadReq_hits::cpu2 8657 # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total 8657 # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2 1109 # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total 1109 # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2 9766 # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total 9766 # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2 9766 # number of overall hits
system.cpu2.l1c.overall_hits::total 9766 # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2 36622 # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total 36622 # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2 23922 # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total 23922 # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2 60544 # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total 60544 # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2 60544 # number of overall misses
system.cpu2.l1c.overall_misses::total 60544 # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2 606579368 # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total 606579368 # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2 739451035 # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total 739451035 # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2 1346030403 # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total 1346030403 # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2 1346030403 # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total 1346030403 # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2 45279 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total 45279 # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2 25031 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total 25031 # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2 70310 # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total 70310 # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2 70310 # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total 70310 # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808808 # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total 0.808808 # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955695 # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total 0.955695 # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2 0.861101 # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total 0.861101 # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2 0.861101 # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total 0.861101 # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16563.250724 # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 16563.250724 # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 30910.920283 # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 30910.920283 # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 22232.267491 # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 22232.267491 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 22232.267491 # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 22232.267491 # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs 834628 # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.l1c.blocked::no_mshrs 63193 # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_mshrs 13.207602 # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
system.cpu2.l1c.writebacks::writebacks 9768 # number of writebacks
system.cpu2.l1c.writebacks::total 9768 # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36622 # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total 36622 # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23922 # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total 23922 # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2 60544 # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total 60544 # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2 60544 # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total 60544 # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9774 # number of ReadReq MSHR uncacheable
system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9774 # number of ReadReq MSHR uncacheable
system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5417 # number of WriteReq MSHR uncacheable
system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5417 # number of WriteReq MSHR uncacheable
system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15191 # number of overall MSHR uncacheable misses
system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15191 # number of overall MSHR uncacheable misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 569957368 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total 569957368 # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 715531035 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total 715531035 # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1285488403 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total 1285488403 # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1285488403 # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total 1285488403 # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 714145091 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 714145091 # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 834952155 # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 834952155 # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1549097246 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1549097246 # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808808 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808808 # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955695 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955695 # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.861101 # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total 0.861101 # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.861101 # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total 0.861101 # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15563.250724 # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15563.250724 # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 29911.003888 # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 29911.003888 # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 21232.300525 # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 21232.300525 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 21232.300525 # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 21232.300525 # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 73065.796092 # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73065.796092 # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154135.527968 # average WriteReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154135.527968 # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 101974.672240 # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 101974.672240 # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.num_reads 99494 # number of read accesses completed
system.cpu3.num_writes 54686 # number of write accesses completed
system.cpu3.l1c.tags.replacements 22431 # number of replacements
system.cpu3.l1c.tags.tagsinuse 392.658378 # Cycle average of tags in use
system.cpu3.l1c.tags.total_refs 13393 # Total number of references to valid blocks.
system.cpu3.l1c.tags.sampled_refs 22832 # Sample count of references to valid blocks.
system.cpu3.l1c.tags.avg_refs 0.586589 # Average number of references to valid blocks.
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.l1c.tags.occ_blocks::cpu3 392.658378 # Average occupied blocks per requestor
system.cpu3.l1c.tags.occ_percent::cpu3 0.766911 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_percent::total 0.766911 # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id
system.cpu3.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id
system.cpu3.l1c.tags.tag_accesses 337999 # Number of tag accesses
system.cpu3.l1c.tags.data_accesses 337999 # Number of data accesses
system.cpu3.l1c.ReadReq_hits::cpu3 8615 # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total 8615 # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3 1106 # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total 1106 # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3 9721 # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total 9721 # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3 9721 # number of overall hits
system.cpu3.l1c.overall_hits::total 9721 # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3 36594 # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total 36594 # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3 23974 # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total 23974 # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3 60568 # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total 60568 # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3 60568 # number of overall misses
system.cpu3.l1c.overall_misses::total 60568 # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3 607642440 # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total 607642440 # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3 730577546 # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total 730577546 # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3 1338219986 # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total 1338219986 # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3 1338219986 # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total 1338219986 # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3 45209 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total 45209 # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3 25080 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total 25080 # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3 70289 # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total 70289 # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3 70289 # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total 70289 # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.809441 # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total 0.809441 # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955901 # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total 0.955901 # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3 0.861700 # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total 0.861700 # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3 0.861700 # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total 0.861700 # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16604.974586 # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 16604.974586 # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 30473.744306 # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 30473.744306 # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 22094.505118 # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 22094.505118 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 22094.505118 # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 22094.505118 # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs 833585 # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.l1c.blocked::no_mshrs 63208 # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_mshrs 13.187967 # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
system.cpu3.l1c.writebacks::writebacks 9871 # number of writebacks
system.cpu3.l1c.writebacks::total 9871 # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36594 # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total 36594 # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23974 # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total 23974 # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3 60568 # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total 60568 # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3 60568 # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total 60568 # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9814 # number of ReadReq MSHR uncacheable
system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9814 # number of ReadReq MSHR uncacheable
system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5449 # number of WriteReq MSHR uncacheable
system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5449 # number of WriteReq MSHR uncacheable
system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15263 # number of overall MSHR uncacheable misses
system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15263 # number of overall MSHR uncacheable misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 571049440 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total 571049440 # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 706605546 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total 706605546 # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1277654986 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total 1277654986 # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1277654986 # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total 1277654986 # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 718813002 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 718813002 # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 842609106 # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 842609106 # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1561422108 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1561422108 # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.809441 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.809441 # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955901 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955901 # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861700 # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total 0.861700 # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861700 # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total 0.861700 # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15605.001913 # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15605.001913 # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 29473.827730 # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 29473.827730 # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 21094.554649 # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 21094.554649 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 21094.554649 # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 21094.554649 # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 73243.631751 # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73243.631751 # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 154635.548908 # average WriteReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154635.548908 # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 102301.127432 # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 102301.127432 # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu4.num_reads 99490 # number of read accesses completed
system.cpu4.num_writes 54928 # number of write accesses completed
system.cpu4.l1c.tags.replacements 22277 # number of replacements
system.cpu4.l1c.tags.tagsinuse 391.439470 # Cycle average of tags in use
system.cpu4.l1c.tags.total_refs 13388 # Total number of references to valid blocks.
system.cpu4.l1c.tags.sampled_refs 22671 # Sample count of references to valid blocks.
system.cpu4.l1c.tags.avg_refs 0.590534 # Average number of references to valid blocks.
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu4.l1c.tags.occ_blocks::cpu4 391.439470 # Average occupied blocks per requestor
system.cpu4.l1c.tags.occ_percent::cpu4 0.764530 # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_percent::total 0.764530 # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
system.cpu4.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id
system.cpu4.l1c.tags.tag_accesses 337649 # Number of tag accesses
system.cpu4.l1c.tags.data_accesses 337649 # Number of data accesses
system.cpu4.l1c.ReadReq_hits::cpu4 8692 # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total 8692 # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4 1145 # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total 1145 # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4 9837 # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total 9837 # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4 9837 # number of overall hits
system.cpu4.l1c.overall_hits::total 9837 # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4 36462 # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total 36462 # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4 23928 # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total 23928 # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4 60390 # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total 60390 # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4 60390 # number of overall misses
system.cpu4.l1c.overall_misses::total 60390 # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4 604688688 # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total 604688688 # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4 724847511 # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total 724847511 # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4 1329536199 # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total 1329536199 # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4 1329536199 # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total 1329536199 # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4 45154 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total 45154 # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4 25073 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total 25073 # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4 70227 # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total 70227 # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4 70227 # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total 70227 # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807503 # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total 0.807503 # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954333 # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total 0.954333 # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4 0.859926 # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total 0.859926 # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4 0.859926 # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total 0.859926 # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16584.078986 # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 16584.078986 # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 30292.858200 # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 30292.858200 # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 22015.833731 # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 22015.833731 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 22015.833731 # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 22015.833731 # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs 834109 # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu4.l1c.blocked::no_mshrs 63123 # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_mshrs 13.214027 # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
system.cpu4.l1c.writebacks::writebacks 9949 # number of writebacks
system.cpu4.l1c.writebacks::total 9949 # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36462 # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total 36462 # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23928 # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total 23928 # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4 60390 # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total 60390 # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4 60390 # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total 60390 # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9946 # number of ReadReq MSHR uncacheable
system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9946 # number of ReadReq MSHR uncacheable
system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5329 # number of WriteReq MSHR uncacheable
system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5329 # number of WriteReq MSHR uncacheable
system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15275 # number of overall MSHR uncacheable misses
system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15275 # number of overall MSHR uncacheable misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 568228688 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total 568228688 # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 700919511 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total 700919511 # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1269148199 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total 1269148199 # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1269148199 # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total 1269148199 # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 727166434 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 727166434 # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 837934166 # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 837934166 # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1565100600 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1565100600 # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807503 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807503 # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954333 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954333 # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859926 # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total 0.859926 # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859926 # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total 0.859926 # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15584.133838 # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15584.133838 # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 29292.858200 # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 29292.858200 # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 21015.866849 # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 21015.866849 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 21015.866849 # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 21015.866849 # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 73111.445204 # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73111.445204 # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157240.413961 # average WriteReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157240.413961 # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 102461.577741 # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 102461.577741 # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu5.num_reads 99495 # number of read accesses completed
system.cpu5.num_writes 55318 # number of write accesses completed
system.cpu5.l1c.tags.replacements 22409 # number of replacements
system.cpu5.l1c.tags.tagsinuse 392.682039 # Cycle average of tags in use
system.cpu5.l1c.tags.total_refs 13393 # Total number of references to valid blocks.
system.cpu5.l1c.tags.sampled_refs 22790 # Sample count of references to valid blocks.
system.cpu5.l1c.tags.avg_refs 0.587670 # Average number of references to valid blocks.
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu5.l1c.tags.occ_blocks::cpu5 392.682039 # Average occupied blocks per requestor
system.cpu5.l1c.tags.occ_percent::cpu5 0.766957 # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_percent::total 0.766957 # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_task_id_blocks::1024 381 # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
system.cpu5.l1c.tags.occ_task_id_percent::1024 0.744141 # Percentage of cache occupancy per task id
system.cpu5.l1c.tags.tag_accesses 337688 # Number of tag accesses
system.cpu5.l1c.tags.data_accesses 337688 # Number of data accesses
system.cpu5.l1c.ReadReq_hits::cpu5 8637 # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total 8637 # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5 1146 # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total 1146 # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5 9783 # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total 9783 # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5 9783 # number of overall hits
system.cpu5.l1c.overall_hits::total 9783 # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5 36329 # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total 36329 # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5 24118 # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total 24118 # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5 60447 # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total 60447 # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5 60447 # number of overall misses
system.cpu5.l1c.overall_misses::total 60447 # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5 601479868 # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total 601479868 # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5 729882091 # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total 729882091 # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5 1331361959 # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total 1331361959 # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5 1331361959 # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total 1331361959 # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5 44966 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total 44966 # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5 25264 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total 25264 # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5 70230 # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total 70230 # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5 70230 # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total 70230 # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807922 # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total 0.807922 # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954639 # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total 0.954639 # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5 0.860701 # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total 0.860701 # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5 0.860701 # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total 0.860701 # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16556.466404 # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 16556.466404 # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 30262.960901 # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 30262.960901 # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 22025.277665 # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 22025.277665 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 22025.277665 # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 22025.277665 # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs 826632 # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu5.l1c.blocked::no_mshrs 62727 # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_mshrs 13.178249 # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
system.cpu5.l1c.writebacks::writebacks 9995 # number of writebacks
system.cpu5.l1c.writebacks::total 9995 # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36329 # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total 36329 # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24118 # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total 24118 # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5 60447 # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total 60447 # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5 60447 # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total 60447 # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9798 # number of ReadReq MSHR uncacheable
system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9798 # number of ReadReq MSHR uncacheable
system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5473 # number of WriteReq MSHR uncacheable
system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5473 # number of WriteReq MSHR uncacheable
system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15271 # number of overall MSHR uncacheable misses
system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15271 # number of overall MSHR uncacheable misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 565152868 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total 565152868 # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 705764091 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total 705764091 # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1270916959 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total 1270916959 # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1270916959 # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total 1270916959 # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 717311081 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 717311081 # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 861132955 # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 861132955 # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1578444036 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1578444036 # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807922 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807922 # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954639 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954639 # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860701 # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total 0.860701 # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860701 # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total 0.860701 # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15556.521457 # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15556.521457 # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 29262.960901 # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 29262.960901 # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 21025.310752 # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 21025.310752 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 21025.310752 # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 21025.310752 # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 73209.949071 # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73209.949071 # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 157342.034533 # average WriteReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157342.034533 # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 103362.192129 # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 103362.192129 # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu6.num_reads 100000 # number of read accesses completed
system.cpu6.num_writes 55059 # number of write accesses completed
system.cpu6.l1c.tags.replacements 22318 # number of replacements
system.cpu6.l1c.tags.tagsinuse 390.741535 # Cycle average of tags in use
system.cpu6.l1c.tags.total_refs 13451 # Total number of references to valid blocks.
system.cpu6.l1c.tags.sampled_refs 22720 # Sample count of references to valid blocks.
system.cpu6.l1c.tags.avg_refs 0.592033 # Average number of references to valid blocks.
system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu6.l1c.tags.occ_blocks::cpu6 390.741535 # Average occupied blocks per requestor
system.cpu6.l1c.tags.occ_percent::cpu6 0.763167 # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_percent::total 0.763167 # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
system.cpu6.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
system.cpu6.l1c.tags.tag_accesses 338536 # Number of tag accesses
system.cpu6.l1c.tags.data_accesses 338536 # Number of data accesses
system.cpu6.l1c.ReadReq_hits::cpu6 8731 # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total 8731 # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6 1150 # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total 1150 # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6 9881 # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total 9881 # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6 9881 # number of overall hits
system.cpu6.l1c.overall_hits::total 9881 # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6 36733 # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total 36733 # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6 23795 # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total 23795 # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6 60528 # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total 60528 # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6 60528 # number of overall misses
system.cpu6.l1c.overall_misses::total 60528 # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6 609896687 # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total 609896687 # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6 716784676 # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total 716784676 # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6 1326681363 # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total 1326681363 # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6 1326681363 # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total 1326681363 # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6 45464 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total 45464 # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6 24945 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total 24945 # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6 70409 # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total 70409 # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6 70409 # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total 70409 # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807958 # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total 0.807958 # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953899 # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total 0.953899 # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6 0.859663 # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total 0.859663 # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6 0.859663 # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total 0.859663 # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16603.508752 # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 16603.508752 # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 30123.331624 # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 30123.331624 # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 21918.473483 # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 21918.473483 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 21918.473483 # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 21918.473483 # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs 822803 # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu6.l1c.blocked::no_mshrs 62827 # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_mshrs 13.096328 # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
system.cpu6.l1c.writebacks::writebacks 9777 # number of writebacks
system.cpu6.l1c.writebacks::total 9777 # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36733 # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total 36733 # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23795 # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total 23795 # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6 60528 # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total 60528 # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6 60528 # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total 60528 # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9837 # number of ReadReq MSHR uncacheable
system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9837 # number of ReadReq MSHR uncacheable
system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5532 # number of WriteReq MSHR uncacheable
system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5532 # number of WriteReq MSHR uncacheable
system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15369 # number of overall MSHR uncacheable misses
system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15369 # number of overall MSHR uncacheable misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 573164687 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total 573164687 # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 692991676 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total 692991676 # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1266156363 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total 1266156363 # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1266156363 # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total 1266156363 # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 718909036 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 718909036 # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 867837123 # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 867837123 # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1586746159 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1586746159 # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807958 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807958 # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953899 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953899 # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859663 # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total 0.859663 # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859663 # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total 0.859663 # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15603.535976 # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15603.535976 # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 29123.415676 # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 29123.415676 # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20918.523047 # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20918.523047 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20918.523047 # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20918.523047 # average overall mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 73082.142523 # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73082.142523 # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 156875.835683 # average WriteReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156875.835683 # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 103243.292277 # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 103243.292277 # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu7.num_reads 99734 # number of read accesses completed
system.cpu7.num_writes 54921 # number of write accesses completed
system.cpu7.l1c.tags.replacements 22329 # number of replacements
system.cpu7.l1c.tags.tagsinuse 392.290074 # Cycle average of tags in use
system.cpu7.l1c.tags.total_refs 13499 # Total number of references to valid blocks.
system.cpu7.l1c.tags.sampled_refs 22713 # Sample count of references to valid blocks.
system.cpu7.l1c.tags.avg_refs 0.594329 # Average number of references to valid blocks.
system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu7.l1c.tags.occ_blocks::cpu7 392.290074 # Average occupied blocks per requestor
system.cpu7.l1c.tags.occ_percent::cpu7 0.766192 # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_percent::total 0.766192 # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id
system.cpu7.l1c.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id
system.cpu7.l1c.tags.tag_accesses 338596 # Number of tag accesses
system.cpu7.l1c.tags.data_accesses 338596 # Number of data accesses
system.cpu7.l1c.ReadReq_hits::cpu7 8795 # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total 8795 # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7 1165 # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total 1165 # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7 9960 # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total 9960 # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7 9960 # number of overall hits
system.cpu7.l1c.overall_hits::total 9960 # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7 36684 # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total 36684 # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7 23790 # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total 23790 # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7 60474 # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total 60474 # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7 60474 # number of overall misses
system.cpu7.l1c.overall_misses::total 60474 # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7 611011013 # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total 611011013 # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7 715403706 # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total 715403706 # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7 1326414719 # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total 1326414719 # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7 1326414719 # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total 1326414719 # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7 45479 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total 45479 # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7 24955 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total 24955 # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7 70434 # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total 70434 # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7 70434 # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total 70434 # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806614 # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total 0.806614 # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953316 # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total 0.953316 # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7 0.858591 # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total 0.858591 # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7 0.858591 # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total 0.858591 # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16656.062943 # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 16656.062943 # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 30071.614376 # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 30071.614376 # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 21933.636257 # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 21933.636257 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 21933.636257 # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 21933.636257 # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs 829723 # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu7.l1c.blocked::no_mshrs 63058 # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_mshrs 13.158093 # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
system.cpu7.l1c.writebacks::writebacks 9746 # number of writebacks
system.cpu7.l1c.writebacks::total 9746 # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36684 # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total 36684 # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23790 # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total 23790 # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7 60474 # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total 60474 # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7 60474 # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total 60474 # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9918 # number of ReadReq MSHR uncacheable
system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9918 # number of ReadReq MSHR uncacheable
system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5421 # number of WriteReq MSHR uncacheable
system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5421 # number of WriteReq MSHR uncacheable
system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15339 # number of overall MSHR uncacheable misses
system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15339 # number of overall MSHR uncacheable misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 574327013 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total 574327013 # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 691615706 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total 691615706 # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1265942719 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total 1265942719 # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1265942719 # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total 1265942719 # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 726668427 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 726668427 # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 847371643 # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 847371643 # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1574040070 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1574040070 # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806614 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806614 # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953316 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953316 # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858591 # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total 0.858591 # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858591 # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total 0.858591 # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15656.062943 # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15656.062943 # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 29071.698445 # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 29071.698445 # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20933.669329 # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20933.669329 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20933.669329 # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20933.669329 # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 73267.637326 # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73267.637326 # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 156312.791551 # average WriteReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156312.791551 # average WriteReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 102616.863550 # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 102616.863550 # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 14328 # number of replacements
system.l2c.tags.tagsinuse 791.177993 # Cycle average of tags in use
system.l2c.tags.total_refs 163940 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 15120 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 10.842593 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 732.189847 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0 7.660754 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1 7.418431 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2 7.928491 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3 7.181835 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu4 7.391664 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu5 6.508374 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu6 7.134486 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu7 7.764111 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.715029 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0 0.007481 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1 0.007245 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2 0.007743 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3 0.007014 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu4 0.007218 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu5 0.006356 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu6 0.006967 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu7 0.007582 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.772635 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 792 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 650 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 2105170 # Number of tag accesses
system.l2c.tags.data_accesses 2105170 # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks 77576 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 77576 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0 276 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1 259 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2 279 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3 261 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4 303 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5 269 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6 291 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7 289 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 2227 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0 1751 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1 1771 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2 1804 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3 1773 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4 1863 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5 1769 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6 1750 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7 1757 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 14238 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0 10760 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1 10778 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2 10893 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3 11049 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu4 10672 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu5 10913 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu6 11141 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu7 10949 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 87155 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0 12511 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1 12549 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2 12697 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3 12822 # number of demand (read+write) hits
system.l2c.demand_hits::cpu4 12535 # number of demand (read+write) hits
system.l2c.demand_hits::cpu5 12682 # number of demand (read+write) hits
system.l2c.demand_hits::cpu6 12891 # number of demand (read+write) hits
system.l2c.demand_hits::cpu7 12706 # number of demand (read+write) hits
system.l2c.demand_hits::total 101393 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0 12511 # number of overall hits
system.l2c.overall_hits::cpu1 12549 # number of overall hits
system.l2c.overall_hits::cpu2 12697 # number of overall hits
system.l2c.overall_hits::cpu3 12822 # number of overall hits
system.l2c.overall_hits::cpu4 12535 # number of overall hits
system.l2c.overall_hits::cpu5 12682 # number of overall hits
system.l2c.overall_hits::cpu6 12891 # number of overall hits
system.l2c.overall_hits::cpu7 12706 # number of overall hits
system.l2c.overall_hits::total 101393 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0 2046 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1 2029 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2 2111 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3 2056 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4 2033 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5 2090 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6 2030 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7 1987 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 16382 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0 4599 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1 4725 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2 4817 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3 4668 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4 4596 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5 4594 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6 4511 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7 4557 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 37067 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0 771 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1 761 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2 769 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3 709 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu4 779 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu5 699 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu6 722 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu7 759 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 5969 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0 5370 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1 5486 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2 5586 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3 5377 # number of demand (read+write) misses
system.l2c.demand_misses::cpu4 5375 # number of demand (read+write) misses
system.l2c.demand_misses::cpu5 5293 # number of demand (read+write) misses
system.l2c.demand_misses::cpu6 5233 # number of demand (read+write) misses
system.l2c.demand_misses::cpu7 5316 # number of demand (read+write) misses
system.l2c.demand_misses::total 43036 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0 5370 # number of overall misses
system.l2c.overall_misses::cpu1 5486 # number of overall misses
system.l2c.overall_misses::cpu2 5586 # number of overall misses
system.l2c.overall_misses::cpu3 5377 # number of overall misses
system.l2c.overall_misses::cpu4 5375 # number of overall misses
system.l2c.overall_misses::cpu5 5293 # number of overall misses
system.l2c.overall_misses::cpu6 5233 # number of overall misses
system.l2c.overall_misses::cpu7 5316 # number of overall misses
system.l2c.overall_misses::total 43036 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0 72840477 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1 70862981 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2 74683475 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3 72897976 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4 72564980 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5 68905302 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6 71238981 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7 72107979 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 576102151 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0 293596847 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1 301266861 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2 306960376 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3 297631356 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4 293263365 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5 292806382 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6 287321715 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7 290617373 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 2363464275 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0 53018410 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1 52427412 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2 53340392 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3 48936413 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu4 53163418 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu5 48227901 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu6 50021405 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu7 52163904 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 411299255 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0 346615257 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1 353694273 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2 360300768 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3 346567769 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4 346426783 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5 341034283 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6 337343120 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7 342781277 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 2774763530 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0 346615257 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1 353694273 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2 360300768 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3 346567769 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4 346426783 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5 341034283 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6 337343120 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7 342781277 # number of overall miss cycles
system.l2c.overall_miss_latency::total 2774763530 # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks 77576 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 77576 # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0 2322 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1 2288 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2 2390 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3 2317 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4 2336 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5 2359 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6 2321 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7 2276 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 18609 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0 6350 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1 6496 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2 6621 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3 6441 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4 6459 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5 6363 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6 6261 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7 6314 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 51305 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0 11531 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1 11539 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2 11662 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3 11758 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu4 11451 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu5 11612 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu6 11863 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu7 11708 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 93124 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0 17881 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1 18035 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2 18283 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3 18199 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4 17910 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5 17975 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6 18124 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7 18022 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 144429 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0 17881 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1 18035 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2 18283 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3 18199 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4 17910 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5 17975 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6 18124 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7 18022 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 144429 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0 0.881137 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1 0.886801 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2 0.883264 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3 0.887354 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4 0.870291 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5 0.885969 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6 0.874623 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7 0.873023 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.880327 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0 0.724252 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1 0.727371 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2 0.727534 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3 0.724732 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4 0.711565 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5 0.721986 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6 0.720492 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7 0.721729 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.722483 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0 0.066863 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1 0.065950 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2 0.065941 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3 0.060299 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu4 0.068029 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu5 0.060196 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu6 0.060862 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu7 0.064827 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.064097 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0 0.300319 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1 0.304186 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2 0.305530 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3 0.295456 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4 0.300112 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5 0.294465 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6 0.288733 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7 0.294973 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.297973 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0 0.300319 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1 0.304186 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2 0.305530 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3 0.295456 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4 0.300112 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5 0.294465 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6 0.288733 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7 0.294973 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.297973 # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0 35601.406158 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 34925.076885 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 35378.244908 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 35456.214008 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 35693.546483 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 32969.044019 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 35093.094089 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 36289.873679 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 35166.777622 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 63839.279626 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 63760.182222 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 63724.387793 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 63759.930591 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 63808.390992 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 63736.696125 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 63693.574595 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 63773.836515 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 63761.952006 # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0 68765.771725 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1 68892.788436 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2 69363.318596 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69021.739069 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu4 68245.722721 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu5 68995.566524 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu6 69281.724377 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu7 68727.146245 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 68905.889596 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 64546.602793 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 64472.160591 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 64500.674544 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 64453.741678 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 64451.494512 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 64431.188929 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 64464.574814 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 64481.052859 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 64475.405010 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 64546.602793 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 64472.160591 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 64500.674544 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 64453.741678 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 64451.494512 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 64431.188929 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 64464.574814 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 64481.052859 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 64475.405010 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 37689 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 7229 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs 5.213584 # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 6662 # number of writebacks
system.l2c.writebacks::total 6662 # number of writebacks
system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu1 5 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::total 8 # number of UpgradeReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu0 7 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu1 5 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu2 7 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu3 7 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu4 3 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu6 6 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu7 6 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total 45 # number of ReadExReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0 9 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1 9 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu2 12 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3 7 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu4 14 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu5 5 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu6 8 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu7 8 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total 72 # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0 16 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1 14 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2 19 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3 14 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4 17 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5 9 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6 14 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7 14 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 117 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0 16 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1 14 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2 19 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3 14 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4 17 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5 9 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6 14 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7 14 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 117 # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks 1261 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 1261 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0 2045 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1 2024 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2 2111 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3 2055 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4 2032 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5 2090 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6 2030 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7 1987 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 16374 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0 4592 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1 4720 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2 4810 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3 4661 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4 4593 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5 4590 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6 4505 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7 4551 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 37022 # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0 762 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1 752 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2 757 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3 702 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu4 765 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu5 694 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu6 714 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu7 751 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 5897 # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0 5354 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1 5472 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2 5567 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3 5363 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4 5358 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5 5284 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6 5219 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7 5302 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 42919 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0 5354 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1 5472 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2 5567 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3 5363 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4 5358 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5 5284 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6 5219 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7 5302 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 42919 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0 9885 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1 9741 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2 9774 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3 9813 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu4 9945 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu5 9798 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu6 9837 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu7 9918 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 78711 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0 5567 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1 5462 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2 5416 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3 5447 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu4 5329 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu5 5472 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu6 5532 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu7 5421 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 43646 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0 15452 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1 15203 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2 15190 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3 15260 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu4 15274 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu5 15270 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu6 15369 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu7 15339 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 122357 # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0 109082461 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1 108150960 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2 112626780 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3 109540787 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4 108317960 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5 111427287 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6 108309961 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7 105900964 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 873357160 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0 247432848 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1 253923362 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2 258718876 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3 250876356 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4 247138365 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5 246828882 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6 242219215 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7 244887373 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1992025277 # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 45035910 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 44634913 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 45307393 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 41572414 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 44985419 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 41094402 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 42561407 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 44302905 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 349494763 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0 292468758 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1 298558275 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2 304026269 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3 292448770 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4 292123784 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5 287923284 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6 284780622 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7 289190278 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 2341520040 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0 292468758 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1 298558275 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2 304026269 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3 292448770 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4 292123784 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5 287923284 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6 284780622 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7 289190278 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 2341520040 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 521573114 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 514181757 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 515732776 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 517979251 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 524791253 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 517494740 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 519233265 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 524055269 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 4155041425 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 302263386 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 299275381 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 295496378 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 297456387 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 290732905 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 298997210 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 303692889 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 296080198 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 2383994734 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0 823836500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1 813457138 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2 811229154 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3 815435638 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4 815524158 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5 816491950 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6 822926154 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7 820135467 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 6539036159 # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.880706 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.884615 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.883264 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.886923 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.869863 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.885969 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.874623 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.873023 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.879897 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.723150 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.726601 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.726476 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.723645 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.711101 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.721358 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.719534 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.720779 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.721606 # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.066083 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.065170 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.064912 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.059704 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.066806 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.059766 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.060187 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.064144 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063324 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0 0.299424 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1 0.303410 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2 0.304491 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3 0.294687 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4 0.299162 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5 0.293964 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6 0.287961 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7 0.294196 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.297163 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0 0.299424 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1 0.303410 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2 0.304491 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3 0.294687 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4 0.299162 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5 0.293964 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6 0.287961 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7 0.294196 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.297163 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 53341.056724 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 53434.268775 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 53352.335386 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 53304.519221 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 53306.082677 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 53314.491388 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 53354.660591 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 53296.911928 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 53338.045682 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 53883.459930 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 53797.322458 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 53787.708108 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 53824.577558 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 53807.612671 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 53775.355556 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 53766.751387 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 53809.574379 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 53806.527929 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59102.244094 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 59354.937500 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59851.245707 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59219.962963 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58804.469281 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 59213.835735 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59609.813725 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 58991.884154 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59266.536035 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 54626.215540 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 54561.088268 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 54612.227232 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 54530.816707 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 54521.049645 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 54489.644966 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 54566.127994 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 54543.620898 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 54556.724062 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 54626.215540 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 54561.088268 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 54612.227232 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 54530.816707 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 54521.049645 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 54489.644966 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 54566.127994 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 54543.620898 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 54556.724062 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 52764.098533 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 52785.315368 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 52765.784326 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 52785.004688 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 52769.356762 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 52816.364564 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 52783.700823 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 52838.805102 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 52788.573706 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 54295.560625 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 54792.270414 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 54559.892541 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 54609.213696 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 54556.747044 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 54641.302997 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 54897.485358 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 54617.265818 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 54621.150483 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 53315.849081 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 53506.356509 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 53405.474259 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 53436.149279 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 53392.965693 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 53470.330714 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 53544.547726 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 53467.336006 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 53442.272686 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.snoop_filter.tot_requests 127545 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 121489 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.trans_dist::ReadReq 78710 # Transaction distribution
system.membus.trans_dist::ReadResp 84594 # Transaction distribution
system.membus.trans_dist::WriteReq 43645 # Transaction distribution
system.membus.trans_dist::WriteResp 43644 # Transaction distribution
system.membus.trans_dist::WritebackDirty 6662 # Transaction distribution
system.membus.trans_dist::CleanEvict 1288 # Transaction distribution
system.membus.trans_dist::UpgradeReq 60944 # Transaction distribution
system.membus.trans_dist::UpgradeResp 50160 # Transaction distribution
system.membus.trans_dist::ReadExReq 49324 # Transaction distribution
system.membus.trans_dist::ReadExResp 3261 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 5890 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 428122 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 428122 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1134381 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1134381 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 56843 # Total snoops (count)
system.membus.snoop_fanout::samples 246442 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 246442 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 246442 # Request fanout histogram
system.membus.reqLayer0.occupancy 292771939 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 54.1 # Layer utilization (%)
system.membus.respLayer0.occupancy 296967000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 54.9 # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests 667370 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 284034 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 336982 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 12889 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 5997 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 6892 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq 78711 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 370868 # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate 5 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 43646 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 43643 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 84238 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 20479 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 29389 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 29387 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 162232 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 162225 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 292173 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122572 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122578 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122851 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122953 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122545 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122770 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122967 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122678 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 981914 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1769628 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1794530 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1801428 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1802844 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1789097 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1796324 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1791880 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1784489 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 14330220 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 335082 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 628739 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.148986 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.990092 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 176143 28.02% 28.02% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 257926 41.02% 69.04% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 134453 21.38% 90.42% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 47224 7.51% 97.93% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 11211 1.78% 99.72% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 1632 0.26% 99.98% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 146 0.02% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7 4 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 628739 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 500695190 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 92.6 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 101141048 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 18.7 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 101214213 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 18.7 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 101195728 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 18.7 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 101296930 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 18.7 # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy 101179412 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 18.7 # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy 101203668 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 18.7 # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy 101388789 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 18.7 # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy 101354632 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 18.7 # Layer utilization (%)
---------- End Simulation Statistics ----------
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