path: root/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.001487                       # Number of seconds simulated
sim_ticks                                  1486654500                       # Number of ticks simulated
final_tick                                 1486654500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_tick_rate                              296727534                       # Simulator tick rate (ticks/s)
host_mem_usage                                 404724                       # Number of bytes of host memory used
host_seconds                                     5.01                       # Real time elapsed on the host
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0                 76776                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1                 78761                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2                 77348                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3                 78011                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu4                 77583                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu5                 76150                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu6                 79121                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu7                 75007                       # Number of bytes read from this memory
system.physmem.bytes_read::total               618757                       # Number of bytes read from this memory
system.physmem.bytes_written::writebacks       383744                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0               5329                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1               5414                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu2               5336                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu3               5424                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu4               5535                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu5               5438                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu6               5327                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu7               5496                       # Number of bytes written to this memory
system.physmem.bytes_written::total            427043                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0                  11067                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1                  10847                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2                  10757                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3                  10790                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4                  11118                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5                  10756                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6                  10829                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7                  10873                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 87037                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks            5996                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0                  5329                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1                  5414                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2                  5336                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3                  5424                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4                  5535                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5                  5438                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6                  5327                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7                  5496                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                49295                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0                 51643472                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1                 52978685                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2                 52028228                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3                 52474196                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4                 52186302                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5                 51222392                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6                 53220839                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7                 50453552                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               416207666                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         258125879                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0                 3584558                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1                 3641734                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2                 3589267                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3                 3648460                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4                 3723125                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5                 3657877                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6                 3583213                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7                 3696891                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              287251006                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         258125879                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0                55228030                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1                56620419                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2                55617496                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3                56122657                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4                55909426                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5                54880270                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6                56804052                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7                54150443                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              703458672                       # Total bandwidth to/from this memory (bytes/s)
system.membus.snoop_filter.tot_requests        122188                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       120140                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.trans_dist::ReadReq               84101                       # Transaction distribution
system.membus.trans_dist::ReadResp              84098                       # Transaction distribution
system.membus.trans_dist::WriteReq              43299                       # Transaction distribution
system.membus.trans_dist::WriteResp             43298                       # Transaction distribution
system.membus.trans_dist::Writeback              5996                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            58155                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           47311                       # Transaction distribution
system.membus.trans_dist::ReadExReq             50200                       # Transaction distribution
system.membus.trans_dist::ReadExResp             2936                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       419394                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 419394                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1045797                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                 1045797                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                            58108                       # Total snoops (count)
system.membus.snoop_fanout::samples            122188                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  122188    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              122188                       # Request fanout histogram
system.membus.reqLayer0.occupancy           471309000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization              31.7                       # Layer utilization (%)
system.membus.respLayer0.occupancy          318465500                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization             21.4                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.l2c.tags.replacements                    12651                       # number of replacements
system.l2c.tags.tagsinuse                  779.272325                       # Cycle average of tags in use
system.l2c.tags.total_refs                     149024                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                    13435                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    11.092222                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks     728.440089                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0             6.082080                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1             6.684894                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2             6.012810                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3             6.146479                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu4             6.898409                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu5             6.253161                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu6             6.667903                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu7             6.086501                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.711367                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0            0.005940                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1            0.006528                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2            0.005872                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3            0.006002                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu4            0.006737                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu5            0.006107                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu6            0.006512                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu7            0.005944                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.761008                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024          784                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          355                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          425                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.765625                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  1945494                       # Number of tag accesses
system.l2c.tags.data_accesses                 1945494                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0                   10666                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1                   10663                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2                   10584                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3                   10758                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu4                   10608                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu5                   10611                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu6                   10587                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu7                   10524                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  85001                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks           74943                       # number of Writeback hits
system.l2c.Writeback_hits::total                74943                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0                  353                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1                  387                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2                  371                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3                  333                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4                  313                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5                  347                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6                  354                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7                  353                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                2811                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0                  1863                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1                  1918                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2                  1925                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3                  2036                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4                  1873                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5                  1894                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6                  1840                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7                  1970                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                15319                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0                    12529                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1                    12581                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2                    12509                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3                    12794                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu4                    12481                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu5                    12505                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu6                    12427                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu7                    12494                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  100320                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0                   12529                       # number of overall hits
system.l2c.overall_hits::cpu1                   12581                       # number of overall hits
system.l2c.overall_hits::cpu2                   12509                       # number of overall hits
system.l2c.overall_hits::cpu3                   12794                       # number of overall hits
system.l2c.overall_hits::cpu4                   12481                       # number of overall hits
system.l2c.overall_hits::cpu5                   12505                       # number of overall hits
system.l2c.overall_hits::cpu6                   12427                       # number of overall hits
system.l2c.overall_hits::cpu7                   12494                       # number of overall hits
system.l2c.overall_hits::total                 100320                       # number of overall hits
system.l2c.ReadReq_misses::cpu0                   689                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1                   724                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2                   665                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3                   684                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu4                   722                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu5                   677                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu6                   706                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu7                   668                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                 5535                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0               1935                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1               1877                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2               1961                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3               1907                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4               1994                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5               1930                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6               1982                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7               1923                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             15509                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0                4321                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1                4396                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2                4310                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3                4356                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4                4311                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5                4311                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6                4402                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7                4337                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              34744                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0                   5010                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1                   5120                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2                   4975                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3                   5040                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu4                   5033                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu5                   4988                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu6                   5108                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu7                   5005                       # number of demand (read+write) misses
system.l2c.demand_misses::total                 40279                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0                  5010                       # number of overall misses
system.l2c.overall_misses::cpu1                  5120                       # number of overall misses
system.l2c.overall_misses::cpu2                  4975                       # number of overall misses
system.l2c.overall_misses::cpu3                  5040                       # number of overall misses
system.l2c.overall_misses::cpu4                  5033                       # number of overall misses
system.l2c.overall_misses::cpu5                  4988                       # number of overall misses
system.l2c.overall_misses::cpu6                  5108                       # number of overall misses
system.l2c.overall_misses::cpu7                  5005                       # number of overall misses
system.l2c.overall_misses::total                40279                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0        40501462                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1        42600959                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2        38646963                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3        40375453                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu4        42613457                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu5        39385955                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu6        41558456                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu7        39362459                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total      325045164                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0     54709000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1     52877000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2     54939000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3     53407500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4     55477000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5     54482500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6     56188000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7     56111500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    438191500                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0     230273476                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1     234927475                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2     230453472                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3     232391973                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4     230081970                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5     230389480                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6     234880982                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7     230954980                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1854353808                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0        270774938                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1        277528434                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2        269100435                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3        272767426                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4        272695427                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5        269775435                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6        276439438                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7        270317439                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      2179398972                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0       270774938                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1       277528434                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2       269100435                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3       272767426                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4       272695427                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5       269775435                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6       276439438                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7       270317439                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     2179398972                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0               11355                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1               11387                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2               11249                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3               11442                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu4               11330                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu5               11288                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu6               11293                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu7               11192                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              90536                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks        74943                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total            74943                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0             2288                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1             2264                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2             2332                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3             2240                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4             2307                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5             2277                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6             2336                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7             2276                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           18320                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0              6184                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1              6314                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2              6235                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3              6392                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4              6184                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5              6205                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6              6242                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7              6307                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            50063                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0                17539                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1                17701                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2                17484                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3                17834                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4                17514                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5                17493                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6                17535                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7                17499                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              140599                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0               17539                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1               17701                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2               17484                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3               17834                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4               17514                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5               17493                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6               17535                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7               17499                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             140599                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0           0.060678                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1           0.063581                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2           0.059116                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3           0.059780                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu4           0.063725                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu5           0.059975                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu6           0.062517                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu7           0.059685                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.061136                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0        0.845717                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1        0.829064                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2        0.840909                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3        0.851339                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4        0.864326                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5        0.847606                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6        0.848459                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7        0.844903                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.846561                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0         0.698739                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1         0.696231                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2         0.691259                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3         0.681477                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4         0.697122                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5         0.694762                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6         0.705223                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7         0.687649                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.694006                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0            0.285649                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1            0.289249                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2            0.284546                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3            0.282606                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4            0.287370                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5            0.285143                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6            0.291303                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7            0.286016                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.286481                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0           0.285649                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1           0.289249                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2           0.284546                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3           0.282606                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4           0.287370                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5           0.285143                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6           0.291303                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7           0.286016                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.286481                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0 58782.963716                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1 58841.103591                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2 58115.733835                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3 59028.440058                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu4 59021.408587                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu5 58177.186115                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu6 58864.668555                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu7 58925.836826                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 58725.413550                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0 28273.385013                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 28171.017581                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 28015.808261                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 28006.030414                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 27821.965898                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 28229.274611                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 28349.142281                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 29179.147166                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 28254.013798                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 53291.709327                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 53441.190855                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 53469.483063                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 53349.856061                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 53370.904662                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 53442.236140                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 53357.787824                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 53252.243486                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 53371.914805                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 54046.893812                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 54204.772266                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 54090.539698                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 54120.521032                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 54181.487582                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 54084.890738                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 54118.918951                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 54009.478322                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 54107.573972                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 54046.893812                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 54204.772266                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 54090.539698                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 54120.521032                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 54181.487582                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 54084.890738                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 54118.918951                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 54009.478322                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 54107.573972                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs              6195                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                      845                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      7.331361                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks                5996                       # number of writebacks
system.l2c.writebacks::total                     5996                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0                  5                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1                  5                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2                  2                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3                  4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu4                  3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu5                  4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu6                  3                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu7                  4                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total                30                       # number of ReadReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu7               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::total              1                       # number of UpgradeReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu0                2                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu2                1                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5                1                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu6                1                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu7                1                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total               6                       # number of ReadExReq MSHR hits
system.l2c.demand_mshr_hits::cpu0                   7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1                   5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2                   3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3                   4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4                   3                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5                   5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6                   4                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7                   5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 36                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0                  7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1                  5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2                  3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3                  4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4                  3                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5                  5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6                  4                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7                  5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                36                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0              684                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1              719                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2              663                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3              680                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu4              719                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu5              673                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu6              703                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu7              664                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total            5505                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0          1935                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1          1877                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2          1961                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3          1907                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4          1994                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5          1930                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6          1982                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7          1922                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        15508                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0           4319                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1           4396                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2           4309                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3           4356                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4           4311                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5           4310                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6           4401                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7           4336                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         34738                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0              5003                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1              5115                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2              4972                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3              5036                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4              5030                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5              4983                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6              5104                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7              5000                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            40243                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0             5003                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1             5115                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2             4972                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3             5036                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4             5030                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5             4983                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6             5104                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7             5000                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           40243                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0     32025962                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1     33726459                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2     30538463                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3     31944953                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu4     33774957                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu5     31159456                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu6     32933456                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu7     31147460                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total    257251166                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0     78877000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1     76396500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2     79743000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3     77708000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4     81134500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5     78512000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6     80594000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7     78369500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    631334500                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0    177684976                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1    181467975                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2    178041472                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3    179439473                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4    177646470                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5    177921480                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6    181358982                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7    178204480                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1431765308                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0    209710938                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1    215194434                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2    208579935                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3    211384426                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4    211421427                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5    209080936                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6    214292438                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7    209351940                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   1689016474                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0    209710938                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1    215194434                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2    208579935                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3    211384426                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4    211421427                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5    209080936                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6    214292438                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7    209351940                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   1689016474                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    409314490                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    398776491                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    396170985                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    396900494                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    410851489                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    396740988                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    397751989                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    402422989                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   3208929915                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    221607995                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    223708999                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    220357996                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    224036997                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    228210498                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    226077994                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    220622999                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    228291489                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1792914967                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0    630922485                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1    622485490                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2    616528981                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3    620937491                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4    639061987                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5    622818982                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6    618374988                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7    630714478                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   5001844882                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0      0.060238                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1      0.063142                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2      0.058939                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3      0.059430                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu4      0.063460                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu5      0.059621                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu6      0.062251                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu7      0.059328                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.060805                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.845717                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.829064                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.840909                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.851339                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.864326                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.847606                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.848459                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.844464                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.846507                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.698415                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.696231                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.691099                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.681477                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.697122                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.694601                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.705062                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.687490                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.693886                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0       0.285250                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1       0.288967                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2       0.284374                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3       0.282382                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4       0.287199                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5       0.284857                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6       0.291075                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7       0.285731                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.286225                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0      0.285250                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1      0.288967                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2      0.284374                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3      0.282382                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4      0.287199                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5      0.284857                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6      0.291075                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7      0.285731                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.286225                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 46821.581871                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 46907.453408                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 46061.030166                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 46977.872059                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 46974.905424                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 46299.340267                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 46847.021337                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 46908.825301                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 46730.457039                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40763.307494                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40701.385189                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40664.456910                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40748.820136                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40689.317954                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40679.792746                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40662.966700                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40774.973985                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40710.246324                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41140.304700                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41280.249090                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41318.512880                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41193.634757                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41207.717467                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41281.085847                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41208.584867                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41098.819188                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 41216.112269                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 41917.037378                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 42071.248094                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 41950.912108                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 41974.667593                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 42032.092843                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 41958.847281                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 41985.195533                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 41870.388000                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 41970.441418                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 41917.037378                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 42071.248094                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 41950.912108                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 41974.667593                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 42032.092843                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 41958.847281                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 41985.195533                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 41870.388000                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 41970.441418                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.toL2Bus.snoop_filter.tot_requests       556652                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       259205                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       295399                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops              0                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq             369106                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            369100                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             43299                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            43298                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback            74943                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           29164                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          29164                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           161428                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          161427                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       120001                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       119693                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       119622                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       120026                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       120574                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       119580                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       119572                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       119681                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total                958749                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1736824                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1745103                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1743099                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1764010                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1727854                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1727156                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1741472                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1730998                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               13916516                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          322180                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples           556652                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.686233                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           1.173674                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                  52178      9.37%      9.37% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 250105     44.93%     54.30% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 140101     25.17%     79.47% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                  69083     12.41%     91.88% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                  29746      5.34%     97.23% # Request fanout histogram
system.toL2Bus.snoop_fanout::5                  11224      2.02%     99.24% # Request fanout histogram
system.toL2Bus.snoop_fanout::6                   3520      0.63%     99.88% # Request fanout histogram
system.toL2Bus.snoop_fanout::7                    695      0.12%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             556652                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         1484170768                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization             99.8                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         158821901                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization            10.7                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         158474081                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization            10.7                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         158663989                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization            10.7                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         158858134                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization            10.7                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy         159553082                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization            10.7                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy         158926155                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization            10.7                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy         158642094                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization            10.7                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy         158326604                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization            10.6                       # Layer utilization (%)
system.cpu0.num_reads                           99884                       # number of read accesses completed
system.cpu0.num_writes                          54722                       # number of write accesses completed
system.cpu0.num_copies                              0                       # number of copy accesses completed
system.cpu0.l1c.tags.replacements               22159                       # number of replacements
system.cpu0.l1c.tags.tagsinuse             396.508288                       # Cycle average of tags in use
system.cpu0.l1c.tags.total_refs                 13572                       # Total number of references to valid blocks.
system.cpu0.l1c.tags.sampled_refs               22560                       # Sample count of references to valid blocks.
system.cpu0.l1c.tags.avg_refs                0.601596                       # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu0.l1c.tags.occ_blocks::cpu0      396.508288                       # Average occupied blocks per requestor
system.cpu0.l1c.tags.occ_percent::cpu0       0.774430                       # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_percent::total      0.774430                       # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_task_id_blocks::1024          401                       # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::0          266                       # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::1          135                       # Occupied blocks per task id
system.cpu0.l1c.tags.occ_task_id_percent::1024     0.783203                       # Percentage of cache occupancy per task id
system.cpu0.l1c.tags.tag_accesses              336605                       # Number of tag accesses
system.cpu0.l1c.tags.data_accesses             336605                       # Number of data accesses
system.cpu0.l1c.ReadReq_hits::cpu0               8851                       # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total              8851                       # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0              1088                       # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total             1088                       # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0                9939                       # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total               9939                       # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0               9939                       # number of overall hits
system.cpu0.l1c.overall_hits::total              9939                       # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0            36351                       # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total           36351                       # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0           23761                       # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total          23761                       # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0             60112                       # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total            60112                       # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0            60112                       # number of overall misses
system.cpu0.l1c.overall_misses::total           60112                       # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0   2463515507                       # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total   2463515507                       # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0   1861288603                       # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total   1861288603                       # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0   4324804110                       # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total   4324804110                       # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0   4324804110                       # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total   4324804110                       # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0          45202                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total         45202                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0         24849                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total        24849                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0           70051                       # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total          70051                       # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0          70051                       # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total         70051                       # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.804190                       # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total     0.804190                       # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.956216                       # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total     0.956216                       # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0       0.858118                       # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total      0.858118                       # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0      0.858118                       # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total     0.858118                       # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 67770.226596                       # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 67770.226596                       # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 78333.765540                       # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 78333.765540                       # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 71945.769730                       # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 71945.769730                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 71945.769730                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 71945.769730                       # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs      2211784                       # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_mshrs               60234                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_mshrs    36.719859                       # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu0.l1c.writebacks::writebacks           9764                       # number of writebacks
system.cpu0.l1c.writebacks::total                9764                       # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36351                       # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total        36351                       # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23761                       # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total        23761                       # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0        60112                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total        60112                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0        60112                       # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total        60112                       # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0   2386706389                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total   2386706389                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0   1811452635                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total   1811452635                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0   4198159024                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total   4198159024                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0   4198159024                       # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total   4198159024                       # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0   1102233368                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total   1102233368                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0   3973496829                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total   3973496829                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   5075730197                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total   5075730197                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.804190                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.804190                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.956216                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.956216                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.858118                       # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total     0.858118                       # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.858118                       # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total     0.858118                       # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 65657.241589                       # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 65657.241589                       # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 76236.380413                       # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 76236.380413                       # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 69838.951025                       # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 69838.951025                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 69838.951025                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 69838.951025                       # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0          inf                       # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu1.num_reads                           99113                       # number of read accesses completed
system.cpu1.num_writes                          54702                       # number of write accesses completed
system.cpu1.num_copies                              0                       # number of copy accesses completed
system.cpu1.l1c.tags.replacements               22065                       # number of replacements
system.cpu1.l1c.tags.tagsinuse             395.289903                       # Cycle average of tags in use
system.cpu1.l1c.tags.total_refs                 13538                       # Total number of references to valid blocks.
system.cpu1.l1c.tags.sampled_refs               22464                       # Sample count of references to valid blocks.
system.cpu1.l1c.tags.avg_refs                0.602653                       # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu1.l1c.tags.occ_blocks::cpu1      395.289903                       # Average occupied blocks per requestor
system.cpu1.l1c.tags.occ_percent::cpu1       0.772051                       # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_percent::total      0.772051                       # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_task_id_blocks::1024          399                       # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::0          277                       # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::1          122                       # Occupied blocks per task id
system.cpu1.l1c.tags.occ_task_id_percent::1024     0.779297                       # Percentage of cache occupancy per task id
system.cpu1.l1c.tags.tag_accesses              336364                       # Number of tag accesses
system.cpu1.l1c.tags.data_accesses             336364                       # Number of data accesses
system.cpu1.l1c.ReadReq_hits::cpu1               8820                       # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total              8820                       # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1              1137                       # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total             1137                       # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1                9957                       # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total               9957                       # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1               9957                       # number of overall hits
system.cpu1.l1c.overall_hits::total              9957                       # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1            36159                       # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total           36159                       # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1           23877                       # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total          23877                       # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1             60036                       # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total            60036                       # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1            60036                       # number of overall misses
system.cpu1.l1c.overall_misses::total           60036                       # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1   2464134844                       # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total   2464134844                       # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1   1871949720                       # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total   1871949720                       # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1   4336084564                       # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total   4336084564                       # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1   4336084564                       # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total   4336084564                       # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1          44979                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total         44979                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1         25014                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total        25014                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1           69993                       # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total          69993                       # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1          69993                       # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total         69993                       # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.803908                       # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total     0.803908                       # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.954545                       # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total     0.954545                       # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1       0.857743                       # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total      0.857743                       # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1      0.857743                       # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total     0.857743                       # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 68147.206615                       # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 68147.206615                       # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 78399.703480                       # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 78399.703480                       # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 72224.741222                       # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 72224.741222                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 72224.741222                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 72224.741222                       # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs      2199257                       # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_mshrs               59892                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_mshrs    36.720380                       # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu1.l1c.writebacks::writebacks           9710                       # number of writebacks
system.cpu1.l1c.writebacks::total                9710                       # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36159                       # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total        36159                       # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23877                       # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total        23877                       # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1        60036                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total        60036                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1        60036                       # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total        60036                       # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1   2387770588                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total   2387770588                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1   1821987516                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total   1821987516                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1   4209758104                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total   4209758104                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1   4209758104                       # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total   4209758104                       # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1   1078285196                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total   1078285196                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1   4031598145                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total   4031598145                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   5109883341                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total   5109883341                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.803908                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.803908                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.954545                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.954545                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.857743                       # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total     0.857743                       # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.857743                       # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total     0.857743                       # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 66035.304848                       # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 66035.304848                       # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 76307.221008                       # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 76307.221008                       # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 70120.562729                       # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 70120.562729                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 70120.562729                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 70120.562729                       # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1          inf                       # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu2.num_reads                           98176                       # number of read accesses completed
system.cpu2.num_writes                          54646                       # number of write accesses completed
system.cpu2.num_copies                              0                       # number of copy accesses completed
system.cpu2.l1c.tags.replacements               22558                       # number of replacements
system.cpu2.l1c.tags.tagsinuse             395.943086                       # Cycle average of tags in use
system.cpu2.l1c.tags.total_refs                 13415                       # Total number of references to valid blocks.
system.cpu2.l1c.tags.sampled_refs               22958                       # Sample count of references to valid blocks.
system.cpu2.l1c.tags.avg_refs                0.584328                       # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu2.l1c.tags.occ_blocks::cpu2      395.943086                       # Average occupied blocks per requestor
system.cpu2.l1c.tags.occ_percent::cpu2       0.773326                       # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_percent::total      0.773326                       # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_task_id_blocks::1024          400                       # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::0          274                       # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::1          126                       # Occupied blocks per task id
system.cpu2.l1c.tags.occ_task_id_percent::1024     0.781250                       # Percentage of cache occupancy per task id
system.cpu2.l1c.tags.tag_accesses              336254                       # Number of tag accesses
system.cpu2.l1c.tags.data_accesses             336254                       # Number of data accesses
system.cpu2.l1c.ReadReq_hits::cpu2               8574                       # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total              8574                       # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2              1152                       # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total             1152                       # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2                9726                       # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total               9726                       # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2               9726                       # number of overall hits
system.cpu2.l1c.overall_hits::total              9726                       # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2            36359                       # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total           36359                       # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2           23860                       # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total          23860                       # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2             60219                       # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total            60219                       # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2            60219                       # number of overall misses
system.cpu2.l1c.overall_misses::total           60219                       # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2   2471651596                       # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total   2471651596                       # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2   1874289110                       # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total   1874289110                       # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2   4345940706                       # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total   4345940706                       # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2   4345940706                       # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total   4345940706                       # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2          44933                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total         44933                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2         25012                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total        25012                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2           69945                       # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total          69945                       # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2          69945                       # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total         69945                       # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.809183                       # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total     0.809183                       # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.953942                       # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total     0.953942                       # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2       0.860948                       # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total      0.860948                       # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2      0.860948                       # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total     0.860948                       # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 67979.086223                       # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 67979.086223                       # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 78553.608969                       # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 78553.608969                       # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 72168.928511                       # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 72168.928511                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 72168.928511                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 72168.928511                       # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs      2198300                       # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_mshrs               59965                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_mshrs    36.659718                       # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu2.l1c.writebacks::writebacks           9891                       # number of writebacks
system.cpu2.l1c.writebacks::total                9891                       # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36359                       # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total        36359                       # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2        23860                       # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total        23860                       # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2        60219                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total        60219                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2        60219                       # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total        60219                       # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2   2394908316                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total   2394908316                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2   1824229170                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total   1824229170                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2   4219137486                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total   4219137486                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2   4219137486                       # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total   4219137486                       # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2   1069659636                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total   1069659636                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2   3964277301                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total   3964277301                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   5033936937                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total   5033936937                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.809183                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.809183                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.953942                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.953942                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.860948                       # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total     0.860948                       # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.860948                       # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total     0.860948                       # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 65868.376908                       # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 65868.376908                       # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 76455.539396                       # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 76455.539396                       # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 70063.227320                       # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 70063.227320                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 70063.227320                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 70063.227320                       # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2          inf                       # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu3.num_reads                           98913                       # number of read accesses completed
system.cpu3.num_writes                          55212                       # number of write accesses completed
system.cpu3.num_copies                              0                       # number of copy accesses completed
system.cpu3.l1c.tags.replacements               22225                       # number of replacements
system.cpu3.l1c.tags.tagsinuse             393.873430                       # Cycle average of tags in use
system.cpu3.l1c.tags.total_refs                 13306                       # Total number of references to valid blocks.
system.cpu3.l1c.tags.sampled_refs               22621                       # Sample count of references to valid blocks.
system.cpu3.l1c.tags.avg_refs                0.588214                       # Average number of references to valid blocks.
system.cpu3.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu3.l1c.tags.occ_blocks::cpu3      393.873430                       # Average occupied blocks per requestor
system.cpu3.l1c.tags.occ_percent::cpu3       0.769284                       # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_percent::total      0.769284                       # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_task_id_blocks::1024          396                       # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::0          274                       # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::1          122                       # Occupied blocks per task id
system.cpu3.l1c.tags.occ_task_id_percent::1024     0.773438                       # Percentage of cache occupancy per task id
system.cpu3.l1c.tags.tag_accesses              336364                       # Number of tag accesses
system.cpu3.l1c.tags.data_accesses             336364                       # Number of data accesses
system.cpu3.l1c.ReadReq_hits::cpu3               8580                       # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total              8580                       # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3              1197                       # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total             1197                       # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3                9777                       # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total               9777                       # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3               9777                       # number of overall hits
system.cpu3.l1c.overall_hits::total              9777                       # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3            36212                       # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total           36212                       # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3           23956                       # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total          23956                       # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3             60168                       # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total            60168                       # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3            60168                       # number of overall misses
system.cpu3.l1c.overall_misses::total           60168                       # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3   2456007015                       # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total   2456007015                       # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3   1878963119                       # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total   1878963119                       # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3   4334970134                       # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total   4334970134                       # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3   4334970134                       # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total   4334970134                       # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3          44792                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total         44792                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3         25153                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total        25153                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3           69945                       # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total          69945                       # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3          69945                       # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total         69945                       # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.808448                       # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total     0.808448                       # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.952411                       # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total     0.952411                       # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3       0.860219                       # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total      0.860219                       # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3      0.860219                       # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total     0.860219                       # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 67823.014885                       # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 67823.014885                       # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 78433.925488                       # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 78433.925488                       # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 72047.768482                       # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 72047.768482                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 72047.768482                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 72047.768482                       # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs      2191987                       # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_mshrs               59750                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_mshrs    36.685975                       # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu3.l1c.writebacks::writebacks           9841                       # number of writebacks
system.cpu3.l1c.writebacks::total                9841                       # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36212                       # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total        36212                       # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23956                       # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total        23956                       # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3        60168                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total        60168                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3        60168                       # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total        60168                       # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3   2379648497                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total   2379648497                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3   1828763107                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total   1828763107                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3   4208411604                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total   4208411604                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3   4208411604                       # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total   4208411604                       # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3   1072329681                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total   1072329681                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3   3992913639                       # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total   3992913639                       # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   5065243320                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total   5065243320                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.808448                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.808448                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.952411                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.952411                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.860219                       # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total     0.860219                       # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.860219                       # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total     0.860219                       # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 65714.362559                       # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 65714.362559                       # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 76338.416555                       # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 76338.416555                       # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 69944.349222                       # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 69944.349222                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 69944.349222                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 69944.349222                       # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average WriteReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3          inf                       # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu4.num_reads                          100000                       # number of read accesses completed
system.cpu4.num_writes                          54692                       # number of write accesses completed
system.cpu4.num_copies                              0                       # number of copy accesses completed
system.cpu4.l1c.tags.replacements               22289                       # number of replacements
system.cpu4.l1c.tags.tagsinuse             395.541537                       # Cycle average of tags in use
system.cpu4.l1c.tags.total_refs                 13462                       # Total number of references to valid blocks.
system.cpu4.l1c.tags.sampled_refs               22679                       # Sample count of references to valid blocks.
system.cpu4.l1c.tags.avg_refs                0.593589                       # Average number of references to valid blocks.
system.cpu4.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu4.l1c.tags.occ_blocks::cpu4      395.541537                       # Average occupied blocks per requestor
system.cpu4.l1c.tags.occ_percent::cpu4       0.772542                       # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_percent::total      0.772542                       # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_task_id_blocks::1024          390                       # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::0          278                       # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::1          112                       # Occupied blocks per task id
system.cpu4.l1c.tags.occ_task_id_percent::1024     0.761719                       # Percentage of cache occupancy per task id
system.cpu4.l1c.tags.tag_accesses              337633                       # Number of tag accesses
system.cpu4.l1c.tags.data_accesses             337633                       # Number of data accesses
system.cpu4.l1c.ReadReq_hits::cpu4               8739                       # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total              8739                       # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4              1176                       # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total             1176                       # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4                9915                       # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total               9915                       # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4               9915                       # number of overall hits
system.cpu4.l1c.overall_hits::total              9915                       # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4            36692                       # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total           36692                       # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4           23629                       # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total          23629                       # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4             60321                       # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total            60321                       # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4            60321                       # number of overall misses
system.cpu4.l1c.overall_misses::total           60321                       # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4   2465146363                       # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total   2465146363                       # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4   1837411479                       # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total   1837411479                       # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4   4302557842                       # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total   4302557842                       # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4   4302557842                       # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total   4302557842                       # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4          45431                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total         45431                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4         24805                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total        24805                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4           70236                       # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total          70236                       # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4          70236                       # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total         70236                       # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.807642                       # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total     0.807642                       # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.952590                       # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total     0.952590                       # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4       0.858833                       # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total      0.858833                       # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4      0.858833                       # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total     0.858833                       # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 67184.845825                       # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 67184.845825                       # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 77760.864996                       # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 77760.864996                       # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 71327.694203                       # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 71327.694203                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 71327.694203                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 71327.694203                       # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs      2196199                       # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_mshrs               60342                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_mshrs    36.395860                       # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu4.l1c.writebacks::writebacks           9615                       # number of writebacks
system.cpu4.l1c.writebacks::total                9615                       # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36692                       # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total        36692                       # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23629                       # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total        23629                       # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4        60321                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total        60321                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4        60321                       # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total        60321                       # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4   2387693175                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total   2387693175                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4   1788001185                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total   1788001185                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4   4175694360                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total   4175694360                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4   4175694360                       # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total   4175694360                       # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4   1103066428                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total   1103066428                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4   4057809634                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total   4057809634                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   5160876062                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total   5160876062                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.807642                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.807642                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.952590                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.952590                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.858833                       # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total     0.858833                       # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.858833                       # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total     0.858833                       # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 65073.944593                       # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 65073.944593                       # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 75669.778027                       # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 75669.778027                       # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 69224.554633                       # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 69224.554633                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 69224.554633                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 69224.554633                       # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4          inf                       # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu5.num_reads                           98940                       # number of read accesses completed
system.cpu5.num_writes                          55179                       # number of write accesses completed
system.cpu5.num_copies                              0                       # number of copy accesses completed
system.cpu5.l1c.tags.replacements               22195                       # number of replacements
system.cpu5.l1c.tags.tagsinuse             395.048373                       # Cycle average of tags in use
system.cpu5.l1c.tags.total_refs                 13447                       # Total number of references to valid blocks.
system.cpu5.l1c.tags.sampled_refs               22597                       # Sample count of references to valid blocks.
system.cpu5.l1c.tags.avg_refs                0.595079                       # Average number of references to valid blocks.
system.cpu5.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu5.l1c.tags.occ_blocks::cpu5      395.048373                       # Average occupied blocks per requestor
system.cpu5.l1c.tags.occ_percent::cpu5       0.771579                       # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_percent::total      0.771579                       # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_task_id_blocks::1024          402                       # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::0          275                       # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::1          127                       # Occupied blocks per task id
system.cpu5.l1c.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
system.cpu5.l1c.tags.tag_accesses              337000                       # Number of tag accesses
system.cpu5.l1c.tags.data_accesses             337000                       # Number of data accesses
system.cpu5.l1c.ReadReq_hits::cpu5               8717                       # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total              8717                       # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5              1138                       # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total             1138                       # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5                9855                       # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total               9855                       # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5               9855                       # number of overall hits
system.cpu5.l1c.overall_hits::total              9855                       # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5            36402                       # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total           36402                       # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5           23842                       # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total          23842                       # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5             60244                       # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total            60244                       # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5            60244                       # number of overall misses
system.cpu5.l1c.overall_misses::total           60244                       # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5   2469941136                       # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total   2469941136                       # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5   1867542812                       # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total   1867542812                       # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5   4337483948                       # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total   4337483948                       # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5   4337483948                       # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total   4337483948                       # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5          45119                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total         45119                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5         24980                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total        24980                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5           70099                       # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total          70099                       # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5          70099                       # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total         70099                       # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.806800                       # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total     0.806800                       # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.954444                       # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total     0.954444                       # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5       0.859413                       # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total      0.859413                       # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5      0.859413                       # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total     0.859413                       # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 67851.797594                       # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 67851.797594                       # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 78329.956044                       # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 78329.956044                       # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 71998.604807                       # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 71998.604807                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 71998.604807                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 71998.604807                       # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs      2193553                       # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_mshrs               59918                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_mshrs    36.609249                       # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu5.l1c.writebacks::writebacks           9638                       # number of writebacks
system.cpu5.l1c.writebacks::total                9638                       # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36402                       # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total        36402                       # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23842                       # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total        23842                       # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5        60244                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total        60244                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5        60244                       # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total        60244                       # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5   2393170720                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total   2393170720                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5   1817634658                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total   1817634658                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5   4210805378                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total   4210805378                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5   4210805378                       # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total   4210805378                       # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5   1069731206                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total   1069731206                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5   4068656749                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total   4068656749                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   5138387955                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total   5138387955                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.806800                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.806800                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.954444                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.954444                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.859413                       # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total     0.859413                       # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.859413                       # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total     0.859413                       # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 65742.836108                       # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 65742.836108                       # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 76236.668820                       # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 76236.668820                       # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 69895.846524                       # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 69895.846524                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 69895.846524                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 69895.846524                       # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5          inf                       # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu6.num_reads                           98989                       # number of read accesses completed
system.cpu6.num_writes                          55088                       # number of write accesses completed
system.cpu6.num_copies                              0                       # number of copy accesses completed
system.cpu6.l1c.tags.replacements               22403                       # number of replacements
system.cpu6.l1c.tags.tagsinuse             396.761014                       # Cycle average of tags in use
system.cpu6.l1c.tags.total_refs                 13429                       # Total number of references to valid blocks.
system.cpu6.l1c.tags.sampled_refs               22803                       # Sample count of references to valid blocks.
system.cpu6.l1c.tags.avg_refs                0.588914                       # Average number of references to valid blocks.
system.cpu6.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu6.l1c.tags.occ_blocks::cpu6      396.761014                       # Average occupied blocks per requestor
system.cpu6.l1c.tags.occ_percent::cpu6       0.774924                       # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_percent::total      0.774924                       # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_task_id_blocks::1024          400                       # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::0          257                       # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::1          143                       # Occupied blocks per task id
system.cpu6.l1c.tags.occ_task_id_percent::1024     0.781250                       # Percentage of cache occupancy per task id
system.cpu6.l1c.tags.tag_accesses              336438                       # Number of tag accesses
system.cpu6.l1c.tags.data_accesses             336438                       # Number of data accesses
system.cpu6.l1c.ReadReq_hits::cpu6               8710                       # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total              8710                       # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6              1155                       # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total             1155                       # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6                9865                       # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total               9865                       # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6               9865                       # number of overall hits
system.cpu6.l1c.overall_hits::total              9865                       # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6            36281                       # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total           36281                       # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6           23840                       # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total          23840                       # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6             60121                       # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total            60121                       # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6            60121                       # number of overall misses
system.cpu6.l1c.overall_misses::total           60121                       # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6   2471222602                       # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total   2471222602                       # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6   1877806304                       # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total   1877806304                       # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6   4349028906                       # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total   4349028906                       # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6   4349028906                       # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total   4349028906                       # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6          44991                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total         44991                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6         24995                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total        24995                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6           69986                       # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total          69986                       # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6          69986                       # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total         69986                       # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.806406                       # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total     0.806406                       # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.953791                       # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total     0.953791                       # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6       0.859043                       # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total      0.859043                       # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6      0.859043                       # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total     0.859043                       # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 68113.409278                       # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 68113.409278                       # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 78767.042953                       # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 78767.042953                       # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 72337.933601                       # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 72337.933601                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 72337.933601                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 72337.933601                       # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs      2205749                       # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_mshrs               59981                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_mshrs    36.774128                       # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu6.l1c.writebacks::writebacks           9866                       # number of writebacks
system.cpu6.l1c.writebacks::total                9866                       # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36281                       # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total        36281                       # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23840                       # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total        23840                       # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6        60121                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total        60121                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6        60121                       # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total        60121                       # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6   2394594434                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total   2394594434                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6   1827956004                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total   1827956004                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6   4222550438                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total   4222550438                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6   4222550438                       # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total   4222550438                       # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6   1072935197                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total   1072935197                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6   3927350232                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total   3927350232                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   5000285429                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total   5000285429                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.806406                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.806406                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.953791                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.953791                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.859043                       # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total     0.859043                       # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.859043                       # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total     0.859043                       # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 66001.334969                       # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 66001.334969                       # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 76676.006879                       # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 76676.006879                       # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 70234.201660                       # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 70234.201660                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 70234.201660                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 70234.201660                       # average overall mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6          inf                       # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu7.num_reads                           98627                       # number of read accesses completed
system.cpu7.num_writes                          54842                       # number of write accesses completed
system.cpu7.num_copies                              0                       # number of copy accesses completed
system.cpu7.l1c.tags.replacements               22131                       # number of replacements
system.cpu7.l1c.tags.tagsinuse             396.248772                       # Cycle average of tags in use
system.cpu7.l1c.tags.total_refs                 13292                       # Total number of references to valid blocks.
system.cpu7.l1c.tags.sampled_refs               22531                       # Sample count of references to valid blocks.
system.cpu7.l1c.tags.avg_refs                0.589943                       # Average number of references to valid blocks.
system.cpu7.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu7.l1c.tags.occ_blocks::cpu7      396.248772                       # Average occupied blocks per requestor
system.cpu7.l1c.tags.occ_percent::cpu7       0.773923                       # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_percent::total      0.773923                       # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_task_id_blocks::1024          400                       # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::0          273                       # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::1          127                       # Occupied blocks per task id
system.cpu7.l1c.tags.occ_task_id_percent::1024     0.781250                       # Percentage of cache occupancy per task id
system.cpu7.l1c.tags.tag_accesses              334904                       # Number of tag accesses
system.cpu7.l1c.tags.data_accesses             334904                       # Number of data accesses
system.cpu7.l1c.ReadReq_hits::cpu7               8595                       # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total              8595                       # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7              1159                       # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total             1159                       # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7                9754                       # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total               9754                       # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7               9754                       # number of overall hits
system.cpu7.l1c.overall_hits::total              9754                       # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7            36066                       # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total           36066                       # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7           23832                       # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total          23832                       # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7             59898                       # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total            59898                       # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7            59898                       # number of overall misses
system.cpu7.l1c.overall_misses::total           59898                       # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7   2444451917                       # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total   2444451917                       # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7   1868936724                       # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total   1868936724                       # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7   4313388641                       # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total   4313388641                       # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7   4313388641                       # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total   4313388641                       # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7          44661                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total         44661                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7         24991                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total        24991                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7           69652                       # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total          69652                       # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7          69652                       # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total         69652                       # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.807550                       # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total     0.807550                       # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.953623                       # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total     0.953623                       # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7       0.859961                       # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total      0.859961                       # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7      0.859961                       # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total     0.859961                       # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 67777.183968                       # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 67777.183968                       # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 78421.312689                       # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 78421.312689                       # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 72012.231477                       # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 72012.231477                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 72012.231477                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 72012.231477                       # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs      2189961                       # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_mshrs               59729                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_mshrs    36.664953                       # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu7.l1c.writebacks::writebacks           9741                       # number of writebacks
system.cpu7.l1c.writebacks::total                9741                       # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36066                       # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total        36066                       # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23832                       # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total        23832                       # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7        59898                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total        59898                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7        59898                       # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total        59898                       # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7   2368349491                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total   2368349491                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7   1818980712                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total   1818980712                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7   4187330203                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total   4187330203                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7   4187330203                       # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total   4187330203                       # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7   1090983062                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total   1090983062                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7   4047348155                       # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total   4047348155                       # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   5138331217                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total   5138331217                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.807550                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.807550                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.953623                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.953623                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.859961                       # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total     0.859961                       # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.859961                       # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total     0.859961                       # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 65667.096185                       # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 65667.096185                       # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 76325.138973                       # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 76325.138973                       # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 69907.679772                       # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 69907.679772                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 69907.679772                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 69907.679772                       # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average WriteReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------