path: root/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000518                       # Number of seconds simulated
sim_ticks                                   518362500                       # Number of ticks simulated
final_tick                                  518362500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_tick_rate                               97254136                       # Simulator tick rate (ticks/s)
host_mem_usage                                 280792                       # Number of bytes of host memory used
host_seconds                                     5.33                       # Real time elapsed on the host
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0                 83556                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1                 80496                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2                 82210                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3                 83458                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu4                 79724                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu5                 80437                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu6                 82031                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu7                 84431                       # Number of bytes read from this memory
system.physmem.bytes_read::total               656343                       # Number of bytes read from this memory
system.physmem.bytes_written::writebacks       416960                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0               5350                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1               5428                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu2               5478                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu3               5268                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu4               5521                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu5               5505                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu6               5477                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu7               5442                       # Number of bytes written to this memory
system.physmem.bytes_written::total            460429                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0                  10980                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1                  10944                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2                  11020                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3                  10882                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4                  10676                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5                  11074                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6                  11030                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7                  10910                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 87516                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks            6515                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0                  5350                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1                  5428                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2                  5478                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3                  5268                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4                  5521                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5                  5505                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6                  5477                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7                  5442                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                49984                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0                161192216                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1                155289011                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2                158595577                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3                161003159                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4                153799706                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5                155175191                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6                158250259                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7                162880224                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              1266185343                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         804379175                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0                10320963                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1                10471436                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2                10567894                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3                10162772                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4                10650848                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5                10619981                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6                10565965                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7                10498445                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              888237479                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         804379175                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0               171513179                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1               165760448                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2               169163472                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3               171165931                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4               164450553                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5               165795172                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6               168816224                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7               173378668                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             2154422822                       # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.num_reads                           99891                       # number of read accesses completed
system.cpu0.num_writes                          54838                       # number of write accesses completed
system.cpu0.l1c.tags.replacements               22327                       # number of replacements
system.cpu0.l1c.tags.tagsinuse             391.597191                       # Cycle average of tags in use
system.cpu0.l1c.tags.total_refs                 13273                       # Total number of references to valid blocks.
system.cpu0.l1c.tags.sampled_refs               22716                       # Sample count of references to valid blocks.
system.cpu0.l1c.tags.avg_refs                0.584302                       # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu0.l1c.tags.occ_blocks::cpu0      391.597191                       # Average occupied blocks per requestor
system.cpu0.l1c.tags.occ_percent::cpu0       0.764838                       # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_percent::total      0.764838                       # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_task_id_blocks::1024          389                       # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::0          381                       # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
system.cpu0.l1c.tags.occ_task_id_percent::1024     0.759766                       # Percentage of cache occupancy per task id
system.cpu0.l1c.tags.tag_accesses              337776                       # Number of tag accesses
system.cpu0.l1c.tags.data_accesses             337776                       # Number of data accesses
system.cpu0.l1c.ReadReq_hits::cpu0               8714                       # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total              8714                       # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0              1148                       # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total             1148                       # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0                9862                       # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total               9862                       # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0               9862                       # number of overall hits
system.cpu0.l1c.overall_hits::total              9862                       # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0            36629                       # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total           36629                       # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0           23739                       # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total          23739                       # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0             60368                       # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total            60368                       # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0            60368                       # number of overall misses
system.cpu0.l1c.overall_misses::total           60368                       # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0    614304512                       # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total    614304512                       # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0    680799251                       # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total    680799251                       # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0   1295103763                       # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total   1295103763                       # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0   1295103763                       # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total   1295103763                       # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0          45343                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total         45343                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0         24887                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total        24887                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0           70230                       # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total          70230                       # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0          70230                       # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total         70230                       # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.807820                       # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total     0.807820                       # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.953871                       # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total     0.953871                       # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0       0.859576                       # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total      0.859576                       # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0      0.859576                       # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total     0.859576                       # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16770.987797                       # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 16770.987797                       # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 28678.514301                       # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 28678.514301                       # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 21453.481364                       # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 21453.481364                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 21453.481364                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 21453.481364                       # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs       764972                       # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_mshrs               61598                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_mshrs    12.418780                       # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu0.l1c.writebacks::writebacks           9814                       # number of writebacks
system.cpu0.l1c.writebacks::total                9814                       # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36629                       # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total        36629                       # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23739                       # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total        23739                       # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0        60368                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total        60368                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0        60368                       # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total        60368                       # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0         9828                       # number of ReadReq MSHR uncacheable
system.cpu0.l1c.ReadReq_mshr_uncacheable::total         9828                       # number of ReadReq MSHR uncacheable
system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0         5350                       # number of WriteReq MSHR uncacheable
system.cpu0.l1c.WriteReq_mshr_uncacheable::total         5350                       # number of WriteReq MSHR uncacheable
system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0        15178                       # number of overall MSHR uncacheable misses
system.cpu0.l1c.overall_mshr_uncacheable_misses::total        15178                       # number of overall MSHR uncacheable misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    577676512                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total    577676512                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    657061251                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total    657061251                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1234737763                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total   1234737763                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1234737763                       # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total   1234737763                       # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    645410094                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    645410094                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0    821386793                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total    821386793                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   1466796887                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total   1466796887                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.807820                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.807820                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.953871                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.953871                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.859576                       # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total     0.859576                       # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.859576                       # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total     0.859576                       # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15771.015097                       # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15771.015097                       # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 27678.556426                       # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 27678.556426                       # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20453.514494                       # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20453.514494                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20453.514494                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20453.514494                       # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 65670.542735                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65670.542735                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 153530.241682                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153530.241682                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 96639.668402                       # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 96639.668402                       # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu1.num_reads                           99259                       # number of read accesses completed
system.cpu1.num_writes                          55194                       # number of write accesses completed
system.cpu1.l1c.tags.replacements               22288                       # number of replacements
system.cpu1.l1c.tags.tagsinuse             392.187813                       # Cycle average of tags in use
system.cpu1.l1c.tags.total_refs                 13481                       # Total number of references to valid blocks.
system.cpu1.l1c.tags.sampled_refs               22683                       # Sample count of references to valid blocks.
system.cpu1.l1c.tags.avg_refs                0.594322                       # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu1.l1c.tags.occ_blocks::cpu1      392.187813                       # Average occupied blocks per requestor
system.cpu1.l1c.tags.occ_percent::cpu1       0.765992                       # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_percent::total      0.765992                       # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_task_id_blocks::1024          395                       # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::0          378                       # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
system.cpu1.l1c.tags.occ_task_id_percent::1024     0.771484                       # Percentage of cache occupancy per task id
system.cpu1.l1c.tags.tag_accesses              337082                       # Number of tag accesses
system.cpu1.l1c.tags.data_accesses             337082                       # Number of data accesses
system.cpu1.l1c.ReadReq_hits::cpu1               8742                       # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total              8742                       # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1              1127                       # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total             1127                       # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1                9869                       # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total               9869                       # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1               9869                       # number of overall hits
system.cpu1.l1c.overall_hits::total              9869                       # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1            36456                       # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total           36456                       # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1           23797                       # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total          23797                       # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1             60253                       # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total            60253                       # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1            60253                       # number of overall misses
system.cpu1.l1c.overall_misses::total           60253                       # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1    609449513                       # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total    609449513                       # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1    681132433                       # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total    681132433                       # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1   1290581946                       # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total   1290581946                       # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1   1290581946                       # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total   1290581946                       # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1          45198                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total         45198                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1         24924                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total        24924                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1           70122                       # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total          70122                       # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1          70122                       # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total         70122                       # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.806584                       # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total     0.806584                       # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.954783                       # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total     0.954783                       # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1       0.859260                       # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total      0.859260                       # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1      0.859260                       # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total     0.859260                       # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16717.399413                       # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 16717.399413                       # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 28622.617683                       # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 28622.617683                       # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 21419.380711                       # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 21419.380711                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 21419.380711                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 21419.380711                       # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs       761379                       # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_mshrs               61322                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_mshrs    12.416082                       # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu1.l1c.writebacks::writebacks           9824                       # number of writebacks
system.cpu1.l1c.writebacks::total                9824                       # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36456                       # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total        36456                       # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23797                       # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total        23797                       # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1        60253                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total        60253                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1        60253                       # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total        60253                       # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1         9840                       # number of ReadReq MSHR uncacheable
system.cpu1.l1c.ReadReq_mshr_uncacheable::total         9840                       # number of ReadReq MSHR uncacheable
system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1         5428                       # number of WriteReq MSHR uncacheable
system.cpu1.l1c.WriteReq_mshr_uncacheable::total         5428                       # number of WriteReq MSHR uncacheable
system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1        15268                       # number of overall MSHR uncacheable misses
system.cpu1.l1c.overall_mshr_uncacheable_misses::total        15268                       # number of overall MSHR uncacheable misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    572994513                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total    572994513                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    657337433                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total    657337433                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1230331946                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total   1230331946                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1230331946                       # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total   1230331946                       # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    646152701                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    646152701                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1    842788738                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total    842788738                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   1488941439                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total   1488941439                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.806584                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.806584                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.954783                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.954783                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.859260                       # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total     0.859260                       # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.859260                       # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total     0.859260                       # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15717.426843                       # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15717.426843                       # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 27622.701727                       # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 27622.701727                       # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20419.430501                       # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20419.430501                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20419.430501                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20419.430501                       # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 65665.924898                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65665.924898                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 155266.900884                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155266.900884                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 97520.398153                       # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 97520.398153                       # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu2.num_reads                           99508                       # number of read accesses completed
system.cpu2.num_writes                          54525                       # number of write accesses completed
system.cpu2.l1c.tags.replacements               22121                       # number of replacements
system.cpu2.l1c.tags.tagsinuse             392.684502                       # Cycle average of tags in use
system.cpu2.l1c.tags.total_refs                 13597                       # Total number of references to valid blocks.
system.cpu2.l1c.tags.sampled_refs               22507                       # Sample count of references to valid blocks.
system.cpu2.l1c.tags.avg_refs                0.604123                       # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu2.l1c.tags.occ_blocks::cpu2      392.684502                       # Average occupied blocks per requestor
system.cpu2.l1c.tags.occ_percent::cpu2       0.766962                       # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_percent::total      0.766962                       # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_task_id_blocks::1024          386                       # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::0          378                       # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
system.cpu2.l1c.tags.occ_task_id_percent::1024     0.753906                       # Percentage of cache occupancy per task id
system.cpu2.l1c.tags.tag_accesses              338301                       # Number of tag accesses
system.cpu2.l1c.tags.data_accesses             338301                       # Number of data accesses
system.cpu2.l1c.ReadReq_hits::cpu2               8815                       # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total              8815                       # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2              1121                       # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total             1121                       # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2                9936                       # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total               9936                       # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2               9936                       # number of overall hits
system.cpu2.l1c.overall_hits::total              9936                       # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2            36608                       # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total           36608                       # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2           23851                       # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total          23851                       # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2             60459                       # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total            60459                       # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2            60459                       # number of overall misses
system.cpu2.l1c.overall_misses::total           60459                       # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2    611593894                       # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total    611593894                       # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2    682333894                       # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total    682333894                       # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2   1293927788                       # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total   1293927788                       # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2   1293927788                       # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total   1293927788                       # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2          45423                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total         45423                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2         24972                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total        24972                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2           70395                       # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total          70395                       # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2          70395                       # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total         70395                       # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.805935                       # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total     0.805935                       # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.955110                       # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total     0.955110                       # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2       0.858854                       # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total      0.858854                       # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2      0.858854                       # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total     0.858854                       # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16706.563975                       # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 16706.563975                       # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 28608.188084                       # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 28608.188084                       # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 21401.739824                       # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 21401.739824                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 21401.739824                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 21401.739824                       # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs       766345                       # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_mshrs               61950                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_mshrs    12.370379                       # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu2.l1c.writebacks::writebacks           9721                       # number of writebacks
system.cpu2.l1c.writebacks::total                9721                       # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36608                       # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total        36608                       # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2        23851                       # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total        23851                       # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2        60459                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total        60459                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2        60459                       # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total        60459                       # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2         9890                       # number of ReadReq MSHR uncacheable
system.cpu2.l1c.ReadReq_mshr_uncacheable::total         9890                       # number of ReadReq MSHR uncacheable
system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2         5479                       # number of WriteReq MSHR uncacheable
system.cpu2.l1c.WriteReq_mshr_uncacheable::total         5479                       # number of WriteReq MSHR uncacheable
system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2        15369                       # number of overall MSHR uncacheable misses
system.cpu2.l1c.overall_mshr_uncacheable_misses::total        15369                       # number of overall MSHR uncacheable misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    574987894                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total    574987894                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    658483894                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total    658483894                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1233471788                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total   1233471788                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1233471788                       # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total   1233471788                       # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    648669577                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    648669577                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2    848315711                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total    848315711                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   1496985288                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total   1496985288                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.805935                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.805935                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.955110                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.955110                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.858854                       # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total     0.858854                       # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.858854                       # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total     0.858854                       # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15706.618608                       # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15706.618608                       # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 27608.230011                       # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 27608.230011                       # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20401.789444                       # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20401.789444                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20401.789444                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20401.789444                       # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 65588.430435                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65588.430435                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154830.390765                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154830.390765                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 97402.907671                       # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 97402.907671                       # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu3.num_reads                          100000                       # number of read accesses completed
system.cpu3.num_writes                          55096                       # number of write accesses completed
system.cpu3.l1c.tags.replacements               22478                       # number of replacements
system.cpu3.l1c.tags.tagsinuse             393.167313                       # Cycle average of tags in use
system.cpu3.l1c.tags.total_refs                 13728                       # Total number of references to valid blocks.
system.cpu3.l1c.tags.sampled_refs               22864                       # Sample count of references to valid blocks.
system.cpu3.l1c.tags.avg_refs                0.600420                       # Average number of references to valid blocks.
system.cpu3.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu3.l1c.tags.occ_blocks::cpu3      393.167313                       # Average occupied blocks per requestor
system.cpu3.l1c.tags.occ_percent::cpu3       0.767905                       # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_percent::total      0.767905                       # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_task_id_blocks::1024          386                       # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::0          380                       # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
system.cpu3.l1c.tags.occ_task_id_percent::1024     0.753906                       # Percentage of cache occupancy per task id
system.cpu3.l1c.tags.tag_accesses              339546                       # Number of tag accesses
system.cpu3.l1c.tags.data_accesses             339546                       # Number of data accesses
system.cpu3.l1c.ReadReq_hits::cpu3               8879                       # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total              8879                       # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3              1139                       # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total             1139                       # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3               10018                       # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total              10018                       # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3              10018                       # number of overall hits
system.cpu3.l1c.overall_hits::total             10018                       # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3            36721                       # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total           36721                       # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3           23927                       # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total          23927                       # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3             60648                       # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total            60648                       # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3            60648                       # number of overall misses
system.cpu3.l1c.overall_misses::total           60648                       # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3    620124867                       # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total    620124867                       # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3    683533364                       # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total    683533364                       # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3   1303658231                       # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total   1303658231                       # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3   1303658231                       # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total   1303658231                       # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3          45600                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total         45600                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3         25066                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total        25066                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3           70666                       # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total          70666                       # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3          70666                       # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total         70666                       # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.805285                       # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total     0.805285                       # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.954560                       # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total     0.954560                       # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3       0.858235                       # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total      0.858235                       # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3      0.858235                       # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total     0.858235                       # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16887.472209                       # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 16887.472209                       # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 28567.449492                       # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 28567.449492                       # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 21495.485935                       # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 21495.485935                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 21495.485935                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 21495.485935                       # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs       763846                       # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_mshrs               61681                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_mshrs    12.383813                       # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu3.l1c.writebacks::writebacks          10011                       # number of writebacks
system.cpu3.l1c.writebacks::total               10011                       # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36721                       # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total        36721                       # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23927                       # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total        23927                       # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3        60648                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total        60648                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3        60648                       # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total        60648                       # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3         9730                       # number of ReadReq MSHR uncacheable
system.cpu3.l1c.ReadReq_mshr_uncacheable::total         9730                       # number of ReadReq MSHR uncacheable
system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3         5269                       # number of WriteReq MSHR uncacheable
system.cpu3.l1c.WriteReq_mshr_uncacheable::total         5269                       # number of WriteReq MSHR uncacheable
system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3        14999                       # number of overall MSHR uncacheable misses
system.cpu3.l1c.overall_mshr_uncacheable_misses::total        14999                       # number of overall MSHR uncacheable misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    583406867                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total    583406867                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    659607364                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total    659607364                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1243014231                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total   1243014231                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1243014231                       # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total   1243014231                       # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    639132205                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    639132205                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3    818596366                       # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total    818596366                       # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   1457728571                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total   1457728571                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.805285                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.805285                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.954560                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.954560                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.858235                       # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total     0.858235                       # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.858235                       # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total     0.858235                       # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15887.553906                       # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15887.553906                       # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 27567.491286                       # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 27567.491286                       # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20495.551890                       # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20495.551890                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20495.551890                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20495.551890                       # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 65686.763104                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65686.763104                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 155360.858987                       # average WriteReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155360.858987                       # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 97188.383959                       # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 97188.383959                       # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu4.num_reads                           98810                       # number of read accesses completed
system.cpu4.num_writes                          55636                       # number of write accesses completed
system.cpu4.l1c.tags.replacements               22565                       # number of replacements
system.cpu4.l1c.tags.tagsinuse             393.118080                       # Cycle average of tags in use
system.cpu4.l1c.tags.total_refs                 13493                       # Total number of references to valid blocks.
system.cpu4.l1c.tags.sampled_refs               22961                       # Sample count of references to valid blocks.
system.cpu4.l1c.tags.avg_refs                0.587649                       # Average number of references to valid blocks.
system.cpu4.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu4.l1c.tags.occ_blocks::cpu4      393.118080                       # Average occupied blocks per requestor
system.cpu4.l1c.tags.occ_percent::cpu4       0.767809                       # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_percent::total      0.767809                       # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_task_id_blocks::1024          396                       # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::0          388                       # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
system.cpu4.l1c.tags.occ_task_id_percent::1024     0.773438                       # Percentage of cache occupancy per task id
system.cpu4.l1c.tags.tag_accesses              338158                       # Number of tag accesses
system.cpu4.l1c.tags.data_accesses             338158                       # Number of data accesses
system.cpu4.l1c.ReadReq_hits::cpu4               8694                       # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total              8694                       # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4              1170                       # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total             1170                       # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4                9864                       # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total               9864                       # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4               9864                       # number of overall hits
system.cpu4.l1c.overall_hits::total              9864                       # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4            36355                       # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total           36355                       # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4           24124                       # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total          24124                       # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4             60479                       # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total            60479                       # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4            60479                       # number of overall misses
system.cpu4.l1c.overall_misses::total           60479                       # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4    612629802                       # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total    612629802                       # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4    686589261                       # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total    686589261                       # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4   1299219063                       # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total   1299219063                       # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4   1299219063                       # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total   1299219063                       # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4          45049                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total         45049                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4         25294                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total        25294                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4           70343                       # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total          70343                       # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4          70343                       # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total         70343                       # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.807010                       # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total     0.807010                       # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.953744                       # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total     0.953744                       # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4       0.859773                       # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total      0.859773                       # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4      0.859773                       # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total     0.859773                       # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16851.321744                       # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 16851.321744                       # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 28460.838211                       # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 28460.838211                       # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 21482.151871                       # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 21482.151871                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 21482.151871                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 21482.151871                       # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs       755009                       # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_mshrs               61034                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_mshrs    12.370302                       # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu4.l1c.writebacks::writebacks          10039                       # number of writebacks
system.cpu4.l1c.writebacks::total               10039                       # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36355                       # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total        36355                       # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4        24124                       # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total        24124                       # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4        60479                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total        60479                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4        60479                       # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total        60479                       # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4         9580                       # number of ReadReq MSHR uncacheable
system.cpu4.l1c.ReadReq_mshr_uncacheable::total         9580                       # number of ReadReq MSHR uncacheable
system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4         5521                       # number of WriteReq MSHR uncacheable
system.cpu4.l1c.WriteReq_mshr_uncacheable::total         5521                       # number of WriteReq MSHR uncacheable
system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4        15101                       # number of overall MSHR uncacheable misses
system.cpu4.l1c.overall_mshr_uncacheable_misses::total        15101                       # number of overall MSHR uncacheable misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    576274802                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total    576274802                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    662467261                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total    662467261                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1238742063                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total   1238742063                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1238742063                       # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total   1238742063                       # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    630980804                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    630980804                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4    867176198                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total    867176198                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   1498157002                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total   1498157002                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.807010                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.807010                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.953744                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.953744                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.859773                       # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total     0.859773                       # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.859773                       # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total     0.859773                       # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15851.321744                       # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15851.321744                       # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 27460.921116                       # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 27460.921116                       # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20482.184940                       # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20482.184940                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20482.184940                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20482.184940                       # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65864.384551                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65864.384551                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157068.682847                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157068.682847                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 99209.125356                       # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 99209.125356                       # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu5.num_reads                           98552                       # number of read accesses completed
system.cpu5.num_writes                          54926                       # number of write accesses completed
system.cpu5.l1c.tags.replacements               22151                       # number of replacements
system.cpu5.l1c.tags.tagsinuse             392.121942                       # Cycle average of tags in use
system.cpu5.l1c.tags.total_refs                 13428                       # Total number of references to valid blocks.
system.cpu5.l1c.tags.sampled_refs               22535                       # Sample count of references to valid blocks.
system.cpu5.l1c.tags.avg_refs                0.595873                       # Average number of references to valid blocks.
system.cpu5.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu5.l1c.tags.occ_blocks::cpu5      392.121942                       # Average occupied blocks per requestor
system.cpu5.l1c.tags.occ_percent::cpu5       0.765863                       # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_percent::total      0.765863                       # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_task_id_blocks::1024          384                       # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::0          371                       # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::1           13                       # Occupied blocks per task id
system.cpu5.l1c.tags.occ_task_id_percent::1024     0.750000                       # Percentage of cache occupancy per task id
system.cpu5.l1c.tags.tag_accesses              336693                       # Number of tag accesses
system.cpu5.l1c.tags.data_accesses             336693                       # Number of data accesses
system.cpu5.l1c.ReadReq_hits::cpu5               8529                       # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total              8529                       # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5              1201                       # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total             1201                       # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5                9730                       # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total               9730                       # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5               9730                       # number of overall hits
system.cpu5.l1c.overall_hits::total              9730                       # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5            36363                       # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total           36363                       # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5           23944                       # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total          23944                       # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5             60307                       # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total            60307                       # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5            60307                       # number of overall misses
system.cpu5.l1c.overall_misses::total           60307                       # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5    609487073                       # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total    609487073                       # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5    677626855                       # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total    677626855                       # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5   1287113928                       # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total   1287113928                       # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5   1287113928                       # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total   1287113928                       # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5          44892                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total         44892                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5         25145                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total        25145                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5           70037                       # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total          70037                       # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5          70037                       # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total         70037                       # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.810011                       # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total     0.810011                       # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.952237                       # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total     0.952237                       # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5       0.861073                       # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total      0.861073                       # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5      0.861073                       # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total     0.861073                       # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16761.187828                       # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 16761.187828                       # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 28300.486761                       # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 28300.486761                       # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 21342.695342                       # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 21342.695342                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 21342.695342                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 21342.695342                       # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs       765746                       # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_mshrs               61759                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_mshrs    12.398938                       # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu5.l1c.writebacks::writebacks           9825                       # number of writebacks
system.cpu5.l1c.writebacks::total                9825                       # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36363                       # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total        36363                       # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23944                       # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total        23944                       # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5        60307                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total        60307                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5        60307                       # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total        60307                       # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5         9974                       # number of ReadReq MSHR uncacheable
system.cpu5.l1c.ReadReq_mshr_uncacheable::total         9974                       # number of ReadReq MSHR uncacheable
system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5         5505                       # number of WriteReq MSHR uncacheable
system.cpu5.l1c.WriteReq_mshr_uncacheable::total         5505                       # number of WriteReq MSHR uncacheable
system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5        15479                       # number of overall MSHR uncacheable misses
system.cpu5.l1c.overall_mshr_uncacheable_misses::total        15479                       # number of overall MSHR uncacheable misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    573124073                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total    573124073                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    653684855                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total    653684855                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1226808928                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total   1226808928                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1226808928                       # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total   1226808928                       # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    653819057                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    653819057                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5    856353181                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total    856353181                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   1510172238                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total   1510172238                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.810011                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.810011                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.952237                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.952237                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.861073                       # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total     0.861073                       # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.861073                       # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total     0.861073                       # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15761.187828                       # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15761.187828                       # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 27300.570289                       # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 27300.570289                       # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20342.728506                       # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20342.728506                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20342.728506                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20342.728506                       # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 65552.341789                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65552.341789                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 155559.160945                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155559.160945                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 97562.648621                       # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 97562.648621                       # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu6.num_reads                           98949                       # number of read accesses completed
system.cpu6.num_writes                          55414                       # number of write accesses completed
system.cpu6.l1c.tags.replacements               22111                       # number of replacements
system.cpu6.l1c.tags.tagsinuse             389.931977                       # Cycle average of tags in use
system.cpu6.l1c.tags.total_refs                 13393                       # Total number of references to valid blocks.
system.cpu6.l1c.tags.sampled_refs               22506                       # Sample count of references to valid blocks.
system.cpu6.l1c.tags.avg_refs                0.595086                       # Average number of references to valid blocks.
system.cpu6.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu6.l1c.tags.occ_blocks::cpu6      389.931977                       # Average occupied blocks per requestor
system.cpu6.l1c.tags.occ_percent::cpu6       0.761586                       # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_percent::total      0.761586                       # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_task_id_blocks::1024          395                       # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::0          383                       # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::1           12                       # Occupied blocks per task id
system.cpu6.l1c.tags.occ_task_id_percent::1024     0.771484                       # Percentage of cache occupancy per task id
system.cpu6.l1c.tags.tag_accesses              337246                       # Number of tag accesses
system.cpu6.l1c.tags.data_accesses             337246                       # Number of data accesses
system.cpu6.l1c.ReadReq_hits::cpu6               8611                       # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total              8611                       # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6              1144                       # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total             1144                       # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6                9755                       # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total               9755                       # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6               9755                       # number of overall hits
system.cpu6.l1c.overall_hits::total              9755                       # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6            36346                       # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total           36346                       # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6           24035                       # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total          24035                       # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6             60381                       # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total            60381                       # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6            60381                       # number of overall misses
system.cpu6.l1c.overall_misses::total           60381                       # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6    607533641                       # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total    607533641                       # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6    684112648                       # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total    684112648                       # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6   1291646289                       # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total   1291646289                       # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6   1291646289                       # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total   1291646289                       # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6          44957                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total         44957                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6         25179                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total        25179                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6           70136                       # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total          70136                       # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6          70136                       # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total         70136                       # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.808461                       # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total     0.808461                       # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.954565                       # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total     0.954565                       # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6       0.860913                       # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total      0.860913                       # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6      0.860913                       # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total     0.860913                       # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16715.282039                       # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 16715.282039                       # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28463.184855                       # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 28463.184855                       # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 21391.601481                       # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 21391.601481                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 21391.601481                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 21391.601481                       # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs       766078                       # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_mshrs               61691                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_mshrs    12.417986                       # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu6.l1c.writebacks::writebacks           9648                       # number of writebacks
system.cpu6.l1c.writebacks::total                9648                       # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36346                       # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total        36346                       # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6        24035                       # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total        24035                       # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6        60381                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total        60381                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6        60381                       # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total        60381                       # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6         9904                       # number of ReadReq MSHR uncacheable
system.cpu6.l1c.ReadReq_mshr_uncacheable::total         9904                       # number of ReadReq MSHR uncacheable
system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6         5478                       # number of WriteReq MSHR uncacheable
system.cpu6.l1c.WriteReq_mshr_uncacheable::total         5478                       # number of WriteReq MSHR uncacheable
system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6        15382                       # number of overall MSHR uncacheable misses
system.cpu6.l1c.overall_mshr_uncacheable_misses::total        15382                       # number of overall MSHR uncacheable misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    571188641                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total    571188641                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    660079648                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total    660079648                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1231268289                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total   1231268289                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1231268289                       # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total   1231268289                       # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    650717068                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    650717068                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6    843701696                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total    843701696                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   1494418764                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total   1494418764                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.808461                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.808461                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.954565                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.954565                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.860913                       # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total     0.860913                       # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.860913                       # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total     0.860913                       # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15715.309553                       # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15715.309553                       # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 27463.268067                       # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 27463.268067                       # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20391.651165                       # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20391.651165                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20391.651165                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20391.651165                       # average overall mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 65702.450323                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65702.450323                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 154016.373859                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154016.373859                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 97153.735795                       # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 97153.735795                       # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu7.num_reads                           99388                       # number of read accesses completed
system.cpu7.num_writes                          55153                       # number of write accesses completed
system.cpu7.l1c.tags.replacements               22255                       # number of replacements
system.cpu7.l1c.tags.tagsinuse             390.416736                       # Cycle average of tags in use
system.cpu7.l1c.tags.total_refs                 13442                       # Total number of references to valid blocks.
system.cpu7.l1c.tags.sampled_refs               22659                       # Sample count of references to valid blocks.
system.cpu7.l1c.tags.avg_refs                0.593230                       # Average number of references to valid blocks.
system.cpu7.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu7.l1c.tags.occ_blocks::cpu7      390.416736                       # Average occupied blocks per requestor
system.cpu7.l1c.tags.occ_percent::cpu7       0.762533                       # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_percent::total      0.762533                       # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_task_id_blocks::1024          404                       # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::0          395                       # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::1            9                       # Occupied blocks per task id
system.cpu7.l1c.tags.occ_task_id_percent::1024     0.789062                       # Percentage of cache occupancy per task id
system.cpu7.l1c.tags.tag_accesses              338136                       # Number of tag accesses
system.cpu7.l1c.tags.data_accesses             338136                       # Number of data accesses
system.cpu7.l1c.ReadReq_hits::cpu7               8702                       # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total              8702                       # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7              1125                       # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total             1125                       # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7                9827                       # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total               9827                       # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7               9827                       # number of overall hits
system.cpu7.l1c.overall_hits::total              9827                       # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7            36623                       # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total           36623                       # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7           23879                       # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total          23879                       # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7             60502                       # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total            60502                       # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7            60502                       # number of overall misses
system.cpu7.l1c.overall_misses::total           60502                       # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7    619428018                       # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total    619428018                       # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7    681256931                       # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total    681256931                       # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7   1300684949                       # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total   1300684949                       # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7   1300684949                       # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total   1300684949                       # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7          45325                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total         45325                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7         25004                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total        25004                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7           70329                       # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total          70329                       # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7          70329                       # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total         70329                       # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.808009                       # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total     0.808009                       # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.955007                       # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total     0.955007                       # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7       0.860271                       # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total      0.860271                       # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7      0.860271                       # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total     0.860271                       # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16913.634000                       # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 16913.634000                       # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 28529.541899                       # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 28529.541899                       # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 21498.214092                       # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 21498.214092                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 21498.214092                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 21498.214092                       # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs       764751                       # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_mshrs               61551                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_mshrs    12.424672                       # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu7.l1c.writebacks::writebacks           9698                       # number of writebacks
system.cpu7.l1c.writebacks::total                9698                       # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36623                       # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total        36623                       # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23879                       # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total        23879                       # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7        60502                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total        60502                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7        60502                       # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total        60502                       # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7         9744                       # number of ReadReq MSHR uncacheable
system.cpu7.l1c.ReadReq_mshr_uncacheable::total         9744                       # number of ReadReq MSHR uncacheable
system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7         5445                       # number of WriteReq MSHR uncacheable
system.cpu7.l1c.WriteReq_mshr_uncacheable::total         5445                       # number of WriteReq MSHR uncacheable
system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7        15189                       # number of overall MSHR uncacheable misses
system.cpu7.l1c.overall_mshr_uncacheable_misses::total        15189                       # number of overall MSHR uncacheable misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    582807018                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total    582807018                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    657378931                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total    657378931                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1240185949                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total   1240185949                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1240185949                       # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total   1240185949                       # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    639625650                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    639625650                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7    835380703                       # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total    835380703                       # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   1475006353                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total   1475006353                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.808009                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.808009                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.955007                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.955007                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.860271                       # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total     0.860271                       # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.860271                       # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total     0.860271                       # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15913.688611                       # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15913.688611                       # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 27529.583777                       # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 27529.583777                       # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20498.263677                       # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20498.263677                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20498.263677                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20498.263677                       # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 65643.026478                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65643.026478                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 153421.616713                       # average WriteReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153421.616713                       # average WriteReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 97110.168741                       # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 97110.168741                       # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                    14059                       # number of replacements
system.l2c.tags.tagsinuse                  786.833616                       # Cycle average of tags in use
system.l2c.tags.total_refs                     163279                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                    14835                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    11.006336                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks     728.191655                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0             7.576246                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1             6.765492                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2             7.413353                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3             7.547486                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu4             7.173407                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu5             7.531253                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu6             7.038544                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu7             7.596181                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.711125                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0            0.007399                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1            0.006607                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2            0.007240                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3            0.007371                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu4            0.007005                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu5            0.007355                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu6            0.006874                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu7            0.007418                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.768392                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024          776                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          637                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          139                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.757812                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  2098126                       # Number of tag accesses
system.l2c.tags.data_accesses                 2098126                       # Number of data accesses
system.l2c.Writeback_hits::writebacks           77297                       # number of Writeback hits
system.l2c.Writeback_hits::total                77297                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0                  246                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1                  268                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2                  270                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3                  283                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4                  289                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5                  282                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6                  269                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7                  297                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                2204                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0                  1720                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1                  1708                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2                  1780                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3                  1750                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4                  1833                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5                  1787                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6                  1793                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7                  1756                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                14127                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0             10721                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1             10733                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2             10896                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3             11023                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu4             10756                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu5             10769                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu6             10556                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu7             10900                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total            86354                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0                    12441                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1                    12441                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2                    12676                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3                    12773                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu4                    12589                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu5                    12556                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu6                    12349                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu7                    12656                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  100481                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0                   12441                       # number of overall hits
system.l2c.overall_hits::cpu1                   12441                       # number of overall hits
system.l2c.overall_hits::cpu2                   12676                       # number of overall hits
system.l2c.overall_hits::cpu3                   12773                       # number of overall hits
system.l2c.overall_hits::cpu4                   12589                       # number of overall hits
system.l2c.overall_hits::cpu5                   12556                       # number of overall hits
system.l2c.overall_hits::cpu6                   12349                       # number of overall hits
system.l2c.overall_hits::cpu7                   12656                       # number of overall hits
system.l2c.overall_hits::total                 100481                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0               1978                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1               2026                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2               2150                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3               2091                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4               2034                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5               2071                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6               2011                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7               2018                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             16379                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0                4713                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1                4655                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2                4607                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3                4594                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4                4660                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5                4574                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6                4699                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7                4645                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              37147                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0             745                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1             703                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2             745                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3             740                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu4             719                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu5             741                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu6             735                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu7             779                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total           5907                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0                   5458                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1                   5358                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2                   5352                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3                   5334                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu4                   5379                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu5                   5315                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu6                   5434                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu7                   5424                       # number of demand (read+write) misses
system.l2c.demand_misses::total                 43054                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0                  5458                       # number of overall misses
system.l2c.overall_misses::cpu1                  5358                       # number of overall misses
system.l2c.overall_misses::cpu2                  5352                       # number of overall misses
system.l2c.overall_misses::cpu3                  5334                       # number of overall misses
system.l2c.overall_misses::cpu4                  5379                       # number of overall misses
system.l2c.overall_misses::cpu5                  5315                       # number of overall misses
system.l2c.overall_misses::cpu6                  5434                       # number of overall misses
system.l2c.overall_misses::cpu7                  5424                       # number of overall misses
system.l2c.overall_misses::total                43054                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0     60264491                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1     62631489                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2     64255988                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3     63421482                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4     62636494                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5     62720987                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6     60083486                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7     62493486                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    498507903                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0     264922404                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1     260661407                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2     257895914                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3     258059392                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4     261142926                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5     256126416                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6     263147923                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7     259849424                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2081805806                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0     46156062                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1     44483916                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2     46780409                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3     45792918                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu4     45003906                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu5     46499399                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu6     45597417                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu7     48662406                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total    368976433                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0        311078466                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1        305145323                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2        304676323                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3        303852310                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4        306146832                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5        302625815                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6        308745340                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7        308511830                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      2450782239                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0       311078466                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1       305145323                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2       304676323                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3       303852310                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4       306146832                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5       302625815                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6       308745340                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7       308511830                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     2450782239                       # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks        77297                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total            77297                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0             2224                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1             2294                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2             2420                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3             2374                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4             2323                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5             2353                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6             2280                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7             2315                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           18583                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0              6433                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1              6363                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2              6387                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3              6344                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4              6493                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5              6361                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6              6492                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7              6401                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            51274                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0         11466                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1         11436                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2         11641                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3         11763                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu4         11475                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu5         11510                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu6         11291                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu7         11679                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total        92261                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0                17899                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1                17799                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2                18028                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3                18107                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4                17968                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5                17871                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6                17783                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7                18080                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              143535                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0               17899                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1               17799                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2               18028                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3               18107                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4               17968                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5               17871                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6               17783                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7               18080                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             143535                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0        0.889388                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1        0.883173                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2        0.888430                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3        0.880792                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4        0.875592                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5        0.880153                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6        0.882018                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7        0.871706                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.881397                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0         0.732629                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1         0.731573                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2         0.721309                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3         0.724149                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4         0.717696                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5         0.719069                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6         0.723814                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7         0.725668                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.724480                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0     0.064975                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1     0.061473                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2     0.063998                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3     0.062909                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu4     0.062658                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu5     0.064379                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu6     0.065096                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu7     0.066701                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.064025                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0            0.304933                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1            0.301028                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2            0.296872                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3            0.294582                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4            0.299366                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5            0.297409                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6            0.305573                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7            0.300000                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.299955                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0           0.304933                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1           0.301028                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2           0.296872                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3           0.294582                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4           0.299366                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5           0.297409                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6           0.305573                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7           0.300000                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.299955                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0 30467.386754                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 30913.864265                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 29886.506047                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 30330.694405                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 30794.736480                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 30285.363110                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 29877.417205                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 30968.030723                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 30435.796019                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 56210.991725                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 55996.005800                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 55979.143477                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 56173.137135                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 56039.254506                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 55996.155662                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 56000.834858                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 55941.748977                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 56042.366974                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0 61954.445638                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1 63277.263158                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2 62792.495302                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3 61882.321622                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu4 62592.358832                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu5 62752.225371                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu6 62037.302041                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu7 62467.786906                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 62464.268326                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 56994.955295                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 56951.348078                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 56927.564088                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 56965.187477                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 56915.194646                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 56938.064911                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 56817.324255                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 56879.024705                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 56923.450527                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 56994.955295                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 56951.348078                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 56927.564088                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 56965.187477                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 56915.194646                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 56938.064911                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 56817.324255                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 56879.024705                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 56923.450527                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs             19361                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                     3488                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      5.550745                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks                6515                       # number of writebacks
system.l2c.writebacks::total                     6515                       # number of writebacks
system.l2c.UpgradeReq_mshr_hits::cpu0               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu3               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu5               2                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu7               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::total              5                       # number of UpgradeReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu0                4                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu1                5                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu2                3                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu3                3                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu4                5                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5                4                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu6                4                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu7                6                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total              34                       # number of ReadExReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0            7                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1           10                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu2           10                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3            8                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu4           10                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu5           10                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu6            5                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu7            9                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           69                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0                  11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1                  15                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2                  13                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3                  11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4                  15                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5                  14                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6                   9                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7                  15                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                103                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0                 11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1                 15                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2                 13                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3                 11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4                 15                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5                 14                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6                  9                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7                 15                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               103                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         1301                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         1301                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0          1977                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1          2026                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2          2150                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3          2090                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4          2034                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5          2069                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6          2011                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7          2017                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        16374                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0           4709                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1           4650                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2           4604                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3           4591                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4           4655                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5           4570                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6           4695                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7           4639                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         37113                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0          738                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1          693                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2          735                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3          732                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu4          709                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu5          731                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu6          730                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu7          770                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total         5838                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0              5447                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1              5343                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2              5339                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3              5323                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4              5364                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5              5301                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6              5425                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7              5409                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            42951                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0             5447                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1             5343                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2             5339                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3             5323                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4             5364                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5             5301                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6             5425                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7             5409                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           42951                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0         9828                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1         9840                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2         9890                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3         9730                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu4         9580                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu5         9974                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu6         9904                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu7         9744                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        78490                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0         5350                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1         5428                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2         5478                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3         5268                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu4         5521                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu5         5505                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu6         5477                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu7         5442                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        43469                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0        15178                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1        15268                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2        15368                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3        14998                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu4        15101                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu5        15479                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu6        15381                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu7        15186                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       121959                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0     89855482                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1     92102479                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2     97577479                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3     94929976                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4     92285490                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5     94032976                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6     91255478                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7     91583480                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    743622840                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0    217693404                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1    214050407                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2    211784914                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3    212060892                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4    214472426                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5    210317416                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6    216067923                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7    213260425                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1709707807                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0     38583562                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1     37264417                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2     38987911                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3     38163918                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu4     37564408                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu5     38848899                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu6     38077918                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu7     40630907                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total    308121940                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0    256276966                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1    251314824                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2    250772825                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3    250224810                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4    252036834                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5    249166315                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6    254145841                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7    253891332                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   2017829747                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0    256276966                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1    251314824                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2    250772825                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3    250224810                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4    252036834                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5    249166315                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6    254145841                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7    253891332                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   2017829747                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    441544704                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    442822362                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    445114191                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    438042708                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    431552369                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    448559865                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    445961194                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    437879200                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   3531476593                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    247492955                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    251693437                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    254031943                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    244392771                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    255999435                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    255282926                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    253764437                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    253334431                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2015992335                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0    689037659                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1    694515799                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2    699146134                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3    682435479                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4    687551804                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5    703842791                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6    699725631                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7    691213631                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   5547468928                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.888939                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.883173                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.888430                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.880371                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.875592                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.879303                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.882018                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.871274                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.881128                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.732007                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.730787                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.720839                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.723676                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.716926                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.718440                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.723198                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.724731                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.723817                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0     0.064364                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1     0.060598                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2     0.063139                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3     0.062229                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu4     0.061786                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu5     0.063510                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu6     0.064653                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu7     0.065930                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.063277                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0       0.304319                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1       0.300185                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2       0.296150                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3       0.293975                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4       0.298531                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5       0.296626                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6       0.305067                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7       0.299170                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.299237                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0      0.304319                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1      0.300185                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2      0.296150                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3      0.293975                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4      0.298531                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5      0.296626                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6      0.305067                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7      0.299170                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.299237                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 45450.420840                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 45460.256170                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 45384.873953                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 45421.041148                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 45371.430678                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 45448.514258                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 45378.159125                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 45405.790778                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 45414.855258                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 46229.221491                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 46032.345591                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 46000.198523                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 46190.566761                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 46073.560902                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 46021.316411                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 46020.856869                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 45971.206079                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 46067.626088                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 52281.249322                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 53772.607504                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 53044.776871                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 52136.500000                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 52982.239774                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 53144.868673                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 52161.531507                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 52767.411688                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 52778.681055                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 47049.195153                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 47036.276249                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 46969.999063                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 47008.230321                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 46986.732662                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 47003.643652                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 46847.159631                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 46938.682196                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 46979.808316                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 47049.195153                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 47036.276249                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 46969.999063                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 47008.230321                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 46986.732662                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 47003.643652                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 46847.159631                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 46938.682196                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 46979.808316                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44927.218559                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 45002.272561                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 45006.490495                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 45019.805550                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 45047.220146                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44972.916082                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 45028.391963                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44938.341544                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44992.694522                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 46260.365421                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 46369.461496                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 46373.118474                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 46391.945900                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 46368.309183                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 46372.920254                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 46332.743655                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 46551.714627                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 46377.702156                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 45397.131308                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 45488.328465                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 45493.631832                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 45501.765502                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 45530.216807                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 45470.817947                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 45492.856836                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 45516.504083                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 45486.343181                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.snoop_filter.tot_requests        127987                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       121935                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.trans_dist::ReadReq               78487                       # Transaction distribution
system.membus.trans_dist::ReadResp              84311                       # Transaction distribution
system.membus.trans_dist::WriteReq              43469                       # Transaction distribution
system.membus.trans_dist::WriteResp             43465                       # Transaction distribution
system.membus.trans_dist::Writeback              6515                       # Transaction distribution
system.membus.trans_dist::CleanEvict             1324                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            61199                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           50308                       # Transaction distribution
system.membus.trans_dist::ReadExReq             49356                       # Transaction distribution
system.membus.trans_dist::ReadExResp             3201                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq          5828                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       427463                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 427463                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1116768                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                 1116768                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                            57043                       # Total snoops (count)
system.membus.snoop_fanout::samples            255514                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  255514    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              255514                       # Request fanout histogram
system.membus.reqLayer0.occupancy           292277246                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization              56.4                       # Layer utilization (%)
system.membus.respLayer0.occupancy          310111858                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization             59.8                       # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests       663155                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       282754                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       334620                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops          12643                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         6068                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops         6575                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              78490                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            370569                       # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate            4                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             43469                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            43464                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback            83812                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict           20730                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           29471                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          29469                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           161822                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          161815                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       292094                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       122083                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       122289                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       122819                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       122567                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       122495                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       122827                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       122357                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       122446                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total                979883                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1778056                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1772835                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1781127                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1803862                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1797691                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1778038                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1761236                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1781905                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               14254750                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          335326                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples           800967                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.187618                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           1.006332                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 216572     27.04%     27.04% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 322054     40.21%     67.25% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 178446     22.28%     89.53% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                  65924      8.23%     97.76% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                  15526      1.94%     99.69% # Request fanout histogram
system.toL2Bus.snoop_fanout::5                   2251      0.28%     99.98% # Request fanout histogram
system.toL2Bus.snoop_fanout::6                    192      0.02%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7                      2      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             800967                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          495267856                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization             95.5                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         101287347                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization            19.5                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         101004376                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization            19.5                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         101361922                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization            19.6                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         101351771                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization            19.6                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy         101153250                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization            19.5                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy         101246693                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization            19.5                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy         101297808                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization            19.5                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy         101337760                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization            19.5                       # Layer utilization (%)

---------- End Simulation Statistics   ----------