path: root/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000530                       # Number of seconds simulated
sim_ticks                                   530176500                       # Number of ticks simulated
final_tick                                  530176500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_tick_rate                              118834220                       # Simulator tick rate (ticks/s)
host_mem_usage                                 236308                       # Number of bytes of host memory used
host_seconds                                     4.46                       # Real time elapsed on the host
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0                 78184                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1                 80178                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2                 79911                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3                 80308                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu4                 82157                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu5                 80611                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu6                 79164                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu7                 81441                       # Number of bytes read from this memory
system.physmem.bytes_read::total               641954                       # Number of bytes read from this memory
system.physmem.bytes_written::writebacks       404160                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0               5485                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1               5400                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu2               5418                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu3               5526                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu4               5422                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu5               5458                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu6               5386                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu7               5538                       # Number of bytes written to this memory
system.physmem.bytes_written::total            447793                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0                  10774                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1                  10815                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2                  10863                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3                  11071                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4                  10904                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5                  10870                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6                  10935                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7                  10881                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 87113                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks            6315                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0                  5485                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1                  5400                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2                  5418                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3                  5526                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4                  5422                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5                  5458                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6                  5386                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7                  5538                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                49948                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0                147467872                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1                151228883                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2                150725277                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3                151474085                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4                154961602                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5                152045592                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6                149316313                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7                153611109                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              1210830733                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         762312173                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0                10345611                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1                10185287                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2                10219238                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3                10422944                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4                10226783                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5                10294685                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6                10158881                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7                10445578                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              844611181                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         762312173                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0               157813483                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1               161414171                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2               160944516                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3               161897029                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4               165188385                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5               162340277                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6               159475194                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7               164056687                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             2055441914                       # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.num_reads                           99175                       # number of read accesses completed
system.cpu0.num_writes                          54789                       # number of write accesses completed
system.cpu0.l1c.tags.replacements               22440                       # number of replacements
system.cpu0.l1c.tags.tagsinuse             392.189512                       # Cycle average of tags in use
system.cpu0.l1c.tags.total_refs                 13440                       # Total number of references to valid blocks.
system.cpu0.l1c.tags.sampled_refs               22832                       # Sample count of references to valid blocks.
system.cpu0.l1c.tags.avg_refs                0.588648                       # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu0.l1c.tags.occ_blocks::cpu0      392.189512                       # Average occupied blocks per requestor
system.cpu0.l1c.tags.occ_percent::cpu0       0.765995                       # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_percent::total      0.765995                       # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_task_id_blocks::1024          392                       # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::0          373                       # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
system.cpu0.l1c.tags.occ_task_id_percent::1024     0.765625                       # Percentage of cache occupancy per task id
system.cpu0.l1c.tags.tag_accesses              338141                       # Number of tag accesses
system.cpu0.l1c.tags.data_accesses             338141                       # Number of data accesses
system.cpu0.l1c.ReadReq_hits::cpu0               8693                       # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total              8693                       # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0              1204                       # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total             1204                       # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0                9897                       # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total               9897                       # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0               9897                       # number of overall hits
system.cpu0.l1c.overall_hits::total              9897                       # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0            36509                       # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total           36509                       # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0           23927                       # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total          23927                       # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0             60436                       # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total            60436                       # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0            60436                       # number of overall misses
system.cpu0.l1c.overall_misses::total           60436                       # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0    645236912                       # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total    645236912                       # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0    543361201                       # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total    543361201                       # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0   1188598113                       # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total   1188598113                       # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0   1188598113                       # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total   1188598113                       # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0          45202                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total         45202                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0         25131                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total        25131                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0           70333                       # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total          70333                       # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0          70333                       # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total         70333                       # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.807686                       # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total     0.807686                       # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.952091                       # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total     0.952091                       # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0       0.859284                       # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total      0.859284                       # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0      0.859284                       # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total     0.859284                       # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 17673.365800                       # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 17673.365800                       # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 22709.123626                       # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 22709.123626                       # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 19667.054620                       # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 19667.054620                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 19667.054620                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 19667.054620                       # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs       716464                       # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_mshrs               58624                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_mshrs    12.221343                       # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu0.l1c.writebacks::writebacks           9950                       # number of writebacks
system.cpu0.l1c.writebacks::total                9950                       # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36509                       # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total        36509                       # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23927                       # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total        23927                       # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0        60436                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total        60436                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0        60436                       # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total        60436                       # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0         9705                       # number of ReadReq MSHR uncacheable
system.cpu0.l1c.ReadReq_mshr_uncacheable::total         9705                       # number of ReadReq MSHR uncacheable
system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0         5489                       # number of WriteReq MSHR uncacheable
system.cpu0.l1c.WriteReq_mshr_uncacheable::total         5489                       # number of WriteReq MSHR uncacheable
system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0        15194                       # number of overall MSHR uncacheable misses
system.cpu0.l1c.overall_mshr_uncacheable_misses::total        15194                       # number of overall MSHR uncacheable misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    608727912                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total    608727912                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    519435201                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total    519435201                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1128163113                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total   1128163113                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1128163113                       # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total   1128163113                       # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    718425919                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    718425919                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0    939004763                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total    939004763                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   1657430682                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total   1657430682                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.807686                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.807686                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.952091                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.952091                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.859284                       # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total     0.859284                       # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.859284                       # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total     0.859284                       # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 16673.365800                       # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 16673.365800                       # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 21709.165420                       # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 21709.165420                       # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 18667.071166                       # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 18667.071166                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 18667.071166                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 18667.071166                       # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 74026.369809                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74026.369809                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 171070.279286                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 171070.279286                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 109084.551928                       # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 109084.551928                       # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu1.num_reads                           99705                       # number of read accesses completed
system.cpu1.num_writes                          54823                       # number of write accesses completed
system.cpu1.l1c.tags.replacements               22335                       # number of replacements
system.cpu1.l1c.tags.tagsinuse             390.697643                       # Cycle average of tags in use
system.cpu1.l1c.tags.total_refs                 13624                       # Total number of references to valid blocks.
system.cpu1.l1c.tags.sampled_refs               22725                       # Sample count of references to valid blocks.
system.cpu1.l1c.tags.avg_refs                0.599516                       # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu1.l1c.tags.occ_blocks::cpu1      390.697643                       # Average occupied blocks per requestor
system.cpu1.l1c.tags.occ_percent::cpu1       0.763081                       # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_percent::total      0.763081                       # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_task_id_blocks::1024          390                       # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::0          375                       # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::1           15                       # Occupied blocks per task id
system.cpu1.l1c.tags.occ_task_id_percent::1024     0.761719                       # Percentage of cache occupancy per task id
system.cpu1.l1c.tags.tag_accesses              339221                       # Number of tag accesses
system.cpu1.l1c.tags.data_accesses             339221                       # Number of data accesses
system.cpu1.l1c.ReadReq_hits::cpu1               8840                       # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total              8840                       # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1              1148                       # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total             1148                       # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1                9988                       # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total               9988                       # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1               9988                       # number of overall hits
system.cpu1.l1c.overall_hits::total              9988                       # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1            36605                       # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total           36605                       # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1           23987                       # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total          23987                       # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1             60592                       # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total            60592                       # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1            60592                       # number of overall misses
system.cpu1.l1c.overall_misses::total           60592                       # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1    646842299                       # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total    646842299                       # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1    543658224                       # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total    543658224                       # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1   1190500523                       # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total   1190500523                       # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1   1190500523                       # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total   1190500523                       # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1          45445                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total         45445                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1         25135                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total        25135                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1           70580                       # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total          70580                       # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1          70580                       # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total         70580                       # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.805479                       # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total     0.805479                       # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.954327                       # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total     0.954327                       # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1       0.858487                       # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total      0.858487                       # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1      0.858487                       # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total     0.858487                       # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 17670.872804                       # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 17670.872804                       # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 22664.702714                       # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 22664.702714                       # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 19647.816923                       # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 19647.816923                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 19647.816923                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 19647.816923                       # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs       718948                       # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_mshrs               59028                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_mshrs    12.179779                       # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu1.l1c.writebacks::writebacks           9932                       # number of writebacks
system.cpu1.l1c.writebacks::total                9932                       # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36605                       # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total        36605                       # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23987                       # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total        23987                       # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1        60592                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total        60592                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1        60592                       # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total        60592                       # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1         9715                       # number of ReadReq MSHR uncacheable
system.cpu1.l1c.ReadReq_mshr_uncacheable::total         9715                       # number of ReadReq MSHR uncacheable
system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1         5400                       # number of WriteReq MSHR uncacheable
system.cpu1.l1c.WriteReq_mshr_uncacheable::total         5400                       # number of WriteReq MSHR uncacheable
system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1        15115                       # number of overall MSHR uncacheable misses
system.cpu1.l1c.overall_mshr_uncacheable_misses::total        15115                       # number of overall MSHR uncacheable misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    610238299                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total    610238299                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    519672224                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total    519672224                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1129910523                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total   1129910523                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1129910523                       # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total   1129910523                       # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    721621903                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    721621903                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1    954237303                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total    954237303                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   1675859206                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total   1675859206                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.805479                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.805479                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.954327                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.954327                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.858487                       # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total     0.858487                       # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.858487                       # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total     0.858487                       # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 16670.900123                       # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 16670.900123                       # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 21664.744403                       # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 21664.744403                       # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 18647.849931                       # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 18647.849931                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 18647.849931                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 18647.849931                       # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 74279.145960                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74279.145960                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 176710.611667                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 176710.611667                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 110873.913728                       # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 110873.913728                       # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu2.num_reads                           99117                       # number of read accesses completed
system.cpu2.num_writes                          54908                       # number of write accesses completed
system.cpu2.l1c.tags.replacements               22381                       # number of replacements
system.cpu2.l1c.tags.tagsinuse             392.253516                       # Cycle average of tags in use
system.cpu2.l1c.tags.total_refs                 13534                       # Total number of references to valid blocks.
system.cpu2.l1c.tags.sampled_refs               22797                       # Sample count of references to valid blocks.
system.cpu2.l1c.tags.avg_refs                0.593675                       # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu2.l1c.tags.occ_blocks::cpu2      392.253516                       # Average occupied blocks per requestor
system.cpu2.l1c.tags.occ_percent::cpu2       0.766120                       # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_percent::total      0.766120                       # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_task_id_blocks::1024          416                       # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::0          405                       # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
system.cpu2.l1c.tags.occ_task_id_percent::1024     0.812500                       # Percentage of cache occupancy per task id
system.cpu2.l1c.tags.tag_accesses              338010                       # Number of tag accesses
system.cpu2.l1c.tags.data_accesses             338010                       # Number of data accesses
system.cpu2.l1c.ReadReq_hits::cpu2               8679                       # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total              8679                       # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2              1137                       # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total             1137                       # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2                9816                       # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total               9816                       # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2               9816                       # number of overall hits
system.cpu2.l1c.overall_hits::total              9816                       # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2            36478                       # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total           36478                       # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2           24024                       # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total          24024                       # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2             60502                       # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total            60502                       # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2            60502                       # number of overall misses
system.cpu2.l1c.overall_misses::total           60502                       # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2    647459345                       # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total    647459345                       # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2    543523925                       # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total    543523925                       # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2   1190983270                       # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total   1190983270                       # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2   1190983270                       # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total   1190983270                       # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2          45157                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total         45157                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2         25161                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total        25161                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2           70318                       # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total          70318                       # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2          70318                       # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total         70318                       # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.807804                       # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total     0.807804                       # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.954811                       # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total     0.954811                       # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2       0.860406                       # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total      0.860406                       # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2      0.860406                       # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total     0.860406                       # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 17749.310406                       # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 17749.310406                       # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 22624.206002                       # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 22624.206002                       # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 19685.023140                       # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 19685.023140                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 19685.023140                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 19685.023140                       # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs       722959                       # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_mshrs               59032                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_mshrs    12.246900                       # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu2.l1c.writebacks::writebacks           9774                       # number of writebacks
system.cpu2.l1c.writebacks::total                9774                       # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36478                       # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total        36478                       # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2        24024                       # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total        24024                       # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2        60502                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total        60502                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2        60502                       # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total        60502                       # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2         9767                       # number of ReadReq MSHR uncacheable
system.cpu2.l1c.ReadReq_mshr_uncacheable::total         9767                       # number of ReadReq MSHR uncacheable
system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2         5419                       # number of WriteReq MSHR uncacheable
system.cpu2.l1c.WriteReq_mshr_uncacheable::total         5419                       # number of WriteReq MSHR uncacheable
system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2        15186                       # number of overall MSHR uncacheable misses
system.cpu2.l1c.overall_mshr_uncacheable_misses::total        15186                       # number of overall MSHR uncacheable misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    610981345                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total    610981345                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    519499925                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total    519499925                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1130481270                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total   1130481270                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1130481270                       # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total   1130481270                       # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    722748371                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    722748371                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2    934057840                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total    934057840                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   1656806211                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total   1656806211                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.807804                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.807804                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.954811                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.954811                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.860406                       # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total     0.860406                       # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.860406                       # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total     0.860406                       # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 16749.310406                       # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 16749.310406                       # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 21624.206002                       # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 21624.206002                       # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 18685.023140                       # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 18685.023140                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 18685.023140                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 18685.023140                       # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 73999.014129                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73999.014129                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 172367.196900                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 172367.196900                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 109100.896286                       # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 109100.896286                       # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu3.num_reads                          100000                       # number of read accesses completed
system.cpu3.num_writes                          55255                       # number of write accesses completed
system.cpu3.l1c.tags.replacements               22194                       # number of replacements
system.cpu3.l1c.tags.tagsinuse             391.395366                       # Cycle average of tags in use
system.cpu3.l1c.tags.total_refs                 13678                       # Total number of references to valid blocks.
system.cpu3.l1c.tags.sampled_refs               22603                       # Sample count of references to valid blocks.
system.cpu3.l1c.tags.avg_refs                0.605141                       # Average number of references to valid blocks.
system.cpu3.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu3.l1c.tags.occ_blocks::cpu3      391.395366                       # Average occupied blocks per requestor
system.cpu3.l1c.tags.occ_percent::cpu3       0.764444                       # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_percent::total      0.764444                       # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_task_id_blocks::1024          409                       # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::0          403                       # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
system.cpu3.l1c.tags.occ_task_id_percent::1024     0.798828                       # Percentage of cache occupancy per task id
system.cpu3.l1c.tags.tag_accesses              337339                       # Number of tag accesses
system.cpu3.l1c.tags.data_accesses             337339                       # Number of data accesses
system.cpu3.l1c.ReadReq_hits::cpu3               8923                       # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total              8923                       # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3              1132                       # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total             1132                       # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3               10055                       # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total              10055                       # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3              10055                       # number of overall hits
system.cpu3.l1c.overall_hits::total             10055                       # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3            36521                       # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total           36521                       # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3           23639                       # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total          23639                       # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3             60160                       # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total            60160                       # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3            60160                       # number of overall misses
system.cpu3.l1c.overall_misses::total           60160                       # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3    641069966                       # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total    641069966                       # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3    531956623                       # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total    531956623                       # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3   1173026589                       # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total   1173026589                       # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3   1173026589                       # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total   1173026589                       # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3          45444                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total         45444                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3         24771                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total        24771                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3           70215                       # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total          70215                       # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3          70215                       # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total         70215                       # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.803648                       # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total     0.803648                       # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.954301                       # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total     0.954301                       # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3       0.856797                       # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total      0.856797                       # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3      0.856797                       # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total     0.856797                       # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 17553.461461                       # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 17553.461461                       # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 22503.347138                       # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 22503.347138                       # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 19498.447291                       # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 19498.447291                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 19498.447291                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 19498.447291                       # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs       718925                       # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_mshrs               58812                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_mshrs    12.224121                       # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu3.l1c.writebacks::writebacks           9851                       # number of writebacks
system.cpu3.l1c.writebacks::total                9851                       # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36521                       # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total        36521                       # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23639                       # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total        23639                       # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3        60160                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total        60160                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3        60160                       # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total        60160                       # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3         9973                       # number of ReadReq MSHR uncacheable
system.cpu3.l1c.ReadReq_mshr_uncacheable::total         9973                       # number of ReadReq MSHR uncacheable
system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3         5527                       # number of WriteReq MSHR uncacheable
system.cpu3.l1c.WriteReq_mshr_uncacheable::total         5527                       # number of WriteReq MSHR uncacheable
system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3        15500                       # number of overall MSHR uncacheable misses
system.cpu3.l1c.overall_mshr_uncacheable_misses::total        15500                       # number of overall MSHR uncacheable misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    604549966                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total    604549966                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    508318623                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total    508318623                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1112868589                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total   1112868589                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1112868589                       # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total   1112868589                       # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    738348758                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    738348758                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3    962176807                       # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total    962176807                       # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   1700525565                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total   1700525565                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.803648                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.803648                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.954301                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.954301                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.856797                       # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total     0.856797                       # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.856797                       # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total     0.856797                       # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 16553.488842                       # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 16553.488842                       # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 21503.389441                       # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 21503.389441                       # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 18498.480535                       # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 18498.480535                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 18498.480535                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 18498.480535                       # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 74034.769678                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74034.769678                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 174086.630541                       # average WriteReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174086.630541                       # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 109711.326774                       # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 109711.326774                       # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu4.num_reads                           98958                       # number of read accesses completed
system.cpu4.num_writes                          54718                       # number of write accesses completed
system.cpu4.l1c.tags.replacements               22445                       # number of replacements
system.cpu4.l1c.tags.tagsinuse             392.205168                       # Cycle average of tags in use
system.cpu4.l1c.tags.total_refs                 13326                       # Total number of references to valid blocks.
system.cpu4.l1c.tags.sampled_refs               22839                       # Sample count of references to valid blocks.
system.cpu4.l1c.tags.avg_refs                0.583476                       # Average number of references to valid blocks.
system.cpu4.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu4.l1c.tags.occ_blocks::cpu4      392.205168                       # Average occupied blocks per requestor
system.cpu4.l1c.tags.occ_percent::cpu4       0.766026                       # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_percent::total      0.766026                       # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_task_id_blocks::1024          394                       # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::0          383                       # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
system.cpu4.l1c.tags.occ_task_id_percent::1024     0.769531                       # Percentage of cache occupancy per task id
system.cpu4.l1c.tags.tag_accesses              336585                       # Number of tag accesses
system.cpu4.l1c.tags.data_accesses             336585                       # Number of data accesses
system.cpu4.l1c.ReadReq_hits::cpu4               8551                       # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total              8551                       # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4              1195                       # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total             1195                       # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4                9746                       # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total               9746                       # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4               9746                       # number of overall hits
system.cpu4.l1c.overall_hits::total              9746                       # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4            36430                       # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total           36430                       # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4           23820                       # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total          23820                       # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4             60250                       # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total            60250                       # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4            60250                       # number of overall misses
system.cpu4.l1c.overall_misses::total           60250                       # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4    646410865                       # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total    646410865                       # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4    541537295                       # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total    541537295                       # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4   1187948160                       # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total   1187948160                       # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4   1187948160                       # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total   1187948160                       # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4          44981                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total         44981                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4         25015                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total        25015                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4           69996                       # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total          69996                       # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4          69996                       # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total         69996                       # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.809898                       # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total     0.809898                       # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.952229                       # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total     0.952229                       # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4       0.860763                       # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total      0.860763                       # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4      0.860763                       # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total     0.860763                       # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 17743.916141                       # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 17743.916141                       # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 22734.563182                       # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 22734.563182                       # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 19716.981909                       # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 19716.981909                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 19716.981909                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 19716.981909                       # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs       719943                       # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_mshrs               58800                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_mshrs    12.243929                       # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu4.l1c.writebacks::writebacks           9851                       # number of writebacks
system.cpu4.l1c.writebacks::total                9851                       # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36430                       # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total        36430                       # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23820                       # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total        23820                       # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4        60250                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total        60250                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4        60250                       # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total        60250                       # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4         9773                       # number of ReadReq MSHR uncacheable
system.cpu4.l1c.ReadReq_mshr_uncacheable::total         9773                       # number of ReadReq MSHR uncacheable
system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4         5424                       # number of WriteReq MSHR uncacheable
system.cpu4.l1c.WriteReq_mshr_uncacheable::total         5424                       # number of WriteReq MSHR uncacheable
system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4        15197                       # number of overall MSHR uncacheable misses
system.cpu4.l1c.overall_mshr_uncacheable_misses::total        15197                       # number of overall MSHR uncacheable misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    609980865                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total    609980865                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    517717295                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total    517717295                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1127698160                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total   1127698160                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1127698160                       # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total   1127698160                       # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    724329762                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    724329762                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4    945564873                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total    945564873                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   1669894635                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total   1669894635                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.809898                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.809898                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.952229                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.952229                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.860763                       # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total     0.860763                       # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.860763                       # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total     0.860763                       # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 16743.916141                       # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 16743.916141                       # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 21734.563182                       # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 21734.563182                       # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 18716.981909                       # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 18716.981909                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 18716.981909                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 18716.981909                       # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 74115.395682                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74115.395682                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 174329.806969                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174329.806969                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 109883.176614                       # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 109883.176614                       # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu5.num_reads                           99011                       # number of read accesses completed
system.cpu5.num_writes                          55007                       # number of write accesses completed
system.cpu5.l1c.tags.replacements               22453                       # number of replacements
system.cpu5.l1c.tags.tagsinuse             391.576438                       # Cycle average of tags in use
system.cpu5.l1c.tags.total_refs                 13255                       # Total number of references to valid blocks.
system.cpu5.l1c.tags.sampled_refs               22854                       # Sample count of references to valid blocks.
system.cpu5.l1c.tags.avg_refs                0.579986                       # Average number of references to valid blocks.
system.cpu5.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu5.l1c.tags.occ_blocks::cpu5      391.576438                       # Average occupied blocks per requestor
system.cpu5.l1c.tags.occ_percent::cpu5       0.764798                       # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_percent::total      0.764798                       # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_task_id_blocks::1024          401                       # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::0          384                       # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
system.cpu5.l1c.tags.occ_task_id_percent::1024     0.783203                       # Percentage of cache occupancy per task id
system.cpu5.l1c.tags.tag_accesses              336606                       # Number of tag accesses
system.cpu5.l1c.tags.data_accesses             336606                       # Number of data accesses
system.cpu5.l1c.ReadReq_hits::cpu5               8524                       # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total              8524                       # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5              1134                       # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total             1134                       # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5                9658                       # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total               9658                       # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5               9658                       # number of overall hits
system.cpu5.l1c.overall_hits::total              9658                       # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5            36435                       # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total           36435                       # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5           23892                       # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total          23892                       # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5             60327                       # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total            60327                       # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5            60327                       # number of overall misses
system.cpu5.l1c.overall_misses::total           60327                       # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5    644721410                       # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total    644721410                       # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5    540612961                       # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total    540612961                       # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5   1185334371                       # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total   1185334371                       # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5   1185334371                       # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total   1185334371                       # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5          44959                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total         44959                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5         25026                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total        25026                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5           69985                       # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total          69985                       # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5          69985                       # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total         69985                       # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.810405                       # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total     0.810405                       # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.954687                       # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total     0.954687                       # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5       0.861999                       # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total      0.861999                       # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5      0.861999                       # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total     0.861999                       # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 17695.112117                       # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 17695.112117                       # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 22627.363176                       # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 22627.363176                       # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 19648.488587                       # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 19648.488587                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 19648.488587                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 19648.488587                       # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs       717184                       # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_mshrs               58708                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_mshrs    12.216120                       # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu5.l1c.writebacks::writebacks           9910                       # number of writebacks
system.cpu5.l1c.writebacks::total                9910                       # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36435                       # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total        36435                       # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23892                       # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total        23892                       # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5        60327                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total        60327                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5        60327                       # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total        60327                       # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5         9763                       # number of ReadReq MSHR uncacheable
system.cpu5.l1c.ReadReq_mshr_uncacheable::total         9763                       # number of ReadReq MSHR uncacheable
system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5         5458                       # number of WriteReq MSHR uncacheable
system.cpu5.l1c.WriteReq_mshr_uncacheable::total         5458                       # number of WriteReq MSHR uncacheable
system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5        15221                       # number of overall MSHR uncacheable misses
system.cpu5.l1c.overall_mshr_uncacheable_misses::total        15221                       # number of overall MSHR uncacheable misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    608288410                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total    608288410                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    516720961                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total    516720961                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1125009371                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total   1125009371                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1125009371                       # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total   1125009371                       # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    723860386                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    723860386                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5    946272316                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total    946272316                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   1670132702                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total   1670132702                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.810405                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.810405                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.954687                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.954687                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.861999                       # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total     0.861999                       # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.861999                       # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total     0.861999                       # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 16695.167010                       # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 16695.167010                       # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 21627.363176                       # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 21627.363176                       # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 18648.521740                       # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 18648.521740                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 18648.521740                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 18648.521740                       # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 74143.233227                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74143.233227                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 173373.454745                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173373.454745                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 109725.556928                       # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 109725.556928                       # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu6.num_reads                           99860                       # number of read accesses completed
system.cpu6.num_writes                          55212                       # number of write accesses completed
system.cpu6.l1c.tags.replacements               22379                       # number of replacements
system.cpu6.l1c.tags.tagsinuse             392.641405                       # Cycle average of tags in use
system.cpu6.l1c.tags.total_refs                 13476                       # Total number of references to valid blocks.
system.cpu6.l1c.tags.sampled_refs               22769                       # Sample count of references to valid blocks.
system.cpu6.l1c.tags.avg_refs                0.591857                       # Average number of references to valid blocks.
system.cpu6.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu6.l1c.tags.occ_blocks::cpu6      392.641405                       # Average occupied blocks per requestor
system.cpu6.l1c.tags.occ_percent::cpu6       0.766878                       # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_percent::total      0.766878                       # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_task_id_blocks::1024          390                       # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::0          383                       # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
system.cpu6.l1c.tags.occ_task_id_percent::1024     0.761719                       # Percentage of cache occupancy per task id
system.cpu6.l1c.tags.tag_accesses              338111                       # Number of tag accesses
system.cpu6.l1c.tags.data_accesses             338111                       # Number of data accesses
system.cpu6.l1c.ReadReq_hits::cpu6               8761                       # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total              8761                       # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6              1100                       # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total             1100                       # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6                9861                       # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total               9861                       # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6               9861                       # number of overall hits
system.cpu6.l1c.overall_hits::total              9861                       # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6            36533                       # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total           36533                       # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6           23935                       # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total          23935                       # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6             60468                       # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total            60468                       # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6            60468                       # number of overall misses
system.cpu6.l1c.overall_misses::total           60468                       # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6    641137331                       # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total    641137331                       # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6    545446790                       # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total    545446790                       # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6   1186584121                       # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total   1186584121                       # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6   1186584121                       # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total   1186584121                       # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6          45294                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total         45294                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6         25035                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total        25035                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6           70329                       # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total          70329                       # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6          70329                       # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total         70329                       # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.806575                       # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total     0.806575                       # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.956062                       # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total     0.956062                       # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6       0.859788                       # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total      0.859788                       # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6      0.859788                       # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total     0.859788                       # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 17549.539622                       # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 17549.539622                       # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 22788.668895                       # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 22788.668895                       # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 19623.339965                       # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 19623.339965                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 19623.339965                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 19623.339965                       # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs       722832                       # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_mshrs               59177                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_mshrs    12.214746                       # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu6.l1c.writebacks::writebacks           9900                       # number of writebacks
system.cpu6.l1c.writebacks::total                9900                       # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36533                       # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total        36533                       # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23935                       # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total        23935                       # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6        60468                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total        60468                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6        60468                       # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total        60468                       # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6         9853                       # number of ReadReq MSHR uncacheable
system.cpu6.l1c.ReadReq_mshr_uncacheable::total         9853                       # number of ReadReq MSHR uncacheable
system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6         5386                       # number of WriteReq MSHR uncacheable
system.cpu6.l1c.WriteReq_mshr_uncacheable::total         5386                       # number of WriteReq MSHR uncacheable
system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6        15239                       # number of overall MSHR uncacheable misses
system.cpu6.l1c.overall_mshr_uncacheable_misses::total        15239                       # number of overall MSHR uncacheable misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    604606331                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total    604606331                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    521511790                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total    521511790                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1126118121                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total   1126118121                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1126118121                       # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total   1126118121                       # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    730958843                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    730958843                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6    936459347                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total    936459347                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   1667418190                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total   1667418190                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.806575                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.806575                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.956062                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.956062                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.859788                       # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total     0.859788                       # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.859788                       # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total     0.859788                       # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 16549.594367                       # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 16549.594367                       # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 21788.668895                       # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 21788.668895                       # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 18623.373040                       # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 18623.373040                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 18623.373040                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 18623.373040                       # average overall mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 74186.424744                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74186.424744                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 173869.169514                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173869.169514                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 109417.822036                       # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 109417.822036                       # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu7.num_reads                           99316                       # number of read accesses completed
system.cpu7.num_writes                          55530                       # number of write accesses completed
system.cpu7.l1c.tags.replacements               22262                       # number of replacements
system.cpu7.l1c.tags.tagsinuse             392.242621                       # Cycle average of tags in use
system.cpu7.l1c.tags.total_refs                 13656                       # Total number of references to valid blocks.
system.cpu7.l1c.tags.sampled_refs               22650                       # Sample count of references to valid blocks.
system.cpu7.l1c.tags.avg_refs                0.602914                       # Average number of references to valid blocks.
system.cpu7.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu7.l1c.tags.occ_blocks::cpu7      392.242621                       # Average occupied blocks per requestor
system.cpu7.l1c.tags.occ_percent::cpu7       0.766099                       # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_percent::total      0.766099                       # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_task_id_blocks::1024          388                       # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::0          370                       # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
system.cpu7.l1c.tags.occ_task_id_percent::1024     0.757812                       # Percentage of cache occupancy per task id
system.cpu7.l1c.tags.tag_accesses              338652                       # Number of tag accesses
system.cpu7.l1c.tags.data_accesses             338652                       # Number of data accesses
system.cpu7.l1c.ReadReq_hits::cpu7               8912                       # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total              8912                       # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7              1186                       # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total             1186                       # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7               10098                       # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total              10098                       # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7              10098                       # number of overall hits
system.cpu7.l1c.overall_hits::total             10098                       # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7            36380                       # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total           36380                       # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7           23998                       # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total          23998                       # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7             60378                       # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total            60378                       # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7            60378                       # number of overall misses
system.cpu7.l1c.overall_misses::total           60378                       # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7    644409565                       # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total    644409565                       # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7    538142857                       # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total    538142857                       # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7   1182552422                       # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total   1182552422                       # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7   1182552422                       # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total   1182552422                       # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7          45292                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total         45292                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7         25184                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total        25184                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7           70476                       # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total          70476                       # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7          70476                       # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total         70476                       # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.803232                       # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total     0.803232                       # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.952907                       # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total     0.952907                       # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7       0.856717                       # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total      0.856717                       # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7      0.856717                       # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total     0.856717                       # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 17713.292056                       # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 17713.292056                       # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 22424.487749                       # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 22424.487749                       # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 19585.816390                       # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 19585.816390                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 19585.816390                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 19585.816390                       # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs       716334                       # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_mshrs               58812                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_mshrs    12.180065                       # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu7.l1c.writebacks::writebacks           9846                       # number of writebacks
system.cpu7.l1c.writebacks::total                9846                       # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36380                       # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total        36380                       # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23998                       # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total        23998                       # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7        60378                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total        60378                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7        60378                       # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total        60378                       # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7         9762                       # number of ReadReq MSHR uncacheable
system.cpu7.l1c.ReadReq_mshr_uncacheable::total         9762                       # number of ReadReq MSHR uncacheable
system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7         5539                       # number of WriteReq MSHR uncacheable
system.cpu7.l1c.WriteReq_mshr_uncacheable::total         5539                       # number of WriteReq MSHR uncacheable
system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7        15301                       # number of overall MSHR uncacheable misses
system.cpu7.l1c.overall_mshr_uncacheable_misses::total        15301                       # number of overall MSHR uncacheable misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    608029565                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total    608029565                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    514144857                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total    514144857                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1122174422                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total   1122174422                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1122174422                       # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total   1122174422                       # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    722808914                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    722808914                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7    961004780                       # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total    961004780                       # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   1683813694                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total   1683813694                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.803232                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.803232                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.952907                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.952907                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.856717                       # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total     0.856717                       # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.856717                       # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total     0.856717                       # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 16713.292056                       # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 16713.292056                       # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 21424.487749                       # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 21424.487749                       # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 18585.816390                       # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 18585.816390                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 18585.816390                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 18585.816390                       # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 74043.117599                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74043.117599                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 173497.884095                       # average WriteReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173497.884095                       # average WriteReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 110045.990066                       # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 110045.990066                       # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                    13767                       # number of replacements
system.l2c.tags.tagsinuse                  787.442113                       # Cycle average of tags in use
system.l2c.tags.total_refs                     164717                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                    14568                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    11.306768                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks     730.095360                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0             6.568517                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1             7.047502                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2             7.052359                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3             7.453742                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu4             6.826765                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu5             7.175771                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu6             7.149899                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu7             8.072198                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.712984                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0            0.006415                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1            0.006882                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2            0.006887                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3            0.007279                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu4            0.006667                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu5            0.007008                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu6            0.006982                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu7            0.007883                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.768986                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024          801                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          661                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          140                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.782227                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  2101238                       # Number of tag accesses
system.l2c.tags.data_accesses                 2101238                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks        77585                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total           77585                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0                  280                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1                  286                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2                  296                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3                  265                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4                  264                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5                  299                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6                  295                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7                  273                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                2258                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0                  1755                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1                  1883                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2                  1739                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3                  1749                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4                  1791                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5                  1796                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6                  1820                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7                  1726                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                14259                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0             10845                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1             10830                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2             10896                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3             10859                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu4             10783                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu5             11038                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu6             10953                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu7             10583                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total            86787                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0                    12600                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1                    12713                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2                    12635                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3                    12608                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu4                    12574                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu5                    12834                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu6                    12773                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu7                    12309                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  101046                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0                   12600                       # number of overall hits
system.l2c.overall_hits::cpu1                   12713                       # number of overall hits
system.l2c.overall_hits::cpu2                   12635                       # number of overall hits
system.l2c.overall_hits::cpu3                   12608                       # number of overall hits
system.l2c.overall_hits::cpu4                   12574                       # number of overall hits
system.l2c.overall_hits::cpu5                   12834                       # number of overall hits
system.l2c.overall_hits::cpu6                   12773                       # number of overall hits
system.l2c.overall_hits::cpu7                   12309                       # number of overall hits
system.l2c.overall_hits::total                 101046                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0               2028                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1               2036                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2               2114                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3               2014                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4               2072                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5               1987                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6               2026                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7               2019                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             16296                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0                4674                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1                4592                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2                4655                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3                4541                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4                4557                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5                4639                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6                4724                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7                4602                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              36984                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0             715                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1             735                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2             738                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3             731                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu4             726                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu5             715                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu6             671                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu7             749                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total           5780                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0                   5389                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1                   5327                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2                   5393                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3                   5272                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu4                   5283                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu5                   5354                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu6                   5395                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu7                   5351                       # number of demand (read+write) misses
system.l2c.demand_misses::total                 42764                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0                  5389                       # number of overall misses
system.l2c.overall_misses::cpu1                  5327                       # number of overall misses
system.l2c.overall_misses::cpu2                  5393                       # number of overall misses
system.l2c.overall_misses::cpu3                  5272                       # number of overall misses
system.l2c.overall_misses::cpu4                  5283                       # number of overall misses
system.l2c.overall_misses::cpu5                  5354                       # number of overall misses
system.l2c.overall_misses::cpu6                  5395                       # number of overall misses
system.l2c.overall_misses::cpu7                  5351                       # number of overall misses
system.l2c.overall_misses::total                42764                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0     32787478                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1     32272475                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2     34405982                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3     32097495                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4     34646656                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5     31653981                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6     32901471                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7     32271475                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    263037013                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0     151347885                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1     149012881                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2     150333871                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3     147794053                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4     149925888                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5     151442380                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6     154217889                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7     149568871                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   1203643718                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0     49081904                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1     50341908                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2     51226892                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3     50079413                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu4     49691401                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu5     48946419                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu6     46272414                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu7     51820900                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total    397461251                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0        200429789                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1        199354789                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2        201560763                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3        197873466                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4        199617289                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5        200388799                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6        200490303                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7        201389771                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      1601104969                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0       200429789                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1       199354789                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2       201560763                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3       197873466                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4       199617289                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5       200388799                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6       200490303                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7       201389771                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     1601104969                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks        77585                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total        77585                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0             2308                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1             2322                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2             2410                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3             2279                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4             2336                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5             2286                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6             2321                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7             2292                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           18554                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0              6429                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1              6475                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2              6394                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3              6290                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4              6348                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5              6435                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6              6544                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7              6328                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            51243                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0         11560                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1         11565                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2         11634                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3         11590                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu4         11509                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu5         11753                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu6         11624                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu7         11332                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total        92567                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0                17989                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1                18040                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2                18028                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3                17880                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4                17857                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5                18188                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6                18168                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7                17660                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              143810                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0               17989                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1               18040                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2               18028                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3               17880                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4               17857                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5               18188                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6               18168                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7               17660                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             143810                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0        0.878683                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1        0.876830                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2        0.877178                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3        0.883721                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4        0.886986                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5        0.869204                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6        0.872900                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7        0.880890                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.878301                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0         0.727018                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1         0.709189                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2         0.728026                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3         0.721940                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4         0.717864                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5         0.720901                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6         0.721883                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7         0.727244                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.721738                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0     0.061851                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1     0.063554                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2     0.063435                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3     0.063072                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu4     0.063081                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu5     0.060836                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu6     0.057725                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu7     0.066096                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.062441                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0            0.299572                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1            0.295288                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2            0.299146                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3            0.294855                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4            0.295850                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5            0.294370                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6            0.296951                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7            0.303001                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.297365                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0           0.299572                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1           0.295288                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2           0.299146                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3           0.294855                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4           0.295850                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5           0.294370                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6           0.296951                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7           0.303001                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.297365                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0 16167.395464                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 15850.920923                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 16275.298959                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 15937.187190                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 16721.359073                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 15930.539004                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 16239.620434                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 15983.890540                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 16141.201092                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 32380.805520                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 32450.540287                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 32295.138776                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 32546.587316                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 32900.129032                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 32645.479629                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 32645.615792                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 32500.841156                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 32544.984804                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0 68646.019580                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1 68492.391837                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2 69413.132791                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3 68508.088919                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu4 68445.455923                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu5 68456.530070                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu6 68960.378539                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu7 69186.782377                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 68764.922318                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 37192.389868                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 37423.463300                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 37374.515668                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 37532.903263                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 37784.836078                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 37427.866829                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 37162.243373                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 37635.913100                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 37440.486601                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 37192.389868                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 37423.463300                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 37374.515668                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 37532.903263                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 37784.836078                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 37427.866829                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 37162.243373                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 37635.913100                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 37440.486601                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs             15217                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                     2217                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      6.863780                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks                6315                       # number of writebacks
system.l2c.writebacks::total                     6315                       # number of writebacks
system.l2c.UpgradeReq_mshr_hits::cpu3               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu4               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu7               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::total              3                       # number of UpgradeReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu0                6                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu1                4                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu2                5                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu3                5                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu4                2                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5                4                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu6                4                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu7                8                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total              38                       # number of ReadExReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0           13                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1            7                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu2            5                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3            6                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu4           11                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu5           10                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu6            3                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu7            4                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           59                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0                  19                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1                  11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2                  10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3                  11                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4                  13                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5                  14                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6                   7                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7                  12                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 97                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0                 19                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1                 11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2                 10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3                 11                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4                 13                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5                 14                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6                  7                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7                 12                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                97                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         1226                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         1226                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0          2028                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1          2036                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2          2114                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3          2013                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4          2071                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5          1987                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6          2026                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7          2018                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        16293                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0           4668                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1           4588                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2           4650                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3           4536                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4           4555                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5           4635                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6           4720                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7           4594                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         36946                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0          702                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1          728                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2          733                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3          725                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu4          715                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu5          705                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu6          668                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu7          745                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total         5721                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0              5370                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1              5316                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2              5383                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3              5261                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4              5270                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5              5340                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6              5388                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7              5339                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            42667                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0             5370                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1             5316                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2             5383                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3             5261                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4             5270                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5             5340                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6             5388                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7             5339                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           42667                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0         9705                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1         9715                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2         9767                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3         9972                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu4         9773                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu5         9763                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu6         9852                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu7         9762                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        78309                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0         5486                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1         5400                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2         5419                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3         5526                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu4         5423                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu5         5458                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu6         5386                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu7         5538                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        43636                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0        15191                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1        15115                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2        15186                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3        15498                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu4        15196                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu5        15221                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu6        15238                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu7        15300                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       121945                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0     39014213                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1     39232059                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2     40780597                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3     38858267                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4     39920741                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5     38246941                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6     38960747                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7     38849596                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    313863161                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0    104350937                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1    102876549                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2    103582540                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3    102275935                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4    104240403                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5    104871121                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6    106828418                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7    103332582                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total    832358485                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0     41502671                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1     42773140                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2     43592644                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3     42525173                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu4     42051842                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu5     41416678                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu6     39402449                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu7     44058192                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total    337322789                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0    145853608                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1    145649689                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2    147175184                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3    144801108                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4    146292245                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5    146287799                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6    146230867                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7    147390774                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   1169681274                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0    145853608                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1    145649689                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2    147175184                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3    144801108                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4    146292245                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5    146287799                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6    146230867                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7    147390774                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   1169681274                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    503077334                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    503572362                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    506294012                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    516868052                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    506181413                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    506175452                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    511232158                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    505608163                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   4059008946                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    292251287                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    290147025                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    292888717                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    297220505                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    290868538                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    292450481                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    288970880                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    297704385                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2342501818                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0    795328621                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1    793719387                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2    799182729                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3    814088557                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4    797049951                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5    798625933                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6    800203038                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7    803312548                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   6401510764                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.878683                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.876830                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.877178                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.883282                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.886558                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.869204                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.872900                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.880454                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.878139                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.726085                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.708571                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.727244                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.721145                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.717549                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.720280                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.721271                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.725980                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.720996                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0     0.060727                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1     0.062949                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2     0.063005                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3     0.062554                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu4     0.062125                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu5     0.059985                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu6     0.057467                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu7     0.065743                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.061804                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0       0.298516                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1       0.294678                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2       0.298591                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3       0.294239                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4       0.295122                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5       0.293600                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6       0.296565                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7       0.302322                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.296690                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0      0.298516                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1      0.294678                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2      0.298591                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3      0.294239                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4      0.295122                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5      0.293600                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6      0.296565                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7      0.302322                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.296690                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 19237.777613                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 19269.184185                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 19290.727058                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 19303.659712                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 19276.070014                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 19248.586311                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 19230.378578                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 19251.534192                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19263.681397                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 22354.528063                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 22422.961857                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 22275.815054                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 22547.604718                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 22884.830516                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 22625.916073                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 22633.139407                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 22492.943404                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 22529.055513                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59120.613960                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 58754.313187                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59471.547067                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 58655.411034                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58813.765035                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 58747.060993                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 58985.702096                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59138.512752                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 58962.207481                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 27160.820857                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 27398.361362                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 27340.736392                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 27523.495153                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 27759.439279                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 27394.718914                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 27140.101522                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 27606.438284                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 27414.190686                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 27160.820857                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 27398.361362                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 27340.736392                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 27523.495153                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 27759.439279                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 27394.718914                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 27140.101522                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 27606.438284                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 27414.190686                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 51836.922617                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 51834.520021                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 51837.208150                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 51831.934617                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 51793.861967                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 51846.302571                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 51891.205644                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 51793.501639                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 51833.236869                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 53272.199599                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 53730.930556                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 54048.480716                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 53785.831524                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 53636.094044                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 53581.986259                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 53652.224285                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 53756.660347                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 53682.780686                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 52355.251201                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 52512.033543                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 52626.282695                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 52528.620274                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 52451.299750                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 52468.690165                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 52513.652579                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 52504.088105                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 52495.065513                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               78306                       # Transaction distribution
system.membus.trans_dist::ReadResp              84006                       # Transaction distribution
system.membus.trans_dist::WriteReq              43633                       # Transaction distribution
system.membus.trans_dist::WriteResp             43633                       # Transaction distribution
system.membus.trans_dist::WritebackDirty         6315                       # Transaction distribution
system.membus.trans_dist::CleanEvict             1254                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            60980                       # Transaction distribution
system.membus.trans_dist::ReadExReq             48711                       # Transaction distribution
system.membus.trans_dist::ReadExResp             3097                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq          5709                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       375644                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 375644                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1089674                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                 1089674                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                            56426                       # Total snoops (count)
system.membus.snoop_fanout::samples            252331                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  252331    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              252331                       # Request fanout histogram
system.membus.reqLayer0.occupancy           290210873                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization              54.7                       # Layer utilization (%)
system.membus.respLayer0.occupancy          244257000                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization             46.1                       # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests       663692                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       283641                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       333885                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops          12353                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         5692                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops         6661                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              78309                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            370176                       # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             43636                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            43632                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty        83900                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict          105566                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           29367                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          29367                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           161854                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          161852                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       291888                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       133128                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       133137                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       133276                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       133136                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       132901                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       133285                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       133385                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       132788                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1065036                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1790740                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1793737                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1783183                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1779785                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1777562                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1801715                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1799686                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1764480                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               14290888                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          334512                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples           624442                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.148246                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.987708                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 174331     27.92%     27.92% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 257461     41.23%     69.15% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 132941     21.29%     90.44% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                  47060      7.54%     97.97% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                  10899      1.75%     99.72% # Request fanout histogram
system.toL2Bus.snoop_fanout::5                   1610      0.26%     99.98% # Request fanout histogram
system.toL2Bus.snoop_fanout::6                    136      0.02%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7                      4      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8                      0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              7                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             624442                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          496537925                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization             93.7                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         101982318                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization            19.2                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         102105458                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization            19.3                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         101942894                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization            19.2                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         101777352                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization            19.2                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy         101724075                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization            19.2                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy         101820787                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization            19.2                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy         102063169                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization            19.3                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy         101980781                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization            19.2                       # Layer utilization (%)

---------- End Simulation Statistics   ----------