path: root/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000517                       # Number of seconds simulated
sim_ticks                                   516502000                       # Number of ticks simulated
final_tick                                  516502000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_tick_rate                               87177041                       # Simulator tick rate (ticks/s)
host_mem_usage                                 277532                       # Number of bytes of host memory used
host_seconds                                     5.92                       # Real time elapsed on the host
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0                 77818                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1                 80958                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2                 77616                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3                 81564                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu4                 77320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu5                 77018                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu6                 77760                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu7                 78103                       # Number of bytes read from this memory
system.physmem.bytes_read::total               628157                       # Number of bytes read from this memory
system.physmem.bytes_written::writebacks       397760                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0               5585                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1               5520                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu2               5375                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu3               5451                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu4               5416                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu5               5446                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu6               5475                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu7               5563                       # Number of bytes written to this memory
system.physmem.bytes_written::total            441591                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0                  10975                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1                  10902                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2                  10962                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3                  11130                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4                  10918                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5                  10679                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6                  10980                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7                  10819                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 87365                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks            6215                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0                  5585                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1                  5520                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2                  5375                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3                  5451                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4                  5416                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5                  5446                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6                  5475                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7                  5563                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                50046                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0                150663502                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1                156742859                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2                150272409                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3                157916136                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4                149699324                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5                149114621                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6                150551208                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7                151215291                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              1216175349                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         770103504                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0                10813124                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1                10687277                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2                10406542                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3                10553686                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4                10485923                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5                10544006                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6                10600153                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7                10770529                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              854964744                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         770103504                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0               161476625                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1               167430136                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2               160678952                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3               168469822                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4               160185246                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5               159658627                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6               161151360                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7               161985820                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             2071140092                       # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.num_reads                           99458                       # number of read accesses completed
system.cpu0.num_writes                          55230                       # number of write accesses completed
system.cpu0.l1c.tags.replacements               22190                       # number of replacements
system.cpu0.l1c.tags.tagsinuse             391.694293                       # Cycle average of tags in use
system.cpu0.l1c.tags.total_refs                 13468                       # Total number of references to valid blocks.
system.cpu0.l1c.tags.sampled_refs               22585                       # Sample count of references to valid blocks.
system.cpu0.l1c.tags.avg_refs                0.596325                       # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu0.l1c.tags.occ_blocks::cpu0      391.694293                       # Average occupied blocks per requestor
system.cpu0.l1c.tags.occ_percent::cpu0       0.765028                       # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_percent::total      0.765028                       # Average percentage of cache occupancy
system.cpu0.l1c.tags.occ_task_id_blocks::1024          395                       # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::0          386                       # Occupied blocks per task id
system.cpu0.l1c.tags.age_task_id_blocks_1024::1            9                       # Occupied blocks per task id
system.cpu0.l1c.tags.occ_task_id_percent::1024     0.771484                       # Percentage of cache occupancy per task id
system.cpu0.l1c.tags.tag_accesses              337088                       # Number of tag accesses
system.cpu0.l1c.tags.data_accesses             337088                       # Number of data accesses
system.cpu0.l1c.ReadReq_hits::cpu0               8685                       # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total              8685                       # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0              1212                       # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total             1212                       # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0                9897                       # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total               9897                       # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0               9897                       # number of overall hits
system.cpu0.l1c.overall_hits::total              9897                       # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0            36327                       # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total           36327                       # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0           23903                       # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total          23903                       # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0             60230                       # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total            60230                       # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0            60230                       # number of overall misses
system.cpu0.l1c.overall_misses::total           60230                       # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0    590238894                       # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total    590238894                       # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0    671544552                       # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total    671544552                       # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0   1261783446                       # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total   1261783446                       # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0   1261783446                       # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total   1261783446                       # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0          45012                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total         45012                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0         25115                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total        25115                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0           70127                       # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total          70127                       # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0          70127                       # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total         70127                       # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.807051                       # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total     0.807051                       # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.951742                       # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total     0.951742                       # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0       0.858870                       # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total      0.858870                       # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0      0.858870                       # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total     0.858870                       # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16247.939384                       # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 16247.939384                       # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 28094.571895                       # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 28094.571895                       # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 20949.417998                       # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 20949.417998                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 20949.417998                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 20949.417998                       # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs       738586                       # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_mshrs               60679                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_mshrs    12.172020                       # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu0.l1c.writebacks::writebacks           9780                       # number of writebacks
system.cpu0.l1c.writebacks::total                9780                       # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0        36327                       # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total        36327                       # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23903                       # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total        23903                       # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0        60230                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total        60230                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0        60230                       # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total        60230                       # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0         9914                       # number of ReadReq MSHR uncacheable
system.cpu0.l1c.ReadReq_mshr_uncacheable::total         9914                       # number of ReadReq MSHR uncacheable
system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0         5586                       # number of WriteReq MSHR uncacheable
system.cpu0.l1c.WriteReq_mshr_uncacheable::total         5586                       # number of WriteReq MSHR uncacheable
system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0        15500                       # number of overall MSHR uncacheable misses
system.cpu0.l1c.overall_mshr_uncacheable_misses::total        15500                       # number of overall MSHR uncacheable misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0    553912894                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total    553912894                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    647643552                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total    647643552                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0   1201556446                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total   1201556446                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0   1201556446                       # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total   1201556446                       # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    648458134                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    648458134                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0    875575663                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total    875575663                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   1524033797                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total   1524033797                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.807051                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.807051                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.951742                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.951742                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.858870                       # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total     0.858870                       # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.858870                       # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total     0.858870                       # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15247.966912                       # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15247.966912                       # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 27094.655566                       # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 27094.655566                       # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19949.467807                       # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19949.467807                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19949.467807                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19949.467807                       # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 65408.324995                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65408.324995                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 156744.658611                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156744.658611                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 98324.761097                       # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 98324.761097                       # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu1.num_reads                           99343                       # number of read accesses completed
system.cpu1.num_writes                          54840                       # number of write accesses completed
system.cpu1.l1c.tags.replacements               22376                       # number of replacements
system.cpu1.l1c.tags.tagsinuse             393.102021                       # Cycle average of tags in use
system.cpu1.l1c.tags.total_refs                 13319                       # Total number of references to valid blocks.
system.cpu1.l1c.tags.sampled_refs               22762                       # Sample count of references to valid blocks.
system.cpu1.l1c.tags.avg_refs                0.585142                       # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu1.l1c.tags.occ_blocks::cpu1      393.102021                       # Average occupied blocks per requestor
system.cpu1.l1c.tags.occ_percent::cpu1       0.767777                       # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_percent::total      0.767777                       # Average percentage of cache occupancy
system.cpu1.l1c.tags.occ_task_id_blocks::1024          386                       # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::0          376                       # Occupied blocks per task id
system.cpu1.l1c.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
system.cpu1.l1c.tags.occ_task_id_percent::1024     0.753906                       # Percentage of cache occupancy per task id
system.cpu1.l1c.tags.tag_accesses              337670                       # Number of tag accesses
system.cpu1.l1c.tags.data_accesses             337670                       # Number of data accesses
system.cpu1.l1c.ReadReq_hits::cpu1               8618                       # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total              8618                       # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1              1175                       # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total             1175                       # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1                9793                       # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total               9793                       # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1               9793                       # number of overall hits
system.cpu1.l1c.overall_hits::total              9793                       # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1            36716                       # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total           36716                       # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1           23707                       # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total          23707                       # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1             60423                       # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total            60423                       # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1            60423                       # number of overall misses
system.cpu1.l1c.overall_misses::total           60423                       # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1    601446212                       # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total    601446212                       # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1    664813201                       # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total    664813201                       # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1   1266259413                       # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total   1266259413                       # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1   1266259413                       # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total   1266259413                       # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1          45334                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total         45334                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1         24882                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total        24882                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1           70216                       # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total          70216                       # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1          70216                       # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total         70216                       # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.809900                       # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total     0.809900                       # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.952777                       # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total     0.952777                       # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1       0.860530                       # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total      0.860530                       # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1      0.860530                       # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total     0.860530                       # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16381.038566                       # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 16381.038566                       # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 28042.907200                       # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 28042.907200                       # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 20956.579663                       # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 20956.579663                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 20956.579663                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 20956.579663                       # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs       733404                       # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_mshrs               60457                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_mshrs    12.131002                       # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu1.l1c.writebacks::writebacks           9757                       # number of writebacks
system.cpu1.l1c.writebacks::total                9757                       # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1        36716                       # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total        36716                       # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23707                       # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total        23707                       # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1        60423                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total        60423                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1        60423                       # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total        60423                       # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1         9790                       # number of ReadReq MSHR uncacheable
system.cpu1.l1c.ReadReq_mshr_uncacheable::total         9790                       # number of ReadReq MSHR uncacheable
system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1         5520                       # number of WriteReq MSHR uncacheable
system.cpu1.l1c.WriteReq_mshr_uncacheable::total         5520                       # number of WriteReq MSHR uncacheable
system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1        15310                       # number of overall MSHR uncacheable misses
system.cpu1.l1c.overall_mshr_uncacheable_misses::total        15310                       # number of overall MSHR uncacheable misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1    564731212                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total    564731212                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    641108201                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total    641108201                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1   1205839413                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total   1205839413                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1   1205839413                       # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total   1205839413                       # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    639869720                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    639869720                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1    879270140                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total    879270140                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   1519139860                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total   1519139860                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.809900                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.809900                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.952777                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.952777                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.860530                       # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total     0.860530                       # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.860530                       # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total     0.860530                       # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15381.065802                       # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15381.065802                       # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 27042.991564                       # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 27042.991564                       # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19956.629313                       # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19956.629313                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19956.629313                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19956.629313                       # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 65359.521961                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65359.521961                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 159288.068841                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159288.068841                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 99225.333769                       # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 99225.333769                       # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu2.num_reads                           99555                       # number of read accesses completed
system.cpu2.num_writes                          54722                       # number of write accesses completed
system.cpu2.l1c.tags.replacements               22333                       # number of replacements
system.cpu2.l1c.tags.tagsinuse             393.011664                       # Cycle average of tags in use
system.cpu2.l1c.tags.total_refs                 13583                       # Total number of references to valid blocks.
system.cpu2.l1c.tags.sampled_refs               22742                       # Sample count of references to valid blocks.
system.cpu2.l1c.tags.avg_refs                0.597265                       # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu2.l1c.tags.occ_blocks::cpu2      393.011664                       # Average occupied blocks per requestor
system.cpu2.l1c.tags.occ_percent::cpu2       0.767601                       # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_percent::total      0.767601                       # Average percentage of cache occupancy
system.cpu2.l1c.tags.occ_task_id_blocks::1024          409                       # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::0          397                       # Occupied blocks per task id
system.cpu2.l1c.tags.age_task_id_blocks_1024::1           12                       # Occupied blocks per task id
system.cpu2.l1c.tags.occ_task_id_percent::1024     0.798828                       # Percentage of cache occupancy per task id
system.cpu2.l1c.tags.tag_accesses              337922                       # Number of tag accesses
system.cpu2.l1c.tags.data_accesses             337922                       # Number of data accesses
system.cpu2.l1c.ReadReq_hits::cpu2               8790                       # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total              8790                       # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2              1177                       # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total             1177                       # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2                9967                       # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total               9967                       # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2               9967                       # number of overall hits
system.cpu2.l1c.overall_hits::total              9967                       # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2            36445                       # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total           36445                       # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2           23901                       # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total          23901                       # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2             60346                       # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total            60346                       # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2            60346                       # number of overall misses
system.cpu2.l1c.overall_misses::total           60346                       # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2    601110816                       # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total    601110816                       # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2    668105531                       # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total    668105531                       # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2   1269216347                       # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total   1269216347                       # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2   1269216347                       # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total   1269216347                       # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2          45235                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total         45235                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2         25078                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total        25078                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2           70313                       # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total          70313                       # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2          70313                       # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total         70313                       # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.805681                       # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total     0.805681                       # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.953066                       # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total     0.953066                       # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2       0.858248                       # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total      0.858248                       # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2      0.858248                       # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total     0.858248                       # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16493.642914                       # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 16493.642914                       # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27953.036735                       # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 27953.036735                       # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 21032.319408                       # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 21032.319408                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 21032.319408                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 21032.319408                       # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs       742378                       # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_mshrs               60996                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_mshrs    12.170929                       # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu2.l1c.writebacks::writebacks           9726                       # number of writebacks
system.cpu2.l1c.writebacks::total                9726                       # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2        36445                       # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total        36445                       # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2        23901                       # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total        23901                       # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2        60346                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total        60346                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2        60346                       # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total        60346                       # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2         9904                       # number of ReadReq MSHR uncacheable
system.cpu2.l1c.ReadReq_mshr_uncacheable::total         9904                       # number of ReadReq MSHR uncacheable
system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2         5377                       # number of WriteReq MSHR uncacheable
system.cpu2.l1c.WriteReq_mshr_uncacheable::total         5377                       # number of WriteReq MSHR uncacheable
system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2        15281                       # number of overall MSHR uncacheable misses
system.cpu2.l1c.overall_mshr_uncacheable_misses::total        15281                       # number of overall MSHR uncacheable misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2    564666816                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total    564666816                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    644204531                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total    644204531                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2   1208871347                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total   1208871347                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2   1208871347                       # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total   1208871347                       # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    647672238                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    647672238                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2    840893759                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total    840893759                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   1488565997                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total   1488565997                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.805681                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.805681                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.953066                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.953066                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.858248                       # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total     0.858248                       # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.858248                       # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total     0.858248                       # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15493.670353                       # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15493.670353                       # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 26953.036735                       # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 26953.036735                       # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20032.335979                       # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20032.335979                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20032.335979                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20032.335979                       # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 65395.015953                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65395.015953                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 156387.159940                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156387.159940                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 97412.865454                       # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 97412.865454                       # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu3.num_reads                           99759                       # number of read accesses completed
system.cpu3.num_writes                          54933                       # number of write accesses completed
system.cpu3.l1c.tags.replacements               22211                       # number of replacements
system.cpu3.l1c.tags.tagsinuse             391.604025                       # Cycle average of tags in use
system.cpu3.l1c.tags.total_refs                 13361                       # Total number of references to valid blocks.
system.cpu3.l1c.tags.sampled_refs               22604                       # Sample count of references to valid blocks.
system.cpu3.l1c.tags.avg_refs                0.591090                       # Average number of references to valid blocks.
system.cpu3.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu3.l1c.tags.occ_blocks::cpu3      391.604025                       # Average occupied blocks per requestor
system.cpu3.l1c.tags.occ_percent::cpu3       0.764852                       # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_percent::total      0.764852                       # Average percentage of cache occupancy
system.cpu3.l1c.tags.occ_task_id_blocks::1024          393                       # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::0          381                       # Occupied blocks per task id
system.cpu3.l1c.tags.age_task_id_blocks_1024::1           12                       # Occupied blocks per task id
system.cpu3.l1c.tags.occ_task_id_percent::1024     0.767578                       # Percentage of cache occupancy per task id
system.cpu3.l1c.tags.tag_accesses              336889                       # Number of tag accesses
system.cpu3.l1c.tags.data_accesses             336889                       # Number of data accesses
system.cpu3.l1c.ReadReq_hits::cpu3               8685                       # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total              8685                       # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3              1067                       # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total             1067                       # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3                9752                       # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total               9752                       # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3               9752                       # number of overall hits
system.cpu3.l1c.overall_hits::total              9752                       # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3            36549                       # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total           36549                       # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3           23764                       # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total          23764                       # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3             60313                       # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total            60313                       # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3            60313                       # number of overall misses
system.cpu3.l1c.overall_misses::total           60313                       # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3    596458593                       # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total    596458593                       # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3    667670467                       # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total    667670467                       # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3   1264129060                       # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total   1264129060                       # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3   1264129060                       # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total   1264129060                       # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3          45234                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total         45234                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3         24831                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total        24831                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3           70065                       # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total          70065                       # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3          70065                       # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total         70065                       # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.807998                       # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total     0.807998                       # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.957030                       # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total     0.957030                       # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3       0.860815                       # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total      0.860815                       # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3      0.860815                       # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total     0.860815                       # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16319.423049                       # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 16319.423049                       # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 28095.878935                       # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 28095.878935                       # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 20959.479051                       # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 20959.479051                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 20959.479051                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 20959.479051                       # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs       744732                       # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_mshrs               61238                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_mshrs    12.161272                       # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu3.l1c.writebacks::writebacks           9780                       # number of writebacks
system.cpu3.l1c.writebacks::total                9780                       # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3        36549                       # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total        36549                       # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23764                       # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total        23764                       # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3        60313                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total        60313                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3        60313                       # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total        60313                       # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3        10012                       # number of ReadReq MSHR uncacheable
system.cpu3.l1c.ReadReq_mshr_uncacheable::total        10012                       # number of ReadReq MSHR uncacheable
system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3         5455                       # number of WriteReq MSHR uncacheable
system.cpu3.l1c.WriteReq_mshr_uncacheable::total         5455                       # number of WriteReq MSHR uncacheable
system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3        15467                       # number of overall MSHR uncacheable misses
system.cpu3.l1c.overall_mshr_uncacheable_misses::total        15467                       # number of overall MSHR uncacheable misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3    559909593                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total    559909593                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    643907467                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total    643907467                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3   1203817060                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total   1203817060                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3   1203817060                       # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total   1203817060                       # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    654349566                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    654349566                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3    848349724                       # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total    848349724                       # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   1502699290                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total   1502699290                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.807998                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.807998                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.957030                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.957030                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.860815                       # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total     0.860815                       # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.860815                       # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total     0.860815                       # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15319.423049                       # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15319.423049                       # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 27095.921015                       # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 27095.921015                       # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19959.495631                       # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19959.495631                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19959.495631                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19959.495631                       # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 65356.528765                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65356.528765                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 155517.822915                       # average WriteReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155517.822915                       # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 97155.187819                       # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 97155.187819                       # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu4.num_reads                          100000                       # number of read accesses completed
system.cpu4.num_writes                          55127                       # number of write accesses completed
system.cpu4.l1c.tags.replacements               22421                       # number of replacements
system.cpu4.l1c.tags.tagsinuse             392.948683                       # Cycle average of tags in use
system.cpu4.l1c.tags.total_refs                 13931                       # Total number of references to valid blocks.
system.cpu4.l1c.tags.sampled_refs               22818                       # Sample count of references to valid blocks.
system.cpu4.l1c.tags.avg_refs                0.610527                       # Average number of references to valid blocks.
system.cpu4.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu4.l1c.tags.occ_blocks::cpu4      392.948683                       # Average occupied blocks per requestor
system.cpu4.l1c.tags.occ_percent::cpu4       0.767478                       # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_percent::total      0.767478                       # Average percentage of cache occupancy
system.cpu4.l1c.tags.occ_task_id_blocks::1024          397                       # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::0          386                       # Occupied blocks per task id
system.cpu4.l1c.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
system.cpu4.l1c.tags.occ_task_id_percent::1024     0.775391                       # Percentage of cache occupancy per task id
system.cpu4.l1c.tags.tag_accesses              339409                       # Number of tag accesses
system.cpu4.l1c.tags.data_accesses             339409                       # Number of data accesses
system.cpu4.l1c.ReadReq_hits::cpu4               9015                       # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total              9015                       # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4              1217                       # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total             1217                       # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4               10232                       # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total              10232                       # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4              10232                       # number of overall hits
system.cpu4.l1c.overall_hits::total             10232                       # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4            36534                       # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total           36534                       # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4           23911                       # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total          23911                       # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4             60445                       # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total            60445                       # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4            60445                       # number of overall misses
system.cpu4.l1c.overall_misses::total           60445                       # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4    594216920                       # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total    594216920                       # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4    670376038                       # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total    670376038                       # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4   1264592958                       # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total   1264592958                       # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4   1264592958                       # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total   1264592958                       # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4          45549                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total         45549                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4         25128                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total        25128                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4           70677                       # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total          70677                       # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4          70677                       # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total         70677                       # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.802081                       # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total     0.802081                       # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.951568                       # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total     0.951568                       # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4       0.855229                       # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total      0.855229                       # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4      0.855229                       # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total     0.855229                       # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16264.764877                       # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 16264.764877                       # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 28036.302873                       # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 28036.302873                       # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 20921.382381                       # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 20921.382381                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 20921.382381                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 20921.382381                       # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs       737141                       # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_mshrs               60832                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_mshrs    12.117652                       # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu4.l1c.writebacks::writebacks           9985                       # number of writebacks
system.cpu4.l1c.writebacks::total                9985                       # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4        36534                       # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total        36534                       # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4        23911                       # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total        23911                       # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4        60445                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total        60445                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4        60445                       # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total        60445                       # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4         9865                       # number of ReadReq MSHR uncacheable
system.cpu4.l1c.ReadReq_mshr_uncacheable::total         9865                       # number of ReadReq MSHR uncacheable
system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4         5418                       # number of WriteReq MSHR uncacheable
system.cpu4.l1c.WriteReq_mshr_uncacheable::total         5418                       # number of WriteReq MSHR uncacheable
system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4        15283                       # number of overall MSHR uncacheable misses
system.cpu4.l1c.overall_mshr_uncacheable_misses::total        15283                       # number of overall MSHR uncacheable misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4    557683920                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total    557683920                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    646466038                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total    646466038                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4   1204149958                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total   1204149958                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4   1204149958                       # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total   1204149958                       # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    645821695                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    645821695                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4    857369844                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total    857369844                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   1503191539                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total   1503191539                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.802081                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.802081                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.951568                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.951568                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.855229                       # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total     0.855229                       # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.855229                       # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total     0.855229                       # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15264.792248                       # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15264.792248                       # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 27036.344695                       # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 27036.344695                       # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19921.415469                       # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19921.415469                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19921.415469                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19921.415469                       # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65465.959959                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65465.959959                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 158244.710963                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 158244.710963                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 98357.098672                       # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 98357.098672                       # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu5.num_reads                           99788                       # number of read accesses completed
system.cpu5.num_writes                          55138                       # number of write accesses completed
system.cpu5.l1c.tags.replacements               22475                       # number of replacements
system.cpu5.l1c.tags.tagsinuse             392.735284                       # Cycle average of tags in use
system.cpu5.l1c.tags.total_refs                 13651                       # Total number of references to valid blocks.
system.cpu5.l1c.tags.sampled_refs               22873                       # Sample count of references to valid blocks.
system.cpu5.l1c.tags.avg_refs                0.596817                       # Average number of references to valid blocks.
system.cpu5.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu5.l1c.tags.occ_blocks::cpu5      392.735284                       # Average occupied blocks per requestor
system.cpu5.l1c.tags.occ_percent::cpu5       0.767061                       # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_percent::total      0.767061                       # Average percentage of cache occupancy
system.cpu5.l1c.tags.occ_task_id_blocks::1024          398                       # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::0          388                       # Occupied blocks per task id
system.cpu5.l1c.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
system.cpu5.l1c.tags.occ_task_id_percent::1024     0.777344                       # Percentage of cache occupancy per task id
system.cpu5.l1c.tags.tag_accesses              340255                       # Number of tag accesses
system.cpu5.l1c.tags.data_accesses             340255                       # Number of data accesses
system.cpu5.l1c.ReadReq_hits::cpu5               8878                       # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total              8878                       # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5              1131                       # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total             1131                       # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5               10009                       # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total              10009                       # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5              10009                       # number of overall hits
system.cpu5.l1c.overall_hits::total             10009                       # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5            36858                       # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total           36858                       # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5           23929                       # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total          23929                       # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5             60787                       # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total            60787                       # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5            60787                       # number of overall misses
system.cpu5.l1c.overall_misses::total           60787                       # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5    604018831                       # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total    604018831                       # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5    667551562                       # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total    667551562                       # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5   1271570393                       # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total   1271570393                       # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5   1271570393                       # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total   1271570393                       # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5          45736                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total         45736                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5         25060                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total        25060                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5           70796                       # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total          70796                       # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5          70796                       # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total         70796                       # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.805886                       # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total     0.805886                       # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.954868                       # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total     0.954868                       # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5       0.858622                       # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total      0.858622                       # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5      0.858622                       # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total     0.858622                       # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16387.726708                       # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 16387.726708                       # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27897.177567                       # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 27897.177567                       # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 20918.459424                       # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 20918.459424                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 20918.459424                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 20918.459424                       # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs       731203                       # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_mshrs               60676                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_mshrs    12.050943                       # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu5.l1c.writebacks::writebacks           9872                       # number of writebacks
system.cpu5.l1c.writebacks::total                9872                       # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5        36858                       # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total        36858                       # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23929                       # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total        23929                       # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5        60787                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total        60787                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5        60787                       # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total        60787                       # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5         9627                       # number of ReadReq MSHR uncacheable
system.cpu5.l1c.ReadReq_mshr_uncacheable::total         9627                       # number of ReadReq MSHR uncacheable
system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5         5446                       # number of WriteReq MSHR uncacheable
system.cpu5.l1c.WriteReq_mshr_uncacheable::total         5446                       # number of WriteReq MSHR uncacheable
system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5        15073                       # number of overall MSHR uncacheable misses
system.cpu5.l1c.overall_mshr_uncacheable_misses::total        15073                       # number of overall MSHR uncacheable misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5    567160831                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total    567160831                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    643622562                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total    643622562                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5   1210783393                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total   1210783393                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5   1210783393                       # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total   1210783393                       # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    632098852                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    632098852                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5    869172204                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total    869172204                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   1501271056                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total   1501271056                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.805886                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.805886                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.954868                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.954868                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.858622                       # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total     0.858622                       # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.858622                       # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total     0.858622                       # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15387.726708                       # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15387.726708                       # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 26897.177567                       # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 26897.177567                       # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19918.459424                       # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19918.459424                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19918.459424                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19918.459424                       # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 65658.964579                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65658.964579                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 159598.274697                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159598.274697                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 99600.016984                       # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 99600.016984                       # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu6.num_reads                           99577                       # number of read accesses completed
system.cpu6.num_writes                          55267                       # number of write accesses completed
system.cpu6.l1c.tags.replacements               22184                       # number of replacements
system.cpu6.l1c.tags.tagsinuse             392.209079                       # Cycle average of tags in use
system.cpu6.l1c.tags.total_refs                 13575                       # Total number of references to valid blocks.
system.cpu6.l1c.tags.sampled_refs               22573                       # Sample count of references to valid blocks.
system.cpu6.l1c.tags.avg_refs                0.601382                       # Average number of references to valid blocks.
system.cpu6.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu6.l1c.tags.occ_blocks::cpu6      392.209079                       # Average occupied blocks per requestor
system.cpu6.l1c.tags.occ_percent::cpu6       0.766033                       # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_percent::total      0.766033                       # Average percentage of cache occupancy
system.cpu6.l1c.tags.occ_task_id_blocks::1024          389                       # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::0          375                       # Occupied blocks per task id
system.cpu6.l1c.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
system.cpu6.l1c.tags.occ_task_id_percent::1024     0.759766                       # Percentage of cache occupancy per task id
system.cpu6.l1c.tags.tag_accesses              337224                       # Number of tag accesses
system.cpu6.l1c.tags.data_accesses             337224                       # Number of data accesses
system.cpu6.l1c.ReadReq_hits::cpu6               8787                       # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total              8787                       # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6              1092                       # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total             1092                       # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6                9879                       # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total               9879                       # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6               9879                       # number of overall hits
system.cpu6.l1c.overall_hits::total              9879                       # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6            36436                       # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total           36436                       # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6           23858                       # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total          23858                       # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6             60294                       # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total            60294                       # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6            60294                       # number of overall misses
system.cpu6.l1c.overall_misses::total           60294                       # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6    592887114                       # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total    592887114                       # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6    676055850                       # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total    676055850                       # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6   1268942964                       # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total   1268942964                       # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6   1268942964                       # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total   1268942964                       # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6          45223                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total         45223                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6         24950                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total        24950                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6           70173                       # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total          70173                       # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6          70173                       # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total         70173                       # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.805696                       # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total     0.805696                       # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.956232                       # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total     0.956232                       # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6       0.859219                       # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total      0.859219                       # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6      0.859219                       # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total     0.859219                       # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16272.014326                       # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 16272.014326                       # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28336.652276                       # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 28336.652276                       # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 21045.924371                       # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 21045.924371                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 21045.924371                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 21045.924371                       # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs       742965                       # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_mshrs               61020                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_mshrs    12.175762                       # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu6.l1c.writebacks::writebacks           9883                       # number of writebacks
system.cpu6.l1c.writebacks::total                9883                       # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6        36436                       # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total        36436                       # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23858                       # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total        23858                       # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6        60294                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total        60294                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6        60294                       # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total        60294                       # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6         9920                       # number of ReadReq MSHR uncacheable
system.cpu6.l1c.ReadReq_mshr_uncacheable::total         9920                       # number of ReadReq MSHR uncacheable
system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6         5475                       # number of WriteReq MSHR uncacheable
system.cpu6.l1c.WriteReq_mshr_uncacheable::total         5475                       # number of WriteReq MSHR uncacheable
system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6        15395                       # number of overall MSHR uncacheable misses
system.cpu6.l1c.overall_mshr_uncacheable_misses::total        15395                       # number of overall MSHR uncacheable misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6    556451114                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total    556451114                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    652198850                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total    652198850                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6   1208649964                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total   1208649964                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6   1208649964                       # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total   1208649964                       # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    646733639                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    646733639                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6    847369233                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total    847369233                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   1494102872                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total   1494102872                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.805696                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.805696                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.956232                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.956232                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.859219                       # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total     0.859219                       # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.859219                       # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total     0.859219                       # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15272.014326                       # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15272.014326                       # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 27336.694191                       # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 27336.694191                       # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20045.940956                       # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20045.940956                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20045.940956                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20045.940956                       # average overall mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 65194.923286                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65194.923286                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 154770.636164                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154770.636164                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 97051.177135                       # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 97051.177135                       # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu7.num_reads                           99427                       # number of read accesses completed
system.cpu7.num_writes                          55134                       # number of write accesses completed
system.cpu7.l1c.tags.replacements               22242                       # number of replacements
system.cpu7.l1c.tags.tagsinuse             391.816785                       # Cycle average of tags in use
system.cpu7.l1c.tags.total_refs                 13453                       # Total number of references to valid blocks.
system.cpu7.l1c.tags.sampled_refs               22633                       # Sample count of references to valid blocks.
system.cpu7.l1c.tags.avg_refs                0.594398                       # Average number of references to valid blocks.
system.cpu7.l1c.tags.warmup_cycle                   0                       # Cycle when the warmup percentage was hit.
system.cpu7.l1c.tags.occ_blocks::cpu7      391.816785                       # Average occupied blocks per requestor
system.cpu7.l1c.tags.occ_percent::cpu7       0.765267                       # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_percent::total      0.765267                       # Average percentage of cache occupancy
system.cpu7.l1c.tags.occ_task_id_blocks::1024          391                       # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::0          382                       # Occupied blocks per task id
system.cpu7.l1c.tags.age_task_id_blocks_1024::1            9                       # Occupied blocks per task id
system.cpu7.l1c.tags.occ_task_id_percent::1024     0.763672                       # Percentage of cache occupancy per task id
system.cpu7.l1c.tags.tag_accesses              338054                       # Number of tag accesses
system.cpu7.l1c.tags.data_accesses             338054                       # Number of data accesses
system.cpu7.l1c.ReadReq_hits::cpu7               8636                       # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total              8636                       # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7              1148                       # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total             1148                       # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7                9784                       # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total               9784                       # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7               9784                       # number of overall hits
system.cpu7.l1c.overall_hits::total              9784                       # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7            36700                       # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total           36700                       # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7           23832                       # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total          23832                       # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7             60532                       # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total            60532                       # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7            60532                       # number of overall misses
system.cpu7.l1c.overall_misses::total           60532                       # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7    601580634                       # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total    601580634                       # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7    672036114                       # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total    672036114                       # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7   1273616748                       # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total   1273616748                       # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7   1273616748                       # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total   1273616748                       # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7          45336                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total         45336                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7         24980                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total        24980                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7           70316                       # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total          70316                       # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7          70316                       # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total         70316                       # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.809511                       # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total     0.809511                       # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.954043                       # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total     0.954043                       # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7       0.860857                       # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total      0.860857                       # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7      0.860857                       # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total     0.860857                       # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16391.842888                       # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 16391.842888                       # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 28198.897029                       # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 28198.897029                       # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 21040.387696                       # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 21040.387696                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 21040.387696                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 21040.387696                       # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs       739183                       # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_mshrs               60836                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_mshrs    12.150421                       # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu7.l1c.writebacks::writebacks           9689                       # number of writebacks
system.cpu7.l1c.writebacks::total                9689                       # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7        36700                       # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total        36700                       # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23832                       # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total        23832                       # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7        60532                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total        60532                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7        60532                       # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total        60532                       # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7         9751                       # number of ReadReq MSHR uncacheable
system.cpu7.l1c.ReadReq_mshr_uncacheable::total         9751                       # number of ReadReq MSHR uncacheable
system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7         5566                       # number of WriteReq MSHR uncacheable
system.cpu7.l1c.WriteReq_mshr_uncacheable::total         5566                       # number of WriteReq MSHR uncacheable
system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7        15317                       # number of overall MSHR uncacheable misses
system.cpu7.l1c.overall_mshr_uncacheable_misses::total        15317                       # number of overall MSHR uncacheable misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7    564880634                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total    564880634                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    648206114                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total    648206114                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7   1213086748                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total   1213086748                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7   1213086748                       # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total   1213086748                       # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    637373819                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    637373819                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7    878019147                       # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total    878019147                       # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   1515392966                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total   1515392966                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.809511                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.809511                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.954043                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.954043                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.860857                       # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total     0.860857                       # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.860857                       # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total     0.860857                       # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15391.842888                       # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15391.842888                       # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 27198.980950                       # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 27198.980950                       # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20040.420736                       # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20040.420736                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20040.420736                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20040.420736                       # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 65364.969644                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65364.969644                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 157746.882321                       # average WriteReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157746.882321                       # average WriteReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 98935.363714                       # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 98935.363714                       # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                    13635                       # number of replacements
system.l2c.tags.tagsinuse                  787.795797                       # Cycle average of tags in use
system.l2c.tags.total_refs                     163881                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                    14421                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    11.364052                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks     732.377461                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0             6.931961                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1             6.975655                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2             6.944636                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3             7.398268                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu4             6.695089                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu5             6.188919                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu6             7.047720                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu7             7.236089                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.715212                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0            0.006769                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1            0.006812                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2            0.006782                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3            0.007225                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu4            0.006538                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu5            0.006044                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu6            0.006883                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu7            0.007066                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.769332                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024          786                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0          654                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          132                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024     0.767578                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  2092959                       # Number of tag accesses
system.l2c.tags.data_accesses                 2092959                       # Number of data accesses
system.l2c.Writeback_hits::writebacks           77190                       # number of Writeback hits
system.l2c.Writeback_hits::total                77190                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0                  242                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1                  278                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2                  290                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3                  299                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4                  286                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5                  279                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6                  254                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7                  287                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                2215                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0                  1757                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1                  1745                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2                  1812                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3                  1725                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4                  1792                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5                  1760                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6                  1718                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7                  1773                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                14082                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0             10725                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1             10956                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2             10775                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3             10922                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu4             10805                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu5             10917                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu6             10735                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu7             10921                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total            86756                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0                    12482                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1                    12701                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2                    12587                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3                    12647                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu4                    12597                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu5                    12677                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu6                    12453                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu7                    12694                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  100838                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0                   12482                       # number of overall hits
system.l2c.overall_hits::cpu1                   12701                       # number of overall hits
system.l2c.overall_hits::cpu2                   12587                       # number of overall hits
system.l2c.overall_hits::cpu3                   12647                       # number of overall hits
system.l2c.overall_hits::cpu4                   12597                       # number of overall hits
system.l2c.overall_hits::cpu5                   12677                       # number of overall hits
system.l2c.overall_hits::cpu6                   12453                       # number of overall hits
system.l2c.overall_hits::cpu7                   12694                       # number of overall hits
system.l2c.overall_hits::total                 100838                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0               2065                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1               2004                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2               2022                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3               2044                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4               2054                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5               2029                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6               2097                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7               2076                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             16391                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0                4632                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1                4551                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2                4580                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3                4616                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4                4586                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5                4561                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6                4720                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7                4602                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              36848                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0             688                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1             704                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2             710                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3             732                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu4             671                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu5             651                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu6             677                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu7             715                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total           5548                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0                   5320                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1                   5255                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2                   5290                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3                   5348                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu4                   5257                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu5                   5212                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu6                   5397                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu7                   5317                       # number of demand (read+write) misses
system.l2c.demand_misses::total                 42396                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0                  5320                       # number of overall misses
system.l2c.overall_misses::cpu1                  5255                       # number of overall misses
system.l2c.overall_misses::cpu2                  5290                       # number of overall misses
system.l2c.overall_misses::cpu3                  5348                       # number of overall misses
system.l2c.overall_misses::cpu4                  5257                       # number of overall misses
system.l2c.overall_misses::cpu5                  5212                       # number of overall misses
system.l2c.overall_misses::cpu6                  5397                       # number of overall misses
system.l2c.overall_misses::cpu7                  5317                       # number of overall misses
system.l2c.overall_misses::total                42396                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0     61352981                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1     61176995                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2     58729489                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3     63986497                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4     59053489                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5     58462992                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6     64338488                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7     61927494                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    489028425                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0     253959415                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1     249536911                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2     250480927                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3     252977424                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4     251220434                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5     249579925                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6     257995414                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7     252050416                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2017800866                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0     42779912                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1     43250421                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2     44195907                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3     44710425                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu4     41223921                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu5     40317415                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu6     42323414                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu7     44497906                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total    343299321                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0        296739327                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1        292787332                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2        294676834                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3        297687849                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4        292444355                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5        289897340                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6        300318828                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7        296548322                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      2361100187                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0       296739327                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1       292787332                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2       294676834                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3       297687849                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4       292444355                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5       289897340                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6       300318828                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7       296548322                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     2361100187                       # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks        77190                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total            77190                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0             2307                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1             2282                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2             2312                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3             2343                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4             2340                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5             2308                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6             2351                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7             2363                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           18606                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0              6389                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1              6296                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2              6392                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3              6341                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4              6378                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5              6321                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6              6438                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7              6375                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            50930                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0         11413                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1         11660                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2         11485                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3         11654                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu4         11476                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu5         11568                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu6         11412                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu7         11636                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total        92304                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0                17802                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1                17956                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2                17877                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3                17995                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4                17854                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5                17889                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6                17850                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7                18011                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              143234                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0               17802                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1               17956                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2               17877                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3               17995                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4               17854                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5               17889                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6               17850                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7               18011                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             143234                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0        0.895102                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1        0.878177                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2        0.874567                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3        0.872386                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4        0.877778                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5        0.879116                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6        0.891961                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7        0.878544                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.880952                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0         0.724996                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1         0.722840                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2         0.716521                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3         0.727961                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4         0.719034                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5         0.721563                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6         0.733147                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7         0.721882                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.723503                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0     0.060282                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1     0.060377                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2     0.061820                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3     0.062811                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu4     0.058470                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu5     0.056276                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu6     0.059324                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu7     0.061447                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.060106                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0            0.298843                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1            0.292660                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2            0.295911                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3            0.297194                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4            0.294444                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5            0.291352                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6            0.302353                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7            0.295208                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.295991                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0           0.298843                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1           0.292660                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2           0.295911                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3           0.297194                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4           0.294444                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5           0.291352                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6           0.302353                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7           0.295208                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.295991                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0 29710.886683                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 30527.442615                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 29045.246785                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 31304.548434                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 28750.481500                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 28813.697388                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 30681.205532                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 29830.199422                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 29835.179367                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 54827.162133                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 54831.226324                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 54690.158734                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 54804.467938                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 54779.859137                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 54720.439597                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 54660.045339                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 54769.755758                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 54760.119030                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0 62180.104651                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1 61435.257102                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2 62247.756338                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3 61079.815574                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu4 61436.543964                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu5 61931.513057                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu6 62516.121123                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu7 62234.833566                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 61878.031903                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 55778.068985                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 55715.952807                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 55704.505482                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 55663.397345                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 55629.513981                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 55621.132003                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 55645.511951                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 55773.617077                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 55691.579088                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 55778.068985                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 55715.952807                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 55704.505482                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 55663.397345                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 55629.513981                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 55621.132003                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 55645.511951                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 55773.617077                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 55691.579088                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs             18273                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                     3257                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs      5.610378                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks                6215                       # number of writebacks
system.l2c.writebacks::total                     6215                       # number of writebacks
system.l2c.UpgradeReq_mshr_hits::cpu0               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu4               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu5               1                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::total              3                       # number of UpgradeReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu0                5                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu1                3                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu2                3                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu3                1                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu4                7                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5                5                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu6                5                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu7                3                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total              32                       # number of ReadExReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0            5                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1            7                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu2            5                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3            9                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu4           10                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu5            7                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu6            5                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu7            7                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           55                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0                  10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1                  10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2                   8                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3                  10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4                  17                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5                  12                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6                  10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7                  10                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 87                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0                 10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1                 10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2                  8                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3                 10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4                 17                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5                 12                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6                 10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7                 10                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                87                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks         1195                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total         1195                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0          2064                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1          2004                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2          2022                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3          2044                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4          2053                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5          2028                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6          2097                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7          2076                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        16388                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0           4627                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1           4548                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2           4577                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3           4615                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4           4579                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5           4556                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6           4715                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7           4599                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         36816                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0          683                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1          697                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2          705                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3          723                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu4          661                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu5          644                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu6          672                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu7          708                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total         5493                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0              5310                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1              5245                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2              5282                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3              5338                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4              5240                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5              5200                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6              5387                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7              5307                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            42309                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0             5310                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1             5245                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2             5282                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3             5338                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4             5240                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5             5200                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6             5387                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7             5307                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           42309                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0         9914                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1         9790                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2         9904                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3        10012                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu4         9864                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu5         9627                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu6         9920                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu7         9751                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        78782                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0         5585                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1         5520                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2         5375                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3         5452                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu4         5416                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu5         5446                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu6         5475                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu7         5563                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        43832                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0        15499                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1        15310                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2        15279                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3        15464                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu4        15280                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu5        15073                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu6        15395                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu7        15314                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total       122614                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0     91133472                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1     88462987                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2     89280980                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3     90268986                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4     90591474                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5     89517985                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6     92579479                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7     91580988                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    723416351                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0    207502416                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1    203985411                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2    204607928                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3    206817424                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4    205245434                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5    203808925                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6    210680914                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7    205992916                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1648641368                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0     35739912                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1     36064422                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2     36944907                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3     37169425                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu4     34229921                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu5     33582416                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu6     35467415                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu7     37159907                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total    286358325                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0    243242328                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1    240049833                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2    241552835                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3    243986849                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4    239475355                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5    237391341                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6    246148329                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7    243152823                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   1934999693                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0    243242328                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1    240049833                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2    241552835                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3    243986849                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4    239475355                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5    237391341                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6    246148329                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7    243152823                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   1934999693                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    440524373                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    434529373                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    439498845                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    444350349                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    438452875                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    427687869                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    440147866                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    432536724                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   3497728274                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    254487945                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    251283938                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    245260938                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    249610444                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    246551945                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    247817429                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    250267435                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    254241933                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1999522007                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0    695012318                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1    685813311                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2    684759783                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3    693960793                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4    685004820                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5    675505298                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6    690415301                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7    686778657                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   5497250281                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.894668                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.878177                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.874567                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.872386                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.877350                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.878683                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.891961                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.878544                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.880791                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.724213                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.722363                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.716051                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.727803                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.717937                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.720772                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.732370                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.721412                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.722875                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0     0.059844                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1     0.059777                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2     0.061384                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3     0.062039                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu4     0.057598                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu5     0.055671                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu6     0.058885                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu7     0.060846                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.059510                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0       0.298281                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1       0.292103                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2       0.295463                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3       0.296638                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4       0.293492                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5       0.290681                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6       0.301793                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7       0.294653                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.295384                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0      0.298281                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1      0.292103                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2      0.295463                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3      0.296638                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4      0.293492                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5      0.290681                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6      0.301793                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7      0.294653                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.295384                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 44153.813953                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 44143.207086                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 44154.787339                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 44162.909002                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 44126.387725                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 44141.018245                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 44148.535527                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 44114.156069                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44143.052905                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 44845.994381                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 44851.673483                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44703.501857                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44814.176381                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44823.200262                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44734.180202                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44683.120679                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44790.805827                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 44780.567362                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 52327.836018                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 51742.355811                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 52404.123404                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 51409.993084                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 51785.054463                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 52146.608696                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 52778.891369                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 52485.744350                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 52131.499181                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 45808.348023                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 45767.365682                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 45731.320523                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 45707.540090                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 45701.403626                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 45652.180962                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 45693.025617                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 45817.377614                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 45734.942754                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 45808.348023                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 45767.365682                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 45731.320523                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 45707.540090                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 45701.403626                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 45652.180962                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 45693.025617                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 45817.377614                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 45734.942754                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44434.574642                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44385.022778                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44375.893074                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44381.776768                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44449.804846                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44425.871923                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44369.744556                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44358.191365                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44397.556218                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45566.328559                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 45522.452536                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45629.941953                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45783.280264                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45522.884970                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 45504.485678                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 45710.947032                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 45702.306849                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45617.859258                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44842.397445                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 44795.121555                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44817.054977                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44875.891943                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44830.158377                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 44815.584024                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 44846.723027                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 44846.457947                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 44833.789624                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               78781                       # Transaction distribution
system.membus.trans_dist::ReadResp              84254                       # Transaction distribution
system.membus.trans_dist::WriteReq              43831                       # Transaction distribution
system.membus.trans_dist::WriteResp             43828                       # Transaction distribution
system.membus.trans_dist::Writeback              6215                       # Transaction distribution
system.membus.trans_dist::CleanEvict             1216                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            61094                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           50117                       # Transaction distribution
system.membus.trans_dist::ReadExReq             49522                       # Transaction distribution
system.membus.trans_dist::ReadExResp             3101                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq          5483                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       427442                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 427442                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port      1069738                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                 1069738                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                            57394                       # Total snoops (count)
system.membus.snoop_fanout::samples            254906                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  254906    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              254906                       # Request fanout histogram
system.membus.reqLayer0.occupancy           291050214                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization              56.4                       # Layer utilization (%)
system.membus.respLayer0.occupancy          309370624                       # Layer occupancy (ticks)
system.membus.respLayer0.utilization             59.9                       # Layer utilization (%)
system.toL2Bus.trans_dist::ReadReq              78782                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            371328                       # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate            3                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             43832                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            43827                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback            83405                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict           20435                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           29579                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp          29579                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           161223                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          161218                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       292561                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side       122545                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side       122537                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side       122267                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side       122810                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side       122614                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side       122506                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side       122579                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side       122756                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total                980614                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side      1769994                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side      1778957                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side      1770860                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side      1783783                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side      1787183                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side      1781792                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side      1778656                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side      1778193                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               14229418                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          335158                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples           800908                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            7.017024                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.129362                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::7                 787273     98.30%     98.30% # Request fanout histogram
system.toL2Bus.snoop_fanout::8                  13635      1.70%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              7                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              8                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total             800908                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy          495395322                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization             95.9                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy         101110391                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization            19.6                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         101309873                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization            19.6                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy         101121441                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization            19.6                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy         101199500                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization            19.6                       # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy         101216377                       # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization            19.6                       # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy         101535375                       # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization            19.7                       # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy         101020631                       # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization            19.6                       # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy         101318353                       # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization            19.6                       # Layer utilization (%)

---------- End Simulation Statistics   ----------