path: root/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.127293                       # Number of seconds simulated
sim_ticks                                127293406500                       # Number of ticks simulated
final_tick                               127293406500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 627920                       # Simulator instruction rate (inst/s)
host_op_rate                                   801678                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1135795886                       # Simulator tick rate (ticks/s)
host_mem_usage                                 312172                       # Number of bytes of host memory used
host_seconds                                   112.07                       # Real time elapsed on the host
sim_insts                                    70373629                       # Number of instructions simulated
sim_ops                                      89847363                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            255488                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           7924480                       # Number of bytes read from this memory
system.physmem.bytes_read::total              8179968                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       255488                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          255488                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      5370176                       # Number of bytes written to this memory
system.physmem.bytes_written::total           5370176                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3992                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             123820                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                127812                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           83909                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                83909                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst              2007080                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             62253656                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                64260736                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         2007080                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            2007080                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          42187385                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               42187385                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          42187385                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             2007080                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            62253656                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              106448121                       # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1946                       # Number of system calls
system.cpu.numCycles                        254586813                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    70373629                       # Number of instructions committed
system.cpu.committedOps                      89847363                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses              81528488                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                     56                       # Number of float alu accesses
system.cpu.num_func_calls                     3311620                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts      9253644                       # number of instructions that are conditional controls
system.cpu.num_int_insts                     81528488                       # number of integer instructions
system.cpu.num_fp_insts                            56                       # number of float instructions
system.cpu.num_int_register_reads           141328474                       # number of times the integer registers were read
system.cpu.num_int_register_writes           53916283                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                   36                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                  20                       # number of times the floating registers were written
system.cpu.num_cc_register_reads            334802006                       # number of times the CC registers were read
system.cpu.num_cc_register_writes            36877020                       # number of times the CC registers were written
system.cpu.num_mem_refs                      43422001                       # number of memory refs
system.cpu.num_load_insts                    22866262                       # Number of load instructions
system.cpu.num_store_insts                   20555739                       # Number of store instructions
system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
system.cpu.num_busy_cycles               254586812.998000                       # Number of busy cycles
system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
system.cpu.Branches                          13741486                       # Number of branches fetched
system.cpu.op_class::No_OpClass                     0      0.00%      0.00% # Class of executed instruction
system.cpu.op_class::IntAlu                  47187957     52.03%     52.03% # Class of executed instruction
system.cpu.op_class::IntMult                    80119      0.09%     52.12% # Class of executed instruction
system.cpu.op_class::IntDiv                         0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::FloatCvt                       0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  7      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     52.12% # Class of executed instruction
system.cpu.op_class::MemRead                 22866262     25.21%     77.33% # Class of executed instruction
system.cpu.op_class::MemWrite                20555739     22.67%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                   90690084                       # Class of executed instruction
system.cpu.dcache.tags.replacements            155902                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4076.389329                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            42608169                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            159998                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            266.304385                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        1061071000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4076.389329                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.995212                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.995212                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          856                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         3191                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          85731098                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         85731098                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     22749839                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        22749839                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     19742869                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       19742869                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        83623                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         83623                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        15919                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      42492708                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         42492708                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     42576331                       # number of overall hits
system.cpu.dcache.overall_hits::total        42576331                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data        30228                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total         30228                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       107032                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       107032                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data        40121                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total        40121                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data       137260                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         137260                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       177381                       # number of overall misses
system.cpu.dcache.overall_misses::total        177381                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data    517066000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total    517066000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   5689116000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   5689116000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data   6206182000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total   6206182000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data   6206182000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total   6206182000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     22780067                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     22780067                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       123744                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       123744                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15919                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     42629968                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     42629968                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     42753712                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42753712                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001327                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.001327                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005392                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.005392                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.324226                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.324226                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.003220                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.003220                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.004149                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.004149                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17105.531295                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17105.531295                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.412064                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.412064                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45214.789451                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 45214.789451                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 34987.862285                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 34987.862285                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       128239                       # number of writebacks
system.cpu.dcache.writebacks::total            128239                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1120                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total         1120                       # number of ReadReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data         1120                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total         1120                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data         1120                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total         1120                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29108                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        29108                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107032                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       107032                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        23858                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total        23858                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       136140                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       136140                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       159998                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       159998                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    457995500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total    457995500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5528568000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   5528568000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1058278000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1058278000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5986563500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   5986563500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7044841500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   7044841500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001278                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001278                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005392                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.192801                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.192801                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003194                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.003194                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003742                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.003742                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15734.351381                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15734.351381                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51653.412064                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51653.412064                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44357.364406                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44357.364406                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43973.582342                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 43973.582342                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44030.809760                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 44030.809760                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements             16890                       # number of replacements
system.cpu.icache.tags.tagsinuse          1733.672960                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            78126162                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             18908                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           4131.910408                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1733.672960                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.846520                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.846520                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         2018                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           15                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          294                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1645                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.985352                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         156309048                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        156309048                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     78126162                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        78126162                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      78126162                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         78126162                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     78126162                       # number of overall hits
system.cpu.icache.overall_hits::total        78126162                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        18908                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         18908                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        18908                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          18908                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        18908                       # number of overall misses
system.cpu.icache.overall_misses::total         18908                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    413935000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    413935000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    413935000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    413935000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    413935000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    413935000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     78145070                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     78145070                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     78145070                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     78145070                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     78145070                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     78145070                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000242                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000242                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000242                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000242                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000242                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000242                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21892.056272                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 21892.056272                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21892.056272                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 21892.056272                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21892.056272                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 21892.056272                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        18908                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        18908                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        18908                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        18908                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        18908                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        18908                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    385573000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    385573000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    385573000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    385573000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    385573000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    385573000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000242                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000242                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000242                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20392.056272                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20392.056272                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20392.056272                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 20392.056272                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20392.056272                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20392.056272                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            94693                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        30351.005772                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              74295                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           125788                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.590637                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 27796.867853                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  1151.768393                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  1402.369526                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.848293                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.035149                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.042797                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.926239                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31095                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1359                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2        15103                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13917                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          607                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.948944                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses          2689980                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses         2689980                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        14916                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        31426                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          46342                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       128239                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       128239                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         4752                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         4752                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        14916                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        36178                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           51094                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        14916                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        36178                       # number of overall hits
system.cpu.l2cache.overall_hits::total          51094                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3992                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        21540                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        25532                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       102280                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       102280                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3992                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       123820                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        127812                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3992                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       123820                       # number of overall misses
system.cpu.l2cache.overall_misses::total       127812                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    210047000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1133331500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   1343378500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5371640000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   5371640000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    210047000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   6504971500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   6715018500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    210047000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   6504971500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   6715018500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        18908                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data        52966                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        71874                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       128239                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       128239                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       107032                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       107032                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        18908                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       159998                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       178906                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        18908                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       159998                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       178906                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.211128                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.406676                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.355233                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955602                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.955602                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.211128                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.773885                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.714409                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.211128                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.773885                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.714409                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52616.983968                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52615.204271                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52615.482532                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52518.967540                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52518.967540                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52616.983968                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52535.709094                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52538.247582                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52616.983968                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52535.709094                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52538.247582                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        83909                       # number of writebacks
system.cpu.l2cache.writebacks::total            83909                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3992                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21540                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        25532                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102280                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       102280                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3992                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       123820                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       127812                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3992                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       123820                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       127812                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    161778000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    873989500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1035767500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4142346500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4142346500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    161778000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5016336000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   5178114000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    161778000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5016336000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   5178114000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.211128                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.406676                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.355233                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955602                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955602                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.211128                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.773885                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.714409                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.211128                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.773885                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.714409                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40525.551102                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40575.185701                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40567.425192                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.063551                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.063551                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40525.551102                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40513.131966                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40513.519857                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40525.551102                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40513.131966                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40513.519857                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq          71874                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp         71874                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       128239                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       107032                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       107032                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        37816                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       448235                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total            486051                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1210112                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18447168                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total           19657280                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples       307145                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3             307145    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total         307145                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy      281811500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      28362000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     239997000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
system.membus.trans_dist::ReadReq               25532                       # Transaction distribution
system.membus.trans_dist::ReadResp              25532                       # Transaction distribution
system.membus.trans_dist::Writeback             83909                       # Transaction distribution
system.membus.trans_dist::ReadExReq            102280                       # Transaction distribution
system.membus.trans_dist::ReadExResp           102280                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       339533                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 339533                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13550144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                13550144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            214640                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  214640    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              214640                       # Request fanout histogram
system.membus.reqLayer0.occupancy           566253984                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.4                       # Layer utilization (%)
system.membus.respLayer1.occupancy          642220500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)

---------- End Simulation Statistics   ----------