Open doc files, version 1 of everything

This copies over files from:

http://download.nvidia.com/open-gpu-doc/

with a few overrides from local, as-yet-to-be-published
files (generally just a file suffix and licensing tweak).

Here's the script that was used to create this commit:

    wget -r http://download.nvidia.com/open-gpu-doc/
    mv download.nvidia.com/open-gpu-doc/* .
    rm -rf download.nvidia.com/
    find . -name index.html  | xargs rm -f
    find . -name Thumbs.db | xargs rm -f

    find . -type f | grep -v \.git | xargs file | grep CRLF | cut -f1 -d: | xargs dos2unix

    for f in `find . -name 1 | cut -f2 -d "/"`; do pushd $f; mv 1/* .; popd; done
    find . -name 1 | xargs rmdir

    rm -rf Host-Fifo/volta/gv100
    mkdir -p Host-Fifo/volta/gv100

    cp $sw/docs/Public_Devel_Docs/release/Host-Fifo/volta/gv100/* Host-Fifo/volta/gv100/

    rm Display-Ref-Manuals/gv100/dev_display.ref
    cp $sw/docs/Public_Devel_Docs/release/Display-Ref-Manuals/1/gv100/dev_display.ref \
       Display-Ref-Manuals/gv100/dev_display.ref.txt

    git add .
    git mv DCB/DCB-4.0-Specification.html DCB/DCB-4.x-Specification.html

    git reset HEAD Display-Class-Methods/2
    git reset HEAD DCB/2

    git commit

Reviewed-by: Andy Ritger

4 files changed, 168 insertions, 0 deletions

diff --git a/pascal/BIT_DISPLAY_PTRS-U-BIT_DP_PTRS-d.pdf b/pascal/BIT_DISPLAY_PTRS-U-BIT_DP_PTRS-d.pdf
new file mode 100644
index 0000000..9029f0c
--- /dev/null
+++ b/pascal/BIT_DISPLAY_PTRS-U-BIT_DP_PTRS-d.pdf
diff --git a/pascal/gp100-fbpa.txt b/pascal/gp100-fbpa.txt
new file mode 100644
index 0000000..6258f06
--- /dev/null
+++ b/pascal/gp100-fbpa.txt
@@ -0,0 +1,92 @@
+--------------------------------------------------------------------------------
+
+Synopsis:
+
+Description of changes made to the framebuffer partition addressing (FBPA) in
+Pascal and later NVIDIA architectures.
+
+--------------------------------------------------------------------------------
+
+Description:
+
+NVIDIA moved and expanded the MMIO space used for accessing the per-partition
+information on Pascal and later architectures.  Relative offsets to specific
+controls remain the same as for prior architectures, for the most part.
+
+--------------------------------------------------------------------------------
+
+Summary:
+
+These MMIO ranges have been moved and expanded from 0x1000 to 0x4000 in size:
+
+Name                Old Range               New Range
+NV_PFB_FBPA         0x10F000 (0x1000)       0x9A0000 (0x4000)
+NV_PFB_FBPA[i]      0x110000+(i * 0x1000)   0x900000+(i * 0x4000)
+NV_PFB_FBPA_MC[i]   0x11D000+(i * 0x1000)   0x980000+(i * 0x4000)
+
+The number of NV_PFB_FBPA[i] ranges is increased to a maximum of 16.
+The number of NV_PFB_FBPA_MC[i] ranges remains 3.
+
+Memory partition sizing and programming is the same as in prior NVIDIA
+architectures.
+
+FBPAs are grouped into logical FBP units.  In most prior NVIDIA architectures
+(except GF108) each logical FBP mapped to one FBPA.  To support High Bandwidth
+Memory (HBM) GP100 groups 2 FBPAs into each logical FBP.  This is noted here to
+be clear that the number of logical FBPs does not necessarily equate to the number
+of physical FBPAs.  The register NV_PTOP_SCAL_NUM_FBPA_PER_FBP (0x22458) defines
+this relationship in Pascal and later architectures.
+
+Per-partition memory size detection works similarly to the way it has in prior
+NVIDIA architectures:
+
+1) Determine maximum number of possible FBPAs by reading
+    NV_PTOP_SCAL_NUM_FBPAS (0x2243C)
+2) Determine number of FBPAs per FBP by reading
+    NV_PTOP_SCAL_NUM_FBPA_PER_FBP (0x22458)
+3) Determine maximum number of LTCs per FBP by reading
+    NV_FUSE_STATUS_OPT_ROP_L2_FBP(i) (0x21d70+(i)*4)
+4) For each bit not set in NV_FUSE_STATUS_OPT_FBIO (0x21C14)
+    a. Read the partition memory size from
+        NV_PFB_FBPA[i] + _CSTATUS_RAMAMOUNT (0x20C)
+    b. Up to the number of possible FBPAs determined in #1
+5) Any difference in the per-partition memory size indicates a "mixed memory"
+    configuration (Fermi & Kepler).
+6) Any difference in the per-partition LTC coverage effectively indicates a
+    "mixed memory" configuration (Maxwell and later).
+7) For "mixed memory" configurations:
+    a. Set NV_PFB_FBHUB_NUM_ACTIVE_FBPS (0x100800) bit 4 to 1.
+    b. Treat GPU FB address space as split into lower and upper sections.
+        The lower size is common partition size * FBPA count and is
+        based at 0.  The upper section starts at either 0x2'00000000
+        (Fermi/Kepler) or 0x10'00000000 (Maxwell & later) PLUS the
+        common partition size.  Its size is the remaining GPU FB not
+        already mapped in the lower section.
+    c. The upper section of memory should not be used for displayable or
+        compression-related surfaces.
+
+--------------------------------------------------------------------------------
+
+Definitions:
+
+#define NV_PTOP_SCAL_NUM_FBPAS                          0x0002243C /* R--4R */
+
+#define NV_PTOP_SCAL_NUM_FBPAS_VALUE                           4:0 /* R-IVF */
+
+
+#define NV_PTOP_SCAL_NUM_FBPA_PER_FBP                   0x00022458 /* R--4R */
+
+#define NV_PTOP_SCAL_NUM_FBPA_PER_FBP_VALUE                    4:0 /* R-IVF */
+
+
+#define NV_FUSE_STATUS_OPT_ROP_L2_FBP(i)        (0x00021d70+(i)*4) /* R-I4A */
+#define NV_FUSE_STATUS_OPT_ROP_L2_FBP__SIZE_1                   16 /*       */
+#define NV_FUSE_STATUS_OPT_ROP_L2_FBP_DATA                    31:0 /* R-IVF */
+
+#define NV_FUSE_STATUS_OPT_FBIO                         0x00021C14 /* R-I4R */
+#define NV_FUSE_STATUS_OPT_FBIO_DATA                          15:0 /* R-IVF */
+
+#define NV_PFB_FBHUB_NUM_ACTIVE_FBPS                    0x00100800 /* RW-4R */
+#define NV_PFB_FBHUB_NUM_ACTIVE_FBPS_MIXED_MEM_DENSITY         4:4 /*       */
+
+--------------------------------------------------------------------------------
diff --git a/pascal/gp100-mmu-format.pdf b/pascal/gp100-mmu-format.pdf
new file mode 100644
index 0000000..f55dff4
--- /dev/null
+++ b/pascal/gp100-mmu-format.pdf
diff --git a/pascal/gp100-msi-intr.txt b/pascal/gp100-msi-intr.txt
new file mode 100644
index 0000000..1081e3b
--- /dev/null
+++ b/pascal/gp100-msi-intr.txt
@@ -0,0 +1,76 @@
+--------------------------------------------------------------------------------
+
+Synopsis:
+
+Description of changes made to the interrupt controller in Pascal and later
+NVIDIA architectures.
+
+--------------------------------------------------------------------------------
+
+Description:
+
+NVIDIA replaced the old interrupt control tree in Pascal and later architectures
+to migrate away from a legacy PCI interrupt based scheme toward MSI-X interrupts.
+
+--------------------------------------------------------------------------------
+
+Summary:
+
+These registers no longer exist in Pascal and later architectures:
+#define NV_PMC_INTR_2                           0x00000108 /*       */
+#define NV_PMC_INTR_LTC                         0x0000017c /* R--4R */
+#define NV_PMC_INTR_FBPA                        0x00000180 /* R--4R */
+#define NV_PMC_INTR_READ(i)             (0x00000160+(i)*4) /* R--4A */
+#define NV_PMC_INTR_IMSK(i)             (0x00000640+(i)*4) /* RW-4A */
+
+These registers are added in Pascal and later architectures:
+#define NV_PMC_INTR_MODE(i)             (0x00000120+(i)*4) /* R--4A */
+#define NV_PMC_INTR_EN_SET(i)           (0x00000160+(i)*4) /* -W-4A */
+#define NV_PMC_INTR_EN_CLEAR(i)         (0x00000180+(i)*4) /* -W-4A */
+#define NV_PMC_INTR_SW(i)               (0x000001A0+(i)*4) /* RW-4A */
+#define NV_PMC_INTR_LTC                         0x000001C0 /* R--4R */
+#define NV_PMC_INTR_FBPA                        0x000001D0 /* R--4R */
+
+The fields of the device interrupt pending register are no longer writable.
+#define NV_PMC_INTR(i)                              (0x00000100+(i)*4)
+
+The function of this register has changed.  It is now a read-only status register
+reporting the per-device interrupt enable state.
+#define NV_PMC_INTR_EN(i)                           (0x00000140+(i)*4)
+
+Furthermore, the NV_PMC_INTR(2) has been removed.  Only INTR(0) and INTR(1) exist
+on Pascal and later architectures.
+
+Each bit of NV_PMC_INTR_MODE(i) defines whether the corresponding device interrupt
+is LEVEL trigger (0) or EDGE trigger (1).
+
+NV_PMC_INTR_EN(i) is now read-only and no longer used to enable/disable interrupts.
+That task is now handled by NV_PMC_INTR_EN_SET(i) and NV_PMC_INTR_EN_CLEAR(i).
+Each bit corresponds with a GPU device.
+
+The mapping of devices to interrupts is best determined by parsing the PTOP
+DEVICE_INFO structure, however legacy devices still map to the same bitfields
+as in pre-Pascal architectures.
+
+Device              Bit#
+NVENC1              1
+CE5                 2
+NVENC2              4
+CE0                 5
+CE1                 6
+CE2/GRCOPY          7
+PFIFO               8
+REPLAYABLE_FAULT    9
+CE3                 10
+CE4                 11
+PGRAPH              12
+PFB                 13
+SEC                 15
+NVENC0              16
+NVDEC               17
+THERMAL             18
+PTIMER              20
+PMU                 24
+LTC                 25
+SW                  31
+