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Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
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#define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS 0x000008AC /* RW-4R */
The MMU_NUM_ACTIVE_LTCS_USE_NVLINK segment of
MMU_NUM_ACTIVE_LTCS register hold the status of peer
connection through NVLINK. This is used to decide whether a
peer is PCIe connected or NVLink connected. If NVLink
connected then NVLINK_PEER_THROUGH_L2 determines whether the
peer traffic will be sent to master L2 or not(directly sent to
HSHUB).
#define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK 23:16 /* RWEVF */
#define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_INIT 0x00000000 /* RWE-V */
#define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER(i) ((i)+16):((i)+16) /* */
#define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER__SIZE_1 8 /* */
#define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_ENABLED 0x00000001 /* */
#define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_DISABLED 0x00000000 /* */
NVLINK_PEER_THROUGH_L2 flag tells MMU/HUBs whether NVLINK
connected peer traffic to be sent through master L2 (for
caching opportunity) or not. Caching is determined by VOL (==0
is cached) bit.
#define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2 24:24 /* RWEVF */
#define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_INIT 0x00000000 /* RWE-V */
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KEY LEGEND
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Each define in the .ref file has a 5 field code to say what kind of define it is: i.e. /* RW--R */
The following legend shows accepted values for each of the 5 fields:
Read, Write, Internal State, Declaration/Size, and Define Indicator.
Read
' ' = Other Information
'-' = Field is part of a write-only register
'C' = Value read is always the same, constant value line follows (C)
'R' = Value is read
Write
' ' = Other Information
'-' = Must not be written (D), value ignored when written (R,A,F)
'W' = Can be written
Internal State
' ' = Other Information
'-' = No internal state
'X' = Internal state, initial value is unknown
'I' = Internal state, initial value is known and follows (I), see "Reset Signal" section for signal.
'E' = Internal state, initial value is known and follows (E), see "Reset Signal" section for signal.
'B' = Internal state, initial value is known and follows (B), see "Reset Signal" section for signal.
'C' = Internal state, initial value is known and follows (C), see "Reset Signal" section for signal.
'V' = (legacy) Internal state, initialize at volatile reset
'D' = (legacy) Internal state, default initial value at object creation (legacy: Only used in dev_ram.ref)
'C' = (legacy) Internal state, initial value at object creation
'C' = (legacy) Internal state, class-based initial value at object creation (legacy: Only used in dev_ram.ref)
Declaration/Size
' ' = Other Information
'-' = Does Not Apply
'V' = Type is void
'U' = Type is unsigned integer
'S' = Type is signed integer
'F' = Type is IEEE floating point
'1' = Byte size (008)
'2' = Short size (016)
'3' = Three byte size (024)
'4' = Word size (032)
'8' = Double size (064)
Define Indicator
' ' = Other Information
'C' = Clear value
'D' = Device
'L' = Logical device.
'M' = Memory
'R' = Register
'A' = Array of Registers
'F' = Field
'V' = Value
'T' = Task
'P' = Phantom Register
'B' = (legacy) Bundle address
'G' = (legacy) General purpose configuration register
'C' = (legacy) Class
Reset signal defaults for graphics engine registers.
All graphics engine registers use the following defaults for reset signals:
'E' = initialized with engine_reset_
'I' = initialized with context_reset_
'B' = initialized with reset_IB_dly_
Reset signal
For units that differ from the graphics engine defaults, the reset signals should be defined here:
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