kill some stdio function decl

5 files changed, 0 insertions, 958 deletions

diff --git a/arch/arm/include/asm/arch-mx7ulp/scg.h b/arch/arm/include/asm/arch-mx7ulp/scg.h
deleted file mode 100644
index 531d8f3..0000000
--- a/arch/arm/include/asm/arch-mx7ulp/scg.h
+++ /dev/null
@@ -1,342 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- */
-
-#ifndef _ASM_ARCH_SCG_H
-#define _ASM_ARCH_SCG_H
-
-#include <common.h>
-
-#ifdef CONFIG_CLK_DEBUG
-#define clk_debug(fmt, args...)	printf(fmt, ##args)
-#else
-#define clk_debug(fmt, args...)
-#endif
-
-#define SCG_CCR_SCS_SHIFT		(24)
-#define SCG_CCR_SCS_MASK		((0xFUL) << SCG_CCR_SCS_SHIFT)
-#define SCG_CCR_DIVCORE_SHIFT		(16)
-#define SCG_CCR_DIVCORE_MASK		((0xFUL) << SCG_CCR_DIVCORE_SHIFT)
-#define SCG_CCR_DIVPLAT_SHIFT		(12)
-#define SCG_CCR_DIVPLAT_MASK		((0xFUL) << SCG_CCR_DIVPLAT_SHIFT)
-#define SCG_CCR_DIVEXT_SHIFT		(8)
-#define SCG_CCR_DIVEXT_MASK		((0xFUL) << SCG_CCR_DIVEXT_SHIFT)
-#define SCG_CCR_DIVBUS_SHIFT		(4)
-#define SCG_CCR_DIVBUS_MASK		((0xFUL) << SCG_CCR_DIVBUS_SHIFT)
-#define SCG_CCR_DIVSLOW_SHIFT		(0)
-#define SCG_CCR_DIVSLOW_MASK		((0xFUL) << SCG_CCR_DIVSLOW_SHIFT)
-
-/* SCG DDR Clock Control Register */
-#define SCG_DDRCCR_DDRCS_SHIFT		(24)
-#define SCG_DDRCCR_DDRCS_MASK		((0x1UL) << SCG_DDRCCR_DDRCS_SHIFT)
-
-#define SCG_DDRCCR_DDRDIV_SHIFT		(0)
-#define SCG_DDRCCR_DDRDIV_MASK		((0x7UL) << SCG_DDRCCR_DDRDIV_SHIFT)
-
-/* SCG NIC Clock Control Register */
-#define SCG_NICCCR_NICCS_SHIFT		(28)
-#define SCG_NICCCR_NICCS_MASK		((0x1UL) << SCG_NICCCR_NICCS_SHIFT)
-
-#define SCG_NICCCR_NIC0_DIV_SHIFT       (24)
-#define SCG_NICCCR_NIC0_DIV_MASK        ((0xFUL) << SCG_NICCCR_NIC0_DIV_SHIFT)
-
-#define SCG_NICCCR_GPU_DIV_SHIFT        (20)
-#define SCG_NICCCR_GPU_DIV_MASK         ((0xFUL) << SCG_NICCCR_GPU_DIV_SHIFT)
-
-#define SCG_NICCCR_NIC1_DIV_SHIFT       (16)
-#define SCG_NICCCR_NIC1_DIV_MASK        ((0xFUL) << SCG_NICCCR_NIC1_DIV_SHIFT)
-
-#define SCG_NICCCR_NIC1_DIVEXT_SHIFT    (8)
-#define SCG_NICCCR_NIC1_DIVEXT_MASK   ((0xFUL) << SCG_NICCCR_NIC1_DIVEXT_SHIFT)
-
-#define SCG_NICCCR_NIC1_DIVBUS_SHIFT    (4)
-#define SCG_NICCCR_NIC1_DIVBUS_MASK   ((0xFUL) << SCG_NICCCR_NIC1_DIVBUS_SHIFT)
-
-/* SCG NIC clock status register */
-#define SCG_NICCSR_NICCS_SHIFT          (28)
-#define SCG_NICCSR_NICCS_MASK           ((0x1UL) << SCG_NICCSR_NICCS_SHIFT)
-
-#define SCG_NICCSR_NIC0DIV_SHIFT        (24)
-#define SCG_NICCSR_NIC0DIV_MASK         ((0xFUL) << SCG_NICCSR_NIC0DIV_SHIFT)
-#define SCG_NICCSR_GPUDIV_SHIFT         (20)
-#define SCG_NICCSR_GPUDIV_MASK          ((0xFUL) << SCG_NICCSR_GPUDIV_SHIFT)
-#define SCG_NICCSR_NIC1DIV_SHIFT        (16)
-#define SCG_NICCSR_NIC1DIV_MASK         ((0xFUL) << SCG_NICCSR_NIC1DIV_SHIFT)
-#define SCG_NICCSR_NIC1EXTDIV_SHIFT     (8)
-#define SCG_NICCSR_NIC1EXTDIV_MASK      ((0xFUL) << SCG_NICCSR_NIC1EXTDIV_SHIFT)
-#define SCG_NICCSR_NIC1BUSDIV_SHIFT     (4)
-#define SCG_NICCSR_NIC1BUSDIV_MASK      ((0xFUL) << SCG_NICCSR_NIC1BUSDIV_SHIFT)
-
-/* SCG Slow IRC Control Status Register */
-#define SCG_SIRC_CSR_SIRCVLD_SHIFT      (24)
-#define SCG_SIRC_CSR_SIRCVLD_MASK       ((0x1UL) << SCG_SIRC_CSR_SIRCVLD_SHIFT)
-
-#define SCG_SIRC_CSR_SIRCEN_SHIFT       (0)
-#define SCG_SIRC_CSR_SIRCEN_MASK        ((0x1UL) << SCG_SIRC_CSR_SIRCEN_SHIFT)
-
-/* SCG Slow IRC Configuration Register */
-#define SCG_SIRCCFG_RANGE_SHIFT         (0)
-#define SCG_SIRCCFG_RANGE_MASK          ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT)
-#define SCG_SIRCCFG_RANGE_4M            ((0x0UL) << SCG_SIRCCFG_RANGE_SHIFT)
-#define SCG_SIRCCFG_RANGE_16M           ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT)
-
-/* SCG Slow IRC Divide Register */
-#define SCG_SIRCDIV_DIV3_SHIFT          (16)
-#define SCG_SIRCDIV_DIV3_MASK           ((0x7UL) << SCG_SIRCDIV_DIV3_SHIFT)
-
-#define SCG_SIRCDIV_DIV2_SHIFT          (8)
-#define SCG_SIRCDIV_DIV2_MASK           ((0x7UL) << SCG_SIRCDIV_DIV2_SHIFT)
-
-#define SCG_SIRCDIV_DIV1_SHIFT          (0)
-#define SCG_SIRCDIV_DIV1_MASK           ((0x7UL) << SCG_SIRCDIV_DIV1_SHIFT)
-/*
- * FIRC/SIRC DIV1 ==> xIRC_PLAT_CLK
- * FIRC/SIRC DIV2 ==> xIRC_BUS_CLK
- * FIRC/SIRC DIV3 ==> xIRC_SLOW_CLK
- */
-
-/* SCG Fast IRC Control Status Register */
-#define SCG_FIRC_CSR_FIRCVLD_SHIFT      (24)
-#define SCG_FIRC_CSR_FIRCVLD_MASK       ((0x1UL) << SCG_FIRC_CSR_FIRCVLD_SHIFT)
-
-#define SCG_FIRC_CSR_FIRCEN_SHIFT       (0)
-#define SCG_FIRC_CSR_FIRCEN_MASK        ((0x1UL) << SCG_FIRC_CSR_FIRCEN_SHIFT)
-
-/* SCG Fast IRC Divide Register */
-#define SCG_FIRCDIV_DIV3_SHIFT          (16)
-#define SCG_FIRCDIV_DIV3_MASK           ((0x7UL) << SCG_FIRCDIV_DIV3_SHIFT)
-
-#define SCG_FIRCDIV_DIV2_SHIFT          (8)
-#define SCG_FIRCDIV_DIV2_MASK           ((0x7UL) << SCG_FIRCDIV_DIV2_SHIFT)
-
-#define SCG_FIRCDIV_DIV1_SHIFT          (0)
-#define SCG_FIRCDIV_DIV1_MASK           ((0x7UL) << SCG_FIRCDIV_DIV1_SHIFT)
-
-#define SCG_FIRCCFG_RANGE_SHIFT         (0)
-#define SCG_FIRCCFG_RANGE_MASK          ((0x3UL) << SCG_FIRCCFG_RANGE_SHIFT)
-
-#define SCG_FIRCCFG_RANGE_SHIFT         (0)
-#define SCG_FIRCCFG_RANGE_48M           ((0x0UL) << SCG_FIRCCFG_RANGE_SHIFT)
-
-/* SCG System OSC Control Status Register */
-#define SCG_SOSC_CSR_SOSCVLD_SHIFT      (24)
-#define SCG_SOSC_CSR_SOSCVLD_MASK       ((0x1UL) << SCG_SOSC_CSR_SOSCVLD_SHIFT)
-
-/* SCG Fast IRC Divide Register */
-#define SCG_SOSCDIV_DIV3_SHIFT          (16)
-#define SCG_SOSCDIV_DIV3_MASK           ((0x7UL) << SCG_SOSCDIV_DIV3_SHIFT)
-
-#define SCG_SOSCDIV_DIV2_SHIFT          (8)
-#define SCG_SOSCDIV_DIV2_MASK           ((0x7UL) << SCG_SOSCDIV_DIV2_SHIFT)
-
-#define SCG_SOSCDIV_DIV1_SHIFT          (0)
-#define SCG_SOSCDIV_DIV1_MASK           ((0x7UL) << SCG_SOSCDIV_DIV1_SHIFT)
-
-/* SCG RTC OSC Control Status Register */
-#define SCG_ROSC_CSR_ROSCVLD_SHIFT      (24)
-#define SCG_ROSC_CSR_ROSCVLD_MASK       ((0x1UL) << SCG_ROSC_CSR_ROSCVLD_SHIFT)
-
-#define SCG_SPLL_CSR_SPLLVLD_SHIFT      (24)
-#define SCG_SPLL_CSR_SPLLVLD_MASK       ((0x1UL) << SCG_SPLL_CSR_SPLLVLD_SHIFT)
-#define SCG_SPLL_CSR_SPLLEN_SHIFT       (0)
-#define SCG_SPLL_CSR_SPLLEN_MASK        ((0x1UL) << SCG_SPLL_CSR_SPLLEN_SHIFT)
-#define SCG_APLL_CSR_APLLEN_SHIFT       (0)
-#define SCG_APLL_CSR_APLLEN_MASK        (0x1UL)
-#define SCG_APLL_CSR_APLLVLD_MASK       (0x01000000)
-
-#define SCG_UPLL_CSR_UPLLVLD_MASK       (0x01000000)
-
-
-#define SCG_PLL_PFD3_GATE_MASK          (0x80000000)
-#define SCG_PLL_PFD2_GATE_MASK          (0x00800000)
-#define SCG_PLL_PFD1_GATE_MASK          (0x00008000)
-#define SCG_PLL_PFD0_GATE_MASK          (0x00000080)
-#define SCG_PLL_PFD3_VALID_MASK         (0x40000000)
-#define SCG_PLL_PFD2_VALID_MASK         (0x00400000)
-#define SCG_PLL_PFD1_VALID_MASK         (0x00004000)
-#define SCG_PLL_PFD0_VALID_MASK         (0x00000040)
-
-#define SCG_PLL_PFD0_FRAC_SHIFT         (0)
-#define SCG_PLL_PFD0_FRAC_MASK          ((0x3F) << SCG_PLL_PFD0_FRAC_SHIFT)
-#define SCG_PLL_PFD1_FRAC_SHIFT         (8)
-#define SCG_PLL_PFD1_FRAC_MASK          ((0x3F) << SCG_PLL_PFD1_FRAC_SHIFT)
-#define SCG_PLL_PFD2_FRAC_SHIFT         (16)
-#define SCG_PLL_PFD2_FRAC_MASK          ((0x3F) << SCG_PLL_PFD2_FRAC_SHIFT)
-#define SCG_PLL_PFD3_FRAC_SHIFT         (24)
-#define SCG_PLL_PFD3_FRAC_MASK          ((0x3F) << SCG_PLL_PFD3_FRAC_SHIFT)
-
-#define SCG_PLL_CFG_POSTDIV2_SHIFT      (28)
-#define SCG_PLL_CFG_POSTDIV2_MASK       ((0xFUL) << SCG_PLL_CFG_POSTDIV2_SHIFT)
-#define SCG_PLL_CFG_POSTDIV1_SHIFT      (24)
-#define SCG_PLL_CFG_POSTDIV1_MASK       ((0xFUL) << SCG_PLL_CFG_POSTDIV1_SHIFT)
-#define SCG_PLL_CFG_MULT_SHIFT          (16)
-#define SCG1_SPLL_CFG_MULT_MASK         ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT)
-#define SCG_APLL_CFG_MULT_MASK          ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT)
-#define SCG_PLL_CFG_PFDSEL_SHIFT        (14)
-#define SCG_PLL_CFG_PFDSEL_MASK         ((0x3UL) << SCG_PLL_CFG_PFDSEL_SHIFT)
-#define SCG_PLL_CFG_PREDIV_SHIFT        (8)
-#define SCG_PLL_CFG_PREDIV_MASK         ((0x7UL) << SCG_PLL_CFG_PREDIV_SHIFT)
-#define SCG_PLL_CFG_BYPASS_SHIFT        (2)
-/* 0: SPLL, 1: bypass */
-#define SCG_PLL_CFG_BYPASS_MASK         ((0x1UL) << SCG_PLL_CFG_BYPASS_SHIFT)
-#define SCG_PLL_CFG_PLLSEL_SHIFT        (1)
-/* 0: pll, 1: pfd */
-#define SCG_PLL_CFG_PLLSEL_MASK         ((0x1UL) << SCG_PLL_CFG_PLLSEL_SHIFT)
-#define SCG_PLL_CFG_CLKSRC_SHIFT        (0)
-/* 0: Sys-OSC, 1: FIRC */
-#define SCG_PLL_CFG_CLKSRC_MASK         ((0x1UL) << SCG_PLL_CFG_CLKSRC_SHIFT)
-#define SCG0_SPLL_CFG_MULT_SHIFT        (17)
-/* 0: Multiplier = 20, 1: Multiplier = 22 */
-#define SCG0_SPLL_CFG_MULT_MASK         ((0x1UL) << SCG0_SPLL_CFG_MULT_SHIFT)
-
-#define PLL_USB_EN_USB_CLKS_MASK	(0x01 << 6)
-#define PLL_USB_PWR_MASK		(0x01 << 12)
-#define PLL_USB_ENABLE_MASK		(0x01 << 13)
-#define PLL_USB_BYPASS_MASK		(0x01 << 16)
-#define PLL_USB_REG_ENABLE_MASK		(0x01 << 21)
-#define PLL_USB_DIV_SEL_MASK		(0x07 << 22)
-#define PLL_USB_LOCK_MASK		(0x01 << 31)
-
-enum scg_clk {
-	SCG_SOSC_CLK,
-	SCG_FIRC_CLK,
-	SCG_SIRC_CLK,
-	SCG_ROSC_CLK,
-	SCG_SIRC_DIV1_CLK,
-	SCG_SIRC_DIV2_CLK,
-	SCG_SIRC_DIV3_CLK,
-	SCG_FIRC_DIV1_CLK,
-	SCG_FIRC_DIV2_CLK,
-	SCG_FIRC_DIV3_CLK,
-	SCG_SOSC_DIV1_CLK,
-	SCG_SOSC_DIV2_CLK,
-	SCG_SOSC_DIV3_CLK,
-	SCG_CORE_CLK,
-	SCG_BUS_CLK,
-	SCG_SPLL_PFD0_CLK,
-	SCG_SPLL_PFD1_CLK,
-	SCG_SPLL_PFD2_CLK,
-	SCG_SPLL_PFD3_CLK,
-	SCG_DDR_CLK,
-	SCG_NIC0_CLK,
-	SCG_GPU_CLK,
-	SCG_NIC1_CLK,
-	SCG_NIC1_BUS_CLK,
-	SCG_NIC1_EXT_CLK,
-	SCG_APLL_PFD0_CLK,
-	SCG_APLL_PFD1_CLK,
-	SCG_APLL_PFD2_CLK,
-	SCG_APLL_PFD3_CLK,
-	USB_PLL_OUT,
-	MIPI_PLL_OUT
-};
-
-enum scg_sys_src {
-	SCG_SCS_SYS_OSC = 1,
-	SCG_SCS_SLOW_IRC,
-	SCG_SCS_FAST_IRC,
-	SCG_SCS_RTC_OSC,
-	SCG_SCS_AUX_PLL,
-	SCG_SCS_SYS_PLL,
-	SCG_SCS_USBPHY_PLL,
-};
-
-/* PLL supported by i.mx7ulp */
-enum pll_clocks {
-	PLL_M4_SPLL,	/* M4 SPLL */
-	PLL_M4_APLL,	/* M4 APLL*/
-	PLL_A7_SPLL,	/* A7 SPLL */
-	PLL_A7_APLL,	/* A7 APLL */
-	PLL_USB,	/* USB PLL*/
-	PLL_MIPI,	/* MIPI PLL */
-};
-
-typedef struct scg_regs {
-	u32 verid;	/* VERSION_ID */
-	u32 param;	/*  PARAMETER */
-	u32 rsvd11[2];
-
-	u32 csr;	/*  Clock Status Register */
-	u32 rccr;	/*  Run Clock Control Register */
-	u32 vccr;	/*  VLPR Clock Control Register */
-	u32 hccr;	/*  HSRUN Clock Control Register */
-	u32 clkoutcnfg;	/*  SCG CLKOUT Configuration Register */
-	u32 rsvd12[3];
-	u32 ddrccr;	/*  SCG DDR Clock Control Register */
-	u32 rsvd13[3];
-	u32 nicccr;	/*  NIC Clock Control Register */
-	u32 niccsr;	/*  NIC Clock Status Register */
-	u32 rsvd10[46];
-
-	u32 sosccsr;	/*  System OSC Control Status Register, offset 0x100 */
-	u32 soscdiv;	/*  System OSC Divide Register */
-	u32 sosccfg;	/*  System Oscillator Configuration Register */
-	u32 sosctest;	/*  System Oscillator Test Register */
-	u32 rsvd20[60];
-
-	u32 sirccsr;	/*  Slow IRC Control Status Register, offset 0x200 */
-	u32 sircdiv;	/*  Slow IRC Divide Register */
-	u32 sirccfg;	/*  Slow IRC Configuration Register */
-	u32 sirctrim;	/*  Slow IRC Trim Register */
-	u32 loptrim;	/*  Low Power Oscillator Trim Register */
-	u32 sirctest;	/*  Slow IRC Test Register */
-	u32 rsvd30[58];
-
-	u32 firccsr;	/*  Fast IRC Control Status Register, offset 0x300 */
-	u32 fircdiv;
-	u32 firccfg;
-	u32 firctcfg;	/*  Fast IRC Trim Configuration Register */
-	u32 firctriml;	/*  Fast IRC Trim Low Register */
-	u32 firctrimh;
-	u32 fircstat;	/*  Fast IRC Status Register */
-	u32 firctest;	/*  Fast IRC Test Register */
-	u32 rsvd40[56];
-
-	u32 rtccsr;	/*  RTC OSC Control Status Register, offset 0x400 */
-	u32 rsvd50[63];
-
-	u32 apllcsr; /*  Auxiliary PLL Control Status Register, offset 0x500 */
-	u32 aplldiv;	/*  Auxiliary PLL Divider Register */
-	u32 apllcfg;	/*  Auxiliary PLL Configuration Register */
-	u32 apllpfd;	/*  Auxiliary PLL PFD Register */
-	u32 apllnum;	/*  Auxiliary PLL Numerator Register */
-	u32 aplldenom;	/*  Auxiliary PLL Denominator Register */
-	u32 apllss;	/*  Auxiliary PLL Spread Spectrum Register */
-	u32 rsvd60[55];
-	u32 apllock_cnfg; /*  Auxiliary PLL LOCK Configuration Register */
-	u32 rsvd61[1];
-
-	u32 spllcsr;	/*  System PLL Control Status Register, offset 0x600 */
-	u32 splldiv;	/*  System PLL Divide Register */
-	u32 spllcfg;	/*  System PLL Configuration Register */
-	u32 spllpfd;	/*  System PLL Test Register */
-	u32 spllnum;	/*  System PLL Numerator Register */
-	u32 splldenom;	/*  System PLL Denominator Register */
-	u32 spllss;	/*  System PLL Spread Spectrum Register */
-	u32 rsvd70[55];
-	u32 spllock_cnfg;	/*  System PLL LOCK Configuration Register */
-	u32 rsvd71[1];
-
-	u32 upllcsr;	/*  USB PLL Control Status Register, offset 0x700 */
-	u32 uplldiv;	/*  USB PLL Divide Register */
-	u32 upllcfg;	/*  USB PLL Configuration Register */
-} scg_t, *scg_p;
-
-u32 scg_clk_get_rate(enum scg_clk clk);
-int scg_enable_pll_pfd(enum scg_clk clk, u32 frac);
-int scg_enable_usb_pll(bool usb_control);
-u32 decode_pll(enum pll_clocks pll);
-
-void scg_a7_rccr_init(void);
-void scg_a7_spll_init(void);
-void scg_a7_ddrclk_init(void);
-void scg_a7_apll_init(void);
-void scg_a7_firc_init(void);
-void scg_a7_nicclk_init(void);
-void scg_a7_sys_clk_sel(enum scg_sys_src clk);
-void scg_a7_info(void);
-void scg_a7_soscdiv_init(void);
-void scg_a7_init_core_clk(void);
-
-#endif
diff --git a/include/bootcount.h b/include/bootcount.h
deleted file mode 100644
index 8fa8cf8..0000000
--- a/include/bootcount.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2012
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- */
-#ifndef _BOOTCOUNT_H__
-#define _BOOTCOUNT_H__
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/byteorder.h>
-#include <env.h>
-
-#ifdef CONFIG_DM_BOOTCOUNT
-
-struct bootcount_ops {
-	/**
-	 * get() - get the current bootcount value
-	 *
-	 * Returns the current counter value of the bootcount backing
-	 * store.
-	 *
-	 * @dev:	Device to read from
-	 * @bootcount:	Address to put the current bootcount value
-	 */
-	int (*get)(struct udevice *dev, u32 *bootcount);
-
-	/**
-	 * set() - set a bootcount value (e.g. to reset or increment)
-	 *
-	 * Sets the value in the bootcount backing store.
-	 *
-	 * @dev:	Device to read from
-	 * @bootcount:	New bootcount value to store
-	 */
-	int (*set)(struct udevice *dev, const u32 bootcount);
-};
-
-/* Access the operations for a bootcount device */
-#define bootcount_get_ops(dev)	((struct bootcount_ops *)(dev)->driver->ops)
-
-/**
- * dm_bootcount_get() - Read the current value from a bootcount storage
- *
- * @dev:	Device to read from
- * @bootcount:	Place to put the current bootcount
- * @return 0 if OK, -ve on error
- */
-int dm_bootcount_get(struct udevice *dev, u32 *bootcount);
-
-/**
- * dm_bootcount_set() - Write a value to a bootcount storage
- *
- * @dev:	Device to read from
- * @bootcount:  Value to be written to the backing storage
- * @return 0 if OK, -ve on error
- */
-int dm_bootcount_set(struct udevice *dev, u32 bootcount);
-
-#endif
-
-#if defined(CONFIG_SPL_BOOTCOUNT_LIMIT) || defined(CONFIG_BOOTCOUNT_LIMIT)
-
-#if !defined(CONFIG_SYS_BOOTCOUNT_LE) && !defined(CONFIG_SYS_BOOTCOUNT_BE)
-# if __BYTE_ORDER == __LITTLE_ENDIAN
-#  define CONFIG_SYS_BOOTCOUNT_LE
-# else
-#  define CONFIG_SYS_BOOTCOUNT_BE
-# endif
-#endif
-
-#ifdef CONFIG_SYS_BOOTCOUNT_LE
-static inline void raw_bootcount_store(volatile u32 *addr, u32 data)
-{
-	out_le32(addr, data);
-}
-
-static inline u32 raw_bootcount_load(volatile u32 *addr)
-{
-	return in_le32(addr);
-}
-#else
-static inline void raw_bootcount_store(volatile u32 *addr, u32 data)
-{
-	out_be32(addr, data);
-}
-
-static inline u32 raw_bootcount_load(volatile u32 *addr)
-{
-	return in_be32(addr);
-}
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-static inline int bootcount_error(void)
-{
-	unsigned long bootcount = bootcount_load();
-	unsigned long bootlimit = env_get_ulong("bootlimit", 10, 0);
-
-	if (bootlimit && bootcount > bootlimit) {
-		printf("Warning: Bootlimit (%lu) exceeded.", bootlimit);
-		if (!(gd->flags & GD_FLG_SPL_INIT))
-			printf(" Using altbootcmd.");
-		printf("\n");
-
-		return 1;
-	}
-
-	return 0;
-}
-
-static inline void bootcount_inc(void)
-{
-	unsigned long bootcount = bootcount_load();
-
-	if (gd->flags & GD_FLG_SPL_INIT) {
-		bootcount_store(++bootcount);
-		return;
-	}
-
-#ifndef CONFIG_SPL_BUILD
-	/* Only increment bootcount when no bootcount support in SPL */
-#ifndef CONFIG_SPL_BOOTCOUNT_LIMIT
-	bootcount_store(++bootcount);
-#endif
-	env_set_ulong("bootcount", bootcount);
-#endif /* !CONFIG_SPL_BUILD */
-}
-
-#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_BOOTCOUNT_LIMIT)
-void bootcount_store(ulong a) {};
-ulong bootcount_load(void) { return 0; }
-#endif /* CONFIG_SPL_BUILD && !CONFIG_SPL_BOOTCOUNT_LIMIT */
-#else
-static inline int bootcount_error(void) { return 0; }
-static inline void bootcount_inc(void) {}
-#endif /* CONFIG_SPL_BOOTCOUNT_LIMIT || CONFIG_BOOTCOUNT_LIMIT */
-#endif /* _BOOTCOUNT_H__ */
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
deleted file mode 100644
index 121de2b..0000000
--- a/include/configs/tam3517-common.h
+++ /dev/null
@@ -1,326 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * Copyright (C) 2009 TechNexion Ltd.
- */
-
-#ifndef __TAM3517_H
-#define __TAM3517_H
-
-/*
- * High Level Configuration Options
- */
-
-#include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap.h>
-
-/* Clock Defines */
-#define V_OSCK			26000000	/* Clock output from T2 */
-#define V_SCLK			(V_OSCK >> 1)
-
-#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10) + \
-					2 * 1024 * 1024)
-/*
- * DDR related
- */
-#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
-
-/*
- * Hardware drivers
- */
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
-					115200}
-/* EHCI */
-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	25
-
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
-
-/*
- * Board NAND Info.
- */
-#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
-							/* to access */
-							/* nand at CS0 */
-
-#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
-							/* NAND devices */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
-
-#define CONFIG_SYS_MAXARGS		32	/* max number of command */
-						/* args */
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
-#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
-					0x01F00000) /* 31MB */
-
-#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
-								/* address */
-
-/*
- * AM3517 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
-#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
-
-/*
- * Physical Memory Map
- */
-#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
-
-/*
- * FLASH and environment organization
- */
-
-/* **** PISMO SUPPORT *** */
-
-/* Redundant Environment */
-#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
-#define CONFIG_ENV_OFFSET		0x180000
-#define CONFIG_ENV_ADDR			0x180000
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
-						2 * CONFIG_SYS_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
-#define CONFIG_SYS_INIT_RAM_SIZE	0x800
-#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - \
-					 GENERATED_GBL_DATA_SIZE)
-
-/*
- * ethernet support, EMAC
- *
- */
-#define CONFIG_DRIVER_TI_EMAC_USE_RMII
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_NET_RETRY_COUNT 10
-
-/* Defines for SPL */
-#define CONFIG_SPL_CONSOLE
-#define CONFIG_SPL_NAND_SOFTECC
-#define CONFIG_SPL_NAND_WORKSPACE	0x8f07f000 /* below BSS */
-
-#define CONFIG_SPL_NAND_BASE
-#define CONFIG_SPL_NAND_DRIVERS
-#define CONFIG_SPL_NAND_ECC
-
-#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
-					 CONFIG_SPL_TEXT_BASE)
-#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
-
-#define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
-#define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
-#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
-
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
-
-/* FAT */
-#define CONFIG_SPL_FS_LOAD_KERNEL_NAME		"uImage"
-#define CONFIG_SPL_FS_LOAD_ARGS_NAME		"args"
-
-/* RAW SD card / eMMC */
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */
-
-/* NAND boot config */
-#define CONFIG_SYS_NAND_PAGE_COUNT	64
-#define CONFIG_SYS_NAND_PAGE_SIZE	2048
-#define CONFIG_SYS_NAND_OOBSIZE		64
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
-#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
-					 48, 49, 50, 51, 52, 53, 54, 55,\
-					 56, 57, 58, 59, 60, 61, 62, 63}
-#define CONFIG_SYS_NAND_ECCSIZE		256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW
-
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
-
-/* Setup MTD for NAND on the SOM */
-
-#define	CONFIG_TAM3517_SETTINGS						\
-	"netdev=eth0\0"							\
-	"nandargs=setenv bootargs root=${nandroot} "			\
-		"rootfstype=${nandrootfstype}\0"			\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip_sta=setenv bootargs ${bootargs} "			\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
-	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
-		"else run addip_sta;fi\0"				\
-	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
-	"addtty=setenv bootargs ${bootargs}"				\
-		" console=ttyO0,${baudrate}\0"				\
-	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
-	"loadaddr=82000000\0"						\
-	"kernel_addr_r=82000000\0"					\
-	"hostname=" CONFIG_HOSTNAME "\0"			\
-	"bootfile=" CONFIG_HOSTNAME "/uImage\0"		\
-	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
-		"bootm ${kernel_addr}\0"				\
-	"nandboot=run nandargs addip addtty addmtd addmisc;"		\
-		"nand read ${kernel_addr_r} kernel\0"			\
-		"bootm ${kernel_addr_r}\0"				\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
-		"run nfsargs addip addtty addmtd addmisc;"		\
-		"bootm ${kernel_addr_r}\0"				\
-	"net_self=if run net_self_load;then "				\
-		"run ramargs addip addtty addmtd addmisc;"		\
-		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
-		"else echo Images not loades;fi\0"			\
-	"u-boot=" CONFIG_HOSTNAME "/u-boot.img\0"		\
-	"load=tftp ${loadaddr} ${u-boot}\0"				\
-	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
-	"mlo=" CONFIG_HOSTNAME "/MLO\0"			\
-	"uboot_addr=0x80000\0"						\
-	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
-		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
-	"updatemlo=nandecc hw;nand erase 0 20000;"			\
-		"nand write ${loadaddr} 0 20000\0"			\
-	"upd=if run load;then echo Updating u-boot;if run update;"	\
-		"then echo U-Boot updated;"				\
-			"else echo Error updating u-boot !;"		\
-			"echo Board without bootloader !!;"		\
-		"fi;"							\
-		"else echo U-Boot not downloaded..exiting;fi\0"		\
-
-/*
- * this is common code for all TAM3517 boards.
- * MAC address is stored from manufacturer in
- * I2C EEPROM
- */
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-/*
- * The I2C EEPROM on the TAM3517 contains
- * mac address and production data
- */
-struct tam3517_module_info {
-	char customer[48];
-	char product[48];
-
-	/*
-	 * bit 0~47  : sequence number
-	 * bit 48~55 : week of year, from 0.
-	 * bit 56~63 : year
-	 */
-	unsigned long long sequence_number;
-
-	/*
-	 * bit 0~7   : revision fixed
-	 * bit 8~15  : revision major
-	 * bit 16~31 : TNxxx
-	 */
-	unsigned int revision;
-	unsigned char eth_addr[4][8];
-	unsigned char _rev[100];
-};
-
-#define TAM3517_READ_EEPROM(info, ret) \
-do {								\
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
-	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,		\
-		(void *)info, sizeof(*info)))			\
-		ret = 1;					\
-	else							\
-		ret = 0;					\
-} while (0)
-
-#define TAM3517_READ_MAC_FROM_EEPROM(info)			\
-do {								\
-	char buf[80], ethname[20];				\
-	int i;							\
-	memset(buf, 0, sizeof(buf));				\
-	for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) {	\
-		sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X",	\
-			(info)->eth_addr[i][5],			\
-			(info)->eth_addr[i][4],			\
-			(info)->eth_addr[i][3],			\
-			(info)->eth_addr[i][2],			\
-			(info)->eth_addr[i][1],			\
-			(info)->eth_addr[i][0]);			\
-								\
-		if (i)						\
-			sprintf(ethname, "eth%daddr", i);	\
-		else						\
-			strcpy(ethname, "ethaddr");		\
-		printf("Setting %s from EEPROM with %s\n", ethname, buf);\
-		env_set(ethname, buf);				\
-	}							\
-} while (0)
-
-/* The following macros are taken from Technexion's documentation */
-#define TAM3517_sequence_number(info) \
-	((info)->sequence_number % 0x1000000000000LL)
-#define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
-#define TAM3517_year(info) ((info)->sequence_number >> 56)
-#define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
-#define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
-#define TAM3517_revision_tn(info) ((info)->revision >> 16)
-
-#define TAM3517_PRINT_SOM_INFO(info)				\
-do {								\
-	printf("Vendor:%s\n", (info)->customer);		\
-	printf("SOM:   %s\n", (info)->product);			\
-	printf("SeqNr: %02llu%02llu%012llu\n",			\
-		TAM3517_year(info),				\
-		TAM3517_week_of_year(info),			\
-		TAM3517_sequence_number(info));			\
-	printf("Rev:   TN%u %u.%u\n",				\
-		TAM3517_revision_tn(info),			\
-		TAM3517_revision_major(info),			\
-		TAM3517_revision_fixed(info));			\
-} while (0)
-
-#endif
-
-#endif /* __TAM3517_H */
diff --git a/include/efi_selftest.h b/include/efi_selftest.h
deleted file mode 100644
index eaee188..0000000
--- a/include/efi_selftest.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *  EFI application loader
- *
- *  Copyright (c) 2017 Heinrich Schuchardt <xypron.glpk@gmx.de>
- */
-
-#ifndef _EFI_SELFTEST_H
-#define _EFI_SELFTEST_H
-
-#include <common.h>
-#include <efi.h>
-#include <efi_api.h>
-#include <efi_loader.h>
-#include <linker_lists.h>
-
-#define EFI_ST_SUCCESS 0
-#define EFI_ST_FAILURE 1
-#define EFI_ST_SUCCESS_STR L"SUCCESS"
-/*
- * Prints a message.
- */
-#define efi_st_printf(...) \
-	(efi_st_printc(-1, __VA_ARGS__))
-
-/*
- * Prints an error message.
- *
- * @...	format string followed by fields to print
- */
-#define efi_st_error(...) \
-	(efi_st_printc(EFI_LIGHTRED, "%s(%u):\nERROR: ", __FILE__, __LINE__), \
-	efi_st_printc(EFI_LIGHTRED, __VA_ARGS__))
-
-/*
- * Prints a TODO message.
- *
- * @...	format string followed by fields to print
- */
-#define efi_st_todo(...) \
-	(efi_st_printc(EFI_YELLOW, "%s(%u):\nTODO: ", __FILE__, __LINE__), \
-	efi_st_printc(EFI_YELLOW, __VA_ARGS__)) \
-
-/*
- * A test may be setup and executed at boottime,
- * it may be setup at boottime and executed at runtime,
- * or it may be setup and executed at runtime.
- */
-enum efi_test_phase {
-	EFI_EXECUTE_BEFORE_BOOTTIME_EXIT = 1,
-	EFI_SETUP_BEFORE_BOOTTIME_EXIT,
-	EFI_SETUP_AFTER_BOOTTIME_EXIT,
-};
-
-extern struct efi_simple_text_output_protocol *con_out;
-extern struct efi_simple_text_input_protocol *con_in;
-
-/*
- * Exit the boot services.
- *
- * The size of the memory map is determined.
- * Pool memory is allocated to copy the memory map.
- * The memory amp is copied and the map key is obtained.
- * The map key is used to exit the boot services.
- */
-void efi_st_exit_boot_services(void);
-
-/*
- * Print a colored message
- *
- * @color	color, see constants in efi_api.h, use -1 for no color
- * @fmt		printf format
- * @...		arguments to be printed
- *		on return position of terminating zero word
- */
-void efi_st_printc(int color, const char *fmt, ...)
-		 __attribute__ ((format (__printf__, 2, 3)));
-
-/**
- * efi_st_translate_char() - translate a unicode character to a string
- *
- * @code:	unicode character
- * Return:	string
- */
-u16 *efi_st_translate_char(u16 code);
-
-/**
- * efi_st_translate_code() - translate a scan code to a human readable string
- *
- * @code:	unicode character
- * Return:	string
- */
-u16 *efi_st_translate_code(u16 code);
-
-/*
- * Compare an u16 string to a char string.
- *
- * @buf1:	u16 string
- * @buf2:	char string
- * @return:	0 if both buffers contain the same bytes
- */
-int efi_st_strcmp_16_8(const u16 *buf1, const char *buf2);
-
-/*
- * Reads an Unicode character from the input device.
- *
- * @return: Unicode character
- */
-u16 efi_st_get_key(void);
-
-/**
- * struct efi_unit_test - EFI unit test
- *
- * An efi_unit_test provides a interface to an EFI unit test.
- *
- * @name:	name of unit test
- * @phase:	specifies when setup and execute are executed
- * @setup:	set up the unit test
- * @teardown:	tear down the unit test
- * @execute:	execute the unit test
- * @on_request:	test is only executed on request
- */
-struct efi_unit_test {
-	const char *name;
-	const enum efi_test_phase phase;
-	int (*setup)(const efi_handle_t handle,
-		     const struct efi_system_table *systable);
-	int (*execute)(void);
-	int (*teardown)(void);
-	bool on_request;
-};
-
-/* Declare a new EFI unit test */
-#define EFI_UNIT_TEST(__name)						\
-	ll_entry_declare(struct efi_unit_test, __name, efi_unit_test)
-
-#endif /* _EFI_SELFTEST_H */
diff --git a/include/stdio.h b/include/stdio.h
index a18aab0..d5a5928 100644
--- a/include/stdio.h
+++ b/include/stdio.h
@@ -13,18 +13,9 @@ int tstc(void);
 	(defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_SERIAL_SUPPORT)) || \
 	(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) && \
 		defined(CONFIG_SPL_SERIAL_SUPPORT))
-void putc(const char c);
-void puts(const char *s);
 int __printf(1, 2) printf(const char *fmt, ...);
 int vprintf(const char *fmt, va_list args);
 #else
-static inline void putc(const char c)
-{
-}
-
-static inline void puts(const char *s)
-{
-}
 
 static inline int __printf(1, 2) printf(const char *fmt, ...)
 {
@@ -45,10 +36,4 @@ static inline int vprintf(const char *fmt, va_list args)
 #define stderr		2
 #define MAX_FILES	3
 
-int __printf(2, 3) fprintf(int file, const char *fmt, ...);
-void fputs(int file, const char *s);
-void fputc(int file, const char c);
-int ftstc(int file);
-int fgetc(int file);
-
 #endif /* __STDIO_H */