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authorIru Cai <mytbk920423@gmail.com>2019-10-30 15:42:15 +0800
committerIru Cai <mytbk920423@gmail.com>2019-10-30 15:42:15 +0800
commit1a691f101632955a994a0198fc5498b108e97fbc (patch)
tree04903c08c0d9f60460451188d026cf50bee1651b /include/configs/ti_armv7_omap.h
parent08dd4564b1f5c3258caf6bfc4bdc77ead1b042d6 (diff)
downloaduext4-1a691f101632955a994a0198fc5498b108e97fbc.tar.xz
rm include/configs
Diffstat (limited to 'include/configs/ti_armv7_omap.h')
-rw-r--r--include/configs/ti_armv7_omap.h28
1 files changed, 0 insertions, 28 deletions
diff --git a/include/configs/ti_armv7_omap.h b/include/configs/ti_armv7_omap.h
deleted file mode 100644
index 98b5839..0000000
--- a/include/configs/ti_armv7_omap.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * ti_armv7_omap.h
- *
- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
- *
- * The various ARMv7 SoCs from TI all share a number of IP blocks when
- * implementing a given feature. This is meant to isolate the features
- * that are based on OMAP architecture.
- */
-#ifndef __CONFIG_TI_ARMV7_OMAP_H__
-#define __CONFIG_TI_ARMV7_OMAP_H__
-
-/*
- * GPMC NAND block. We support 1 device and the physical address to
- * access CS0 at is 0x8000000.
- */
-#ifdef CONFIG_NAND
-#ifndef CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_NAND_BASE 0x8000000
-#endif
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#endif
-
-/* Now for the remaining common defines */
-#include <configs/ti_armv7_common.h>
-
-#endif /* __CONFIG_TI_ARMV7_OMAP_H__ */