diff options
Diffstat (limited to 'arch/arm/include/asm/arch-aspeed')
| -rw-r--r-- | arch/arm/include/asm/arch-aspeed/pinctrl.h | 51 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 247 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-aspeed/sdram_ast2500.h | 137 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-aspeed/timer.h | 53 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-aspeed/wdt.h | 113 |
5 files changed, 0 insertions, 601 deletions
diff --git a/arch/arm/include/asm/arch-aspeed/pinctrl.h b/arch/arm/include/asm/arch-aspeed/pinctrl.h deleted file mode 100644 index dd85464..0000000 --- a/arch/arm/include/asm/arch-aspeed/pinctrl.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2017 Google, Inc - */ -#ifndef _ASM_ARCH_PERIPH_H -#define _ASM_ARCH_PERIPH_H - -/* - * Peripherals supported by the hardware. - * These are used to specify pinctrl settings. - */ - -enum periph_id { - PERIPH_ID_UART1, - PERIPH_ID_UART2, - PERIPH_ID_UART3, - PERIPH_ID_UART4, - PERIPH_ID_LPC, - PERIPH_ID_PWM0, - PERIPH_ID_PWM1, - PERIPH_ID_PWM2, - PERIPH_ID_PWM3, - PERIPH_ID_PWM4, - PERIPH_ID_PWM5, - PERIPH_ID_PWM6, - PERIPH_ID_PWM7, - PERIPH_ID_PWM8, - PERIPH_ID_MAC1, - PERIPH_ID_MAC2, - PERIPH_ID_VIDEO, - PERIPH_ID_SPI1, - PERIPH_ID_SPI2, - PERIPH_ID_I2C1, - PERIPH_ID_I2C2, - PERIPH_ID_I2C3, - PERIPH_ID_I2C4, - PERIPH_ID_I2C5, - PERIPH_ID_I2C6, - PERIPH_ID_I2C7, - PERIPH_ID_I2C8, - PERIPH_ID_I2C9, - PERIPH_ID_I2C10, - PERIPH_ID_I2C11, - PERIPH_ID_I2C12, - PERIPH_ID_I2C13, - PERIPH_ID_I2C14, - PERIPH_ID_SD1, - PERIPH_ID_SD2, -}; - -#endif /* _ASM_ARCH_SCU_AST2500_H */ diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h deleted file mode 100644 index 8db4901..0000000 --- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h +++ /dev/null @@ -1,247 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2016 Google, Inc - */ -#ifndef _ASM_ARCH_SCU_AST2500_H -#define _ASM_ARCH_SCU_AST2500_H - -#define SCU_UNLOCK_VALUE 0x1688a8a8 - -#define SCU_HWSTRAP_VGAMEM_SHIFT 2 -#define SCU_HWSTRAP_VGAMEM_MASK (3 << SCU_HWSTRAP_VGAMEM_SHIFT) -#define SCU_HWSTRAP_MAC1_RGMII (1 << 6) -#define SCU_HWSTRAP_MAC2_RGMII (1 << 7) -#define SCU_HWSTRAP_DDR4 (1 << 24) -#define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23) - -#define SCU_MPLL_DENUM_SHIFT 0 -#define SCU_MPLL_DENUM_MASK 0x1f -#define SCU_MPLL_NUM_SHIFT 5 -#define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT) -#define SCU_MPLL_POST_SHIFT 13 -#define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT) -#define SCU_PCLK_DIV_SHIFT 23 -#define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT) -#define SCU_SDCLK_DIV_SHIFT 12 -#define SCU_SDCLK_DIV_MASK (7 << SCU_SDCLK_DIV_SHIFT) -#define SCU_HPLL_DENUM_SHIFT 0 -#define SCU_HPLL_DENUM_MASK 0x1f -#define SCU_HPLL_NUM_SHIFT 5 -#define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT) -#define SCU_HPLL_POST_SHIFT 13 -#define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT) - -#define SCU_MACCLK_SHIFT 16 -#define SCU_MACCLK_MASK (7 << SCU_MACCLK_SHIFT) - -#define SCU_MISC2_RGMII_HPLL (1 << 23) -#define SCU_MISC2_RGMII_CLKDIV_SHIFT 20 -#define SCU_MISC2_RGMII_CLKDIV_MASK (3 << SCU_MISC2_RGMII_CLKDIV_SHIFT) -#define SCU_MISC2_RMII_MPLL (1 << 19) -#define SCU_MISC2_RMII_CLKDIV_SHIFT 16 -#define SCU_MISC2_RMII_CLKDIV_MASK (3 << SCU_MISC2_RMII_CLKDIV_SHIFT) -#define SCU_MISC2_UARTCLK_SHIFT 24 - -#define SCU_MISC_D2PLL_OFF (1 << 4) -#define SCU_MISC_UARTCLK_DIV13 (1 << 12) -#define SCU_MISC_GCRT_USB20CLK (1 << 21) - -#define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT 0 -#define SCU_MICDS_MAC1RGMII_TXDLY_MASK (0x3f\ - << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT) -#define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT 6 -#define SCU_MICDS_MAC2RGMII_TXDLY_MASK (0x3f\ - << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT) -#define SCU_MICDS_MAC1RMII_RDLY_SHIFT 12 -#define SCU_MICDS_MAC1RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT) -#define SCU_MICDS_MAC2RMII_RDLY_SHIFT 18 -#define SCU_MICDS_MAC2RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT) -#define SCU_MICDS_MAC1RMII_TXFALL (1 << 24) -#define SCU_MICDS_MAC2RMII_TXFALL (1 << 25) -#define SCU_MICDS_RMII1_RCLKEN (1 << 29) -#define SCU_MICDS_RMII2_RCLKEN (1 << 30) -#define SCU_MICDS_RGMIIPLL (1 << 31) - -/* - * SYSRESET is actually more like a Power register, - * except that corresponding bit set to 1 means that - * the peripheral is off. - */ -#define SCU_SYSRESET_XDMA (1 << 25) -#define SCU_SYSRESET_MCTP (1 << 24) -#define SCU_SYSRESET_ADC (1 << 23) -#define SCU_SYSRESET_JTAG (1 << 22) -#define SCU_SYSRESET_MIC (1 << 18) -#define SCU_SYSRESET_SDIO (1 << 16) -#define SCU_SYSRESET_USB11HOST (1 << 15) -#define SCU_SYSRESET_USBHUB (1 << 14) -#define SCU_SYSRESET_CRT (1 << 13) -#define SCU_SYSRESET_MAC2 (1 << 12) -#define SCU_SYSRESET_MAC1 (1 << 11) -#define SCU_SYSRESET_PECI (1 << 10) -#define SCU_SYSRESET_PWM (1 << 9) -#define SCU_SYSRESET_PCI_VGA (1 << 8) -#define SCU_SYSRESET_2D (1 << 7) -#define SCU_SYSRESET_VIDEO (1 << 6) -#define SCU_SYSRESET_LPC (1 << 5) -#define SCU_SYSRESET_HAC (1 << 4) -#define SCU_SYSRESET_USBHID (1 << 3) -#define SCU_SYSRESET_I2C (1 << 2) -#define SCU_SYSRESET_AHB (1 << 1) -#define SCU_SYSRESET_SDRAM_WDT (1 << 0) - -/* Bits 16-27 in the register control pin functions for I2C devices 3-14 */ -#define SCU_PINMUX_CTRL5_I2C (1 << 16) - -/* - * The values are grouped by function, not by register. - * They are actually scattered across multiple loosely related registers. - */ -#define SCU_PIN_FUN_MAC1_MDC (1 << 30) -#define SCU_PIN_FUN_MAC1_MDIO (1 << 31) -#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0) -#define SCU_PIN_FUN_MAC2_MDIO (1 << 2) -#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1) -#define SCU_PIN_FUN_SCL1 (1 << 12) -#define SCU_PIN_FUN_SCL2 (1 << 14) -#define SCU_PIN_FUN_SDA1 (1 << 13) -#define SCU_PIN_FUN_SDA2 (1 << 15) - -#define SCU_CLKSTOP_MAC1 (1 << 20) -#define SCU_CLKSTOP_MAC2 (1 << 21) -#define SCU_CLKSTOP_SDCLK (1 << 27) - -#define SCU_D2PLL_EXT1_OFF (1 << 0) -#define SCU_D2PLL_EXT1_BYPASS (1 << 1) -#define SCU_D2PLL_EXT1_RESET (1 << 2) -#define SCU_D2PLL_EXT1_MODE_SHIFT 3 -#define SCU_D2PLL_EXT1_MODE_MASK (3 << SCU_D2PLL_EXT1_MODE_SHIFT) -#define SCU_D2PLL_EXT1_PARAM_SHIFT 5 -#define SCU_D2PLL_EXT1_PARAM_MASK (0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT) - -#define SCU_D2PLL_NUM_SHIFT 0 -#define SCU_D2PLL_NUM_MASK (0xff << SCU_D2PLL_NUM_SHIFT) -#define SCU_D2PLL_DENUM_SHIFT 8 -#define SCU_D2PLL_DENUM_MASK (0x1f << SCU_D2PLL_DENUM_SHIFT) -#define SCU_D2PLL_POST_SHIFT 13 -#define SCU_D2PLL_POST_MASK (0x3f << SCU_D2PLL_POST_SHIFT) -#define SCU_D2PLL_ODIV_SHIFT 19 -#define SCU_D2PLL_ODIV_MASK (7 << SCU_D2PLL_ODIV_SHIFT) -#define SCU_D2PLL_SIC_SHIFT 22 -#define SCU_D2PLL_SIC_MASK (0x1f << SCU_D2PLL_SIC_SHIFT) -#define SCU_D2PLL_SIP_SHIFT 27 -#define SCU_D2PLL_SIP_MASK (0x1f << SCU_D2PLL_SIP_SHIFT) - -#define SCU_CLKDUTY_DCLK_SHIFT 0 -#define SCU_CLKDUTY_DCLK_MASK (0x3f << SCU_CLKDUTY_DCLK_SHIFT) -#define SCU_CLKDUTY_RGMII1TXCK_SHIFT 8 -#define SCU_CLKDUTY_RGMII1TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII1TXCK_SHIFT) -#define SCU_CLKDUTY_RGMII2TXCK_SHIFT 16 -#define SCU_CLKDUTY_RGMII2TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII2TXCK_SHIFT) - -#ifndef __ASSEMBLY__ - -struct ast2500_clk_priv { - struct ast2500_scu *scu; -}; - -struct ast2500_scu { - u32 protection_key; - u32 sysreset_ctrl1; - u32 clk_sel1; - u32 clk_stop_ctrl1; - u32 freq_counter_ctrl; - u32 freq_counter_cmp; - u32 intr_ctrl; - u32 d2_pll_param; - u32 m_pll_param; - u32 h_pll_param; - u32 d_pll_param; - u32 misc_ctrl1; - u32 pci_config[3]; - u32 sysreset_status; - u32 vga_handshake[2]; - u32 mac_clk_delay; - u32 misc_ctrl2; - u32 vga_scratch[8]; - u32 hwstrap; - u32 rng_ctrl; - u32 rng_data; - u32 rev_id; - u32 pinmux_ctrl[6]; - u32 reserved0; - u32 extrst_sel; - u32 pinmux_ctrl1[4]; - u32 reserved1[2]; - u32 mac_clk_delay_100M; - u32 mac_clk_delay_10M; - u32 wakeup_enable; - u32 wakeup_control; - u32 reserved2[3]; - u32 sysreset_ctrl2; - u32 clk_sel2; - u32 clk_stop_ctrl2; - u32 freerun_counter; - u32 freerun_counter_ext; - u32 clk_duty_meas_ctrl; - u32 clk_duty_meas_res; - u32 reserved3[4]; - /* The next registers are not key-protected */ - struct ast2500_cpu2 { - u32 ctrl; - u32 base_addr[9]; - u32 cache_ctrl; - } cpu2; - u32 reserved4; - u32 d_pll_ext_param[3]; - u32 d2_pll_ext_param[3]; - u32 mh_pll_ext_param; - u32 reserved5; - u32 chip_id[2]; - u32 reserved6[2]; - u32 uart_clk_ctrl; - u32 reserved7[7]; - u32 pcie_config; - u32 mmio_decode; - u32 reloc_ctrl_decode[2]; - u32 mailbox_addr; - u32 shared_sram_decode[2]; - u32 bmc_rev_id; - u32 reserved8; - u32 bmc_device_id; - u32 reserved9[13]; - u32 clk_duty_sel; -}; - -/** - * ast_get_clk() - get a pointer to Clock Driver - * - * @devp, OUT - pointer to Clock Driver - * @return zero on success, error code (< 0) otherwise. - */ -int ast_get_clk(struct udevice **devp); - -/** - * ast_get_scu() - get a pointer to SCU registers - * - * @return pointer to struct ast2500_scu on success, ERR_PTR otherwise - */ -void *ast_get_scu(void); - -/** - * ast_scu_unlock() - unlock protected registers - * - * @scu, pointer to ast2500_scu - */ -void ast_scu_unlock(struct ast2500_scu *scu); - -/** - * ast_scu_lock() - lock protected registers - * - * @scu, pointer to ast2500_scu - */ -void ast_scu_lock(struct ast2500_scu *scu); - -#endif /* __ASSEMBLY__ */ - -#endif /* _ASM_ARCH_SCU_AST2500_H */ diff --git a/arch/arm/include/asm/arch-aspeed/sdram_ast2500.h b/arch/arm/include/asm/arch-aspeed/sdram_ast2500.h deleted file mode 100644 index 0bc551f..0000000 --- a/arch/arm/include/asm/arch-aspeed/sdram_ast2500.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2016 Google, Inc - */ -#ifndef _ASM_ARCH_SDRAM_AST2500_H -#define _ASM_ARCH_SDRAM_AST2500_H - -#define SDRAM_UNLOCK_KEY 0xfc600309 -#define SDRAM_VIDEO_UNLOCK_KEY 0x2003000f - -#define SDRAM_PCR_CKE_EN (1 << 0) -#define SDRAM_PCR_AUTOPWRDN_EN (1 << 1) -#define SDRAM_PCR_CKE_DELAY_SHIFT 4 -#define SDRAM_PCR_CKE_DELAY_MASK 7 -#define SDRAM_PCR_RESETN_DIS (1 << 7) -#define SDRAM_PCR_ODT_EN (1 << 8) -#define SDRAM_PCR_ODT_AUTO_ON (1 << 10) -#define SDRAM_PCR_ODT_EXT_EN (1 << 11) -#define SDRAM_PCR_TCKE_PW_SHIFT 12 -#define SDRAM_PCR_TCKE_PW_MASK 7 -#define SDRAM_PCR_RGAP_CTRL_EN (1 << 15) -#define SDRAM_PCR_MREQI_DIS (1 << 17) - -/* Fixed priority DRAM Requests mask */ -#define SDRAM_REQ_VGA_HW_CURSOR (1 << 0) -#define SDRAM_REQ_VGA_TEXT_CG_FONT (1 << 1) -#define SDRAM_REQ_VGA_TEXT_ASCII (1 << 2) -#define SDRAM_REQ_VGA_CRT (1 << 3) -#define SDRAM_REQ_SOC_DC_CURSOR (1 << 4) -#define SDRAM_REQ_SOC_DC_OCD (1 << 5) -#define SDRAM_REQ_SOC_DC_CRT (1 << 6) -#define SDRAM_REQ_VIDEO_HIPRI_WRITE (1 << 7) -#define SDRAM_REQ_USB20_EHCI1 (1 << 8) -#define SDRAM_REQ_USB20_EHCI2 (1 << 9) -#define SDRAM_REQ_CPU (1 << 10) -#define SDRAM_REQ_AHB2 (1 << 11) -#define SDRAM_REQ_AHB (1 << 12) -#define SDRAM_REQ_MAC0 (1 << 13) -#define SDRAM_REQ_MAC1 (1 << 14) -#define SDRAM_REQ_PCIE (1 << 16) -#define SDRAM_REQ_XDMA (1 << 17) -#define SDRAM_REQ_ENCRYPTION (1 << 18) -#define SDRAM_REQ_VIDEO_FLAG (1 << 21) -#define SDRAM_REQ_VIDEO_LOW_PRI_WRITE (1 << 28) -#define SDRAM_REQ_2D_RW (1 << 29) -#define SDRAM_REQ_MEMCHECK (1 << 30) - -#define SDRAM_ICR_RESET_ALL (1 << 31) - -#define SDRAM_CONF_CAP_SHIFT 0 -#define SDRAM_CONF_CAP_MASK 3 -#define SDRAM_CONF_DDR4 (1 << 4) -#define SDRAM_CONF_SCRAMBLE (1 << 8) -#define SDRAM_CONF_SCRAMBLE_PAT2 (1 << 9) -#define SDRAM_CONF_CACHE_EN (1 << 10) -#define SDRAM_CONF_CACHE_INIT_EN (1 << 12) -#define SDRAM_CONF_DUALX8 (1 << 13) -#define SDRAM_CONF_CACHE_INIT_DONE (1 << 19) - -#define SDRAM_CONF_CAP_128M 0 -#define SDRAM_CONF_CAP_256M 1 -#define SDRAM_CONF_CAP_512M 2 -#define SDRAM_CONF_CAP_1024M 3 - -#define SDRAM_MISC_DDR4_TREFRESH (1 << 3) - -#define SDRAM_PHYCTRL0_INIT (1 << 0) -#define SDRAM_PHYCTRL0_AUTO_UPDATE (1 << 1) -#define SDRAM_PHYCTRL0_NRST (1 << 2) - -#define SDRAM_REFRESH_CYCLES_SHIFT 0 -#define SDRAM_REFRESH_CYCLES_MASK 0xf -#define SDRAM_REFRESH_ZQCS_EN (1 << 7) -#define SDRAM_REFRESH_PERIOD_SHIFT 8 -#define SDRAM_REFRESH_PERIOD_MASK 0xf - -#define SDRAM_TEST_LEN_SHIFT 4 -#define SDRAM_TEST_LEN_MASK 0xfffff -#define SDRAM_TEST_START_ADDR_SHIFT 24 -#define SDRAM_TEST_START_ADDR_MASK 0x3f - -#define SDRAM_TEST_EN (1 << 0) -#define SDRAM_TEST_MODE_SHIFT 1 -#define SDRAM_TEST_MODE_MASK 3 -#define SDRAM_TEST_MODE_WO 0 -#define SDRAM_TEST_MODE_RB 1 -#define SDRAM_TEST_MODE_RW 2 -#define SDRAM_TEST_GEN_MODE_SHIFT 3 -#define SDRAM_TEST_GEN_MODE_MASK 7 -#define SDRAM_TEST_TWO_MODES (1 << 6) -#define SDRAM_TEST_ERRSTOP (1 << 7) -#define SDRAM_TEST_DONE (1 << 12) -#define SDRAM_TEST_FAIL (1 << 13) - -#define SDRAM_AC_TRFC_SHIFT 0 -#define SDRAM_AC_TRFC_MASK 0xff - -#ifndef __ASSEMBLY__ - -struct ast2500_sdrammc_regs { - u32 protection_key; - u32 config; - u32 gm_protection_key; - u32 refresh_timing; - u32 ac_timing[3]; - u32 misc_control; - u32 mr46_mode_setting; - u32 mr5_mode_setting; - u32 mode_setting_control; - u32 mr02_mode_setting; - u32 mr13_mode_setting; - u32 power_control; - u32 req_limit_mask; - u32 pri_group_setting; - u32 max_grant_len[4]; - u32 intr_ctrl; - u32 ecc_range_ctrl; - u32 first_ecc_err_addr; - u32 last_ecc_err_addr; - u32 phy_ctrl[4]; - u32 ecc_test_ctrl; - u32 test_addr; - u32 test_fail_dq_bit; - u32 test_init_val; - u32 phy_debug_ctrl; - u32 phy_debug_data; - u32 reserved1[30]; - u32 scu_passwd; - u32 reserved2[7]; - u32 scu_mpll; - u32 reserved3[19]; - u32 scu_hwstrap; -}; - -#endif /* __ASSEMBLY__ */ - -#endif /* _ASM_ARCH_SDRAM_AST2500_H */ diff --git a/arch/arm/include/asm/arch-aspeed/timer.h b/arch/arm/include/asm/arch-aspeed/timer.h deleted file mode 100644 index ff24e2f..0000000 --- a/arch/arm/include/asm/arch-aspeed/timer.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2016 Google, Inc - */ -#ifndef _ASM_ARCH_TIMER_H -#define _ASM_ARCH_TIMER_H - -/* Each timer has 4 control bits in ctrl1 register. - * Timer1 uses bits 0:3, Timer2 uses bits 4:7 and so on, - * such that timer X uses bits (4 * X - 4):(4 * X - 1) - * If the timer does not support PWM, bit 4 is reserved. - */ -#define AST_TMC_EN (1 << 0) -#define AST_TMC_1MHZ (1 << 1) -#define AST_TMC_OVFINTR (1 << 2) -#define AST_TMC_PWM (1 << 3) - -/* Timers are counted from 1 in the datasheet. */ -#define AST_TMC_CTRL1_SHIFT(n) (4 * ((n) - 1)) - -#define AST_TMC_RATE (1000*1000) - -#ifndef __ASSEMBLY__ - -/* - * All timers share control registers, which makes it harder to make them - * separate devices. Since only one timer is needed at the moment, making - * it this just one device. - */ - -struct ast_timer_counter { - u32 status; - u32 reload_val; - u32 match1; - u32 match2; -}; - -struct ast_timer { - struct ast_timer_counter timers1[3]; - u32 ctrl1; - u32 ctrl2; -#ifdef CONFIG_ASPEED_AST2500 - u32 ctrl3; - u32 ctrl1_clr; -#else - u32 reserved[2]; -#endif - struct ast_timer_counter timers2[5]; -}; - -#endif /* __ASSEMBLY__ */ - -#endif /* _ASM_ARCH_TIMER_H */ diff --git a/arch/arm/include/asm/arch-aspeed/wdt.h b/arch/arm/include/asm/arch-aspeed/wdt.h deleted file mode 100644 index fb04d41..0000000 --- a/arch/arm/include/asm/arch-aspeed/wdt.h +++ /dev/null @@ -1,113 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Google, Inc - */ - -#ifndef _ASM_ARCH_WDT_H -#define _ASM_ARCH_WDT_H - -#define WDT_BASE 0x1e785000 - -/* - * Special value that needs to be written to counter_restart register to - * (re)start the timer - */ -#define WDT_COUNTER_RESTART_VAL 0x4755 - -/* Control register */ -#define WDT_CTRL_RESET_MODE_SHIFT 5 -#define WDT_CTRL_RESET_MODE_MASK 3 - -#define WDT_CTRL_EN (1 << 0) -#define WDT_CTRL_RESET (1 << 1) -#define WDT_CTRL_CLK1MHZ (1 << 4) -#define WDT_CTRL_2ND_BOOT (1 << 7) - -/* Values for Reset Mode */ -#define WDT_CTRL_RESET_SOC 0 -#define WDT_CTRL_RESET_CHIP 1 -#define WDT_CTRL_RESET_CPU 2 -#define WDT_CTRL_RESET_MASK 3 - -/* Reset Mask register */ -#define WDT_RESET_ARM (1 << 0) -#define WDT_RESET_COPROC (1 << 1) -#define WDT_RESET_SDRAM (1 << 2) -#define WDT_RESET_AHB (1 << 3) -#define WDT_RESET_I2C (1 << 4) -#define WDT_RESET_MAC1 (1 << 5) -#define WDT_RESET_MAC2 (1 << 6) -#define WDT_RESET_GCRT (1 << 7) -#define WDT_RESET_USB20 (1 << 8) -#define WDT_RESET_USB11_HOST (1 << 9) -#define WDT_RESET_USB11_EHCI2 (1 << 10) -#define WDT_RESET_VIDEO (1 << 11) -#define WDT_RESET_HAC (1 << 12) -#define WDT_RESET_LPC (1 << 13) -#define WDT_RESET_SDSDIO (1 << 14) -#define WDT_RESET_MIC (1 << 15) -#define WDT_RESET_CRT2C (1 << 16) -#define WDT_RESET_PWM (1 << 17) -#define WDT_RESET_PECI (1 << 18) -#define WDT_RESET_JTAG (1 << 19) -#define WDT_RESET_ADC (1 << 20) -#define WDT_RESET_GPIO (1 << 21) -#define WDT_RESET_MCTP (1 << 22) -#define WDT_RESET_XDMA (1 << 23) -#define WDT_RESET_SPI (1 << 24) -#define WDT_RESET_MISC (1 << 25) - -#define WDT_RESET_DEFAULT \ - (WDT_RESET_ARM | WDT_RESET_COPROC | WDT_RESET_I2C | \ - WDT_RESET_MAC1 | WDT_RESET_MAC2 | WDT_RESET_GCRT | \ - WDT_RESET_USB20 | WDT_RESET_USB11_HOST | WDT_RESET_USB11_EHCI2 | \ - WDT_RESET_VIDEO | WDT_RESET_HAC | WDT_RESET_LPC | \ - WDT_RESET_SDSDIO | WDT_RESET_MIC | WDT_RESET_CRT2C | \ - WDT_RESET_PWM | WDT_RESET_PECI | WDT_RESET_JTAG | \ - WDT_RESET_ADC | WDT_RESET_GPIO | WDT_RESET_MISC) - -#ifndef __ASSEMBLY__ -struct ast_wdt { - u32 counter_status; - u32 counter_reload_val; - u32 counter_restart; - u32 ctrl; - u32 timeout_status; - u32 clr_timeout_status; - u32 reset_width; - /* On pre-ast2500 SoCs this register is reserved. */ - u32 reset_mask; -}; - -/** - * Given flags parameter passed to wdt_reset or wdt_start uclass functions, - * gets Reset Mode value from it. - * - * @flags: flags parameter passed into wdt_reset or wdt_start - * @return Reset Mode value - */ -u32 ast_reset_mode_from_flags(ulong flags); - -/** - * Given flags parameter passed to wdt_reset or wdt_start uclass functions, - * gets Reset Mask value from it. Reset Mask is only supported on ast2500 - * - * @flags: flags parameter passed into wdt_reset or wdt_start - * @return Reset Mask value - */ -u32 ast_reset_mask_from_flags(ulong flags); - -/** - * Given Reset Mask and Reset Mode values, converts them to flags, - * suitable for passing into wdt_start or wdt_reset uclass functions. - * - * On ast2500 Reset Mask is 25 bits wide and Reset Mode is 2 bits wide, so they - * can both be packed into single 32 bits wide value. - * - * @reset_mode: Reset Mode - * @reset_mask: Reset Mask - */ -ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask); -#endif /* __ASSEMBLY__ */ - -#endif /* _ASM_ARCH_WDT_H */ |