diff options
Diffstat (limited to 'arch/arm/include/asm/arch-hi6220')
| -rw-r--r-- | arch/arm/include/asm/arch-hi6220/dwmmc.h | 7 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-hi6220/gpio.h | 26 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-hi6220/hi6220.h | 389 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h | 419 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-hi6220/periph.h | 29 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-hi6220/pinmux.h | 81 |
6 files changed, 0 insertions, 951 deletions
diff --git a/arch/arm/include/asm/arch-hi6220/dwmmc.h b/arch/arm/include/asm/arch-hi6220/dwmmc.h deleted file mode 100644 index cf51c17..0000000 --- a/arch/arm/include/asm/arch-hi6220/dwmmc.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Linaro - * Peter Griffin <peter.griffin@linaro.org> - */ - -int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width); diff --git a/arch/arm/include/asm/arch-hi6220/gpio.h b/arch/arm/include/asm/arch-hi6220/gpio.h deleted file mode 100644 index c5ee359..0000000 --- a/arch/arm/include/asm/arch-hi6220/gpio.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Linaro - * Peter Griffin <peter.griffin@linaro.org> - */ - -#ifndef _HI6220_GPIO_H_ -#define _HI6220_GPIO_H_ - -#define HI6220_GPIO_BASE(bank) (((bank < 4) ? 0xf8011000 : \ - 0xf7020000 - 0x4000) + (0x1000 * bank)) - -#define HI6220_GPIO_PER_BANK 8 -#define HI6220_GPIO_DIR 0x400 - -struct gpio_bank { - u8 *base; /* address of registers in physical memory */ -}; - -/* Information about a GPIO bank */ -struct hikey_gpio_platdata { - int bank_index; - ulong base; /* address of registers in physical memory */ -}; - -#endif /* _HI6220_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-hi6220/hi6220.h b/arch/arm/include/asm/arch-hi6220/hi6220.h deleted file mode 100644 index 55729e3..0000000 --- a/arch/arm/include/asm/arch-hi6220/hi6220.h +++ /dev/null @@ -1,389 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Linaro - * Peter Griffin <peter.griffin@linaro.org> - */ - -#ifndef __HI6220_H__ -#define __HI6220_H__ - -#include "hi6220_regs_alwayson.h" - -#define HI6220_MMC0_BASE 0xF723D000 -#define HI6220_MMC1_BASE 0xF723E000 - -#define HI6220_UART0_BASE 0xF8015000 -#define HI6220_UART3_BASE 0xF7113000 - -#define HI6220_PMUSSI_BASE 0xF8000000 - -#define HI6220_PERI_BASE 0xF7030000 - -struct peri_sc_periph_regs { - u32 ctrl1; /*0x0*/ - u32 ctrl2; - u32 ctrl3; - u32 ctrl4; - u32 ctrl5; - u32 ctrl6; - u32 ctrl8; - u32 ctrl9; - u32 ctrl10; - u32 ctrl12; - u32 ctrl13; - u32 ctrl14; - - u32 unknown_1[8]; - - u32 ddr_ctrl0; /*0x50*/ - - u32 unknown_2[16]; - - u32 stat1; /*0x94*/ - - u32 unknown_3[90]; - - u32 clk0_en; /*0x200*/ - u32 clk0_dis; - u32 clk0_stat; - - u32 unknown_4; - - u32 clk1_en; /*0x210*/ - u32 clk1_dis; - u32 clk1_stat; - - u32 unknown_5; - - u32 clk2_en; /*0x220*/ - u32 clk2_dis; - u32 clk2_stat; - - u32 unknown_6; - - u32 clk3_en; /*0x230*/ - u32 clk3_dis; - u32 clk3_stat; - - u32 unknown_7; - - u32 clk8_en; /*0x240*/ - u32 clk8_dis; - u32 clk8_stat; - - u32 unknown_8; - - u32 clk9_en; /*0x250*/ - u32 clk9_dis; - u32 clk9_stat; - - u32 unknown_9; - - u32 clk10_en; /*0x260*/ - u32 clk10_dis; - u32 clk10_stat; - - u32 unknown_10; - - u32 clk12_en; /*0x270*/ - u32 clk12_dis; - u32 clk12_stat; - - u32 unknown_11[33]; - - u32 rst0_en; /*0x300*/ - u32 rst0_dis; - u32 rst0_stat; - - u32 unknown_12; - - u32 rst1_en; /*0x310*/ - u32 rst1_dis; - u32 rst1_stat; - - u32 unknown_13; - - u32 rst2_en; /*0x320*/ - u32 rst2_dis; - u32 rst2_stat; - - u32 unknown_14; - - u32 rst3_en; /*0x330*/ - u32 rst3_dis; - u32 rst3_stat; - - u32 unknown_15; - - u32 rst8_en; /*0x340*/ - u32 rst8_dis; - u32 rst8_stat; - - u32 unknown_16[45]; - - u32 clk0_sel; /*0x400*/ - - u32 unknown_17[36]; - - u32 clkcfg8bit1; /*0x494*/ - u32 clkcfg8bit2; - - u32 unknown_18[538]; - - u32 reserved8_addr; /*0xd04*/ -}; - - -/* CTRL1 bit definitions */ - -#define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0) -#define PERI_CTRL1_HIFI_INT_MASK (1 << 1) -#define PERI_CTRL1_HIFI_ALL_INT_MASK (1 << 2) -#define PERI_CTRL1_ETR_AXI_CSYSREQ_N_MSK (1 << 16) -#define PERI_CTRL1_HIFI_INT_MASK_MSK (1 << 17) -#define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK (1 << 18) - - -/* CTRL2 bit definitions */ - -#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0 (1 << 0) -#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC1 (1 << 2) -#define PERI_CTRL2_NAND_SYS_MEM_SEL (1 << 6) -#define PERI_CTRL2_G3D_DDRT_AXI_SEL (1 << 7) -#define PERI_CTRL2_GU_MDM_BBP_TESTPIN_SEL (1 << 8) -#define PERI_CTRL2_CODEC_SSI_MASTER_CHECK (1 << 9) -#define PERI_CTRL2_FUNC_TEST_SOFT (1 << 12) -#define PERI_CTRL2_CSSYS_TS_ENABLE (1 << 15) -#define PERI_CTRL2_HIFI_RAMCTRL_S_EMA (1 << 16) -#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAW (1 << 20) -#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAS (1 << 22) -#define PERI_CTRL2_HIFI_RAMCTRL_S_RET1N (1 << 26) -#define PERI_CTRL2_HIFI_RAMCTRL_S_RET2N (1 << 27) -#define PERI_CTRL2_HIFI_RAMCTRL_S_PGEN (1 << 28) - -/* CTRL3 bit definitions */ - -#define PERI_CTRL3_HIFI_DDR_HARQMEM_ADDR (1 << 0) -#define PERI_CTRL3_HIFI_HARQMEMRMP_EN (1 << 12) -#define PERI_CTRL3_HARQMEM_SYS_MED_SEL (1 << 13) -#define PERI_CTRL3_SOC_AP_OCCUPY_GRP1 (1 << 14) -#define PERI_CTRL3_SOC_AP_OCCUPY_GRP2 (1 << 16) -#define PERI_CTRL3_SOC_AP_OCCUPY_GRP3 (1 << 18) -#define PERI_CTRL3_SOC_AP_OCCUPY_GRP4 (1 << 20) -#define PERI_CTRL3_SOC_AP_OCCUPY_GRP5 (1 << 22) -#define PERI_CTRL3_SOC_AP_OCCUPY_GRP6 (1 << 24) - -/* CTRL4 bit definitions */ - -#define PERI_CTRL4_PICO_FSELV (1 << 0) -#define PERI_CTRL4_FPGA_EXT_PHY_SEL (1 << 3) -#define PERI_CTRL4_PICO_REFCLKSEL (1 << 4) -#define PERI_CTRL4_PICO_SIDDQ (1 << 6) -#define PERI_CTRL4_PICO_SUSPENDM_SLEEPM (1 << 7) -#define PERI_CTRL4_PICO_OGDISABLE (1 << 8) -#define PERI_CTRL4_PICO_COMMONONN (1 << 9) -#define PERI_CTRL4_PICO_VBUSVLDEXT (1 << 10) -#define PERI_CTRL4_PICO_VBUSVLDEXTSEL (1 << 11) -#define PERI_CTRL4_PICO_VATESTENB (1 << 12) -#define PERI_CTRL4_PICO_SUSPENDM (1 << 14) -#define PERI_CTRL4_PICO_SLEEPM (1 << 15) -#define PERI_CTRL4_BC11_C (1 << 16) -#define PERI_CTRL4_BC11_B (1 << 17) -#define PERI_CTRL4_BC11_A (1 << 18) -#define PERI_CTRL4_BC11_GND (1 << 19) -#define PERI_CTRL4_BC11_FLOAT (1 << 20) -#define PERI_CTRL4_OTG_PHY_SEL (1 << 21) -#define PERI_CTRL4_USB_OTG_SS_SCALEDOWN_MODE (1 << 22) -#define PERI_CTRL4_OTG_DM_PULLDOWN (1 << 24) -#define PERI_CTRL4_OTG_DP_PULLDOWN (1 << 25) -#define PERI_CTRL4_OTG_IDPULLUP (1 << 26) -#define PERI_CTRL4_OTG_DRVBUS (1 << 27) -#define PERI_CTRL4_OTG_SESSEND (1 << 28) -#define PERI_CTRL4_OTG_BVALID (1 << 29) -#define PERI_CTRL4_OTG_AVALID (1 << 30) -#define PERI_CTRL4_OTG_VBUSVALID (1 << 31) - -/* CTRL5 bit definitions */ - -#define PERI_CTRL5_USBOTG_RES_SEL (1 << 3) -#define PERI_CTRL5_PICOPHY_ACAENB (1 << 4) -#define PERI_CTRL5_PICOPHY_BC_MODE (1 << 5) -#define PERI_CTRL5_PICOPHY_CHRGSEL (1 << 6) -#define PERI_CTRL5_PICOPHY_VDATSRCEND (1 << 7) -#define PERI_CTRL5_PICOPHY_VDATDETENB (1 << 8) -#define PERI_CTRL5_PICOPHY_DCDENB (1 << 9) -#define PERI_CTRL5_PICOPHY_IDDIG (1 << 10) -#define PERI_CTRL5_DBG_MUX (1 << 11) - -/* CTRL6 bit definitions */ - -#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMA (1 << 0) -#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAW (1 << 4) -#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAS (1 << 6) -#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET1N (1 << 10) -#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET2N (1 << 11) -#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_PGEN (1 << 12) - -/* CTRL8 bit definitions */ - -#define PERI_CTRL8_PICOPHY_TXRISETUNE0 (1 << 0) -#define PERI_CTRL8_PICOPHY_TXPREEMPAMPTUNE0 (1 << 2) -#define PERI_CTRL8_PICOPHY_TXRESTUNE0 (1 << 4) -#define PERI_CTRL8_PICOPHY_TXHSSVTUNE0 (1 << 6) -#define PERI_CTRL8_PICOPHY_COMPDISTUNE0 (1 << 8) -#define PERI_CTRL8_PICOPHY_TXPREEMPPULSETUNE0 (1 << 11) -#define PERI_CTRL8_PICOPHY_OTGTUNE0 (1 << 12) -#define PERI_CTRL8_PICOPHY_SQRXTUNE0 (1 << 16) -#define PERI_CTRL8_PICOPHY_TXVREFTUNE0 (1 << 20) -#define PERI_CTRL8_PICOPHY_TXFSLSTUNE0 (1 << 28) - -/* CTRL9 bit definitions */ - -#define PERI_CTRL9_PICOPLY_TESTCLKEN (1 << 0) -#define PERI_CTRL9_PICOPLY_TESTDATAOUTSEL (1 << 1) -#define PERI_CTRL9_PICOPLY_TESTADDR (1 << 4) -#define PERI_CTRL9_PICOPLY_TESTDATAIN (1 << 8) - -/* CLK0 EN/DIS/STAT bit definitions */ - -#define PERI_CLK0_MMC0 (1 << 0) -#define PERI_CLK0_MMC1 (1 << 1) -#define PERI_CLK0_MMC2 (1 << 2) -#define PERI_CLK0_NANDC (1 << 3) -#define PERI_CLK0_USBOTG (1 << 4) -#define PERI_CLK0_PICOPHY (1 << 5) -#define PERI_CLK0_PLL (1 << 6) - -/* CLK1 EN/DIS/STAT bit definitions */ - -#define PERI_CLK1_HIFI (1 << 0) -#define PERI_CLK1_DIGACODEC (1 << 5) - -/* CLK2 EN/DIS/STAT bit definitions */ - -#define PERI_CLK2_IPF (1 << 0) -#define PERI_CLK2_SOCP (1 << 1) -#define PERI_CLK2_DMAC (1 << 2) -#define PERI_CLK2_SECENG (1 << 3) -#define PERI_CLK2_HPM0 (1 << 5) -#define PERI_CLK2_HPM1 (1 << 6) -#define PERI_CLK2_HPM2 (1 << 7) -#define PERI_CLK2_HPM3 (1 << 8) - -/* CLK8 EN/DIS/STAT bit definitions */ - -#define PERI_CLK8_RS0 (1 << 0) -#define PERI_CLK8_RS2 (1 << 1) -#define PERI_CLK8_RS3 (1 << 2) -#define PERI_CLK8_MS0 (1 << 3) -#define PERI_CLK8_MS2 (1 << 5) -#define PERI_CLK8_XG2RAM0 (1 << 6) -#define PERI_CLK8_X2SRAM (1 << 7) -#define PERI_CLK8_SRAM (1 << 8) -#define PERI_CLK8_ROM (1 << 9) -#define PERI_CLK8_HARQ (1 << 10) -#define PERI_CLK8_MMU (1 << 11) -#define PERI_CLK8_DDRC (1 << 12) -#define PERI_CLK8_DDRPHY (1 << 13) -#define PERI_CLK8_DDRPHY_REF (1 << 14) -#define PERI_CLK8_X2X_SYSNOC (1 << 15) -#define PERI_CLK8_X2X_CCPU (1 << 16) -#define PERI_CLK8_DDRT (1 << 17) -#define PERI_CLK8_DDRPACK_RS (1 << 18) - -/* CLK9 EN/DIS/STAT bit definitions */ - -#define PERI_CLK9_CARM_DAP (1 << 0) -#define PERI_CLK9_CARM_ATB (1 << 1) -#define PERI_CLK9_CARM_LBUS (1 << 2) -#define PERI_CLK9_CARM_KERNEL (1 << 3) - -/* CLK10 EN/DIS/STAT bit definitions */ - -#define PERI_CLK10_IPF_CCPU (1 << 0) -#define PERI_CLK10_SOCP_CCPU (1 << 1) -#define PERI_CLK10_SECENG_CCPU (1 << 2) -#define PERI_CLK10_HARQ_CCPU (1 << 3) -#define PERI_CLK10_IPF_MCU (1 << 16) -#define PERI_CLK10_SOCP_MCU (1 << 17) -#define PERI_CLK10_SECENG_MCU (1 << 18) -#define PERI_CLK10_HARQ_MCU (1 << 19) - -/* CLK12 EN/DIS/STAT bit definitions */ - -#define PERI_CLK12_HIFI_SRC (1 << 0) -#define PERI_CLK12_MMC0_SRC (1 << 1) -#define PERI_CLK12_MMC1_SRC (1 << 2) -#define PERI_CLK12_MMC2_SRC (1 << 3) -#define PERI_CLK12_SYSPLL_DIV (1 << 4) -#define PERI_CLK12_TPIU_SRC (1 << 5) -#define PERI_CLK12_MMC0_HF (1 << 6) -#define PERI_CLK12_MMC1_HF (1 << 7) -#define PERI_CLK12_PLL_TEST_SRC (1 << 8) -#define PERI_CLK12_CODEC_SOC (1 << 9) -#define PERI_CLK12_MEDIA (1 << 10) - -/* RST0 EN/DIS/STAT bit definitions */ - -#define PERI_RST0_MMC0 (1 << 0) -#define PERI_RST0_MMC1 (1 << 1) -#define PERI_RST0_MMC2 (1 << 2) -#define PERI_RST0_NANDC (1 << 3) -#define PERI_RST0_USBOTG_BUS (1 << 4) -#define PERI_RST0_POR_PICOPHY (1 << 5) -#define PERI_RST0_USBOTG (1 << 6) -#define PERI_RST0_USBOTG_32K (1 << 7) - -/* RST1 EN/DIS/STAT bit definitions */ - -#define PERI_RST1_HIFI (1 << 0) -#define PERI_RST1_DIGACODEC (1 << 5) - -/* RST2 EN/DIS/STAT bit definitions */ - -#define PERI_RST2_IPF (1 << 0) -#define PERI_RST2_SOCP (1 << 1) -#define PERI_RST2_DMAC (1 << 2) -#define PERI_RST2_SECENG (1 << 3) -#define PERI_RST2_ABB (1 << 4) -#define PERI_RST2_HPM0 (1 << 5) -#define PERI_RST2_HPM1 (1 << 6) -#define PERI_RST2_HPM2 (1 << 7) -#define PERI_RST2_HPM3 (1 << 8) - -/* RST3 EN/DIS/STAT bit definitions */ - -#define PERI_RST3_CSSYS (1 << 0) -#define PERI_RST3_I2C0 (1 << 1) -#define PERI_RST3_I2C1 (1 << 2) -#define PERI_RST3_I2C2 (1 << 3) -#define PERI_RST3_I2C3 (1 << 4) -#define PERI_RST3_UART1 (1 << 5) -#define PERI_RST3_UART2 (1 << 6) -#define PERI_RST3_UART3 (1 << 7) -#define PERI_RST3_UART4 (1 << 8) -#define PERI_RST3_SSP (1 << 9) -#define PERI_RST3_PWM (1 << 10) -#define PERI_RST3_BLPWM (1 << 11) -#define PERI_RST3_TSENSOR (1 << 12) -#define PERI_RST3_DAPB (1 << 18) -#define PERI_RST3_HKADC (1 << 19) -#define PERI_RST3_CODEC (1 << 20) - -/* RST8 EN/DIS/STAT bit definitions */ - -#define PERI_RST8_RS0 (1 << 0) -#define PERI_RST8_RS2 (1 << 1) -#define PERI_RST8_RS3 (1 << 2) -#define PERI_RST8_MS0 (1 << 3) -#define PERI_RST8_MS2 (1 << 5) -#define PERI_RST8_XG2RAM0 (1 << 6) -#define PERI_RST8_X2SRAM_TZMA (1 << 7) -#define PERI_RST8_SRAM (1 << 8) -#define PERI_RST8_HARQ (1 << 10) -#define PERI_RST8_DDRC (1 << 12) -#define PERI_RST8_DDRC_APB (1 << 13) -#define PERI_RST8_DDRPACK_APB (1 << 14) -#define PERI_RST8_DDRT (1 << 17) - -#endif /*__HI62220_H__*/ diff --git a/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h b/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h deleted file mode 100644 index 4b9a0d4..0000000 --- a/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h +++ /dev/null @@ -1,419 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Linaro - * Peter Griffin <peter.griffin@linaro.org> - */ - -#ifndef __HI6220_ALWAYSON_H__ -#define __HI6220_ALWAYSON_H__ - -#define ALWAYSON_CTRL_BASE 0xF7800000 - -struct alwayson_sc_regs { - u32 ctrl0; /*0x0*/ - u32 ctrl1; - u32 ctrl2; - - u32 unknown; - - u32 stat0; /*0x10*/ - u32 stat1; - u32 mcu_imctrl; - u32 mcu_imstat; - - u32 unknown_1[9]; - - u32 secondary_int_en0; /*0x44*/ - u32 secondary_int_statr0; - u32 secondary_int_statm0; - - u32 unknown_2; - - u32 mcu_wkup_int_en6; /*0x54*/ - u32 mcu_wkup_int_statr6; - u32 mcu_wkup_int_statm6; - - u32 unknown_3; - - u32 mcu_wkup_int_en5; /*0x64*/ - u32 mcu_wkup_int_statr5; - u32 mcu_wkup_int_statm5; - - u32 unknown_4[9]; - - u32 mcu_wkup_int_en4; /*0x94*/ - u32 mcu_wkup_int_statr4; - u32 mcu_wkup_int_statm4; - - u32 unknown_5[2]; - - u32 mcu_wkup_int_en0; /*0xa8*/ - u32 mcu_wkup_int_statr0; - u32 mcu_wkup_int_statm0; - - u32 mcu_wkup_int_en1; /*0xb4*/ - u32 mcu_wkup_int_statr1; - u32 mcu_wkup_int_statm1; - - u32 unknown_6; - - u32 int_statr; /*0xc4*/ - u32 int_statm; - u32 int_clear; - - u32 int_en_set; /*0xd0*/ - u32 int_en_dis; - u32 int_en_stat; - - u32 unknown_7[2]; - - u32 int_statr1; /*0xc4*/ - u32 int_statm1; - u32 int_clear1; - - u32 int_en_set1; /*0xf0*/ - u32 int_en_dis1; - u32 int_en_stat1; - - u32 unknown_8[53]; - - u32 timer_en0; /*0x1d0*/ - u32 timer_en1; - - u32 unknown_9[6]; - - u32 timer_en4; /*0x1f0*/ - u32 timer_en5; - - u32 unknown_10[130]; - - u32 mcu_subsys_ctrl0; /*0x400*/ - u32 mcu_subsys_ctrl1; - u32 mcu_subsys_ctrl2; - u32 mcu_subsys_ctrl3; - u32 mcu_subsys_ctrl4; - u32 mcu_subsys_ctrl5; - u32 mcu_subsys_ctrl6; - u32 mcu_subsys_ctrl7; - - u32 unknown_10_1[8]; - - u32 mcu_subsys_stat0; /*0x440*/ - u32 mcu_subsys_stat1; - u32 mcu_subsys_stat2; - u32 mcu_subsys_stat3; - u32 mcu_subsys_stat4; - u32 mcu_subsys_stat5; - u32 mcu_subsys_stat6; - u32 mcu_subsys_stat7; - - u32 unknown_11[116]; - - u32 clk4_en; /*0x630*/ - u32 clk4_dis; - u32 clk4_stat; - - u32 clk5_en; /*0x63c*/ - u32 clk5_dis; - u32 clk5_stat; - - u32 unknown_12[42]; - - u32 rst4_en; /*0x6f0*/ - u32 rst4_dis; - u32 rst4_stat; - - u32 rst5_en; /*0x6fc*/ - u32 rst5_dis; - u32 rst5_stat; - - u32 unknown_13[62]; - - u32 pw_clk0_en; /*0x800*/ - u32 pw_clk0_dis; - u32 pw_clk0_stat; - - u32 unknown_13_1; - - u32 pw_rst0_en; /*0x810*/ - u32 pw_rst0_dis; - u32 pw_rst0_stat; - - u32 unknown_14; - - u32 pw_isoen0; /*0x820*/ - u32 pw_isodis0; - u32 pw_iso_stat0; - - u32 unknown_14_1; - - u32 pw_mtcmos_en0; /*0x830*/ - u32 pw_mtcmos_dis0; - u32 pw_mtcmos_stat0; - u32 pw_mtcmos_ack_stat0; - u32 pw_mtcmos_timeout_stat0; - - u32 unknown_14_2[3]; - - u32 pw_stat0; /*0x850*/ - u32 pw_stat1; - - u32 unknown_15[10]; - - u32 systest_stat; /*0x880*/ - - u32 unknown_16[3]; - - u32 systest_slicer_cnt0;/*0x890*/ - u32 systest_slicer_cnt1; - - u32 unknown_17[12]; - - u32 pw_ctrl1; /*0x8C8*/ - u32 pw_ctrl; - - u32 mcpu_voteen; - u32 mcpu_votedis; - u32 mcpu_votestat; - - u32 unknown_17_1; - - u32 mcpu_vote_msk0; /*0x8E0*/ - u32 mcpu_vote_msk1; - u32 mcpu_votestat0_msk; - u32 mcpu_votestat1_msk; - - u32 peri_voteen; /*0x8F0*/ - u32 peri_votedis; - u32 peri_votestat; - - u32 unknown_17_2; - - u32 peri_vote_msk0; /*0x900*/ - u32 peri_vote_msk1; - u32 peri_votestat0_msk; - u32 erpi_votestat1_msk; - u32 acpu_voteen; - u32 acpu_votedis; - u32 acpu_votestat; - - u32 unknown_18; - - u32 acpu_vote_msk0; /*0x920*/ - u32 acpu_vote_msk1; - u32 acpu_votestat0_msk; - u32 acpu_votestat1_msk; - u32 mcu_voteen; - u32 mcu_votedis; - u32 mcu_votestat; - - u32 unknown_18_1; - - u32 mcu_vote_msk0; /*0x940*/ - u32 mcu_vote_msk1; - u32 mcu_vote_votestat0_msk; - u32 mcu_vote_votestat1_msk; - - u32 unknown_18_1_2[4]; - - u32 mcu_vote_vote1en; /*0x960*/ - u32 mcu_vote_vote1dis; - u32 mcu_vote_vote1stat; - - u32 unknown_18_2; - - u32 mcu_vote_vote1_msk0;/*0x970*/ - u32 mcu_vote_vote1_msk1; - u32 mcu_vote_vote1stat0_msk; - u32 mcu_vote_vote1stat1_msk; - u32 mcu_vote_vote2en; - u32 mcu_vote_vote2dis; - u32 mcu_vote_vote2stat; - - u32 unknown_18_3; - - u32 mcu_vote2_msk0; /*0x990*/ - u32 mcu_vote2_msk1; - u32 mcu_vote2stat0_msk; - u32 mcu_vote2stat1_msk; - u32 vote_ctrl; - u32 vote_stat; /*0x9a4*/ - - u32 unknown_19[342]; - - u32 econum; /*0xf00*/ - - u32 unknown_20_1[3]; - - u32 scchipid; /*0xf10*/ - - u32 unknown_20_2[2]; - - u32 scsocid; /*0xf1c*/ - - u32 unknown_20[48]; - - u32 soc_fpga_rtl_def; /*0xfe0*/ - u32 soc_fpga_pr_def; - u32 soc_fpga_res_def0; - u32 soc_fpga_res_def1; /*0xfec*/ -}; - -/* ctrl0 bit definitions */ - -#define ALWAYSON_SC_SYS_CTRL0_MODE_NORMAL 0x004 -#define ALWAYSON_SC_SYS_CTRL0_MODE_MASK 0x007 - -/* ctrl1 bit definitions */ - -#define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG (1 << 0) -#define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM (1 << 1) -#define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP (1 << 2) -#define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL (1 << 3) -#define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG (1 << 4) -#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG (1 << 6) -#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG (1 << 7) -#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG (1 << 8) -#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG (1 << 9) -#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG (1 << 10) -#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1 (1 << 11) -#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT (1 << 12) -#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT (1 << 13) -#define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG (1 << 15) -#define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG_MSK (1 << 16) -#define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK (1 << 17) -#define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP_MSK (1 << 18) -#define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL_MSK (1 << 19) -#define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG_MSK (1 << 20) -#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG_MSK (1 << 22) -#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG_MSK (1 << 23) -#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG_MSK (1 << 24) -#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG_MSK (1 << 25) -#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG_MSK (1 << 26) -#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK (1 << 27) -#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK (1 << 28) -#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK (1 << 29) -#define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK (1 << 31) - -/* ctrl2 bit definitions */ - -#define ALWAYSON_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR (1 << 26) -#define ALWAYSON_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR (1 << 27) -#define ALWAYSON_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR (1 << 28) -#define ALWAYSON_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR (1 << 29) -#define ALWAYSON_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR (1 << 30) -#define ALWAYSON_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR (1 << 31) - -/* stat0 bit definitions */ - -#define ALWAYSON_SC_SYS_STAT0_MCU_RST_STAT (1 << 25) -#define ALWAYSON_SC_SYS_STAT0_MCU_SOFTRST_STAT (1 << 26) -#define ALWAYSON_SC_SYS_STAT0_MCU_WDGRST_STAT (1 << 27) -#define ALWAYSON_SC_SYS_STAT0_TSENSOR_HARDRST_STAT (1 << 28) -#define ALWAYSON_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT (1 << 29) -#define ALWAYSON_SC_SYS_STAT0_CM3_WDG1_RST_STAT (1 << 30) -#define ALWAYSON_SC_SYS_STAT0_GLB_SRST_STAT (1 << 31) - -/* stat1 bit definitions */ - -#define ALWAYSON_SC_SYS_STAT1_MODE_STATUS (1 << 0) -#define ALWAYSON_SC_SYS_STAT1_BOOT_SEL_LOCK (1 << 16) -#define ALWAYSON_SC_SYS_STAT1_FUNC_MODE_LOCK (1 << 17) -#define ALWAYSON_SC_SYS_STAT1_BOOT_MODE_LOCK (1 << 19) -#define ALWAYSON_SC_SYS_STAT1_FUN_JTAG_MODE_OUT (1 << 20) -#define ALWAYSON_SC_SYS_STAT1_SECURITY_BOOT_FLG (1 << 27) -#define ALWAYSON_SC_SYS_STAT1_EFUSE_NANDBOOT_MSK (1 << 28) -#define ALWAYSON_SC_SYS_STAT1_EFUSE_NAND_BITWIDE (1 << 29) - -/* ctrl3 bit definitions */ - -#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3 0x003 -#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK 0x007 -#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_CSSYS_CTRL_PROT (1 << 3) -#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_TCXO_AFC_OEN_CRG (1 << 4) -#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM1 (1 << 8) -#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM0 (1 << 9) -#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_SD (1 << 10) -#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_MCU_SUBSYS_CTRL3_RESERVED (1 << 11) - -/* clk4_en bit definitions */ - -#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_MCU (1 << 0) -#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_MCU_DAP (1 << 3) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER0 (1 << 4) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER1 (1 << 5) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT0 (1 << 6) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT1 (1 << 7) -#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_S (1 << 8) -#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_NS (1 << 9) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_EFUSEC (1 << 10) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TZPC (1 << 11) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT0 (1 << 12) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT1 (1 << 13) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT2 (1 << 14) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER0 (1 << 15) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER1 (1 << 16) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER2 (1 << 17) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER3 (1 << 18) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER4 (1 << 19) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER5 (1 << 20) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER6 (1 << 21) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER7 (1 << 22) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER8 (1 << 23) -#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_UART0 (1 << 24) -#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC0 (1 << 25) -#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC1 (1 << 26) -#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_PMUSSI (1 << 27) -#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_JTAG_AUTH (1 << 28) -#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_CS_DAPB_ON (1 << 29) -#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_PDM (1 << 30) -#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_SSI_PAD (1 << 31) - -/* clk5_en bit definitions */ - -#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU (1 << 0) -#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_CCPU (1 << 1) -#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_CCPU (1 << 2) -#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_CCPU (1 << 3) -#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU (1 << 16) -#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_MCU (1 << 17) -#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_MCU (1 << 18) -#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_MCU (1 << 19) - -/* rst4_dis bit definitions */ - -#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_ECTR_N (1 << 0) -#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_SYS_N (1 << 1) -#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_POR_N (1 << 2) -#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_DAP_N (1 << 3) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER0_N (1 << 4) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER1_N (1 << 5) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT0_N (1 << 6) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT1_N (1 << 7) -#define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_S_N (1 << 8) -#define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_NS_N (1 << 9) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_EFUSEC_N (1 << 10) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT0_N (1 << 12) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT1_N (1 << 13) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT2_N (1 << 14) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER0_N (1 << 15) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER1_N (1 << 16) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER2_N (1 << 17) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER3_N (1 << 18) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER4_N (1 << 19) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER5_N (1 << 20) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER6_N (1 << 21) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER7_N (1 << 22) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER8_N (1 << 23) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_UART0_N (1 << 24) -#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC0_N (1 << 25) -#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC1_N (1 << 26) -#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N (1 << 27) -#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_JTAG_AUTH_N (1 << 28) -#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_CS_DAPB_ON_N (1 << 29) -#define ALWAYSON_SC_PERIPH_RST4_DIS_MDM_SUBSYS_GLB (1 << 30) - -#define PCLK_TIMER1 (1 << 16) -#define PCLK_TIMER0 (1 << 15) - -#endif /* __HI6220_ALWAYSON_H__ */ diff --git a/arch/arm/include/asm/arch-hi6220/periph.h b/arch/arm/include/asm/arch-hi6220/periph.h deleted file mode 100644 index edec213..0000000 --- a/arch/arm/include/asm/arch-hi6220/periph.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Linaro - * Peter Griffin <peter.griffin@linaro.org> - */ - -#ifndef __ASM_ARM_ARCH_PERIPH_H -#define __ASM_ARM_ARCH_PERIPH_H - -/* - * Peripherals required for pinmux configuration. List will - * grow with support for more devices getting added. - * Numbering based on interrupt table. - * - */ -enum periph_id { - PERIPH_ID_UART0 = 36, - PERIPH_ID_UART1, - PERIPH_ID_UART2, - PERIPH_ID_UART3, - PERIPH_ID_UART4, - PERIPH_ID_UART5, - PERIPH_ID_SDMMC0 = 72, - PERIPH_ID_SDMMC1, - - PERIPH_ID_NONE = -1, -}; - -#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-hi6220/pinmux.h b/arch/arm/include/asm/arch-hi6220/pinmux.h deleted file mode 100644 index b4a9957..0000000 --- a/arch/arm/include/asm/arch-hi6220/pinmux.h +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Linaro - * Peter Griffin <peter.griffin@linaro.org> - */ - -#ifndef __ASM_ARM_ARCH_PINMUX_H -#define __ASM_ARM_ARCH_PINMUX_H - -#include "periph.h" - - -/* iomg bit definition */ -#define MUX_M0 0 -#define MUX_M1 1 -#define MUX_M2 2 -#define MUX_M3 3 -#define MUX_M4 4 -#define MUX_M5 5 -#define MUX_M6 6 -#define MUX_M7 7 - -/* iocg bit definition */ -#define PULL_MASK (3) -#define PULL_DIS (0) -#define PULL_UP (1 << 0) -#define PULL_DOWN (1 << 1) - -/* drive strength definition */ -#define DRIVE_MASK (7 << 4) -#define DRIVE1_02MA (0 << 4) -#define DRIVE1_04MA (1 << 4) -#define DRIVE1_08MA (2 << 4) -#define DRIVE1_10MA (3 << 4) -#define DRIVE2_02MA (0 << 4) -#define DRIVE2_04MA (1 << 4) -#define DRIVE2_08MA (2 << 4) -#define DRIVE2_10MA (3 << 4) -#define DRIVE3_04MA (0 << 4) -#define DRIVE3_08MA (1 << 4) -#define DRIVE3_12MA (2 << 4) -#define DRIVE3_16MA (3 << 4) -#define DRIVE3_20MA (4 << 4) -#define DRIVE3_24MA (5 << 4) -#define DRIVE3_32MA (6 << 4) -#define DRIVE3_40MA (7 << 4) -#define DRIVE4_02MA (0 << 4) -#define DRIVE4_04MA (2 << 4) -#define DRIVE4_08MA (4 << 4) -#define DRIVE4_10MA (6 << 4) - -#define HI6220_PINMUX0_BASE 0xf7010000 -#define HI6220_PINMUX1_BASE 0xf7010800 - -#ifndef __ASSEMBLY__ - -/* maybe more registers, but highest used is 123 */ -#define REG_NUM 123 - -struct hi6220_pinmux0_regs { - uint32_t iomg[REG_NUM]; -}; - -struct hi6220_pinmux1_regs { - uint32_t iocfg[REG_NUM]; -}; - -#endif - -/** - * Configures the pinmux for a particular peripheral. - * - * This function will configure the peripheral pinmux along with - * pull-up/down and drive strength. - * - * @param peripheral peripheral to be configured - * @return 0 if ok, -1 on error (e.g. unsupported peripheral) - */ -int hi6220_pinmux_config(int peripheral); - -#endif |