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-rw-r--r--arch/arm/include/asm/arch-lpc32xx/clk.h186
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/config.h72
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/cpu.h53
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/dma.h66
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/emc.h99
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/gpio.h42
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/gpio_grp.h39
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/i2c.h37
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/mux.h34
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/sys_proto.h22
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/timer.h60
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/uart.h100
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/wdt.h37
13 files changed, 0 insertions, 847 deletions
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h
deleted file mode 100644
index 5ab48a9..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- */
-
-#ifndef _LPC32XX_CLK_H
-#define _LPC32XX_CLK_H
-
-#include <asm/types.h>
-
-#define OSC_CLK_FREQUENCY 13000000
-#define RTC_CLK_FREQUENCY 32768
-
-/* Clocking and Power Control Registers */
-struct clk_pm_regs {
- u32 reserved0[5];
- u32 boot_map; /* Boot Map Control Register */
- u32 p0_intr_er; /* Port 0/1 Start and Interrupt Enable */
- u32 usbdiv_ctrl; /* USB Clock Pre-Divide Register */
- /* Internal Start Signal Sources Registers */
- u32 start_er_int; /* Start Enable Register */
- u32 start_rsr_int; /* Start Raw Status Register */
- u32 start_sr_int; /* Start Status Register */
- u32 start_apr_int; /* Start Activation Polarity Register */
- /* Device Pin Start Signal Sources Registers */
- u32 start_er_pin; /* Start Enable Register */
- u32 start_rsr_pin; /* Start Raw Status Register */
- u32 start_sr_pin; /* Start Status Register */
- u32 start_apr_pin; /* Start Activation Polarity Register */
- /* Clock Control Registers */
- u32 hclkdiv_ctrl; /* HCLK Divider Control Register */
- u32 pwr_ctrl; /* Power Control Register */
- u32 pll397_ctrl; /* PLL397 Control Register */
- u32 osc_ctrl; /* Main Oscillator Control Register */
- u32 sysclk_ctrl; /* SYSCLK Control Register */
- u32 lcdclk_ctrl; /* LCD Clock Control Register */
- u32 hclkpll_ctrl; /* HCLK PLL Control Register */
- u32 reserved1;
- u32 adclk_ctrl1; /* ADC Clock Control1 Register */
- u32 usb_ctrl; /* USB Control Register */
- u32 sdramclk_ctrl; /* SDRAM Clock Control Register */
- u32 ddr_lap_nom; /* DDR Calibration Nominal Value */
- u32 ddr_lap_count; /* DDR Calibration Measured Value */
- u32 ddr_cal_delay; /* DDR Calibration Delay Value */
- u32 ssp_ctrl; /* SSP Control Register */
- u32 i2s_ctrl; /* I2S Clock Control Register */
- u32 ms_ctrl; /* Memory Card Control Register */
- u32 reserved2[3];
- u32 macclk_ctrl; /* Ethernet MAC Clock Control Register */
- u32 reserved3[4];
- u32 test_clk; /* Test Clock Selection Register */
- u32 sw_int; /* Software Interrupt Register */
- u32 i2cclk_ctrl; /* I2C Clock Control Register */
- u32 keyclk_ctrl; /* Keyboard Scan Clock Control Register */
- u32 adclk_ctrl; /* ADC Clock Control Register */
- u32 pwmclk_ctrl; /* PWM Clock Control Register */
- u32 timclk_ctrl; /* Watchdog and Highspeed Timer Control */
- u32 timclk_ctrl1; /* Motor and Timer Clock Control */
- u32 spi_ctrl; /* SPI Control Register */
- u32 flashclk_ctrl; /* NAND Flash Clock Control Register */
- u32 reserved4;
- u32 u3clk; /* UART 3 Clock Control Register */
- u32 u4clk; /* UART 4 Clock Control Register */
- u32 u5clk; /* UART 5 Clock Control Register */
- u32 u6clk; /* UART 6 Clock Control Register */
- u32 irdaclk; /* IrDA Clock Control Register */
- u32 uartclk_ctrl; /* UART Clock Control Register */
- u32 dmaclk_ctrl; /* DMA Clock Control Register */
- u32 autoclk_ctrl; /* Autoclock Control Register */
-};
-
-/* HCLK Divider Control Register bits */
-#define CLK_HCLK_DDRAM_MASK (0x3 << 7)
-#define CLK_HCLK_DDRAM_HALF (0x2 << 7)
-#define CLK_HCLK_DDRAM_NOMINAL (0x1 << 7)
-#define CLK_HCLK_DDRAM_STOPPED (0x0 << 7)
-#define CLK_HCLK_PERIPH_DIV_MASK (0x1F << 2)
-#define CLK_HCLK_PERIPH_DIV(n) ((((n) - 1) & 0x1F) << 2)
-#define CLK_HCLK_ARM_PLL_DIV_MASK (0x3 << 0)
-#define CLK_HCLK_ARM_PLL_DIV_4 (0x2 << 0)
-#define CLK_HCLK_ARM_PLL_DIV_2 (0x1 << 0)
-#define CLK_HCLK_ARM_PLL_DIV_1 (0x0 << 0)
-
-/* Power Control Register bits */
-#define CLK_PWR_HCLK_RUN_PERIPH (1 << 10)
-#define CLK_PWR_EMC_SREFREQ (1 << 9)
-#define CLK_PWR_EMC_SREFREQ_UPDATE (1 << 8)
-#define CLK_PWR_SDRAM_SREFREQ (1 << 7)
-#define CLK_PWR_HIGHCORE_LEVEL (1 << 5)
-#define CLK_PWR_SYSCLKEN_LEVEL (1 << 4)
-#define CLK_PWR_SYSCLKEN_CTRL (1 << 3)
-#define CLK_PWR_NORMAL_RUN (1 << 2)
-#define CLK_PWR_HIGHCORE_CTRL (1 << 1)
-#define CLK_PWR_STOP_MODE (1 << 0)
-
-/* SYSCLK Control Register bits */
-#define CLK_SYSCLK_PLL397 (1 << 1)
-#define CLK_SYSCLK_MUX (1 << 0)
-
-/* HCLK PLL Control Register bits */
-#define CLK_HCLK_PLL_OPERATING (1 << 16)
-#define CLK_HCLK_PLL_BYPASS (1 << 15)
-#define CLK_HCLK_PLL_DIRECT (1 << 14)
-#define CLK_HCLK_PLL_FEEDBACK (1 << 13)
-#define CLK_HCLK_PLL_POSTDIV_MASK (0x3 << 11)
-#define CLK_HCLK_PLL_POSTDIV_16 (0x3 << 11)
-#define CLK_HCLK_PLL_POSTDIV_8 (0x2 << 11)
-#define CLK_HCLK_PLL_POSTDIV_4 (0x1 << 11)
-#define CLK_HCLK_PLL_POSTDIV_2 (0x0 << 11)
-#define CLK_HCLK_PLL_PREDIV_MASK (0x3 << 9)
-#define CLK_HCLK_PLL_PREDIV_4 (0x3 << 9)
-#define CLK_HCLK_PLL_PREDIV_3 (0x2 << 9)
-#define CLK_HCLK_PLL_PREDIV_2 (0x1 << 9)
-#define CLK_HCLK_PLL_PREDIV_1 (0x0 << 9)
-#define CLK_HCLK_PLL_FEEDBACK_DIV_MASK (0xFF << 1)
-#define CLK_HCLK_PLL_FEEDBACK_DIV(n) ((((n) - 1) & 0xFF) << 1)
-#define CLK_HCLK_PLL_LOCKED (1 << 0)
-
-/* Ethernet MAC Clock Control Register bits */
-#define CLK_MAC_RMII (0x3 << 3)
-#define CLK_MAC_MII (0x1 << 3)
-#define CLK_MAC_MASTER (1 << 2)
-#define CLK_MAC_SLAVE (1 << 1)
-#define CLK_MAC_REG (1 << 0)
-
-/* I2C Clock Control Register bits */
-#define CLK_I2C2_ENABLE (1 << 1)
-#define CLK_I2C1_ENABLE (1 << 0)
-
-/* Timer Clock Control1 Register bits */
-#define CLK_TIMCLK_MOTOR (1 << 6)
-#define CLK_TIMCLK_TIMER3 (1 << 5)
-#define CLK_TIMCLK_TIMER2 (1 << 4)
-#define CLK_TIMCLK_TIMER1 (1 << 3)
-#define CLK_TIMCLK_TIMER0 (1 << 2)
-#define CLK_TIMCLK_TIMER5 (1 << 1)
-#define CLK_TIMCLK_TIMER4 (1 << 0)
-
-/* Timer Clock Control Register bits */
-#define CLK_TIMCLK_HSTIMER (1 << 1)
-#define CLK_TIMCLK_WATCHDOG (1 << 0)
-
-/* UART Clock Control Register bits */
-#define CLK_UART(n) (1 << ((n) - 3))
-
-/* UARTn Clock Select Registers bits */
-#define CLK_UART_HCLK (1 << 16)
-#define CLK_UART_X_DIV(n) (((n) & 0xFF) << 8)
-#define CLK_UART_Y_DIV(n) (((n) & 0xFF) << 0)
-
-/* DMA Clock Control Register bits */
-#define CLK_DMA_ENABLE (1 << 0)
-
-/* NAND Clock Control Register bits */
-#define CLK_NAND_SLC (1 << 0)
-#define CLK_NAND_MLC (1 << 1)
-#define CLK_NAND_SLC_SELECT (1 << 2)
-#define CLK_NAND_MLC_INT (1 << 5)
-
-/* SSP Clock Control Register bits */
-#define CLK_SSP0_ENABLE_CLOCK (1 << 0)
-
-/* SDRAMCLK register bits */
-#define CLK_SDRAM_DDR_SEL (1 << 1)
-
-/* USB control register definitions */
-#define CLK_USBCTRL_PLL_STS (1 << 0)
-#define CLK_USBCTRL_FDBK_PLUS1(n) (((n) & 0xFF) << 1)
-#define CLK_USBCTRL_POSTDIV_2POW(n) (((n) & 0x3) << 11)
-#define CLK_USBCTRL_PLL_PWRUP (1 << 16)
-#define CLK_USBCTRL_CLK_EN1 (1 << 17)
-#define CLK_USBCTRL_CLK_EN2 (1 << 18)
-#define CLK_USBCTRL_BUS_KEEPER (0x1 << 19)
-#define CLK_USBCTRL_USBHSTND_EN (1 << 21)
-#define CLK_USBCTRL_USBDVND_EN (1 << 22)
-#define CLK_USBCTRL_HCLK_EN (1 << 24)
-
-unsigned int get_sys_clk_rate(void);
-unsigned int get_hclk_pll_rate(void);
-unsigned int get_hclk_clk_div(void);
-unsigned int get_hclk_clk_rate(void);
-unsigned int get_periph_clk_div(void);
-unsigned int get_periph_clk_rate(void);
-unsigned int get_sdram_clk_rate(void);
-
-#endif /* _LPC32XX_CLK_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
deleted file mode 100644
index 0836091..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Common definitions for LPC32XX board configurations
- *
- * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
- */
-
-#ifndef _LPC32XX_CONFIG_H
-#define _LPC32XX_CONFIG_H
-
-
-/* Basic CPU architecture */
-
-/* UART configuration */
-#if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
- (CONFIG_SYS_LPC32XX_UART == 7)
-#if !defined(CONFIG_LPC32XX_HSUART)
-#define CONFIG_LPC32XX_HSUART
-#endif
-#endif
-
-#if !defined(CONFIG_SYS_NS16550_CLK)
-#define CONFIG_SYS_NS16550_CLK 13000000
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
-
-/* Ethernet */
-#define LPC32XX_ETH_BASE ETHERNET_BASE
-
-/* NAND */
-#if defined(CONFIG_NAND_LPC32XX_SLC)
-#define NAND_LARGE_BLOCK_PAGE_SIZE 0x800
-#define NAND_SMALL_BLOCK_PAGE_SIZE 0x200
-
-#if !defined(CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE
-#endif
-
-#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE)
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
- 48, 49, 50, 51, 52, 53, 54, 55, \
- 56, 57, 58, 59, 60, 61, 62, 63, }
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
-#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE)
-#define CONFIG_SYS_NAND_OOBSIZE 16
-#define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, }
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-#else
-#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value"
-#endif
-
-#define CONFIG_SYS_NAND_ECCSIZE 0x100
-#define CONFIG_SYS_NAND_ECCBYTES 3
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#endif /* CONFIG_NAND_LPC32XX_SLC */
-
-/* NOR Flash */
-
-/* USB OHCI */
-#if defined(CONFIG_USB_OHCI_LPC32XX)
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_USB_OHCI_CPU_INIT
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lpc32xx-ohci"
-#endif
-
-#endif /* _LPC32XX_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h b/arch/arm/include/asm/arch-lpc32xx/cpu.h
deleted file mode 100644
index 7e0b781..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/cpu.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- */
-
-#ifndef _LPC32XX_CPU_H
-#define _LPC32XX_CPU_H
-
-/* LPC32XX Memory map */
-
-/* AHB physical base addresses */
-#define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */
-#define SSP0_BASE 0x20084000 /* SSP0 registers base */
-#define SD_CARD_BASE 0x20098000 /* SD card interface registers base */
-#define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */
-#define DMA_BASE 0x31000000 /* DMA controller registers base */
-#define USB_BASE 0x31020000 /* USB registers base */
-#define LCD_BASE 0x31040000 /* LCD registers base */
-#define ETHERNET_BASE 0x31060000 /* Ethernet registers base */
-#define EMC_BASE 0x31080000 /* EMC configuration registers base */
-
-/* FAB peripherals base addresses */
-#define CLK_PM_BASE 0x40004000 /* System control registers base */
-#define HS_UART1_BASE 0x40014000 /* High speed UART 1 registers base */
-#define HS_UART2_BASE 0x40018000 /* High speed UART 2 registers base */
-#define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */
-#define RTC_BASE 0x40024000 /* RTC registers base */
-#define GPIO_BASE 0x40028000 /* GPIO registers base */
-#define MUX_BASE 0x40028000 /* MUX registers base */
-#define WDT_BASE 0x4003C000 /* Watchdog timer registers base */
-#define TIMER0_BASE 0x40044000 /* Timer0 registers base */
-#define TIMER1_BASE 0x4004C000 /* Timer1 registers base */
-#define UART_CTRL_BASE 0x40054000 /* UART control regsisters base */
-
-/* APB peripherals base addresses */
-#define UART3_BASE 0x40080000 /* UART 3 registers base */
-#define UART4_BASE 0x40088000 /* UART 4 registers base */
-#define UART5_BASE 0x40090000 /* UART 5 registers base */
-#define UART6_BASE 0x40098000 /* UART 6 registers base */
-#define I2C1_BASE 0x400A0000 /* I2C 1 registers base */
-#define I2C2_BASE 0x400A8000 /* I2C 2 registers base */
-
-/* External SDRAM Memory Bank base addresses */
-#define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */
-#define EMC_DYCS1_BASE 0xA0000000 /* SDRAM DYCS1 base address */
-
-/* External Static Memory Bank base addresses */
-#define EMC_CS0_BASE 0xE0000000
-#define EMC_CS1_BASE 0xE1000000
-#define EMC_CS2_BASE 0xE2000000
-#define EMC_CS3_BASE 0xE3000000
-
-#endif /* _LPC32XX_CPU_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/dma.h b/arch/arm/include/asm/arch-lpc32xx/dma.h
deleted file mode 100644
index 8775491..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/dma.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * LPC32xx DMA Controller Interface
- *
- * Copyright (C) 2008 by NXP Semiconductors
- * @Author: Kevin Wells
- * @Descr: Definitions for LPC3250 chip
- * @References: NXP LPC3250 User's Guide
- */
-
-#ifndef _LPC32XX_DMA_H
-#define _LPC32XX_DMA_H
-
-#include <common.h>
-
-/*
- * DMA linked list structure used with a channel's LLI register;
- * refer to UM10326, "LPC32x0 and LPC32x0/01 User manual" - Rev. 3
- * tables 84, 85, 86 & 87 for details.
- */
-struct lpc32xx_dmac_ll {
- u32 dma_src;
- u32 dma_dest;
- u32 next_lli;
- u32 next_ctrl;
-};
-
-/* control register definitions */
-#define DMAC_CHAN_INT_TC_EN (1 << 31) /* channel terminal count interrupt */
-#define DMAC_CHAN_DEST_AUTOINC (1 << 27) /* automatic destination increment */
-#define DMAC_CHAN_SRC_AUTOINC (1 << 26) /* automatic source increment */
-#define DMAC_CHAN_DEST_AHB1 (1 << 25) /* AHB1 master for dest. transfer */
-#define DMAC_CHAN_DEST_WIDTH_32 (1 << 22) /* Destination data width selection */
-#define DMAC_CHAN_SRC_WIDTH_32 (1 << 19) /* Source data width selection */
-#define DMAC_CHAN_DEST_BURST_1 0
-#define DMAC_CHAN_DEST_BURST_4 (1 << 15) /* Destination data burst size */
-#define DMAC_CHAN_SRC_BURST_1 0
-#define DMAC_CHAN_SRC_BURST_4 (1 << 12) /* Source data burst size */
-
-/*
- * config_ch register definitions
- * DMAC_CHAN_FLOW_D_xxx: flow control with DMA as the controller
- * DMAC_DEST_PERIP: Macro for loading destination peripheral
- * DMAC_SRC_PERIP: Macro for loading source peripheral
- */
-#define DMAC_CHAN_FLOW_D_M2P (0x1 << 11)
-#define DMAC_CHAN_FLOW_D_P2M (0x2 << 11)
-#define DMAC_DEST_PERIP(n) (((n) & 0x1F) << 6)
-#define DMAC_SRC_PERIP(n) (((n) & 0x1F) << 1)
-
-/*
- * config_ch register definitions
- * (source and destination peripheral ID numbers).
- * These can be used with the DMAC_DEST_PERIP and DMAC_SRC_PERIP macros.
- */
-#define DMA_PERID_NAND1 1
-
-/* Channel enable bit */
-#define DMAC_CHAN_ENABLE (1 << 0)
-
-int lpc32xx_dma_get_channel(void);
-int lpc32xx_dma_start_xfer(unsigned int channel,
- const struct lpc32xx_dmac_ll *desc, u32 config);
-int lpc32xx_dma_wait_status(unsigned int channel);
-
-#endif /* _LPC32XX_DMA_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/emc.h b/arch/arm/include/asm/arch-lpc32xx/emc.h
deleted file mode 100644
index 20698a3..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/emc.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- */
-
-#ifndef _LPC32XX_EMC_H
-#define _LPC32XX_EMC_H
-
-#include <asm/types.h>
-
-/* EMC Registers */
-struct emc_regs {
- u32 ctrl; /* Controls operation of the EMC */
- u32 status; /* Provides EMC status information */
- u32 config; /* Configures operation of the EMC */
- u32 reserved0[5];
- u32 control; /* Controls dyn memory operation */
- u32 refresh; /* Configures dyn memory refresh operation */
- u32 read_config; /* Configures the dyn memory read strategy */
- u32 reserved1;
- u32 t_rp; /* Precharge command period */
- u32 t_ras; /* Active to precharge command period */
- u32 t_srex; /* Self-refresh exit time */
- u32 reserved2[2];
- u32 t_wr; /* Write recovery time */
- u32 t_rc; /* Active to active command period */
- u32 t_rfc; /* Auto-refresh period */
- u32 t_xsr; /* Exit self-refresh to active command time */
- u32 t_rrd; /* Active bank A to active bank B latency */
- u32 t_mrd; /* Load mode register to active command time */
- u32 t_cdlr; /* Last data in to read command time */
- u32 reserved3[8];
- u32 extended_wait; /* time for static memory rd/wr transfers */
- u32 reserved4[31];
- u32 config0; /* Configuration information for the SDRAM */
- u32 rascas0; /* RAS and CAS latencies for the SDRAM */
- u32 reserved5[6];
- u32 config1; /* Configuration information for the SDRAM */
- u32 rascas1; /* RAS and CAS latencies for the SDRAM */
- u32 reserved6[54];
- struct emc_stat_t {
- u32 config; /* Static memory configuration */
- u32 waitwen; /* Delay from chip select to write enable */
- u32 waitoen; /* Delay to output enable */
- u32 waitrd; /* Delay to a read access */
- u32 waitpage; /* Delay for async page mode read */
- u32 waitwr; /* Delay to a write access */
- u32 waitturn; /* Number of bus turnaround cycles */
- u32 reserved;
- } stat[4];
- u32 reserved7[96];
- struct emc_ahb_t {
- u32 control; /* Control register for AHB */
- u32 status; /* Status register for AHB */
- u32 timeout; /* Timeout register for AHB */
- u32 reserved[5];
- } ahb[5];
-};
-
-/* Static Memory Configuration Register bits */
-#define EMC_STAT_CONFIG_WP (1 << 20)
-#define EMC_STAT_CONFIG_EW (1 << 8)
-#define EMC_STAT_CONFIG_PB (1 << 7)
-#define EMC_STAT_CONFIG_PC (1 << 6)
-#define EMC_STAT_CONFIG_PM (1 << 3)
-#define EMC_STAT_CONFIG_32BIT (2 << 0)
-#define EMC_STAT_CONFIG_16BIT (1 << 0)
-#define EMC_STAT_CONFIG_8BIT (0 << 0)
-
-/* Static Memory Delay Registers */
-#define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F)
-#define EMC_STAT_WAITOEN(n) ((n) & 0x0F)
-#define EMC_STAT_WAITRD(n) (((n) - 1) & 0x1F)
-#define EMC_STAT_WAITPAGE(n) (((n) - 1) & 0x1F)
-#define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F)
-#define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F)
-
-/* EMC settings for DRAM */
-struct emc_dram_settings {
- u32 cmddelay;
- u32 config0;
- u32 rascas0;
- u32 rdconfig;
- u32 trp;
- u32 tras;
- u32 tsrex;
- u32 twr;
- u32 trc;
- u32 trfc;
- u32 txsr;
- u32 trrd;
- u32 tmrd;
- u32 tcdlr;
- u32 refresh;
- u32 mode;
- u32 emode;
-};
-
-#endif /* _LPC32XX_EMC_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio.h b/arch/arm/include/asm/arch-lpc32xx/gpio.h
deleted file mode 100644
index 93e7a88..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/gpio.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * LPC32xx GPIO interface
- *
- * (C) Copyright 2014 DENX Software Engineering GmbH
- * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
- */
-
-/**
- * GPIO Register map for LPC32xx
- */
-
-struct gpio_regs {
- u32 p3_inp_state;
- u32 p3_outp_set;
- u32 p3_outp_clr;
- u32 p3_outp_state;
- /* Watch out! the following are shared between p2 and p3 */
- u32 p2_p3_dir_set;
- u32 p2_p3_dir_clr;
- u32 p2_p3_dir_state;
- /* Now back to 'one register for one port' */
- u32 p2_inp_state;
- u32 p2_outp_set;
- u32 p2_outp_clr;
- u32 reserved1[6];
- u32 p0_inp_state;
- u32 p0_outp_set;
- u32 p0_outp_clr;
- u32 p0_outp_state;
- u32 p0_dir_set;
- u32 p0_dir_clr;
- u32 p0_dir_state;
- u32 reserved2;
- u32 p1_inp_state;
- u32 p1_outp_set;
- u32 p1_outp_clr;
- u32 p1_outp_state;
- u32 p1_dir_set;
- u32 p1_dir_clr;
- u32 p1_dir_state;
-};
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h b/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
deleted file mode 100644
index 762bbee..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * LPC32xx GPIO interface macro for pin mapping.
- *
- * (C) Copyright 2015 DENX Software Engineering GmbH
- * Written-by: Sylvain Lemieux <slemieux@@tycoint.com>
- */
-
-#ifndef _LPC32XX_GPIO_GRP_H
-#define _LPC32XX_GPIO_GRP_H
-
-/*
- * Macro to map the pin for the lpc32xx_gpio driver.
- * Note: - GPIOS are considered here as homogeneous and linear from 0 to 159;
- * mapping is done per register, as group of 32.
- * (see drivers/gpio/lpc32xx_gpio.c for details).
- * - macros can be use with the following pins:
- * P0.0 - P0.7
- * P1.0 - P1.23
- * P2.0 - P2.12
- * P3 GPI_0 - GPI_9 / GPI_15 - GPI_23 / GPI_25 / GPI_27 - GPI_28
- * P3 GPO_0 - GPO_23
- * P3 GPIO_0 - GPIO_5 (output register only)
- */
-#define LPC32XX_GPIO_P0_GRP 0
-#define LPC32XX_GPIO_P1_GRP 32
-#define LPC32XX_GPIO_P2_GRP 64
-#define LPC32XX_GPO_P3_GRP 96
-#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25)
-#define LPC32XX_GPI_P3_GRP 128
-
-/*
- * A specific GPIO can be selected with this macro
- * ie, GPIO P0.1 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P0_GRP, 1)
- * See the LPC32x0 User's guide for GPIO group numbers
- */
-#define LPC32XX_GPIO(x, y) ((x) + (y))
-
-#endif /* _LPC32XX_GPIO_GRP_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/i2c.h b/arch/arm/include/asm/arch-lpc32xx/i2c.h
deleted file mode 100644
index 5301d4c..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/i2c.h
+++ /dev/null
@@ -1,37 +0,0 @@
-#ifndef _LPC32XX_I2C_H
-#define _LPC32XX_I2C_H
-
-#include <common.h>
-#include <asm/types.h>
-
-/* i2c register set */
-struct lpc32xx_i2c_base {
- union {
- u32 rx;
- u32 tx;
- };
- u32 stat;
- u32 ctrl;
- u32 clk_hi;
- u32 clk_lo;
- u32 adr;
- u32 rxfl;
- u32 txfl;
- u32 rxb;
- u32 txb;
- u32 stx;
- u32 stxfl;
-};
-
-#ifdef CONFIG_DM_I2C
-enum {
- I2C_0, I2C_1, I2C_2,
-};
-
-struct lpc32xx_i2c_dev {
- struct lpc32xx_i2c_base *base;
- int index;
- uint speed;
-};
-#endif /* CONFIG_DM_I2C */
-#endif /* _LPC32XX_I2C_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/mux.h b/arch/arm/include/asm/arch-lpc32xx/mux.h
deleted file mode 100644
index d661e82..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/mux.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * LPC32xx MUX interface
- *
- * (C) Copyright 2015 DENX Software Engineering GmbH
- * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
- */
-
-/**
- * MUX register map for LPC32xx
- */
-
-struct mux_regs {
- u32 reserved1[10];
- u32 p2_mux_set;
- u32 p2_mux_clr;
- u32 p2_mux_state;
- u32 reserved2[51];
- u32 p_mux_set;
- u32 p_mux_clr;
- u32 p_mux_state;
- u32 reserved3;
- u32 p3_mux_set;
- u32 p3_mux_clr;
- u32 p3_mux_state;
- u32 reserved4;
- u32 p0_mux_set;
- u32 p0_mux_clr;
- u32 p0_mux_state;
- u32 reserved5;
- u32 p1_mux_set;
- u32 p1_mux_clr;
- u32 p1_mux_state;
-};
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
deleted file mode 100644
index 4675dc3..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
- */
-
-#ifndef _LPC32XX_SYS_PROTO_H
-#define _LPC32XX_SYS_PROTO_H
-
-#include <asm/arch/emc.h>
-
-void lpc32xx_uart_init(unsigned int uart_id);
-void lpc32xx_dma_init(void);
-void lpc32xx_mac_init(void);
-void lpc32xx_mlc_nand_init(void);
-void lpc32xx_slc_nand_init(void);
-void lpc32xx_i2c_init(unsigned int devnum);
-void lpc32xx_ssp_init(void);
-void lpc32xx_usb_init(void);
-#if defined(CONFIG_SPL_BUILD)
-void ddr_init(const struct emc_dram_settings *dram);
-#endif
-#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/timer.h b/arch/arm/include/asm/arch-lpc32xx/timer.h
deleted file mode 100644
index 302bd6b..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/timer.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- */
-
-#ifndef _LPC32XX_TIMER_H
-#define _LPC32XX_TIMER_H
-
-#include <asm/types.h>
-
-/* Timer/Counter Registers */
-struct timer_regs {
- u32 ir; /* Interrupt Register */
- u32 tcr; /* Timer Control Register */
- u32 tc; /* Timer Counter */
- u32 pr; /* Prescale Register */
- u32 pc; /* Prescale Counter */
- u32 mcr; /* Match Control Register */
- u32 mr[4]; /* Match Registers */
- u32 ccr; /* Capture Control Register */
- u32 cr[4]; /* Capture Registers */
- u32 emr; /* External Match Register */
- u32 reserved[12];
- u32 ctcr; /* Count Control Register */
-};
-
-/* Timer/Counter Interrupt Register bits */
-#define TIMER_IR_CR(n) (1 << ((n) + 4))
-#define TIMER_IR_MR(n) (1 << (n))
-
-/* Timer/Counter Timer Control Register bits */
-#define TIMER_TCR_COUNTER_RESET (1 << 1)
-#define TIMER_TCR_COUNTER_ENABLE (1 << 0)
-#define TIMER_TCR_COUNTER_DISABLE (0 << 0)
-
-/* Timer/Counter Match Control Register bits */
-#define TIMER_MCR_STOP(n) (1 << (3 * (n) + 2))
-#define TIMER_MCR_RESET(n) (1 << (3 * (n) + 1))
-#define TIMER_MCR_INTERRUPT(n) (1 << (3 * (n)))
-
-/* Timer/Counter Capture Control Register bits */
-#define TIMER_CCR_INTERRUPT(n) (1 << (3 * (n) + 2))
-#define TIMER_CCR_FALLING_EDGE(n) (1 << (3 * (n) + 1))
-#define TIMER_CCR_RISING_EDGE(n) (1 << (3 * (n)))
-
-/* Timer/Counter External Match Register bits */
-#define TIMER_EMR_EMC_TOGGLE(n) (0x3 << (2 * (n) + 4))
-#define TIMER_EMR_EMC_SET(n) (0x2 << (2 * (n) + 4))
-#define TIMER_EMR_EMC_CLEAR(n) (0x1 << (2 * (n) + 4))
-#define TIMER_EMR_EMC_NOTHING(n) (0x0 << (2 * (n) + 4))
-#define TIMER_EMR_EM(n) (1 << (n))
-
-/* Timer/Counter Count Control Register bits */
-#define TIMER_CTCR_INPUT(n) ((n) << 2)
-#define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0)
-#define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0)
-#define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0)
-#define TIMER_CTCR_MODE_TIMER (0x0 << 0)
-
-#endif /* _LPC32XX_TIMER_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/uart.h b/arch/arm/include/asm/arch-lpc32xx/uart.h
deleted file mode 100644
index 8ffd867..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/uart.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- */
-
-#ifndef _LPC32XX_UART_H
-#define _LPC32XX_UART_H
-
-#include <asm/types.h>
-
-/* 14-clock UART Registers */
-struct hsuart_regs {
- union {
- u32 rx; /* Receiver FIFO */
- u32 tx; /* Transmitter FIFO */
- };
- u32 level; /* FIFO Level Register */
- u32 iir; /* Interrupt ID Register */
- u32 ctrl; /* Control Register */
- u32 rate; /* Rate Control Register */
-};
-
-/* 14-clock UART Receiver FIFO Register bits */
-#define HSUART_RX_BREAK (1 << 10)
-#define HSUART_RX_ERROR (1 << 9)
-#define HSUART_RX_EMPTY (1 << 8)
-#define HSUART_RX_DATA (0xff << 0)
-
-/* 14-clock UART Level Register bits */
-#define HSUART_LEVEL_TX (0xff << 8)
-#define HSUART_LEVEL_RX (0xff << 0)
-
-/* 14-clock UART Interrupt Identification Register bits */
-#define HSUART_IIR_TX_INT_SET (1 << 6)
-#define HSUART_IIR_RX_OE (1 << 5)
-#define HSUART_IIR_BRK (1 << 4)
-#define HSUART_IIR_FE (1 << 3)
-#define HSUART_IIR_RX_TIMEOUT (1 << 2)
-#define HSUART_IIR_RX_TRIG (1 << 1)
-#define HSUART_IIR_TX (1 << 0)
-
-/* 14-clock UART Control Register bits */
-#define HSUART_CTRL_HRTS_INV (1 << 21)
-#define HSUART_CTRL_HRTS_TRIG_48 (0x3 << 19)
-#define HSUART_CTRL_HRTS_TRIG_32 (0x2 << 19)
-#define HSUART_CTRL_HRTS_TRIG_16 (0x1 << 19)
-#define HSUART_CTRL_HRTS_TRIG_8 (0x0 << 19)
-#define HSUART_CTRL_HRTS_EN (1 << 18)
-#define HSUART_CTRL_TMO_16 (0x3 << 16)
-#define HSUART_CTRL_TMO_8 (0x2 << 16)
-#define HSUART_CTRL_TMO_4 (0x1 << 16)
-#define HSUART_CTRL_TMO_DISABLED (0x0 << 16)
-#define HSUART_CTRL_HCTS_INV (1 << 15)
-#define HSUART_CTRL_HCTS_EN (1 << 14)
-#define HSUART_CTRL_HSU_OFFSET(n) ((n) << 9)
-#define HSUART_CTRL_HSU_BREAK (1 << 8)
-#define HSUART_CTRL_HSU_ERR_INT_EN (1 << 7)
-#define HSUART_CTRL_HSU_RX_INT_EN (1 << 6)
-#define HSUART_CTRL_HSU_TX_INT_EN (1 << 5)
-#define HSUART_CTRL_HSU_RX_TRIG_48 (0x5 << 2)
-#define HSUART_CTRL_HSU_RX_TRIG_32 (0x4 << 2)
-#define HSUART_CTRL_HSU_RX_TRIG_16 (0x3 << 2)
-#define HSUART_CTRL_HSU_RX_TRIG_8 (0x2 << 2)
-#define HSUART_CTRL_HSU_RX_TRIG_4 (0x1 << 2)
-#define HSUART_CTRL_HSU_RX_TRIG_1 (0x0 << 2)
-#define HSUART_CTRL_HSU_TX_TRIG_16 (0x3 << 0)
-#define HSUART_CTRL_HSU_TX_TRIG_8 (0x2 << 0)
-#define HSUART_CTRL_HSU_TX_TRIG_4 (0x1 << 0)
-#define HSUART_CTRL_HSU_TX_TRIG_0 (0x0 << 0)
-
-/* UART Control Registers */
-struct uart_ctrl_regs {
- u32 ctrl; /* Control Register */
- u32 clkmode; /* Clock Mode Register */
- u32 loop; /* Loopback Control Register */
-};
-
-/* UART Control Register bits */
-#define UART_CTRL_UART3_MD_CTRL (1 << 11)
-#define UART_CTRL_HDPX_INV (1 << 10)
-#define UART_CTRL_HDPX_EN (1 << 9)
-#define UART_CTRL_UART6_IRDA (1 << 5)
-#define UART_CTRL_IR_TX6_INV (1 << 4)
-#define UART_CTRL_IR_RX6_INV (1 << 3)
-#define UART_CTRL_IR_RX_LENGTH (1 << 2)
-#define UART_CTRL_IR_TX_LENGTH (1 << 1)
-#define UART_CTRL_UART5_USB_MODE (1 << 0)
-
-/* UART Clock Mode Register bits */
-#define UART_CLKMODE_STATX(n) (1 << ((n) + 16))
-#define UART_CLKMODE_STAT (1 << 14)
-#define UART_CLKMODE_MASK(n) (0x3 << (2 * (n) - 2))
-#define UART_CLKMODE_AUTO(n) (0x2 << (2 * (n) - 2))
-#define UART_CLKMODE_ON(n) (0x1 << (2 * (n) - 2))
-#define UART_CLKMODE_OFF(n) (0x0 << (2 * (n) - 2))
-
-/* UART Loopback Control Register bits */
-#define UART_LOOPBACK(n) (1 << ((n) - 1))
-
-#endif /* _LPC32XX_UART_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/wdt.h b/arch/arm/include/asm/arch-lpc32xx/wdt.h
deleted file mode 100644
index dd0fc16..0000000
--- a/arch/arm/include/asm/arch-lpc32xx/wdt.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- */
-
-#ifndef _LPC32XX_WDT_H
-#define _LPC32XX_WDT_H
-
-#include <asm/types.h>
-
-/* Watchdog Timer Registers */
-struct wdt_regs {
- u32 isr; /* Interrupt Status Register */
- u32 ctrl; /* Control Register */
- u32 counter; /* Counter Value Register */
- u32 mctrl; /* Match Control Register */
- u32 match0; /* Match 0 Register */
- u32 emr; /* External Match Control Register */
- u32 pulse; /* Reset Pulse Length Register */
- u32 res; /* Reset Source Register */
-};
-
-/* Watchdog Timer Control Register bits */
-#define WDTIM_CTRL_PAUSE_EN (1 << 2)
-#define WDTIM_CTRL_RESET_COUNT (1 << 1)
-#define WDTIM_CTRL_COUNT_ENAB (1 << 0)
-
-/* Watchdog Timer Match Control Register bits */
-#define WDTIM_MCTRL_RESFRC2 (1 << 6)
-#define WDTIM_MCTRL_RESFRC1 (1 << 5)
-#define WDTIM_MCTRL_M_RES2 (1 << 4)
-#define WDTIM_MCTRL_M_RES1 (1 << 3)
-#define WDTIM_MCTRL_STOP_COUNT0 (1 << 2)
-#define WDTIM_MCTRL_RESET_COUNT0 (1 << 1)
-#define WDTIM_MCTRL_MR0_INT (1 << 0)
-
-#endif /* _LPC32XX_WDT_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-17 10:42:21 +0000