12 files changed, 0 insertions, 893 deletions
diff --git a/arch/arm/include/asm/arch-ls102xa/clock.h b/arch/arm/include/asm/arch-ls102xa/clock.h
deleted file mode 100644
index bf67df5..0000000
--- a/arch/arm/include/asm/arch-ls102xa/clock.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- */
-
-#ifndef __ASM_ARCH_LS102XA_CLOCK_H_
-#define __ASM_ARCH_LS102XA_CLOCK_H_
-
-#include <common.h>
-
-enum mxc_clock {
-	MXC_ARM_CLK = 0,
-	MXC_UART_CLK,
-	MXC_ESDHC_CLK,
-	MXC_I2C_CLK,
-	MXC_DSPI_CLK,
-};
-
-unsigned int mxc_get_clock(enum mxc_clock clk);
-ulong get_ddr_freq(ulong);
-uint get_svr(void);
-
-#endif /* __ASM_ARCH_LS102XA_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
deleted file mode 100644
index 9705378..0000000
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014, Freescale Semiconductor
- */
-
-#ifndef _ASM_ARMV7_LS102XA_CONFIG_
-#define _ASM_ARMV7_LS102XA_CONFIG_
-
-#define OCRAM_BASE_ADDR				0x10000000
-#define OCRAM_SIZE				0x00010000
-#define OCRAM_BASE_S_ADDR			0x10010000
-#define OCRAM_S_SIZE				0x00010000
-
-#define CONFIG_SYS_IMMR				0x01000000
-#define CONFIG_SYS_DCSRBAR			0x20000000
-
-#define CONFIG_SYS_DCSR_DCFG_ADDR	(CONFIG_SYS_DCSRBAR + 0x00220000)
-#define SYS_FSL_DCSR_RCPM_ADDR	(CONFIG_SYS_DCSRBAR + 0x00222000)
-
-#define SYS_FSL_GIC_ADDR			(CONFIG_SYS_IMMR + 0x00400000)
-#define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_FSL_CSU_ADDR                 (CONFIG_SYS_IMMR + 0x00510000)
-#define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
-#define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
-#define CONFIG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)
-#define CONFIG_SYS_FSL_SEC_ADDR			(CONFIG_SYS_IMMR + 0x700000)
-#define CONFIG_SYS_FSL_JR0_ADDR			(CONFIG_SYS_IMMR + 0x710000)
-#define CONFIG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0x00e90000)
-#define CONFIG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0x00e80200)
-#define CONFIG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
-#define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
-#define CONFIG_SYS_FSL_LS1_CLK_ADDR		(CONFIG_SYS_IMMR + 0x00ee1000)
-#define CONFIG_SYS_FSL_RCPM_ADDR		(CONFIG_SYS_IMMR + 0x00ee2000)
-#define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
-#define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011d0500)
-#define CONFIG_SYS_DCU_ADDR			(CONFIG_SYS_IMMR + 0x01ce0000)
-#define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_EHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x07600000)
-
-#define CONFIG_SYS_FSL_SEC_OFFSET		0x00700000
-#define CONFIG_SYS_FSL_JR0_OFFSET		0x00710000
-#define CONFIG_SYS_TSEC1_OFFSET			0x01d10000
-#define CONFIG_SYS_TSEC2_OFFSET			0x01d50000
-#define CONFIG_SYS_TSEC3_OFFSET			0x01d90000
-#define CONFIG_SYS_MDIO1_OFFSET			0x01d24000
-
-#define TSEC_BASE_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
-#define MDIO_BASE_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
-
-#define SCTR_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01b00000)
-
-#define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01180000)
-#define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01190000)
-#define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x011a0000)
-
-#define WDOG1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01ad0000)
-
-#define QSPI0_BASE_ADDR				(CONFIG_SYS_IMMR + 0x00550000)
-#define DSPI1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01100000)
-
-#define LPUART_BASE				(CONFIG_SYS_IMMR + 0x01950000)
-
-#define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
-#define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
-
-#define CONFIG_SYS_PCIE1_PHYS_BASE		0x4000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_BASE		0x4800000000ULL
-#define CONFIG_SYS_PCIE1_VIRT_ADDR		0x24000000UL
-#define CONFIG_SYS_PCIE2_VIRT_ADDR		0x34000000UL
-#define CONFIG_SYS_PCIE_MMAP_SIZE		(192 * 1024 * 1024) /* 192M */
-/*
- * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR)
- * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr.
- */
-#define CONFIG_SYS_PCIE1_PHYS_ADDR		(CONFIG_SYS_PCIE1_PHYS_BASE + \
-						 CONFIG_SYS_PCIE1_VIRT_ADDR)
-#define CONFIG_SYS_PCIE2_PHYS_ADDR		(CONFIG_SYS_PCIE2_PHYS_BASE + \
-						 CONFIG_SYS_PCIE2_VIRT_ADDR)
-
-/* SATA */
-#define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
-#define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
-#define CONFIG_SYS_SCSI_MAX_LUN		1
-#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
-						CONFIG_SYS_SCSI_MAX_LUN)
-#ifdef CONFIG_DDR_SPD
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED			CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
-#endif
-
-#define CONFIG_SYS_FSL_IFC_BE
-#define CONFIG_SYS_FSL_ESDHC_BE
-#define CONFIG_SYS_FSL_WDOG_BE
-#define CONFIG_SYS_FSL_DSPI_BE
-#define CONFIG_SYS_FSL_QSPI_BE
-#define CONFIG_SYS_FSL_DCU_BE
-#define CONFIG_SYS_FSL_SEC_MON_LE
-#define CONFIG_SYS_FSL_SFP_VER_3_2
-#define CONFIG_SYS_FSL_SFP_BE
-#define CONFIG_SYS_FSL_SRK_LE
-
-#define DCU_LAYER_MAX_NUM			16
-
-#ifdef CONFIG_ARCH_LS1021A
-#define CONFIG_USB_MAX_CONTROLLER_COUNT		1
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
-#else
-#error SoC not defined
-#endif
-
-#define FSL_IFC_COMPAT		"fsl,ifc"
-#define FSL_QSPI_COMPAT		"fsl,ls1021a-qspi"
-#define FSL_DSPI_COMPAT		"fsl,ls1021a-v1.0-dspi"
-
-#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h
deleted file mode 100644
index d99a6f3..0000000
--- a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __FSL_SERDES_H
-#define __FSL_SERDES_H
-
-#include <config.h>
-
-enum srds_prtcl {
-	/*
-	 * Nobody will check whether the device 'NONE' has been configured,
-	 * So use it to indicate if the serdes_prtcl_map has been initialized.
-	 */
-	NONE = 0,
-	PCIE1,
-	PCIE2,
-	SATA1,
-	SGMII_TSEC1,
-	SGMII_TSEC2,
-};
-
-enum srds {
-	FSL_SRDS_1  = 0,
-	FSL_SRDS_2  = 1,
-};
-
-int is_serdes_configured(enum srds_prtcl device);
-void fsl_serdes_init(void);
-const char *serdes_clock_to_string(u32 clock);
-
-int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
-enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
-
-#endif /* __FSL_SERDES_H */
diff --git a/arch/arm/include/asm/arch-ls102xa/gpio.h b/arch/arm/include/asm/arch-ls102xa/gpio.h
deleted file mode 100644
index dad181e..0000000
--- a/arch/arm/include/asm/arch-ls102xa/gpio.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-/*
- * Dummy header file to enable CONFIG_OF_CONTROL.
- * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
- * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
- * OF_CONTROL must have arch/gpio.h.
- */
-
-#ifndef __ASM_ARCH_LS102XA_GPIO_H_
-#define __ASM_ARCH_LS102XA_GPIO_H_
-
-#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
deleted file mode 100644
index f2ba182..0000000
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ /dev/null
@@ -1,432 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __ASM_ARCH_LS102XA_IMMAP_H_
-#define __ASM_ARCH_LS102XA_IMMAP_H_
-#include <fsl_immap.h>
-
-#define SVR_MAJ(svr)		(((svr) >>  4) & 0xf)
-#define SVR_MIN(svr)		(((svr) >>  0) & 0xf)
-#define SVR_SOC_VER(svr)	(((svr) >> 8) & 0x7ff)
-#define IS_E_PROCESSOR(svr)	(svr & 0x80000)
-#define IS_SVR_REV(svr, maj, min) \
-		((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min))
-
-#define SOC_VER_SLS1020		0x00
-#define SOC_VER_LS1020		0x10
-#define SOC_VER_LS1021		0x11
-#define SOC_VER_LS1022		0x12
-
-#define SOC_MAJOR_VER_1_0	0x1
-#define SOC_MAJOR_VER_2_0	0x2
-
-#define CCSR_BRR_OFFSET		0xe4
-#define CCSR_SCRATCHRW1_OFFSET	0x200
-
-#define RCWSR0_SYS_PLL_RAT_SHIFT	25
-#define RCWSR0_SYS_PLL_RAT_MASK		0x1f
-#define RCWSR0_MEM_PLL_RAT_SHIFT	16
-#define RCWSR0_MEM_PLL_RAT_MASK		0x3f
-
-#define RCWSR4_SRDS1_PRTCL_SHIFT	24
-#define RCWSR4_SRDS1_PRTCL_MASK		0xff000000
-
-#define TIMER_COMP_VAL			0xffffffffffffffffull
-#define ARCH_TIMER_CTRL_ENABLE		(1 << 0)
-#define SYS_COUNTER_CTRL_ENABLE		(1 << 24)
-
-#define DCFG_CCSR_PORSR1_RCW_MASK	0xff800000
-#define DCFG_CCSR_PORSR1_RCW_SRC_I2C	0x24800000
-
-#define DCFG_DCSR_PORCR1		0
-
-/*
- * Define default values for some CCSR macros to make header files cleaner
- *
- * To completely disable CCSR relocation in a board header file, define
- * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
- * to a value that is the same as CONFIG_SYS_CCSRBAR.
- */
-
-#ifdef CONFIG_SYS_CCSRBAR_PHYS
-#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly."
-#endif
-
-#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
-#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
-#endif
-
-#ifndef CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR		CONFIG_SYS_IMMR
-#endif
-
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0xf
-#else
-#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
-#endif
-#endif
-
-#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_IMMR
-#endif
-
-#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
-				 CONFIG_SYS_CCSRBAR_PHYS_LOW)
-
-struct sys_info {
-	unsigned long freq_processor[CONFIG_MAX_CPUS];
-	unsigned long freq_systembus;
-	unsigned long freq_ddrbus;
-	unsigned long freq_localbus;
-};
-
-#define CCSR_DEVDISR1_QE	0x00000001
-
-/* Device Configuration and Pin Control */
-struct ccsr_gur {
-	u32     porsr1;         /* POR status 1 */
-	u32     porsr2;         /* POR status 2 */
-	u8      res_008[0x20-0x8];
-	u32     gpporcr1;       /* General-purpose POR configuration */
-	u32	gpporcr2;
-	u32     dcfg_fusesr;    /* Fuse status register */
-	u8      res_02c[0x70-0x2c];
-	u32     devdisr;        /* Device disable control */
-	u32     devdisr2;       /* Device disable control 2 */
-	u32     devdisr3;       /* Device disable control 3 */
-	u32     devdisr4;       /* Device disable control 4 */
-	u32     devdisr5;       /* Device disable control 5 */
-	u8      res_084[0x94-0x84];
-	u32     coredisru;      /* uppper portion for support of 64 cores */
-	u32     coredisrl;      /* lower portion for support of 64 cores */
-	u8      res_09c[0xa4-0x9c];
-	u32     svr;            /* System version */
-	u8	res_0a8[0xb0-0xa8];
-	u32	rstcr;		/* Reset control */
-	u32	rstrqpblsr;	/* Reset request preboot loader status */
-	u8	res_0b8[0xc0-0xb8];
-	u32	rstrqmr1;	/* Reset request mask */
-	u8	res_0c4[0xc8-0xc4];
-	u32	rstrqsr1;	/* Reset request status */
-	u8	res_0cc[0xd4-0xcc];
-	u32	rstrqwdtmrl;	/* Reset request WDT mask */
-	u8	res_0d8[0xdc-0xd8];
-	u32	rstrqwdtsrl;	/* Reset request WDT status */
-	u8	res_0e0[0xe4-0xe0];
-	u32	brrl;		/* Boot release */
-	u8      res_0e8[0x100-0xe8];
-	u32     rcwsr[16];      /* Reset control word status */
-#define RCW_SB_EN_REG_INDEX	7
-#define RCW_SB_EN_MASK		0x00200000
-	u8      res_140[0x200-0x140];
-	u32     scratchrw[4];  /* Scratch Read/Write */
-	u8      res_210[0x300-0x210];
-	u32     scratchw1r[4];  /* Scratch Read (Write once) */
-	u8      res_310[0x400-0x310];
-	u32	crstsr;
-	u8      res_404[0x550-0x404];
-	u32	sataliodnr;
-	u8	res_554[0x604-0x554];
-	u32	pamubypenr;
-	u32	dmacr1;
-	u8      res_60c[0x740-0x60c];   /* add more registers when needed */
-	u32     tp_ityp[64];    /* Topology Initiator Type Register */
-	struct {
-		u32     upper;
-		u32     lower;
-	} tp_cluster[1];        /* Core Cluster n Topology Register */
-	u8	res_848[0xe60-0x848];
-	u32	ddrclkdr;
-	u8	res_e60[0xe68-0xe64];
-	u32	ifcclkdr;
-	u8	res_e68[0xe80-0xe6c];
-	u32	sdhcpcr;
-};
-
-#define SCFG_ETSECDMAMCR_LE_BD_FR	0x00000c00
-#define SCFG_SNPCNFGCR_SEC_RD_WR	0xc0000000
-#define SCFG_ETSECCMCR_GE2_CLK125	0x04000000
-#define SCFG_ETSECCMCR_GE0_CLK125	0x00000000
-#define SCFG_ETSECCMCR_GE1_CLK125	0x08000000
-#define SCFG_PIXCLKCR_PXCKEN		0x80000000
-#define SCFG_QSPI_CLKSEL		0x50100000
-#define SCFG_SNPCNFGCR_SEC_RD_WR	0xc0000000
-#define SCFG_SNPCNFGCR_DCU_RD_WR	0x03000000
-#define SCFG_SNPCNFGCR_SATA_RD_WR	0x00c00000
-#define SCFG_SNPCNFGCR_USB3_RD_WR	0x00300000
-#define SCFG_SNPCNFGCR_DBG_RD_WR	0x000c0000
-#define SCFG_SNPCNFGCR_EDMA_SNP		0x00020000
-#define SCFG_ENDIANCR_LE		0x80000000
-#define SCFG_DPSLPCR_WDRR_EN		0x00000001
-#define SCFG_PMCINTECR_LPUART		0x40000000
-#define SCFG_PMCINTECR_FTM		0x20000000
-#define SCFG_PMCINTECR_GPIO		0x10000000
-#define SCFG_PMCINTECR_IRQ0		0x08000000
-#define SCFG_PMCINTECR_IRQ1		0x04000000
-#define SCFG_PMCINTECR_ETSECRXG0	0x00800000
-#define SCFG_PMCINTECR_ETSECRXG1	0x00400000
-#define SCFG_PMCINTECR_ETSECERRG0	0x00080000
-#define SCFG_PMCINTECR_ETSECERRG1	0x00040000
-#define SCFG_CLUSTERPMCR_WFIL2EN	0x80000000
-
-#define SCFG_BASE			0x01570000
-#define SCFG_USB3PRM1CR			0x070
-#define SCFG_USB_TXVREFTUNE		0x9
-#define SCFG_USB_SQRXTUNE_MASK		0x7
-#define SCFG_USB3PRM2CR			0x074
-#define SCFG_USB_PCSTXSWINGFULL_MASK	0x0000FE00
-#define SCFG_USB_PCSTXSWINGFULL_VAL		0x00008E00
-
-#define USB_PHY_BASE			0x08510000
-#define USB_PHY_RX_OVRD_IN_HI	0x200c
-#define USB_PHY_RX_EQ_VAL_1		0x0000
-#define USB_PHY_RX_EQ_VAL_2		0x8000
-#define USB_PHY_RX_EQ_VAL_3		0x8004
-#define USB_PHY_RX_EQ_VAL_4		0x800C
-
-/* Supplemental Configuration Unit */
-struct ccsr_scfg {
-	u32 dpslpcr;
-	u32 resv0[2];
-	u32 etsecclkdpslpcr;
-	u32 resv1[5];
-	u32 fuseovrdcr;
-	u32 pixclkcr;
-	u32 resv2[5];
-	u32 spimsicr;
-	u32 resv3[6];
-	u32 pex1pmwrcr;
-	u32 pex1pmrdsr;
-	u32 resv4[3];
-	u32 usb3prm1cr;
-	u32 usb4prm2cr;
-	u32 pex1rdmsgpldlsbsr;
-	u32 pex1rdmsgpldmsbsr;
-	u32 pex2rdmsgpldlsbsr;
-	u32 pex2rdmsgpldmsbsr;
-	u32 pex1rdmmsgrqsr;
-	u32 pex2rdmmsgrqsr;
-	u32 spimsiclrcr;
-	u32 pexmscportsr[2];
-	u32 pex2pmwrcr;
-	u32 resv5[24];
-	u32 mac1_streamid;
-	u32 mac2_streamid;
-	u32 mac3_streamid;
-	u32 pex1_streamid;
-	u32 pex2_streamid;
-	u32 dma_streamid;
-	u32 sata_streamid;
-	u32 usb3_streamid;
-	u32 qe_streamid;
-	u32 sdhc_streamid;
-	u32 adma_streamid;
-	u32 letechsftrstcr;
-	u32 core0_sft_rst;
-	u32 core1_sft_rst;
-	u32 resv6[1];
-	u32 usb_hi_addr;
-	u32 etsecclkadjcr;
-	u32 sai_clk;
-	u32 resv7[1];
-	u32 dcu_streamid;
-	u32 usb2_streamid;
-	u32 ftm_reset;
-	u32 altcbar;
-	u32 qspi_cfg;
-	u32 pmcintecr;
-	u32 pmcintlecr;
-	u32 pmcintsr;
-	u32 qos1;
-	u32 qos2;
-	u32 qos3;
-	u32 cci_cfg;
-	u32 endiancr;
-	u32 etsecdmamcr;
-	u32 usb3prm3cr;
-	u32 resv9[1];
-	u32 debug_streamid;
-	u32 resv10[5];
-	u32 snpcnfgcr;
-	u32 hrstcr;
-	u32 intpcr;
-	u32 resv12[20];
-	u32 scfgrevcr;
-	u32 coresrencr;
-	u32 pex2pmrdsr;
-	u32 eddrtqcfg;
-	u32 ddrc2cr;
-	u32 ddrc3cr;
-	u32 ddrc4cr;
-	u32 ddrgcr;
-	u32 resv13[120];
-	u32 qeioclkcr;
-	u32 etsecmcr;
-	u32 sdhciovserlcr;
-	u32 resv14[61];
-	u32 sparecr[8];
-	u32 resv15[248];
-	u32 core0sftrstsr;
-	u32 clusterpmcr;
-};
-
-/* Clocking */
-struct ccsr_clk {
-	struct {
-		u32 clkcncsr;	/* core cluster n clock control status */
-		u8  res_004[0x1c];
-	} clkcsr[2];
-	u8	res_040[0x7c0]; /* 0x100 */
-	struct {
-		u32 pllcngsr;
-		u8 res_804[0x1c];
-	} pllcgsr[2];
-	u8	res_840[0x1c0];
-	u32	clkpcsr;	/* 0xa00 Platform clock domain control/status */
-	u8	res_a04[0x1fc];
-	u32	pllpgsr;	/* 0xc00 Platform PLL General Status */
-	u8	res_c04[0x1c];
-	u32	plldgsr;	/* 0xc20 DDR PLL General Status */
-	u8	res_c24[0x3dc];
-};
-
-/* System Counter */
-struct sctr_regs {
-	u32 cntcr;
-	u32 cntsr;
-	u32 cntcv1;
-	u32 cntcv2;
-	u32 resv1[4];
-	u32 cntfid0;
-	u32 cntfid1;
-	u32 resv2[1002];
-	u32 counterid[12];
-};
-
-#define MAX_SERDES			1
-#define SRDS_MAX_LANES			4
-#define SRDS_MAX_BANK			2
-
-#define SRDS_RSTCTL_RST			0x80000000
-#define SRDS_RSTCTL_RSTDONE		0x40000000
-#define SRDS_RSTCTL_RSTERR		0x20000000
-#define SRDS_RSTCTL_SWRST		0x10000000
-#define SRDS_RSTCTL_SDEN		0x00000020
-#define SRDS_RSTCTL_SDRST_B		0x00000040
-#define SRDS_RSTCTL_PLLRST_B		0x00000080
-#define SRDS_PLLCR0_POFF		0x80000000
-#define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
-#define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
-#define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
-#define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
-#define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
-#define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
-#define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
-#define SRDS_PLLCR0_PLL_LCK		0x00800000
-#define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
-#define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
-#define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
-#define SRDS_PLLCR0_FRATE_SEL_5_15	0x00060000
-#define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
-#define SRDS_PLLCR0_FRATE_SEL_3_12	0x00090000
-#define SRDS_PLLCR0_FRATE_SEL_3		0x000a0000
-#define SRDS_PLLCR1_PLL_BWSEL		0x08000000
-
-struct ccsr_serdes {
-	struct {
-		u32	rstctl;	/* Reset Control Register */
-
-		u32	pllcr0; /* PLL Control Register 0 */
-
-		u32	pllcr1; /* PLL Control Register 1 */
-		u32	res_0c;	/* 0x00c */
-		u32	pllcr3;
-		u32	pllcr4;
-		u8	res_18[0x20-0x18];
-	} bank[2];
-	u8	res_40[0x90-0x40];
-	u32	srdstcalcr;	/* 0x90 TX Calibration Control */
-	u8	res_94[0xa0-0x94];
-	u32	srdsrcalcr;	/* 0xa0 RX Calibration Control */
-	u8	res_a4[0xb0-0xa4];
-	u32	srdsgr0;	/* 0xb0 General Register 0 */
-	u8	res_b4[0xe0-0xb4];
-	u32	srdspccr0;	/* 0xe0 Protocol Converter Config 0 */
-	u32	srdspccr1;	/* 0xe4 Protocol Converter Config 1 */
-	u32	srdspccr2;	/* 0xe8 Protocol Converter Config 2 */
-	u32	srdspccr3;	/* 0xec Protocol Converter Config 3 */
-	u32	srdspccr4;	/* 0xf0 Protocol Converter Config 4 */
-	u8	res_f4[0x100-0xf4];
-	struct {
-		u32	lnpssr;	/* 0x100, 0x120, ..., 0x1e0 */
-		u8	res_104[0x120-0x104];
-	} srdslnpssr[4];
-	u8	res_180[0x300-0x180];
-	u32	srdspexeqcr;
-	u32	srdspexeqpcr[11];
-	u8	res_330[0x400-0x330];
-	u32	srdspexapcr;
-	u8	res_404[0x440-0x404];
-	u32	srdspexbpcr;
-	u8	res_444[0x800-0x444];
-	struct {
-		u32	gcr0;	/* 0x800 General Control Register 0 */
-		u32	gcr1;	/* 0x804 General Control Register 1 */
-		u32	gcr2;	/* 0x808 General Control Register 2 */
-		u32	sscr0;
-		u32	recr0;	/* 0x810 Receive Equalization Control */
-		u32	recr1;
-		u32	tecr0;	/* 0x818 Transmit Equalization Control */
-		u32	sscr1;
-		u32	ttlcr0;	/* 0x820 Transition Tracking Loop Ctrl 0 */
-		u8	res_824[0x83c-0x824];
-		u32	tcsr3;
-	} lane[4];	/* Lane A, B, C, D, E, F, G, H */
-	u8	res_a00[0x1000-0xa00];	/* from 0xa00 to 0xfff */
-};
-
-#define RCPM_POWMGTCSR			0x130
-#define RCPM_POWMGTCSR_SERDES_PW	0x80000000
-#define RCPM_POWMGTCSR_LPM20_REQ	0x00100000
-#define RCPM_POWMGTCSR_LPM20_ST		0x00000200
-#define RCPM_POWMGTCSR_P_LPM20_ST	0x00000100
-#define RCPM_IPPDEXPCR0			0x140
-#define RCPM_IPPDEXPCR0_ETSEC		0x80000000
-#define RCPM_IPPDEXPCR0_GPIO		0x00000040
-#define RCPM_IPPDEXPCR1			0x144
-#define RCPM_IPPDEXPCR1_LPUART		0x40000000
-#define RCPM_IPPDEXPCR1_FLEXTIMER	0x20000000
-#define RCPM_IPPDEXPCR1_OCRAM1		0x10000000
-#define RCPM_NFIQOUTR			0x15c
-#define RCPM_NIRQOUTR			0x16c
-#define RCPM_DSIMSKR			0x18c
-#define RCPM_CLPCL10SETR		0x1c4
-#define RCPM_CLPCL10SETR_C0		0x00000001
-
-struct ccsr_rcpm {
-	u8 rev1[0x4c];
-	u32 twaitsr;
-	u8 rev2[0xe0];
-	u32 powmgtcsr;
-	u8 rev3[0xc];
-	u32 ippdexpcr0;
-	u32 ippdexpcr1;
-	u8 rev4[0x14];
-	u32 nfiqoutr;
-	u8 rev5[0xc];
-	u32 nirqoutr;
-	u8 rev6[0x1c];
-	u32 dsimskr;
-	u8 rev7[0x34];
-	u32 clpcl10setr;
-};
-
-uint get_svr(void);
-
-#endif	/* __ASM_ARCH_LS102XA_IMMAP_H_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/imx-regs.h b/arch/arm/include/asm/arch-ls102xa/imx-regs.h
deleted file mode 100644
index 64853d8..0000000
--- a/arch/arm/include/asm/arch-ls102xa/imx-regs.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- */
-
-#ifndef __ASM_ARCH_IMX_REGS_H__
-#define __ASM_ARCH_IMX_REGS_H__
-
-#define I2C_QUIRK_REG	/* enable 8-bit driver */
-
-#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h
deleted file mode 100644
index 5d6a4e7..0000000
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-
-#ifndef __FSL_LS102XA_DEVDIS_H_
-#define __FSL_LS102XA_DEVDIS_H_
-
-#include <fsl_devdis.h>
-
-const struct devdis_table devdis_tbl[] = {
-	{ "pbl", 0x0, 0x80000000 },	/* PBL	*/
-	{ "esdhc", 0x0, 0x20000000 },	/* eSDHC	*/
-	{ "qdma", 0x0, 0x800000 },	/* qDMA		*/
-	{ "edma", 0x0, 0x400000 },	/* eDMA		*/
-	{ "usb3", 0x0, 0x84000 },	/* USB3.0 controller and PHY*/
-	{ "usb2", 0x0, 0x40000 },	/* USB2.0 controller	*/
-	{ "sata", 0x0, 0x8000 },	/* SATA		*/
-	{ "sec", 0x0, 0x200 },		/* SEC		*/
-	{ "dcu", 0x0, 0x2 },		/* Display controller Unit	*/
-	{ "qe", 0x0, 0x1 },		/* QUICC Engine	*/
-	{ "etsec1", 0x1, 0x80000000 },	/* eTSEC1 controller	*/
-	{ "etesc2", 0x1, 0x40000000 },	/* eTSEC2 controller	*/
-	{ "etsec3", 0x1, 0x20000000 },	/* eTSEC3 controller	*/
-	{ "pex1", 0x2, 0x80000000 },	/* PCIE controller 1	*/
-	{ "pex2", 0x2, 0x40000000 },	/* PCIE controller 2	*/
-	{ "duart1", 0x3, 0x20000000 },	/* DUART1	*/
-	{ "duart2", 0x3, 0x10000000 },	/* DUART2	*/
-	{ "qspi", 0x3, 0x8000000 },	/* QSPI		*/
-	{ "ddr", 0x4, 0x80000000 },	/* DDR		*/
-	{ "ocram1", 0x4, 0x8000000 },	/* OCRAM1	*/
-	{ "ifc", 0x4, 0x800000 },	/* IFC		*/
-	{ "gpio", 0x4, 0x400000 },	/* GPIO		*/
-	{ "dbg", 0x4, 0x200000 },	/* DBG		*/
-	{ "can1", 0x4, 0x80000 },	/* FlexCAN1	*/
-	{ "can2_4", 0x4, 0x40000 },	/* FlexCAN2_3_4	*/
-	{ "ftm2_8", 0x4, 0x20000 },	/* FlexTimer2_3_4_5_6_7_8	*/
-	{ "secmon", 0x4, 0x4000 },	/* Security Monitor	*/
-	{ "wdog1_2", 0x4, 0x400 },	/* WatchDog1_2	*/
-	{ "i2c2_3", 0x4, 0x200 },	/* I2C2_3	*/
-	{ "sai1_4", 0x4, 0x100 },	/* SAI1_2_3_4	*/
-	{ "lpuart2_6", 0x4, 0x80 },	/* LPUART2_3_4_5_6	*/
-	{ "dspi1_2", 0x4, 0x40 },	/* DSPI1_2	*/
-	{ "asrc", 0x4, 0x20 },		/* ASRC		*/
-	{ "spdif", 0x4, 0x10 },		/* SPDIF	*/
-	{ "i2c1", 0x4, 0x4 },		/* I2C1		*/
-	{ "lpuart1", 0x4, 0x2 },	/* LPUART1	*/
-	{ "ftm1", 0x4, 0x1 },		/* FlexTimer1	*/
-};
-
-#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
deleted file mode 100644
index 1fde8bc..0000000
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- */
-
-#ifndef __FSL_LS102XA_SOC_H
-#define __FSL_LS102XA_SOC_H
-
-unsigned int get_soc_major_rev(void);
-int arch_soc_init(void);
-int ls102xa_smmu_stream_id_init(void);
-
-void erratum_a008850_post(void);
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
-void erratum_a010315(void);
-#endif
-
-#endif /* __FSL_LS102XA_SOC_H */
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
deleted file mode 100644
index 93b0a26..0000000
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __FSL_LS102XA_STREAM_ID_H_
-#define __FSL_LS102XA_STREAM_ID_H_
-
-#include <fsl_sec.h>
-
-#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \
-	{ .compat = name, \
-	  .id = { idA }, .num_ids = 1, \
-	  .reg_offset = off + CONFIG_SYS_IMMR, \
-	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
-	}
-
-#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
-	{ .compat = name, \
-	  .id = { idA, idB }, .num_ids = 2, \
-	  .reg_offset = off + CONFIG_SYS_IMMR, \
-	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
-	}
-
-/*
- * handle both old and new versioned SEC properties:
- * "fsl,secX.Y" became "fsl,sec-vX.Y" during development
- */
-#define SET_SEC_JR_LIODN_ENTRY(jrnum, liodnA, liodnB) \
-	SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB, \
-		offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
-		CONFIG_SYS_FSL_SEC_OFFSET, \
-		CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \
-	SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
-		offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
-		CONFIG_SYS_FSL_SEC_OFFSET, \
-		CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
-
-/* This is a bit evil since we treat rtic param as both a string & hex value */
-#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
-	SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
-		liodnA,	\
-		offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
-		CONFIG_SYS_FSL_SEC_OFFSET, \
-		CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
-	SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
-		liodnA,	\
-		offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
-		CONFIG_SYS_FSL_SEC_OFFSET, \
-		CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
-
-#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
-	SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
-		offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
-		CONFIG_SYS_FSL_SEC_OFFSET, 0)
-
-struct liodn_id_table {
-	const char *compat;
-	u32 id[2];
-	u8 num_ids;
-	phys_addr_t compat_offset;
-	unsigned long reg_offset;
-};
-
-struct smmu_stream_id {
-	uint16_t offset;
-	uint16_t stream_id;
-	char dev_name[32];
-};
-
-void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size);
-void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
-#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h
deleted file mode 100644
index b6daf32..0000000
--- a/arch/arm/include/asm/arch-ls102xa/ns_access.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __FSL_NS_ACCESS_H_
-#define __FSL_NS_ACCESS_H_
-
-enum csu_cslx_ind {
-	CSU_CSLX_PCIE2_IO = 0,
-	CSU_CSLX_PCIE1_IO,
-	CSU_CSLX_MG2TPR_IP,
-	CSU_CSLX_IFC_MEM,
-	CSU_CSLX_OCRAM,
-	CSU_CSLX_GIC,
-	CSU_CSLX_PCIE1,
-	CSU_CSLX_OCRAM2,
-	CSU_CSLX_QSPI_MEM,
-	CSU_CSLX_PCIE2,
-	CSU_CSLX_SATA,
-	CSU_CSLX_USB3,
-	CSU_CSLX_SERDES = 32,
-	CSU_CSLX_QDMA,
-	CSU_CSLX_LPUART2,
-	CSU_CSLX_LPUART1,
-	CSU_CSLX_LPUART4,
-	CSU_CSLX_LPUART3,
-	CSU_CSLX_LPUART6,
-	CSU_CSLX_LPUART5,
-	CSU_CSLX_DSPI2 = 40,
-	CSU_CSLX_DSPI1,
-	CSU_CSLX_QSPI,
-	CSU_CSLX_ESDHC,
-	CSU_CSLX_2D_ACE,
-	CSU_CSLX_IFC,
-	CSU_CSLX_I2C1,
-	CSU_CSLX_USB2,
-	CSU_CSLX_I2C3,
-	CSU_CSLX_I2C2,
-	CSU_CSLX_DUART2 = 50,
-	CSU_CSLX_DUART1,
-	CSU_CSLX_WDT2,
-	CSU_CSLX_WDT1,
-	CSU_CSLX_EDMA,
-	CSU_CSLX_SYS_CNT,
-	CSU_CSLX_DMA_MUX2,
-	CSU_CSLX_DMA_MUX1,
-	CSU_CSLX_DDR,
-	CSU_CSLX_QUICC,
-	CSU_CSLX_DCFG_CCU_RCPM = 60,
-	CSU_CSLX_SECURE_BOOTROM,
-	CSU_CSLX_SFP,
-	CSU_CSLX_TMU,
-	CSU_CSLX_SECURE_MONITOR,
-	CSU_CSLX_RESERVED0,
-	CSU_CSLX_ETSEC1,
-	CSU_CSLX_SEC5_5,
-	CSU_CSLX_ETSEC3,
-	CSU_CSLX_ETSEC2,
-	CSU_CSLX_GPIO2 = 70,
-	CSU_CSLX_GPIO1,
-	CSU_CSLX_GPIO4,
-	CSU_CSLX_GPIO3,
-	CSU_CSLX_PLATFORM_CONT,
-	CSU_CSLX_CSU,
-	CSU_CSLX_ASRC,
-	CSU_CSLX_SPDIF,
-	CSU_CSLX_FLEXCAN2,
-	CSU_CSLX_FLEXCAN1,
-	CSU_CSLX_FLEXCAN4 = 80,
-	CSU_CSLX_FLEXCAN3,
-	CSU_CSLX_SAI2,
-	CSU_CSLX_SAI1,
-	CSU_CSLX_SAI4,
-	CSU_CSLX_SAI3,
-	CSU_CSLX_FTM2,
-	CSU_CSLX_FTM1,
-	CSU_CSLX_FTM4,
-	CSU_CSLX_FTM3,
-	CSU_CSLX_FTM6 = 90,
-	CSU_CSLX_FTM5,
-	CSU_CSLX_FTM8,
-	CSU_CSLX_FTM7,
-	CSU_CSLX_EPU,
-	CSU_CSLX_COP_DCSR,
-	CSU_CSLX_DDI,
-	CSU_CSLX_GDI,
-	CSU_CSLX_RESERVED1,
-	CSU_CSLX_USB3_PHY = 116,
-	CSU_CSLX_RESERVED2,
-	CSU_CSLX_MAX,
-};
-
-#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/soc.h b/arch/arm/include/asm/arch-ls102xa/soc.h
deleted file mode 100644
index e69de29..0000000
--- a/arch/arm/include/asm/arch-ls102xa/soc.h
+++ /dev/null
diff --git a/arch/arm/include/asm/arch-ls102xa/spl.h b/arch/arm/include/asm/arch-ls102xa/spl.h
deleted file mode 100644
index 990c74d..0000000
--- a/arch/arm/include/asm/arch-ls102xa/spl.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __ASM_ARCH_SPL_H__
-#define __ASM_ARCH_SPL_H__
-
-#define BOOT_DEVICE_NONE	0
-#define BOOT_DEVICE_XIP		1
-#define BOOT_DEVICE_XIPWAIT	2
-#define BOOT_DEVICE_NAND	3
-#define BOOT_DEVICE_ONENAND	4
-#define BOOT_DEVICE_MMC1	5
-#define BOOT_DEVICE_MMC2	6
-#define BOOT_DEVICE_MMC2_2	7
-#define BOOT_DEVICE_SPI		10
-
-#endif	/* __ASM_ARCH_SPL_H__ */