diff options
Diffstat (limited to 'arch/arm/include/asm/arch-omap4')
| -rw-r--r-- | arch/arm/include/asm/arch-omap4/clock.h | 252 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap4/cpu.h | 109 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap4/ehci.h | 38 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap4/gpio.h | 34 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap4/hardware.h | 25 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap4/i2c.h | 11 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap4/mem.h | 61 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap4/mmc_host_def.h | 38 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap4/mux_omap4.h | 328 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap4/omap.h | 143 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap4/spl.h | 22 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap4/sys_proto.h | 71 |
12 files changed, 0 insertions, 1132 deletions
diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h deleted file mode 100644 index 037045c..0000000 --- a/arch/arm/include/asm/arch-omap4/clock.h +++ /dev/null @@ -1,252 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Aneesh V <aneesh@ti.com> - */ -#ifndef _CLOCKS_OMAP4_H_ -#define _CLOCKS_OMAP4_H_ -#include <common.h> -#include <asm/omap_common.h> - -/* - * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per - * loop, allow for a minimum of 2 ms wait (in reality the wait will be - * much more than that) - */ -#define LDELAY 1000000 - -/* CM_DLL_CTRL */ -#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 -#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) -#define CM_DLL_CTRL_NO_OVERRIDE 0 - -/* CM_CLKMODE_DPLL */ -#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 -#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) -#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 -#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 -#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) -#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 -#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) -#define CM_CLKMODE_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) - -#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 -#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 - -#define DPLL_EN_STOP 1 -#define DPLL_EN_MN_BYPASS 4 -#define DPLL_EN_LOW_POWER_BYPASS 5 -#define DPLL_EN_FAST_RELOCK_BYPASS 6 -#define DPLL_EN_LOCK 7 - -/* CM_IDLEST_DPLL fields */ -#define ST_DPLL_CLK_MASK 1 - -/* CM_CLKSEL_DPLL */ -#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 -#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) -#define CM_CLKSEL_DPLL_M_SHIFT 8 -#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) -#define CM_CLKSEL_DPLL_N_SHIFT 0 -#define CM_CLKSEL_DPLL_N_MASK 0x7F -#define CM_CLKSEL_DCC_EN_SHIFT 22 -#define CM_CLKSEL_DCC_EN_MASK (1 << 22) - -/* CM_SYS_CLKSEL */ -#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 - -/* CM_CLKSEL_CORE */ -#define CLKSEL_CORE_SHIFT 0 -#define CLKSEL_L3_SHIFT 4 -#define CLKSEL_L4_SHIFT 8 - -#define CLKSEL_CORE_X2_DIV_1 0 -#define CLKSEL_L3_CORE_DIV_2 1 -#define CLKSEL_L4_L3_DIV_2 1 - -/* CM_ABE_PLL_REF_CLKSEL */ -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 -#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 - -/* CM_BYPCLK_DPLL_IVA */ -#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 -#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 - -#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 - -/* CM_SHADOW_FREQ_CONFIG1 */ -#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 -#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 -#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 - -#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 -#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) - -#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 -#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) - -/*CM_<clock_domain>__CLKCTRL */ -#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 -#define CD_CLKCTRL_CLKTRCTRL_MASK 3 - -#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 -#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 -#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 -#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 - - -/* CM_<clock_domain>_<module>_CLKCTRL */ -#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 -#define MODULE_CLKCTRL_MODULEMODE_MASK 3 -#define MODULE_CLKCTRL_IDLEST_SHIFT 16 -#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) - -#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 -#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 -#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 - -#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 -#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 -#define MODULE_CLKCTRL_IDLEST_IDLE 2 -#define MODULE_CLKCTRL_IDLEST_DISABLED 3 - -/* CM_L4PER_GPIO4_CLKCTRL */ -#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) - -/* CM_L3INIT_HSMMCn_CLKCTRL */ -#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) - -/* CM_WKUP_GPTIMER1_CLKCTRL */ -#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) - -/* CM_CAM_ISS_CLKCTRL */ -#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) - -/* CM_DSS_DSS_CLKCTRL */ -#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 - -/* CM_COREAON_USB_PHY_CORE_CLKCTRL */ -#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) - -/* CM_L3INIT_USBPHY_CLKCTRL */ -#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK (1 << 8) - -/* CM_MPU_MPU_CLKCTRL */ -#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 -#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25 -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) - -/* Clock frequencies */ -#define OMAP_SYS_CLK_IND_38_4_MHZ 6 - -/* PRM_VC_VAL_BYPASS */ -#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 - -/* PMIC */ -#define SMPS_I2C_SLAVE_ADDR 0x12 -/* TWL6030 SMPS */ -#define SMPS_REG_ADDR_VCORE1 0x55 -#define SMPS_REG_ADDR_VCORE2 0x5B -#define SMPS_REG_ADDR_VCORE3 0x61 -/* TWL6032 SMPS */ -#define SMPS_REG_ADDR_SMPS1 0x55 -#define SMPS_REG_ADDR_SMPS2 0x5B -#define SMPS_REG_ADDR_SMPS5 0x49 - -#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 -#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 - -/* TPS */ -#define TPS62361_I2C_SLAVE_ADDR 0x60 -#define TPS62361_REG_ADDR_SET0 0x0 -#define TPS62361_REG_ADDR_SET1 0x1 -#define TPS62361_REG_ADDR_SET2 0x2 -#define TPS62361_REG_ADDR_SET3 0x3 -#define TPS62361_REG_ADDR_CTRL 0x4 -#define TPS62361_REG_ADDR_TEMP 0x5 -#define TPS62361_REG_ADDR_RMP_CTRL 0x6 -#define TPS62361_REG_ADDR_CHIP_ID 0x8 -#define TPS62361_REG_ADDR_CHIP_ID_2 0x9 - -#define TPS62361_BASE_VOLT_MV 500 -#define TPS62361_VSEL0_GPIO 7 - -/* AUXCLKx reg fields */ -#define AUXCLK_ENABLE_MASK (1 << 8) -#define AUXCLK_SRCSELECT_SHIFT 1 -#define AUXCLK_SRCSELECT_MASK (3 << 1) -#define AUXCLK_CLKDIV_SHIFT 16 -#define AUXCLK_CLKDIV_MASK (0xF << 16) - -#define AUXCLK_SRCSELECT_SYS_CLK 0 -#define AUXCLK_SRCSELECT_CORE_DPLL 1 -#define AUXCLK_SRCSELECT_PER_DPLL 2 -#define AUXCLK_SRCSELECT_ALTERNATE 3 - -#define AUXCLK_CLKDIV_2 1 -#define AUXCLK_CLKDIV_16 0xF - -/* ALTCLKSRC */ -#define ALTCLKSRC_MODE_MASK 3 -#define ALTCLKSRC_ENABLE_INT_MASK 4 -#define ALTCLKSRC_ENABLE_EXT_MASK 8 - -#define ALTCLKSRC_MODE_ACTIVE 1 - -#define DPLL_NO_LOCK 0 -#define DPLL_LOCK 1 - -/* Clock Defines */ -#define V_OSCK 38400000 /* Clock output from T2 */ -#define V_SCLK V_OSCK - -struct omap4_scrm_regs { - u32 revision; /* 0x0000 */ - u32 pad00[63]; - u32 clksetuptime; /* 0x0100 */ - u32 pmicsetuptime; /* 0x0104 */ - u32 pad01[2]; - u32 altclksrc; /* 0x0110 */ - u32 pad02[2]; - u32 c2cclkm; /* 0x011c */ - u32 pad03[56]; - u32 extclkreq; /* 0x0200 */ - u32 accclkreq; /* 0x0204 */ - u32 pwrreq; /* 0x0208 */ - u32 pad04[1]; - u32 auxclkreq0; /* 0x0210 */ - u32 auxclkreq1; /* 0x0214 */ - u32 auxclkreq2; /* 0x0218 */ - u32 auxclkreq3; /* 0x021c */ - u32 auxclkreq4; /* 0x0220 */ - u32 auxclkreq5; /* 0x0224 */ - u32 pad05[3]; - u32 c2cclkreq; /* 0x0234 */ - u32 pad06[54]; - u32 auxclk0; /* 0x0310 */ - u32 auxclk1; /* 0x0314 */ - u32 auxclk2; /* 0x0318 */ - u32 auxclk3; /* 0x031c */ - u32 auxclk4; /* 0x0320 */ - u32 auxclk5; /* 0x0324 */ - u32 pad07[54]; - u32 rsttime_reg; /* 0x0400 */ - u32 pad08[6]; - u32 c2crstctrl; /* 0x041c */ - u32 extpwronrstctrl; /* 0x0420 */ - u32 pad09[59]; - u32 extwarmrstst_reg; /* 0x0510 */ - u32 apewarmrstst_reg; /* 0x0514 */ - u32 pad10[1]; - u32 c2cwarmrstst_reg; /* 0x051C */ -}; -#endif /* _CLOCKS_OMAP4_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h deleted file mode 100644 index 4c9ed45..0000000 --- a/arch/arm/include/asm/arch-omap4/cpu.h +++ /dev/null @@ -1,109 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2010 - * Texas Instruments, <www.ti.com> - */ - -#ifndef _CPU_H -#define _CPU_H - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> -#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ - -#include <asm/arch/hardware.h> - -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct gptimer { - u32 tidr; /* 0x00 r */ - u8 res[0xc]; - u32 tiocp_cfg; /* 0x10 rw */ - u32 tistat; /* 0x14 r */ - u32 tisr; /* 0x18 rw */ - u32 tier; /* 0x1c rw */ - u32 twer; /* 0x20 rw */ - u32 tclr; /* 0x24 rw */ - u32 tcrr; /* 0x28 rw */ - u32 tldr; /* 0x2c rw */ - u32 ttgr; /* 0x30 rw */ - u32 twpc; /* 0x34 r */ - u32 tmar; /* 0x38 rw */ - u32 tcar1; /* 0x3c r */ - u32 tcicr; /* 0x40 rw */ - u32 tcar2; /* 0x44 r */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -/* enable sys_clk NO-prescale /1 */ -#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) - -/* Watchdog */ -#ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct watchdog { - u8 res1[0x34]; - u32 wwps; /* 0x34 r */ - u8 res2[0x10]; - u32 wspr; /* 0x48 rw */ -}; -#endif /* __ASSEMBLY__ */ -#endif /* __KERNEL_STRICT_NAMES */ - -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -#define TCLR_ST (0x1 << 0) -#define TCLR_AR (0x1 << 1) -#define TCLR_PRE (0x1 << 5) - -/* I2C base */ -#define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000) -#define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000) -#define I2C_BASE3 (OMAP44XX_L4_PER_BASE + 0x60000) -#define I2C_BASE4 (OMAP44XX_L4_PER_BASE + 0x350000) - -/* MUSB base */ -#define MUSB_BASE (OMAP44XX_L4_CORE_BASE + 0xAB000) - -/* OMAP4 GPIO registers */ -#define OMAP_GPIO_REVISION 0x0000 -#define OMAP_GPIO_SYSCONFIG 0x0010 -#define OMAP_GPIO_SYSSTATUS 0x0114 -#define OMAP_GPIO_IRQSTATUS1 0x0118 -#define OMAP_GPIO_IRQSTATUS2 0x0128 -#define OMAP_GPIO_IRQENABLE2 0x012c -#define OMAP_GPIO_IRQENABLE1 0x011c -#define OMAP_GPIO_WAKE_EN 0x0120 -#define OMAP_GPIO_CTRL 0x0130 -#define OMAP_GPIO_OE 0x0134 -#define OMAP_GPIO_DATAIN 0x0138 -#define OMAP_GPIO_DATAOUT 0x013c -#define OMAP_GPIO_LEVELDETECT0 0x0140 -#define OMAP_GPIO_LEVELDETECT1 0x0144 -#define OMAP_GPIO_RISINGDETECT 0x0148 -#define OMAP_GPIO_FALLINGDETECT 0x014c -#define OMAP_GPIO_DEBOUNCE_EN 0x0150 -#define OMAP_GPIO_DEBOUNCE_VAL 0x0154 -#define OMAP_GPIO_CLEARIRQENABLE1 0x0160 -#define OMAP_GPIO_SETIRQENABLE1 0x0164 -#define OMAP_GPIO_CLEARWKUENA 0x0180 -#define OMAP_GPIO_SETWKUENA 0x0184 -#define OMAP_GPIO_CLEARDATAOUT 0x0190 -#define OMAP_GPIO_SETDATAOUT 0x0194 - -/* - * PRCM - */ - -/* PRM */ -#define PRM_BASE 0x4A306000 -#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) - -#define PRM_RSTCTRL PRM_DEVICE_BASE -#define PRM_RSTCTRL_RESET 0x01 -#define PRM_RSTST (PRM_DEVICE_BASE + 0x4) -#define PRM_RSTST_WARM_RESET_MASK 0x07EA - -#endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap4/ehci.h b/arch/arm/include/asm/arch-omap4/ehci.h deleted file mode 100644 index 30bdaad..0000000 --- a/arch/arm/include/asm/arch-omap4/ehci.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * OMAP EHCI port support - * Based on LINUX KERNEL - * drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com - * Author: Govindraj R <govindraj.raja@ti.com> - */ - -#ifndef _OMAP4_EHCI_H_ -#define _OMAP4_EHCI_H_ - -#define OMAP_EHCI_BASE (OMAP44XX_L4_CORE_BASE + 0x64C00) -#define OMAP_UHH_BASE (OMAP44XX_L4_CORE_BASE + 0x64000) -#define OMAP_USBTLL_BASE (OMAP44XX_L4_CORE_BASE + 0x62000) - -/* UHH, TLL and opt clocks */ -#define CM_L3INIT_HSUSBHOST_CLKCTRL 0x4A009358UL - -#define HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK (1 << 24) - -/* TLL Register Set */ -#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) -#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) -#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) -#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) -#define OMAP_USBTLL_SYSSTATUS_RESETDONE 1 - -#define OMAP_UHH_SYSCONFIG_SOFTRESET 1 -#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE (1 << 2) -#define OMAP_UHH_SYSCONFIG_NOIDLE (1 << 2) -#define OMAP_UHH_SYSCONFIG_NOSTDBY (1 << 4) - -#define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_NOIDLE | \ - OMAP_UHH_SYSCONFIG_NOSTDBY) - -#endif /* _OMAP4_EHCI_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/gpio.h b/arch/arm/include/asm/arch-omap4/gpio.h deleted file mode 100644 index aceb3e2..0000000 --- a/arch/arm/include/asm/arch-omap4/gpio.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2009 Wind River Systems, Inc. - * Tom Rix <Tom.Rix@windriver.com> - * - * This work is derived from the linux 2.6.27 kernel source - * To fetch, use the kernel repository - * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git - * Use the v2.6.27 tag. - * - * Below is the original's header including its copyright - * - * linux/arch/arm/plat-omap/gpio.c - * - * Support functions for OMAP GPIO - * - * Copyright (C) 2003-2005 Nokia Corporation - * Written by Juha Yrjölä <juha.yrjola@nokia.com> - */ -#ifndef _GPIO_OMAP4_H -#define _GPIO_OMAP4_H - -#include <asm/omap_gpio.h> - -#define OMAP_MAX_GPIO 192 - -#define OMAP44XX_GPIO1_BASE 0x4A310000 -#define OMAP44XX_GPIO2_BASE 0x48055000 -#define OMAP44XX_GPIO3_BASE 0x48057000 -#define OMAP44XX_GPIO4_BASE 0x48059000 -#define OMAP44XX_GPIO5_BASE 0x4805B000 -#define OMAP44XX_GPIO6_BASE 0x4805D000 - -#endif /* _GPIO_OMAP4_H */ diff --git a/arch/arm/include/asm/arch-omap4/hardware.h b/arch/arm/include/asm/arch-omap4/hardware.h deleted file mode 100644 index 48dc809..0000000 --- a/arch/arm/include/asm/arch-omap4/hardware.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * hardware.h - * - * hardware specific header - * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ - */ - -#ifndef __OMAP_HARDWARE_H -#define __OMAP_HARDWARE_H - -#include <asm/arch/omap.h> - -/* - * Common hardware definitions - */ - -/* BCH Error Location Module */ -#define ELM_BASE 0x48078000 - -/* GPMC Base address */ -#define GPMC_BASE 0x50000000 - -#endif diff --git a/arch/arm/include/asm/arch-omap4/i2c.h b/arch/arm/include/asm/arch-omap4/i2c.h deleted file mode 100644 index c8f2f97..0000000 --- a/arch/arm/include/asm/arch-omap4/i2c.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2004-2010 - * Texas Instruments, <www.ti.com> - */ -#ifndef _OMAP4_I2C_H_ -#define _OMAP4_I2C_H_ - -#define I2C_DEFAULT_BASE I2C_BASE1 - -#endif /* _OMAP4_I2C_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/mem.h b/arch/arm/include/asm/arch-omap4/mem.h deleted file mode 100644 index 3026a00..0000000 --- a/arch/arm/include/asm/arch-omap4/mem.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments, <www.ti.com> - * - * Author - * Mansoor Ahamed <mansoor.ahamed@ti.com> - * - * Initial Code from: - * Richard Woodruff <r-woodruff2@ti.com> - */ - -#ifndef _MEM_H_ -#define _MEM_H_ - -/* - * GPMC settings - - * Definitions is as per the following format - * #define <PART>_GPMC_CONFIG<x> <value> - * Where: - * PART is the part name e.g. STNOR - Intel Strata Flash - * x is GPMC config registers from 1 to 6 (there will be 6 macros) - * Value is corresponding value - * - * For every valid PRCM configuration there should be only one definition of - * the same. if values are independent of the board, this definition will be - * present in this file if values are dependent on the board, then this should - * go into corresponding mem-boardName.h file - * - * Currently valid part Names are (PART): - * M_NAND - Micron NAND - * STNOR - STMicrolelctronics M29W128GL - */ -#define GPMC_SIZE_256M 0x0 -#define GPMC_SIZE_128M 0x8 -#define GPMC_SIZE_64M 0xC -#define GPMC_SIZE_32M 0xE -#define GPMC_SIZE_16M 0xF - -#define M_NAND_GPMC_CONFIG1 0x00000800 -#define M_NAND_GPMC_CONFIG2 0x001e1e00 -#define M_NAND_GPMC_CONFIG3 0x001e1e00 -#define M_NAND_GPMC_CONFIG4 0x16051807 -#define M_NAND_GPMC_CONFIG5 0x00151e1e -#define M_NAND_GPMC_CONFIG6 0x16000f80 -#define M_NAND_GPMC_CONFIG7 0x00000008 - -#define STNOR_GPMC_CONFIG1 0x00001200 -#define STNOR_GPMC_CONFIG2 0x00101000 -#define STNOR_GPMC_CONFIG3 0x00030301 -#define STNOR_GPMC_CONFIG4 0x10041004 -#define STNOR_GPMC_CONFIG5 0x000C1010 -#define STNOR_GPMC_CONFIG6 0x08070280 -#define STNOR_GPMC_CONFIG7 0x00000F48 - -/* max number of GPMC Chip Selects */ -#define GPMC_MAX_CS 8 -/* max number of GPMC regs */ -#define GPMC_MAX_REG 7 - -#endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h deleted file mode 100644 index d067799..0000000 --- a/arch/arm/include/asm/arch-omap4/mmc_host_def.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation's version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef MMC_HOST_DEF_H -#define MMC_HOST_DEF_H - -#include <asm/omap_mmc.h> - -/* - * OMAP HSMMC register definitions - */ - -#define OMAP_HSMMC1_BASE 0x4809C000 -#define OMAP_HSMMC2_BASE 0x480B4000 -#define OMAP_HSMMC3_BASE 0x480AD000 - -#endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap4/mux_omap4.h b/arch/arm/include/asm/arch-omap4/mux_omap4.h deleted file mode 100644 index 854203c..0000000 --- a/arch/arm/include/asm/arch-omap4/mux_omap4.h +++ /dev/null @@ -1,328 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2004-2009 - * Texas Instruments Incorporated - * Richard Woodruff <r-woodruff2@ti.com> - * Aneesh V <aneesh@ti.com> - * Balaji Krishnamoorthy <balajitk@ti.com> - */ -#ifndef _MUX_OMAP4_H_ -#define _MUX_OMAP4_H_ - -#include <asm/types.h> - -struct pad_conf_entry { - - u16 offset; - - u16 val; - -}; - -#ifdef CONFIG_OFF_PADCONF -#define OFF_PD (1 << 12) -#define OFF_PU (3 << 12) -#define OFF_OUT_PTD (0 << 10) -#define OFF_OUT_PTU (2 << 10) -#define OFF_IN (1 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (1 << 9) -#else -#define OFF_PD (0 << 12) -#define OFF_PU (0 << 12) -#define OFF_OUT_PTD (0 << 10) -#define OFF_OUT_PTU (0 << 10) -#define OFF_IN (0 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (0 << 9) -#endif - -#define IEN (1 << 8) -#define IDIS (0 << 8) -#define PTU (3 << 3) -#define PTD (1 << 3) -#define EN (1 << 3) -#define DIS (0 << 3) - -#define M0 0 -#define M1 1 -#define M2 2 -#define M3 3 -#define M4 4 -#define M5 5 -#define M6 6 -#define M7 7 - -#define SAFE_MODE M7 - -#ifdef CONFIG_OFF_PADCONF -#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) -#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) -#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) -#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) -#else -#define OFF_IN_PD 0 -#define OFF_IN_PU 0 -#define OFF_OUT_PD 0 -#define OFF_OUT_PU 0 -#endif - -#define CORE_REVISION 0x0000 -#define CORE_HWINFO 0x0004 -#define CORE_SYSCONFIG 0x0010 -#define GPMC_AD0 0x0040 -#define GPMC_AD1 0x0042 -#define GPMC_AD2 0x0044 -#define GPMC_AD3 0x0046 -#define GPMC_AD4 0x0048 -#define GPMC_AD5 0x004A -#define GPMC_AD6 0x004C -#define GPMC_AD7 0x004E -#define GPMC_AD8 0x0050 -#define GPMC_AD9 0x0052 -#define GPMC_AD10 0x0054 -#define GPMC_AD11 0x0056 -#define GPMC_AD12 0x0058 -#define GPMC_AD13 0x005A -#define GPMC_AD14 0x005C -#define GPMC_AD15 0x005E -#define GPMC_A16 0x0060 -#define GPMC_A17 0x0062 -#define GPMC_A18 0x0064 -#define GPMC_A19 0x0066 -#define GPMC_A20 0x0068 -#define GPMC_A21 0x006A -#define GPMC_A22 0x006C -#define GPMC_A23 0x006E -#define GPMC_A24 0x0070 -#define GPMC_A25 0x0072 -#define GPMC_NCS0 0x0074 -#define GPMC_NCS1 0x0076 -#define GPMC_NCS2 0x0078 -#define GPMC_NCS3 0x007A -#define GPMC_NWP 0x007C -#define GPMC_CLK 0x007E -#define GPMC_NADV_ALE 0x0080 -#define GPMC_NOE 0x0082 -#define GPMC_NWE 0x0084 -#define GPMC_NBE0_CLE 0x0086 -#define GPMC_NBE1 0x0088 -#define GPMC_WAIT0 0x008A -#define GPMC_WAIT1 0x008C -#define C2C_DATA11 0x008E -#define C2C_DATA12 0x0090 -#define C2C_DATA13 0x0092 -#define C2C_DATA14 0x0094 -#define C2C_DATA15 0x0096 -#define HDMI_HPD 0x0098 -#define HDMI_CEC 0x009A -#define HDMI_DDC_SCL 0x009C -#define HDMI_DDC_SDA 0x009E -#define CSI21_DX0 0x00A0 -#define CSI21_DY0 0x00A2 -#define CSI21_DX1 0x00A4 -#define CSI21_DY1 0x00A6 -#define CSI21_DX2 0x00A8 -#define CSI21_DY2 0x00AA -#define CSI21_DX3 0x00AC -#define CSI21_DY3 0x00AE -#define CSI21_DX4 0x00B0 -#define CSI21_DY4 0x00B2 -#define CSI22_DX0 0x00B4 -#define CSI22_DY0 0x00B6 -#define CSI22_DX1 0x00B8 -#define CSI22_DY1 0x00BA -#define CAM_SHUTTER 0x00BC -#define CAM_STROBE 0x00BE -#define CAM_GLOBALRESET 0x00C0 -#define USBB1_ULPITLL_CLK 0x00C2 -#define USBB1_ULPITLL_STP 0x00C4 -#define USBB1_ULPITLL_DIR 0x00C6 -#define USBB1_ULPITLL_NXT 0x00C8 -#define USBB1_ULPITLL_DAT0 0x00CA -#define USBB1_ULPITLL_DAT1 0x00CC -#define USBB1_ULPITLL_DAT2 0x00CE -#define USBB1_ULPITLL_DAT3 0x00D0 -#define USBB1_ULPITLL_DAT4 0x00D2 -#define USBB1_ULPITLL_DAT5 0x00D4 -#define USBB1_ULPITLL_DAT6 0x00D6 -#define USBB1_ULPITLL_DAT7 0x00D8 -#define USBB1_HSIC_DATA 0x00DA -#define USBB1_HSIC_STROBE 0x00DC -#define USBC1_ICUSB_DP 0x00DE -#define USBC1_ICUSB_DM 0x00E0 -#define SDMMC1_CLK 0x00E2 -#define SDMMC1_CMD 0x00E4 -#define SDMMC1_DAT0 0x00E6 -#define SDMMC1_DAT1 0x00E8 -#define SDMMC1_DAT2 0x00EA -#define SDMMC1_DAT3 0x00EC -#define SDMMC1_DAT4 0x00EE -#define SDMMC1_DAT5 0x00F0 -#define SDMMC1_DAT6 0x00F2 -#define SDMMC1_DAT7 0x00F4 -#define ABE_MCBSP2_CLKX 0x00F6 -#define ABE_MCBSP2_DR 0x00F8 -#define ABE_MCBSP2_DX 0x00FA -#define ABE_MCBSP2_FSX 0x00FC -#define ABE_MCBSP1_CLKX 0x00FE -#define ABE_MCBSP1_DR 0x0100 -#define ABE_MCBSP1_DX 0x0102 -#define ABE_MCBSP1_FSX 0x0104 -#define ABE_PDM_UL_DATA 0x0106 -#define ABE_PDM_DL_DATA 0x0108 -#define ABE_PDM_FRAME 0x010A -#define ABE_PDM_LB_CLK 0x010C -#define ABE_CLKS 0x010E -#define ABE_DMIC_CLK1 0x0110 -#define ABE_DMIC_DIN1 0x0112 -#define ABE_DMIC_DIN2 0x0114 -#define ABE_DMIC_DIN3 0x0116 -#define UART2_CTS 0x0118 -#define UART2_RTS 0x011A -#define UART2_RX 0x011C -#define UART2_TX 0x011E -#define HDQ_SIO 0x0120 -#define I2C1_SCL 0x0122 -#define I2C1_SDA 0x0124 -#define I2C2_SCL 0x0126 -#define I2C2_SDA 0x0128 -#define I2C3_SCL 0x012A -#define I2C3_SDA 0x012C -#define I2C4_SCL 0x012E -#define I2C4_SDA 0x0130 -#define MCSPI1_CLK 0x0132 -#define MCSPI1_SOMI 0x0134 -#define MCSPI1_SIMO 0x0136 -#define MCSPI1_CS0 0x0138 -#define MCSPI1_CS1 0x013A -#define MCSPI1_CS2 0x013C -#define MCSPI1_CS3 0x013E -#define UART3_CTS_RCTX 0x0140 -#define UART3_RTS_SD 0x0142 -#define UART3_RX_IRRX 0x0144 -#define UART3_TX_IRTX 0x0146 -#define SDMMC5_CLK 0x0148 -#define SDMMC5_CMD 0x014A -#define SDMMC5_DAT0 0x014C -#define SDMMC5_DAT1 0x014E -#define SDMMC5_DAT2 0x0150 -#define SDMMC5_DAT3 0x0152 -#define MCSPI4_CLK 0x0154 -#define MCSPI4_SIMO 0x0156 -#define MCSPI4_SOMI 0x0158 -#define MCSPI4_CS0 0x015A -#define UART4_RX 0x015C -#define UART4_TX 0x015E -#define USBB2_ULPITLL_CLK 0x0160 -#define USBB2_ULPITLL_STP 0x0162 -#define USBB2_ULPITLL_DIR 0x0164 -#define USBB2_ULPITLL_NXT 0x0166 -#define USBB2_ULPITLL_DAT0 0x0168 -#define USBB2_ULPITLL_DAT1 0x016A -#define USBB2_ULPITLL_DAT2 0x016C -#define USBB2_ULPITLL_DAT3 0x016E -#define USBB2_ULPITLL_DAT4 0x0170 -#define USBB2_ULPITLL_DAT5 0x0172 -#define USBB2_ULPITLL_DAT6 0x0174 -#define USBB2_ULPITLL_DAT7 0x0176 -#define USBB2_HSIC_DATA 0x0178 -#define USBB2_HSIC_STROBE 0x017A -#define UNIPRO_TX0 0x017C -#define UNIPRO_TY0 0x017E -#define UNIPRO_TX1 0x0180 -#define UNIPRO_TY1 0x0182 -#define UNIPRO_TX2 0x0184 -#define UNIPRO_TY2 0x0186 -#define UNIPRO_RX0 0x0188 -#define UNIPRO_RY0 0x018A -#define UNIPRO_RX1 0x018C -#define UNIPRO_RY1 0x018E -#define UNIPRO_RX2 0x0190 -#define UNIPRO_RY2 0x0192 -#define USBA0_OTG_CE 0x0194 -#define USBA0_OTG_DP 0x0196 -#define USBA0_OTG_DM 0x0198 -#define FREF_CLK1_OUT 0x019A -#define FREF_CLK2_OUT 0x019C -#define SYS_NIRQ1 0x019E -#define SYS_NIRQ2 0x01A0 -#define SYS_BOOT0 0x01A2 -#define SYS_BOOT1 0x01A4 -#define SYS_BOOT2 0x01A6 -#define SYS_BOOT3 0x01A8 -#define SYS_BOOT4 0x01AA -#define SYS_BOOT5 0x01AC -#define DPM_EMU0 0x01AE -#define DPM_EMU1 0x01B0 -#define DPM_EMU2 0x01B2 -#define DPM_EMU3 0x01B4 -#define DPM_EMU4 0x01B6 -#define DPM_EMU5 0x01B8 -#define DPM_EMU6 0x01BA -#define DPM_EMU7 0x01BC -#define DPM_EMU8 0x01BE -#define DPM_EMU9 0x01C0 -#define DPM_EMU10 0x01C2 -#define DPM_EMU11 0x01C4 -#define DPM_EMU12 0x01C6 -#define DPM_EMU13 0x01C8 -#define DPM_EMU14 0x01CA -#define DPM_EMU15 0x01CC -#define DPM_EMU16 0x01CE -#define DPM_EMU17 0x01D0 -#define DPM_EMU18 0x01D2 -#define DPM_EMU19 0x01D4 -#define WAKEUPEVENT_0 0x01D8 -#define WAKEUPEVENT_1 0x01DC -#define WAKEUPEVENT_2 0x01E0 -#define WAKEUPEVENT_3 0x01E4 -#define WAKEUPEVENT_4 0x01E8 -#define WAKEUPEVENT_5 0x01EC -#define WAKEUPEVENT_6 0x01F0 - -#define WKUP_REVISION 0x0000 -#define WKUP_HWINFO 0x0004 -#define WKUP_SYSCONFIG 0x0010 -#define PAD0_SIM_IO 0x0040 -#define PAD1_SIM_CLK 0x0042 -#define PAD0_SIM_RESET 0x0044 -#define PAD1_SIM_CD 0x0046 -#define PAD0_SIM_PWRCTRL 0x0048 -#define PAD1_SR_SCL 0x004A -#define PAD0_SR_SDA 0x004C -#define PAD1_FREF_XTAL_IN 0x004E -#define PAD0_FREF_SLICER_IN 0x0050 -#define PAD1_FREF_CLK_IOREQ 0x0052 -#define PAD0_FREF_CLK0_OUT 0x0054 -#define PAD1_FREF_CLK3_REQ 0x0056 -#define PAD0_FREF_CLK3_OUT 0x0058 -#define PAD1_FREF_CLK4_REQ 0x005A -#define PAD0_FREF_CLK4_OUT 0x005C -#define PAD1_SYS_32K 0x005E -#define PAD0_SYS_NRESPWRON 0x0060 -#define PAD1_SYS_NRESWARM 0x0062 -#define PAD0_SYS_PWR_REQ 0x0064 -#define PAD1_SYS_PWRON_RESET 0x0066 -#define PAD0_SYS_BOOT6 0x0068 -#define PAD1_SYS_BOOT7 0x006A -#define PAD0_JTAG_NTRST 0x006C -#define PAD1_JTAG_TCK 0x006D -#define PAD0_JTAG_RTCK 0x0070 -#define PAD1_JTAG_TMS_TMSC 0x0072 -#define PAD0_JTAG_TDI 0x0074 -#define PAD1_JTAG_TDO 0x0076 -#define PADCONF_WAKEUPEVENT_0 0x007C -#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0 -#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4 -#define PADCONF_MODE 0x05A8 -#define CONTROL_XTAL_OSCILLATOR 0x05AC -#define CONTROL_CONTROL_I2C_2 0x0604 -#define CONTROL_CONTROL_JTAG 0x0608 -#define CONTROL_CONTROL_SYS 0x060C -#define CONTROL_SPARE_RW 0x0614 -#define CONTROL_SPARE_R 0x0618 -#define CONTROL_SPARE_R_C0 0x061C - -#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ 0x4A31E05A -#endif /* _MUX_OMAP4_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h deleted file mode 100644 index 8919088..0000000 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ /dev/null @@ -1,143 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Authors: - * Aneesh V <aneesh@ti.com> - * - * Derived from OMAP3 work by - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <x0khasim@ti.com> - */ - -#ifndef _OMAP4_H_ -#define _OMAP4_H_ - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> -#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ - -#include <linux/sizes.h> - -/* - * L4 Peripherals - L4 Wakeup and L4 Core now - */ -#define OMAP44XX_L4_CORE_BASE 0x4A000000 -#define OMAP44XX_L4_WKUP_BASE 0x4A300000 -#define OMAP44XX_L4_PER_BASE 0x48000000 - -#define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000 -#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000 -#define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START -#define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END - -/* CONTROL_ID_CODE */ -#define CONTROL_ID_CODE 0x4A002204 - -#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F -#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F -#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F -#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F -#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F -#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F -#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F -#define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F - -/* UART */ -#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) -#define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000) -#define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000) - -/* General Purpose Timers */ -#define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000) -#define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000) -#define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000) - -/* Watchdog Timer2 - MPU watchdog */ -#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) - -/* - * Hardware Register Details - */ - -/* Watchdog Timer */ -#define WD_UNLOCK1 0xAAAA -#define WD_UNLOCK2 0x5555 - -/* GP Timer */ -#define TCLR_ST (0x1 << 0) -#define TCLR_AR (0x1 << 1) -#define TCLR_PRE (0x1 << 5) - -/* Control Module */ -#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) -#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f -#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 -#define CONTROL_EFUSE_2_OVERRIDE 0x99084000 - -/* LPDDR2 IO regs */ -#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C -#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E -#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C -#define LPDDR2IO_GR10_WD_MASK (3 << 17) -#define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F - -/* CONTROL_EFUSE_2 */ -#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 - -#define MMC1_PWRDNZ (1 << 26) -#define MMC1_PBIASLITE_PWRDNZ (1 << 22) -#define MMC1_PBIASLITE_VMODE (1 << 21) - -#ifndef __ASSEMBLY__ - -struct s32ktimer { - unsigned char res[0x10]; - unsigned int s32k_cr; /* 0x10 */ -}; - -#define DEVICE_TYPE_SHIFT (0x8) -#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) - -#endif /* __ASSEMBLY__ */ - -/* - * Non-secure SRAM Addresses - * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE - * at 0x40304000(EMU base) so that our code works for both EMU and GP - */ -#define NON_SECURE_SRAM_START 0x40304000 -#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */ -#define NON_SECURE_SRAM_IMG_END 0x4030C000 -#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K) -/* base address for indirect vectors (internal boot mode) */ -#define SRAM_ROM_VECT_BASE 0x4030D000 - -/* ABB settings */ -#define OMAP_ABB_SETTLING_TIME 50 -#define OMAP_ABB_CLOCK_CYCLES 16 - -/* ABB tranxdone mask */ -#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7) - -#define OMAP44XX_SAR_RAM_BASE 0x4a326000 -#define OMAP_REBOOT_REASON_OFFSET 0xA0C -#define OMAP_REBOOT_REASON_SIZE 0x0F - -/* Boot parameters */ -#ifndef __ASSEMBLY__ -struct omap_boot_parameters { - unsigned int boot_message; - unsigned int boot_device_descriptor; - unsigned char boot_device; - unsigned char reset_reason; - unsigned char ch_flags; -}; - -int omap_reboot_mode(char *mode, unsigned int length); -int omap_reboot_mode_clear(void); -int omap_reboot_mode_store(char *mode); -#endif - -#endif diff --git a/arch/arm/include/asm/arch-omap4/spl.h b/arch/arm/include/asm/arch-omap4/spl.h deleted file mode 100644 index d24944a..0000000 --- a/arch/arm/include/asm/arch-omap4/spl.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 - * Texas Instruments, <www.ti.com> - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_NONE 0x00 -#define BOOT_DEVICE_XIP 0x01 -#define BOOT_DEVICE_XIPWAIT 0x02 -#define BOOT_DEVICE_NAND 0x03 -#define BOOT_DEVICE_ONENAND 0x04 -#define BOOT_DEVICE_MMC1 0x05 -#define BOOT_DEVICE_MMC2 0x06 -#define BOOT_DEVICE_MMC2_2 0x07 -#define BOOT_DEVICE_UART 0x43 -#define BOOT_DEVICE_USB 0x45 - -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2 -#endif diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h deleted file mode 100644 index b2a6887..0000000 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ /dev/null @@ -1,71 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -#include <asm/arch/omap.h> -#include <asm/arch/clock.h> -#include <asm/io.h> -#include <asm/omap_common.h> -#include <linux/mtd/omap_gpmc.h> -#include <asm/arch/mux_omap4.h> -#include <asm/ti-common/sys_proto.h> - -#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -extern const struct emif_regs emif_regs_elpida_200_mhz_2cs; -extern const struct emif_regs emif_regs_elpida_380_mhz_1cs; -extern const struct emif_regs emif_regs_elpida_400_mhz_1cs; -extern const struct emif_regs emif_regs_elpida_400_mhz_2cs; -extern const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2; -extern const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2; -extern const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2; -#else -extern const struct lpddr2_device_details elpida_2G_S4_details; -extern const struct lpddr2_device_details elpida_4G_S4_details; -#endif - -#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -extern const struct lpddr2_device_timings jedec_default_timings; -#else -extern const struct lpddr2_device_timings elpida_2G_S4_timings; -#endif - -struct omap_sysinfo { - char *board_string; -}; -extern const struct omap_sysinfo sysinfo; - -void gpmc_init(void); -void watchdog_init(void); -u32 get_device_type(void); -void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); -void set_muxconf_regs(void); -u32 wait_on_value(u32, u32, void *, u32); -void sdelay(unsigned long); -void setup_early_clocks(void); -void prcm_init(void); -void do_board_detect(void); -void bypass_dpll(u32 const base); -void freq_update_core(void); -u32 get_sys_clk_freq(void); -u32 omap4_ddr_clk(void); -void cancel_out(u32 *num, u32 *den, u32 den_limit); -void sdram_init(void); -u32 omap_sdram_size(void); -u32 cortex_rev(void); -void save_omap_boot_params(void); -void init_omap_revision(void); -void do_io_settings(void); -void sri2c_init(void); -int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); -u32 warm_reset(void); -void force_emif_self_refresh(void); -void setup_warmreset_time(void); - -#define OMAP4_SERVICE_PL310_CONTROL_REG_SET 0x102 - -#endif |