diff options
Diffstat (limited to 'arch/arm/include/asm/arch-stv0991')
| -rw-r--r-- | arch/arm/include/asm/arch-stv0991/gpio.h | 21 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-stv0991/hardware.h | 72 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-stv0991/stv0991_cgu.h | 130 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-stv0991/stv0991_creg.h | 103 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-stv0991/stv0991_defs.h | 15 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-stv0991/stv0991_gpt.h | 42 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-stv0991/stv0991_periph.h | 45 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-stv0991/stv0991_wdru.h | 27 |
8 files changed, 0 insertions, 455 deletions
diff --git a/arch/arm/include/asm/arch-stv0991/gpio.h b/arch/arm/include/asm/arch-stv0991/gpio.h deleted file mode 100644 index b27f407..0000000 --- a/arch/arm/include/asm/arch-stv0991/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef __ASM_ARCH_STV0991_GPIO_H -#define __ASM_ARCH_STV0991_GPIO_H - -enum gpio_direction { - GPIO_DIRECTION_IN, - GPIO_DIRECTION_OUT, -}; - -struct gpio_regs { - u32 data; /* offset 0x0 */ - u32 reserved[0xff]; /* 0x4--0x3fc */ - u32 dir; /* offset 0x400 */ -}; - -#endif /* __ASM_ARCH_STV0991_GPIO_H */ diff --git a/arch/arm/include/asm/arch-stv0991/hardware.h b/arch/arm/include/asm/arch-stv0991/hardware.h deleted file mode 100644 index ea8f820..0000000 --- a/arch/arm/include/asm/arch-stv0991/hardware.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef _ASM_ARCH_HARDWARE_H -#define _ASM_ARCH_HARDWARE_H - -/* STV0991 */ -#define SRAM0_BASE_ADDR 0x00000000UL -#define SRAM1_BASE_ADDR 0x00068000UL -#define SRAM2_BASE_ADDR 0x000D0000UL -#define SRAM3_BASE_ADDR 0x00138000UL -#define CFS_SRAM0_BASE_ADDR 0x00198000UL -#define CFS_SRAM1_BASE_ADDR 0x001B8000UL -#define FAST_SRAM_BASE_ADDR 0x001D8000UL -#define FLASH_BASE_ADDR 0x40000000UL -#define PL310_BASE_ADDR 0x70000000UL -#define HSAXIM_BASE_ADDR 0x70100000UL -#define IMGSS_BASE_ADDR 0x70200000UL -#define ADC_BASE_ADDR 0x80000000UL -#define GPIOA_BASE_ADDR 0x80001000UL -#define GPIOB_BASE_ADDR 0x80002000UL -#define GPIOC_BASE_ADDR 0x80003000UL -#define HDM_BASE_ADDR 0x80004000UL -#define THSENS_BASE_ADDR 0x80200000UL -#define GPTIMER2_BASE_ADDR 0x80201000UL -#define GPTIMER1_BASE_ADDR 0x80202000UL -#define QSPI_BASE_ADDR 0x80203000UL -#define CGU_BASE_ADDR 0x80204000UL -#define CREG_BASE_ADDR 0x80205000UL -#define PEC_BASE_ADDR 0x80206000UL -#define WDRU_BASE_ADDR 0x80207000UL -#define BSEC_BASE_ADDR 0x80208000UL -#define DAP_ROM_BASE_ADDR 0x80210000UL -#define SOC_CTI_BASE_ADDR 0x80211000UL -#define TPIU_BASE_ADDR 0x80212000UL -#define TMC_ETF_BASE_ADDR 0x80213000UL -#define R4_ETM_BASE_ADDR 0x80214000UL -#define R4_CTI_BASE_ADDR 0x80215000UL -#define R4_DBG_BASE_ADDR 0x80216000UL -#define GMAC_BASE_ADDR 0x80300000UL -#define RNSS_BASE_ADDR 0x80302000UL -#define CRYP_BASE_ADDR 0x80303000UL -#define HASH_BASE_ADDR 0x80304000UL -#define GPDMA_BASE_ADDR 0x80305000UL -#define ISA_BASE_ADDR 0x8032A000UL -#define HCI_BASE_ADDR 0x80400000UL -#define I2C1_BASE_ADDR 0x80401000UL -#define I2C2_BASE_ADDR 0x80402000UL -#define SAI_BASE_ADDR 0x80403000UL -#define USI_BASE_ADDR 0x80404000UL -#define SPI1_BASE_ADDR 0x80405000UL -#define UART_BASE_ADDR 0x80406000UL -#define SPI2_BASE_ADDR 0x80500000UL -#define CAN_BASE_ADDR 0x80501000UL -#define USART1_BASE_ADDR 0x80502000UL -#define USART2_BASE_ADDR 0x80503000UL -#define USART3_BASE_ADDR 0x80504000UL -#define USART4_BASE_ADDR 0x80505000UL -#define USART5_BASE_ADDR 0x80506000UL -#define USART6_BASE_ADDR 0x80507000UL -#define SDI2_BASE_ADDR 0x80600000UL -#define SDI1_BASE_ADDR 0x80601000UL -#define VICA_BASE_ADDR 0x81000000UL -#define VICB_BASE_ADDR 0x81001000UL -#define STM_CHANNELS_BASE_ADDR 0x81100000UL -#define STM_BASE_ADDR 0x81110000UL -#define SROM_BASE_ADDR 0xFFFF0000UL - -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h deleted file mode 100644 index df9dd54..0000000 --- a/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef _STV0991_CGU_H -#define _STV0991_CGU_H - -struct stv0991_cgu_regs { - u32 cpu_freq; /* offset 0x0 */ - u32 icn2_freq; /* offset 0x4 */ - u32 dma_freq; /* offset 0x8 */ - u32 isp_freq; /* offset 0xc */ - u32 h264_freq; /* offset 0x10 */ - u32 osif_freq; /* offset 0x14 */ - u32 ren_freq; /* offset 0x18 */ - u32 tim_freq; /* offset 0x1c */ - u32 sai_freq; /* offset 0x20 */ - u32 eth_freq; /* offset 0x24 */ - u32 i2c_freq; /* offset 0x28 */ - u32 spi_freq; /* offset 0x2c */ - u32 uart_freq; /* offset 0x30 */ - u32 qspi_freq; /* offset 0x34 */ - u32 sdio_freq; /* offset 0x38 */ - u32 usi_freq; /* offset 0x3c */ - u32 can_line_freq; /* offset 0x40 */ - u32 debug_freq; /* offset 0x44 */ - u32 trace_freq; /* offset 0x48 */ - u32 stm_freq; /* offset 0x4c */ - u32 eth_ctrl; /* offset 0x50 */ - u32 reserved[3]; /* offset 0x54 */ - u32 osc_ctrl; /* offset 0x60 */ - u32 pll1_ctrl; /* offset 0x64 */ - u32 pll1_freq; /* offset 0x68 */ - u32 pll1_fract; /* offset 0x6c */ - u32 pll1_spread; /* offset 0x70 */ - u32 pll1_status; /* offset 0x74 */ - u32 pll2_ctrl; /* offset 0x78 */ - u32 pll2_freq; /* offset 0x7c */ - u32 pll2_fract; /* offset 0x80 */ - u32 pll2_spread; /* offset 0x84 */ - u32 pll2_status; /* offset 0x88 */ - u32 cgu_enable_1; /* offset 0x8c */ - u32 cgu_enable_2; /* offset 0x90 */ - u32 cgu_isp_pulse; /* offset 0x94 */ - u32 cgu_h264_pulse; /* offset 0x98 */ - u32 cgu_osif_pulse; /* offset 0x9c */ - u32 cgu_ren_pulse; /* offset 0xa0 */ - -}; - -/* CGU Timer */ -#define CLK_TMR_OSC 0 -#define CLK_TMR_MCLK 1 -#define CLK_TMR_PLL1 2 -#define CLK_TMR_PLL2 3 -#define MDIV_SHIFT_TMR 3 -#define DIV_SHIFT_TMR 6 - -#define TIMER1_CLK_CFG (0 << DIV_SHIFT_TMR \ - | 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK) - -/* Clock Enable/Disable */ - -#define TIMER1_CLK_EN (1 << 15) - -/* CGU Uart config */ -#define CLK_UART_MCLK 0 -#define CLK_UART_PLL1 1 -#define CLK_UART_PLL2 2 - -#define MDIV_SHIFT_UART 3 -#define DIV_SHIFT_UART 6 - -#define UART_CLK_CFG (4 << DIV_SHIFT_UART \ - | 1 << MDIV_SHIFT_UART | CLK_UART_MCLK) - -/* CGU Ethernet clock config */ -#define CLK_ETH_MCLK 0 -#define CLK_ETH_PLL1 1 -#define CLK_ETH_PLL2 2 - -#define MDIV_SHIFT_ETH 3 -#define DIV_SHIFT_ETH 6 -#define DIV_ETH_125 9 -#define DIV_ETH_50 12 -#define DIV_ETH_P2P 15 - -#define ETH_CLK_CFG (4 << DIV_ETH_P2P | 4 << DIV_ETH_50 \ - | 1 << DIV_ETH_125 \ - | 0 << DIV_SHIFT_ETH \ - | 3 << MDIV_SHIFT_ETH | CLK_ETH_PLL1) - /* CGU Ethernet control */ - -#define ETH_CLK_TX_EXT_PHY 0 -#define ETH_CLK_TX_125M 1 -#define ETH_CLK_TX_25M 2 -#define ETH_CLK_TX_2M5 3 -#define ETH_CLK_TX_DIS 7 - -#define ETH_CLK_RX_EXT_PHY 0 -#define ETH_CLK_RX_25M 1 -#define ETH_CLK_RX_2M5 2 -#define ETH_CLK_RX_DIS 3 -#define RX_CLK_SHIFT 3 -#define ETH_CLK_MASK ~(0x1F) - -#define ETH_PHY_MODE_GMII 0 -#define ETH_PHY_MODE_RMII 1 -#define ETH_PHY_CLK_DIS 1 - -#define ETH_CLK_CTRL (ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \ - | ETH_CLK_TX_EXT_PHY) -/* CGU qspi clock */ -#define DIV_HCLK1_SHIFT 9 -#define DIV_CRYP_SHIFT 6 -#define MDIV_QSPI_SHIFT 3 - -#define CLK_QSPI_OSC 0 -#define CLK_QSPI_MCLK 1 -#define CLK_QSPI_PLL1 2 -#define CLK_QSPI_PLL2 3 - -#define QSPI_CLK_CTRL (3 << DIV_HCLK1_SHIFT \ - | 1 << DIV_CRYP_SHIFT \ - | 0 << MDIV_QSPI_SHIFT \ - | CLK_QSPI_OSC) - -#endif diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_creg.h b/arch/arm/include/asm/arch-stv0991/stv0991_creg.h deleted file mode 100644 index 4d444a6..0000000 --- a/arch/arm/include/asm/arch-stv0991/stv0991_creg.h +++ /dev/null @@ -1,103 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef _STV0991_CREG_H -#define _STV0991_CREG_H - -struct stv0991_creg { - u32 version; /* offset 0x0 */ - u32 hdpctl; /* offset 0x4 */ - u32 hdpval; /* offset 0x8 */ - u32 hdpgposet; /* offset 0xc */ - u32 hdpgpoclr; /* offset 0x10 */ - u32 hdpgpoval; /* offset 0x14 */ - u32 stm_mux; /* offset 0x18 */ - u32 sysctrl_1; /* offset 0x1c */ - u32 sysctrl_2; /* offset 0x20 */ - u32 sysctrl_3; /* offset 0x24 */ - u32 sysctrl_4; /* offset 0x28 */ - u32 reserved_1[0x35]; /* offset 0x2C-0xFC */ - u32 mux1; /* offset 0x100 */ - u32 mux2; /* offset 0x104 */ - u32 mux3; /* offset 0x108 */ - u32 mux4; /* offset 0x10c */ - u32 mux5; /* offset 0x110 */ - u32 mux6; /* offset 0x114 */ - u32 mux7; /* offset 0x118 */ - u32 mux8; /* offset 0x11c */ - u32 mux9; /* offset 0x120 */ - u32 mux10; /* offset 0x124 */ - u32 mux11; /* offset 0x128 */ - u32 mux12; /* offset 0x12c */ - u32 mux13; /* offset 0x130 */ - u32 reserved_2[0x33]; /* offset 0x134-0x1FC */ - u32 cfg_pad1; /* offset 0x200 */ - u32 cfg_pad2; /* offset 0x204 */ - u32 cfg_pad3; /* offset 0x208 */ - u32 cfg_pad4; /* offset 0x20c */ - u32 cfg_pad5; /* offset 0x210 */ - u32 cfg_pad6; /* offset 0x214 */ - u32 cfg_pad7; /* offset 0x218 */ - u32 reserved_3[0x39]; /* offset 0x21C-0x2FC */ - u32 vdd_pad1; /* offset 0x300 */ - u32 vdd_pad2; /* offset 0x304 */ - u32 reserved_4[0x3e]; /* offset 0x308-0x3FC */ - u32 vdd_comp1; /* offset 0x400 */ -}; - -/* CREG MUX 13 register */ -#define FLASH_CS_NC_SHIFT 4 -#define FLASH_CS_NC_MASK ~(7 << FLASH_CS_NC_SHIFT) -#define CFG_FLASH_CS_NC (0 << FLASH_CS_NC_SHIFT) - -#define FLASH_CLK_SHIFT 0 -#define FLASH_CLK_MASK ~(7 << FLASH_CLK_SHIFT) -#define CFG_FLASH_CLK (0 << FLASH_CLK_SHIFT) - -/* CREG MUX 12 register */ -#define GPIOC_30_MUX_SHIFT 24 -#define GPIOC_30_MUX_MASK ~(1 << GPIOC_30_MUX_SHIFT) -#define CFG_GPIOC_30_UART_TX (1 << GPIOC_30_MUX_SHIFT) - -#define GPIOC_31_MUX_SHIFT 28 -#define GPIOC_31_MUX_MASK ~(1 << GPIOC_31_MUX_SHIFT) -#define CFG_GPIOC_31_UART_RX (1 << GPIOC_31_MUX_SHIFT) - -/* CREG MUX 7 register */ -#define GPIOB_16_MUX_SHIFT 0 -#define GPIOB_16_MUX_MASK ~(1 << GPIOB_16_MUX_SHIFT) -#define CFG_GPIOB_16_UART_TX (1 << GPIOB_16_MUX_SHIFT) - -#define GPIOB_17_MUX_SHIFT 4 -#define GPIOB_17_MUX_MASK ~(1 << GPIOB_17_MUX_SHIFT) -#define CFG_GPIOB_17_UART_RX (1 << GPIOB_17_MUX_SHIFT) - -/* CREG CFG_PAD6 register */ - -#define GPIOC_31_MODE_SHIFT 30 -#define GPIOC_31_MODE_MASK ~(1 << GPIOC_31_MODE_SHIFT) -#define CFG_GPIOC_31_MODE_OD (0 << GPIOC_31_MODE_SHIFT) -#define CFG_GPIOC_31_MODE_PP (1 << GPIOC_31_MODE_SHIFT) - -#define GPIOC_30_MODE_SHIFT 28 -#define GPIOC_30_MODE_MASK ~(1 << GPIOC_30_MODE_SHIFT) -#define CFG_GPIOC_30_MODE_LOW (0 << GPIOC_30_MODE_SHIFT) -#define CFG_GPIOC_30_MODE_HIGH (1 << GPIOC_30_MODE_SHIFT) - -/* CREG Ethernet pad config */ - -#define VDD_ETH_PS_1V8 0 -#define VDD_ETH_PS_2V5 2 -#define VDD_ETH_PS_3V3 3 -#define VDD_ETH_PS_MASK 0x3 - -#define VDD_ETH_PS_SHIFT 12 -#define ETH_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_PS_SHIFT) - -#define VDD_ETH_M_PS_SHIFT 28 -#define ETH_M_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_M_PS_SHIFT) - -#endif diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_defs.h b/arch/arm/include/asm/arch-stv0991/stv0991_defs.h deleted file mode 100644 index 97d28b2..0000000 --- a/arch/arm/include/asm/arch-stv0991/stv0991_defs.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef __STV0991_DEFS_H__ -#define __STV0991_DEFS_H__ -#include <asm/arch/stv0991_periph.h> - -extern int stv0991_pinmux_config(enum periph_id); -extern int clock_setup(enum periph_clock); - -#endif - diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h deleted file mode 100644 index cd27472..0000000 --- a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef _STV0991_GPT_H -#define _STV0991_GPT_H - -#include <asm/arch-stv0991/hardware.h> - -struct gpt_regs { - u32 cr1; - u32 cr2; - u32 reserved_1; - u32 dier; /* dma_int_en */ - u32 sr; /* status reg */ - u32 egr; /* event gen */ - u32 reserved_2[3]; /* offset 0x18--0x20*/ - u32 cnt; - u32 psc; - u32 arr; -}; - -struct gpt_regs *const gpt1_regs_ptr = - (struct gpt_regs *) GPTIMER1_BASE_ADDR; - -/* Timer control1 register */ -#define GPT_CR1_CEN 0x0001 -#define GPT_MODE_AUTO_RELOAD (1 << 7) - -/* Timer prescalar reg */ -#define GPT_PRESCALER_128 0x128 - -/* Auto reload register for free running config */ -#define GPT_FREE_RUNNING 0xFFFF - -/* Timer, HZ specific defines */ -#define CONFIG_STV0991_HZ 1000 -#define CONFIG_STV0991_HZ_CLOCK (27*1000*1000)/GPT_PRESCALER_128 - -#endif diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_periph.h b/arch/arm/include/asm/arch-stv0991/stv0991_periph.h deleted file mode 100644 index 7a50be1..0000000 --- a/arch/arm/include/asm/arch-stv0991/stv0991_periph.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef __ASM_ARM_ARCH_PERIPH_H -#define __ASM_ARM_ARCH_PERIPH_H - -/* - * Peripherals required for pinmux configuration. List will - * grow with support for more devices getting added. - * Numbering based on interrupt table. - * - */ -enum periph_id { - UART_GPIOC_30_31 = 0, - UART_GPIOB_16_17, - ETH_GPIOB_10_31_C_0_4, - QSPI_CS_CLK_PAD, - PERIPH_ID_I2C0, - PERIPH_ID_I2C1, - PERIPH_ID_I2C2, - PERIPH_ID_I2C3, - PERIPH_ID_I2C4, - PERIPH_ID_I2C5, - PERIPH_ID_I2C6, - PERIPH_ID_I2C7, - PERIPH_ID_SPI0, - PERIPH_ID_SPI1, - PERIPH_ID_SPI2, - PERIPH_ID_SDMMC0, - PERIPH_ID_SDMMC1, - PERIPH_ID_SDMMC2, - PERIPH_ID_SDMMC3, - PERIPH_ID_I2S1, -}; - -enum periph_clock { - UART_CLOCK_CFG = 0, - ETH_CLOCK_CFG, - QSPI_CLOCK_CFG, -}; - -#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h b/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h deleted file mode 100644 index 8cb8a8a..0000000 --- a/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. - */ - -#ifndef _STV0991_WD_RST_H -#define _STV0991_WD_RST_H -#include <asm/arch-stv0991/hardware.h> - -struct stv0991_wd_ru { - u32 wdru_config; - u32 wdru_ctrl1; - u32 wdru_ctrl2; - u32 wdru_tim; - u32 wdru_count; - u32 wdru_stat; - u32 wdru_wrlock; -}; - -struct stv0991_wd_ru *const stv0991_wd_ru_ptr = \ - (struct stv0991_wd_ru *)WDRU_BASE_ADDR; - -/* Watchdog control register */ -#define WDRU_RST_SYS 0x1 - -#endif |