14 files changed, 0 insertions, 926 deletions

diff --git a/arch/arm/include/asm/arch-tegra20/clock-tables.h b/arch/arm/include/asm/arch-tegra20/clock-tables.h
deleted file mode 100644
index 861b3d5..0000000
--- a/arch/arm/include/asm/arch-tegra20/clock-tables.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * Copyright (c) 2010-2012 NVIDIA Corporation <www.nvidia.com>
- */
-
-/* Tegra20 clock PLL tables */
-
-#ifndef _CLOCK_TABLES_H_
-#define _CLOCK_TABLES_H_
-
-/* The PLLs supported by the hardware */
-enum clock_id {
-	CLOCK_ID_FIRST,
-	CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
-	CLOCK_ID_MEMORY,
-	CLOCK_ID_PERIPH,
-	CLOCK_ID_AUDIO,
-	CLOCK_ID_USB,
-	CLOCK_ID_DISPLAY,
-
-	/* now the simple ones */
-	CLOCK_ID_FIRST_SIMPLE,
-	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
-	CLOCK_ID_EPCI,
-	CLOCK_ID_SFROM32KHZ,
-
-	/* These are the base clocks (inputs to the Tegra SOC) */
-	CLOCK_ID_32KHZ,
-	CLOCK_ID_OSC,
-	CLOCK_ID_CLK_M,
-
-	CLOCK_ID_COUNT,	/* number of clocks */
-	CLOCK_ID_NONE = -1,
-};
-
-/* The clocks supported by the hardware */
-enum periph_id {
-	PERIPH_ID_FIRST,
-
-	/* Low word: 31:0 */
-	PERIPH_ID_CPU = PERIPH_ID_FIRST,
-	PERIPH_ID_RESERVED1,
-	PERIPH_ID_RESERVED2,
-	PERIPH_ID_AC97,
-	PERIPH_ID_RTC,
-	PERIPH_ID_TMR,
-	PERIPH_ID_UART1,
-	PERIPH_ID_UART2,
-
-	/* 8 */
-	PERIPH_ID_GPIO,
-	PERIPH_ID_SDMMC2,
-	PERIPH_ID_SPDIF,
-	PERIPH_ID_I2S1,
-	PERIPH_ID_I2C1,
-	PERIPH_ID_NDFLASH,
-	PERIPH_ID_SDMMC1,
-	PERIPH_ID_SDMMC4,
-
-	/* 16 */
-	PERIPH_ID_TWC,
-	PERIPH_ID_PWM,
-	PERIPH_ID_I2S2,
-	PERIPH_ID_EPP,
-	PERIPH_ID_VI,
-	PERIPH_ID_2D,
-	PERIPH_ID_USBD,
-	PERIPH_ID_ISP,
-
-	/* 24 */
-	PERIPH_ID_3D,
-	PERIPH_ID_IDE,
-	PERIPH_ID_DISP2,
-	PERIPH_ID_DISP1,
-	PERIPH_ID_HOST1X,
-	PERIPH_ID_VCP,
-	PERIPH_ID_RESERVED30,
-	PERIPH_ID_CACHE2,
-
-	/* Middle word: 63:32 */
-	PERIPH_ID_MEM,
-	PERIPH_ID_AHBDMA,
-	PERIPH_ID_APBDMA,
-	PERIPH_ID_RESERVED35,
-	PERIPH_ID_KBC,
-	PERIPH_ID_STAT_MON,
-	PERIPH_ID_PMC,
-	PERIPH_ID_FUSE,
-
-	/* 40 */
-	PERIPH_ID_KFUSE,
-	PERIPH_ID_SBC1,
-	PERIPH_ID_SNOR,
-	PERIPH_ID_SPI1,
-	PERIPH_ID_SBC2,
-	PERIPH_ID_XIO,
-	PERIPH_ID_SBC3,
-	PERIPH_ID_DVC_I2C,
-
-	/* 48 */
-	PERIPH_ID_DSI,
-	PERIPH_ID_TVO,
-	PERIPH_ID_MIPI,
-	PERIPH_ID_HDMI,
-	PERIPH_ID_CSI,
-	PERIPH_ID_TVDAC,
-	PERIPH_ID_I2C2,
-	PERIPH_ID_UART3,
-
-	/* 56 */
-	PERIPH_ID_RESERVED56,
-	PERIPH_ID_EMC,
-	PERIPH_ID_USB2,
-	PERIPH_ID_USB3,
-	PERIPH_ID_MPE,
-	PERIPH_ID_VDE,
-	PERIPH_ID_BSEA,
-	PERIPH_ID_BSEV,
-
-	/* Upper word 95:64 */
-	PERIPH_ID_SPEEDO,
-	PERIPH_ID_UART4,
-	PERIPH_ID_UART5,
-	PERIPH_ID_I2C3,
-	PERIPH_ID_SBC4,
-	PERIPH_ID_SDMMC3,
-	PERIPH_ID_PCIE,
-	PERIPH_ID_OWR,
-
-	/* 72 */
-	PERIPH_ID_AFI,
-	PERIPH_ID_CORESIGHT,
-	PERIPH_ID_PCIEXCLK,
-	PERIPH_ID_AVPUCQ,
-	PERIPH_ID_RESERVED76,
-	PERIPH_ID_RESERVED77,
-	PERIPH_ID_RESERVED78,
-	PERIPH_ID_RESERVED79,
-
-	/* 80 */
-	PERIPH_ID_RESERVED80,
-	PERIPH_ID_RESERVED81,
-	PERIPH_ID_RESERVED82,
-	PERIPH_ID_RESERVED83,
-	PERIPH_ID_IRAMA,
-	PERIPH_ID_IRAMB,
-	PERIPH_ID_IRAMC,
-	PERIPH_ID_IRAMD,
-
-	/* 88 */
-	PERIPH_ID_CRAM2,
-	PERIPH_ID_SYNC_CLK_DOUBLER,
-	PERIPH_ID_CLK_M_DOUBLER,
-	PERIPH_ID_RESERVED91,
-	PERIPH_ID_SUS_OUT,
-	PERIPH_ID_DEV2_OUT,
-	PERIPH_ID_DEV1_OUT,
-
-	PERIPH_ID_COUNT,
-	PERIPH_ID_NONE = -1,
-};
-
-enum pll_out_id {
-	PLL_OUT1,
-	PLL_OUT2,
-	PLL_OUT3,
-	PLL_OUT4
-};
-
-/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
-#define PERIPH_REG(id) ((id) >> 5)
-
-/* Mask value for a clock (within PERIPH_REG(id)) */
-#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
-
-/* return 1 if a PLL ID is in range, and not a simple PLL */
-#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
-		(id) < CLOCK_ID_FIRST_SIMPLE)
-
-/* return 1 if a peripheral ID is in range */
-#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
-		(id) < PERIPH_ID_COUNT)
-
-#endif	/* _CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/clock.h b/arch/arm/include/asm/arch-tegra20/clock.h
deleted file mode 100644
index 8158b83..0000000
--- a/arch/arm/include/asm/arch-tegra20/clock.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- */
-
-/* Tegra20 clock control functions */
-
-#ifndef _TEGRA20_CLOCK_H
-#define _TEGRA20_CLOCK_H
-
-#include <asm/arch-tegra/clock.h>
-
-/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
-#define OSC_FREQ_SHIFT          30
-#define OSC_FREQ_MASK           (3U << OSC_FREQ_SHIFT)
-
-int tegra_plle_enable(void);
-
-#endif	/* _TEGRA20_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-tegra20/display.h b/arch/arm/include/asm/arch-tegra20/display.h
deleted file mode 100644
index e7b3cff..0000000
--- a/arch/arm/include/asm/arch-tegra20/display.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *  (C) Copyright 2010
- *  NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
-#define __ASM_ARCH_TEGRA_DISPLAY_H
-
-#include <asm/arch-tegra/dc.h>
-
-/* This holds information about a window which can be displayed */
-struct disp_ctl_win {
-	enum win_color_depth_id fmt;	/* Color depth/format */
-	unsigned	bpp;		/* Bits per pixel */
-	phys_addr_t	phys_addr;	/* Physical address in memory */
-	unsigned	x;		/* Horizontal address offset (bytes) */
-	unsigned	y;		/* Veritical address offset (bytes) */
-	unsigned	w;		/* Width of source window */
-	unsigned	h;		/* Height of source window */
-	unsigned	stride;		/* Number of bytes per line */
-	unsigned	out_x;		/* Left edge of output window (col) */
-	unsigned	out_y;		/* Top edge of output window (row) */
-	unsigned	out_w;		/* Width of output window in pixels */
-	unsigned	out_h;		/* Height of output window in pixels */
-};
-
-#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
diff --git a/arch/arm/include/asm/arch-tegra20/emc.h b/arch/arm/include/asm/arch-tegra20/emc.h
deleted file mode 100644
index 58ee08c..0000000
--- a/arch/arm/include/asm/arch-tegra20/emc.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _ARCH_EMC_H_
-#define _ARCH_EMC_H_
-
-#include <asm/types.h>
-
-#define TEGRA_EMC_NUM_REGS	46
-
-/* EMC Registers */
-struct emc_ctlr {
-	u32 cfg;		/* 0x00: EMC_CFG */
-	u32 reserved0[3];	/* 0x04 ~ 0x0C */
-	u32 adr_cfg;		/* 0x10: EMC_ADR_CFG */
-	u32 adr_cfg1;		/* 0x14: EMC_ADR_CFG_1 */
-	u32 reserved1[2];	/* 0x18 ~ 0x18 */
-	u32 refresh_ctrl;	/* 0x20: EMC_REFCTRL */
-	u32 pin;		/* 0x24: EMC_PIN */
-	u32 timing_ctrl;	/* 0x28: EMC_TIMING_CONTROL */
-	u32 rc;			/* 0x2C: EMC_RC */
-	u32 rfc;		/* 0x30: EMC_RFC */
-	u32 ras;		/* 0x34: EMC_RAS */
-	u32 rp;			/* 0x38: EMC_RP */
-	u32 r2w;		/* 0x3C: EMC_R2W */
-	u32 w2r;		/* 0x40: EMC_W2R */
-	u32 r2p;		/* 0x44: EMC_R2P */
-	u32 w2p;		/* 0x48: EMC_W2P */
-	u32 rd_rcd;		/* 0x4C: EMC_RD_RCD */
-	u32 wd_rcd;		/* 0x50: EMC_WD_RCD */
-	u32 rrd;		/* 0x54: EMC_RRD */
-	u32 rext;		/* 0x58: EMC_REXT */
-	u32 wdv;		/* 0x5C: EMC_WDV */
-	u32 quse;		/* 0x60: EMC_QUSE */
-	u32 qrst;		/* 0x64: EMC_QRST */
-	u32 qsafe;		/* 0x68: EMC_QSAFE */
-	u32 rdv;		/* 0x6C: EMC_RDV */
-	u32 refresh;		/* 0x70: EMC_REFRESH */
-	u32 burst_refresh_num;	/* 0x74: EMC_BURST_REFRESH_NUM */
-	u32 pdex2wr;		/* 0x78: EMC_PDEX2WR */
-	u32 pdex2rd;		/* 0x7c: EMC_PDEX2RD */
-	u32 pchg2pden;		/* 0x80: EMC_PCHG2PDEN */
-	u32 act2pden;		/* 0x84: EMC_ACT2PDEN */
-	u32 ar2pden;		/* 0x88: EMC_AR2PDEN */
-	u32 rw2pden;		/* 0x8C: EMC_RW2PDEN */
-	u32 txsr;		/* 0x90: EMC_TXSR */
-	u32 tcke;		/* 0x94: EMC_TCKE */
-	u32 tfaw;		/* 0x98: EMC_TFAW */
-	u32 trpab;		/* 0x9C: EMC_TRPAB */
-	u32 tclkstable;		/* 0xA0: EMC_TCLKSTABLE */
-	u32 tclkstop;		/* 0xA4: EMC_TCLKSTOP */
-	u32 trefbw;		/* 0xA8: EMC_TREFBW */
-	u32 quse_extra;		/* 0xAC: EMC_QUSE_EXTRA */
-	u32 odt_write;		/* 0xB0: EMC_ODT_WRITE */
-	u32 odt_read;		/* 0xB4: EMC_ODT_READ */
-	u32 reserved2[5];	/* 0xB8 ~ 0xC8 */
-	u32 mrs;		/* 0xCC: EMC_MRS */
-	u32 emrs;		/* 0xD0: EMC_EMRS */
-	u32 ref;		/* 0xD4: EMC_REF */
-	u32 pre;		/* 0xD8: EMC_PRE */
-	u32 nop;		/* 0xDC: EMC_NOP */
-	u32 self_ref;		/* 0xE0: EMC_SELF_REF */
-	u32 dpd;		/* 0xE4: EMC_DPD */
-	u32 mrw;		/* 0xE8: EMC_MRW */
-	u32 mrr;		/* 0xEC: EMC_MRR */
-	u32 reserved3;		/* 0xF0: */
-	u32 fbio_cfg1;		/* 0xF4: EMC_FBIO_CFG1 */
-	u32 fbio_dqsib_dly;	/* 0xF8: EMC_FBIO_DQSIB_DLY */
-	u32 fbio_dqsib_dly_msb;	/* 0xFC: EMC_FBIO_DQSIB_DLY_MSG */
-	u32 fbio_spare;		/* 0x100: SBIO_SPARE */
-				/* There are more registers ... */
-};
-
-/**
- * Set up the EMC for the given rate. The timing parameters are retrieved
- * from the device tree "nvidia,tegra20-emc" node and its
- * "nvidia,tegra20-emc-table" sub-nodes.
- *
- * @param blob	Device tree blob
- * @param rate	Clock speed of memory controller in Hz (=2x memory bus rate)
- * @return 0 if ok, else -ve error code (look in emc.c to decode it)
- */
-int tegra_set_emc(const void *blob, unsigned rate);
-
-/**
- * Get a pointer to the EMC controller from the device tree.
- *
- * @param blob	Device tree blob
- * @return pointer to EMC controller
- */
-struct emc_ctlr *emc_get_controller(const void *blob);
-
-#endif
diff --git a/arch/arm/include/asm/arch-tegra20/flow.h b/arch/arm/include/asm/arch-tegra20/flow.h
deleted file mode 100644
index 33be841..0000000
--- a/arch/arm/include/asm/arch-tegra20/flow.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010, 2011
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _FLOW_H_
-#define _FLOW_H_
-
-struct flow_ctlr {
-	u32	halt_cpu_events;
-	u32	halt_cop_events;
-	u32	cpu_csr;
-	u32	cop_csr;
-	u32	halt_cpu1_events;
-	u32	cpu1_csr;
-};
-
-#endif
diff --git a/arch/arm/include/asm/arch-tegra20/funcmux.h b/arch/arm/include/asm/arch-tegra20/funcmux.h
deleted file mode 100644
index e9e96c1..0000000
--- a/arch/arm/include/asm/arch-tegra20/funcmux.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- */
-
-/* Tegra20 high-level function multiplexing */
-
-#ifndef _TEGRA20_FUNCMUX_H_
-#define _TEGRA20_FUNCMUX_H_
-
-#include <asm/arch-tegra/funcmux.h>
-
-/* Configs supported by the func mux */
-enum {
-	FUNCMUX_DEFAULT = 0,	/* default config */
-
-	/* UART configs */
-	FUNCMUX_UART1_IRRX_IRTX = 0,
-	FUNCMUX_UART1_UAA_UAB,
-	FUNCMUX_UART1_GPU,
-	FUNCMUX_UART1_SDIO1,
-	FUNCMUX_UART2_UAD = 0,
-	FUNCMUX_UART4_GMC = 0,
-
-	/* I2C configs */
-	FUNCMUX_DVC_I2CP = 0,
-	FUNCMUX_I2C1_RM = 0,
-	FUNCMUX_I2C2_DDC = 0,
-	FUNCMUX_I2C2_PTA,
-	FUNCMUX_I2C3_DTF = 0,
-
-	/* SDMMC configs */
-	FUNCMUX_SDMMC1_SDIO1_4BIT = 0,
-	FUNCMUX_SDMMC2_DTA_DTD_8BIT = 0,
-	FUNCMUX_SDMMC3_SDB_4BIT = 0,
-	FUNCMUX_SDMMC3_SDB_SLXA_8BIT,
-	FUNCMUX_SDMMC4_ATC_ATD_8BIT = 0,
-	FUNCMUX_SDMMC4_ATB_GMA_4_BIT,
-	FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT,
-
-	/* USB configs */
-	FUNCMUX_USB2_ULPI = 0,
-
-	/* Serial Flash configs */
-	FUNCMUX_SPI1_GMC_GMD = 0,
-
-	/* NAND flags */
-	FUNCMUX_NDFLASH_ATC = 0,
-	FUNCMUX_NDFLASH_KBC_8_BIT,
-};
-#endif	/* _TEGRA20_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/gp_padctrl.h b/arch/arm/include/asm/arch-tegra20/gp_padctrl.h
deleted file mode 100644
index dd2ee12..0000000
--- a/arch/arm/include/asm/arch-tegra20/gp_padctrl.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *  (C) Copyright 2010,2011
- *  NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _TEGRA20_GP_PADCTRL_H_
-#define _TEGRA20_GP_PADCTRL_H_
-
-#include <asm/arch-tegra/gp_padctrl.h>
-
-/* APB_MISC_GP and padctrl registers */
-struct apb_misc_gp_ctlr {
-	u32	modereg;	/* 0x00: APB_MISC_GP_MODEREG */
-	u32	hidrev;		/* 0x04: APB_MISC_GP_HIDREV */
-	u32	reserved0[22];	/* 0x08 - 0x5C: */
-	u32	emu_revid;	/* 0x60: APB_MISC_GP_EMU_REVID */
-	u32	xactor_scratch;	/* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
-	u32	aocfg1;		/* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
-	u32	aocfg2;		/* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
-	u32	atcfg1;		/* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
-	u32	atcfg2;		/* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
-	u32	cdevcfg1;	/* 0x78: APB_MISC_GP_CDEV1CFGPADCTRL */
-	u32	cdevcfg2;	/* 0x7C: APB_MISC_GP_CDEV2CFGPADCTRL */
-	u32	csuscfg;	/* 0x80: APB_MISC_GP_CSUSCFGPADCTRL */
-	u32	dap1cfg;	/* 0x84: APB_MISC_GP_DAP1CFGPADCTRL */
-	u32	dap2cfg;	/* 0x88: APB_MISC_GP_DAP2CFGPADCTRL */
-	u32	dap3cfg;	/* 0x8C: APB_MISC_GP_DAP3CFGPADCTRL */
-	u32	dap4cfg;	/* 0x90: APB_MISC_GP_DAP4CFGPADCTRL */
-	u32	dbgcfg;		/* 0x94: APB_MISC_GP_DBGCFGPADCTRL */
-	u32	lcdcfg1;	/* 0x98: APB_MISC_GP_LCDCFG1PADCTRL */
-	u32	lcdcfg2;	/* 0x9C: APB_MISC_GP_LCDCFG2PADCTRL */
-	u32	sdmmc2_cfg;	/* 0xA0: APB_MISC_GP_SDMMC2CFGPADCTRL */
-	u32	sdmmc3_cfg;	/* 0xA4: APB_MISC_GP_SDMMC3CFGPADCTRL */
-	u32	spicfg;		/* 0xA8: APB_MISC_GP_SPICFGPADCTRL */
-	u32	uaacfg;		/* 0xAC: APB_MISC_GP_UAACFGPADCTRL */
-	u32	uabcfg;		/* 0xB0: APB_MISC_GP_UABCFGPADCTRL */
-	u32	uart2cfg;	/* 0xB4: APB_MISC_GP_UART2CFGPADCTRL */
-	u32	uart3cfg;	/* 0xB8: APB_MISC_GP_UART3CFGPADCTRL */
-	u32	vicfg1;		/* 0xBC: APB_MISC_GP_VICFG1PADCTRL */
-	u32	vicfg2;		/* 0xC0: APB_MISC_GP_VICFG2PADCTRL */
-	u32	xm2cfga;	/* 0xC4: APB_MISC_GP_XM2CFGAPADCTRL */
-	u32	xm2cfgc;	/* 0xC8: APB_MISC_GP_XM2CFGCPADCTRL */
-	u32	xm2cfgd;	/* 0xCC: APB_MISC_GP_XM2CFGDPADCTRL */
-	u32	xm2clkcfg;	/* 0xD0: APB_MISC_GP_XM2CLKCFGPADCTRL */
-	u32	memcomp;	/* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */
-};
-
-#endif	/* _TEGRA20_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/gpio.h b/arch/arm/include/asm/arch-tegra20/gpio.h
deleted file mode 100644
index 6818c28..0000000
--- a/arch/arm/include/asm/arch-tegra20/gpio.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2011, Google Inc. All rights reserved.
- * Portions Copyright 2011-2012 NVIDIA Corporation
- */
-
-#ifndef _TEGRA20_GPIO_H_
-#define _TEGRA20_GPIO_H_
-
-/*
- * The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports,
- * each with 8 GPIOs.
- */
-#define TEGRA_GPIO_PORTS	4	/* number of ports per bank */
-#define TEGRA_GPIO_BANKS	7	/* number of banks */
-
-#include <asm/arch-tegra/gpio.h>
-
-/* GPIO Controller registers for a single bank */
-struct gpio_ctlr_bank {
-	uint gpio_config[TEGRA_GPIO_PORTS];
-	uint gpio_dir_out[TEGRA_GPIO_PORTS];
-	uint gpio_out[TEGRA_GPIO_PORTS];
-	uint gpio_in[TEGRA_GPIO_PORTS];
-	uint gpio_int_status[TEGRA_GPIO_PORTS];
-	uint gpio_int_enable[TEGRA_GPIO_PORTS];
-	uint gpio_int_level[TEGRA_GPIO_PORTS];
-	uint gpio_int_clear[TEGRA_GPIO_PORTS];
-};
-
-struct gpio_ctlr {
-	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
-};
-
-#endif	/* TEGRA20_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/mc.h b/arch/arm/include/asm/arch-tegra20/mc.h
deleted file mode 100644
index 71283e4..0000000
--- a/arch/arm/include/asm/arch-tegra20/mc.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *  (C) Copyright 2014
- *  NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _TEGRA20_MC_H_
-#define _TEGRA20_MC_H_
-
-/**
- * Defines the memory controller registers we need/care about
- */
-struct mc_ctlr {
-	u32 reserved0[3];			/* offset 0x00 - 0x08 */
-	u32 mc_emem_cfg;			/* offset 0x0C */
-	u32 mc_emem_adr_cfg;			/* offset 0x10 */
-	u32 mc_emem_arb_cfg0;			/* offset 0x14 */
-	u32 mc_emem_arb_cfg1;			/* offset 0x18 */
-	u32 mc_emem_arb_cfg2;			/* offset 0x1C */
-	u32 reserved1;				/* offset 0x20 */
-	u32 mc_gart_cfg;			/* offset 0x24 */
-	u32 mc_gart_entry_addr;			/* offset 0x28 */
-	u32 mc_gart_entry_data;			/* offset 0x2C */
-	u32 mc_gart_error_req;			/* offset 0x30 */
-	u32 mc_gart_error_addr;			/* offset 0x34 */
-	u32 reserved2;				/* offset 0x38 */
-	u32 mc_timeout_ctrl;			/* offset 0x3C */
-	u32 reserved3[6];			/* offset 0x40 - 0x54 */
-	u32 mc_decerr_emem_others_status;	/* offset 0x58 */
-	u32 mc_decerr_emem_others_adr;		/* offset 0x5C */
-	u32 reserved4[40];			/* offset 0x60 - 0xFC */
-	u32 reserved5[93];			/* offset 0x100 - 0x270 */
-};
-
-#endif	/* _TEGRA20_MC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h
deleted file mode 100644
index e9e3801..0000000
--- a/arch/arm/include/asm/arch-tegra20/pinmux.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *  (C) Copyright 2010,2011
- *  NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _TEGRA20_PINMUX_H_
-#define _TEGRA20_PINMUX_H_
-
-/*
- * Pin groups which we adjust. There are three basic attributes of each pin
- * group which use this enum:
- *
- *	- function
- *	- pullup / pulldown
- *	- tristate or normal
- */
-enum pmux_pingrp {
-	/* APB_MISC_PP_TRISTATE_REG_A_0 */
-	PMUX_PINGRP_ATA,
-	PMUX_PINGRP_ATB,
-	PMUX_PINGRP_ATC,
-	PMUX_PINGRP_ATD,
-	PMUX_PINGRP_CDEV1,
-	PMUX_PINGRP_CDEV2,
-	PMUX_PINGRP_CSUS,
-	PMUX_PINGRP_DAP1,
-
-	PMUX_PINGRP_DAP2,
-	PMUX_PINGRP_DAP3,
-	PMUX_PINGRP_DAP4,
-	PMUX_PINGRP_DTA,
-	PMUX_PINGRP_DTB,
-	PMUX_PINGRP_DTC,
-	PMUX_PINGRP_DTD,
-	PMUX_PINGRP_DTE,
-
-	PMUX_PINGRP_GPU,
-	PMUX_PINGRP_GPV,
-	PMUX_PINGRP_I2CP,
-	PMUX_PINGRP_IRTX,
-	PMUX_PINGRP_IRRX,
-	PMUX_PINGRP_KBCB,
-	PMUX_PINGRP_KBCA,
-	PMUX_PINGRP_PMC,
-
-	PMUX_PINGRP_PTA,
-	PMUX_PINGRP_RM,
-	PMUX_PINGRP_KBCE,
-	PMUX_PINGRP_KBCF,
-	PMUX_PINGRP_GMA,
-	PMUX_PINGRP_GMC,
-	PMUX_PINGRP_SDIO1,
-	PMUX_PINGRP_OWC,
-
-	/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
-	PMUX_PINGRP_GME,
-	PMUX_PINGRP_SDC,
-	PMUX_PINGRP_SDD,
-	PMUX_PINGRP_RESERVED0,
-	PMUX_PINGRP_SLXA,
-	PMUX_PINGRP_SLXC,
-	PMUX_PINGRP_SLXD,
-	PMUX_PINGRP_SLXK,
-
-	PMUX_PINGRP_SPDI,
-	PMUX_PINGRP_SPDO,
-	PMUX_PINGRP_SPIA,
-	PMUX_PINGRP_SPIB,
-	PMUX_PINGRP_SPIC,
-	PMUX_PINGRP_SPID,
-	PMUX_PINGRP_SPIE,
-	PMUX_PINGRP_SPIF,
-
-	PMUX_PINGRP_SPIG,
-	PMUX_PINGRP_SPIH,
-	PMUX_PINGRP_UAA,
-	PMUX_PINGRP_UAB,
-	PMUX_PINGRP_UAC,
-	PMUX_PINGRP_UAD,
-	PMUX_PINGRP_UCA,
-	PMUX_PINGRP_UCB,
-
-	PMUX_PINGRP_RESERVED1,
-	PMUX_PINGRP_ATE,
-	PMUX_PINGRP_KBCC,
-	PMUX_PINGRP_RESERVED2,
-	PMUX_PINGRP_RESERVED3,
-	PMUX_PINGRP_GMB,
-	PMUX_PINGRP_GMD,
-	PMUX_PINGRP_DDC,
-
-	/* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
-	PMUX_PINGRP_LD0,
-	PMUX_PINGRP_LD1,
-	PMUX_PINGRP_LD2,
-	PMUX_PINGRP_LD3,
-	PMUX_PINGRP_LD4,
-	PMUX_PINGRP_LD5,
-	PMUX_PINGRP_LD6,
-	PMUX_PINGRP_LD7,
-
-	PMUX_PINGRP_LD8,
-	PMUX_PINGRP_LD9,
-	PMUX_PINGRP_LD10,
-	PMUX_PINGRP_LD11,
-	PMUX_PINGRP_LD12,
-	PMUX_PINGRP_LD13,
-	PMUX_PINGRP_LD14,
-	PMUX_PINGRP_LD15,
-
-	PMUX_PINGRP_LD16,
-	PMUX_PINGRP_LD17,
-	PMUX_PINGRP_LHP0,
-	PMUX_PINGRP_LHP1,
-	PMUX_PINGRP_LHP2,
-	PMUX_PINGRP_LVP0,
-	PMUX_PINGRP_LVP1,
-	PMUX_PINGRP_HDINT,
-
-	PMUX_PINGRP_LM0,
-	PMUX_PINGRP_LM1,
-	PMUX_PINGRP_LVS,
-	PMUX_PINGRP_LSC0,
-	PMUX_PINGRP_LSC1,
-	PMUX_PINGRP_LSCK,
-	PMUX_PINGRP_LDC,
-	PMUX_PINGRP_LCSN,
-
-	/* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
-	PMUX_PINGRP_LSPI,
-	PMUX_PINGRP_LSDA,
-	PMUX_PINGRP_LSDI,
-	PMUX_PINGRP_LPW0,
-	PMUX_PINGRP_LPW1,
-	PMUX_PINGRP_LPW2,
-	PMUX_PINGRP_LDI,
-	PMUX_PINGRP_LHS,
-
-	PMUX_PINGRP_LPP,
-	PMUX_PINGRP_RESERVED4,
-	PMUX_PINGRP_KBCD,
-	PMUX_PINGRP_GPU7,
-	PMUX_PINGRP_DTF,
-	PMUX_PINGRP_UDA,
-	PMUX_PINGRP_CRTP,
-	PMUX_PINGRP_SDB,
-
-	/* these pin groups only have pullup and pull down control */
-	PMUX_PINGRP_CK32,
-	PMUX_PINGRP_DDRC,
-	PMUX_PINGRP_PMCA,
-	PMUX_PINGRP_PMCB,
-	PMUX_PINGRP_PMCC,
-	PMUX_PINGRP_PMCD,
-	PMUX_PINGRP_PMCE,
-	PMUX_PINGRP_XM2C,
-	PMUX_PINGRP_XM2D,
-	PMUX_PINGRP_COUNT,
-};
-
-/*
- * Functions which can be assigned to each of the pin groups. The values here
- * bear no relation to the values programmed into pinmux registers and are
- * purely a convenience. The translation is done through a table search.
- */
-enum pmux_func {
-	PMUX_FUNC_DEFAULT,
-	PMUX_FUNC_AHB_CLK,
-	PMUX_FUNC_APB_CLK,
-	PMUX_FUNC_AUDIO_SYNC,
-	PMUX_FUNC_CRT,
-	PMUX_FUNC_DAP1,
-	PMUX_FUNC_DAP2,
-	PMUX_FUNC_DAP3,
-	PMUX_FUNC_DAP4,
-	PMUX_FUNC_DAP5,
-	PMUX_FUNC_DISPA,
-	PMUX_FUNC_DISPB,
-	PMUX_FUNC_EMC_TEST0_DLL,
-	PMUX_FUNC_EMC_TEST1_DLL,
-	PMUX_FUNC_GMI,
-	PMUX_FUNC_GMI_INT,
-	PMUX_FUNC_HDMI,
-	PMUX_FUNC_I2C,
-	PMUX_FUNC_I2C2,
-	PMUX_FUNC_I2C3,
-	PMUX_FUNC_IDE,
-	PMUX_FUNC_KBC,
-	PMUX_FUNC_MIO,
-	PMUX_FUNC_MIPI_HS,
-	PMUX_FUNC_NAND,
-	PMUX_FUNC_OSC,
-	PMUX_FUNC_OWR,
-	PMUX_FUNC_PCIE,
-	PMUX_FUNC_PLLA_OUT,
-	PMUX_FUNC_PLLC_OUT1,
-	PMUX_FUNC_PLLM_OUT1,
-	PMUX_FUNC_PLLP_OUT2,
-	PMUX_FUNC_PLLP_OUT3,
-	PMUX_FUNC_PLLP_OUT4,
-	PMUX_FUNC_PWM,
-	PMUX_FUNC_PWR_INTR,
-	PMUX_FUNC_PWR_ON,
-	PMUX_FUNC_RTCK,
-	PMUX_FUNC_SDIO1,
-	PMUX_FUNC_SDIO2,
-	PMUX_FUNC_SDIO3,
-	PMUX_FUNC_SDIO4,
-	PMUX_FUNC_SFLASH,
-	PMUX_FUNC_SPDIF,
-	PMUX_FUNC_SPI1,
-	PMUX_FUNC_SPI2,
-	PMUX_FUNC_SPI2_ALT,
-	PMUX_FUNC_SPI3,
-	PMUX_FUNC_SPI4,
-	PMUX_FUNC_TRACE,
-	PMUX_FUNC_TWC,
-	PMUX_FUNC_UARTA,
-	PMUX_FUNC_UARTB,
-	PMUX_FUNC_UARTC,
-	PMUX_FUNC_UARTD,
-	PMUX_FUNC_UARTE,
-	PMUX_FUNC_ULPI,
-	PMUX_FUNC_VI,
-	PMUX_FUNC_VI_SENSOR_CLK,
-	PMUX_FUNC_XIO,
-	PMUX_FUNC_RSVD1,
-	PMUX_FUNC_RSVD2,
-	PMUX_FUNC_RSVD3,
-	PMUX_FUNC_RSVD4,
-	PMUX_FUNC_COUNT,
-};
-
-#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
-#include <asm/arch-tegra/pinmux.h>
-
-#endif /* _TEGRA20_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/powergate.h b/arch/arm/include/asm/arch-tegra20/powergate.h
deleted file mode 100644
index 439d88b..0000000
--- a/arch/arm/include/asm/arch-tegra20/powergate.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _TEGRA20_POWERGATE_H_
-#define _TEGRA20_POWERGATE_H_
-
-#include <asm/arch-tegra/powergate.h>
-
-#endif /* _TEGRA20_POWERGATE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/pwm.h b/arch/arm/include/asm/arch-tegra20/pwm.h
deleted file mode 100644
index 9467617..0000000
--- a/arch/arm/include/asm/arch-tegra20/pwm.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Tegra pulse width frequency modulator definitions
- *
- * Copyright (c) 2011 The Chromium OS Authors.
- */
-
-#ifndef __ASM_ARCH_TEGRA20_PWM_H
-#define __ASM_ARCH_TEGRA20_PWM_H
-
-#include <asm/arch-tegra/pwm.h>
-
-#endif	/* __ASM_ARCH_TEGRA20_PWM_H */
diff --git a/arch/arm/include/asm/arch-tegra20/sdram_param.h b/arch/arm/include/asm/arch-tegra20/sdram_param.h
deleted file mode 100644
index 3d1405f..0000000
--- a/arch/arm/include/asm/arch-tegra20/sdram_param.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *  (C) Copyright 2010, 2011
- *  NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _SDRAM_PARAM_H_
-#define _SDRAM_PARAM_H_
-
-/*
- * Defines the number of 32-bit words provided in each set of SDRAM parameters
- * for arbitration configuration data.
- */
-#define BCT_SDRAM_ARB_CONFIG_WORDS 27
-
-enum memory_type {
-	MEMORY_TYPE_NONE = 0,
-	MEMORY_TYPE_DDR,
-	MEMORY_TYPE_LPDDR,
-	MEMORY_TYPE_DDR2,
-	MEMORY_TYPE_LPDDR2,
-	MEMORY_TYPE_NUM,
-	MEMORY_TYPE_FORCE32 = 0x7FFFFFFF
-};
-
-/* Defines the SDRAM parameter structure */
-struct sdram_params {
-	enum memory_type memory_type;
-	u32 pllm_charge_pump_setup_control;
-	u32 pllm_loop_filter_setup_control;
-	u32 pllm_input_divider;
-	u32 pllm_feedback_divider;
-	u32 pllm_post_divider;
-	u32 pllm_stable_time;
-	u32 emc_clock_divider;
-	u32 emc_auto_cal_interval;
-	u32 emc_auto_cal_config;
-	u32 emc_auto_cal_wait;
-	u32 emc_pin_program_wait;
-	u32 emc_rc;
-	u32 emc_rfc;
-	u32 emc_ras;
-	u32 emc_rp;
-	u32 emc_r2w;
-	u32 emc_w2r;
-	u32 emc_r2p;
-	u32 emc_w2p;
-	u32 emc_rd_rcd;
-	u32 emc_wr_rcd;
-	u32 emc_rrd;
-	u32 emc_rext;
-	u32 emc_wdv;
-	u32 emc_quse;
-	u32 emc_qrst;
-	u32 emc_qsafe;
-	u32 emc_rdv;
-	u32 emc_refresh;
-	u32 emc_burst_refresh_num;
-	u32 emc_pdex2wr;
-	u32 emc_pdex2rd;
-	u32 emc_pchg2pden;
-	u32 emc_act2pden;
-	u32 emc_ar2pden;
-	u32 emc_rw2pden;
-	u32 emc_txsr;
-	u32 emc_tcke;
-	u32 emc_tfaw;
-	u32 emc_trpab;
-	u32 emc_tclkstable;
-	u32 emc_tclkstop;
-	u32 emc_trefbw;
-	u32 emc_quseextra;
-	u32 emc_fbioc_fg1;
-	u32 emc_fbio_dqsib_dly;
-	u32 emc_fbio_dqsib_dly_msb;
-	u32 emc_fbio_quse_dly;
-	u32 emc_fbio_quse_dly_msb;
-	u32 emc_fbio_cfg5;
-	u32 emc_fbio_cfg6;
-	u32 emc_fbio_spare;
-	u32 emc_mrs;
-	u32 emc_emrs;
-	u32 emc_mrw1;
-	u32 emc_mrw2;
-	u32 emc_mrw3;
-	u32 emc_mrw_reset_command;
-	u32 emc_mrw_reset_init_wait;
-	u32 emc_adr_cfg;
-	u32 emc_adr_cfg1;
-	u32 emc_emem_cfg;
-	u32 emc_low_latency_config;
-	u32 emc_cfg;
-	u32 emc_cfg2;
-	u32 emc_dbg;
-	u32 ahb_arbitration_xbar_ctrl;
-	u32 emc_cfg_dig_dll;
-	u32 emc_dll_xform_dqs;
-	u32 emc_dll_xform_quse;
-	u32 warm_boot_wait;
-	u32 emc_ctt_term_ctrl;
-	u32 emc_odt_write;
-	u32 emc_odt_read;
-	u32 emc_zcal_ref_cnt;
-	u32 emc_zcal_wait_cnt;
-	u32 emc_zcal_mrw_cmd;
-	u32 emc_mrs_reset_dll;
-	u32 emc_mrw_zq_init_dev0;
-	u32 emc_mrw_zq_init_dev1;
-	u32 emc_mrw_zq_init_wait;
-	u32 emc_mrs_reset_dll_wait;
-	u32 emc_emrs_emr2;
-	u32 emc_emrs_emr3;
-	u32 emc_emrs_ddr2_dll_enable;
-	u32 emc_mrs_ddr2_dll_reset;
-	u32 emc_emrs_ddr2_ocd_calib;
-	u32 emc_edr2_wait;
-	u32 emc_cfg_clktrim0;
-	u32 emc_cfg_clktrim1;
-	u32 emc_cfg_clktrim2;
-	u32 pmc_ddr_pwr;
-	u32 apb_misc_gp_xm2cfga_padctrl;
-	u32 apb_misc_gp_xm2cfgc_padctrl;
-	u32 apb_misc_gp_xm2cfgc_padctrl2;
-	u32 apb_misc_gp_xm2cfgd_padctrl;
-	u32 apb_misc_gp_xm2cfgd_padctrl2;
-	u32 apb_misc_gp_xm2clkcfg_padctrl;
-	u32 apb_misc_gp_xm2comp_padctrl;
-	u32 apb_misc_gp_xm2vttgen_padctrl;
-	u32 arbitration_config[BCT_SDRAM_ARB_CONFIG_WORDS];
-};
-#endif
diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h
deleted file mode 100644
index 3fecbcd..0000000
--- a/arch/arm/include/asm/arch-tegra20/tegra.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _TEGRA20_H_
-#define _TEGRA20_H_
-
-#define NV_PA_SDRAM_BASE	0x00000000
-#define NV_PA_MC_BASE		0x7000F000
-
-#include <asm/arch-tegra/tegra.h>
-
-#define TEGRA_USB1_BASE		0xC5000000
-
-#define BCT_ODMDATA_OFFSET	4068	/* 12 bytes from end of BCT */
-
-#define MAX_NUM_CPU		2
-
-#endif	/* TEGRA20_H */