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-rw-r--r--arch/arm/include/asm/arch-tegra30/clock-tables.h372
-rw-r--r--arch/arm/include/asm/arch-tegra30/clock.h19
-rw-r--r--arch/arm/include/asm/arch-tegra30/flow.h24
-rw-r--r--arch/arm/include/asm/arch-tegra30/funcmux.h20
-rw-r--r--arch/arm/include/asm/arch-tegra30/gp_padctrl.h54
-rw-r--r--arch/arm/include/asm/arch-tegra30/gpio.h42
-rw-r--r--arch/arm/include/asm/arch-tegra30/mc.h37
-rw-r--r--arch/arm/include/asm/arch-tegra30/pinmux.h404
-rw-r--r--arch/arm/include/asm/arch-tegra30/powergate.h6
-rw-r--r--arch/arm/include/asm/arch-tegra30/tegra.h20
10 files changed, 0 insertions, 998 deletions
diff --git a/arch/arm/include/asm/arch-tegra30/clock-tables.h b/arch/arm/include/asm/arch-tegra30/clock-tables.h
deleted file mode 100644
index 8588009..0000000
--- a/arch/arm/include/asm/arch-tegra30/clock-tables.h
+++ /dev/null
@@ -1,372 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
- */
-
-/* Tegra30 clock PLL tables */
-
-#ifndef _TEGRA30_CLOCK_TABLES_H_
-#define _TEGRA30_CLOCK_TABLES_H_
-
-/* The PLLs supported by the hardware */
-enum clock_id {
- CLOCK_ID_FIRST,
- CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
- CLOCK_ID_MEMORY,
- CLOCK_ID_PERIPH,
- CLOCK_ID_AUDIO,
- CLOCK_ID_USB,
- CLOCK_ID_DISPLAY,
-
- /* now the simple ones */
- CLOCK_ID_FIRST_SIMPLE,
- CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
- CLOCK_ID_EPCI,
- CLOCK_ID_SFROM32KHZ,
-
- /* These are the base clocks (inputs to the Tegra SOC) */
- CLOCK_ID_32KHZ,
- CLOCK_ID_OSC,
- CLOCK_ID_CLK_M,
-
- CLOCK_ID_COUNT, /* number of PLLs */
- CLOCK_ID_DISPLAY2, /* Tegra3, placeholder */
- CLOCK_ID_NONE = -1,
-};
-
-/* The clocks supported by the hardware */
-enum periph_id {
- PERIPH_ID_FIRST,
-
- /* Low word: 31:0 */
- PERIPH_ID_CPU = PERIPH_ID_FIRST,
- PERIPH_ID_COP,
- PERIPH_ID_TRIGSYS,
- PERIPH_ID_RESERVED3,
- PERIPH_ID_RESERVED4,
- PERIPH_ID_TMR,
- PERIPH_ID_UART1,
- PERIPH_ID_UART2,
-
- /* 8 */
- PERIPH_ID_GPIO,
- PERIPH_ID_SDMMC2,
- PERIPH_ID_SPDIF,
- PERIPH_ID_I2S1,
- PERIPH_ID_I2C1,
- PERIPH_ID_NDFLASH,
- PERIPH_ID_SDMMC1,
- PERIPH_ID_SDMMC4,
-
- /* 16 */
- PERIPH_ID_RESERVED16,
- PERIPH_ID_PWM,
- PERIPH_ID_I2S2,
- PERIPH_ID_EPP,
- PERIPH_ID_VI,
- PERIPH_ID_2D,
- PERIPH_ID_USBD,
- PERIPH_ID_ISP,
-
- /* 24 */
- PERIPH_ID_3D,
- PERIPH_ID_RESERVED24,
- PERIPH_ID_DISP2,
- PERIPH_ID_DISP1,
- PERIPH_ID_HOST1X,
- PERIPH_ID_VCP,
- PERIPH_ID_I2S0,
- PERIPH_ID_CACHE2,
-
- /* Middle word: 63:32 */
- PERIPH_ID_MEM,
- PERIPH_ID_AHBDMA,
- PERIPH_ID_APBDMA,
- PERIPH_ID_RESERVED35,
- PERIPH_ID_KBC,
- PERIPH_ID_STAT_MON,
- PERIPH_ID_PMC,
- PERIPH_ID_FUSE,
-
- /* 40 */
- PERIPH_ID_KFUSE,
- PERIPH_ID_SBC1,
- PERIPH_ID_SNOR,
- PERIPH_ID_RESERVED43,
- PERIPH_ID_SBC2,
- PERIPH_ID_RESERVED45,
- PERIPH_ID_SBC3,
- PERIPH_ID_DVC_I2C,
-
- /* 48 */
- PERIPH_ID_DSI,
- PERIPH_ID_TVO,
- PERIPH_ID_MIPI,
- PERIPH_ID_HDMI,
- PERIPH_ID_CSI,
- PERIPH_ID_TVDAC,
- PERIPH_ID_I2C2,
- PERIPH_ID_UART3,
-
- /* 56 */
- PERIPH_ID_RESERVED56,
- PERIPH_ID_EMC,
- PERIPH_ID_USB2,
- PERIPH_ID_USB3,
- PERIPH_ID_MPE,
- PERIPH_ID_VDE,
- PERIPH_ID_BSEA,
- PERIPH_ID_BSEV,
-
- /* Upper word 95:64 */
- PERIPH_ID_SPEEDO,
- PERIPH_ID_UART4,
- PERIPH_ID_UART5,
- PERIPH_ID_I2C3,
- PERIPH_ID_SBC4,
- PERIPH_ID_SDMMC3,
- PERIPH_ID_PCIE,
- PERIPH_ID_OWR,
-
- /* 72 */
- PERIPH_ID_AFI,
- PERIPH_ID_CORESIGHT,
- PERIPH_ID_PCIEXCLK,
- PERIPH_ID_AVPUCQ,
- PERIPH_ID_RESERVED76,
- PERIPH_ID_RESERVED77,
- PERIPH_ID_RESERVED78,
- PERIPH_ID_DTV,
-
- /* 80 */
- PERIPH_ID_NANDSPEED,
- PERIPH_ID_I2CSLOW,
- PERIPH_ID_DSIB,
- PERIPH_ID_RESERVED83,
- PERIPH_ID_IRAMA,
- PERIPH_ID_IRAMB,
- PERIPH_ID_IRAMC,
- PERIPH_ID_IRAMD,
-
- /* 88 */
- PERIPH_ID_CRAM2,
- PERIPH_ID_RESERVED89,
- PERIPH_ID_MDOUBLER,
- PERIPH_ID_RESERVED91,
- PERIPH_ID_SUSOUT,
- PERIPH_ID_RESERVED93,
- PERIPH_ID_RESERVED94,
- PERIPH_ID_RESERVED95,
-
- PERIPH_ID_VW_FIRST,
- /* V word: 31:0 */
- PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
- PERIPH_ID_CPULP,
- PERIPH_ID_3D2,
- PERIPH_ID_MSELECT,
- PERIPH_ID_TSENSOR,
- PERIPH_ID_I2S3,
- PERIPH_ID_I2S4,
- PERIPH_ID_I2C4,
-
- /* 08 */
- PERIPH_ID_SBC5,
- PERIPH_ID_SBC6,
- PERIPH_ID_AUDIO,
- PERIPH_ID_APBIF,
- PERIPH_ID_DAM0,
- PERIPH_ID_DAM1,
- PERIPH_ID_DAM2,
- PERIPH_ID_HDA2CODEC2X,
-
- /* 16 */
- PERIPH_ID_ATOMICS,
- PERIPH_ID_EX_RESERVED17,
- PERIPH_ID_EX_RESERVED18,
- PERIPH_ID_EX_RESERVED19,
- PERIPH_ID_EX_RESERVED20,
- PERIPH_ID_EX_RESERVED21,
- PERIPH_ID_EX_RESERVED22,
- PERIPH_ID_ACTMON,
-
- /* 24 */
- PERIPH_ID_EX_RESERVED24,
- PERIPH_ID_EX_RESERVED25,
- PERIPH_ID_EX_RESERVED26,
- PERIPH_ID_EX_RESERVED27,
- PERIPH_ID_SATA,
- PERIPH_ID_HDA,
- PERIPH_ID_EX_RESERVED30,
- PERIPH_ID_EX_RESERVED31,
-
- /* W word: 31:0 */
- PERIPH_ID_HDA2HDMICODEC,
- PERIPH_ID_SATACOLD,
- PERIPH_ID_RESERVED0_PCIERX0,
- PERIPH_ID_RESERVED1_PCIERX1,
- PERIPH_ID_RESERVED2_PCIERX2,
- PERIPH_ID_RESERVED3_PCIERX3,
- PERIPH_ID_RESERVED4_PCIERX4,
- PERIPH_ID_RESERVED5_PCIERX5,
-
- /* 40 */
- PERIPH_ID_CEC,
- PERIPH_ID_RESERVED6_PCIE2,
- PERIPH_ID_RESERVED7_EMC,
- PERIPH_ID_RESERVED8_HDMI,
- PERIPH_ID_RESERVED9_SATA,
- PERIPH_ID_RESERVED10_MIPI,
- PERIPH_ID_EX_RESERVED46,
- PERIPH_ID_EX_RESERVED47,
-
- PERIPH_ID_COUNT,
- PERIPH_ID_NONE = -1,
-};
-
-enum pll_out_id {
- PLL_OUT1,
- PLL_OUT2,
- PLL_OUT3,
- PLL_OUT4
-};
-
-/*
- * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
- * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
- * confusion bewteen PERIPH_ID_... and PERIPHC_...
- *
- * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
- * confusing.
- */
-enum periphc_internal_id {
- /* 0x00 */
- PERIPHC_I2S1,
- PERIPHC_I2S2,
- PERIPHC_SPDIF_OUT,
- PERIPHC_SPDIF_IN,
- PERIPHC_PWM,
- PERIPHC_05h,
- PERIPHC_SBC2,
- PERIPHC_SBC3,
-
- /* 0x08 */
- PERIPHC_08h,
- PERIPHC_I2C1,
- PERIPHC_DVC_I2C,
- PERIPHC_0bh,
- PERIPHC_0ch,
- PERIPHC_SBC1,
- PERIPHC_DISP1,
- PERIPHC_DISP2,
-
- /* 0x10 */
- PERIPHC_CVE,
- PERIPHC_11h,
- PERIPHC_VI,
- PERIPHC_13h,
- PERIPHC_SDMMC1,
- PERIPHC_SDMMC2,
- PERIPHC_G3D,
- PERIPHC_G2D,
-
- /* 0x18 */
- PERIPHC_NDFLASH,
- PERIPHC_SDMMC4,
- PERIPHC_VFIR,
- PERIPHC_EPP,
- PERIPHC_MPE,
- PERIPHC_MIPI,
- PERIPHC_UART1,
- PERIPHC_UART2,
-
- /* 0x20 */
- PERIPHC_HOST1X,
- PERIPHC_21h,
- PERIPHC_TVO,
- PERIPHC_HDMI,
- PERIPHC_24h,
- PERIPHC_TVDAC,
- PERIPHC_I2C2,
- PERIPHC_EMC,
-
- /* 0x28 */
- PERIPHC_UART3,
- PERIPHC_29h,
- PERIPHC_VI_SENSOR,
- PERIPHC_2bh,
- PERIPHC_2ch,
- PERIPHC_SBC4,
- PERIPHC_I2C3,
- PERIPHC_SDMMC3,
-
- /* 0x30 */
- PERIPHC_UART4,
- PERIPHC_UART5,
- PERIPHC_VDE,
- PERIPHC_OWR,
- PERIPHC_NOR,
- PERIPHC_CSITE,
- PERIPHC_I2S0,
- PERIPHC_37h,
-
- PERIPHC_VW_FIRST,
- /* 0x38 */
- PERIPHC_G3D2 = PERIPHC_VW_FIRST,
- PERIPHC_MSELECT,
- PERIPHC_TSENSOR,
- PERIPHC_I2S3,
- PERIPHC_I2S4,
- PERIPHC_I2C4,
- PERIPHC_SBC5,
- PERIPHC_SBC6,
-
- /* 0x40 */
- PERIPHC_AUDIO,
- PERIPHC_41h,
- PERIPHC_DAM0,
- PERIPHC_DAM1,
- PERIPHC_DAM2,
- PERIPHC_HDA2CODEC2X,
- PERIPHC_ACTMON,
- PERIPHC_EXTPERIPH1,
-
- /* 0x48 */
- PERIPHC_EXTPERIPH2,
- PERIPHC_EXTPERIPH3,
- PERIPHC_NANDSPEED,
- PERIPHC_I2CSLOW,
- PERIPHC_SYS,
- PERIPHC_SPEEDO,
- PERIPHC_4eh,
- PERIPHC_4fh,
-
- /* 0x50 */
- PERIPHC_50h,
- PERIPHC_51h,
- PERIPHC_52h,
- PERIPHC_53h,
- PERIPHC_SATAOOB,
- PERIPHC_SATA,
- PERIPHC_HDA,
-
- PERIPHC_COUNT,
-
- PERIPHC_NONE = -1,
-};
-
-/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
-#define PERIPH_REG(id) \
- (id < PERIPH_ID_VW_FIRST) ? \
- ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
-
-/* Mask value for a clock (within PERIPH_REG(id)) */
-#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
-
-/* return 1 if a PLL ID is in range */
-#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
-
-/* return 1 if a peripheral ID is in range */
-#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
- (id) < PERIPH_ID_COUNT)
-
-#endif /* _TEGRA30_CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/clock.h b/arch/arm/include/asm/arch-tegra30/clock.h
deleted file mode 100644
index 7f5a115..0000000
--- a/arch/arm/include/asm/arch-tegra30/clock.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
- */
-
-/* Tegra30 clock control functions */
-
-#ifndef _TEGRA30_CLOCK_H_
-#define _TEGRA30_CLOCK_H_
-
-#include <asm/arch-tegra/clock.h>
-
-/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
-#define OSC_FREQ_SHIFT 28
-#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
-
-int tegra_plle_enable(void);
-
-#endif /* _TEGRA30_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/flow.h b/arch/arm/include/asm/arch-tegra30/flow.h
deleted file mode 100644
index f3e947e..0000000
--- a/arch/arm/include/asm/arch-tegra30/flow.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
- */
-
-#ifndef _TEGRA30_FLOW_H_
-#define _TEGRA30_FLOW_H_
-
-struct flow_ctlr {
- u32 halt_cpu_events;
- u32 halt_cop_events;
- u32 cpu_csr;
- u32 cop_csr;
- u32 xrq_events;
- u32 halt_cpu1_events;
- u32 cpu1_csr;
- u32 halt_cpu2_events;
- u32 cpu2_csr;
- u32 halt_cpu3_events;
- u32 cpu3_csr;
- u32 cluster_control;
-};
-
-#endif /* _TEGRA30_FLOW_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/funcmux.h b/arch/arm/include/asm/arch-tegra30/funcmux.h
deleted file mode 100644
index 2e8b335..0000000
--- a/arch/arm/include/asm/arch-tegra30/funcmux.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
- */
-
-/* Tegra30 high-level function multiplexing */
-
-#ifndef _TEGRA30_FUNCMUX_H_
-#define _TEGRA30_FUNCMUX_H_
-
-#include <asm/arch-tegra/funcmux.h>
-
-/* Configs supported by the func mux */
-enum {
- FUNCMUX_DEFAULT = 0, /* default config */
-
- /* UART configs */
- FUNCMUX_UART1_ULPI = 0,
-};
-#endif /* _TEGRA30_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h
deleted file mode 100644
index 4ff785d..0000000
--- a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
- */
-
-#ifndef _TEGRA30_GP_PADCTRL_H_
-#define _TEGRA30_GP_PADCTRL_H_
-
-#include <asm/arch-tegra/gp_padctrl.h>
-
-/* APB_MISC_GP and padctrl registers */
-struct apb_misc_gp_ctlr {
- u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
- u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
- u32 reserved0[22]; /* 0x08 - 0x5C: */
- u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
- u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
- u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
- u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
- u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
- u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
- u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
- u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
- u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
- u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
- u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
- u32 csuscfg; /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */
- u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
- u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
- u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
- u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
- u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
- u32 lcdcfg1; /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */
- u32 lcdcfg2; /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */
- u32 sdio2cfg; /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */
- u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
- u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
- u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
- u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
- u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
- u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
- u32 vicfg1; /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */
- u32 vivttgen; /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */
- u32 reserved1[7]; /* 0xD0-0xE8: */
- u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
-};
-
-/* SDMMC1/3 settings from section 24.6 of T30 TRM */
-#define SDIOCFG_DRVUP_SLWF 1
-#define SDIOCFG_DRVDN_SLWR 1
-#define SDIOCFG_DRVUP 0x2E
-#define SDIOCFG_DRVDN 0x2A
-
-#endif /* _TEGRA30_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/gpio.h b/arch/arm/include/asm/arch-tegra30/gpio.h
deleted file mode 100644
index 1dd2e42..0000000
--- a/arch/arm/include/asm/arch-tegra30/gpio.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
- */
-
-#ifndef _TEGRA30_GPIO_H_
-#define _TEGRA30_GPIO_H_
-
-/*
- * The Tegra 3x GPIO controller has 246 GPIOS in 8 banks of 4 ports,
- * each with 8 GPIOs.
- */
-#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */
-#define TEGRA_GPIO_BANKS 8 /* number of banks */
-
-#include <asm/arch-tegra/gpio.h>
-
-/* GPIO Controller registers for a single bank */
-struct gpio_ctlr_bank {
- uint gpio_config[TEGRA_GPIO_PORTS];
- uint gpio_dir_out[TEGRA_GPIO_PORTS];
- uint gpio_out[TEGRA_GPIO_PORTS];
- uint gpio_in[TEGRA_GPIO_PORTS];
- uint gpio_int_status[TEGRA_GPIO_PORTS];
- uint gpio_int_enable[TEGRA_GPIO_PORTS];
- uint gpio_int_level[TEGRA_GPIO_PORTS];
- uint gpio_int_clear[TEGRA_GPIO_PORTS];
- uint gpio_masked_config[TEGRA_GPIO_PORTS];
- uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
- uint gpio_masked_out[TEGRA_GPIO_PORTS];
- uint gpio_masked_in[TEGRA_GPIO_PORTS];
- uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
- uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
- uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
- uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
-};
-
-struct gpio_ctlr {
- struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
-};
-
-#endif /* _TEGRA30_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/mc.h b/arch/arm/include/asm/arch-tegra30/mc.h
deleted file mode 100644
index bbb0fe7..0000000
--- a/arch/arm/include/asm/arch-tegra30/mc.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2014
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _TEGRA30_MC_H_
-#define _TEGRA30_MC_H_
-
-/**
- * Defines the memory controller registers we need/care about
- */
-struct mc_ctlr {
- u32 reserved0[4]; /* offset 0x00 - 0x0C */
- u32 mc_smmu_config; /* offset 0x10 */
- u32 mc_smmu_tlb_config; /* offset 0x14 */
- u32 mc_smmu_ptc_config; /* offset 0x18 */
- u32 mc_smmu_ptb_asid; /* offset 0x1C */
- u32 mc_smmu_ptb_data; /* offset 0x20 */
- u32 reserved1[3]; /* offset 0x24 - 0x2C */
- u32 mc_smmu_tlb_flush; /* offset 0x30 */
- u32 mc_smmu_ptc_flush; /* offset 0x34 */
- u32 mc_smmu_asid_security; /* offset 0x38 */
- u32 reserved2[5]; /* offset 0x3C - 0x4C */
- u32 mc_emem_cfg; /* offset 0x50 */
- u32 mc_emem_adr_cfg; /* offset 0x54 */
- u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */
- u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */
- u32 reserved3[12]; /* offset 0x60 - 0x8C */
- u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */
- u32 reserved4[338]; /* offset 0x100 - 0x644 */
- u32 mc_video_protect_bom; /* offset 0x648 */
- u32 mc_video_protect_size_mb; /* offset 0x64c */
- u32 mc_video_protect_reg_ctrl; /* offset 0x650 */
-};
-
-#endif /* _TEGRA30_MC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h
deleted file mode 100644
index 1261943..0000000
--- a/arch/arm/include/asm/arch-tegra30/pinmux.h
+++ /dev/null
@@ -1,404 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
- */
-
-#ifndef _TEGRA30_PINMUX_H_
-#define _TEGRA30_PINMUX_H_
-
-enum pmux_pingrp {
- PMUX_PINGRP_ULPI_DATA0_PO1,
- PMUX_PINGRP_ULPI_DATA1_PO2,
- PMUX_PINGRP_ULPI_DATA2_PO3,
- PMUX_PINGRP_ULPI_DATA3_PO4,
- PMUX_PINGRP_ULPI_DATA4_PO5,
- PMUX_PINGRP_ULPI_DATA5_PO6,
- PMUX_PINGRP_ULPI_DATA6_PO7,
- PMUX_PINGRP_ULPI_DATA7_PO0,
- PMUX_PINGRP_ULPI_CLK_PY0,
- PMUX_PINGRP_ULPI_DIR_PY1,
- PMUX_PINGRP_ULPI_NXT_PY2,
- PMUX_PINGRP_ULPI_STP_PY3,
- PMUX_PINGRP_DAP3_FS_PP0,
- PMUX_PINGRP_DAP3_DIN_PP1,
- PMUX_PINGRP_DAP3_DOUT_PP2,
- PMUX_PINGRP_DAP3_SCLK_PP3,
- PMUX_PINGRP_PV0,
- PMUX_PINGRP_PV1,
- PMUX_PINGRP_SDMMC1_CLK_PZ0,
- PMUX_PINGRP_SDMMC1_CMD_PZ1,
- PMUX_PINGRP_SDMMC1_DAT3_PY4,
- PMUX_PINGRP_SDMMC1_DAT2_PY5,
- PMUX_PINGRP_SDMMC1_DAT1_PY6,
- PMUX_PINGRP_SDMMC1_DAT0_PY7,
- PMUX_PINGRP_PV2,
- PMUX_PINGRP_PV3,
- PMUX_PINGRP_CLK2_OUT_PW5,
- PMUX_PINGRP_CLK2_REQ_PCC5,
- PMUX_PINGRP_LCD_PWR1_PC1,
- PMUX_PINGRP_LCD_PWR2_PC6,
- PMUX_PINGRP_LCD_SDIN_PZ2,
- PMUX_PINGRP_LCD_SDOUT_PN5,
- PMUX_PINGRP_LCD_WR_N_PZ3,
- PMUX_PINGRP_LCD_CS0_N_PN4,
- PMUX_PINGRP_LCD_DC0_PN6,
- PMUX_PINGRP_LCD_SCK_PZ4,
- PMUX_PINGRP_LCD_PWR0_PB2,
- PMUX_PINGRP_LCD_PCLK_PB3,
- PMUX_PINGRP_LCD_DE_PJ1,
- PMUX_PINGRP_LCD_HSYNC_PJ3,
- PMUX_PINGRP_LCD_VSYNC_PJ4,
- PMUX_PINGRP_LCD_D0_PE0,
- PMUX_PINGRP_LCD_D1_PE1,
- PMUX_PINGRP_LCD_D2_PE2,
- PMUX_PINGRP_LCD_D3_PE3,
- PMUX_PINGRP_LCD_D4_PE4,
- PMUX_PINGRP_LCD_D5_PE5,
- PMUX_PINGRP_LCD_D6_PE6,
- PMUX_PINGRP_LCD_D7_PE7,
- PMUX_PINGRP_LCD_D8_PF0,
- PMUX_PINGRP_LCD_D9_PF1,
- PMUX_PINGRP_LCD_D10_PF2,
- PMUX_PINGRP_LCD_D11_PF3,
- PMUX_PINGRP_LCD_D12_PF4,
- PMUX_PINGRP_LCD_D13_PF5,
- PMUX_PINGRP_LCD_D14_PF6,
- PMUX_PINGRP_LCD_D15_PF7,
- PMUX_PINGRP_LCD_D16_PM0,
- PMUX_PINGRP_LCD_D17_PM1,
- PMUX_PINGRP_LCD_D18_PM2,
- PMUX_PINGRP_LCD_D19_PM3,
- PMUX_PINGRP_LCD_D20_PM4,
- PMUX_PINGRP_LCD_D21_PM5,
- PMUX_PINGRP_LCD_D22_PM6,
- PMUX_PINGRP_LCD_D23_PM7,
- PMUX_PINGRP_LCD_CS1_N_PW0,
- PMUX_PINGRP_LCD_M1_PW1,
- PMUX_PINGRP_LCD_DC1_PD2,
- PMUX_PINGRP_HDMI_INT_PN7,
- PMUX_PINGRP_DDC_SCL_PV4,
- PMUX_PINGRP_DDC_SDA_PV5,
- PMUX_PINGRP_CRT_HSYNC_PV6,
- PMUX_PINGRP_CRT_VSYNC_PV7,
- PMUX_PINGRP_VI_D0_PT4,
- PMUX_PINGRP_VI_D1_PD5,
- PMUX_PINGRP_VI_D2_PL0,
- PMUX_PINGRP_VI_D3_PL1,
- PMUX_PINGRP_VI_D4_PL2,
- PMUX_PINGRP_VI_D5_PL3,
- PMUX_PINGRP_VI_D6_PL4,
- PMUX_PINGRP_VI_D7_PL5,
- PMUX_PINGRP_VI_D8_PL6,
- PMUX_PINGRP_VI_D9_PL7,
- PMUX_PINGRP_VI_D10_PT2,
- PMUX_PINGRP_VI_D11_PT3,
- PMUX_PINGRP_VI_PCLK_PT0,
- PMUX_PINGRP_VI_MCLK_PT1,
- PMUX_PINGRP_VI_VSYNC_PD6,
- PMUX_PINGRP_VI_HSYNC_PD7,
- PMUX_PINGRP_UART2_RXD_PC3,
- PMUX_PINGRP_UART2_TXD_PC2,
- PMUX_PINGRP_UART2_RTS_N_PJ6,
- PMUX_PINGRP_UART2_CTS_N_PJ5,
- PMUX_PINGRP_UART3_TXD_PW6,
- PMUX_PINGRP_UART3_RXD_PW7,
- PMUX_PINGRP_UART3_CTS_N_PA1,
- PMUX_PINGRP_UART3_RTS_N_PC0,
- PMUX_PINGRP_PU0,
- PMUX_PINGRP_PU1,
- PMUX_PINGRP_PU2,
- PMUX_PINGRP_PU3,
- PMUX_PINGRP_PU4,
- PMUX_PINGRP_PU5,
- PMUX_PINGRP_PU6,
- PMUX_PINGRP_GEN1_I2C_SDA_PC5,
- PMUX_PINGRP_GEN1_I2C_SCL_PC4,
- PMUX_PINGRP_DAP4_FS_PP4,
- PMUX_PINGRP_DAP4_DIN_PP5,
- PMUX_PINGRP_DAP4_DOUT_PP6,
- PMUX_PINGRP_DAP4_SCLK_PP7,
- PMUX_PINGRP_CLK3_OUT_PEE0,
- PMUX_PINGRP_CLK3_REQ_PEE1,
- PMUX_PINGRP_GMI_WP_N_PC7,
- PMUX_PINGRP_GMI_IORDY_PI5,
- PMUX_PINGRP_GMI_WAIT_PI7,
- PMUX_PINGRP_GMI_ADV_N_PK0,
- PMUX_PINGRP_GMI_CLK_PK1,
- PMUX_PINGRP_GMI_CS0_N_PJ0,
- PMUX_PINGRP_GMI_CS1_N_PJ2,
- PMUX_PINGRP_GMI_CS2_N_PK3,
- PMUX_PINGRP_GMI_CS3_N_PK4,
- PMUX_PINGRP_GMI_CS4_N_PK2,
- PMUX_PINGRP_GMI_CS6_N_PI3,
- PMUX_PINGRP_GMI_CS7_N_PI6,
- PMUX_PINGRP_GMI_AD0_PG0,
- PMUX_PINGRP_GMI_AD1_PG1,
- PMUX_PINGRP_GMI_AD2_PG2,
- PMUX_PINGRP_GMI_AD3_PG3,
- PMUX_PINGRP_GMI_AD4_PG4,
- PMUX_PINGRP_GMI_AD5_PG5,
- PMUX_PINGRP_GMI_AD6_PG6,
- PMUX_PINGRP_GMI_AD7_PG7,
- PMUX_PINGRP_GMI_AD8_PH0,
- PMUX_PINGRP_GMI_AD9_PH1,
- PMUX_PINGRP_GMI_AD10_PH2,
- PMUX_PINGRP_GMI_AD11_PH3,
- PMUX_PINGRP_GMI_AD12_PH4,
- PMUX_PINGRP_GMI_AD13_PH5,
- PMUX_PINGRP_GMI_AD14_PH6,
- PMUX_PINGRP_GMI_AD15_PH7,
- PMUX_PINGRP_GMI_A16_PJ7,
- PMUX_PINGRP_GMI_A17_PB0,
- PMUX_PINGRP_GMI_A18_PB1,
- PMUX_PINGRP_GMI_A19_PK7,
- PMUX_PINGRP_GMI_WR_N_PI0,
- PMUX_PINGRP_GMI_OE_N_PI1,
- PMUX_PINGRP_GMI_DQS_PI2,
- PMUX_PINGRP_GMI_RST_N_PI4,
- PMUX_PINGRP_GEN2_I2C_SCL_PT5,
- PMUX_PINGRP_GEN2_I2C_SDA_PT6,
- PMUX_PINGRP_SDMMC4_CLK_PCC4,
- PMUX_PINGRP_SDMMC4_CMD_PT7,
- PMUX_PINGRP_SDMMC4_DAT0_PAA0,
- PMUX_PINGRP_SDMMC4_DAT1_PAA1,
- PMUX_PINGRP_SDMMC4_DAT2_PAA2,
- PMUX_PINGRP_SDMMC4_DAT3_PAA3,
- PMUX_PINGRP_SDMMC4_DAT4_PAA4,
- PMUX_PINGRP_SDMMC4_DAT5_PAA5,
- PMUX_PINGRP_SDMMC4_DAT6_PAA6,
- PMUX_PINGRP_SDMMC4_DAT7_PAA7,
- PMUX_PINGRP_SDMMC4_RST_N_PCC3,
- PMUX_PINGRP_CAM_MCLK_PCC0,
- PMUX_PINGRP_PCC1,
- PMUX_PINGRP_PBB0,
- PMUX_PINGRP_CAM_I2C_SCL_PBB1,
- PMUX_PINGRP_CAM_I2C_SDA_PBB2,
- PMUX_PINGRP_PBB3,
- PMUX_PINGRP_PBB4,
- PMUX_PINGRP_PBB5,
- PMUX_PINGRP_PBB6,
- PMUX_PINGRP_PBB7,
- PMUX_PINGRP_PCC2,
- PMUX_PINGRP_JTAG_RTCK_PU7,
- PMUX_PINGRP_PWR_I2C_SCL_PZ6,
- PMUX_PINGRP_PWR_I2C_SDA_PZ7,
- PMUX_PINGRP_KB_ROW0_PR0,
- PMUX_PINGRP_KB_ROW1_PR1,
- PMUX_PINGRP_KB_ROW2_PR2,
- PMUX_PINGRP_KB_ROW3_PR3,
- PMUX_PINGRP_KB_ROW4_PR4,
- PMUX_PINGRP_KB_ROW5_PR5,
- PMUX_PINGRP_KB_ROW6_PR6,
- PMUX_PINGRP_KB_ROW7_PR7,
- PMUX_PINGRP_KB_ROW8_PS0,
- PMUX_PINGRP_KB_ROW9_PS1,
- PMUX_PINGRP_KB_ROW10_PS2,
- PMUX_PINGRP_KB_ROW11_PS3,
- PMUX_PINGRP_KB_ROW12_PS4,
- PMUX_PINGRP_KB_ROW13_PS5,
- PMUX_PINGRP_KB_ROW14_PS6,
- PMUX_PINGRP_KB_ROW15_PS7,
- PMUX_PINGRP_KB_COL0_PQ0,
- PMUX_PINGRP_KB_COL1_PQ1,
- PMUX_PINGRP_KB_COL2_PQ2,
- PMUX_PINGRP_KB_COL3_PQ3,
- PMUX_PINGRP_KB_COL4_PQ4,
- PMUX_PINGRP_KB_COL5_PQ5,
- PMUX_PINGRP_KB_COL6_PQ6,
- PMUX_PINGRP_KB_COL7_PQ7,
- PMUX_PINGRP_CLK_32K_OUT_PA0,
- PMUX_PINGRP_SYS_CLK_REQ_PZ5,
- PMUX_PINGRP_CORE_PWR_REQ,
- PMUX_PINGRP_CPU_PWR_REQ,
- PMUX_PINGRP_PWR_INT_N,
- PMUX_PINGRP_CLK_32K_IN,
- PMUX_PINGRP_OWR,
- PMUX_PINGRP_DAP1_FS_PN0,
- PMUX_PINGRP_DAP1_DIN_PN1,
- PMUX_PINGRP_DAP1_DOUT_PN2,
- PMUX_PINGRP_DAP1_SCLK_PN3,
- PMUX_PINGRP_CLK1_REQ_PEE2,
- PMUX_PINGRP_CLK1_OUT_PW4,
- PMUX_PINGRP_SPDIF_IN_PK6,
- PMUX_PINGRP_SPDIF_OUT_PK5,
- PMUX_PINGRP_DAP2_FS_PA2,
- PMUX_PINGRP_DAP2_DIN_PA4,
- PMUX_PINGRP_DAP2_DOUT_PA5,
- PMUX_PINGRP_DAP2_SCLK_PA3,
- PMUX_PINGRP_SPI2_MOSI_PX0,
- PMUX_PINGRP_SPI2_MISO_PX1,
- PMUX_PINGRP_SPI2_CS0_N_PX3,
- PMUX_PINGRP_SPI2_SCK_PX2,
- PMUX_PINGRP_SPI1_MOSI_PX4,
- PMUX_PINGRP_SPI1_SCK_PX5,
- PMUX_PINGRP_SPI1_CS0_N_PX6,
- PMUX_PINGRP_SPI1_MISO_PX7,
- PMUX_PINGRP_SPI2_CS1_N_PW2,
- PMUX_PINGRP_SPI2_CS2_N_PW3,
- PMUX_PINGRP_SDMMC3_CLK_PA6,
- PMUX_PINGRP_SDMMC3_CMD_PA7,
- PMUX_PINGRP_SDMMC3_DAT0_PB7,
- PMUX_PINGRP_SDMMC3_DAT1_PB6,
- PMUX_PINGRP_SDMMC3_DAT2_PB5,
- PMUX_PINGRP_SDMMC3_DAT3_PB4,
- PMUX_PINGRP_SDMMC3_DAT4_PD1,
- PMUX_PINGRP_SDMMC3_DAT5_PD0,
- PMUX_PINGRP_SDMMC3_DAT6_PD3,
- PMUX_PINGRP_SDMMC3_DAT7_PD4,
- PMUX_PINGRP_PEX_L0_PRSNT_N_PDD0,
- PMUX_PINGRP_PEX_L0_RST_N_PDD1,
- PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2,
- PMUX_PINGRP_PEX_WAKE_N_PDD3,
- PMUX_PINGRP_PEX_L1_PRSNT_N_PDD4,
- PMUX_PINGRP_PEX_L1_RST_N_PDD5,
- PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6,
- PMUX_PINGRP_PEX_L2_PRSNT_N_PDD7,
- PMUX_PINGRP_PEX_L2_RST_N_PCC6,
- PMUX_PINGRP_PEX_L2_CLKREQ_N_PCC7,
- PMUX_PINGRP_HDMI_CEC_PEE3,
- PMUX_PINGRP_COUNT,
-};
-
-enum pmux_drvgrp {
- PMUX_DRVGRP_AO1,
- PMUX_DRVGRP_AO2,
- PMUX_DRVGRP_AT1,
- PMUX_DRVGRP_AT2,
- PMUX_DRVGRP_AT3,
- PMUX_DRVGRP_AT4,
- PMUX_DRVGRP_AT5,
- PMUX_DRVGRP_CDEV1,
- PMUX_DRVGRP_CDEV2,
- PMUX_DRVGRP_CSUS,
- PMUX_DRVGRP_DAP1,
- PMUX_DRVGRP_DAP2,
- PMUX_DRVGRP_DAP3,
- PMUX_DRVGRP_DAP4,
- PMUX_DRVGRP_DBG,
- PMUX_DRVGRP_LCD1,
- PMUX_DRVGRP_LCD2,
- PMUX_DRVGRP_SDIO2,
- PMUX_DRVGRP_SDIO3,
- PMUX_DRVGRP_SPI,
- PMUX_DRVGRP_UAA,
- PMUX_DRVGRP_UAB,
- PMUX_DRVGRP_UART2,
- PMUX_DRVGRP_UART3,
- PMUX_DRVGRP_VI1,
- PMUX_DRVGRP_SDIO1 = (0x84 / 4),
- PMUX_DRVGRP_CRT = (0x90 / 4),
- PMUX_DRVGRP_DDC,
- PMUX_DRVGRP_GMA,
- PMUX_DRVGRP_GMB,
- PMUX_DRVGRP_GMC,
- PMUX_DRVGRP_GMD,
- PMUX_DRVGRP_GME,
- PMUX_DRVGRP_GMF,
- PMUX_DRVGRP_GMG,
- PMUX_DRVGRP_GMH,
- PMUX_DRVGRP_OWR,
- PMUX_DRVGRP_UDA,
- PMUX_DRVGRP_GPV,
- PMUX_DRVGRP_DEV3,
- PMUX_DRVGRP_CEC = (0xd0 / 4),
- PMUX_DRVGRP_COUNT,
-};
-
-enum pmux_func {
- PMUX_FUNC_DEFAULT,
- PMUX_FUNC_BLINK,
- PMUX_FUNC_CEC,
- PMUX_FUNC_CLK_12M_OUT,
- PMUX_FUNC_CLK_32K_IN,
- PMUX_FUNC_CORE_PWR_REQ,
- PMUX_FUNC_CPU_PWR_REQ,
- PMUX_FUNC_CRT,
- PMUX_FUNC_DAP,
- PMUX_FUNC_DDR,
- PMUX_FUNC_DEV3,
- PMUX_FUNC_DISPLAYA,
- PMUX_FUNC_DISPLAYB,
- PMUX_FUNC_DTV,
- PMUX_FUNC_EXTPERIPH1,
- PMUX_FUNC_EXTPERIPH2,
- PMUX_FUNC_EXTPERIPH3,
- PMUX_FUNC_GMI,
- PMUX_FUNC_GMI_ALT,
- PMUX_FUNC_HDA,
- PMUX_FUNC_HDCP,
- PMUX_FUNC_HDMI,
- PMUX_FUNC_HSI,
- PMUX_FUNC_I2C1,
- PMUX_FUNC_I2C2,
- PMUX_FUNC_I2C3,
- PMUX_FUNC_I2C4,
- PMUX_FUNC_I2CPWR,
- PMUX_FUNC_I2S0,
- PMUX_FUNC_I2S1,
- PMUX_FUNC_I2S2,
- PMUX_FUNC_I2S3,
- PMUX_FUNC_I2S4,
- PMUX_FUNC_INVALID,
- PMUX_FUNC_KBC,
- PMUX_FUNC_MIO,
- PMUX_FUNC_NAND,
- PMUX_FUNC_NAND_ALT,
- PMUX_FUNC_OWR,
- PMUX_FUNC_PCIE,
- PMUX_FUNC_PWM0,
- PMUX_FUNC_PWM1,
- PMUX_FUNC_PWM2,
- PMUX_FUNC_PWM3,
- PMUX_FUNC_PWR_INT_N,
- PMUX_FUNC_RTCK,
- PMUX_FUNC_SATA,
- PMUX_FUNC_SDMMC1,
- PMUX_FUNC_SDMMC2,
- PMUX_FUNC_SDMMC3,
- PMUX_FUNC_SDMMC4,
- PMUX_FUNC_SPDIF,
- PMUX_FUNC_SPI1,
- PMUX_FUNC_SPI2,
- PMUX_FUNC_SPI2_ALT,
- PMUX_FUNC_SPI3,
- PMUX_FUNC_SPI4,
- PMUX_FUNC_SPI5,
- PMUX_FUNC_SPI6,
- PMUX_FUNC_SYSCLK,
- PMUX_FUNC_TEST,
- PMUX_FUNC_TRACE,
- PMUX_FUNC_UARTA,
- PMUX_FUNC_UARTB,
- PMUX_FUNC_UARTC,
- PMUX_FUNC_UARTD,
- PMUX_FUNC_UARTE,
- PMUX_FUNC_ULPI,
- PMUX_FUNC_VGP1,
- PMUX_FUNC_VGP2,
- PMUX_FUNC_VGP3,
- PMUX_FUNC_VGP4,
- PMUX_FUNC_VGP5,
- PMUX_FUNC_VGP6,
- PMUX_FUNC_VI,
- PMUX_FUNC_VI_ALT1,
- PMUX_FUNC_VI_ALT2,
- PMUX_FUNC_VI_ALT3,
- PMUX_FUNC_RSVD1,
- PMUX_FUNC_RSVD2,
- PMUX_FUNC_RSVD3,
- PMUX_FUNC_RSVD4,
- PMUX_FUNC_COUNT,
-};
-
-#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
-#define TEGRA_PMX_SOC_HAS_DRVGRPS
-#define TEGRA_PMX_GRPS_HAVE_LPMD
-#define TEGRA_PMX_GRPS_HAVE_SCHMT
-#define TEGRA_PMX_GRPS_HAVE_HSM
-#define TEGRA_PMX_PINS_HAVE_E_INPUT
-#define TEGRA_PMX_PINS_HAVE_LOCK
-#define TEGRA_PMX_PINS_HAVE_OD
-#define TEGRA_PMX_PINS_HAVE_IO_RESET
-#include <asm/arch-tegra/pinmux.h>
-
-#endif /* _TEGRA30_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/powergate.h b/arch/arm/include/asm/arch-tegra30/powergate.h
deleted file mode 100644
index c70e44b..0000000
--- a/arch/arm/include/asm/arch-tegra30/powergate.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _TEGRA30_POWERGATE_H_
-#define _TEGRA30_POWERGATE_H_
-
-#include <asm/arch-tegra/powergate.h>
-
-#endif /* _TEGRA30_POWERGATE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h
deleted file mode 100644
index 1de7d2f..0000000
--- a/arch/arm/include/asm/arch-tegra30/tegra.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
- */
-
-#ifndef _TEGRA30_H_
-#define _TEGRA30_H_
-
-#define NV_PA_MC_BASE 0x7000F000
-#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */
-
-#include <asm/arch-tegra/tegra.h>
-
-#define TEGRA_USB1_BASE 0x7D000000
-
-#define BCT_ODMDATA_OFFSET 6116 /* 12 bytes from end of BCT */
-
-#define MAX_NUM_CPU 4
-
-#endif /* TEGRA30_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-19 12:42:18 +0000