diff options
Diffstat (limited to 'arch/arm/include/asm/arch-vf610')
| -rw-r--r-- | arch/arm/include/asm/arch-vf610/clock.h | 31 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-vf610/crm_regs.h | 275 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-vf610/ddrmc-vf610.h | 83 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-vf610/gpio.h | 28 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-vf610/imx-regs.h | 479 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-vf610/iomux-vf610.h | 255 |
6 files changed, 0 insertions, 1151 deletions
diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h deleted file mode 100644 index 72184fd..0000000 --- a/arch/arm/include/asm/arch-vf610/clock.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#include <common.h> - -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_BUS_CLK, - MXC_IPG_CLK, - MXC_UART_CLK, - MXC_ESDHC_CLK, - MXC_FEC_CLK, - MXC_I2C_CLK, - MXC_DSPI_CLK, -}; - -void enable_ocotp_clk(unsigned char enable); -unsigned int mxc_get_clock(enum mxc_clock clk); -u32 get_lpuart_clk(void); -#ifdef CONFIG_SYS_I2C_MXC -int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); -#endif - -#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK) - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h deleted file mode 100644 index 0c9ed52..0000000 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ /dev/null @@ -1,275 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - */ - -#ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__ -#define __ARCH_ARM_MACH_VF610_CCM_REGS_H__ - -#ifndef __ASSEMBLY__ - -#include <linux/types.h> - -/* Clock Controller Module (CCM) */ -struct ccm_reg { - u32 ccr; - u32 csr; - u32 ccsr; - u32 cacrr; - u32 cscmr1; - u32 cscdr1; - u32 cscdr2; - u32 cscdr3; - u32 cscmr2; - u32 cscdr4; - u32 ctor; - u32 clpcr; - u32 cisr; - u32 cimr; - u32 ccosr; - u32 cgpr; - u32 ccgr0; - u32 ccgr1; - u32 ccgr2; - u32 ccgr3; - u32 ccgr4; - u32 ccgr5; - u32 ccgr6; - u32 ccgr7; - u32 ccgr8; - u32 ccgr9; - u32 ccgr10; - u32 ccgr11; - u32 cmeor0; - u32 cmeor1; - u32 cmeor2; - u32 cmeor3; - u32 cmeor4; - u32 cmeor5; - u32 cppdsr; - u32 ccowr; - u32 ccpgr0; - u32 ccpgr1; - u32 ccpgr2; - u32 ccpgr3; -}; - -/* Analog components control digital interface (ANADIG) */ -struct anadig_reg { - u32 reserved_0x000[4]; - u32 pll3_ctrl; - u32 reserved_0x014[3]; - u32 pll7_ctrl; - u32 reserved_0x024[3]; - u32 pll2_ctrl; - u32 reserved_0x034[3]; - u32 pll2_ss; - u32 reserved_0x044[3]; - u32 pll2_num; - u32 reserved_0x054[3]; - u32 pll2_denom; - u32 reserved_0x064[3]; - u32 pll4_ctrl; - u32 reserved_0x074[3]; - u32 pll4_num; - u32 reserved_0x084[3]; - u32 pll4_denom; - u32 reserved_0x094[3]; - u32 pll6_ctrl; - u32 reserved_0x0A4[3]; - u32 pll6_num; - u32 reserved_0x0B4[3]; - u32 pll6_denom; - u32 reserved_0x0C4[7]; - u32 pll5_ctrl; - u32 reserved_0x0E4[3]; - u32 pll3_pfd; - u32 reserved_0x0F4[3]; - u32 pll2_pfd; - u32 reserved_0x104[3]; - u32 reg_1p1; - u32 reserved_0x114[3]; - u32 reg_3p0; - u32 reserved_0x124[3]; - u32 reg_2p5; - u32 reserved_0x134[7]; - u32 ana_misc0; - u32 reserved_0x154[3]; - u32 ana_misc1; - u32 reserved_0x164[63]; - u32 anadig_digprog; - u32 reserved_0x264[3]; - u32 pll1_ctrl; - u32 reserved_0x274[3]; - u32 pll1_ss; - u32 reserved_0x284[3]; - u32 pll1_num; - u32 reserved_0x294[3]; - u32 pll1_denom; - u32 reserved_0x2A4[3]; - u32 pll1_pdf; - u32 reserved_0x2B4[3]; - u32 pll_lock; -}; -#endif - -#define CCM_CCR_FIRC_EN (1 << 16) -#define CCM_CCR_OSCNT_MASK 0xff -#define CCM_CCR_OSCNT(v) ((v) & 0xff) - -#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19 -#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19) -#define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19) - -#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16 -#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16) -#define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16) - -#define CCM_CCSR_PLL2_PFD4_EN (1 << 15) -#define CCM_CCSR_PLL2_PFD3_EN (1 << 14) -#define CCM_CCSR_PLL2_PFD2_EN (1 << 13) -#define CCM_CCSR_PLL2_PFD1_EN (1 << 12) -#define CCM_CCSR_PLL1_PFD4_EN (1 << 11) -#define CCM_CCSR_PLL1_PFD3_EN (1 << 10) -#define CCM_CCSR_PLL1_PFD2_EN (1 << 9) -#define CCM_CCSR_PLL1_PFD1_EN (1 << 8) - -#define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6) -#define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5) - -#define CCM_CCSR_SYS_CLK_SEL_OFFSET 0 -#define CCM_CCSR_SYS_CLK_SEL_MASK 0x7 -#define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7) - -#define CCM_CACRR_IPG_CLK_DIV_OFFSET 11 -#define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11) -#define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11) -#define CCM_CACRR_BUS_CLK_DIV_OFFSET 3 -#define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3) -#define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3) -#define CCM_CACRR_ARM_CLK_DIV_OFFSET 0 -#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7 -#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7) - -#define CCM_CSCMR1_DCU1_CLK_SEL (1 << 29) -#define CCM_CSCMR1_DCU0_CLK_SEL (1 << 28) - -#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET 22 -#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22) -#define CCM_CSCMR1_QSPI0_CLK_SEL(v) (((v) & 0x3) << 22) -#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18 -#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18) -#define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18) -#define CCM_CSCMR1_NFC_CLK_SEL_OFFSET 12 -#define CCM_CSCMR1_NFC_CLK_SEL_MASK (0x3 << 12) -#define CCM_CSCMR1_NFC_CLK_SEL(v) (((v) & 0x3) << 12) - -#define CCM_CSCDR1_RMII_CLK_EN (1 << 24) - -#define CCM_CSCDR2_NFC_EN (1 << 9) -#define CCM_CSCDR2_NFC_FRAC_DIV_EN (1 << 13) -#define CCM_CSCDR2_NFC_CLK_INV (1 << 14) -#define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET 4 -#define CCM_CSCDR2_NFC_FRAC_DIV_MASK (0xf << 4) -#define CCM_CSCDR2_NFC_FRAC_DIV(v) (((v) & 0xf) << 4) - -#define CCM_CSCDR2_ESDHC1_EN (1 << 29) -#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20 -#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20) -#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20) - -#define CCM_CSCDR3_DCU1_EN (1 << 23) -#define CCM_CSCDR3_DCU1_DIV_MASK (0x7 << 20) -#define CCM_CSCDR3_DCU1_DIV(v) (((v) & 0x7) << 20) -#define CCM_CSCDR3_DCU0_EN (1 << 19) -#define CCM_CSCDR3_DCU0_DIV_MASK (0x7 << 16) -#define CCM_CSCDR3_DCU0_DIV(v) (((v) & 0x7) << 16) - -#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET 13 -#define CCM_CSCDR3_NFC_PRE_DIV_MASK (0x7 << 13) -#define CCM_CSCDR3_NFC_PRE_DIV(v) (((v) & 0x7) << 13) -#define CCM_CSCDR3_QSPI0_EN (1 << 4) -#define CCM_CSCDR3_QSPI0_DIV(v) ((v) << 3) -#define CCM_CSCDR3_QSPI0_X2_DIV(v) ((v) << 2) -#define CCM_CSCDR3_QSPI0_X4_DIV(v) ((v) & 0x3) - -#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4 -#define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4) -#define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4) - -#define CCM_REG_CTRL_MASK 0xffffffff -#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14) -#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) -#define CCM_CCGR0_UART2_CTRL_MASK (0x3 << 18) -#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24) -#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26) -#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8) -#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) -#define CCM_CCGR1_TCON0_CTRL_MASK (0x3 << 26) -#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) -#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8) -#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16) -#define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18) -#define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20) -#define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22) -#define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24) -#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26) -#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3 -#define CCM_CCGR3_SCSC_CTRL_MASK (0x3 << 4) -#define CCM_CCGR3_DCU0_CTRL_MASK (0x3 << 16) -#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20) -#define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22) -#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24) -#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12) -#define CCM_CCGR4_I2C1_CTRL_MASK (0x3 << 14) -#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10) -#define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24) -#define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26) -#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28) -#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4) -#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8) -#define CCM_CCGR9_FEC0_CTRL_MASK 0x3 -#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2) -#define CCM_CCGR10_NFC_CTRL_MASK 0x3 -#define CCM_CCGR10_I2C2_CTRL_MASK (0x3 << 12) -#define CCM_CCGR10_I2C3_CTRL_MASK (0x3 << 14) - -#define ANADIG_PLL7_CTRL_BYPASS (1 << 16) -#define ANADIG_PLL7_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL7_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL7_CTRL_DIV_SELECT (1 << 1) -#define ANADIG_PLL5_CTRL_BYPASS (1 << 16) -#define ANADIG_PLL5_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL5_CTRL_DIV_SELECT 1 -#define ANADIG_PLL3_CTRL_BYPASS (1 << 16) -#define ANADIG_PLL3_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL3_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL3_CTRL_DIV_SELECT (1 << 1) -#define ANADIG_PLL2_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL2_CTRL_DIV_SELECT 1 -#define ANADIG_PLL1_CTRL_ENABLE (1 << 13) -#define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12) -#define ANADIG_PLL1_CTRL_DIV_SELECT 1 - -#define FASE_CLK_FREQ 24000000 -#define SLOW_CLK_FREQ 32000 -#define PLL1_PFD1_FREQ 500000000 -#define PLL1_PFD2_FREQ 452000000 -#define PLL1_PFD3_FREQ 396000000 -#define PLL1_PFD4_FREQ 528000000 -#define PLL1_MAIN_FREQ 528000000 -#define PLL2_PFD1_FREQ 500000000 -#define PLL2_PFD2_FREQ 396000000 -#define PLL2_PFD3_FREQ 339000000 -#define PLL2_PFD4_FREQ 413000000 -#define PLL2_MAIN_FREQ 528000000 -#define PLL3_MAIN_FREQ 480000000 -#define PLL3_PFD3_FREQ 298000000 -#define PLL5_MAIN_FREQ 500000000 - -#define ENET_EXTERNAL_CLK 50000000 -#define AUDIO_EXTERNAL_CLK 24576000 - -#endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h deleted file mode 100644 index 03e3cec..0000000 --- a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 - * Toradex, Inc. - * - * Authors: Stefan Agner - * Sanchayan Maity - */ - -#ifndef __ASM_ARCH_VF610_DDRMC_H -#define __ASM_ARCH_VF610_DDRMC_H - -#include <asm/arch/iomux-vf610.h> - -struct ddr3_jedec_timings { - u8 tinit; - u32 trst_pwron; - u32 cke_inactive; - u8 wrlat; - u8 caslat_lin; - u8 trc; - u8 trrd; - u8 tccd; - u8 tbst_int_interval; - u8 tfaw; - u8 trp; - u8 twtr; - u8 tras_min; - u8 tmrd; - u8 trtp; - u32 tras_max; - u8 tmod; - u8 tckesr; - u8 tcke; - u8 trcd_int; - u8 tras_lockout; - u8 tdal; - u8 bstlen; - u16 tdll; - u8 trp_ab; - u16 tref; - u8 trfc; - u16 tref_int; - u8 tpdex; - u8 txpdll; - u8 txsnr; - u16 txsr; - u8 cksrx; - u8 cksre; - u8 freq_chg_en; - u16 zqcl; - u16 zqinit; - u8 zqcs; - u8 ref_per_zq; - u8 zqcs_rotate; - u8 aprebit; - u8 cmd_age_cnt; - u8 age_cnt; - u8 q_fullness; - u8 odt_rd_mapcs0; - u8 odt_wr_mapcs0; - u8 wlmrd; - u8 wldqsen; -}; - -struct ddrmc_cr_setting { - u32 setting; - int cr_rnum; /* CR register ; -1 for last entry */ -}; - -struct ddrmc_phy_setting { - u32 setting; - int phy_rnum; /* PHY register ; -1 for last entry */ -}; - -void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count); -void ddrmc_phy_init(void); -void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, - struct ddrmc_cr_setting *board_cr_settings, - struct ddrmc_phy_setting *board_phy_settings, - int col_diff, int row_diff); - -#endif diff --git a/arch/arm/include/asm/arch-vf610/gpio.h b/arch/arm/include/asm/arch-vf610/gpio.h deleted file mode 100644 index 9bfdf16..0000000 --- a/arch/arm/include/asm/arch-vf610/gpio.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2015 - * Bhuvanchandra DV, Toradex, Inc. - */ - -#ifndef __ASM_ARCH_VF610_GPIO_H -#define __ASM_ARCH_VF610_GPIO_H - -#define VYBRID_GPIO_COUNT 32 -#define VF610_GPIO_DIRECTION_IN 0x0 -#define VF610_GPIO_DIRECTION_OUT 0x1 - -/* GPIO registers */ -struct vybrid_gpio_regs { - u32 gpio_pdor; - u32 gpio_psor; - u32 gpio_pcor; - u32 gpio_ptor; - u32 gpio_pdir; -}; - -struct vybrid_gpio_platdata { - unsigned int chip; - u32 base; - const char *port_name; -}; -#endif /* __ASM_ARCH_VF610_GPIO_H */ diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h deleted file mode 100644 index ae0a187..0000000 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ /dev/null @@ -1,479 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - */ - -#ifndef __ASM_ARCH_IMX_REGS_H__ -#define __ASM_ARCH_IMX_REGS_H__ - -#define ARCH_MXC - -#define IRAM_BASE_ADDR 0x3F000000 /* internal ram */ -#define IRAM_SIZE 0x00080000 /* 512 KB */ - -#define AIPS0_BASE_ADDR 0x40000000 -#define AIPS1_BASE_ADDR 0x40080000 - -/* AIPS 0 */ -#define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000) -#define MSCM_IR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001800) -#define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000) -#define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000) -#define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000) -#define NIC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00008000) -#define NIC1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00009000) -#define NIC2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000) -#define NIC3_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000) -#define NIC4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000C000) -#define NIC5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000) -#define NIC6_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000E000) -#define NIC7_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000F000) -#define AHBTZASC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000) -#define TZASC_SYS0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00011000) -#define TZASC_SYS1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00012000) -#define TZASC_GFX_BASE_ADDR (AIPS0_BASE_ADDR + 0x00013000) -#define TZASC_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00014000) -#define TZASC_DDR1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00015000) -#define CSU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00017000) -#define DMA0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00018000) -#define DMA0_TCD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00019000) -#define SEMA4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001D000) -#define FB_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001E000) -#define DMA_MUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00024000) -#define UART0_BASE (AIPS0_BASE_ADDR + 0x00027000) -#define UART1_BASE (AIPS0_BASE_ADDR + 0x00028000) -#define UART2_BASE (AIPS0_BASE_ADDR + 0x00029000) -#define UART3_BASE (AIPS0_BASE_ADDR + 0x0002A000) -#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002C000) -#define SPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002D000) -#define SAI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002F000) -#define SAI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000) -#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000) -#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000) -#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000) -#define USBC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00034000) -#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000) -#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000) -#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000) -#define FTM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000) -#define ADC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003B000) -#define TCON0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003D000) -#define WDOG1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000) -#define LPTMR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00040000) -#define RLE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000) -#define MLB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00043000) -#define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000) -#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000) -#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000) -#define USB_PHY0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050800) -#define USB_PHY1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050C00) -#define SCSC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000) -#define DCU0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00058000) -#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000) -#define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000) -#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000) -#define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000) -#define WDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000) -#define I2C1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000) -#define I2C2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00067000) -#define I2C3_BASE_ADDR (AIPS0_BASE_ADDR + 0x000E6000) -#define I2C4_BASE_ADDR (AIPS0_BASE_ADDR + 0x000E7000) -#define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000) -#define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000) -#define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000) -#define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000) -#define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000) -#define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000) -#define GPIO0_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF000) -#define GPIO1_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF040) -#define GPIO2_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF080) -#define GPIO3_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF0C0) -#define GPIO4_BASE_ADDR (AIPS0_BASE_ADDR + 0x000FF100) - -/* AIPS 1 */ -#define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000) -#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000) -#define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000) -#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000) -#define USBC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00034000) -#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000) -#define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000) -#define DCU1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00058000) -#define NFC_BASE_ADDR (AIPS1_BASE_ADDR + 0x00060000) - -#define QSPI0_AMBA_BASE 0x20000000 - -/* MUX mode and PAD ctrl are in one register */ -#define CONFIG_IOMUX_SHARE_CONF_REG - -#define FEC_QUIRK_ENET_MAC -#define I2C_QUIRK_REG - -/* MSCM interrupt rounter */ -#define MSCM_IRSPRC_CP0_EN 1 -#define MSCM_IRSPRC_NUM 112 - -/* DDRMC */ -#define DDRMC_PHY_DQ_TIMING 0x00002613 -#define DDRMC_PHY_DQS_TIMING 0x00002615 -#define DDRMC_PHY_CTRL 0x00210000 -#define DDRMC_PHY_MASTER_CTRL 0x0001012a -#define DDRMC_PHY_SLAVE_CTRL 0x00002000 -#define DDRMC_PHY_OFF 0x00000000 -#define DDRMC_PHY_PROC_PAD_ODT 0x00010101 - -#define DDRMC_PHY50_DDR3_MODE (1 << 12) -#define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8) - -#define DDRMC_CR00_DRAM_CLASS_DDR3 (0x6 << 8) -#define DDRMC_CR00_DRAM_CLASS_LPDDR2 (0x5 << 8) -#define DDRMC_CR00_START 1 -#define DDRMC_CR02_DRAM_TINIT(v) ((v) & 0xffffff) -#define DDRMC_CR10_TRST_PWRON(v) (v) -#define DDRMC_CR11_CKE_INACTIVE(v) (v) -#define DDRMC_CR12_WRLAT(v) (((v) & 0x1f) << 8) -#define DDRMC_CR12_CASLAT_LIN(v) ((v) & 0x3f) -#define DDRMC_CR13_TRC(v) (((v) & 0xff) << 24) -#define DDRMC_CR13_TRRD(v) (((v) & 0xff) << 16) -#define DDRMC_CR13_TCCD(v) (((v) & 0x1f) << 8) -#define DDRMC_CR13_TBST_INT_INTERVAL(v) ((v) & 0x7) -#define DDRMC_CR14_TFAW(v) (((v) & 0x3f) << 24) -#define DDRMC_CR14_TRP(v) (((v) & 0x1f) << 16) -#define DDRMC_CR14_TWTR(v) (((v) & 0xf) << 8) -#define DDRMC_CR14_TRAS_MIN(v) ((v) & 0xff) -#define DDRMC_CR16_TMRD(v) (((v) & 0x1f) << 24) -#define DDRMC_CR16_TRTP(v) (((v) & 0xf) << 16) -#define DDRMC_CR17_TRAS_MAX(v) (((v) & 0x1ffff) << 8) -#define DDRMC_CR17_TMOD(v) ((v) & 0xff) -#define DDRMC_CR18_TCKESR(v) (((v) & 0x1f) << 8) -#define DDRMC_CR18_TCKE(v) ((v) & 0x7) -#define DDRMC_CR20_AP_EN (1 << 24) -#define DDRMC_CR21_TRCD_INT(v) (((v) & 0xff) << 16) -#define DDRMC_CR21_TRAS_LOCKOUT(v) ((v) << 8) -#define DDRMC_CR21_CCMAP_EN 1 -#define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16) -#define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24) -#define DDRMC_CR23_TDLL(v) ((v) & 0xffff) -#define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f) -#define DDRMC_CR25_TREF_EN (1 << 16) -#define DDRMC_CR26_TREF(v) (((v) & 0xffff) << 16) -#define DDRMC_CR26_TRFC(v) ((v) & 0x3ff) -#define DDRMC_CR28_TREF_INT(v) ((v) & 0xffff) -#define DDRMC_CR29_TPDEX(v) ((v) & 0xffff) -#define DDRMC_CR30_TXPDLL(v) ((v) & 0xffff) -#define DDRMC_CR31_TXSNR(v) (((v) & 0xffff) << 16) -#define DDRMC_CR31_TXSR(v) ((v) & 0xffff) -#define DDRMC_CR33_EN_QK_SREF (1 << 16) -#define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16) -#define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8) -#define DDRMC_CR38_FREQ_CHG_EN(v) (((v) & 0x1) << 8) -#define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0xffff) << 16) -#define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8) -#define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3) -#define DDRMC_CR41_PHY_INI_STRT_INI_DIS 1 -#define DDRMC_CR48_MR1_DA_0(v) (((v) & 0xffff) << 16) -#define DDRMC_CR48_MR0_DA_0(v) ((v) & 0xffff) -#define DDRMC_CR66_ZQCL(v) (((v) & 0xfff) << 16) -#define DDRMC_CR66_ZQINIT(v) ((v) & 0xfff) -#define DDRMC_CR67_ZQCS(v) ((v) & 0xfff) -#define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8) -#define DDRMC_CR70_REF_PER_ZQ(v) (v) -#define DDRMC_CR72_ZQCS_ROTATE(v) (((v) & 0x1) << 24) -#define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24) -#define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16) -#define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8) -#define DDRMC_CR74_BANKSPLT_EN (1 << 24) -#define DDRMC_CR74_ADDR_CMP_EN (1 << 16) -#define DDRMC_CR74_CMD_AGE_CNT(v) (((v) & 0xff) << 8) -#define DDRMC_CR74_AGE_CNT(v) ((v) & 0xff) -#define DDRMC_CR75_RW_PG_EN (1 << 24) -#define DDRMC_CR75_RW_EN (1 << 16) -#define DDRMC_CR75_PRI_EN (1 << 8) -#define DDRMC_CR75_PLEN 1 -#define DDRMC_CR76_NQENT_ACTDIS(v) (((v) & 0x7) << 24) -#define DDRMC_CR76_D_RW_G_BKCN(v) (((v) & 0x3) << 16) -#define DDRMC_CR76_W2R_SPLT_EN (1 << 8) -#define DDRMC_CR76_CS_EN 1 -#define DDRMC_CR77_CS_MAP (1 << 24) -#define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8) -#define DDRMC_CR77_SWAP_EN 1 -#define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24) -#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf) -#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24) -#define DDRMC_CR80_MC_INIT_COMPLETE (1 << 8) -#define DDRMC_CR82_INT_MASK (1 << 28) -#define DDRMC_CR87_ODT_WR_MAPCS0(v) ((v) << 24) -#define DDRMC_CR87_ODT_RD_MAPCS0(v) ((v) << 16) -#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16) -#define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf) -#define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16) -#define DDRMC_CR93_SW_LVL_MODE_OFF (8) -#define DDRMC_CR93_SW_LVL_MODE(v) (((v) & 0x3) << DDRMC_CR93_SW_LVL_MODE_OFF) -#define DDRMC_CR93_SWLVL_LOAD BIT(16) -#define DDRMC_CR93_SWLVL_START BIT(24) -#define DDRMC_CR94_SWLVL_EXIT BIT(0) -#define DDRMC_CR94_SWLVL_OP_DONE BIT(8) -#define DDRMC_CR94_SWLVL_RESP_0_OFF (24) -#define DDRMC_CR95_SWLVL_RESP_1_OFF (0) -#define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) -#define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) -#define DDRMC_CR97_WRLVL_EN (1 << 24) -#define DDRMC_CR98_WRLVL_DL_0(v) ((v) & 0xffff) -#define DDRMC_CR99_WRLVL_DL_1(v) ((v) & 0xffff) -#define DDRMC_CR101_PHY_RDLVL_EDGE_OFF (24) -#define DDRMC_CR101_PHY_RDLVL_EDGE BIT(DDRMC_CR101_PHY_RDLVL_EDGE_OFF) -#define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16) -#define DDRMC_CR102_RDLVL_REG_EN (1 << 8) -#define DDRMC_CR105_RDLVL_DL_0_OFF (8) -#define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << DDRMC_CR105_RDLVL_DL_0_OFF) -#define DDRMC_CR106_RDLVL_GTDL_0(v) ((v) & 0xff) -#define DDRMC_CR110_RDLVL_DL_1_OFF (0) -#define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff) -#define DDRMC_CR110_RDLVL_GTDL_1(v) (((v) & 0xff) << 16) -#define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8) -#define DDRMC_CR115_RDLVL_GTDL_2(v) ((v) & 0xff) -#define DDRMC_CR117_AXI0_W_PRI(v) (((v) & 0x3) << 8) -#define DDRMC_CR117_AXI0_R_PRI(v) ((v) & 0x3) -#define DDRMC_CR118_AXI1_W_PRI(v) (((v) & 0x3) << 24) -#define DDRMC_CR118_AXI1_R_PRI(v) (((v) & 0x3) << 16) -#define DDRMC_CR120_AXI0_PRI1_RPRI(v) (((v) & 0xf) << 24) -#define DDRMC_CR120_AXI0_PRI0_RPRI(v) (((v) & 0xf) << 16) -#define DDRMC_CR121_AXI0_PRI3_RPRI(v) (((v) & 0xf) << 8) -#define DDRMC_CR121_AXI0_PRI2_RPRI(v) ((v) & 0xf) -#define DDRMC_CR122_AXI1_PRI1_RPRI(v) (((v) & 0xf) << 24) -#define DDRMC_CR122_AXI1_PRI0_RPRI(v) (((v) & 0xf) << 16) -#define DDRMC_CR122_AXI0_PRIRLX(v) ((v) & 0x3ff) -#define DDRMC_CR123_AXI1_PRI3_RPRI(v) (((v) & 0xf) << 8) -#define DDRMC_CR123_AXI1_PRI2_RPRI(v) ((v) & 0xf) -#define DDRMC_CR123_AXI1_P_ODR_EN (1 << 16) -#define DDRMC_CR124_AXI1_PRIRLX(v) ((v) & 0x3ff) -#define DDRMC_CR126_PHY_RDLAT(v) (((v) & 0x3f) << 8) -#define DDRMC_CR132_WRLAT_ADJ(v) (((v) & 0x1f) << 8) -#define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f) -#define DDRMC_CR137_PHYCTL_DL(v) (((v) & 0xf) << 16) -#define DDRMC_CR138_PHY_WRLV_MXDL(v) (((v) & 0xffff) << 16) -#define DDRMC_CR138_PHYDRAM_CK_EN(v) (((v) & 0x7) << 8) -#define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24) -#define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16) -#define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8) -#define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff) -#define DDRMC_CR140_PHY_WRLV_WW(v) ((v) & 0x3ff) -#define DDRMC_CR143_RDLV_GAT_MXDL(v) (((v) & 0xffff) << 16) -#define DDRMC_CR143_RDLV_MXDL(v) ((v) & 0xffff) -#define DDRMC_CR144_PHY_RDLVL_RES(v) (((v) & 0xff) << 24) -#define DDRMC_CR144_PHY_RDLV_LOAD(v) (((v) & 0xff) << 16) -#define DDRMC_CR144_PHY_RDLV_DLL(v) (((v) & 0xff) << 8) -#define DDRMC_CR144_PHY_RDLV_EN(v) ((v) & 0xff) -#define DDRMC_CR145_PHY_RDLV_RR(v) ((v) & 0x3ff) -#define DDRMC_CR146_PHY_RDLVL_RESP(v) (v) -#define DDRMC_CR147_RDLV_RESP_MASK(v) ((v) & 0xfffff) -#define DDRMC_CR148_RDLV_GATE_RESP_MASK(v) ((v) & 0xfffff) -#define DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(v) (((v) & 0xf) << 8) -#define DDRMC_CR151_RDLVL_DQ_ZERO_CNT(v) ((v) & 0xf) -#define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27) -#define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21) -#define DDRMC_CR154_DDR_SEL_PAD_CONTR(v) (((v) & 0x3) << 18) -#define DDRMC_CR154_PAD_ZQ_HW_FOR(v) (((v) & 0x1) << 14) -#define DDRMC_CR155_AXI0_AWCACHE (1 << 10) -#define DDRMC_CR155_PAD_ODT_BYTE1(v) (((v) & 0x7) << 3) -#define DDRMC_CR155_PAD_ODT_BYTE0(v) ((v) & 0x7) -#define DDRMC_CR158_TWR(v) ((v) & 0x3f) -#define DDRMC_CR161_ODT_EN(v) (((v) & 0x1) << 16) -#define DDRMC_CR161_TODTH_RD(v) (((v) & 0xf) << 8) -#define DDRMC_CR161_TODTH_WR(v) ((v) & 0xf) - -/* System Reset Controller (SRC) */ -#define SRC_SRSR_SW_RST (0x1 << 18) -#define SRC_SRSR_RESETB (0x1 << 7) -#define SRC_SRSR_JTAG_RST (0x1 << 5) -#define SRC_SRSR_WDOG_M4 (0x1 << 4) -#define SRC_SRSR_WDOG_A5 (0x1 << 3) -#define SRC_SRSR_POR_RST (0x1 << 0) -#define SRC_SBMR1_BOOTCFG1_SDMMC BIT(6) -#define SRC_SBMR1_BOOTCFG1_MMC BIT(4) -#define SRC_SBMR2_BMOD_MASK (0x3 << 24) -#define SRC_SBMR2_BMOD_SHIFT 24 -#define SRC_SBMR2_BMOD_FUSES 0x0 -#define SRC_SBMR2_BMOD_SERIAL 0x1 -#define SRC_SBMR2_BMOD_RCON 0x2 - -/* Slow Clock Source Controller Module (SCSC) */ -#define SCSC_SOSC_CTR_SOSC_EN 0x1 - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include <asm/types.h> - -/* System Reset Controller (SRC) */ -struct src { - u32 scr; - u32 sbmr1; - u32 srsr; - u32 secr; - u32 gpsr; - u32 sicr; - u32 simr; - u32 sbmr2; - u32 gpr0; - u32 gpr1; - u32 gpr2; - u32 gpr3; - u32 gpr4; - u32 hab0; - u32 hab1; - u32 hab2; - u32 hab3; - u32 hab4; - u32 hab5; - u32 misc0; - u32 misc1; - u32 misc2; - u32 misc3; -}; - -/* Periodic Interrupt Timer (PIT) */ -struct pit_reg { - u32 mcr; - u32 recv0[55]; - u32 ltmr64h; - u32 ltmr64l; - u32 recv1[6]; - u32 ldval0; - u32 cval0; - u32 tctrl0; - u32 tflg0; - u32 ldval1; - u32 cval1; - u32 tctrl1; - u32 tflg1; - u32 ldval2; - u32 cval2; - u32 tctrl2; - u32 tflg2; - u32 ldval3; - u32 cval3; - u32 tctrl3; - u32 tflg3; - u32 ldval4; - u32 cval4; - u32 tctrl4; - u32 tflg4; - u32 ldval5; - u32 cval5; - u32 tctrl5; - u32 tflg5; - u32 ldval6; - u32 cval6; - u32 tctrl6; - u32 tflg6; - u32 ldval7; - u32 cval7; - u32 tctrl7; - u32 tflg7; -}; - -/* Watchdog Timer (WDOG) */ -struct wdog_regs { - u16 wcr; - u16 wsr; - u16 wrsr; - u16 wicr; - u16 wmcr; -}; - -/* LPDDR2/DDR3 SDRAM Memory Controller (DDRMC) */ -struct ddrmr_regs { - u32 cr[162]; - u32 rsvd[94]; - u32 phy[53]; -}; - -/* On-Chip One Time Programmable Controller (OCOTP) */ -struct ocotp_regs { - u32 ctrl; - u32 ctrl_set; - u32 ctrl_clr; - u32 ctrl_tog; - u32 timing; - u32 rsvd0[3]; - u32 data; - u32 rsvd1[3]; - u32 read_ctrl; - u32 rsvd2[3]; - u32 read_fuse_data; - u32 rsvd3[7]; - u32 scs; - u32 scs_set; - u32 scs_clr; - u32 scs_tog; - u32 crc_addr; - u32 rsvd4[3]; - u32 crc_value; - u32 rsvd5[3]; - u32 version; - u32 rsvd6[0xdb]; - - struct fuse_bank { - u32 fuse_regs[0x20]; - } bank[16]; -}; - -struct fuse_bank0_regs { - u32 lock; - u32 rsvd0[3]; - u32 uid_low; - u32 rsvd1[3]; - u32 uid_high; - u32 rsvd2[0x17]; -}; - -struct fuse_bank4_regs { - u32 sjc_resp0; - u32 rsvd0[3]; - u32 sjc_resp1; - u32 rsvd1[3]; - u32 mac_addr0; - u32 rsvd2[3]; - u32 mac_addr1; - u32 rsvd3[3]; - u32 mac_addr2; - u32 rsvd4[3]; - u32 mac_addr3; - u32 rsvd5[3]; - u32 gp1; - u32 rsvd6[3]; - u32 gp2; - u32 rsvd7[3]; -}; - -/* MSCM Interrupt Router */ -struct mscm_ir { - u32 ircp0ir; - u32 ircp1ir; - u32 rsvd1[6]; - u32 ircpgir; - u32 rsvd2[23]; - u16 irsprc[112]; - u16 rsvd3[848]; -}; - -/* SCSC */ -struct scsc_reg { - u32 sirc_ctr; - u32 sosc_ctr; -}; - -/* MSCM */ -struct mscm { - u32 cpxtype; - u32 cpxnum; - u32 cpxmaster; - u32 cpxcount; - u32 cpxcfg0; - u32 cpxcfg1; - u32 cpxcfg2; - u32 cpxcfg3; -}; - -#endif /* __ASSEMBLER__*/ - -#endif /* __ASM_ARCH_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h deleted file mode 100644 index 8ba03e5..0000000 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ /dev/null @@ -1,255 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - */ - -#ifndef __IOMUX_VF610_H__ -#define __IOMUX_VF610_H__ - -#include <asm/mach-imx/iomux-v3.h> - -/* Pad control groupings */ -#define VF610_UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_25ohm | \ - PAD_CTL_OBE_IBE_ENABLE) -#define VF610_SDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_20ohm | \ - PAD_CTL_OBE_IBE_ENABLE) -#define VF610_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ - PAD_CTL_OBE_IBE_ENABLE) -#define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm -#define VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_25ohm | \ - PAD_CTL_INPUT_DIFFERENTIAL) -#define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_ODE | \ - PAD_CTL_OBE_IBE_ENABLE) -#define VF610_NFC_IO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \ - PAD_CTL_DSE_50ohm | PAD_CTL_PUS_47K_UP | \ - PAD_CTL_OBE_IBE_ENABLE) -#define VF610_NFC_CN_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \ - PAD_CTL_DSE_25ohm | PAD_CTL_OBE_ENABLE) -#define VF610_NFC_RB_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_IBE_ENABLE) - -#define VF610_QSPI_PAD_CTRL (PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \ - PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE) - -#define VF610_GPIO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | \ - PAD_CTL_IBE_ENABLE) - -#define VF610_DSPI_PAD_CTRL (PAD_CTL_OBE_ENABLE | PAD_CTL_DSE_20ohm | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH) -#define VF610_DSPI_SIN_PAD_CTRL (PAD_CTL_IBE_ENABLE | PAD_CTL_DSE_20ohm | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH) -#define VF610_DCU_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \ - PAD_CTL_DSE_37ohm | PAD_CTL_OBE_ENABLE) - -enum { - VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTA7__GPIO_134 = IOMUX_PAD(0x0218, 0x0218, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTA17__GPIO_7 = IOMUX_PAD(0x001c, 0x001c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTA20__GPIO_10 = IOMUX_PAD(0x0028, 0x0028, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTA21__GPIO_11 = IOMUX_PAD(0x002c, 0x002c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTA30__GPIO_20 = IOMUX_PAD(0x0050, 0x0050, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTA31__GPIO_21 = IOMUX_PAD(0x0054, 0x0054, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB0__GPIO_22 = IOMUX_PAD(0x0058, 0x0058, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB1__GPIO_23 = IOMUX_PAD(0x005C, 0x005C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL), - VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL), - VF610_PAD_PTB6__GPIO_28 = IOMUX_PAD(0x0070, 0x0070, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB7__GPIO_29 = IOMUX_PAD(0x0074, 0x0074, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB8__GPIO_30 = IOMUX_PAD(0x0078, 0x0078, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB9__GPIO_31 = IOMUX_PAD(0x007C, 0x007C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB10__UART0_TX = IOMUX_PAD(0x0080, 0x0080, 1, __NA_, 0, VF610_UART_PAD_CTRL), - VF610_PAD_PTB11__UART0_RX = IOMUX_PAD(0x0084, 0x0084, 1, __NA_, 0, VF610_UART_PAD_CTRL), - VF610_PAD_PTB12__GPIO_34 = IOMUX_PAD(0x0088, 0x0088, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB13__GPIO_35 = IOMUX_PAD(0x008c, 0x008c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB16__GPIO_38 = IOMUX_PAD(0x0098, 0x0098, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB17__GPIO_39 = IOMUX_PAD(0x009c, 0x009c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB18__GPIO_40 = IOMUX_PAD(0x00a0, 0x00a0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB21__GPIO_43 = IOMUX_PAD(0x00ac, 0x00ac, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB22__GPIO_44 = IOMUX_PAD(0x00b0, 0x00b0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB23__GPIO_93 = IOMUX_PAD(0x0174, 0x0174, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB26__GPIO_96 = IOMUX_PAD(0x0180, 0x0180, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTB28__GPIO_98 = IOMUX_PAD(0x0188, 0x0188, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC1__GPIO_46 = IOMUX_PAD(0x00b8, 0x00b8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC0__GPIO_45 = IOMUX_PAD(0x00b4, 0x00b4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC2__GPIO_47 = IOMUX_PAD(0x00bc, 0x00bc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC3__RMII0_RD1 = IOMUX_PAD(0x00c0, 0x00c0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC3__GPIO_48 = IOMUX_PAD(0x00c0, 0x00c0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC4__RMII0_RD0 = IOMUX_PAD(0x00c4, 0x00c4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC4__GPIO_49 = IOMUX_PAD(0x00c4, 0x00c4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC5__RMII0_RXER = IOMUX_PAD(0x00c8, 0x00c8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC5__GPIO_50 = IOMUX_PAD(0x00c8, 0x00c8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC6__GPIO_51 = IOMUX_PAD(0x00cc, 0x00cc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC7__GPIO_52 = IOMUX_PAD(0x00D0, 0x00D0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC8__GPIO_53 = IOMUX_PAD(0x00D4, 0x00D4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC10__RMII1_MDIO = IOMUX_PAD(0x00dc, 0x00dc, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC9__RMII1_MDC = IOMUX_PAD(0x00d8, 0x00d8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC11__RMII1_CRS_DV = IOMUX_PAD(0x00e0, 0x00e0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC12__RMII1_RD1 = IOMUX_PAD(0x00e4, 0x00e4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC13__RMII1_RD0 = IOMUX_PAD(0x00e8, 0x00e8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC14__RMII1_RXER = IOMUX_PAD(0x00ec, 0x00ec, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC15__RMII1_TD1 = IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC16__RMII1_TD0 = IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTC17__RMII1_TXEN = IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL), - VF610_PAD_PTD5__DSPI1_CS0 = IOMUX_PAD(0x0150, 0x0150, 3, 0x300, 1, VF610_DSPI_PAD_CTRL), - VF610_PAD_PTD6__DSPI1_SIN = IOMUX_PAD(0x0154, 0x0154, 3, 0x2fc, 1, VF610_DSPI_SIN_PAD_CTRL), - VF610_PAD_PTD7__DSPI1_SOUT = IOMUX_PAD(0x0158, 0x0158, 3, __NA_, 0, VF610_DSPI_PAD_CTRL), - VF610_PAD_PTD8__DSPI1_SCK = IOMUX_PAD(0x015c, 0x015c, 3, 0x2f8, 1, VF610_DSPI_PAD_CTRL), - VF610_PAD_PTC29__GPIO_102 = IOMUX_PAD(0x0198, 0x0198, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTC30__GPIO_103 = IOMUX_PAD(0x019c, 0x019c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTA27__ESDHC1_DAT1 = IOMUX_PAD(0x0044, 0x0044, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTA28__ESDHC1_DAT2 = IOMUX_PAD(0x0048, 0x0048, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), - VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL), - VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL), - VF610_PAD_PTA22__I2C2_SCL = IOMUX_PAD(0x0030, 0x0030, 6, 0x034c, 0, VF610_I2C_PAD_CTRL), - VF610_PAD_PTA23__I2C2_SDA = IOMUX_PAD(0x0034, 0x0034, 6, 0x0350, 0, VF610_I2C_PAD_CTRL), - VF610_PAD_PTD31__NF_IO15 = IOMUX_PAD(0x00fc, 0x00fc, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD31__GPIO_63 = IOMUX_PAD(0x00fc, 0x00fc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD30__NF_IO14 = IOMUX_PAD(0x0100, 0x0100, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD30__GPIO_64 = IOMUX_PAD(0x0100, 0x0100, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD29__NF_IO13 = IOMUX_PAD(0x0104, 0x0104, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD29__GPIO_65 = IOMUX_PAD(0x0104, 0x0104, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD28__NF_IO12 = IOMUX_PAD(0x0108, 0x0108, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD28__GPIO_66 = IOMUX_PAD(0x0108, 0x0108, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD27__NF_IO11 = IOMUX_PAD(0x010c, 0x010c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD27__GPIO_67 = IOMUX_PAD(0x010c, 0x010c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD26__NF_IO10 = IOMUX_PAD(0x0110, 0x0110, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD26__GPIO_68 = IOMUX_PAD(0x0110, 0x0110, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD25__NF_IO9 = IOMUX_PAD(0x0114, 0x0114, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD25__GPIO_69 = IOMUX_PAD(0x0114, 0x0114, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD24__NF_IO8 = IOMUX_PAD(0x0118, 0x0118, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD24__GPIO_70 = IOMUX_PAD(0x0118, 0x0118, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD23__NF_IO7 = IOMUX_PAD(0x011c, 0x011c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD0__QSPI0_A_QSCK = IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD0__UART2_TX = IOMUX_PAD(0x013c, 0x013c, 2, 0x38c, 2, VF610_UART_PAD_CTRL), - VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD1__UART2_RX = IOMUX_PAD(0x0140, 0x0140, 2, 0x388, 2, VF610_UART_PAD_CTRL), - VF610_PAD_PTD2__QSPI0_A_DATA3 = IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD2__GPIO_81 = IOMUX_PAD(0x0144, 0x0144, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD3__QSPI0_A_DATA2 = IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD3__GPIO_82 = IOMUX_PAD(0x0148, 0x0148, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD4__GPIO_83 = IOMUX_PAD(0x014C, 0x014C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD4__QSPI0_A_DATA1 = IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD5__QSPI0_A_DATA0 = IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD7__QSPI0_B_QSCK = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD8__QSPI0_B_CS0 = IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD9__QSPI0_B_DATA3 = IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD9__GPIO_88 = IOMUX_PAD(0x0160, 0x0160, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD10__QSPI0_B_DATA2 = IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD10__GPIO_89 = IOMUX_PAD(0x0164, 0x0164, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD11__QSPI0_B_DATA1 = IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD11__GPIO_90 = IOMUX_PAD(0x0168, 0x0168, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD12__QSPI0_B_DATA0 = IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), - VF610_PAD_PTD12__GPIO_91 = IOMUX_PAD(0x016c, 0x016c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD13__GPIO_92 = IOMUX_PAD(0x0170, 0x0170, 0, __NA_, 0, VF610_GPIO_PAD_CTRL), - VF610_PAD_PTD22__NF_IO6 = IOMUX_PAD(0x0120, 0x0120, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD21__NF_IO5 = IOMUX_PAD(0x0124, 0x0124, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD20__NF_IO4 = IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD19__NF_IO3 = IOMUX_PAD(0x012c, 0x012c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD18__NF_IO2 = IOMUX_PAD(0x0130, 0x0130, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD17__NF_IO1 = IOMUX_PAD(0x0134, 0x0134, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTD16__NF_IO0 = IOMUX_PAD(0x0138, 0x0138, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL), - VF610_PAD_PTB24__NF_WE_B = IOMUX_PAD(0x0178, 0x0178, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - VF610_PAD_PTB25__NF_CE0_B = IOMUX_PAD(0x017c, 0x017c, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - - VF610_PAD_PTB27__NF_RE_B = IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - - VF610_PAD_PTC26__NF_RB_B = IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL), - - VF610_PAD_PTC27__NF_ALE = IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - - VF610_PAD_PTC28__NF_CLE = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL), - - VF610_PAD_PTE0__DCU0_HSYNC = IOMUX_PAD(0x01a4, 0x01a4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE1__DCU0_VSYNC = IOMUX_PAD(0x01a8, 0x01a8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE2__DCU0_PCLK = IOMUX_PAD(0x01ac, 0x01ac, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE4__DCU0_DE = IOMUX_PAD(0x01b4, 0x01b4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE5__DCU0_R0 = IOMUX_PAD(0x01b8, 0x01b8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE6__DCU0_R1 = IOMUX_PAD(0x01bc, 0x01bc, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE7__DCU0_R2 = IOMUX_PAD(0x01c0, 0x01c0, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE8__DCU0_R3 = IOMUX_PAD(0x01c4, 0x01c4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE9__DCU0_R4 = IOMUX_PAD(0x01c8, 0x01c8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE10__DCU0_R5 = IOMUX_PAD(0x01cc, 0x01cc, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE11__DCU0_R6 = IOMUX_PAD(0x01d0, 0x01d0, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE12__DCU0_R7 = IOMUX_PAD(0x01d4, 0x01d4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE13__DCU0_G0 = IOMUX_PAD(0x01d8, 0x01d8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE14__DCU0_G1 = IOMUX_PAD(0x01dc, 0x01dc, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE15__DCU0_G2 = IOMUX_PAD(0x01e0, 0x01e0, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE16__DCU0_G3 = IOMUX_PAD(0x01e4, 0x01e4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE17__DCU0_G4 = IOMUX_PAD(0x01e8, 0x01e8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE18__DCU0_G5 = IOMUX_PAD(0x01ec, 0x01ec, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE19__DCU0_G6 = IOMUX_PAD(0x01f0, 0x01f0, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE20__DCU0_G7 = IOMUX_PAD(0x01f4, 0x01f4, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE21__DCU0_B0 = IOMUX_PAD(0x01f8, 0x01f8, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE22__DCU0_B1 = IOMUX_PAD(0x01fc, 0x01fc, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE23__DCU0_B2 = IOMUX_PAD(0x0200, 0x0200, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE24__DCU0_B3 = IOMUX_PAD(0x0204, 0x0204, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE25__DCU0_B4 = IOMUX_PAD(0x0208, 0x0208, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE26__DCU0_B5 = IOMUX_PAD(0x020c, 0x020c, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE27__DCU0_B6 = IOMUX_PAD(0x0210, 0x0210, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - VF610_PAD_PTE28__DCU0_B7 = IOMUX_PAD(0x0214, 0x0214, 1, __NA_, 0, VF610_DCU_PAD_CTRL), - - VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, 0x022c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, 0x0230, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, 0x0234, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, 0x0238, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, 0x023c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, 0x0240, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, 0x0244, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, 0x0248, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, 0x024c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, 0x025c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, 0x026c, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1), - VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 = IOMUX_PAD(0x02dc, 0x02dc, 0, __NA_, 0, VF610_DDR_PAD_CTRL), - VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2 = IOMUX_PAD(0x02e0, 0x02e0, 0, __NA_, 0, VF610_DDR_PAD_CTRL), -}; - -#endif /* __IOMUX_VF610_H__ */ |