7 files changed, 0 insertions, 353 deletions
diff --git a/include/dt-bindings/memory/mpc83xx-sdram.h b/include/dt-bindings/memory/mpc83xx-sdram.h
deleted file mode 100644
index 7d4ce01..0000000
--- a/include/dt-bindings/memory/mpc83xx-sdram.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2018
- * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
- */
-
-#ifndef DT_BINDINGS_MPC83XX_SDRAM_H
-#define DT_BINDINGS_MPC83XX_SDRAM_H
-
-/* DDR Control Driver register */
-
-#define DSO_DISABLE	0
-#define DSO_ENABLE	1
-
-#define DSO_P_IMPEDANCE_HIGHEST_Z	0x0
-#define DSO_P_IMPEDANCE_MUCH_HIGHER_Z	0x8
-#define DSO_P_IMPEDANCE_HIGHER_Z	0xC
-#define DSO_P_IMPEDANCE_NOMINAL		0xE
-#define DSO_P_IMPEDANCE_LOWER_Z		0xF
-
-#define DSO_N_IMPEDANCE_HIGHEST_Z	0x0
-#define DSO_N_IMPEDANCE_MUCH_HIGHER_Z	0x8
-#define DSO_N_IMPEDANCE_HIGHER_Z	0xC
-#define DSO_N_IMPEDANCE_NOMINAL		0xE
-#define DSO_N_IMPEDANCE_LOWER_Z		0xF
-
-#define ODT_TERMINATION_75_OHM		0
-#define ODT_TERMINATION_150_OHM		1
-
-#define DDR_TYPE_DDR2_1_8_VOLT		0
-#define DDR_TYPE_DDR1_2_5_VOLT		1
-
-#define MVREF_SEL_EXTERNAL		0
-#define MVREF_SEL_INTERNAL_GVDD		1
-
-#define M_ODR_ENABLE			0
-#define M_ODR_DISABLE			1
-
-/* CS config register */
-
-#define AUTO_PRECHARGE_ENABLE	0x00800000
-#define AUTO_PRECHARGE_DISABLE	0x00000000
-
-#define ODT_RD_NEVER		0x00000000
-#define ODT_RD_ONLY_CURRENT	0x00100000
-#define ODT_RD_ONLY_OTHER_CS	0x00200000
-#define ODT_RD_ONLY_OTHER_DIMM	0x00300000
-#define ODT_RD_ALL		0x00400000
-
-#define ODT_WR_NEVER		0x00000000
-#define ODT_WR_ONLY_CURRENT	0x00010000
-#define ODT_WR_ONLY_OTHER_CS	0x00020000
-#define ODT_WR_ONLY_OTHER_DIMM	0x00030000
-#define ODT_WR_ALL		0x00040000
-
-/* DDR SDRAM Clock Control register */
-
-#define CLOCK_ADJUST_025	0x01000000
-#define CLOCK_ADJUST_05		0x02000000
-#define CLOCK_ADJUST_075	0x03000000
-#define CLOCK_ADJUST_1		0x04000000
-
-#define CASLAT_20		0x3	/* CAS latency = 2.0 */
-#define CASLAT_25		0x4	/* CAS latency = 2.5 */
-#define CASLAT_30		0x5	/* CAS latency = 3.0 */
-#define CASLAT_35		0x6	/* CAS latency = 3.5 */
-#define CASLAT_40		0x7	/* CAS latency = 4.0 */
-#define CASLAT_45		0x8	/* CAS latency = 4.5 */
-#define CASLAT_50		0x9	/* CAS latency = 5.0 */
-#define CASLAT_55		0xa	/* CAS latency = 5.5 */
-#define CASLAT_60		0xb	/* CAS latency = 6.0 */
-#define CASLAT_65		0xc	/* CAS latency = 6.5 */
-#define CASLAT_70		0xd	/* CAS latency = 7.0 */
-#define CASLAT_75		0xe	/* CAS latency = 7.5 */
-#define CASLAT_80		0xf	/* CAS latency = 8.0 */
-
-/* DDR SDRAM Timing Configuration 2 register */
-
-#define READ_LAT_PLUS_1		0x0
-#define READ_LAT		0x2
-#define READ_LAT_PLUS_1_4	0x3
-#define READ_LAT_PLUS_1_2	0x4
-#define READ_LAT_PLUS_3_4	0x5
-#define READ_LAT_PLUS_5_4	0x7
-#define READ_LAT_PLUS_3_2	0x8
-#define READ_LAT_PLUS_7_4	0x9
-#define READ_LAT_PLUS_2		0xA
-#define READ_LAT_PLUS_9_4	0xB
-#define READ_LAT_PLUS_5_2	0xC
-#define READ_LAT_PLUS_11_4	0xD
-#define READ_LAT_PLUS_3		0xE
-#define READ_LAT_PLUS_13_4	0xF
-#define READ_LAT_PLUS_7_2	0x10
-#define READ_LAT_PLUS_15_4	0x11
-#define READ_LAT_PLUS_4		0x12
-#define READ_LAT_PLUS_17_4	0x13
-#define READ_LAT_PLUS_9_2	0x14
-#define READ_LAT_PLUS_19_4	0x15
-
-#define CLOCK_DELAY_0		0x0
-#define CLOCK_DELAY_1_4		0x1
-#define CLOCK_DELAY_1_2		0x2
-#define CLOCK_DELAY_3_4		0x3
-#define CLOCK_DELAY_1		0x4
-#define CLOCK_DELAY_5_4		0x5
-#define CLOCK_DELAY_3_2		0x6
-
-/* DDR SDRAM Control Configuration */
-
-#define SREN_DISABLE	0x0
-#define SREN_ENABLE	0x1
-
-#define ECC_DISABLE	0x0
-#define ECC_ENABLE	0x1
-
-#define RD_DISABLE	0x0
-#define RD_ENABLE	0x1
-
-#define TYPE_DDR1	0x2
-#define TYPE_DDR2	0x3
-
-#define DYN_PWR_DISABLE		0x0
-#define DYN_PWR_ENABLE		0x1
-
-#define DATA_BUS_WIDTH_16	0x1
-#define DATA_BUS_WIDTH_32	0x2
-
-#define NCAP_DISABLE	0x0
-#define NCAP_ENABLE	0x1
-
-#define TIMING_1T	0x0
-#define TIMING_2T	0x1
-
-#define INTERLEAVE_NONE		0x0
-#define INTERLEAVE_1_AND_2	0x1
-
-#define PRECHARGE_MA_10		0x0
-#define PRECHARGE_MA_8		0x1
-
-#define STRENGTH_FULL		0x0
-#define STRENGTH_HALF		0x1
-
-#define INITIALIZATION_DONT_BYPASS	0x0
-#define INITIALIZATION_BYPASS		0x1
-
-/* DDR SDRAM Control Configuration 2 register */
-
-#define MODE_NORMAL	0x0
-#define MODE_REFRESH	0x1
-
-#define DLL_RESET_ENABLE	0x0
-#define DLL_RESET_DISABLE	0x1
-
-#define DQS_TRUE	0x0
-
-#define ODT_ASSERT_NEVER	0x0
-#define ODT_ASSERT_WRITES	0x1
-#define ODT_ASSERT_READS	0x2
-#define ODT_ASSERT_ALWAYS	0x3
-
-#endif
diff --git a/include/dt-bindings/memory/rk3368-dmc.h b/include/dt-bindings/memory/rk3368-dmc.h
deleted file mode 100644
index b06ffde..0000000
--- a/include/dt-bindings/memory/rk3368-dmc.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef DT_BINDINGS_RK3368_DMC_H
-#define DT_BINDINGS_RK3368_DMC_H
-
-#define DMC_MSCH_CBDR       0x0
-#define DMC_MSCH_CBRD       0x1
-#define DMC_MSCH_CRBD       0x2
-
-#define DDR3_800D 0
-#define DDR3_800E 1
-#define DDR3_1066E 2
-#define DDR3_1066F 3
-#define DDR3_1066G 4
-#define DDR3_1333F 5
-#define DDR3_1333G 6
-#define DDR3_1333H 7
-#define DDR3_1333J 8
-#define DDR3_1600G 9
-#define DDR3_1600H 10
-#define DDR3_1600J 11
-#define DDR3_1600K 12
-#define DDR3_1866J 13
-#define DDR3_1866K 14
-#define DDR3_1866L 15
-#define DDR3_1866M 16
-#define DDR3_2133K 17
-#define DDR3_2133L 18
-#define DDR3_2133M 19
-#define DDR3_2133N 20
-
-#endif
diff --git a/include/dt-bindings/memory/stm32-sdram.h b/include/dt-bindings/memory/stm32-sdram.h
deleted file mode 100644
index ab91d2b..0000000
--- a/include/dt-bindings/memory/stm32-sdram.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#ifndef DT_BINDINGS_STM32_SDRAM_H
-#define DT_BINDINGS_STM32_SDRAM_H
-
-#define NO_COL_8	0x0
-#define NO_COL_9	0x1
-#define NO_COL_10	0x2
-#define NO_COL_11	0x3
-
-#define NO_ROW_11	0x0
-#define NO_ROW_12	0x1
-#define NO_ROW_13	0x2
-
-#define MWIDTH_8	0x0
-#define MWIDTH_16	0x1
-#define MWIDTH_32	0x2
-#define BANKS_2		0x0
-#define BANKS_4		0x1
-#define CAS_1		0x1
-#define CAS_2		0x2
-#define CAS_3		0x3
-#define SDCLK_DIS	0x0
-#define SDCLK_2		0x2
-#define SDCLK_3		0x3
-#define RD_BURST_EN	0x1
-#define RD_BURST_DIS	0x0
-#define RD_PIPE_DL_0	0x0
-#define RD_PIPE_DL_1	0x1
-#define RD_PIPE_DL_2	0x2
-
-/* Timing = value +1 cycles */
-#define TMRD_1		(1 - 1)
-#define TMRD_2		(2 - 1)
-#define TMRD_3		(3 - 1)
-#define TXSR_1		(1 - 1)
-#define TXSR_6		(6 - 1)
-#define TXSR_7		(7 - 1)
-#define TRAS_1		(1 - 1)
-#define TRAS_4		(4 - 1)
-#define TRC_6		(6 - 1)
-#define TWR_1		(1 - 1)
-#define TWR_2		(2 - 1)
-#define TRP_2		(2 - 1)
-#define TRCD_1		(1 - 1)
-#define TRCD_2		(2 - 1)
-
-#endif
diff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h
deleted file mode 100644
index 8f48985..0000000
--- a/include/dt-bindings/memory/tegra114-mc.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H
-#define DT_BINDINGS_MEMORY_TEGRA114_MC_H
-
-#define TEGRA_SWGROUP_PTC	0
-#define TEGRA_SWGROUP_DC	1
-#define TEGRA_SWGROUP_DCB	2
-#define TEGRA_SWGROUP_EPP	3
-#define TEGRA_SWGROUP_G2	4
-#define TEGRA_SWGROUP_AVPC	5
-#define TEGRA_SWGROUP_NV	6
-#define TEGRA_SWGROUP_HDA	7
-#define TEGRA_SWGROUP_HC	8
-#define TEGRA_SWGROUP_MSENC	9
-#define TEGRA_SWGROUP_PPCS	10
-#define TEGRA_SWGROUP_VDE	11
-#define TEGRA_SWGROUP_MPCORELP	12
-#define TEGRA_SWGROUP_MPCORE	13
-#define TEGRA_SWGROUP_VI	14
-#define TEGRA_SWGROUP_ISP	15
-#define TEGRA_SWGROUP_XUSB_HOST	16
-#define TEGRA_SWGROUP_XUSB_DEV	17
-#define TEGRA_SWGROUP_EMUCIF	18
-#define TEGRA_SWGROUP_TSEC	19
-
-#endif
diff --git a/include/dt-bindings/memory/tegra124-mc.h b/include/dt-bindings/memory/tegra124-mc.h
deleted file mode 100644
index 7d8ee79..0000000
--- a/include/dt-bindings/memory/tegra124-mc.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H
-#define DT_BINDINGS_MEMORY_TEGRA124_MC_H
-
-#define TEGRA_SWGROUP_PTC	0
-#define TEGRA_SWGROUP_DC	1
-#define TEGRA_SWGROUP_DCB	2
-#define TEGRA_SWGROUP_AFI	3
-#define TEGRA_SWGROUP_AVPC	4
-#define TEGRA_SWGROUP_HDA	5
-#define TEGRA_SWGROUP_HC	6
-#define TEGRA_SWGROUP_MSENC	7
-#define TEGRA_SWGROUP_PPCS	8
-#define TEGRA_SWGROUP_SATA	9
-#define TEGRA_SWGROUP_VDE	10
-#define TEGRA_SWGROUP_MPCORELP	11
-#define TEGRA_SWGROUP_MPCORE	12
-#define TEGRA_SWGROUP_ISP2	13
-#define TEGRA_SWGROUP_XUSB_HOST	14
-#define TEGRA_SWGROUP_XUSB_DEV	15
-#define TEGRA_SWGROUP_ISP2B	16
-#define TEGRA_SWGROUP_TSEC	17
-#define TEGRA_SWGROUP_A9AVP	18
-#define TEGRA_SWGROUP_GPU	19
-#define TEGRA_SWGROUP_SDMMC1A	20
-#define TEGRA_SWGROUP_SDMMC2A	21
-#define TEGRA_SWGROUP_SDMMC3A	22
-#define TEGRA_SWGROUP_SDMMC4A	23
-#define TEGRA_SWGROUP_VIC	24
-#define TEGRA_SWGROUP_VI	25
-
-#endif
diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h
deleted file mode 100644
index d1731bc..0000000
--- a/include/dt-bindings/memory/tegra210-mc.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H
-#define DT_BINDINGS_MEMORY_TEGRA210_MC_H
-
-#define TEGRA_SWGROUP_PTC	0
-#define TEGRA_SWGROUP_DC	1
-#define TEGRA_SWGROUP_DCB	2
-#define TEGRA_SWGROUP_AFI	3
-#define TEGRA_SWGROUP_AVPC	4
-#define TEGRA_SWGROUP_HDA	5
-#define TEGRA_SWGROUP_HC	6
-#define TEGRA_SWGROUP_NVENC	7
-#define TEGRA_SWGROUP_PPCS	8
-#define TEGRA_SWGROUP_SATA	9
-#define TEGRA_SWGROUP_MPCORE	10
-#define TEGRA_SWGROUP_ISP2	11
-#define TEGRA_SWGROUP_XUSB_HOST	12
-#define TEGRA_SWGROUP_XUSB_DEV	13
-#define TEGRA_SWGROUP_ISP2B	14
-#define TEGRA_SWGROUP_TSEC	15
-#define TEGRA_SWGROUP_A9AVP	16
-#define TEGRA_SWGROUP_GPU	17
-#define TEGRA_SWGROUP_SDMMC1A	18
-#define TEGRA_SWGROUP_SDMMC2A	19
-#define TEGRA_SWGROUP_SDMMC3A	20
-#define TEGRA_SWGROUP_SDMMC4A	21
-#define TEGRA_SWGROUP_VIC	22
-#define TEGRA_SWGROUP_VI	23
-#define TEGRA_SWGROUP_NVDEC	24
-#define TEGRA_SWGROUP_APE	25
-#define TEGRA_SWGROUP_NVJPG	26
-#define TEGRA_SWGROUP_SE	27
-#define TEGRA_SWGROUP_AXIAP	28
-#define TEGRA_SWGROUP_ETR	29
-#define TEGRA_SWGROUP_TSECB	30
-
-#endif
diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h
deleted file mode 100644
index 502beb0..0000000
--- a/include/dt-bindings/memory/tegra30-mc.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H
-#define DT_BINDINGS_MEMORY_TEGRA30_MC_H
-
-#define TEGRA_SWGROUP_PTC	0
-#define TEGRA_SWGROUP_DC	1
-#define TEGRA_SWGROUP_DCB	2
-#define TEGRA_SWGROUP_EPP	3
-#define TEGRA_SWGROUP_G2	4
-#define TEGRA_SWGROUP_MPE	5
-#define TEGRA_SWGROUP_VI	6
-#define TEGRA_SWGROUP_AFI	7
-#define TEGRA_SWGROUP_AVPC	8
-#define TEGRA_SWGROUP_NV	9
-#define TEGRA_SWGROUP_NV2	10
-#define TEGRA_SWGROUP_HDA	11
-#define TEGRA_SWGROUP_HC	12
-#define TEGRA_SWGROUP_PPCS	13
-#define TEGRA_SWGROUP_SATA	14
-#define TEGRA_SWGROUP_VDE	15
-#define TEGRA_SWGROUP_MPCORELP	16
-#define TEGRA_SWGROUP_MPCORE	17
-#define TEGRA_SWGROUP_ISP	18
-
-#endif