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authorraywu <raywu0301@gmail.com>2018-06-15 00:00:50 +0800
committerraywu <raywu0301@gmail.com>2018-06-15 00:00:50 +0800
commitb7c51c9cf4864df6aabb99a1ae843becd577237c (patch)
treeeebe9b0d0ca03062955223097e57da84dd618b9a /Board/EM/Thunderbolt/TbtDxe
downloadzprj-master.tar.xz
init. 1AQQW051HEADmaster
Diffstat (limited to 'Board/EM/Thunderbolt/TbtDxe')
-rw-r--r--Board/EM/Thunderbolt/TbtDxe/TbtDxe.c652
-rw-r--r--Board/EM/Thunderbolt/TbtDxe/TbtDxe.cif14
-rw-r--r--Board/EM/Thunderbolt/TbtDxe/TbtDxe.dxs54
-rw-r--r--Board/EM/Thunderbolt/TbtDxe/TbtDxe.mak104
-rw-r--r--Board/EM/Thunderbolt/TbtDxe/TbtDxe.sdl586
-rw-r--r--Board/EM/Thunderbolt/TbtDxe/TbtDxeLib.c209
-rw-r--r--Board/EM/Thunderbolt/TbtDxe/TbtDxeLib.h74
-rw-r--r--Board/EM/Thunderbolt/TbtDxe/TbtGpe.asl797
8 files changed, 2490 insertions, 0 deletions
diff --git a/Board/EM/Thunderbolt/TbtDxe/TbtDxe.c b/Board/EM/Thunderbolt/TbtDxe/TbtDxe.c
new file mode 100644
index 0000000..a1ec300
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtDxe/TbtDxe.c
@@ -0,0 +1,652 @@
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
+
+//*************************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtDxe.c 10 5/19/14 7:32a Barretlin $
+//
+// $Revision: 10 $
+//
+// $Date: 5/19/14 7:32a $
+//*************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtDxe.c $
+//
+// 10 5/19/14 7:32a Barretlin
+// [TAG] EIP165410
+// [Category] New Feature
+// [Description] Support Thunderbolt AIC at NB PCIE slot
+// [Files] TbtPei.c TbtDxe.c TbtGpe.asl TbtSmm.c TbtOemBoard.c
+// TbtOemLib.c TbtOemLib.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// TbtSetupReset.c
+//
+// 9 5/19/14 7:11a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Using setup item choose return value of _RMV method in
+// ASL code
+// [Files] TbtDxe.c TbtGpe.asl TbtOemBoard.c TbtOemBoard.h TbtSetup.sd
+// TbtSetup.sdl TbtSetup.uni
+//
+// 8 2/27/14 8:38a Barretlin
+// [TAG] EIP N/A
+// [Category] Bug Fix
+// [Severity] Minor
+// [Symptom] when thunderbolt is disable in run time, PCIE device whcih
+// using the same PCIE slot might work abnormal
+// [RootCause] protect thunderbolt device function still work
+// [Solution] According thunderbolt policy to skip protect function
+// [Files] TbtDxe.c TbtDxeLib.c
+//
+// 7 1/05/14 1:43p Barretlin
+// [TAG] EIP N/A
+// [Category] New Feature
+// [Description] Support Thunderbolt feature Enable/Disable in run time
+// Support dynamic Thunderbolt AIC location in run time
+// [Files] TbtDxe.c TbtGpe.asl
+//
+// 6 6/21/13 7:40a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Fix build error with non Intel RC project
+// [Files] TbtDxe.sdl TbtDxe.c TbtGpe.asl TbtDxeLib.h
+//
+// 5 6/18/13 1:41p Barretlin
+// [TAG] EIP126581
+// [Category] Spec Update
+// [Severity] Minor
+// [Description] Follow Thunderbolt BIOS Spec rev1.0 to disable ASL code
+// to call Thunderbolt SwSMI when Native PCIE is enable
+// [Files] TbtDxe.c
+//
+// 4 4/10/13 2:31p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Change reported MMIO address way in ASL code
+// [Files] TbtDxe.c TbtGpe.asl
+//
+// 3 4/10/13 1:26p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Fix Thunderbolt ready to boot event does not be excuted
+// on ULT platform
+// [Files] TbtDxe.c
+//
+// 2 1/18/13 2:26a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Improve _RMV ASL code for SharkBay RC
+// [Files] TbtDxe.sdl TbtDxe.c TbtGpe.asl
+//
+// 1 1/10/13 4:56a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+//
+// 11 12/12/12 3:02a Barretlin
+// [TAG] EIP108272
+// [Category] Spec Update
+// [Severity] Important
+// [Description] Update to Spec 1.4 to support Redwood Ridge chip
+// [Files] TbtPei.c TbtSmm.c TbtDxe.c TbtDxe.sdl TbtGpe.asl
+// TbtOemBoard.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+//
+// 10 10/28/12 10:50p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Change GPIO routing for SharkBay ULT platform
+// [Files] TbtDxe.c TbtGpe.asl TbtDxeLib.c TbtDxeLib.h TbtSmm.c
+//
+// 9 10/03/12 9:15p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Change Programming security level timing for saving
+// boot time
+// [Files] TbtPei.c TbtDxe.c TbtOemBoard.c TbtOemBoard.h
+// TbtOemBoard.sdl TbtOemLib.c TbtOemLib.h
+//
+// 8 7/31/12 2:52a Barretlin
+// [TAG] EIP96350
+// [Category] Spec Update
+// [Severity] Important
+// [Description] Change ACPI method from level trigger to edge
+// trigger(_L1x to _E1x)
+// [Files] TbtDxe.c
+//
+// 7 7/31/12 2:46a Barretlin
+// [TAG] EIP91119
+// [Category] Improvement
+// [Description] Resolution for enable/disable Thunderbolt device option
+// rom at POST time
+// [Files] TbtDxe.c
+//
+// 6 7/25/12 11:58p Barretlin
+// [TAG] EIP90644
+// [Category] Improvement
+// [Description] Change pre-boot event timing from ready to boot to pci
+// bus finish assigning resources
+// [Files] TbtDxe.sdl TbtDxe.c TbtDxeLib.c TbtDxeLib.h
+//
+// 5 5/21/12 2:21a Barretlin
+// [TAG] EIP90003
+// [Category] Improvement
+// [Description] If TBT devices with option rom enabled, system maybe
+// cannot boot to OS.
+// [Files] TbtDxe.c TbtSmm.c TbtOemBoard.sdl
+//
+// 4 5/07/12 6:34a Barretlin
+// [TAG] None
+// [Category] Improvement
+// [Description] Add three setup items for debug
+// [Files] TbtDxe.c
+// TbtGpe.asl
+// TbtSmm.c
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtOemBoard.c
+// TbtOemBoard.h
+//
+// 3 4/14/12 4:50a Barretlin
+// [TAG] None
+// [Category] Improvement
+// [Description] Improve ASL code, which redefines device name and RMV
+// mothod at same address when project supports RMV method, that might
+// cause conflict.
+// [Files] TbtDxe.c TbtGpe.asl
+//
+// 2 2/20/12 12:15a Wesleychen
+// - Add ProgramTbtSecurityLevel().
+// - Add a ready to boot event to invoke SW SMI for resource adjust.
+// - Revise the ACPI table update routine become a protocol callback
+// routine.
+//
+// 1 12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+//
+//*************************************************************************
+#include <Efi.h>
+#include <token.h>
+#include <Setup.h>
+#include <AmiLib.h>
+#include <AmiDxeLib.h>
+#include <AmiCspLib.h>
+#include <PciBus.h>
+#include <Acpi20.h>
+#include <Protocol\AcpiSupport.h>
+#include <TbtOemBoard.h>
+
+#if ACPI_SUPPORT
+ #if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x00010014)
+ #include <Protocol\AcpiSystemDescriptionTable.h>
+ #else
+ #include <Protocol\AcpiSupport.h>
+ #endif
+#endif
+#if CSM_SUPPORT
+#include <Protocol\CsmPlatform.h>
+#endif
+#ifndef EFI_SIGNATURE_16
+#define EFI_SIGNATURE_16(A, B) ((A) | (B << 8))
+#endif
+
+#ifndef EFI_SIGNATURE_32
+#define EFI_SIGNATURE_32(A, B, C, D) (EFI_SIGNATURE_16 (A, B) | (EFI_SIGNATURE_16 (C, D) << 16))
+#endif
+
+EFI_GUID gOemTbtProtocolGuid = AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID;
+EFI_GUID TbtHRStatusGuid = AMI_TBT_HR_STATUS_GUID;
+EFI_GUID gTbtHobGuid = AMI_TBT_HOB_GUID;
+EFI_GUID HobListGuid = HOB_LIST_GUID;
+EFI_GUID SetupGuid = SETUP_GUID;
+#ifdef CSM_OPRROM_POLICY_GUID
+EFI_GUID gCsmOpromPolicyGuid = CSM_OPRROM_POLICY_GUID;
+#endif
+
+AMI_TBT_PLATFORM_POLICY_PROTOCOL *gAmiTbtPlatformPolicy = NULL;
+
+typedef struct {
+ UINT32 Signature;
+ UINT32 Length;
+} EFI_ACPI_COMMON_HEADER;
+
+EFI_EVENT mAcpiEvent;
+//VOID *mAcpiReg;
+VOID *CsmOpromPolicyRegs;
+static EFI_BOOT_MODE BootMode;
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: DsdtTableUpdate
+//
+// Description: Update the DSDT table
+//
+// Input: DsdtTable - The table points to DSDT table.
+//
+// Output: None
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+DsdtTableUpdate (
+ IN ACPI_HDR *DsdtTable
+ )
+{
+ UINT8 *CurrPtr;
+ UINT8 *DsdtPointer;
+ UINT32 *Signature = NULL;
+ UINT8 DoneFlag = 0;
+ UINT8 TbtAslStartPoint = 0;
+ UINT8 HexStr[36] = {'0','1','2','3','4','5','6','7','8','9','A','B','C','D','E','F','G','H',\
+ 'I','J','K','L','M','N','O','P','Q','R','S','T','U','V','W','X','Y','Z'};
+
+ CurrPtr = (UINT8 *) DsdtTable;
+ if (gAmiTbtPlatformPolicy != NULL && (!(gAmiTbtPlatformPolicy->TbtAICSupport))) {
+ TRACE((-1, "TbtDxe: Updating DSDT table for Thunderbolt\n"));
+
+ for (DsdtPointer = CurrPtr;
+ DsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length);
+ DsdtPointer++ )
+ {
+ Signature = (UINT32 *) DsdtPointer;
+
+ if (*Signature == EFI_SIGNATURE_32 ('O', 'E', '1', 'X')) {
+ *DsdtPointer = '_';
+ // BIOS support of Thunderbolt devices Specification Update
+ // Revision 1.00
+ // Change ACPI method from level trigger to edge trigger(_L1x to _E1x)
+ #if defined ULT_SUPPORT && ULT_SUPPORT == 1
+ if(IsULTPchSeries()){
+ *(DsdtPointer + 2) = HexStr[gAmiTbtPlatformPolicy->TbtHotPlugEvt/16];
+ *(DsdtPointer + 3) = HexStr[gAmiTbtPlatformPolicy->TbtHotPlugEvt%16];
+ } else {
+ *(DsdtPointer + 3) = HexStr[gAmiTbtPlatformPolicy->TbtHotPlugEvt];
+ }
+ #else
+ *(DsdtPointer + 3) = HexStr[gAmiTbtPlatformPolicy->TbtHotPlugEvt];
+ #endif
+
+ DoneFlag = DoneFlag | 0x0f;
+ TRACE((-1, "TbtDxe: Update Thunderbolt GPE event method\n"));
+ } // GPE event
+
+ if(DoneFlag == 0x0F) return;
+ } //for loop
+ }// !(gAmiTbtPlatformPolicy->TbtAICSupport)
+
+ if (gAmiTbtPlatformPolicy != NULL && gAmiTbtPlatformPolicy->TbtAICSupport) {
+ TRACE((-1, "TbtDxe: Updating DSDT table for Thunderbolt AIC\n"));
+
+ for (DsdtPointer = CurrPtr;
+ DsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length);
+ DsdtPointer++ )
+ {
+ Signature = (UINT32 *) DsdtPointer;
+ switch(*Signature){
+ case (EFI_SIGNATURE_32 ('O', 'E', '1', 'X')):
+ *DsdtPointer = '_';
+ // BIOS support of Thunderbolt devices Specification Update
+ // Revision 1.00
+ // Change ACPI method from level trigger to edge trigger(_L1x to _E1x)
+ #if defined ULT_SUPPORT && ULT_SUPPORT == 1
+ if(IsULTPchSeries()){
+ *(DsdtPointer + 2) = HexStr[gAmiTbtPlatformPolicy->TbtHotPlugEvt/16];
+ *(DsdtPointer + 3) = HexStr[gAmiTbtPlatformPolicy->TbtHotPlugEvt%16];
+ } else {
+ *(DsdtPointer + 3) = HexStr[gAmiTbtPlatformPolicy->TbtHotPlugEvt];
+ }
+ #else
+ *(DsdtPointer + 3) = HexStr[gAmiTbtPlatformPolicy->TbtHotPlugEvt];
+ #endif
+
+ DoneFlag = DoneFlag | BIT00;
+ TRACE((-1, "TbtDxe: Update Thunderbolt GPE event method\n"));
+ break;
+#if defined TBT_INTEL_RC_CONFIG && TBT_INTEL_RC_CONFIG == 1
+#if defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 0
+ case (EFI_SIGNATURE_32 ('R', 'P', '0', '1')):
+#elif defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 1
+ case (EFI_SIGNATURE_32 ('R', 'P', '0', '2')):
+#elif defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 2
+ case (EFI_SIGNATURE_32 ('R', 'P', '0', '3')):
+#elif defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 3
+ case (EFI_SIGNATURE_32 ('R', 'P', '0', '4')):
+#elif defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 4
+ case (EFI_SIGNATURE_32 ('R', 'P', '0', '5')):
+#elif defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 5
+ case (EFI_SIGNATURE_32 ('R', 'P', '0', '6')):
+#elif defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 6
+ case (EFI_SIGNATURE_32 ('R', 'P', '0', '7')):
+#else
+ case (EFI_SIGNATURE_32 ('R', 'P', '0', '8')):
+#endif
+#endif // TBT_INTEL_RC_CONFIG
+ if (DoneFlag){
+ if (gAmiTbtPlatformPolicy->Dev == 0x1C && \
+ gAmiTbtPlatformPolicy->Fun != TBT_UP_PORT_FUNC){
+ *(DsdtPointer + 3) = HexStr[(gAmiTbtPlatformPolicy->Fun + 1)];
+ DoneFlag++;
+ TRACE((-1, "TbtDxe: Update Thunderbolt Host ASL location to SB root port %x\n", gAmiTbtPlatformPolicy->Fun));
+ }
+ if (gAmiTbtPlatformPolicy->Bus == 0 && \
+ gAmiTbtPlatformPolicy->Dev == 1){
+ *DsdtPointer = HexStr[25]; // 'P'
+ *(DsdtPointer + 1) = HexStr[14]; // 'E'
+ *(DsdtPointer + 2) = HexStr[16]; // 'G'
+ *(DsdtPointer + 3) = HexStr[(gAmiTbtPlatformPolicy->Fun)];
+ DoneFlag++;
+ TRACE((-1, "TbtDxe: Update Thunderbolt Host ASL location to PEG%x\n", gAmiTbtPlatformPolicy->Fun));
+ }
+ }
+ break;
+ default:
+ break;
+ } // switch
+
+#if defined TBT_S3_WAK_SMI && TBT_S3_WAK_SMI == 1 && TBT_PCI0_INI_SUPPORT == 1
+ if(DoneFlag == 0x06) return;
+#elif defined TBT_PCI0_INI_SUPPORT && TBT_PCI0_INI_SUPPORT == 1
+ if(DoneFlag == 0x05) return;
+#else
+ if(DoneFlag == 0x04) return;
+#endif
+ } // for loop
+ }// gAmiTbtPlatformPolicy->TbtAICSupport
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: CreateTbtAcpiCallback
+//
+// Description: This function will create all ACPI components for SB when
+// ACPI support protocol is available.
+//
+// Input: Event - Event of callback
+// Context - Context of callback.
+//
+// Output: None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID CreateTbtAcpiCallback (
+ IN EFI_EVENT Event,
+ IN VOID *Context )
+{
+ UINTN Index;
+ EFI_ACPI_SUPPORT_PROTOCOL *As;
+ FACP_20 *Table = NULL;
+ EFI_ACPI_TABLE_VERSION Version;
+ UINTN Handle;
+ ACPI_HDR *DsdtPtr = NULL;
+ EFI_STATUS Status;
+ //UINT8 SubBus;
+ UINTN HRStatusSize = sizeof(AMI_TBT_HR_STATUS_DATA);
+ AMI_TBT_HR_STATUS_DATA HRStatusData;
+ UINT8 TbtSmiNotifyEnable;
+ UINT8 TbtBus;
+ SETUP_DATA *SetupData;
+ UINTN VariableSize = sizeof(SETUP_DATA);
+
+ Status = pBS->LocateProtocol(&gEfiAcpiSupportGuid, NULL, &As);
+
+ // Find DSDT ACPI Table
+ for (Index = 0; Index < ACPI_RSDT_TABLE_NUM; Index++) {
+ Status = As->GetAcpiTable(As, Index, &Table, &Version, &Handle);
+ if (EFI_ERROR(Status)) break;//no more tables left
+
+ if ((Table->Header.Signature == FACP_SIG) && (DsdtPtr == NULL)) {
+ DsdtPtr = (ACPI_HDR*)Table->DSDT;
+
+ TRACE((-1, "TbtDxe: Found DSDT Table at 0x%08X\n", DsdtPtr));
+
+ DsdtTableUpdate (DsdtPtr);
+
+ // Thunderbolt BIOS Implementation guide for Redwood Ridge/Falcon Ridge
+ // based devices rev 1.0
+ // 2.1.3.2 BIOS setup options for Thunderbolt
+ // Switch between Native PCIe Enable and Disabled with the following settings:
+ // --------------------------------------------------------------------
+ // Native PCIe support disabled (default) | Native PCIe support enabled
+ // --------------------------------------------------------------------
+ // SCI Call Enabled | SCI Call Enabled
+ // --------------------------------------------------------------------
+ // SMI Call Enabled | SMI Call Disabled
+ // --------------------------------------------------------------------
+ // Notify Call Enabled | Notify Call Enabled
+ // --------------------------------------------------------------------
+ Status = pBS->AllocatePool( EfiBootServicesData,
+ VariableSize,
+ &SetupData );
+ ASSERT_EFI_ERROR(Status);
+
+ Status = pRS->GetVariable( L"Setup", \
+ &SetupGuid, \
+ NULL, \
+ &VariableSize, \
+ SetupData );
+ ASSERT_EFI_ERROR (Status);
+
+#if defined TBT_INTEL_RC_CONFIG && TBT_INTEL_RC_CONFIG == 1
+ if (SetupData->PciExpNative){
+ TbtSmiNotifyEnable = gAmiTbtPlatformPolicy->NotifyEnabled << 1;
+ } else {
+ TbtSmiNotifyEnable = gAmiTbtPlatformPolicy->SwSmiEnabled | (gAmiTbtPlatformPolicy->NotifyEnabled << 1);
+ }
+#else
+ // For non Intel RC project
+ TbtSmiNotifyEnable = gAmiTbtPlatformPolicy->SwSmiEnabled | (gAmiTbtPlatformPolicy->NotifyEnabled << 1);
+#endif
+ Status = UpdateAslNameObject(DsdtPtr, "TSNE", TbtSmiNotifyEnable);
+ TRACE((-1, "TbtDxe: Updating TSNE Name Object %r\n", Status));
+ ASSERT_EFI_ERROR(Status);
+ pBS->FreePool(SetupData);
+
+ //Update System MMIO PCIE Base address
+ //TRACE((-1, "TbtDxe: Update TBT Host DownStream port MMIO Base address in ASL code\n"));
+ //SubBus = READ_PCI8(gAmiTbtPlatformPolicy->Bus, gAmiTbtPlatformPolicy->Dev, gAmiTbtPlatformPolicy->Fun, PCI_PBUS+1);
+ //Status = UpdateAslNameObject(DsdtPtr, "PEMA", (PCIEX_BASE_ADDRESS | (SubBus << 20)));
+ //TRACE((-1, "TbtDxe: Updating PEMA Name Object %r\n", Status));
+ //ASSERT_EFI_ERROR(Status);
+
+ //Update TBT Host location bus in ASL code
+ if (gAmiTbtPlatformPolicy->TbtAICSupport){
+ if (gAmiTbtPlatformPolicy->Bus == 0 && gAmiTbtPlatformPolicy->Dev == 0x1c){
+ Status = UpdateAslNameObject(DsdtPtr, "TBRP", (gAmiTbtPlatformPolicy->Fun + 1));
+ TRACE((-1, "TbtDxe: Updating TBRP Name Object %r\n", Status));
+ ASSERT_EFI_ERROR(Status);
+ } else if (gAmiTbtPlatformPolicy->Bus == 0 && gAmiTbtPlatformPolicy->Dev == 1){
+ Status = UpdateAslNameObject(DsdtPtr, "TBRP", (gAmiTbtPlatformPolicy->Fun + 0x20));
+ TRACE((-1, "TbtDxe: Updating TBRP Name Object %r\n", Status));
+ ASSERT_EFI_ERROR(Status);
+ }
+ }
+ TbtBus = MMIO_READ8(TBT_CFG_ADDRESS(gAmiTbtPlatformPolicy->Bus, gAmiTbtPlatformPolicy->Dev, gAmiTbtPlatformPolicy->Fun, PCI_SBUS));
+ Status = UpdateAslNameObject(DsdtPtr, "TBUS", TbtBus);
+ TRACE((-1, "TbtDxe: Updating TBUS Name Object %r\n", Status));
+ ASSERT_EFI_ERROR(Status);
+
+ //Update TBT Host Information in ASL code
+ TRACE((-1, "TbtDxe: Update TBT Host Information in ASL code\n"));
+ Status = pRS->GetVariable( L"TbtHRStatusVar", \
+ &TbtHRStatusGuid, \
+ NULL, \
+ &HRStatusSize, \
+ &HRStatusData );
+ if (!EFI_ERROR(Status)){
+ Status = UpdateAslNameObject(DsdtPtr, "TBHR", HRStatusData.TbtHRSeries);
+ TRACE((-1, "TbtDxe: Updating TBHR Name Object %r\n", Status));
+ ASSERT_EFI_ERROR(Status);
+ }
+
+ // Update _RMV method return value for Thunderbolt
+ Status = UpdateAslNameObject( DsdtPtr, "TBMV", gAmiTbtPlatformPolicy->TbtRmvReturnValue);
+ TRACE((-1, "TbtDxe: Update TRMV ASL object value = %x, %r\n", gAmiTbtPlatformPolicy->TbtRmvReturnValue, Status));
+ ASSERT_EFI_ERROR(Status);
+
+ break;
+ }
+ }
+ // Kill the Event
+ pBS->CloseEvent(Event);
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: DisableTbtDeviceRomCallback
+//
+// Description: Disable all Tbt devices option ROM to aviod S4 resume problem.
+//
+// Input: Event - Event of callback
+// Context - Context of callback.
+//
+// Output: None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID DisableTbtDeviceRomCallback (
+ IN EFI_EVENT Event,
+ IN VOID *Context )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+ UINTN Size = sizeof(EFI_HANDLE);
+ CSM_PLATFORM_POLICY_DATA *CsmOpromPolicyData;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ PCI_DEV_INFO *Device;
+
+ TRACE((-1, "TbtDxe: DisableTbtDeviceRomCallback() Entry\n"));
+
+ Status = pBS->LocateHandle(ByRegisterNotify, NULL, CsmOpromPolicyRegs, &Size, &Handle);
+ if (EFI_ERROR(Status)) return;
+
+ Status = pBS->HandleProtocol(Handle, &gCsmOpromPolicyGuid, &CsmOpromPolicyData);
+ if (EFI_ERROR(Status)) return;
+
+ if(CsmOpromPolicyData == NULL) return; //post-process OpROM callback
+ if(CsmOpromPolicyData->PciIo == NULL) return; // OEM Service ROM
+
+ PciIo = CsmOpromPolicyData->PciIo;
+ Device = (PCI_DEV_INFO*)PciIo;
+ while ((Device->Type != tPciRootBrg) && (Device->ParentBrg != NULL)) {
+ Device = Device->ParentBrg;
+ if (Device->Address.Addr.Bus != gAmiTbtPlatformPolicy->Bus) continue;
+ if (Device->Address.Addr.Device != gAmiTbtPlatformPolicy->Dev) continue;
+ if (Device->Address.Addr.Function != gAmiTbtPlatformPolicy->Fun) continue;
+ if (gAmiTbtPlatformPolicy->TbtOptionRom || (BootMode & BOOT_ON_S4_RESUME)){
+ CsmOpromPolicyData->ExecuteThisRom = FALSE; //this attritube default is TRUE
+ TRACE((-1, "TbtDxe: ExecuteThisRom is setted FALSE.\n"));
+ }
+
+ break;
+ }
+
+ TRACE((-1, "TbtDxe: DisableTbtDeviceRomCallback() Exit\n"));
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: InvokeSmiHandlerBeforeBoot
+//
+// Description: To invoke SW SMI befor boot for reaource adjust.
+//
+// Input: Event - Event of callback
+// Context - Context of callback.
+//
+// Output: None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID InvokeSmiHandlerBeforeBoot (
+ IN EFI_EVENT Event,
+ IN VOID *Context )
+{
+ TbtDxeInvokeSmiHandler();
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: TbtDxe_Init
+//
+// Description: This function is the entry point for this DXE.
+//
+// Input: ImageHandle - Image handle
+// SystemTable - Pointer to the system table
+//
+// Output: Return Status based on errors that occurred while waiting for
+// time to expire.
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS TbtDxe_Init (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable )
+{
+ EFI_STATUS Status;
+ EFI_EVENT CsmOpromPolicyEvent = NULL;
+ TBT_HOB *gTbtHob;
+
+ InitAmiLib(ImageHandle, SystemTable);
+ TRACE((-1, "TbtDxe: TbtDxe_Init() Entry!!\n"));
+
+ Status = pBS->LocateProtocol( \
+ &gOemTbtProtocolGuid, \
+ NULL, \
+ &gAmiTbtPlatformPolicy);
+ if (!EFI_ERROR(Status)) {
+ BootMode = GetBootMode();
+ if (gAmiTbtPlatformPolicy->TbtEnable){
+#ifdef CSM_OPRROM_POLICY_GUID
+ Status = RegisterProtocolCallback (&gCsmOpromPolicyGuid,
+ DisableTbtDeviceRomCallback,
+ NULL, &CsmOpromPolicyEvent,
+ &CsmOpromPolicyRegs);
+#endif
+ if (gAmiTbtPlatformPolicy->SmiNotifyEnabled) {
+#if (ACPI_SUPPORT)
+ Status = CreateReadyToBootEvent( TPL_NOTIFY,
+ CreateTbtAcpiCallback,
+ NULL,
+ &mAcpiEvent);
+#endif
+ } // SmiNotifyEnabled
+
+ gTbtHob = (TBT_HOB *)GetEfiConfigurationTable(SystemTable, &HobListGuid);
+ if (gTbtHob){
+ Status = FindNextHobByGuid((EFI_GUID*)&gTbtHobGuid, &gTbtHob);
+ if (!(EFI_ERROR(Status)) && gTbtHob->TbtSecurityLevelFlag){
+ TRACE((-1, "TbtDxe: Need Finish final programming !!!\n"));
+ FinialProgramTbtSecurityLevel(gAmiTbtPlatformPolicy);
+ }
+ } // gTbtHob
+ else TRACE((-1, "TbtDxe: Can not find Thunderbolt Hob !!!\n"));
+ }// TbtEnable
+ }// gAmiTbtPlatformPolicy success
+ TRACE((-1, "TbtDxe: TbtDxe_Init() Exit!!\n"));
+
+ return EFI_SUCCESS;
+}
+
+
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtDxe/TbtDxe.cif b/Board/EM/Thunderbolt/TbtDxe/TbtDxe.cif
new file mode 100644
index 0000000..5e71252
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtDxe/TbtDxe.cif
@@ -0,0 +1,14 @@
+<component>
+ name = "TbtDxe"
+ category = ModulePart
+ LocalRoot = "Board\EM\Thunderbolt\TbtDxe\"
+ RefName = "TbtDxe"
+[files]
+"TbtDxe.sdl"
+"TbtDxe.mak"
+"TbtDxe.c"
+"TbtDxe.dxs"
+"TbtGpe.asl"
+"TbtDxeLib.c"
+"TbtDxeLib.h"
+<endComponent>
diff --git a/Board/EM/Thunderbolt/TbtDxe/TbtDxe.dxs b/Board/EM/Thunderbolt/TbtDxe/TbtDxe.dxs
new file mode 100644
index 0000000..3e8c7e0
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtDxe/TbtDxe.dxs
@@ -0,0 +1,54 @@
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtDxe.dxs 1 1/10/13 4:56a Barretlin $
+//
+// $Revision: 1 $
+//
+// $Date: 1/10/13 4:56a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtDxe.dxs $
+//
+// 1 1/10/13 4:56a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+//
+// 2 2/20/12 12:15a Wesleychen
+// Revise the ACPI table update routine become a protocol callback
+// routine.
+//
+// 1 12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+//
+//**********************************************************************
+#include <TbtOemboard.h>
+
+DEPENDENCY_START
+ AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID
+DEPENDENCY_END
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtDxe/TbtDxe.mak b/Board/EM/Thunderbolt/TbtDxe/TbtDxe.mak
new file mode 100644
index 0000000..7fa124a
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtDxe/TbtDxe.mak
@@ -0,0 +1,104 @@
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
+#**********************************************************************
+# $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtDxe.mak 1 1/10/13 4:56a Barretlin $
+#
+# $Revision: 1 $
+#
+# $Date: 1/10/13 4:56a $
+#**********************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtDxe.mak $
+#
+# 1 1/10/13 4:56a Barretlin
+# Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+# Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+#
+# 2 2/20/12 12:09a Wesleychen
+# [TAG] None
+# [Category] Improvement
+# [Description] Add TbtDxeLib.
+# [Files] TbtDxeLib.c; TbtDxeLib.h; TbtDxe.mak; TbtDxe.sdl;
+# TbtDxe.cif.
+#
+# 1 12/08/11 4:09a Wesleychen
+# Thunderbolt eModule initially releases.
+#
+# 6 1/13/10 2:13p Felixp
+#
+#**********************************************************************
+#<AMI_FHDR_START>
+#
+# Name: TbtDxe.mak
+#
+# Description:
+#
+#<AMI_FHDR_END>
+#**********************************************************************
+All : TbtDxe
+
+CFLAGS = $(CFLAGS) /I$(TbtDxe_DIR)
+#----------------------------------------------------------------------------
+# Generic TBT dependencies
+#----------------------------------------------------------------------------
+$(BUILD_DIR)\TbtDxe.mak : $(TbtDxe_DIR)\$(@B).cif $(TbtDxe_DIR)\$(@B).mak $(BUILD_RULES)
+ $(CIF2MAK) $(TbtDxe_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+#----------------------------------------------------------------------------
+# Add files into CSP Library
+#----------------------------------------------------------------------------
+AMI_CSP_LIB_LIBRARY_PATH = $(AMI_CSP_LIB_LIBRARY_PATH);$(TbtDxe_DIR)
+
+AMI_CSP_LIB_INCLUDE_FILES = "$(TbtDxe_DIR)\TbtDxeLib.h" + \
+$(AMI_CSP_LIB_INCLUDE_FILES)
+
+AMI_CSP_LIB_OBJS = $(AMI_CSP_LIB_OBJS) \
+$(BUILD_DIR)\TbtDxeLib.obj
+
+{$(TbtDxe_DIR)}.c{$(BUILD_DIR)}.obj::
+ $(CC) $(CFLAGS) /I $(TbtDxe_DIR) /Fo$(BUILD_DIR)\ $<
+
+$(BUILD_DIR)\TbtDxeLib.obj : $(TbtDxe_DIR)\TbtDxeLib.c
+
+#----------------------------------------------------------------------------
+# Create TBT DXE Component
+#----------------------------------------------------------------------------
+TbtDxe : $(BUILD_DIR)\TbtDxe.mak TbtDxeBin
+TBT_DXE_OBJECTS =\
+$$(BUILD_DIR)\$(TbtDxe_DIR)\TbtDxe.obj \
+
+TbtDxeBin : $(AMICSPLib) $(AMIDXELIB)
+ $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\
+ /f $(BUILD_DIR)\TbtDxe.mak all\
+ GUID=EFB7F614-BC8B-4DDD-B09A-22079FC1512F\
+ ENTRY_POINT=TbtDxe_Init \
+ "MY_INCLUDES=$(TBT_OEMBOARD_INCLUDES)"\
+ TYPE=BS_DRIVER\
+ DEPEX1=$(TbtDxe_DIR)\TbtDxe.dxs\
+ DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\
+ COMPRESS=1
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtDxe/TbtDxe.sdl b/Board/EM/Thunderbolt/TbtDxe/TbtDxe.sdl
new file mode 100644
index 0000000..eef55bc
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtDxe/TbtDxe.sdl
@@ -0,0 +1,586 @@
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
+#*************************************************************************
+# $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtDxe.sdl 8 7/26/13 2:46a Barretlin $
+#
+# $Revision: 8 $
+#
+# $Date: 7/26/13 2:46a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtDxe.sdl $
+#
+# 8 7/26/13 2:46a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Separate ASL code for Intel RC and non Intel RC
+# [Files] TbtDxe.sdl TbtDxe.cif
+#
+# 7 6/21/13 7:40a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Fix build error with non Intel RC project
+# [Files] TbtDxe.sdl TbtDxe.c TbtGpe.asl TbtDxeLib.h
+#
+# 6 5/27/13 8:54a Barretlin
+# [TAG] EIP122882
+# [Category] Bug Fix
+# [Severity] Normal
+# [Symptom] let system entering sleep status continually and waking up
+# system via Thunderbolt Lan device, system will auto-wake
+# [RootCause] PCIE PME status is not cleared by ASL in SB module
+# [Solution] Clear PCIE PME status againg before system entring sleep
+# status
+# [Files] TbtDxe.sdl TbtGpe.asl
+#
+# 5 4/10/13 1:37p Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Adding a TPTS method into _PTS method in ASL code
+# [Files] TbtDxe.sdl TbtGpe.asl
+#
+# 4 3/21/13 4:58a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Use token to decide where location of OS_UP command for
+# RR chip is
+# [Files] TbtDxe.sdl TbtGpe.asl
+#
+# 3 2/08/13 1:23a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Following Intel sample code move _INI method of
+# thunderbolt from under PCIE root port to under system bus
+# [Files] TbtDxe.sdl TbtGpe.asl
+#
+# 2 1/18/13 2:26a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Improve _RMV ASL code for SharkBay RC
+# [Files] TbtDxe.sdl TbtDxe.c TbtGpe.asl
+#
+# 1 1/10/13 4:56a Barretlin
+# Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+# Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+#
+# 7 12/12/12 3:02a Barretlin
+# [TAG] EIP108272
+# [Category] Spec Update
+# [Severity] Important
+# [Description] Update to Spec 1.4 to support Redwood Ridge chip
+# [Files] TbtPei.c TbtSmm.c TbtDxe.c TbtDxe.sdl TbtGpe.asl
+# TbtOemBoard.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+#
+# 6 7/25/12 11:58p Barretlin
+# [TAG] EIP90644
+# [Category] Improvement
+# [Description] Change pre-boot event timing from ready to boot to pci
+# bus finish assigning resources
+# [Files] TbtDxe.sdl TbtDxe.c TbtDxeLib.c TbtDxeLib.h
+#
+# 5 5/22/12 9:48a Barretlin
+# [TAG] EIPNone
+# [Category] Improvement
+# [Description] Rollback default value of token
+# [Files] TbtDxe.sdl
+#
+# 4 5/07/12 6:30a Barretlin
+# [TAG] None
+# [Category] Improvement
+# [Description] change default value of token, because of it is need
+# SwSMI when S3 resume
+# [Files] TbtDxe.sdl
+#
+# 3 4/16/12 10:17a Barretlin
+# [TAG] EIP86590
+# [Category] Bug Fix
+# [Symptom] Only EP#1 can be detected after resume from S3
+# [Solution] Adding a TWAK method into _WAK method
+# [Files] TbtDxe.sdl TbtGpe.asl
+#
+# 2 2/20/12 12:09a Wesleychen
+# [TAG] None
+# [Category] Improvement
+# [Description] Add TbtDxeLib.
+# [Files] TbtDxeLib.c; TbtDxeLib.h; TbtDxe.mak; TbtDxe.sdl;
+# TbtDxe.cif.
+#
+# 1 12/08/11 4:09a Wesleychen
+# Thunderbolt eModule initially releases.
+#
+#*************************************************************************
+
+TOKEN
+ Name = "TbtDxe_SUPPORT"
+ Value = "1"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ Master = Yes
+ Help = "Main switch to enable TbtDxe support in Project"
+End
+
+TOKEN
+ Name = "TBT_RPNum"
+ Value = "1"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Token = "TBT_UP_PORT_FUNC" "=" "0"
+ Lock = Yes
+End
+
+TOKEN
+ Name = "TBT_RPNum"
+ Value = "0"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Token = "TBT_UP_PORT_FUNC" "=" "0"
+ TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+ Lock = Yes
+End
+
+TOKEN
+ Name = "TBT_RPNum"
+ Value = "2"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Token = "TBT_UP_PORT_FUNC" "=" "1"
+ Lock = Yes
+End
+
+TOKEN
+ Name = "TBT_RPNum"
+ Value = "1"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Token = "TBT_UP_PORT_FUNC" "=" "1"
+ TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+ Lock = Yes
+End
+
+TOKEN
+ Name = "TBT_RPNum"
+ Value = "3"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Token = "TBT_UP_PORT_FUNC" "=" "2"
+ Lock = Yes
+End
+
+TOKEN
+ Name = "TBT_RPNum"
+ Value = "2"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Token = "TBT_UP_PORT_FUNC" "=" "2"
+ TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+ Lock = Yes
+End
+
+TOKEN
+ Name = "TBT_RPNum"
+ Value = "4"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Token = "TBT_UP_PORT_FUNC" "=" "3"
+ Lock = Yes
+End
+
+TOKEN
+ Name = "TBT_RPNum"
+ Value = "3"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Token = "TBT_UP_PORT_FUNC" "=" "3"
+ TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+ Lock = Yes
+End
+
+TOKEN
+ Name = "TBT_RPNum"
+ Value = "5"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Token = "TBT_UP_PORT_FUNC" "=" "4"
+ Lock = Yes
+End
+
+TOKEN
+ Name = "TBT_RPNum"
+ Value = "4"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Token = "TBT_UP_PORT_FUNC" "=" "4"
+ TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+ Lock = Yes
+End
+
+TOKEN
+ Name = "TBT_RPNum"
+ Value = "6"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Token = "TBT_UP_PORT_FUNC" "=" "5"
+ Lock = Yes
+End
+
+TOKEN
+ Name = "TBT_RPNum"
+ Value = "5"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Token = "TBT_UP_PORT_FUNC" "=" "5"
+ TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+ Lock = Yes
+End
+
+TOKEN
+ Name = "TBT_RPNum"
+ Value = "7"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Token = "TBT_UP_PORT_FUNC" "=" "6"
+ Lock = Yes
+End
+
+TOKEN
+ Name = "TBT_RPNum"
+ Value = "6"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Token = "TBT_UP_PORT_FUNC" "=" "6"
+ TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+ Lock = Yes
+End
+
+TOKEN
+ Name = "TBT_RPNum"
+ Value = "8"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Token = "TBT_UP_PORT_FUNC" "=" "7"
+ Lock = Yes
+End
+
+TOKEN
+ Name = "TBT_RPNum"
+ Value = "7"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Token = "TBT_UP_PORT_FUNC" "=" "7"
+ TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+ Lock = Yes
+End
+
+TOKEN
+ Name = "TBT_RP_NUM"
+ Value = "\_SB.PCI0.RP0$(TBT_RPNum)"
+ TokenType = Expression
+ TargetH = Yes
+ Lock = Yes
+End
+
+TOKEN
+ Name = "TBT_RP_NUM"
+ Value = "\_SB.PCI0.PEX$(TBT_RPNum)"
+ TokenType = Expression
+ TargetH = Yes
+ TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+ Lock = Yes
+End
+
+TOKEN
+ Name = "TBT_RMV_REPORT"
+ Value = "1"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ TargetH = Yes
+ Help = "Enable:1/Disable:0 Thunderbolt module report _RMV function in ASL code."
+ Token = "DESKTOP_306AX" "=" "1"
+ Token = "HOTPLUG_RMV_SUPPORT" "=" "0"
+ TOKEN = "TBT_INTEL_RC_CONFIG" "=" "1"
+End
+
+TOKEN
+ Name = "TBT_RMV_REPORT"
+ Value = "1"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ TargetH = Yes
+ Help = "Enable:1/Disable:0 Thunderbolt module report _RMV function in ASL code."
+ Token = "MOBILE_306AX" "=" "1"
+ Token = "HOTPLUG_RMV_SUPPORT" "=" "0"
+ TOKEN = "TBT_INTEL_RC_CONFIG" "=" "1"
+End
+
+TOKEN
+ Name = "TBT_RMV_REPORT"
+ Value = "1"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ TargetH = Yes
+ Help = "Enable:1/Disable:0 Thunderbolt module report _RMV function in ASL code."
+ TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+End
+
+TOKEN
+ Name = "TBT_WAK_SUPPORT"
+ Value = "1"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ TargetH = Yes
+ Help = "Main switch to enable TWAK method in ASL code"
+End
+
+TOKEN
+ Name = "TBT_PTS_SUPPORT"
+ Value = "1"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ TargetH = Yes
+ Help = "Main switch to enable TPTS method in ASL code"
+End
+
+TOKEN
+ Name = "TBT_PCI0_INI_SUPPORT"
+ Value = "0"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ TargetH = Yes
+ Help = "Enable/Disable OS_UP command of RR chip under _INI method of system bus in ASL code."
+End
+
+TOKEN
+ Name = "TBT_S3_WAK_SMI"
+ Value = "0"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ TargetH = Yes
+ Help = "Enable:1/Disable:0 trigger TBT SMI in ASL code when S3 resuming"
+End
+
+TOKEN
+ Name = "TBT_WAK"
+ Value = "\_SB.PCI0.RP0$(TBT_RPNum).TWAK(Arg0)"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Lock = Yes
+ Token = "TBT_WAK_SUPPORT" "=" "1"
+End
+
+TOKEN
+ Name = "TBT_WAK"
+ Value = "\_SB.PCI0.PEX$(TBT_RPNum).TWAK(Arg0)"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Lock = Yes
+ Token = "TBT_WAK_SUPPORT" "=" "1"
+ TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+End
+
+TOKEN
+ Name = "TBT_PTS"
+ Value = "\_SB.PCI0.RP0$(TBT_RPNum).TPTS(Arg0)"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Lock = Yes
+ Token = "TBT_PTS_SUPPORT" "=" "1"
+End
+
+TOKEN
+ Name = "TBT_PTS"
+ Value = "\_SB.PCI0.PEX$(TBT_RPNum).TPTS(Arg0)"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Lock = Yes
+ Token = "TBT_PTS_SUPPORT" "=" "1"
+ TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+End
+
+TOKEN
+ Name = "TBT_CLEAR_PME_STATUS"
+ Value = "1"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ TargetH = Yes
+ Help = "Enable:1/Disable:0 Clear PCIE root port thunderbolt host located PME status in ASL code."
+ Token = "TBT_PTS_SUPPORT" "=" "1"
+End
+
+TOKEN
+ Name = "TBT_CLEAR_PME_STATUS"
+ Value = "0"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ TargetH = Yes
+ Help = "Enable:1/Disable:0 Clear PCIE root port thunderbolt host located PME status in ASL code."
+ Token = "MOBILE_306AX" "=" "1"
+ Token = "TBT_PTS_SUPPORT" "=" "1"
+End
+
+TOKEN
+ Name = "TBT_CLEAR_PME_STATUS"
+ Value = "0"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ TargetH = Yes
+ Help = "Enable:1/Disable:0 Clear PCIE root port thunderbolt host located PME status in ASL code."
+ Token = "DESKTOP_306AX" "=" "1"
+ Token = "TBT_PTS_SUPPORT" "=" "1"
+End
+
+TOKEN
+ Name = "TBT_INI"
+ Value = "\_SB.PCI0.RP0$(TBT_RPNum).TINI()"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Lock = Yes
+ Token = "TBT_PCI0_INI_SUPPORT" "=" "1"
+End
+
+TOKEN
+ Name = "TBT_INI"
+ Value = "\_SB.PCI0.PEX$(TBT_RPNum).TINI()"
+ TokenType = Expression
+ TargetMak = Yes
+ TargetH = Yes
+ Lock = Yes
+ Token = "TBT_PCI0_INI_SUPPORT" "=" "1"
+ TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+End
+
+MODULE
+ Help = "Includes TbtDxe.mak to Project"
+ File = "TbtDxe.mak"
+End
+
+PATH
+ Name = "TbtDxe_DIR"
+End
+
+ELINK
+ Name = "/I$(TbtDxe_DIR)"
+ Parent = "TBT_DXE_INCLUDES"
+ InvokeOrder = AfterParent
+End
+
+ELINK
+ Name = "TBT_DXE_INCLUDES"
+ InvokeOrder = ReplaceParent
+End
+
+ELINK
+ Name = "$(TbtDxe_DIR)\TbtGpe.asl"
+ Parent = "INTEL_GENERIC_ASL"
+ InvokeOrder = AfterParent
+ TOKEN = "TBT_INTEL_RC_CONFIG" "=" "1"
+End
+
+ELINK
+ Name = "$(TbtDxe_DIR)\TbtGpeNonRC.asl"
+ Parent = "GENERIC_ASL"
+ InvokeOrder = AfterParent
+ TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+End
+
+ELINK
+ Name = "$(TBT_WAK)"
+ Parent = "ASL_WAK"
+ Help = "Include TBT Specific Function at WAK.\Arg0 is a sleep state the System is resuming from. "
+ SrcFile = "$(TbtDxe_DIR)\TbtGpe.ASL"
+ InvokeOrder = AfterParent
+ Token = "TBT_WAK_SUPPORT" "=" "1"
+End
+
+ELINK
+ Name = "$(TBT_PTS)"
+ Parent = "ASL_PTS"
+ Help = "Include TBT Specific Function at PTS.\Arg0 is a sleep state the System is resuming from. "
+ SrcFile = "$(TbtDxe_DIR)\TbtGpe.ASL"
+ InvokeOrder = AfterParent
+ Token = "TBT_PTS_SUPPORT" "=" "1"
+End
+
+ELINK
+ Name = "$(TBT_INI)"
+ Parent = "ASL_PCI0_INI"
+ Help = "Include TBT Specific Function at _INI method of PCI0."
+ SrcFile = "$(TbtDxe_DIR)\TbtGpe.ASL"
+ InvokeOrder = AfterParent
+ Token = "TBT_PCI0_INI_SUPPORT" "=" "1"
+End
+
+ELINK
+ Name = "$(BUILD_DIR)\TbtDxe.ffs"
+ Parent = "FV_MAIN"
+ InvokeOrder = AfterParent
+End
+
+ELINK
+ Name = "OEM_PCI_DEVICE_CALLBACK(0, 0, TbtProtectedPciDevice),"
+ Parent = "OEM_SKIP_PCI_DEVICE"
+ InvokeOrder = AfterParent
+End
+
+ELINK
+ Name = "TbtDxeInvokeSmiHandler,"
+ Parent = "ConnectRootBridgeHandles,"
+ InvokeOrder = AfterParent
+End
+
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtDxe/TbtDxeLib.c b/Board/EM/Thunderbolt/TbtDxe/TbtDxeLib.c
new file mode 100644
index 0000000..45f6768
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtDxe/TbtDxeLib.c
@@ -0,0 +1,209 @@
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
+//*************************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtDxeLib.c 4 5/16/14 6:02p Barretlin $
+//
+// $Revision: 4 $
+//
+// $Date: 5/16/14 6:02p $
+//*************************************************************************
+// Revision History
+// ----------------
+//
+//*************************************************************************
+//---------------------------------------------------------------------------
+// Include(s)
+//---------------------------------------------------------------------------
+
+#include <Efi.h>
+#include <Token.h>
+#include <Setup.h>
+#include <AmiPeiLib.h>
+#include <AmiDxeLib.h>
+#include <AmiCspLib.h>
+
+// Produced Protocols
+
+// Consumed Protocols
+
+//---------------------------------------------------------------------------
+// Constant, Macro and Type Definition(s)
+//---------------------------------------------------------------------------
+// Constant Definition(s)
+
+// Macro Definition(s)
+
+// Type Definition(s)
+
+// Function Prototype(s)
+
+//---------------------------------------------------------------------------
+// Variable and External Declaration(s)
+//---------------------------------------------------------------------------
+// Variable Declaration(s)
+
+// GUID Definition(s)
+
+// Protocol Definition(s)
+
+// External Declaration(s)
+
+// Function Definition(s)
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: TbtProtectedPciDevice
+//
+// Description: This function is called by PCI Bus Driver before configuring
+// or disabling any PCI device. This function should examine the
+// Vendor/Device ID or PCI Bus, Device and Function numbers to
+// make sure it is not a south bridge device or any other device
+// which should no be configured by PCI Bus Driver.
+//
+// Input: *PciDevice - Pointer to PCI Device Info structure.
+//
+// Output: EFI_STATUS
+// EFI_SUCCESS - SKIP this device, do not touch
+// PCI Command register.
+// EFI_UNSUPPORTED - DON'T SKIP this device do complete
+// enumeration as usual.
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS TbtProtectedPciDevice (
+ IN PCI_DEV_INFO *PciDevice )
+{
+ AMI_TBT_PLATFORM_POLICY_PROTOCOL *gAmiTbtPlatformPolicy = NULL;
+ EFI_GUID gOemTbtProtocolGuid = AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID;
+ EFI_STATUS Status;
+ UINT8 TBus = TBT_UP_PORT_BUS;
+ UINT8 TDev = TBT_UP_PORT_DEV;
+ UINT8 TFun = TBT_UP_PORT_FUNC;
+
+ TRACE((-1, "\nTbtDxe: TbtProtectedPciDevice Entry !!!\n"));
+ Status = pBS->LocateProtocol( &gOemTbtProtocolGuid, \
+ NULL, \
+ &gAmiTbtPlatformPolicy);
+ if (EFI_ERROR(Status) || (!(gAmiTbtPlatformPolicy->TbtEnable))){
+ return EFI_UNSUPPORTED;
+ }
+
+ if ((!EFI_ERROR(Status)) && (gAmiTbtPlatformPolicy->TbtAICSupport == 1)){
+ if (gAmiTbtPlatformPolicy->Dev == 0x1c){
+ TFun = gAmiTbtPlatformPolicy->Fun;
+ } else {
+ TBus = gAmiTbtPlatformPolicy->Bus;
+ TDev = gAmiTbtPlatformPolicy->Dev;
+ TFun = gAmiTbtPlatformPolicy->Fun;
+ }
+ }
+ TRACE((-1, "TbtDxe: PciDevice @B:%x|D:%x|F:%x !!!\n", PciDevice->Address.Addr.Bus, PciDevice->Address.Addr.Device, PciDevice->Address.Addr.Function));
+#if defined TBT_PCIBUS_SKIP && TBT_PCIBUS_SKIP == 1
+ while ((PciDevice->Type != tPciRootBrg) && (PciDevice->ParentBrg != NULL)) {
+ PciDevice = PciDevice->ParentBrg;
+ if (PciDevice->Address.Addr.Bus != TBus) continue;
+ if (PciDevice->Address.Addr.Device != TDev) continue;
+ if (PciDevice->Address.Addr.Function != TFun) continue;
+
+ TRACE((-1, "TbtDxe: Skip thunderbolt device before PCI BUS assign resource.\n"));
+ return EFI_SUCCESS;
+ }
+#endif
+
+ return EFI_UNSUPPORTED;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: TbtDxeInvokeSmiHandler
+//
+// Description: Invoke SW SMI befor boot for reaource adjust.
+//
+// Input: None
+//
+// Output: None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID TbtDxeInvokeSmiHandler(){
+ AMI_TBT_PLATFORM_POLICY_PROTOCOL *gAmiTbtPlatformPolicy = NULL;
+ EFI_GUID gOemTbtProtocolGuid = AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID;
+ EFI_STATUS Status;
+
+ TRACE((-1, "TbtDxe: TbtDxeInvokeSmiHandler\n"));
+ Status = pBS->LocateProtocol( &gOemTbtProtocolGuid, \
+ NULL, \
+ &gAmiTbtPlatformPolicy);
+ if ((!EFI_ERROR(Status)) && (gAmiTbtPlatformPolicy->TbtEnable)){
+ IoWrite8 (SW_SMI_IO_ADDRESS, TBT_SWSMI_VALUE); //trigger SwSMI for Thunderbolt
+ }
+}
+
+#if defined ULT_SUPPORT && ULT_SUPPORT == 1
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: IsULTPchSeries
+//
+// Description: This function is to get PCH series is ULT series or not
+//
+// Input: None
+//
+// Output: None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+BOOLEAN
+IsULTPchSeries( VOID ){
+ UINT16 PchDeviceId;
+
+ PchDeviceId = MmPciRead16 (0x00, LPC_DEVICE, LPC_FUNC, 0x02);
+ switch(PchDeviceId){
+ case 0x9C40: ///< LynxPoint LP Unfuse
+ case 0x9C41: ///< LynxPoint LP Mobile Super SKU
+ case 0x9C42: ///< LynxPoint LP Mobile TBD SKU
+ case 0x9C43: ///< LynxPoint LP Mobile Premium SKU
+ case 0x9C44: ///< LynxPoint LP Mobile TBD SKU
+ case 0x9C45: ///< LynxPoint LP Mobile Mainstream SKU
+ case 0x9C46: ///< LynxPoint LP Mobile TBD SKU
+ case 0x9C47: ///< LynxPoint LP Mobile Value SKU
+ case 0x9CC1: ///< WildcatPoint LP Mobile Super SKU HSW
+ case 0x9CC2: ///< WildcatPoint LP Mobile Super SKU BDW U
+ case 0x9CC3: ///< WildcatPoint LP Mobile Premium SKU BDW U
+ case 0x9CC4: ///< WildcatPoint LP Mobile TBD SKU
+ case 0x9CC5: ///< WildcatPoint LP Mobile Base SKU BDW U
+ case 0x9CC6: ///< WildcatPoint LP Mobile Super SKU BDW Y
+ case 0x9CC7: ///< WildcatPoint LP Mobile Premium SKU BDW Y
+ case 0x9CC8: ///< WildcatPoint LP Mobile TBD SKU
+ case 0x9CC9: ///< WildcatPoint LP Mobile Base SKU BDW Y
+ case 0x9CCA: ///< WildcatPoint LP Mobile TBD SKU
+ case 0x9CCB: ///< WildcatPoint LP Mobile Performance SKU
+ return TRUE;
+ }
+ return FALSE;
+}
+#endif
+
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtDxe/TbtDxeLib.h b/Board/EM/Thunderbolt/TbtDxe/TbtDxeLib.h
new file mode 100644
index 0000000..a1dbaa0
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtDxe/TbtDxeLib.h
@@ -0,0 +1,74 @@
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
+//*************************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtDxeLib.h 2 6/21/13 7:41a Barretlin $
+//
+// $Revision: 2 $
+//
+// $Date: 6/21/13 7:41a $
+//*************************************************************************
+// Revision History
+// ----------------
+//
+//*************************************************************************
+#include <Efi.h>
+#include <token.h>
+#include <AmiLib.h>
+#include <AmiDxeLib.h>
+#include <AmiCspLib.h>
+
+#ifndef __TBTDXELIB_H__
+#define __TBTDXELIB_H__
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined TBT_INTEL_RC_CONFIG && TBT_INTEL_RC_CONFIG == 1
+EFI_STATUS TbtProtectedPciDevice
+(
+ IN PCI_DEV_INFO *PciDevice
+);
+#endif
+
+VOID TbtDxeInvokeSmiHandler();
+
+#if defined ULT_SUPPORT && ULT_SUPPORT == 1
+BOOLEAN
+IsULTPchSeries
+(
+ VOID
+);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtDxe/TbtGpe.asl b/Board/EM/Thunderbolt/TbtDxe/TbtGpe.asl
new file mode 100644
index 0000000..ad17b9f
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtDxe/TbtGpe.asl
@@ -0,0 +1,797 @@
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
+//*************************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtGpe.asl 22 5/19/14 7:32a Barretlin $
+//
+// $Revision: 22 $
+//
+// $Date: 5/19/14 7:32a $
+//*************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtGpe.asl $
+//
+// 22 5/19/14 7:32a Barretlin
+// [TAG] EIP165410
+// [Category] New Feature
+// [Description] Support Thunderbolt AIC at NB PCIE slot
+// [Files] TbtPei.c TbtDxe.c TbtGpe.asl TbtSmm.c TbtOemBoard.c
+// TbtOemLib.c TbtOemLib.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// TbtSetupReset.c
+//
+// 21 5/19/14 7:13a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Using setup item choose return value of _RMV method in
+// ASL code
+// [Files] TbtDxe.c TbtGpe.asl TbtOemBoard.c TbtOemBoard.h TbtSetup.sd
+// TbtSetup.sdl TbtSetup.uni
+//
+// 20 2/22/14 5:50p Barretlin
+// [TAG] EIP N/A
+// [Category] Bug Fix
+// [Severity] Important
+// [Symptom] For Cactus Ridge host the thunderbolt hotplug event cannot
+// be trigger
+// [RootCause] signal event is not trigger under _INI/TINI method cause
+// OS will not set GPE event enable bit
+// [Solution] Change signal event location of _INI/TINI method
+// [Files] TbtGpe.asl
+//
+// 19 2/18/14 12:07p Barretlin
+//
+// 18 2/18/14 6:02a Barretlin
+// [TAG] EIP152401
+// [Category] Spec Update
+// [Severity] Minor
+// [Description] Update Intel Thunderbolt Sample code rev 1.9
+// [Files] TbtSmm.c TbtGpe.asl TbtOemPorting.asl
+//
+// 17 1/05/14 1:43p Barretlin
+// [TAG] EIP N/A
+// [Category] New Feature
+// [Description] Support Thunderbolt feature Enable/Disable in run time
+// Support dynamic Thunderbolt AIC location in run time
+// [Files] TbtDxe.c TbtGpe.asl
+//
+// 16 7/26/13 2:24a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] remove non Intel RC config
+// [Files] TbtGpe.asl
+//
+// 15 6/21/13 7:41a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Fix build error with non Intel RC project
+// [Files] TbtDxe.sdl TbtDxe.c TbtGpe.asl TbtDxeLib.h
+//
+// 14 6/19/13 9:24a Barretlin
+// [TAG] EIP126581
+// [Category] Spec Update
+// [Severity] Minor
+// [Description] Update Intel Thunderbolt sample code to rev. 1.7
+// [Files] TbtGpe.asl
+//
+// 13 5/27/13 8:57a Barretlin
+// [TAG] EIP124914
+// [Category] New Feature
+// [Description] Support Falcon Ridge chip
+// [Files] TbtGpe.asl
+//
+// 12 5/27/13 8:54a Barretlin
+// [TAG] EIP122882
+// [Category] Bug Fix
+// [Severity] Normal
+// [Symptom] let system entering sleep status continually and waking up
+// system via Thunderbolt Lan device, system will auto-wake
+// [RootCause] PCIE PME status is not cleared by ASL in SB module
+// [Solution] Clear PCIE PME status againg before system entring sleep
+// status
+// [Files] TbtDxe.sdl TbtGpe.asl
+//
+// 11 5/27/13 8:46a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] add sychronized method to make sure executed sequence
+// is one by one
+// [Files] TbtGpe.asl
+//
+// 10 4/12/13 1:18p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Rollback OSUP method and following Intel sample code
+// [Files] TbtGpe.asl
+//
+// 9 4/10/13 2:31p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Change reported MMIO address way in ASL code
+// [Files] TbtDxe.c TbtGpe.asl
+//
+// 8 4/10/13 1:37p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Adding a TPTS method into _PTS method in ASL code
+// [Files] TbtDxe.sdl TbtGpe.asl
+//
+// 7 4/03/13 8:42a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Fix might hang up when S3 resuming
+// [Files] TbtGpe.asl
+//
+// 6 3/21/13 4:58a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Use token to decide where location of OS_UP command for
+// RR chip is
+// [Files] TbtDxe.sdl TbtGpe.asl
+//
+// 5 2/08/13 1:23a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Following Intel sample code move _INI method of
+// thunderbolt from under PCIE root port to under system bus
+// [Files] TbtDxe.sdl TbtGpe.asl
+//
+// 4 2/06/13 7:49a Barretlin
+// [TAG] EIP114556
+// [Category] Spec Update
+// [Severity] Minor
+// [Description] Update RR handshake flow for Thunderbolt RR Spec 0.9
+// [Files] TbtGpe.asl
+//
+// 3 1/24/13 1:31a Barretlin
+// [TAG] EIP N/A
+// [Category] Bug Fix
+// [Severity] Minor
+// [Symptom] TBT debug setup item function fail
+// [RootCause] ASL updating error
+// [Files] TbtGpe.asl
+//
+// 2 1/18/13 2:26a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Improve _RMV ASL code for SharkBay RC
+// [Files] TbtDxe.sdl TbtDxe.c TbtGpe.asl
+//
+// 1 1/10/13 4:56a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+//
+// 6 12/12/12 3:02a Barretlin
+// [TAG] EIP108272
+// [Category] Spec Update
+// [Severity] Important
+// [Description] Update to Spec 1.4 to support Redwood Ridge chip
+// [Files] TbtPei.c TbtSmm.c TbtDxe.c TbtDxe.sdl TbtGpe.asl
+// TbtOemBoard.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+//
+// 5 10/28/12 10:50p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Change GPIO routing for SharkBay ULT platform
+// [Files] TbtDxe.c TbtGpe.asl TbtDxeLib.c TbtDxeLib.h TbtSmm.c
+//
+// 4 5/07/12 6:34a Barretlin
+// [TAG] None
+// [Category] Improvement
+// [Description] Add three setup items for debug
+// [Files] TbtDxe.c
+// TbtGpe.asl
+// TbtSmm.c
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtOemBoard.c
+// TbtOemBoard.h
+//
+// 3 4/16/12 10:17a Barretlin
+// [TAG] EIP86590
+// [Category] Bug Fix
+// [Symptom] Only EP#1 can be detected after resume from S3
+// [Solution] Adding a TWAK method into _WAK method
+// [Files] TbtDxe.sdl TbtGpe.asl
+//
+// 2 4/14/12 4:50a Barretlin
+// [TAG] None
+// [Category] Improvement
+// [Description] Improve ASL code, which redefines device name and RMV
+// mothod at same address when project supports RMV method, that might
+// cause conflict.
+// [Files] TbtDxe.c TbtGpe.asl
+//
+// 1 12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+//
+//*************************************************************************
+Scope(\)
+{
+ Mutex(OSUM, 0) // OS Up mutex
+ Event(WFEV)
+// Name(TBTE, 0) // Thunderbolt function enable
+ Name(PEMA, ASL_PCIEX_BASE_ADDRESS) // PCIE base address
+ Name(TBRP, ASL_TBT_RPNum) // PCIE root port location for Thunderbolt Host
+ Name(TBUS, 0xFF) // Thunderbolt Host BUS number
+ Name(TBHR, 0xFF) //1:Cactus Ridge 2:Redwood Ridge 3:Falcon Ridge 4:Win Ridge will be updated
+ Name(TBMV, 0xFF) // _RMV return value for Thunderbolt
+ Name(RPR6, 0)
+ Name(RPR7, 0)
+ Name(RPR8, 0)
+ Name(RPR9, 0)
+ Name(RPRA, 0)
+ Name(RPRB, 0)
+}
+
+Scope(\_SB)
+{
+ // Include OEM porting required ASL
+ Include("..\\TbtOemBoard\\TbtOemPorting.asl")
+
+ // WMI ACPI device to control TBT force power
+ Device(WMTF)
+ {
+ // pnp0c14 is pnp id assigned to WMI mapper
+ Name(_HID, "PNP0C14")
+ Name(_UID, "TBFP")
+
+ Name(_WDG, Buffer() {
+ // {86CCFD48-205E-4A77-9C48-2021CBEDE341}
+ 0x48, 0xFD, 0xCC, 0x86,
+ 0x5E, 0x20,
+ 0x77, 0x4A,
+ 0x9C, 0x48,
+ 0x20, 0x21, 0xCB, 0xED, 0xE3, 0x41,
+ 84, 70, // Object Id (TF)
+ 1, // Instance Count
+ 0x02 // Flags (WMIACPI_REGFLAG_METHOD)
+ })
+
+ // Set TBT force power
+ // Arg2 is force power value
+ Method(WMTF, 3)
+ {
+ CreateByteField(Arg2,0,FP)
+
+ If(FP)
+ {
+ TBFP(1)
+ }
+ Else
+ {
+ TBFP(0)
+ }
+ }
+ }
+}
+
+Scope(\_GPE)
+{
+ // OSUP method apply TB2P<->P2TB handshake procedure
+ // with Command = OS_Up
+ // Arg0 - Memory mapped IO address of RR host router upstream port
+ Method(OSUP, 1)
+ {
+ Add(Arg0, 0x548, Local0)
+ OperationRegion(PXVD,SystemMemory,Local0,0x08)
+ Field(PXVD,DWordAcc, NoLock, Preserve)
+ {
+ TB2P, 32,
+ P2TB, 32
+ }
+
+ Store(100, Local1)
+ Store(0x0D, P2TB) // Write (OS_Up << 1) | 1 to PCIe2TBT
+ While(LGreater(Local1, 0))
+ {
+ Store(Subtract(Local1, 1), Local1)
+ Store(TB2P, Local2)
+ If(LEqual(Local2, 0xFFFFFFFF))// Device gone
+ {
+ Return(2)
+ }
+ If(And(Local2, 1)) // Done
+ {
+ break
+ }
+ Sleep(50)
+ }
+ Store(0x00, P2TB) // Write 0 to PCIe2TBT
+ Return(1)
+ }
+
+ Method(MMRP)
+ {
+ // Calculate Memory mapped IO address of RR host router PCIE root port
+ // And put it into XXXXX
+
+ Store(\PEMA, Local0)
+ If(LLessEqual(ToInteger(TBRP), 0x08)) // SB PCIE root port
+ {
+ Add(Local0, 0xE0000, Local0) // RP01
+ Subtract(ToInteger(\TBRP), 1, Local1)
+ Multiply(Local1, 0x1000, Local1)
+ Add(Local0, Local1, Local0) //RP0x
+ }
+ Else // NB PCIE root port
+ {
+ Add(Local0, 0x8000, Local0) //PEG0
+ Subtract(ToInteger(\TBRP), 0x20, Local1)
+ Multiply(Local1, 0x1000, Local1)
+ Add(Local0, Local1, Local0)
+ }
+ Return(Local0)
+ }
+
+ // Calculate Memory mapped IO address of RR host router upstream port
+ Method(MMTB)
+ {
+ // Calculate Memory mapped IO address of RR host router upstream port
+ // And put it into XXXXX
+
+ Store(MMRP(), Local0)
+ OperationRegion(MMMM, SystemMemory, Local0, 0x1A)
+ Field(MMMM, AnyAcc, NoLock, Preserve)
+ {
+ Offset(0x19),
+ SBUS, 8
+ }
+
+ Store(SBUS, Local2)
+ Store(\PEMA, Local0)
+ Multiply(Local2, 0x100000, Local2)
+ Add(Local0, Local2, Local0) //TBT HR US port MMIO address
+ Return(Local0)
+ }
+
+ Method(GDRP)
+ {
+ // Put TBT PCIE root port to D0 state
+
+ Store(MMRP(), Local0)
+ OperationRegion(RP_X, SystemMemory, Local0, 0x100)
+ Field(RP_X, AnyAcc, NoLock, Preserve)
+ {
+ Offset(0x84),
+ NBPS, 2, // Power State of PEG slot
+ Offset(0xA4),
+ PSD3, 2 // Power State of SB PCIE slot
+ }
+ If(LLess(TBRP, 0x20)){
+ Store(0, PSD3)
+ Return (PSD3)
+ }
+ If(LGreaterEqual(TBRP, 0x20)){
+ Store(0, NBPS)
+ Return (NBPS)
+ }
+ }
+
+ Method(RPDX, 1)
+ {
+ // Change TBT PCIE root port Power state via Arg0
+ // Arg0 - 0: D0 Status
+ // 3: D3 Status
+
+ Store(MMRP(), Local0)
+ OperationRegion(RP_X, SystemMemory, Local0, 0x100)
+ Field(RP_X, AnyAcc, NoLock, Preserve)
+ {
+ Offset(0x84),
+ NBPS, 2, // Power State of PEG slot
+ Offset(0xA4),
+ PSD3, 2
+ }
+ If(LLess(TBRP, 0x20)){
+ Store(Arg0, PSD3)
+ Sleep(100)
+ }
+ If(LGreaterEqual(TBRP, 0x20)){
+ Store(Arg0, NBPS)
+ Sleep(100)
+ }
+ }
+
+ Method(TBAC)
+ {
+ // Equal Intel BIOS method TSUB and WSUB
+
+ Acquire(OSUM, 0xFFFF)
+ Store(MMRP(), Local0)
+ OperationRegion(RP_X, SystemMemory, Local0, 0x100)
+ Field(RP_X, AnyAcc, NoLock, Preserve)
+ {
+ Offset(0x08),
+ RDCC, 32,
+ Offset(0x18),
+ PBUS, 8,
+ SBUS, 8,
+ SUBS, 8,
+ Offset(0x84),
+ NBPS, 2, // Power State of PEG slot
+ Offset(0xA4),
+ PSD3, 2
+ }
+ Store(0, Local1)
+ While(1)
+ {
+ If(LAnd(LNotEqual(RDCC, 0xFFFFFFFF), LNotEqual(SBUS, 0xFF)))
+ {
+ If(LAnd(LLess(TBRP, 0x20), LEqual(PSD3, 0x0))){
+ Break
+ }
+ If(LAnd(LGreaterEqual(TBRP, 0x20), LEqual(PSD3, 0x0))){
+ Break
+ }
+ }
+ Else
+ {
+ Add(Local1, 0x01, Local1)
+ If(LGreater(Local1, 0x03E8))
+ {
+ P8XH(1,0x7B)
+ P8XH(0,0xAC)
+ Sleep(0x3E8)
+ Break
+ }
+ Else
+ {
+ Sleep(0x10)
+ }
+ }
+ }
+ Release(OSUM)
+ }
+
+ Method(NTFY)
+ {
+ // Intel Chipset Sample code Notify Method
+ Sleep(100)
+ Switch(ToInteger(TBRP)) // TBT Selector
+ {
+ Case (1)
+ {
+ Notify(\_SB.PCI0.RP01,0)
+ }
+ Case (2)
+ {
+ Notify(\_SB.PCI0.RP02,0)
+ }
+ Case (3)
+ {
+ Notify(\_SB.PCI0.RP03,0)
+ }
+ Case (4)
+ {
+ Notify(\_SB.PCI0.RP04,0)
+ }
+ Case (5)
+ {
+ Notify(\_SB.PCI0.RP05,0)
+ }
+ Case (6)
+ {
+ Notify(\_SB.PCI0.RP06,0)
+ }
+ Case (7)
+ {
+ Notify(\_SB.PCI0.RP07,0)
+ }
+ Case (8)
+ {
+ Notify(\_SB.PCI0.RP08,0)
+ }
+ Case (0x20)
+ {
+ Notify(\_SB.PCI0.PEG0,0)
+ }
+ Case (0x21)
+ {
+ Notify(\_SB.PCI0.PEG1,0)
+ }
+ Case (0x22)
+ {
+ Notify(\_SB.PCI0.PEG2,0)
+ }
+ }
+ }
+
+ // Check for 0xFFFFFFFF in TBT Vendor/Device ID
+ // And Call OSUP if true
+ Method(TBFF)
+ {
+ // Get mapped IO address of RR host router upstream port
+ Store(MMTB(), Local0)
+ OperationRegion(PXVD,SystemMemory,Local0,0x4)
+ Field(PXVD,DWordAcc, NoLock, Preserve)
+ {
+ VEDI, 32 // Vendor/Device ID
+ }
+
+ //Check Vendor/Device ID for 0xFFFFFFFF
+ Store(VEDI, Local1)
+ If(LEqual(Local1, 0xFFFFFFFF))
+ {
+ Return (OSUP(Local0))
+ }
+ Else
+ {
+ Return (0)
+ }
+ }
+
+ Method(OE1X)
+ {
+ Name(TSNE, 0xFF) //will be updated by setup menu
+
+ If(LLess(OSYS,2009)) { Return() } // only support win7 or above OS
+
+ Wait(WFEV, 0xFFFF)
+ Signal(WFEV)
+ TBAC()
+ Acquire(OSUM, 0xFFFF)
+ If(LNotEqual(\TBHR, 0x01))// For Redwood Ridge/Falcon Ridge
+ {
+ Store(TBFF(), Local0)
+ If(LEqual(Local0, 1))// Only HR
+ {
+ Sleep(16)
+ Release(OSUM)
+ Return ()
+ }
+ If(LEqual(Local0, 2)) // Disconnect
+ {
+ If(And(TSNE, 0x02)) // If notification is enabled call Notify
+ {
+ Sleep(16)
+ NTFY()
+ }
+ P8XH(0,0x7D)
+ Release(OSUM)
+ Return ()
+ }
+ }
+
+ If(And(TSNE, 0x01))
+ {
+ Store(TBSW, SSMP)
+ }
+ If(And(TSNE, 0x02))
+ {
+ NTFY()
+ }
+ Sleep(16)
+ Release(OSUM)
+ }
+}
+
+#if defined (ASL_TBT_RMV_REPORT) && (ASL_TBT_RMV_REPORT == 1)
+Scope (ASL_TBT_RP_NUM.PXSX)
+{
+ Method(_RMV)
+ {
+ Return(TBMV)
+ } // end _RMV
+}
+#endif
+
+Scope (ASL_TBT_RP_NUM)
+{
+#if defined ASL_TBT_PCI0_INI_SUPPORT && ASL_TBT_PCI0_INI_SUPPORT == 1
+ Method(TINI,0)
+#else
+ Method(_INI,0)
+#endif
+ {
+ If(LLess(OSYS,2009)) { Return() } // only support win7 or above OS
+
+ If(LAnd(LNotEqual(\TBHR, 0xFF), LNotEqual(\TBHR, 0x01)))// For Redwood Ridge/Falcon Ridge
+ {
+ Acquire(OSUM, 0xFFFF)
+ P8XH(0, 0x51) // for debug
+/*
+ Store(MMRP(), Local1)
+ OperationRegion(RP_X, SystemMemory, Local1, 0x20)
+ Field(RP_X, DWordAcc, NoLock, Preserve)
+ {
+ REG0, 32,
+ REG1, 32,
+ REG2, 32,
+ REG3, 32,
+ REG4, 32,
+ REG5, 32,
+ REG6, 32,
+ REG7, 32,
+ }
+ Store(REG6, Local2)
+ Store(0x00F0F000, REG6)
+*/
+ \_GPE.TBAC()
+ // Get memory mapped IO address of RR host router upstream port
+ Store(\_GPE.MMTB(), Local3)
+ // Call OSUP
+ \_GPE.OSUP(Local3)
+ Release(OSUM)
+ }
+ Signal(WFEV)
+ }
+
+#if defined(ASL_TBT_WAK_SUPPORT) && (ASL_TBT_WAK_SUPPORT==1)
+ Method(TWAK, 1)
+ {
+ Name(RPL1, 0)
+ Name(RPL6, 0)
+ Name(RPL7, 0)
+ Name(RPL8, 0)
+ Name(RPL9, 0)
+ Name(RPLA, 0)
+ Name(RPLB, 0)
+
+ If(LLess(OSYS,2009)) { Return() } // only support win7 or above OS
+
+ If(LAnd(LNotEqual(\TBHR, 0xFF), LNotEqual(\TBHR, 0x01)))// Only for Redwood Ridge/Falcon Ridge
+ {
+ Acquire(OSUM, 0xFFFF)
+ \_GPE.TBAC()
+ //Sleep(50) // fix hang up when S3 resuming
+ // Get memory mapped IO address of RR host router upstream port
+ Store(\_GPE.MMRP(), Local0)
+ OperationRegion(RP_X, SystemMemory, Local0, 0x34)
+ Field(RP_X, DWordAcc, NoLock, Preserve)
+ {
+ REG0, 32,
+ REG1, 32,
+ REG2, 32,
+ REG3, 32,
+ REG4, 32,
+ REG5, 32,
+ REG6, 32,
+ REG7, 32,
+ REG8, 32,
+ REG9, 32,
+ REGA, 32,
+ REGB, 32,
+ REGC, 32,
+ }
+ Store(REG1, RPL1)
+ Store(REG6, RPL6)
+ Store(REG7, RPL7)
+ Store(REG8, RPL8)
+ Store(REG9, RPL9)
+ Store(REGA, RPLA)
+ Store(REGB, RPLB)
+ Store(RPR6, REG6)
+ Store(RPR7, REG7)
+ Store(RPR8, REG8)
+ Store(RPR9, REG9)
+ Store(RPRA, REGA)
+ Store(RPRB, REGB)
+ Store(0x00100007, REG1)
+ Store(\_GPE.GDRP(), Local2)
+ \_GPE.RPDX(Zero)
+ Store(\_GPE.MMTB(), Local3)
+ // Call OSUP
+ \_GPE.OSUP(Local3)
+ // Restore TBT root port resource/bus/cmd/D state registers as before Sx entry
+ Store(TBSW, SSMP)
+ // Restore original register values as before calling SMI
+ Store(RPL1, REG1)
+ Store(RPL6, REG6)
+ Store(RPL7, REG7)
+ Store(RPL8, REG8)
+ Store(RPL9, REG9)
+ Store(RPLA, REGA)
+ Store(RPLB, REGB)
+ \_GPE.RPDX(Local2)
+ Release(OSUM)
+
+ // For TBT host at NB PCIE slot
+ If(LGreaterEqual(ToInteger(TBRP), 0x20))
+ {
+ Switch(ToInteger(TBRP))
+ {
+ Case (0x20)
+ {
+ Notify(\_SB.PCI0.PEG0,0)
+ }
+ Case (0x21)
+ {
+ Notify(\_SB.PCI0.PEG1,0)
+ }
+ Case (0x22)
+ {
+ Notify(\_SB.PCI0.PEG2,0)
+ }
+ }
+ }
+ }
+
+#if defined(ASL_TBT_S3_WAK_SMI) && (ASL_TBT_S3_WAK_SMI == 1) && (ASL_TBT_WAK_SUPPORT == 1)
+ Store(Arg0,Local0)
+ If(LEqual(Local0, 0x03)){
+ If(ASL_TBT_RP_NUM.PDSX){
+ Store(TBSW, SSMP)
+ NTFY()
+ }
+ }
+#endif
+ Signal(WFEV)
+ }
+#endif
+
+#if defined(ASL_TBT_PTS_SUPPORT) && (ASL_TBT_PTS_SUPPORT==1)
+ Method(TPTS, 1)
+ {
+ If(LLess(OSYS,2009)) { Return() } // only support win7 or above OS
+
+ If(LAnd(LNotEqual(\TBHR, 0xFF), LNotEqual(\TBHR, 0x01)))// Only for Redwood Ridge/Falcon Ridge
+ {
+ Acquire(OSUM, 0xFFFF)
+ Store(\_GPE.MMRP(), Local0)
+ OperationRegion(RP_X, SystemMemory, Local0, 0x34)
+ Field(RP_X, DWordAcc, NoLock, Preserve)
+ {
+ REG0, 32,
+ REG1, 32,
+ REG2, 32,
+ REG3, 32,
+ REG4, 32,
+ REG5, 32,
+ REG6, 32,
+ REG7, 32,
+ REG8, 32,
+ REG9, 32,
+ REGA, 32,
+ REGB, 32,
+ REGC, 32,
+ }
+ Store(REG6, RPR6)
+ Store(REG7, RPR7)
+ Store(REG8, RPR8)
+ Store(REG9, RPR9)
+ Store(REGA, RPRA)
+ Store(REGB, RPRB)
+ Release(OSUM)
+ }
+#if defined(ASL_TBT_CLEAR_PME_STATUS) && (ASL_TBT_CLEAR_PME_STATUS == 1)
+ If(LOr(PSPX, PMEP)){
+ Store(PMEX, Local1)
+ Store(0, PMEX)
+ Sleep(10)
+ Store(1, PSPX)
+ Sleep(10)
+ If(PSPX){
+ Store(1, PSPX)
+ Sleep(10)
+ }
+ Store(Local1, PMEX)
+ }
+#endif
+ Reset(WFEV)
+ }
+#endif
+}
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
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