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| author | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
|---|---|---|
| committer | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
| commit | b7c51c9cf4864df6aabb99a1ae843becd577237c (patch) | |
| tree | eebe9b0d0ca03062955223097e57da84dd618b9a /Board/SB/Sb.ssp | |
| download | zprj-b7c51c9cf4864df6aabb99a1ae843becd577237c.tar.xz | |
Diffstat (limited to 'Board/SB/Sb.ssp')
| -rw-r--r-- | Board/SB/Sb.ssp | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/Board/SB/Sb.ssp b/Board/SB/Sb.ssp new file mode 100644 index 0000000..3b006ae --- /dev/null +++ b/Board/SB/Sb.ssp @@ -0,0 +1,79 @@ +// This AMI Setup Script Processor (SSP) file contains setup items that +// are related to the CMOS Manager. +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/Sb.ssp 1 2/08/12 8:23a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:23a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/Sb.ssp $ +// +// 1 2/08/12 8:23a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* + +//--------------------------------------------------------------------------- +// CMOS manager starts auto-assigning at 0x40 +// +// This is a typical CMOS usage arrangement. +// (Note: these locations are not currently reserverd by default.) +//--------------------------------------------------------------------------- +// +// 0x00..0x3F Legacy CMOS area, used by CSM +// 0x40..0x7F OEM/ODM +// 0x80..0xBF Chipset +// 0xC0..0xFF Core+Technologies +// +// This is the format of a CMOS token defintion: +//--------------------------------------------------------------------------- +// NvramField (TOKEN_NAME) +// OptionBits = integer // how many bits to use +// [Default = integer] // assembler format "xxxh" +// [CheckSum = YES | NO] // include=YES | exclude=NO +// [Location = cmos address, clobber mask] // CMOS register, size/offset +// EndNvramField + + +//----------------------------------------------------------------- +// TODO: Check if all 8 bits are needed for each of these locations +//----------------------------------------------------------------- + +NvramField (SB_SSP_NMI_CONTROL_BITS) + OptionBits = 8 + Default = 00h + CheckSum = NO + Location = MKF_SB_CMOS_MISC_FLAG_REG, 003h +EndNvramField + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + |