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| author | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
|---|---|---|
| committer | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
| commit | b7c51c9cf4864df6aabb99a1ae843becd577237c (patch) | |
| tree | eebe9b0d0ca03062955223097e57da84dd618b9a /Chipset/eM | |
| download | zprj-master.tar.xz | |
Diffstat (limited to 'Chipset/eM')
29 files changed, 8308 insertions, 0 deletions
diff --git a/Chipset/eM/Ahci/AHCI.EQU b/Chipset/eM/Ahci/AHCI.EQU new file mode 100644 index 0000000..3bfe5a4 --- /dev/null +++ b/Chipset/eM/Ahci/AHCI.EQU @@ -0,0 +1,583 @@ +; TITLE AHCI.EQU - Equates and structures +;**************************************************************************** +;**************************************************************************** +;** ** +;** (C)Copyright 1985-2011, American Megatrends, Inc. ** +;** ** +;** All Rights Reserved. ** +;** ** +;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +;** ** +;** Phone (770)-246-8600 ** +;** ** +;**************************************************************************** +;**************************************************************************** + +;**************************************************************************** +; $Header: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AHCI.EQU 3 2/10/11 10:52a Rameshr $ +; +; $Revision: 3 $ +; +; $Date: 2/10/11 10:52a $ +; +;**************************************************************************** +; Revision History +; ---------------- +; $Log: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AHCI.EQU $ +; +; 3 2/10/11 10:52a Rameshr +; [TAG] EIP53704 +; [Category] Improvement +; [Description] AMI headers update for Alaska Ahci Driver +; [Files] AHCIACC.ASM +; HACCESS.EQU +; AHCI.EQU +; AINT13.EQU +; AInt13Csp.c +; +; 2 5/28/08 9:44a Rameshraju +; Updated the AMI Address. +; +; 1 12/07/07 11:17a Olegi +; +; 6 1/29/07 1:25a Iminglin +; +; 5 11/09/06 3:55a Iminglin +; Make code generic. +; +; 4 10/24/06 11:25p Iminglin +; Stylization. +; +; 3 9/13/06 1:58a Iminglin +; Issue Freeze Lock Command. +; +; 2 9/28/05 5:40a Iminglin +; Update for CDROM. +; +; 1 6/09/05 11:29p Iminglin +; Initialized version +; +; 1 5/20/05 2:37a Iminglin +; Intel AHCI source +; +;**************************************************************************** +; +;************************************************************************; +;* *; +;* Intel(r) Restricted Secret *; +;* *; +;* Support for and Booting from SATA devices in AHCI mode *; +;* *; +;* Enterprise Software Technology *; +;* *; +;* Copyright (c) 2003-2005 Intel Corporation *; +;* *; +;* Version iSrc03x *; +;* *; +;* This information is provided in connection with Intel products. *; +;* No license, express or implied, by estoppel or otherwise, to *; +;* any intellectual property rights is granted by this information *; +;* or by the sale of Intel products. Except as provided in Intel's *; +;* Terms and Conditions of Sale for such products, Intel assumes *; +;* no liability whatsoever, and Intel disclaims any express or *; +;* implied warranty, relating to sale and/or use of Intel products *; +;* including liability or warranties relating to fitness for a *; +;* particular purpose, merchantability, or infringement of any *; +;* patent, copyright or other intellectual property right. Intel *; +;* products are not intended for use in medical, life saving, or *; +;* life sustaining applications. *; +;* Intel retains the right to make changes to specifications and *; +;* product descriptions at any time, without notice and may choose *; +;* to develop product based on these designs. *; +;* *; +;* *Third-party brands and names are the property of their *; +;* respective owners. *; +;* *; +;************************************************************************; +;* *; +;* REFERENCES *; +;* *; +;* Revision Title *; +;* ==================================================================== *; +;* 1.0 Serial ATA Advanced Host Controller Interface (AHCI) *; +;* *; +;************************************************************************; +; +;;;;;;;;;;;; Specification related equates and structures ;;;;;;;;;;;;;;;; +;------------------------------------------------------------------------- +; Maximum #of ports supported by each SATA controller +; +MAX_PORT_NUM equ 20h ; Max #of SATA Ports per SATA Controller +; +;------------------------------------------------------------------------- +; SATA Controller Information Table +; 1. Contains the AHCI related data for the device +; 2. Built during POST +; 3. Each device has its own table +; +INFO_CONTROLLER_STRUC struc + wBusDevFunc dw ? ; Bus#, Dev#, Func# + dHbaBaseAddr dd ? ; HBA Base Address + bIrq db ? ; IRQ used + dHbaCap dd ? ; HBA Capabilities (dCAP field) + dBitPortImp dd ? ; Bit-mapped info of port implemented (dPI field) +INFO_CONTROLLER_STRUC ends +; +;------------------------------------------------------------------------- +; Generic Host Control registers +; +GENERAL_HOST_OFFSET equ 0000h ; Offset of start of Generic Host Control Registers from AHCI Base +; +GENERAL_HOST_STRUC struc + dCAP dd ? ; HBA Capabilities (see below for details) + dGHC dd ? ; Global HBA Control (see below for details) + dIS dd ? ; Interrupt Status Register (see below for details) + dPI dd ? ; Ports Implemented (see below for details) + dVS dd ? ; AHCI Version (see below for details) +GENERAL_HOST_STRUC ends +; +; Details of dCAP field +; +dCAP_NP_MASK equ 1Fh shl 0 ; Bit4-0 = max #of ports (0-based) supported +dCAP_NCS_MASK equ 1Fh shl 8 ; Bit12-8 = #of command slots (0-based) supported +dCAP_PSC equ 1 shl 13 ; Bit-13 = Partial State Capable +dCAP_SSC equ 1 shl 14 ; Bit-14 = Slumber State Capable +dCAP_PMD equ 1 shl 15 ; Bit-15 = PIO Multiple DRQ Block +dCAP_SPM equ 1 shl 17 ; Bit-17 = Supports Port Multiplier +dCAP_SAM equ 1 shl 18 ; Bit-18 = Supports AHCI Mode only +dCAP_SNZO equ 1 shl 19 ; Bit-19 = Supports Non-Zero DMA offsets +dCAP_ISS_MASK equ 0Fh shl 20; Bit23-20 = Interface Speed Support + ISS_1P5_GBPS equ 0001b ; 1.5 Gbps + ISS_1P5_3_GBPS equ 0010b ; 1.5 Gbps and 3 Gbps +dCAP_SCLO equ 1 shl 24 ; Bit-24 = Supports Command List Override +dCAP_SAL equ 1 shl 25 ; Bit-25 = Supports Activity LED +dCAP_SALP equ 1 shl 26 ; Bit-26 = Supports Aggresive Link Power Management +dCAP_SSS equ 1 shl 27 ; Bit-27 = Supports Staggered Spin-Up +dCAP_SIS equ 1 shl 28 ; Bit-28 = Supports Interlock Switch +dCAP_SNCQ equ 1 shl 30 ; Bit-30 = Supports Native Command Queuing +dCAP_S64A equ 1 shl 31 ; Bit-31 = Supports 64-bit Addressing +; +; Details of dGHC field +; +dGHC_HR equ 1 shl 0 ; Bit-0 = HBA Reset +dGHC_IE equ 1 shl 1 ; Bit-1 = Interrupt Enable +dGHC_AE equ 1 shl 31 ; Bit-31 = AHCI Enable +; +; Details of dIS field +; A particular bit, if set to 1, indicates that the corresponding port has an +; interrupt pending. Only ports, that are implemented, have a corresponding +; valid bit; all other bits are reserved. +; +; Details of dPI field +; A particular bit, if set to 1, indicates that the corresponding port is +; available for use. If set to 0, the corresponding port is not available. +; The maximum number of bits that are set to 1, shall not exceed the value +; of (dCap_NP_MASK + 1). At least one bit must be set to 1. +; +; Details of dVS field +; +dVS_MINOR equ 0FFFFh shl 0 ; Bit15-0 = Minor Version +dVS_MAJOR equ 0FFFFh shl 16 ; Bit31-16 = Major Version +; +;------------------------------------------------------------------------- +; Port registers +; +PORT_REGISTER_START equ 100h ; Port registers start at offset 100h from AHCI base +PORT_REGISTER_SET_SIZE equ 80h ; Each port registers set is 128bytes +PORT_REGISTER_SET_SIZE_N equ 07h ; #of bits to be shifted left +; +; Thus Port-N registers set starts at following offset from AHCI base +; PORT_REGISTER_START + (N * 80h) +; i.e. PORT_REGISTER_START + (N << 07h) +; +PORT_REG_STRUC struc + dPCLB dd ? ; Port Command List Base Address (lower 32bit) + dPCLBU dd ? ; Port Command List Base Address (upper 32bit) + dPFB dd ? ; Port FIS Base Address (lower 32bit) + dPFBU dd ? ; Port FIS Base Address (upper 32bit) + dPIS dd ? ; Port Interrupt Status (see below for details) + dPIE dd ? ; Port Interrupt Enable (see below for details) + dPCMD dd ? ; Port Command (see below for details) + dReserved dd ? ; Reserved + dPTFD dd ? ; Port Task File Data (see below for details) + dPSIG dd ? ; Port Signature (see below for details) + dPSSTS dd ? ; Port Serial ATA Status (see below for details) + dPSCTL dd ? ; Port Serial ATA Control (see below for details) + dPSERR dd ? ; Port Serial ATA Error (see below for details) + dPSACT dd ? ; Port Serial ATA Active + dPCI dd ? ; Port Command Issue +PORT_REG_STRUC ends +; +; Details of dPIS field +; +dPIS_DHRS equ 1 shl 0 ; Bit-0 = Device to Host Register FIS Interrupt +dPIS_PSS equ 1 shl 1 ; Bit-1 = PIO Setup FIS Interrupt +dPIS_DSS equ 1 shl 2 ; Bit-2 = DMA Setup FIS Interrupt +dPIS_SDBS equ 1 shl 3 ; Bit-3 = Set Device Bits Interrupt +dPIS_UFS equ 1 shl 4 ; Bit-4 = Unknown FIS Interrupt +dPIS_DPS equ 1 shl 5 ; Bit-5 = Descriptor Processed +dPIS_PCS equ 1 shl 6 ; Bit-6 = Port Connect Change Status +dPIS_DIS equ 1 shl 7 ; Bit-7 = Device Interlock Status + ; Bit21-8..Reserved +dPIS_PRCS equ 1 shl 22; Bit-22 = PhyRdy Change Status +dPIS_IPMS equ 1 shl 23; Bit-23 = Incorrect Port Multiplier Status +dPIS_OFS equ 1 shl 24; Bit-24 = Overflow Status +dPIS_INFS equ 1 shl 26; Bit-26 = Interface Non-Fatal Error Status +dPIS_IFS equ 1 shl 27; Bit-27 = Interface Fatal Error Status +dPIS_HBDS equ 1 shl 28; Bit-28 = Host Bus Data Error Status +dPIS_HBFS equ 1 shl 29; Bit-29 = Host Bus Fatal Error Status +dPIS_TFES equ 1 shl 30; Bit-30 = Task File Error Status +dPIS_CPDS equ 1 shl 31; Bit-31 = Cold Port Detect Status +; +; Details of dPIE field +; +dPIE_DHRE equ 1 shl 0 ; Bit-0 = Device to Host Register FIS Interrupt Enable +dPIE_PSE equ 1 shl 1 ; Bit-1 = PIO Setup FIS Interrupt Enable +dPIE_DSE equ 1 shl 2 ; Bit-2 = DMA Setup FIS Interrupt Enable +dPIE_SDBE equ 1 shl 3 ; Bit-3 = Set Device Bits Interrupt Enable +dPIE_UFE equ 1 shl 4 ; Bit-4 = Unknown FIS Interrupt Enable +dPIE_DPE equ 1 shl 5 ; Bit-5 = Descriptor Processed Interrupt Enable +dPIE_PCE equ 1 shl 6 ; Bit-6 = Port Connect Change Interrupt Enable +dPIE_DIE equ 1 shl 7 ; Bit-7 = Device Interlock Interrupt Enable + ; Bit21-8..Reserved +dPIE_PRCE equ 1 shl 22; Bit-22 = PhyRdy Change Interrupt Enable +dPIE_IPME equ 1 shl 23; Bit-23 = Incorrect Port Multiplier Interrupt Enable +dPIE_OFE equ 1 shl 24; Bit-24 = Overflow Interrupt Enable +dPIE_INFE equ 1 shl 26; Bit-26 = Interface Non-Fatal Error Interrupt Enable +dPIE_IFE equ 1 shl 27; Bit-27 = Interface Fatal Error Interrupt Enable +dPIE_HBDE equ 1 shl 28; Bit-28 = Host Bus Data Error Interrupt Enable +dPIE_HBFE equ 1 shl 29; Bit-29 = Host Bus Fatal Error Interrupt Enable +dPIE_TFEE equ 1 shl 30; Bit-30 = Task File Error Interrupt Enable +dPIE_CPDE equ 1 shl 31; Bit-31 = Cold Port Detect Interrupt Enable +; +; Details of dPCMD field +; +dPCMD_ST equ 1 shl 0 ; Bit-0 = Start process command list + PxCMD_ST0_AND_MASK equ 0FFFFFFFEh; AND Mask to set PxCMD.ST = 0 + PxCMD_ST0_OR_MASK equ 000000000h; OR Mask to set PxCMD.ST = 0 +dPCMD_SUD equ 1 shl 1 ; Bit-1 = Spin-Up Device +dPCMD_POD equ 1 shl 2 ; Bit-2 = Power On Device +dPCMD_CLO equ 1 shl 3 ; Bit-3 = Command List Override +dPCMD_FRE equ 1 shl 4 ; Bit-4 = FIS Receive Enable +; ; Bit7-5....Reserved +dPCMD_CCS_MASK equ 1Fh shl 8 ; Bit12-8 = Current Command Slot +dPCMD_ISS equ 1 shl 13; Bit-13 = Interlock Switch State +dPCMD_FR equ 1 shl 14; Bit-14 = FIS Receive Running +dPCMD_CR equ 1 shl 15; Bit-15 = Command List Running +dPCMD_CPS equ 1 shl 16; Bit-16 = Cold Presence State +dPCMD_PMA equ 1 shl 17; Bit-17 = Port Multiplier Attached +dPCMD_HPCP equ 1 shl 18; Bit-18 = Hot Plug Capable Port +dPCMD_ISP equ 1 shl 19; Bit-19 = Interlock Switch Attached to Port +dPCMD_CPD equ 1 shl 20; Bit-20 = Cold Presence Detect + ; Bit23-21..Reserved +dPCMD_ATAPI equ 1 shl 24; Bit-24 = Device is ATAPI +dPCMD_DLAE equ 1 shl 25; Bit-25 = Drive LED on ATAPI Enable +dPCMD_ALPE equ 1 shl 26; Bit-26 = Aggressive Link Power Management Enable +dPCMD_ASP equ 1 shl 27; Bit-27 = Aggressive Slumber/Partial +dPCMD_ICC_MASK equ 0Fh shl 28; Bit31-28= Interface Communication Control +dPCMD_ICC_MASK_ALIGN equ 28 ; #of bits to be shifted for Interface Communication Control alignment + ICC_NOP_IDLE equ 00h ; HBA ready to accept new interface control command + ICC_ACTIVE equ 01h ; Active + ICC_PARTIAL equ 02h ; Partial + ICC_SLUMBER equ 06h ; Slumber State +; +; +; Details of dPTFD field +; +dPTFD_STS_MASK equ 0FFh shl 0 ; Bit7-0 = Copy of Task File Status Register + dPTFD_STS_ERR equ 1 shl 0 ; Bit-0 = Error + ; Bit2-1...Not applicable + dPTFD_STS_DRQ equ 1 shl 3 ; Bit-3 = Data Xfer Requested + ; Bit5-4...Not applicable + dPTFD_STS_DRDY equ 1 shl 6 ; Bit-6 = Device is ready + dPTFD_STS_BSY equ 1 shl 7 ; Bit-7 = Interface is busy +dPTFD_ERR_MASK equ 0FFh shl 8 ; Bit15-8= Copy of Task File Error Register +; +; Details of dPSIG field +; Contains the signature received from the device on first D2H register FIS. It +; is updated once after a reset sequence. +; Bit7-0 = Sector Count Register +; Bit15-8 = LBA Low Register +; Bit23-16 = LBA Mid Register +; Bit31-24 = LBA High Register +; +; Details of dPSSTS field +; +dPSSTS_DET_MASK equ 0Fh shl 0 ; Bit3-0 = Device Detection + dPSSTS_DET_DEVICE_MASK equ 01h ; Bit-0 = 1, Device Detected + DET_NO_DEVICE_AND_NO_PHY_COMM equ 00h ; No device detected and no Phy communication + DET_DEVICE_BUT_NO_PHY_COMM equ 01h ; Device detected but no Phy communication + DET_DEVICE_AND_PHY_COMM equ 03h ; Device detected and Phy communication + DET_PHY_OFF_LINE equ 04h ; Phy in offline mode +dPSSTS_SPD_MASK equ 0Fh shl 4 ; Bit7-4 = Current Interface Speed + SPD_NO_DEVICE_OR_NO_COMM equ 00h ; No device present or no communication + SPD_GEN_1_COMM equ 01h ; Generation 1 communication rate + SPD_GEN_2_COMM equ 02h ; Generation 2 communication rate +dPSSTS_IPM_MASK equ 0Fh shl 8 ; Bit11-8 = Current Interface State + IPM_NO_DEVICE_OR_NO_COMM equ 00h ; No device present or no communication + IPM_ACTIVE equ 03h ; Interface in Active state(v1.07) + IPM_PARTIAL equ 02h ; Interface in Partial power management state + IPM_SLUMBER equ 01h ; Interface in Slumber power management state(v1.07) +; +; Details of dPSCTL field +; +dPSCTL_DET_MASK equ 0Fh shl 0 ; Bit3-0 = Device Detection Initialization + DET_NO_DET_AND_NO_INIT equ 00h ; No detection or initialization requested + DET_COMM_INIT equ 01h ; Perform Interface communication initialization + DET_DISABLE_SATA equ 04h ; Disable SATA interface and put Phy in offline mode +dPSCTL_SPD_MASK equ 0Fh shl 4 ; Bit7-4 = Speed Allowed + SPD_NO_RESTRICTION equ 00h ; No speed negotiation restriction + SPD_LIMIT_TO_GEN1 equ 01h ; Limit speed negotiation to Gen 1 rate + SPD_LIMIT_TO_GEN2 equ 02h ; Limit speed negotiation to a rate + ; not greater than Gen 2 rate +dPSCTL_IPM_MASK equ 0Fh shl 8 ; Bit11-8 = Interface Power Management Transition Allowed +dPSCTL_IPM_MASK_ALIGN equ 8 ; #of bits to be shifted for Interface Power Management Transition alignment + IPM_NO_RESTRICTION equ 00h ; No interface restriction + IPM_PARTIAL_DISABLED equ 01h ; Transition to Partial state disabled + IPM_SLUMBER_DISABLED equ 02h ; Transition to Slumber state disabled + IPM_PARTIAL_SLUMBER_DISABLED equ 03h ; Transition to both Partial and Slumber states disabled + +dPSCTL_SPM_MASK equ 0Fh shl 12; Bit15-12 = The Select Power Management +dPSCTL_SPM_MASK_ALIGN equ 12 ; #of bits to be shifted for Select Power Management alignment + SPM_NO_TRANSITION equ 00h ; No power management state transition + SPM_PARTIAL_INITIATED equ 01h ; Transition to Partial state initiated + SPM_SLUMBER_INITIATED equ 02h ; Transition to Slumber state initiated + SPM_ACTIVE_INITIATED equ 04h ; Transition to the active power management states initiated + +dPSCTL_PMP_MASK equ 0Fh shl 16; Bit19-16 = The Port Multiplier field +dPSCTL_PMP_MASK_ALIGN equ 16 ; #of bits to be shifted for Port Multiplier alignment + PMP_CONTROL_PORT equ 0Fh ; Control port # of Port Multiplier +; +; Details of dPSERR field +; +dPSERR_ERR_MASK equ 0FFFFh shl 0; Bit15-0= Error + dPSERR_ERR_I equ 1 shl 0 ; Bit-0 = Recovered Data Integrity Error + dPSERR_ERR_M equ 1 shl 1 ; Bit-1 = Recovered Communications Error + ; Bit7-2.......Reserved + dPSERR_ERR_T equ 1 shl 8 ; Bit-8 = Transient Data Integrity Error + dPSERR_ERR_C equ 1 shl 9 ; Bit-9 = Persistent Communication or Data Integrity Error + dPSERR_ERR_P equ 1 shl 10; Bit-10 = Protocol Error + dPSERR_ERR_E equ 1 shl 11; Bit-11 = Master or Target Abort + ; Bit15-12.....Reserved +dPSERR_DIAG_MASK equ 0FFFFh shl 16; Bit31-16 = Diagnostics + dPSERR_DIAG_N equ 1 shl 16; Bit-16 = PhyRdy Change + dPSERR_DIAG_I equ 1 shl 17; Bit-17 = Phy Internal Error + dPSERR_DIAG_W equ 1 shl 18; Bit-18 = Comm Wake + dPSERR_DIAG_B equ 1 shl 19; Bit-19 = 10B to 8B Decode Error + dPSERR_DIAG_D equ 1 shl 20; Bit-20 = Disparity Error + dPSERR_DIAG_C equ 1 shl 21; Bit-21 = CRC Error + dPSERR_DIAG_H equ 1 shl 22; Bit-22 = Handshake Error + dPSERR_DIAG_S equ 1 shl 23; Bit-23 = Link Sequence Error + dPSERR_DIAG_T equ 1 shl 24; Bit-24 = Transport State Transition Error + dPSERR_DIAG_F equ 1 shl 25; Bit-25 = Unknown FIS Type + dPSERR_DIAG_X equ 1 shl 26; Bit-26 = Exchanged + ; Bit31-27.....Reserved +; +;------------------------------------------------------------------------- +; +; Command List Structure +; +COMMAND_LIST_STRUC struc + dDW0 dd ? ; Description Information (details below) + dPRDBC dd ? ; Physical Region Descriptor Byte Count + dCTBA dd ? ; Command Table Base Address (lower 32bit) + dCTBAU dd ? ; Command Table Base Address (upper 32bit) + dReserved1 dd ? ; Reserved dword + dReserved2 dd ? ; Reserved dword + dReserved3 dd ? ; Reserved dword + dReserved4 dd ? ; Reserved dword +COMMAND_LIST_STRUC ends +; +; Details of dDW0 field +; +dDW0_CFL_MASK equ 1Fh shl 0 ; Bit4-0 = Command FIS Length (1-based) in #of DWords +dDW0_ATAPI equ 1 shl 5 ; Bit-5 = ATAPI +dDW0_WRITE equ 1 shl 6 ; Bit-6 = Direction of data transfer + ; 0 = Device Read (data from device to host) + ; 1 = Device Write (data from host to device) +dDW0_PREFETCHABLE equ 1 shl 7 ; Bit-7 = Prefetchable +dDW0_RESET equ 1 shl 8 ; Bit-8 = Device Reset +dDW0_BIST equ 1 shl 9 ; Bit-9 = BIST +dDW0_CLEAR_BSY equ 1 shl 10; Bit-10 = Clear Busy after xmitting FIS and receiving R_OK + ; Bit-11....Reserved +dDW0_PMP_MASK equ 0Fh shl 12; Bit15-12= Port multiplier number to be used + +dDW0_PRDTL_N equ 16 ; Bit-16 = Start bit of PRDTL +dDW0_PRDTL_MASK equ 0FFFFh shl 16;Bit31-16= Physical Region Descriptor Table Length + ; in #of entries, each entry is 4 DWords +;------------------------------------------------------------------------- +; Command Table +; +COMMAND_TABLE_STRUC struc + aCFIS db 40h dup (?) ; Area for command FIS + aACMD db 10h dup (?) ; Area for ATAPI command + aReserved db 30h dup (?) ; Reserbed area + aPRDT db ? ; Start of Physical Region Descriptor Tables +COMMAND_TABLE_STRUC ends +; +;------------------------------------------------------------------------- +; PRDT: Physical Region Descriptor Table +; +PRDT_STRUC struc + dDBA dd ? ; Data Base Address (lower 32bit) + dDBAU dd ? ; Data Base Address (upper 32bit) + dReserved dd ? ; Reserved + dDW3 dd ? ; Description Information (details below) +PRDT_STRUC ends +; +; Details of dDW3 field +; +dDW3_DBC_MASK equ 3FFFFFh shl 0; Bit21-0 = Data Byte Count (0-based) + ; Bit30-22...Reserved +dDW3_INTERRUPT equ 1 shl 31; Bit-31 = Generate interrupt when data is xferred +; +;------------------------------------------------------------------------- +; FIS: Frame Information Structure +; +; FIS Types and size in #of dwords +H2D_REGISTER_FIS_TYPE equ 27h + H2D_REGISTER_FIS_LENGTH_DWORD equ 05h +D2H_REGISTER_FIS_TYPE equ 34h + D2H_REGISTER_FIS_LENGTH_DWORD equ 05h +DMA_SETUP_FIS_TYPE equ 41h + DMA_SETUP_FIS_LENGTH_DWORD equ 07h +BIST_ACTIVATE_FIS_TYPE equ 58h + BIST_ACTIVATE_FIS_LENGTH_DWORD equ 03h +PIO_SETUP_FIS_TYPE equ 5Fh + PIO_SETUP_FIS_LENGTH_DWORD equ 05h +SET_DEVICE_BITS_FIS_TYPE equ 0A1h + SET_DEVICE_BITS_FIS_LENGTH_DWORD equ 02h +ACMD_FIELD_LENGTH_DWORD equ 03h ;(V1.07+) +; +H2D_REGISTER_FIS_STRUC struc + bFisType db ? ; FIS Type + bXferReason db ? ; Cause of transfer + COMMAND_REGISTER_UPDATE equ 80h; Bit-7 = 1, xfer is due to an update of command register + ; Bit6-0=....Reserved + bCommand db ? ; Command + bFeatures db ? ; Features + bSectorNumber db ? ; Sector Number + bCylinderLow db ? ; Cylinder Low + bCylinderHigh db ? ; Cylinder High + bDeviceHead db ? ; Device Head + bSectorNumberExp db ? ; Sector Number Exp + bCylinderLowExp db ? ; Cylinder Low Exp + bCylinderHighExp db ? ; Cylinder High Exp + bFeaturesExp db ? ; Features Exp + bSectorCount db ? ; Sector Count + bSectorCountExp db ? ; Sector Count Exp + bReserved1 db ? ; Reserved + bControl db ? ; Control + bReserved2 db ? ; Reserved + bReserved3 db ? ; Reserved + bReserved4 db ? ; Reserved + bReserved5 db ? ; Reserved +H2D_REGISTER_FIS_STRUC ends +; +D2H_REGISTER_FIS_STRUC struc + bFisType db ? ; FIS Type + bDeviceInterruptLine db ? ; Interrupt line of device + INTERRUPT_BIT equ 40h ; Bit-6 = it reflects interrupt bit line of the device + bStatus db ? ; Status + bError db ? ; Error + bSectorNumber db ? ; Sector Number + bCylinderLow db ? ; Cylinder Low + bCylinderHigh db ? ; Cylinder High + bDeviceHead db ? ; Device Head + bSectorNumberExp db ? ; Sector Number Exp + bCylinderLowExp db ? ; Cylinder Low Exp + bCylinderHighExp db ? ; Cylinder High Exp + bReserved1 db ? ; Features Exp + bSectorCount db ? ; Sector Count + bSectorCountExp db ? ; Sector Count Exp + bReserved2 db ? ; Reserved + bReserved3 db ? ; Control + bReserved4 db ? ; Reserved + bReserved5 db ? ; Reserved + bReserved6 db ? ; Reserved + bReserved7 db ? ; Reserved +D2H_REGISTER_FIS_STRUC ends +; +DMA_SETUP_FIS_STRUC struc + bFisType db ? ; FIS Type + bXferDirnAndInt db ? ; Xfer direction and interrupt + XFER_D2H equ 20h ; Bit-5 = 1, D2H xfer + XFER_H2D equ 00h ; 0, H2D xfer + INTERRUPT_PENDING equ 40h ; Bit-6 = interrupt pending + bReserved1 db ? ; Reserved + bReserved2 db ? ; Reserved + dDmaBufferIdentifierLow dd ? ; DMA Buffer Identifier Low + dDmaBufferIdentifierHigh dd ? ; DMA Buffer Identifier High + dReserved3 dd ? ; Reserved + dDmaBufferOffset dd ? ; DMA Buffer offset + dDmaXferCount dd ? ; DMA Transfer Count in bytes + dReserved4 dd ? ; Reserved +DMA_SETUP_FIS_STRUC ends +; +BIST_ACTIVATE_FIS_STRUC struc + bFisType db ? ; FIS Type + bReserved1 db ? ; Reserved + bPattern db ? ; Pattern Definition + bReserved2 db ? ; Reserved + dData1 dd ? ; Data1 + dData2 dd ? ; Data2 +BIST_ACTIVATE_FIS_STRUC ends +; +PIO_SETUP_FIS_STRUC struc + bFisType db ? ; FIS Type + bXferDirnAndInt db ? ; Xfer direction and interrupt + ; (bit defintions same as DMA_SETUP_FIS) + bStatus db ? ; Status + bError db ? ; Error + bSectorNumber db ? ; Sector Number + bCylinderLow db ? ; Cylinder Low + bCylinderHigh db ? ; Cylinder High + bDeviceHead db ? ; Device Head + bSectorNumberExp db ? ; Sector Number Exp + bCylinderLowExp db ? ; Cylinder Low Exp + bCylinderHighExp db ? ; Cylinder High Exp + bReserved1 db ? ; Reserved + bSectorCount db ? ; Sector Count + bSectorCountExp db ? ; Sector Count Exp + bReserved2 db ? ; Reserved + bE_Status db ? ; Status + wXferCount dw ? ; Xfer count in bytes + wReserved dw ? ; Reserved +PIO_SETUP_FIS_STRUC ends +; +SET_DEVICE_BITS_FIS_STRUC struc + bFisType db ? ; FIS Type + bFlags db ? ; Information flags + bStatus db ? ; Status + bError db ? ; Error + dReserved dd ? ; Reserved +SET_DEVICE_BITS_FIS_STRUC ends +; +; Receive FIS structure +FIS_RECEIVE_STRUC struc + aDSFIS DMA_SETUP_FIS_STRUC {?} ; DMA Setup FIS + bReserved1 db 04h dup (?) ; Reserved + aPSFIS PIO_SETUP_FIS_STRUC {?} ; PIO Setup FIS + bReserved2 db 0Ch dup (?) ; Reserved + aRFIS D2H_REGISTER_FIS_STRUC {?} ; D2H Register FIS + bReserved3 db 04h dup (?) ; Reserved + aSDBFIS SET_DEVICE_BITS_FIS_STRUC {?} ; Set Device Bits FIS + aUFIS db 40h dup (?) ; Unknown FIS + bReserved4 db 60h dup (?) ; Reserved +FIS_RECEIVE_STRUC ends +; +;------------------------------------------------------------------------- +;**************************************************************************** +;**************************************************************************** +;** ** +;** (C)Copyright 1985-2011, American Megatrends, Inc. ** +;** ** +;** All Rights Reserved. ** +;** ** +;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +;** ** +;** Phone (770)-246-8600 ** +;** ** +;**************************************************************************** +;**************************************************************************** + diff --git a/Chipset/eM/Ahci/AHCIACC.ASM b/Chipset/eM/Ahci/AHCIACC.ASM new file mode 100644 index 0000000..1f93536 --- /dev/null +++ b/Chipset/eM/Ahci/AHCIACC.ASM @@ -0,0 +1,1181 @@ + + TITLE AHCIACC.ASM - AHCI Register/Memory Acccess Routines + +;**************************************************************************** +;**************************************************************************** +;** ** +;** (C)Copyright 1985-2014, American Megatrends, Inc. ** +;** ** +;** All Rights Reserved. ** +;** ** +;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +;** ** +;** Phone (770)-246-8600 ** +;** ** +;**************************************************************************** +;**************************************************************************** + +;**************************************************************************** +; $Header: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AHCIACC.ASM 14 12/08/14 5:58a Anbuprakashp $ +; +; $Revision: 14 $ +; +; $Date: 12/08/14 5:58a $ +;**************************************************************************** +; Revision History +; ---------------- +; $Log: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AHCIACC.ASM $ +; +; 14 12/08/14 5:58a Anbuprakashp +; [TAG] EIP192297 +; [Category] Improvement +; [Description] Replacing SmmGetMemoryType usage in AHCI driver with +; AmiBufferValidationLib +; [Files] AhciInt13Smm.c, AhciInt13Smm.mak, AHCIACC.ASM +; +; 13 11/24/14 11:54p Kapilporwal +; [TAG] EIP191939 +; [Category] Improvement +; [Description] Issue about BIG_REAL_MODE_MMIO_ACCESS of AHCI module +; [Files] AI13.bin +; AHCIACC.ASM +; AhciInt13Dxe.c +; AhciInt13Dxe.dxs +; AhciInt13Smm.c +; AhciInt13Smm.cif +; AhciInt13Smm.dxs +; AhciInt13Smm.h +; AhciInt13Smm.mak +; AhciInt13Smm.sdl +; AInt13.c +; Aint13.cif +; AInt13.h +; AhciSmm.c +; AhciSmm.h +; AhciSmmProtocol.h +; +; 12 7/01/14 2:23a Nagadineshk +; [TAG] EIP172162 +; [Category] Bug Fix +; [Severity] Important +; [Symptom] Can't install legacy windows if achiacc.obj is not first +; one of CSM_OEM16_OBJS elink +; [RootCause] Wrong offset of Newly Hooked Interrupt(CPU Exception +; Interrupt) address loaded in Interrupt vector table. +; [Solution] Stored Correct Offset value in IVT +; [Files] AHCIACC.ASM +; +; 11 6/20/14 6:54a Nimishsv +; Recheck-in +; +; 10 12/17/13 7:06a Nimishsv +; [TAG] EIP131322 +; [Category] Improvement +; [Description] Improve S4 resume time with PCIE SSD +; under Win7, reported that if enable AHCIMMIOSMM_SUPPORT, +; and then S4 resume time is very long(about 50s) with win 7. +; (Add support for accessing MMIO region using BIG real mode) +; [Files] AhciMmioSmm.sdl, AHCIACC.asm +; +; 9 8/02/12 8:14a Deepthins +; [TAG] EIP93480 +; [Category] Bug Fix +; [Symptom] AHCI legacy support module is corrupting the memory. +; [RootCause] AHCI legacy support module is corrupting the memory as it +; was using wrong offset for storing the base address. +; [Solution] Properly calculating offset for storing the base address. +; [Files] AINT13.EQU, AInt13.c, AInt13.h and AHCIACC.ASM +; +; 8 1/13/12 12:20a Deepthins +; [TAG] EIP78099 +; [Category] Improvement +; [Description] Handle multiple AHCI controller in legacy. +; [Files] Aint13.sdl , AInt13.c , AInt13.h , AHCIACC.ASM , AHCI.EQU , +; AINT13.bin (AHCIACC.ASM , AINT13.EQU) +; +; 7 2/10/11 10:52a Rameshr +; [TAG] EIP53704 +; [Category] Improvement +; [Description] AMI headers update for Alaska Ahci Driver +; [Files] AHCIACC.ASM +; HACCESS.EQU +; AHCI.EQU +; AINT13.EQU +; AInt13Csp.c +; +; 6 6/21/10 5:34a Rameshr +; AHCI Legacy booting through MMIO reg. +; EIP 38444 +; +; 5 5/28/08 9:43a Rameshraju +; Updated the AMI Address. +; +; 4 3/28/08 10:03a Olegi +; +; 3 3/27/08 5:33p Olegi +; +; 2 19/12/07 4:28p Anandakrishnanl +; Modified the relative offsets to be absolute. +; +; 1 12/07/07 11:17a Olegi +; +;**************************************************************************** + +;---------------------------------------------------------------------------- +; INCLUDE FILES +;---------------------------------------------------------------------------- + include ahci.equ + include haccess.equ + include aint13.equ + include token.equ + + FLAT_MODE_INDEX equ 08h + REAL_MODE_INDEX equ 10h +;---------------------------------------------------------------------------- +; EXTERNS USED +;---------------------------------------------------------------------------- +.586p +OEM16_CSEG SEGMENT PARA PUBLIC 'CODE' USE16 + ASSUME cs:OEM16_CSEG, ds:OEM16_CSEG +;------------------------------------------------------------------------- + PUBLIC AhciApiModuleStart +AhciApiModuleStart LABEL BYTE + jmp SHORT AhciCsm16Api + dw AhciDataStart - AhciApiModuleStart + + +;---------------------------------------------------------------------------- +; IMPORTANT: Do not put any OEM/CHIPSET code above this, the above code and +; and data are at fixed locations. +;---------------------------------------------------------------------------- + +;------------------------------------------------------------------------- +; AHCI_CSM16_API_Start +;---------------------------------------------------------------------------- +; This routine is implementation of the CSM16 API #7. +; Input: CX 80h - ReadRegisterDword call +; 00h - WriteRegisterDword call +; 01h - WaitForFisRecRun call +; For read/write functions: +; SS:SP+3Eh (originally ESI) HBA Base Address +; SS:SP+42h (originally EBX) Port#, Register Offset +; Bit31-16 = Port# (0-based) +; FFFF for Generic Host Control Register +; Bit15-0 = Register offset +; SS:SP+46h (originally EAX) Data to be written +; For WaitForFisRecRun function: +; No input +; Output: NC Successful +; EAX Data read +; CY Error +; Register Usage: Do not destroy any register except EAX +; +;---------------------------------------------------------------------------- +; +AhciCsm16Api PROC FAR PUBLIC +; Adjust current IP so that the data offsets are valid + call $+3 ; Push curent IP + pop bx ; Get current IP in BX + shr bx, 4 + mov ax, cs ; Always x000h + add ax, bx ; New CS + push ax + push newOffset-AhciApiModuleStart + retf ; Execute from new CS:IP + +newOffset: + push bp + mov bp, sp + mov eax, ss:[bp+48h] ; Data to be written (ignored for Read function) + mov ebx, ss:[bp+44h] ; Port# + mov esi, ss:[bp+40h] ; HBA Base Address + + cmp cx, 0 + jz aca_WriteCall + cmp cx, 80h + jnz aca_WaitForFisRecRun + call ReadRegisterDword + jmp SHORT aca_Exit +aca_WaitForFisRecRun: + call WaitForFisRecRun + jmp SHORT aca_Exit +aca_WriteCall: + call WriteRegisterDword + +aca_Exit: + pop bp + +; Adjust sp as if we returned to csm16_func_ret + add sp, 4 ; cs:ip of F000:csm16_func_ret + +; Save EAX, restore it after popad + push eax + pop ds + pop gs +;csm16_func_ret: + popad + push gs + push ds + pop eax + + pop gs + pop fs + pop es + pop ds + +;csm16_exit: + popf + pop ds + pop si + + add sp, 2 ; Do not "pop ax", preserving return code + +; Prepare for FAR return - fetch the CS and patch the segment for RETF + mov cx, WORD PTR ss:[bp+1ah] + mov WORD PTR ss:[bp+06h], cx +; Restore CX + mov cx, WORD PTR ss:[bp+18h] + mov dx, WORD PTR ss:[bp+16h] ;Restore Dx + + pop bp + add sp, 4 + clc + retf 18 + +AhciCsm16Api ENDP + +; +;------------------------------------------------------------------------- +; ReadRegisterDword +;---------------------------------------------------------------------------- +; This routine reads the register. +; Input: ESI HBA Base Address +; EBX Port#, Register Offset +; Bit31-16 = Port# (0-based) +; FFFF for Generic Host Control Register +; Bit15-0 = Register offset +; Output: NC Successful +; EAX Data read +; CY Error +; Register Usage: Do not destroy any register except EAX +; +;---------------------------------------------------------------------------- +; +ReadRegisterDword_FAR PROC FAR PUBLIC + call ReadRegisterDword ; EAX = data read if read + ret +ReadRegisterDword_FAR ENDP + +ReadRegisterDword PROC NEAR PUBLIC + push esi + call CalculateRegisterOffset ; ESI = register offset from base + + push dx ; Dx has the controller number + cli + push bx ; Save bx value in stack + push ax ; Save ax value in stack + mov ax, 0 + mov al, dl ; Move the controller no into al + mov bl, 8 + mul bl ; Multiply it with 8 as AHCI_ACCESS\ + ; structure size is 8 + mov bx, ax ; Move the offset into bx + pop ax ; Restore ax +IF (MKF_AHCI_INT13_SMM_SUPPORT) + push ebx + push ecx + mov ebx, dword ptr cs:[AhciDataStart - AhciApiModuleStart +4+bx] ;ebx=Data + add esi,ebx +IF (MKF_BIG_REAL_MODE_MMIO_ACCESS) + call ReadDWORD +ELSE + mov cx,1 ;Read Function + call AhciGenerateSwSMI + cmp ecx, 0 ; if ECX == 0, MMIO read is Success + jz Read_Success + stc + jmp Read_Return +Read_Success: + clc +Read_Return: +ENDIF + pop ecx + pop ebx + jmp Read_done +ENDIF + mov dx, cs:[AhciDataStart - AhciApiModuleStart +bx] ; DX = Index Port + push eax + mov eax, esi ; EAX = register address + out dx, eax ; Write Address + pop eax + + mov dx, cs:[AhciDataStart - AhciApiModuleStart +2+bx] ; DX = Data Port + in eax, dx ; EAX = adat + + clc ; NC, Successful +Read_done: + pop bx + pop dx + + pop esi + ret +ReadRegisterDword ENDP +; +;---------------------------------------------------------------------------- +; WriteRegisterDword +;---------------------------------------------------------------------------- +; This routine writes the register. +; Input: ESI HBA Base Address +; EBX Port#, Register Offset +; Bit31-16 = Port# (0-based) +; FFFF for Generic Host Control Register +; Bit15-0 = Register offset +; EAX Data to be written +; Output: NC Successful +; CY Error +; Register Usage: Do not destroy any register +; +;---------------------------------------------------------------------------- +; +WriteRegisterDword_FAR PROC FAR PUBLIC + call WriteRegisterDword + ret +WriteRegisterDword_FAR ENDP + +WriteRegisterDword PROC NEAR PUBLIC + push esi + call CalculateRegisterOffset ; ESI = register offset from base + + push dx ; Dx has the controller number + cli + push bx ; Save bx value in stack + push ax ; Save ax value in stack + mov ax, 0 + mov al, dl ; Move the controller no into al + mov bl, 8 + mul bl ; Multiply it with 8 as AHCI_ACCESS\ + ; structure size is 8 + mov bx, ax ; Move the offset into bx + pop ax ; Restore ax + +IF (MKF_AHCI_INT13_SMM_SUPPORT) + push ebx + push ecx + mov ebx, dword ptr cs:[AhciDataStart - AhciApiModuleStart +4+bx] + add esi,ebx +IF (MKF_BIG_REAL_MODE_MMIO_ACCESS) + call WriteDWORD +ELSE + mov ebx,eax ;Write Value + mov cx,2 ;Write Function + call AhciGenerateSwSMI + cmp ecx, 0 ; if ECX == 0, MMIO write is Success + jz Write_Success + stc + jmp Write_Return +Write_Success: + clc +Write_Return: +ENDIF + pop ecx + pop ebx + jmp Write_done +ENDIF + mov dx, cs:[AhciDataStart - AhciApiModuleStart +bx] ; DX = Index Port + push eax + mov eax, esi ; EAX = register address + out dx, eax ; Write Address + pop eax + + mov dx, cs:[AhciDataStart - AhciApiModuleStart +2+bx] ; DX = Data Port + out dx, eax ; Write dword data + clc ; NC, Successful +Write_done: + pop bx + pop dx + + pop esi + ret +WriteRegisterDword ENDP +; +;---------------------------------------------------------------------------- +; CalculateRegisterOffset +;---------------------------------------------------------------------------- +; This routine calculates the register offset from HBA Base. +; Input: EBX Port#, Register Offset within Port +; Bit31-16 = Port# (0-based) +; FFFF for Generic Host Control Register +; Bit15-0 = Register offset +; Output: ESI Register Offset from HBA Base +; Register Usage: Do not destroy any register except ESI +; +;---------------------------------------------------------------------------- +; +CalculateRegisterOffset PROC NEAR PRIVATE + push cx + push ebx + mov cx, bx ; CX = register offset + shr ebx, 16 ; BX = Port# (0-based) + inc bx ; Port# valid? + jz short cro_00 ; No + dec bx ; BX = Port# (0-based) + shl bx, PORT_REGISTER_SET_SIZE_N + add bx, PORT_REGISTER_START +cro_00: + add bx, cx ; BX = Port register offset from HBA base address + movzx esi, bx ; ESI = Port register offset from HBA base address + pop ebx + pop cx + ret +CalculateRegisterOffset ENDP + +; +;---------------------------------------------------------------------------- +; WaitForFisRecRun +;---------------------------------------------------------------------------- +; This routine executes HBA wait for FIS rec run code. If not +; implemented (just ret), AHCI INT13 code will execute the default routine. +; Implement this routine for different OEM/Chipset vendor and return 0 in AL +; to override the default routine execution. +; +; Output: AH 0 if implemented +; +;---------------------------------------------------------------------------- +; +WaitForFisRecRun PROC NEAR PUBLIC + ret +WaitForFisRecRun ENDP + +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: AhciGenerateSwSMI +; +; Description: Generate the Sw SMI to read the MMIO space. +; if the system is in big real mode, read/write the MMIO space without +; SwSMI +; +; Input: Cx = 1 - Read MMIO +; Cx= 2 - Write MMIO +; Eax= Value to write in MMIO for write MMIO +; +; Output: Eax- for Read MMIO +; +; Modified: Ds +; +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> +IF (MKF_AHCI_INT13_SMM_SUPPORT) +AhciGenerateSwSMI PROC NEAR PUBLIC + call Check_Big_Real_mode + jc NotBigReadMode + push es + push 0 + pop es + + cmp cx,1 + je ReadMmio + mov dword ptr es:[esi],eax ;Write MMIO + pop es + ret +ReadMmio: + mov eax,dword ptr es:[esi] ;Read MMIO + pop es + ret +NotBigReadMode: + + mov dx,MKF_SW_SMI_IO_ADDRESS + mov al,MKF_AHCI_INT13_SMM_SWSMI_VALUE + out dx,al ;Generate Sw SMI to Read/Write MMIO + jmp $+2 + ret +AhciGenerateSwSMI ENDP + +;------------------------------------------------------------------------- +; ReadDWORD +;------------------------------------------------------------------------- +; This routine reads DWORD from MMIO. +; Input: ESI HBA Base Address +; +; Output: NC Successful +; EAX Data read +; CY Error +; Register Usage: Do not destroy any register except EAX +; +;------------------------------------------------------------------------- +ReadDWORD PROC NEAR PUBLIC + + push ds + + push 0 + pop ds + + push esi + +; Save original values of registers in stack + push ebx + push es + push di + +; Save a dword from 5000h + mov bx, 5000h + mov es, bx + mov di, 00h + mov ebx, dword ptr es:[di] + + push ebx + + mov byte ptr es:[di], 00h +; Switching to Big Real Mode + call Switch_Big_Real_Mode + +; Reading DWORD from Hba_base_address and store in EAX + mov eax, dword ptr ds:[esi] + + push eax + movzx eax, byte ptr es:[di] + and eax, 01h + jz rdw_done +; Switch back from Big Real mode + call Switch_Original_Mode + +rdw_done: + pop eax + + push eax + movzx eax, byte ptr es:[di] + and eax, 10b + jz org_g20 + call DisblGateA20 +org_g20: + pop eax + + pop ebx +; Restore the original values stored in stack + mov dword ptr es:[di], ebx + + pop di + pop es + pop ebx + + pop esi + + pop ds + clc + + ret +ReadDWORD ENDP + +;------------------------------------------------------------------------- +; WriteDWORD +;------------------------------------------------------------------------- +; This routine writes DWORD in MMIO space. +; Input: EAX Data to be written +; +; Output: ESI HBA Base Address +; NC Successful +; CY Error +; +; Register Usage: Do not destroy any register except EAX +; +;------------------------------------------------------------------------- +WriteDWORD PROC NEAR PUBLIC + push ds + + push 0 + pop ds + + push esi + +; Save original values of registers in stack + push ebx + push es + push di + +; Save a dword from 5000h + mov bx, 5000h + mov es, bx + mov di, 00h + mov ebx, dword ptr es:[di] + + push ebx + + mov byte ptr es:[di], 00h +; Switching to Big Real Mode + call Switch_Big_Real_Mode + +; Writing DWORD stored in EAX into Hba_base_address + mov dword ptr ds:[esi],eax + + push eax + movzx eax, byte ptr es:[di] + and eax, 01h + jz wdw_done + +; Switch back from Big Real mode + call Switch_Original_Mode + +wdw_done: + pop eax + + push eax + movzx eax, byte ptr es:[di] + and eax, 10b + jz org_g201 + call DisblGateA20 +org_g201: + pop eax + pop ebx + +; Restore the original values stored in stack + mov dword ptr es:[di], ebx + + pop di + pop es + pop ebx + + pop esi + + pop ds + clc + + ret +WriteDWORD ENDP + +;---------------------------------------------------------------------------- +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: Switch_Big_Real_Mode +; +; Description: Switch to Big real Mode. +; +; Input: None +; +; Output: +; +; Modified: DS, ES +; +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> +;---------------------------------------------------------------------------- +Switch_Big_Real_Mode PROC NEAR PUBLIC + + push di + call Check_Big_Real_mode + jnc InBigRealMode + mov byte ptr es:[di], 01h + +InBigRealMode: + + mov di, FLAT_MODE_INDEX ;Index for flat mode + call GotoProtectedMode + + pop di + ret + +Switch_Big_Real_Mode ENDP + +;---------------------------------------------------------------------------- +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: Switch_Original_Mode +; +; Description: Switch to Original Mode. +; +; Input: None +; +; Output: +; +; Modified: DS, ES +; +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> +;---------------------------------------------------------------------------- +Switch_Original_Mode PROC NEAR PUBLIC + + push di + mov di, REAL_MODE_INDEX ;Real mode index + call GotoProtectedMode + pop di + + ret + +Switch_Original_Mode ENDP + +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: GotoProtectedMode +; +; Description: This function jumps to protected mode for 4GB limit access +; +; Input: None +; +; Output: None +; +; Modified: None +; +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> + +GotoProtectedMode PROC NEAR PUBLIC + push es + pusha + cli ; Disable interrupts. +; Check the GA20 status.. +; Compare 256bytes at 0:0 with FFFF:10 +; If match, GA20 is disabled else GA20 is enabled. + push di + push es + push ds + push 0000h + pop ds ; DS = 0000. + push 0FFFFh + pop es ; ES = FFFF. + mov cx, 100h / 4 ; Number of Dwords in 256bytes. + xor si, si + mov di, 0010h + repz cmpsd + pop ds + pop es + pop di ;Descriptor table index in di + + pushf ; Save GA20 status + ; ZR/NZ = disabled/enabled. + jnz short gtbrm_00 ; GA20 is already enabled. + + push di + mov di, 00h + or byte ptr es:[di], 10b + pop di + call EnblGateA20 ; Enable GateA20. + +gtbrm_00: + call go_big_mode ; Go to protected mode and comeback + ; to real mode. + popf ; ZR/NZ = GA20 status. + stc ; Routine went to big real mode. + +gtbrm_01: + popa + pop es + ret ; Return to caller. +GotoProtectedMode ENDP + +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: EnblGateA20 +; +; Description: This function enables GateA20 +; +; Input: None +; +; Output: None +; +; Modified: None +; +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> + +EnblGateA20 PROC NEAR PUBLIC + + push ax + mov al,02h + out 92h, al + +; Check the GA20 status.. +; Compare 256bytes at 0:0 with FFFF:10 +; If match, GA20 is disabled else GA20 is enabled. + push di + push es + push ds + push 0000h + pop ds ; DS = 0000. + push 0FFFFh + pop es ; ES = FFFF. + mov cx, 100h / 4 ; Number of Dwords in 256bytes. + xor si, si + mov di, 0010h + repz cmpsd + pop ds + pop es + pop di ;Descriptor table index in di + + jnz eg20_end + + mov al, 0DFh ; Data for output port to enable A20. + out 60h, al + mov al, 0D1h + out 64h, al + +eg20_end: + pop ax + + ret +EnblGateA20 ENDP + +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: go_big_mode +; +; Description: This routine goes to protected mode, sets the DS, ES to the +; given selector, comes back to real mode and sets DS, ES to 0000. +; +; Input: DX - Selector. +; +; Output: Selector 00 can be used to access 4GB. +; +; Modified: EAX. +; +; Referrals: big_gdt. +; +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> + +go_big_mode PROC NEAR PRIVATE + + jmp Executable_code + +;<AMI_SHDR_START> +;---------------------------------------------------------------------------- +; Name: big_gdt +; +; Type: BYTE Array +; +; Description: Global Descriptor Table to switch the system to/from FLAT Mode. +; Since these routines will be called from non-shadowed system +; ROM, the GDT must be on a QWORD boundary or else the bytes +; will get CORRUPTED! +; +;---------------------------------------------------------------------------- +;<AMI_SHDR_END> + +ALIGN 8 +big_gdt LABEL WORD + db 8 dup (0) ;00 - Null descriptor + db 0FFh,0FFh,000h,000h,000h,093h,08Fh,000h ; 08h - DS descriptor for flat mode +big_gdt_end LABEL WORD + +big_gdt_real LABEL WORD + db 8 dup (0) ;00 - Null descriptor + db 0FFh,0FFh,000h,000h,000h,093h,000h,000h ; 08h - DS descriptor for real mode +big_gdt_real_end LABEL WORD + +GDT_DESC LABEL BYTE + dw 010h ; Length of GDT + db 00,00h ; ptr to GDT + db 05h,00h +GDT_DESC_END LABEL BYTE + +Executable_code: + + push ds + push es + push eax + push ebx + push ecx + push edx + push si + push di + +; Changed for CSM - need to save SS, reload SS Limit to 64K selector and restore it + push bp + mov bp, ss + + mov al, 8Dh ; Disable NMI + out 70h, al + +;;; Copy contents from 5000:00(16 bytes) into registers + mov ax, 5000h + mov es, ax + mov si, 00h + mov eax, dword ptr es:[si] + add si, 4 + mov ebx, dword ptr es:[si] + add si, 4 + mov ecx, dword ptr es:[si] + add si, 4 + mov edx, dword ptr es:[si] + push eax + push ebx + push ecx + push edx + +;;; Copy GDT to 5000h:00h + mov ax, cs + mov ds, ax + cmp di, 08h + jne gbm_real + mov si, offset cs:big_gdt + jmp gbm_flat +gbm_real: + mov si, offset cs:big_gdt_real +gbm_flat: + mov ax, 5000h + mov es, ax + mov di, 00h + xor cx, cx + mov cx, 08h + rep movsw + + lgdt fword ptr cs:GDT_DESC + mov eax, cr0 + or al, 01h + mov cr0, eax ; In protected mode. + jmp gbm_00 ; Flush instruction queue - JMP (NEAR) + ; to next instruction. + +gbm_00: + mov ax, 08h ; Selector + mov ds, ax ; DS = selector. + mov es, ax ; ES = selector. + + mov eax, cr0 ; Come back into real mode with DS,ES + and al, 0FEh + mov cr0, eax + jmp gbm_01 ; Flush instruction queue - JMP (NEAR) + ; to next instruction. +gbm_01: + + xor ax, ax + mov ds, ax + mov es, ax + + pop edx + pop ecx + pop ebx +;;; Restore contents of 5000:00h(16 bytes) from registers + mov ax, 5000h + mov es, ax + mov si, 00h + pop eax + mov dword ptr es:[si], eax + add si, 4 + mov dword ptr es:[si], ebx + add si, 4 + mov dword ptr es:[si], ecx + add si, 4 + mov dword ptr es:[si], edx + + pop bp + pop di + pop si + pop edx + pop ecx + pop ebx + pop eax + pop es + pop ds + ret +go_big_mode ENDP + +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: DisblGateA20 +; +; Description: This function disables GateA20 +; +; Input: None +; +; Output: None +; +; Modified: None +; +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> + +DisblGateA20 PROC NEAR PUBLIC + + push ax + mov al,00h + out 92h, al + +; Check the GA20 status.. +; Compare 256bytes at 0:0 with FFFF:10 +; If match, GA20 is disabled else GA20 is enabled. + push di + push es + push ds + push 0000h + pop ds ; DS = 0000. + push 0FFFFh + pop es ; ES = FFFF. + mov cx, 100h / 4 ; Number of Dwords in 256bytes. + xor si, si + mov di, 0010h + repz cmpsd + pop ds + pop es + pop di ;Descriptor table index in di + + jz dg20_end + + mov al, 0DDh ; Data for output port to disables A20. + out 60h, al + mov al, 0D1h + out 64h, al + +dg20_end: + pop ax + + ret + +DisblGateA20 ENDP + +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: Get_EBDA +; +; Description: Get the EBDA Segment Address +; +; Input: None +; +; Output: DS: Ebda Segment +; +; Modified: Ds +; +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> +Get_EBDA PROC NEAR PUBLIC + + push 40h + pop ds + mov ds, ds:[0Eh] ; DS - EBDA segment. + ret + +get_EBDA ENDP + +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: Int0DHandler +; +; Description: Exception 0D handler +; +; Input: None +; +; Output: Exception_flag Set +; +; Modified: None +; +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> +Int0DHandler PROC NEAR PUBLIC + push ds + call Get_EBDA + mov byte ptr ds:[102h],1 ;Set the Flag in Ebda:102 + pop ds + pop ax + add ax, 5 ; Go to Next instruction that doesn't + ; cause Exception + push ax + iret +Int0DHandler ENDP + +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: Check_Big_Real_mode +; +; Description: This function checks wheather system is in Big real mode +; +; Input: None +; +; Output: Carry Set - Not in Big Real mode +; Carry Not Set- System is in Big Real mode +; +; Modified: None +; +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> +Check_Big_Real_mode PROC NEAR PUBLIC + push eax + push edi + push ebx + push es + push ds + pushf + cli + + call Get_EBDA + + mov byte ptr ds:[102h],0 ;EBDA:102 + + push 0 + pop es + + mov eax, dword ptr es:[0Dh*4] + push eax + + push cs ; Runtime segment + push offset cs:Int0DHandler-AhciApiModuleStart + pop eax + mov dword ptr es:[0Dh*4], eax + + + mov edi,0100000h + mov eax,dword ptr es:[edi] + cmp byte ptr ds:[102h],1 ;Check the exception + je Real_mode + + mov edi,0 + mov ebx,dword ptr es:[edi] + cmp eax,ebx + je Real_mode + + ;Read ,Write test for above 1Mb area + mov edi,0100000h + mov ebx,dword ptr es:[edi] + mov eax,055AA55AAh + mov dword ptr es:[edi],eax + mov eax,dword ptr es:[edi] + mov dword ptr es:[edi],ebx + cmp eax,055AA55AAh + jne Real_mode + pop eax + mov dword ptr es:[0Dh*4], eax + popf + clc ;System is in Big Real Mode + jmp Exit_Ret + +Real_mode: + pop eax + mov dword ptr es:[0Dh*4], eax + popf + stc ;System is in Real Mode +Exit_Ret: + pop ds + pop es + pop ebx + pop edi + pop eax + ret +Check_Big_Real_mode ENDP + +ENDIF + +AhciDataStart label word +AhciAccess AHCI_ACCESS (MKF_AHCI_CONTROLLER_COUNT) dup (<>) + +OEM16_CSEG ENDS + +END +;**************************************************************************** +;**************************************************************************** +;** ** +;** (C)Copyright 1985-2014, American Megatrends, Inc. ** +;** ** +;** All Rights Reserved. ** +;** ** +;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +;** ** +;** Phone (770)-246-8600 ** +;** ** +;**************************************************************************** +;**************************************************************************** diff --git a/Chipset/eM/Ahci/AINT13.EQU b/Chipset/eM/Ahci/AINT13.EQU new file mode 100644 index 0000000..f51aaf8 --- /dev/null +++ b/Chipset/eM/Ahci/AINT13.EQU @@ -0,0 +1,748 @@ +; TITLE aint13.equ - Equates and structures for AHCI INT13 +;**************************************************************************** +;**************************************************************************** +;** ** +;** (C)Copyright 1985-2011, American Megatrends, Inc. ** +;** ** +;** All Rights Reserved. ** +;** ** +;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +;** ** +;** Phone (770)-246-8600 ** +;** ** +;**************************************************************************** +;**************************************************************************** + +;**************************************************************************** +; $Header: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AINT13.EQU 5 8/02/12 8:17a Deepthins $ +; +; $Revision: 5 $ +; +; $Date: 8/02/12 8:17a $ +; +;**************************************************************************** +; Revision History +; ---------------- +; $Log: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AINT13.EQU $ +; +; 5 8/02/12 8:17a Deepthins +; [TAG] EIP93480 +; [Category] Bug Fix +; [Severity] Normal +; [Symptom] AHCI legacy support module is corrupting the memory. +; [RootCause] AHCI legacy support module is corrupting the memory as it +; was using wrong offset for storing the base address. +; [Solution] Properly calculating offset for storing the base address. +; [Files] AINT13.EQU, AInt13.c, AInt13.h and AHCIACC.ASM +; +; 4 1/13/12 12:21a Deepthins +; [TAG] EIP78099 +; [Category] Improvement +; [Description] Handle multiple AHCI controller in legacy. +; [Files] Aint13.sdl , AInt13.c , AInt13.h , AHCIACC.ASM , AHCI.EQU , +; AINT13.bin (AHCIACC.ASM , AINT13.EQU) +; +; 3 2/10/11 10:52a Rameshr +; [TAG] EIP53704 +; [Category] Improvement +; [Description] AMI headers update for Alaska Ahci Driver +; [Files] AHCIACC.ASM +; HACCESS.EQU +; AHCI.EQU +; AINT13.EQU +; AInt13Csp.c +; +; 2 5/28/08 9:44a Rameshraju +; Updated the AMI Address. +; +; 1 12/07/07 11:17a Olegi +; +; 7 9/20/07 1:41a Davidhsieh +; +; 6 9/11/07 6:54a Chung +; 1. Add Security Function. +; 2. Modify AHCI Code. +; +; 5 6/06/07 2:06a Chung +; Add AHCI HD Mode Information +; +; 4 5/03/07 4:02a Chung +; EIP9321 - Add SMART function for self test. +; +; 2 1/29/07 1:25a Iminglin +; +; 1 1/25/07 1:21a Iminglin +; Changed by James. +; +; 15 12/20/06 2:26a Iminglin +; 1. Prepare Port Multiplier support. +; 2. Display SMART status. +; +; 14 12/05/06 3:15a Iminglin +; Remove useless equates. +; +; 13 11/09/06 3:47a Iminglin +; Make code generic. +; +; 12 10/27/06 4:28a Iminglin +; Rename Int13 function 48 structure. +; +; 11 10/24/06 11:25p Iminglin +; Stylization. +; +; 10 9/13/06 1:58a Iminglin +; Issue Freeze Lock Command. +; +; 9 7/14/06 4:28a Iminglin +; Clearificatoin. +; +; 8 6/01/06 11:25p Iminglin +; Enable SMART function. +; +; 7 5/19/06 2:09a Iminglin +; Intel source v1.00 change. +; +; 6 3/27/06 12:49a Iminglin +; Change Device Path length. +; +; 5 11/10/05 10:32p Iminglin +; Add smart handle. +; +; 4 10/25/05 2:25a Iminglin +; Remove CD structure. +; +; 3 10/20/05 4:35a Iminglin +; Give a solution for byte alignment. +; +; 2 10/05/05 6:57a Iminglin +; CDROM data structure +; +; 1 6/09/05 11:29p Iminglin +; Initialized version +; +; 1 5/20/05 2:37a Iminglin +; Intel AHCI source +; +;**************************************************************************** +; +;************************************************************************; +;* *; +;* Intel(r) Restricted Secret *; +;* *; +;* Support for and Booting from SATA devices in AHCI mode *; +;* *; +;* Enterprise Software Technology *; +;* *; +;* Copyright (c) 2003-2005 Intel Corporation *; +;* *; +;* Version iSrc03x *; +;* *; +;* This information is provided in connection with Intel products. *; +;* No license, express or implied, by estoppel or otherwise, to *; +;* any intellectual property rights is granted by this information *; +;* or by the sale of Intel products. Except as provided in Intel's *; +;* Terms and Conditions of Sale for such products, Intel assumes *; +;* no liability whatsoever, and Intel disclaims any express or *; +;* implied warranty, relating to sale and/or use of Intel products *; +;* including liability or warranties relating to fitness for a *; +;* particular purpose, merchantability, or infringement of any *; +;* patent, copyright or other intellectual property right. Intel *; +;* products are not intended for use in medical, life saving, or *; +;* life sustaining applications. *; +;* Intel retains the right to make changes to specifications and *; +;* product descriptions at any time, without notice and may choose *; +;* to develop product based on these designs. *; +;* *; +;* *Third-party brands and names are the property of their *; +;* respective owners. *; +;* *; +;************************************************************************; +;* *; +;* REFERENCES *; +;* *; +;* Revision Title *; +;* ==================================================================== *; +;* 1.0 Serial ATA Advanced Host Controller Interface (AHCI) *; +;* *; +;************************************************************************; +; +;------------------------------------------------------------------------- +; IMPLEMENTATION RELATED EQUATES AND STRUCTURES +;------------------------------------------------------------------------- +; SATA Device Information Table +; 1. Contains the AHCI related data for the device +; 2. Built during POST +; 3. Each device has its own table +DEV_INFO_STRUC STRUC + bDetectType db ? ;Detected Device Type (Details Below) + bInstalledType db ? ;Device Installed Type (See Below) + wStatus dw ? ;Bit-mapped device Init Status (Details Below) + bInt13Num db ? ;Device# for INT13 (8xh) + bPMNum db ? ;Port Multipier Port # + bPortNum db ? ;SATA Port# (0-Based) where device is present + wBusDevFunc dw ? ;Bus#, Dev#, Func# of Controller + bControllerNo db ? ;Ahci Controller number + dHbaBase dd ? ;HBA Base Address of Generic Host Control Registers + dHbaCap dd ? ;HBA Capabilities + dPortBase dd ? ;Base Address of SATA port where device is present + bSelector db ? ;Device selector value + bIrq db ? ;IRQ used by this device + bInfoFlag db ? ;Information Flag (details below) + bSectorSizeN db ? ;N value of Sector size 2^N + ;For 512bytes sector, N = 9 + wSmartInfo dw ? ;SMART info (details below) + qTotalSectors dq ? ;Total #of sectors in device (1-based) + wXferCount dw ? ;Device transfer count. Used for ATAPI packer size + bBlockInfo db ? + b32BitInfo db ? + bUDMAInfo db ? + bPIOInfo db ? +DEV_INFO_STRUC ENDS + +; Details of bDetectType +DETECT_NO EQU 00h ;Not detected +DETECT_ATA EQU 01h ;device detected is ATA +DETECT_ATAPI_CD EQU 02h ;device detected is ATAPI CDROM +DETECT_ATAPI_ARMD EQU 03h ;device detected is ATAPI ARMD + +; Details of bInstalledType +INSTALLED_NO EQU 00h ;Not installed +INSTALLED_HDD EQU 01h ;device installed as ATA HDD +INSTALLED_CDROM EQU 02h ;device installed as ATAPI CDROM +INSTALLED_ARMD_FDD EQU 03h ;device installed as ATAPI ARMD FDD +INSTALLED_ARMD_HDD EQU 04h ;device installed as ATAPI ARMD HDD + +; Details of wStatus +ST_SUCCESS EQU 0001h ;Bit 0 = 1, successful (device is installed in this case) +ST_ID_DEV_ERR EQU 0002h ;Bit 1 = 1, Identify Device Failed +ST_DEV_GEOMETRY_ERR EQU 0004h ;Bit 2 = 1, Invalid Device Geometry +ST_INIT_DEV_PARAM_ERR EQU 0008h ;Bit 3 = 1, Init device parameter failed +ST_RECALI_ERR EQU 0010h ;Bit 4 = 1, Recalibrate failed +ST_SMART_ERR EQU 0020h ;Bit 5 = 1, SMART failed +ST_VERIFY_ERR EQU 0040h ;Bit 6 = 1, Verify failed +ST_FREEZE_LOCK_ERR EQU 0080h ;Bit 7 = 1, Security Freeze Lock failed +ST_PORT_RESET_ERR EQU 0100h ;Bit 8 = 1, Port Reset failed +ST_SMART_EVENT EQU 0200h ;Bit 9 = 1, SMART Event was found +ST_RAID_SUPPORT_ERR EQU 0400h ;Bit 10 = 1, Device will be supported by RIAD OROM, not AHCI OROM (ex. HDD) + ;Bit 14-11, Reserved for future use +ST_NOT_SUPPORT_ERR EQU 8000h ;Bit 15 = 1, Device not supported + +; Details of bInfoFlag, a bit-mapped field +INFO_REMOVABLE EQU 01h ;Bit 0 = 1, Device supports removable media +INFO_LBA_48 EQU 02h ;Bit 1 = 1, 48bit LBA enabled +INFO_IRQ EQU 04h ;Bit 2 = 1, Device uses IRQ + ; 0, Device uses DRQ + ;Bit 6-2, Reserved +INFO_ATAPI EQU 80h ;Bit 7 = 1, ATAPI Device + ; 0, ATA Device + +; Details wSmartInfo +AHCI_SMART_SUPPORT EQU 1 shl 0 ;Bit 0 = 0/1, SMART (Not Supported/Supported) +AHCI_SMART_ENABLE EQU 1 shl 1 ;Bit 1 = 0/1, SMART (Disabled/Enabled) +AHCI_SMART_EN EQU 1 shl 1 ;Bit 1 = 0/1, SMART (Disabled/Enabled) +AHCI_SMART_STATUS EQU 1 shl 2 ;Bit 2 = 0/1, Device Status Good/Bad +AHCI_SMART_COMMAND_STATUS EQU 1 shl 7 ;Bit 7 = 0/1, SMART Execution Successful/Error + ;Bit 15-8, Reserved + +; Details qTotalSectors +; This contains the total #of sectors (1-based) in the device. + +;------------------------------------------------------------------------- +; Table containing the pointers to different tables +; 1. Initialized during POST +DEV_PTR_STRUC struc + bInt13Num db ? ; INT13 Drive# for this Port + bPMnum db ? ; Port Multipier port # + bPortNum db ? ; Port# (0-based) on Controller + dParamTablePtr dd ? ; Ptr to device parameter table + dInfoTablePtr dd ? ; Ptr to device info table +DEV_PTR_STRUC ends + +;------------------------------------------------------------------------- + ;(amiahcix-)> +;;;;; INIT_DEV_FUNC_STRUC: Used in INIT_DEVICE_TABLE while initializing device. +;;;;INIT_DEV_FUNC_STRUC struc +;;;; wFunction dw ? ; Routine to be executed +;;;; wStatus dw ? ; Bit-mapped status if error +;;;; bAttrib db ? ; Attribute (details below) +;;;;INIT_DEV_FUNC_STRUC ends +;;;; +;;;;; Details of bAttribute field +;;;;ATTRIB_ERROR equ 01h ;Bit-0 = 0/1, Non-Fatal/Fatal Error +;;;;; ;Bit7-1.....Reserved for future use + ;<(amiahcix-) +;------------------------------------------------------------------------- +; Device parameter table: Same to hdparam.equ +DEV_PARAM_STRUC struc + wMAXCYL dw ? ; maximum no. of cylinders..INT13 interface. (logical) + bMAXHN db ? ; maximum no. of heads..INT13 interface. (logical) + bLBASIG db ? ; LBA signature + bLBASPT db ? ; #of sectors per track drive is configured for. (physical) + wWPCYL dw ? ; start write precomp cyl no. + bReserved db ? ; reserved + bCBYTE db ? ; bit 3 for more than 8 heads + wLBACYL dw ? ; #of cylinders drive is configured for. (physical) + bLBAHD db ? ; #of heads drive is configured for. (physical) + wLANDZ dw ? ; Landing zone + bMAXSN db ? ; no. of sectors per track..INT13 interface. (logical) + bLBACHK db ? ; checksum..LBA +DEV_PARAM_STRUC ends + +; Details of bSignature field: A signature Axh indicates that the table is translated. +DPTBL_SIG_MASK equ 0F0h +lba_signature equ 0A0h ;A0h signature indicating LBA translation + +;------------------------------------------------------------------------- +; Return codes from INT13 +R_SUCCESS EQU 00h ;No error (i.e. Successful) +R_INVALID EQU 01h ;Invalid function request +R_MARK_NOT_FOUND EQU 02h ;Address mark not found +R_WRITE_PROTECT_ERR EQU 03h ;Write protect error +R_SECTOR_NOT_FOUND EQU 04h ;Sector not found +R_RESET_FAIL EQU 05h ;Reset failed +R_MEDIA_CHANGED EQU 06h ;Media changed +R_DRV_PARAM_ACT_FAIL EQU 07h ;Drive parameter activity failed +R_DMA_OVERRUN EQU 08h ;DMA overrun on operation +R_DATA_BOUNDARY_ERR EQU 09h ;Data boundary error +R_BAD_SECTOR EQU 0Ah ;Bad sector flag detected +R_BAD_CYL EQU 0Bh ;Bad cylinder detected +R_INVALID_NUM_OF_SECTOR EQU 0Dh ;Invalid #of sectors on format +R_CTRL_DATA_ADDR_MARK EQU 0Eh ;Control data address mark detected +R_DMA_ARBIT_LEVEL EQU 0Fh ;DMA arbitration level out of range +R_UNCORRECTABLE_ERR EQU 10h ;Uncorrectable ECC/CRC error +R_CORRECTED_DATA_ERR EQU 11h ;ECC corrected data error +R_GENERAL_CTRLER_FAIL EQU 20h ;General controller failure +R_SEEK_FAIL EQU 40h ;Seek operation failed +R_TIME_OUT EQU 80h ;Time out +R_DRV_NOT_READY EQU 0AAh ;Drive not ready +R_UNDEFINED_ERR EQU 0BBh ;Undefined error occurred +R_WRITE_FAULT EQU 0CCh ;Write fault on selected drive +R_STATUS_ERR EQU 0E0h ;Error Register = 0 +R_SENSE_FAIL EQU 0FFh ;Sense Operation failed + +;---------------------------------------------------------------------------- +; Timeout for different operations +SEC_TIMES EQU 00h ;Count for 1sec using refresh signal +MAX_TIMES EQU 05h ;Max time out in seconds + +;---------------------------------------------------------------------------- +IDENTIFY_BUFFER_LENGTH EQU 200h ;512 bytes for Identify device command +SECTOR_LENGTH EQU 200h ;512 bytes sector size +SECTOR_LENGTH_N EQU 9 ;2^n bytes sector size +SELECTOR_NON_LBA EQU 0A0h ;Master without LBA +SELECTOR_LBA EQU 0E0h ;Master with LBA +MAX_STND_XFER_SECTOR EQU 080h ;#of sectors that can be xferred in stnd INT13 func +MAX_EXTD_XFER_SECTOR EQU 07Fh ;#of sectors that can be xferred in extd INT13 func +BLOCK_SIZE EQU 800h ;#of bytes of each transefer from CDROM +BLOCK_SIZE_N EQU 00Bh ;N, block size 2^N + +;------------------------------------------------------------------------- +; Different data area relevant to Hard Disk in BIOS DATA SEGMENT (0040h) +;WINCH_STATUS EQU 74h ;40:74h = DB..Last operation status +;WINCH_NUMBER EQU 75h ;40:75h = DB..#of HDD installed by BIOS +;WINCH_STAT_REG EQU 8Ch ;40:8Ch = DB..Content of status register +;WINCH_ERROR_REG EQU 8Dh ;40:8Dh = DB..Content of error register +;WINCH_INT_FLAG EQU 8Eh ;40:8Eh = DB..Used for interrupt occurrence + +;------------------------------------------------------------------------- +; ATA/ATAPI commands +DEVICE_DIAG_CMD EQU 090h ;Execute device diagnostics command +IDENTIFY_DEVICE_COMMAND EQU 0ECh +ATAPI_IDENTIFY_DEV_CMD EQU 0A1h ;ATAPI identify device command +ATAPI_SIGNATURE EQU 0EB14h ;ATAPI Signature +MULTIPLIER_SIGNATURE EQU 9669h ;Port Multiplier Signature +ATA_SIGNATURE EQU 0000h ;ATA Signature +IDLE_IMMEDIATE EQU 0E2h ;IDLE IMMEDIATE Non-data + +READ_DMA_CMD EQU 0C8h ;Read DMA command +READ_DMA_EXT_CMD EQU 025h ;Read DMA Ext command +READ_MULTIPLE_CMD EQU 0C4h ;Read Multiple command +READ_MULTIPLE_EXT_CMD EQU 029h ;Read Multiple Ext command +READ_SECTORS_CMD EQU 020h ;Read Sector(s) command +READ_EXT_CMD EQU 024h ;Read Sector(s) Ext command + +WRITE_DMA_CMD EQU 0CAh ;Write DMA command +WRITE_DMA_EXT_CMD EQU 035h ;Write DMA Ext command +WRITE_MULTIPLE_CMD EQU 0C5h ;Write Multiple command +WRITE_MULTIPLE_EXT_CMD EQU 039h ;Write Multiple Ext command +WRITE_SECTORS_CMD EQU 030h ;Write Sector(s) command +WRITE_EXT_CMD EQU 034h ;Write Sector(s) Ext command + +READ_VERIFY_CMD EQU 040h ;Verify Sector(s) command +EXTD_READ_VERIFY_CMD EQU 042h ;Verify Sector(s) Ext command + +SET_MULTIPLE_CMD EQU 0C6h ;Set multiple mode command + +ATAPI_RESET_COMMAND EQU 008h ;ATAPI reset command + +SMART_COMMAND EQU 0B0h ;SMART Enable Operations command + SMART_READ_DATA EQU 0D0h + SMART_ATTRIBUTE_AUTOSAVE EQU 0D2h + SMART_SAVE_ATTRIBUTE_VALUES EQU 0D3h + SMART_EXECUTE_OFFLINE_IMMEDIATE EQU 0D4h + SMART_READ_LOG EQU 0D5h + SMART_WRITE_LOG EQU 0D6h +; SMART_ENABLE EQU 0D8h + SMART_DISABLE EQU 0D9h + SMART_RETURN_STATUS EQU 0DAh +;AHCI_HDS --> +SECURITY_SET_CMD equ 0F1h +SECURITY_UNLOCK_CMD equ 0F2h +SECURITY_DISABLE_CMD equ 0F6h +;AHCI_HDS <-- + +SECURITY_FREEZE_LOCK EQU 0F5h + +ATAPI_SOFT_PACKET_CMD EQU 0A0h ;ATAPI command packet value +; Available Packet commands +ATAPI_READ_10_CMD EQU 028h ;ATAPI read command packet value +ATAPI_REQUEST_SENSE_CMD EQU 03h ;ATAPI Request sense +ATAPI_NOP_CMD EQU 00h ;ATAPI Request sense +; Size of "Request Sense Packet" buffer +ATAPI_REQ_SENSE_DATA_SIZE EQU 18 ;ATAPI controller request sense data + +;------------------------------------------------------------------------- +; Input packet structure used in Extended INT13 functions +DISK_ADDRESS_PACKET_STRUC struc + bSize db ? ; Packet size in bytes + bReserved1 db ? ; Reserved (set to 0) + bBlockCount db ? ; #of blocks to be transferred + bReserved2 db ? ; Reserved (set to 0) + dPtrXferBuffer dd ? ; Segment:Offset of transfer buffer + qLBA dq ? ; Selected LBA +DISK_ADDRESS_PACKET_STRUC ends + +DISK_ADDRESS_PACKET_SIZE equ size DISK_ADDRESS_PACKET_STRUC + +; Details of bSize +; It contains size of the packet in bytes including this field. The size is +; 16bytes. If size is less than 16bytes, the function should return error +; with AH = 01h, and CF = 1. If packet size is greater than 16bytes, the +; function ignores the additional information and executes. +; +; Details of bXferCount +; On input, it contains #of sectors to be transferred. On output, it returns +; #of sectors actually transferred. If the input value is 0, the function +; returns successful without any data being transferred. +; +; Details dPtrXferBuffer +; It contains address of the data xfer buffer in segment:offset format. +; +; Details qStartLba +; It contains the absolute LBA of the device. The value can be from 0 to +; (total #of sectors - 1). +;------------------------------------------------------------------------- +; Result Buffer in INT13 Function 48h +;ExtI13DriveInfo STRUC +; wBufferSize DW ? ;Input buffer size in bytes +; wInfoFlags DW ? ;Information flags +; dNumCyls DD ? ;#of cylinders (1-based) +; dNumHeads DD ? ;#of heads (1-based) +; dNumSecs DD ? ;#of sectors per track (1-based) +; qTotalSecs DQ ? ;#of sectors on disk (1-based) +; wSectorSize DW ? ;Sector size in bytes +; pExtTable DD ? ;Ptr to extd parameter table +; wDevPathID DW ? ;Key for Device Path Extension +; bDevPathLength DB ? ;Device path info length (including key) in bytes +; bReserved DB ? ;Reserved (set to 00h) +; wReserved DW ? ;Reserved (set to 0000h) +; dHostBus DD ? ;Host Bus Type in ASCII +; aInterfaceType DB 8 DUP (?) ;Interface Type in ASCII +; aInterfacePath DB 8 DUP (?) ;Interface Path +; aDevPath DB 8 DUP (?) ;Device Path +; bReserved1 DB ? ;Reserved (set to 00h) +; bDevPathChksum DB ? ;Checksum of device path info including wKey field +;ExtI13DriveInfo ENDS + +; Details of wSize field +; It contains the maximum size of the supplied buffer in bytes. +; If buffer size < 1E, function does not return dPtrDpte field. +; If buffer size >= 1E, it should be set to 1E on exit. +; If 1A <= buffer size <= 1D, it should be set to 1A on exit. +; If buffer size < 1A, function returns error. +; Details of wInfoFlag field +; Bit-0 = 1, DMA boundary errors handled transparently +; Bit-1 = 1, Device geometry (in dCylinder, dHead, dSpt fields) is valid +; Bit-2 = 1, Removable Media (Bit6-4 are NOT valid if this Bit-2 = 0) +; Bit-3 = 1, Device supports write with verify on +; Bit-4 = 1, Device supports media change notification +; Bit-5 = 1, Media can be locked +; Bit-6 = 1, Device geometry is set to maximum and no media is present when +; this Bit-6 is set to 1 +; Bit-7 = 1, INT13 Function 50h supported +; Bit15-8....Reserved +; Details of dCylinder field +; It contains physical #of cylinders (1-based). INT13 Function 08h returns +; logical #of cylinders. +; Details of dHead field +; It contains physical #of heads (1-based). INT13 Function 08h returns +; logical #of heads. +; Details of dSpt field +; It contains physical #of sectors/track (1-based). INT13 Function 08h returns +; logical #of sectors/track. +; Details of qTotalSector field +; It contains the total #of sectors (1-based) in the device. If total #of +; sectors > 15482880 (decimal), then bit-1 of wInfoFlag should be set to 0 +; indicating device geometry is not valid. +; Details dPtrDpte field +; This field is present only when INT13 Function 41h returns a 1 in bit-2 of +; output CX. +; Details of wKey field +; It contains BEDDh signature indicating presence of device path information. +; Details of bDevicePathInfoLength +; It contains the length of device path information. The length includes the +; wKey field. +; Details of bHostBusType field +; It contains ASCII string identifying Host Bus. +; 'PCI ' PCI Local Bus 50 43 49 20 +; 'ISA ' Legacy 16bit fixed bus 49 53 41 20 +; 'PCIX' PCI-X Bus 50 43 49 58 +; 'XPRS' PCI Express 58 50 52 53 +; Details of bInterfaceType field +; It contains ASCII string identifying Interface +; 'ATA ' Device using ATA command 41 54 41 20 20 20 20 20 +; 'ATAPI ' Device using ATAPI commands 41 54 41 50 49 20 20 20 +; 'USB ' USB Mass Storage device 55 53 42 20 20 20 20 20 +; 'SATA ' Serial ATA 53 41 54 41 20 20 20 20 +; Details of qInterfacePath field (offset 30h to 37h) +; The content depends on Host Bus Type (bHostBusType field) +; Host Bus Offset Type Content +; ISA 30h Word 16bit base address +; 32h Word Should be 0000h +; 34h Dword Should be 00000000h +; PCI 30h Byte PCI Bus Number +; 31h Byte PCI Slot Number +; 32h Byte PCI Function Number +; 33h Byte Channel Number (FF if not used) +; 34h Dword Should be 00000000h +; Details of bDevicePath field (offset 38h to 47h) +; The content depends on Interface Type (bInterfaceType field) +; Interface Offset Type Content +; SATA 38h Byte SATA Port# (0-based) +; 39h-57h 15byte Set to 0 +; Details of bChecksum field (offset 49h) +; It contains the checksum of device path information including wKey field. +; The byte addition of all bytes in device path information including the +; checksum (offset 1Eh-49h) is 00. +;------------------------------------------------------------------------- +; Extra Functions that are called using interface similar to INT13 +API_DEV_RESET_FUNC equ 00h ; Reset Device +API_PORT_RESET_FUNC equ 01h ; Reset Port +API_DEVICE_ID_FUNC equ 02h ; Identify device data +API_ATAPI_READ_FUNC equ 03h ; Read ATAPI device +API_SMART_ENABLE_FUNC equ 04h ; Enable SMART feature +API_SMART_PROMPT_FUNC equ 05h ; Prop SMART events for errors +API_FREEZE_LOCK_FUNC equ 06h +API_SMART_DISABLE_FUNC equ 07h ;Disable SMART feature ;(EIP9252+) + ;(EIP9321+)>>> Add SMART Function +API_RETURN_SMART_STATUS_FUNC equ 08h ;Return SMART status +API_SMART_READ_DATA_FUNC equ 09h ;Read SMART Data +API_SMART_SHORT_SELFTEST_FUNC equ 0Ah ;SMART Execute Off-Line Immediate +API_SMART_EXTENDED_SELFTEST_FUNC equ 0Bh ;SMART Execute Off-Line Immediate + ;<<<(EIP9321+) + +;------------------------------------------------------------------------- +; Runtime Attribute: bit-mapped information +A_EBDA_USED equ 01h ; Bit-0 = 1, Use EBDA memory for CLCTFIS area + ; Bit-1...Reserved for internal use + ; Bit7-2..Reserved for future use + +;------------------------------------------------------------------------- +; Equates and structures of Virtual DMA Services (VDS) +;------------------------------------------------------------------------- +; DDS (DMA Descriptor structure): Used to Lock/Unlock DMA region. The fields +; namely, dRegionSize, dRegionOffset, wRegionSegment need to be +; initialized with proper values before calling Lock function. The Lock +; function fills wBufferId and dRegionPhysicalAddress fields. The same +; DDS, as returned by Lock function, needs to be used while calling +; UnLock function. +DDS_STRUC struc + dRegionSize dd ? ; Region Size in bytes (filled by caller) + dRegionOffset dd ? ; Region Offset (filled by caller) + wRegionSegment dw ? ; Region Segment (filled by caller) + wBufferId dw ? ; Buffer ID (filled by VDS function) + dRegionPhysicalAddress dd ? ; Physical address of region (filled by VDS function) +DDS_STRUC ends + +; EDDS (Extended DMA Descriptor structure): EDDS contains EDDS Header followed +; by one or more EDDS entry. The maximum #of entries that EDDS can +; accommodate is limited by the space available for EDDS. In this +; implementation, space for maximum 16 entries are available in EDDS. +MAX_NO_OF_EDDS_ENTRY equ 16 ; Max #of entries EDDS can accommodate + +EDDS_HEADER_STRUC struc + dRegionSize dd ? ; Region Size in bytes (filled by caller) + dRegionOffset dd ? ; Region Offset (filled by caller) + wRegionSegment dw ? ; Region Segment (filled by caller) + wReserved dw ? ; Reserved (filled by caller) + wNoOfAvailableEntry dw ? ; #of entries available in EDDS (filled by caller) + wNoOfUsedEntry dw ? ; #of entries used in EDDS (filled by VDS function) +EDDS_HEADER_STRUC ends + +EDDS_ENTRY_STRUC struc + dRegionPhysicalAddress dd ? ; Physical address of region (filled by VDS function) + dRegionSize dd ? ; Region size in bytes (filled by VDS function) +EDDS_ENTRY_STRUC ends + +;------------------------------------------------------------------------- +; EQUATES FOR COMMAND LIST, COMMAND TABLE, FIS, DDS, EDDS +; CLCTFIS area is in EBDA, both DDS and EDDS are in EBDA. +;------------------------------------------------------------------------- +SIZE_CMD_LIST equ 1024 ; 1kbytes for command list +SIZE_FIS equ 0256 ; 256bytes for FIS +SIZE_CMD_TABLE equ 0384 ; 384bytes for command table +; +SIZE_DDS equ size DDS_STRUC ; 16bytes for DDS +SIZE_EDDS equ size EDDS_HEADER_STRUC + \ + (MAX_NO_OF_EDDS_ENTRY * (size EDDS_ENTRY_STRUC)); 272bytes for EDDS + +SIZE_ALIGN_BUFFER equ BLOCK_SIZE+2 ;(v1.07) + +SIZE_CLCTFIS_AREA_K equ 4 ; CLCTFIS area in unit of 1k in system memory/EBDA +SIZE_CLCTFIS_AREA_B equ SIZE_CLCTFIS_AREA_K*1024 ; CLCTFIS area in bytes in system memory/EBDA + +; Equates for start offset of different areas +; Command List at offset 0000h, FIS at offset 0400h, Command Table at +; offset 0500h. +START_CMD_LIST equ 0000h ; Command List must be 1kbyte aligned +START_FIS equ START_CMD_LIST+SIZE_CMD_LIST ; FIS must be 256byte aligned +START_CMD_TABLE equ START_FIS+SIZE_FIS ; Command table must be 128byte aligned +START_DDS equ START_CMD_TABLE+SIZE_CMD_TABLE ; Start of DDS +START_EDDS equ START_DDS+SIZE_DDS ; Start of EDDS +START_ALIGN_BUFFER equ START_EDDS+SIZE_EDDS ; Start of DMA Alignment Buffer +START_LOCAL_BUFFER equ START_ALIGN_BUFFER+SIZE_ALIGN_BUFFER ; Start of Local Buffer(v1.07) + +;------------------------------------------------------------------------- +; INT13 FUNCTION TABLE STRUCTURE +;------------------------------------------------------------------------- +AI13_FUNC_STRUC struc + bFuncNum db ? ; Function# + wFuncProc dw ? ; Offset of Execution routine +AI13_FUNC_STRUC ends + +;------------------------------------------------------------------------- +; EQUATES OF DIFFERENT PARAMETERS IN STACK +;------------------------------------------------------------------------- +; +; Stack equates for PUSH GS/PUSH FS/PUSH ES/PUSH DS/PUSHAD +; after allocating N bytes in stack +; +; GS, FS, ES, DS positions in stack PUSH GS +; PUSH FS +; PUSH ES +; PUSH DS +; PUSHAD +; sub sp, SIZE_AHCI_INT13_MISC_STACK +; +TASKF_STRUC STRUC + CmdListBase dd ? ;32bit Command List base address + CmdTableBase dd ? ;32bit Command Table base address + FisRecBase dd ? ;32bit FIS Receive base address + HbaBase dd ? ;32bit HBA Base address + CmdListPtr dd ? ;Ptr (Seg:Off) to Command List + CmdTablePtr dd ? ;Ptr (Seg:Off) to Command Table + FisRecPtr dd ? ;Ptr (Seg:Off) to FIS Receive + DdsPtr dd ? ;Ptr (Seg:off) to DDS + EddsPtr dd ? ;Ptr (Seg:off) to EDDS + DevInfoTablePtr dd ? ;Ptr (Seg:off) to Device Info Table + PortNum db ? ;Port# (0-based) on Controller + bControllerNo db ? + Selector db ? ;Device Selector + InfoFlag db ? ;Device Info Flag + RequestedSectorCount db ? ;#of sector(s) access requested + AccessedSectorCount db ? ;#of sector(s) actually accessed + CmdSlotMask db ? ;Bit-mask of slot(s) used in command list + CmdSlotNum db ? ;Slot# (0-based) used in command list + Attribute db ? ;Bit-mapped attribute of misc information + Port21 db ? ;Content of Port21 + PortA1 db ? ;Content of PortA1 + ReservedDD1 dd ? ;Reserved + ReservedDD2 dd ? ;Reserved + ModUserBufferOfs dw ? ;Offset of modified user buffer + ModUserBufferSeg dw ? ;Segment of modified user buffer + ModUserBufferSize dw ? ;Size in Dwords (1-based) of modified user buffer + OrgUserBufferOfs dw ? ;Original segment of user buffer, to overcome unaligned user buffer + OrgUserBufferSeg dw ? ;Original Offset of user buffer, to overcome unaligned user buffer + AlignBufferOfs dw ? ;Offset to Alignment buffer, to be used for temp DMA alignment buffer + AlignBufferSeg dw ? ;Segment to Alignment buffer, to be used for temp DMA alignment buffer +TASKF_STRUC ENDS + +PUSHAD_STRUC STRUC + + StackFS dw ? + StackDS dw ? + StackES dw ? + StackGS dw ? + + StackEDI dd ? + StackESI dd ? + StackEBP dd ? + StackESP dd ? + StackEBX dd ? + StackEDX dd ? + StackECX dd ? + StackEAX dd ? + +PUSHAD_STRUC ENDS + +;SIZE_AHCI_INT13_MISC_STACK equ AI13_STACK_BUFFER_STRUC.StackEDI ; EDI is the last in PUSHAD + + +S_AHCI_STACK struc +TaskFile TASKF_STRUC <> +Stack PUSHAD_STRUC <> +S_AHCI_STACK ends + + ;(amiahcix+)> +;---------------------------------------------------------------------------- +; AHCI error equates +;---------------------------------------------------------------------------- + +; 000h-03Fh : CIDs for CORE compnents. +; Used for stBIOSError.wErrorCode[15:8] +CID_AHCI EQU 004h + +;---------------------------------------; +; AHCI_x_ERR +;---------------------------------------; +EQU_AHCI_ERR macro COUNT + AHCI_&COUNT&_ERR EQU (CID_AHCI SHL 8) + COUNT +endm + +AHCI_ACCESS STRUCT + Index dw ? + Data dw ? + BaseAddress dd ? +AHCI_ACCESS ENDS + +; builds 64 AHCI_x_ERR: + +; AHCI_0_ERR EQU (CID_AHCI SHL 8) + 0 +; AHCI_1_ERR EQU (CID_AHCI SHL 8) + 1 +; AHCI_2_ERR EQU (CID_AHCI SHL 8) + 2 +; AHCI_3_ERR EQU (CID_AHCI SHL 8) + 3 +; . +; . +ATA_COUNT = 0 ; starts from AHCI_0_err +REPEAT 64 ; Max 64 AHCI errors + EQU_AHCI_ERR %ATA_COUNT + ATA_COUNT = ATA_COUNT+1 +ENDM +;---------------------------------------; + ;<(amiahcix+) + + +;------------------------------------------------------------------------- +;**************************************************************************** +;**************************************************************************** +;** ** +;** (C)Copyright 1985-2011, American Megatrends, Inc. ** +;** ** +;** All Rights Reserved. ** +;** ** +;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +;** ** +;** Phone (770)-246-8600 ** +;** ** +;**************************************************************************** +;**************************************************************************** diff --git a/Chipset/eM/Ahci/AInt13Csp.c b/Chipset/eM/Ahci/AInt13Csp.c new file mode 100644 index 0000000..44365ba --- /dev/null +++ b/Chipset/eM/Ahci/AInt13Csp.c @@ -0,0 +1,111 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//**************************************************************************** +// $Header: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AInt13Csp.c 3 2/10/11 10:52a Rameshr $ +// +// $Revision: 3 $ +// +// $Date: 2/10/11 10:52a $ +// +//**************************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AInt13Csp.c $ +// +// 3 2/10/11 10:52a Rameshr +// [TAG] EIP53704 +// [Category] Improvement +// [Description] AMI headers update for Alaska Ahci Driver +// [Files] AHCIACC.ASM +// HACCESS.EQU +// AHCI.EQU +// AINT13.EQU +// AInt13Csp.c +// +// 2 5/28/08 9:44a Rameshraju +// Updated the AMI Address. +// +// 1 12/07/07 11:17a Olegi +// +//**************************************************************************** + +//<AMI_FHDR_START> +//---------------------------------------------------------------------------- +// +// Name: AINT13CSP.C +// Description: AHCI INT13 Support Chipset Configuration File +// +//---------------------------------------------------------------------------- +//<AMI_FHDR_END> + +#define LBAR_REGISTER 0x20 +#define LBAR_ADDRESS_MASK 0xFFFFFFE0 +#define INDEX_OFFSET_FROM_LBAR 0x10 +#define DATA_OFFSET_FROM_LBAR 0x14 + +#include "AmiDxeLib.h" +#include "Protocol\PciIo.h" + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Name: GetAccessInfo +// +// Description: This is chipset porting routine that returns index/data ports +// to access memory-mapped registers. +// +// Input: PciIo +// +// Output: EFI_SUCCESS - Access information is collected +// EFI_ACCESS_DENIED - No Access information avaliable +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +GetAccessInfo ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + OUT UINT16 *AccessIndexPort, + OUT UINT16 *AccessDataPort +) +{ + EFI_STATUS Status; + UINT32 lbar; + + Status = PciIo->Pci.Read(PciIo, EfiPciIoWidthUint32, LBAR_REGISTER, 1, &lbar); + ASSERT_EFI_ERROR(Status); + + lbar &= LBAR_ADDRESS_MASK; // Legacy Bus Master Base Address + + *AccessIndexPort = (UINT16)lbar + INDEX_OFFSET_FROM_LBAR; + *AccessDataPort = (UINT16)lbar + DATA_OFFSET_FROM_LBAR; + + return EFI_SUCCESS; + +} + + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Chipset/eM/Ahci/AhciAccess.c b/Chipset/eM/Ahci/AhciAccess.c new file mode 100644 index 0000000..36ea264 --- /dev/null +++ b/Chipset/eM/Ahci/AhciAccess.c @@ -0,0 +1,252 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/AHCI/AhciAccess.c 3 2/11/11 4:09a Rameshr $ +// +// $Revision: 3 $ +// +// $Date: 2/11/11 4:09a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/AHCI/AhciAccess.c $ +// +// 3 2/11/11 4:09a Rameshr +// [TAG] EIP53704 +// [Category] Improvement +// [Description] AMI headers update for Alaska Ahci Driver +// [Files] AhciAccess.c +// +// 2 5/07/10 11:51a Krishnakumarg +// Update for coding standard. +// +// 1 5/28/08 9:49a Rameshraju +// Initial Check-in for Index/Data access method. +// +//********************************************************************** +//<AMI_FHDR_START> +// +// Name: AhciAccess.c +// +// Description: Provides Index Data Port Access to AHCI Controller +// +//<AMI_FHDR_END> +//********************************************************************** +//#include <AmiDxeLib.h> + +#define LBAR_REGISTER 0x20 +#define LBAR_ADDRESS_MASK 0xFFFFFFE0 +#define INDEX_OFFSET_FROM_LBAR 0x10 +#define DATA_OFFSET_FROM_LBAR 0x14 + +#include "AmiDxeLib.h" +#include "Protocol\PciIo.h" + +UINT16 IndexPort, DataPort; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Name: InitilizeIndexDataPortAddress +// +// Description: This is chipset porting routine that returns index/data ports +// to access memory-mapped registers. +// +// Input: PciIo +// +// Output: EFI_SUCCESS - Access information is collected +// EFI_ACCESS_DENIED - No Access information avaliable +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +InitilizeIndexDataPortAddress ( + IN EFI_PCI_IO_PROTOCOL *PciIo +) +{ + EFI_STATUS Status; + UINT32 lbar; + + Status = PciIo->Pci.Read(PciIo, EfiPciIoWidthUint32, LBAR_REGISTER, 1, &lbar); + ASSERT_EFI_ERROR(Status); + + lbar &= LBAR_ADDRESS_MASK; // Legacy Bus Master Base Address + + IndexPort = (UINT16)lbar + INDEX_OFFSET_FROM_LBAR; + DataPort = (UINT16)lbar + DATA_OFFSET_FROM_LBAR; + + return EFI_SUCCESS; + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Name: ReadDataDword +// +// Description: Read the Dword Data using Index/Data access method +// +// Input: BaseAddress - BaseAddress of AHCI Controller +// Index - Index address to read +// +// Output: Value Read +// +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT32 +ReadDataDword( + IN UINTN BaseAddr, + IN UINTN Index +) +{ + IoWrite32(IndexPort, (UINT32)Index); + return IoRead32(DataPort); +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Name: WriteDataDword +// +// Description: WriteRead the Dword Data using Index/Data access method +// +// Input: BaseAddress - BaseAddress of AHCI Controller +// Index - Index address to Write +// Data - Data to be written +// +// Output: Nothing +// +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +WriteDataDword( + IN UINTN BaseAddr, + IN UINTN Index, + IN UINTN Data +) +{ + IoWrite32(IndexPort, (UINT32)Index); + IoWrite32(DataPort, (UINT32)Data); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Name: ReadDataDword +// +// Description: Read the Word Data using Index/Data access method +// +// Input: BaseAddress - BaseAddress of AHCI Controller +// Index - Index address to read +// +// Output: Value Read +// +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT16 +ReadDataWord( + IN UINTN BaseAddr, + IN UINTN Index +) +{ + IoWrite32(IndexPort, (UINT32)Index); + return (UINT16)IoRead32(DataPort); +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Name: WriteDataDword +// +// Description: WriteRead the word Data using Index/Data access method +// +// Input: BaseAddress - BaseAddress of AHCI Controller +// Index - Index address to Write +// Data - Data to be written +// +// Output: Nothing +// +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +WriteDataWord( + IN UINTN BaseAddr, + IN UINTN Index, + IN UINTN Data +) +{ + IoWrite32(IndexPort, (UINT32)Index); + IoWrite32(DataPort, (UINT16)Data); +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Name: ReadDataDword +// +// Description: Read the Byte Data using Index/Data access method +// +// Input: BaseAddress - BaseAddress of AHCI Controller +// Index - Index address to read +// +// Output: Value Read +// +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8 +ReadDataByte( + IN UINTN BaseAddr, + IN UINTN Index +) +{ + IoWrite32(IndexPort, (UINT32)Index); + return (UINT8)IoRead32(DataPort); +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Name: WriteDataByte +// +// Description: WriteRead the Dword Data using Index/Data access method +// +// Input: BaseAddress - BaseAddress of AHCI Controller +// Index - Index address to Write +// Data - Data to be written +// +// Output: Nothing +// +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +WriteDataByte( + IN UINTN BaseAddr, + IN UINTN Index, + IN UINTN Data +) +{ + IoWrite32(IndexPort, (UINT32)Index); + IoWrite8(DataPort, (UINT8)Data); +} + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//**********************************************************************
\ No newline at end of file diff --git a/Chipset/eM/Ahci/AhciAccess.cif b/Chipset/eM/Ahci/AhciAccess.cif new file mode 100644 index 0000000..d5a2046 --- /dev/null +++ b/Chipset/eM/Ahci/AhciAccess.cif @@ -0,0 +1,8 @@ +<component> + name = "AHCI CSP-Template" + category = ModulePart + LocalRoot = "Chipset\eM\Ahci" + RefName = "ACSP" +[files] +"AhciAccess.c" +<endComponent> diff --git a/Chipset/eM/Ahci/AhciCsp.cif b/Chipset/eM/Ahci/AhciCsp.cif new file mode 100644 index 0000000..1c12363 --- /dev/null +++ b/Chipset/eM/Ahci/AhciCsp.cif @@ -0,0 +1,12 @@ +<component> + name = "AHCI Int13 CSP-Template" + category = ModulePart + LocalRoot = "Chipset\eM\Ahci" + RefName = "AHCI_INT13_CSP" +[files] +"AHCIACC.ASM" +"HACCESS.EQU" +"AHCI.EQU" +"AINT13.EQU" +"AInt13Csp.c" +<endComponent> diff --git a/Chipset/eM/Ahci/HACCESS.EQU b/Chipset/eM/Ahci/HACCESS.EQU new file mode 100644 index 0000000..53c2292 --- /dev/null +++ b/Chipset/eM/Ahci/HACCESS.EQU @@ -0,0 +1,108 @@ +; TITLE HACCESS.EQU - Accessing HBA memory-mapped register +;**************************************************************************** +;**************************************************************************** +;** ** +;** (C)Copyright 1985-2011, American Megatrends, Inc. ** +;** ** +;** All Rights Reserved. ** +;** ** +;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +;** ** +;** Phone (770)-246-8600 ** +;** ** +;**************************************************************************** +;**************************************************************************** + +;**************************************************************************** +; $Header: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/HACCESS.EQU 3 2/10/11 10:52a Rameshr $ +; +; $Revision: 3 $ +; +; $Date: 2/10/11 10:52a $ +; +;**************************************************************************** +; Revision History +; ---------------- +; $Log: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/HACCESS.EQU $ +; +; 3 2/10/11 10:52a Rameshr +; [TAG] EIP53704 +; [Category] Improvement +; [Description] AMI headers update for Alaska Ahci Driver +; [Files] AHCIACC.ASM +; HACCESS.EQU +; AHCI.EQU +; AINT13.EQU +; AInt13Csp.c +; +; 2 5/28/08 9:43a Rameshraju +; Updated the AMI Address. +; +; 1 12/07/07 11:17a Olegi +; +; 4 12/05/06 3:16a Iminglin +; Remove useless. +; +; 3 11/29/06 3:18a Iminglin +; CSP modification. +; +; 2 11/23/06 10:12p Iminglin +; Default is for ICH7. +; +; 1 6/09/05 11:29p Iminglin +; Initialized version +; +; 1 5/20/05 2:37a Iminglin +; Intel AHCI source +; +;**************************************************************************** + +;------------------------------------------------------------------------- +; +; Input parameter in register CH to read/write memory-mapped registers. +; +;ACCESS_DATA equ 0ADh +; +; Output parameter in register CH from read/write memory-mapped registers. +; This data is checked for determining whether access is successful. +; +;DATA_ACCESSED equ 0DAh ; Access is Successful + ; Any other value -> error +; +;------------------------------------------------------------------------- +; Function number used for common control routine to access memory-mapped +; registers using any access method +; +;READ_BYTE equ 00h ; Func# 00h for Read Byte Data +;READ_WORD equ 01h ; Func# 01h for Read Word Data +;READ_DWORD equ 02h ; Func# 02h for Read Dword Data +; +;WRITE_BYTE equ 10h ; Func# 10h for Write Byte Data +;WRITE_WORD equ 11h ; Func# 11h for Write Word Data +;WRITE_DWORD equ 12h ; Func# 12h for Write Dword Data +; +;INIT_BYTE_ARRAY equ 20h ; Func# 20h for Init Byte Array +;INIT_WORD_ARRAY equ 21h ; Func# 21h for Init Word Array +;INIT_DWORD_ARRAY equ 22h ; Func# 22h for Init Dword Array +; +;------------------------------------------------------------------------- +; +;RW_FUNC_STRUC struc +; bFunction db ? ; Function# +; wPtrToRoutine dw ? ; Offset of execution routine +;RW_FUNC_STRUC ends +;------------------------------------------------------------------------- +;**************************************************************************** +;**************************************************************************** +;** ** +;** (C)Copyright 1985-2011, American Megatrends, Inc. ** +;** ** +;** All Rights Reserved. ** +;** ** +;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +;** ** +;** Phone (770)-246-8600 ** +;** ** +;**************************************************************************** +;**************************************************************************** + diff --git a/Chipset/eM/ME/MEUD/CSP_MEUD.c b/Chipset/eM/ME/MEUD/CSP_MEUD.c new file mode 100644 index 0000000..2036dee --- /dev/null +++ b/Chipset/eM/ME/MEUD/CSP_MEUD.c @@ -0,0 +1,1196 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2009, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* +//************************************************************************* +// $Header: /Alaska/SOURCE/Modules/OFBD Intel ME Update/CSP_MEUD/ME80/CSP_MEUD.c 14 5/14/15 4:33a Tristinchou $ +// +// $Revision: 14 $ +// +// $Date: 5/14/15 4:33a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/OFBD Intel ME Update/CSP_MEUD/ME80/CSP_MEUD.c $ +// +// 14 5/14/15 4:33a Tristinchou +// [TAG] EIP215437 +// [Category] New Feature +// [Description] ME capsule update support on SharkBay +// +// 13 3/05/14 2:51a Tristinchou +// [TAG] EIP147099 +// [Category] New Feature +// [Description] Support ME FWUpdate API +// +// 12 10/01/13 1:40a Klzhan +// [TAG] EIPNone +// [Category] Improvement +// [Description] backward compatible +// +// 11 9/30/13 6:05a Klzhan +// [TAG] EIPNone +// [Category] Improvement +// [Description] Support PI 1.2 +// +// 10 8/23/13 4:14a Tristinchou +// [TAG] EIPNone +// [Category] Improvement +// [Description] Fix build error with CrescentBay project. +// +// 9 5/16/13 6:24a Klzhan +// [TAG] EIPNone +// [Category] Improvement +// [Description] 1. Pre-allocate Memory while ME is disable(Avoid +// allocate memory error message). +// 2. Support PDR reiong is on top of SPI(AFU 3.05 and +// 4.6.3_Flash_Combined_2_36) +// +// 8 3/15/13 5:18a Klzhan +// [TAG] EIPNone +// [Category] Improvement +// [Description] Add new token BITS_OF_SPI_DENSITY +// [Files] CSP_MEUD.c +// CSP_MEUD.h +// CSP_MEUD.sdl +// CSP_MEUD.mak +// CSP_MEUD.cif +// +// 7 11/29/12 4:42a Klzhan +// BugFix : Can't update ME when 2 SPI installed. A token is added +// (Lynx Point spec updated, BIT define chaged). +// +// 6 11/29/12 2:24a Klzhan +// BugFix : Mac address restored to wrong address. +// +// 5 11/28/12 4:03a Klzhan +// Getting wrong Flash capacity when 2 flash component. +// +// 4 9/07/12 4:46a Klzhan +// Support ME 9. +// +// 1 12/12/11 2:38a Wesleychen +// Update to rev.2 for FD region length correction. +// +// 2 5/09/11 3:25a Klzhan +// Correct FD region length. +// +// 1 4/22/11 2:47a Klzhan +// Initial check - in +// +// +// +//********************************************************************** +//<AMI_FHDR_START> +// +// Name: CSP_MEUD.c +// +// Description: +// +//<AMI_FHDR_END> +//********************************************************************** +#include "Efi.h" +#include "token.h" +#include <AmiLib.h> +#include <AmiDxeLib.h> +#include <SB.h> +#include "CoreBiosMsg.h" +#include "ReferenceCode\ME\Protocol\Heci\Heci.h" +#include "MeChipset.h" +#include "PchRegs\PchRegsRcrb.h" +#include "CSP_MEUD.h" +#include <MEUD\MEUD.h> +#include "Flash.h" +#include "MEFwUpdLcl\MeFwUpdLclProtocol.h" + +#if defined SecSMIFlash_SUPPORT && SecSMIFlash_SUPPORT == 1 +#include <Protocol\SecSmiFlash.h> +#endif + +#if PI_SPECIFICATION_VERSION >= 0x1000A +#include <Protocol\SmmBase2.h> +#define RETURN(status) {return status;} + +extern EFI_GUID gEfiSmmBase2ProtocolGuid; +EFI_SMM_BASE2_PROTOCOL *gSmmBase2; +EFI_SMM_SYSTEM_TABLE2 *gSmst; +#endif +#if defined SecSMIFlash_SUPPORT && SecSMIFlash_SUPPORT == 1 +static EFI_GUID gEfiSecSmiFlashProtocolGuid = SEC_SMI_FLASH_GUID; +UINT32 *gFwCapsuleAddress = NULL; +#endif + +EFI_GUID gEfiHeciProtocolGuid = HECI_PROTOCOL_GUID; + +BOOLEAN IsIgnition; +BOOLEAN Is_SECOVR_JMPR; +BOOLEAN Is_MEFW; + +EFI_PHYSICAL_ADDRESS Phy_Address; +OFBD_TC_55_ME_PROCESS_STRUCT *StructPtr; +UINT8 MacAddr[6]; +UINT8 Nounce[8]; +UINT32 Factory_Base; +UINT32 Factory_Limit; +#ifdef _HECI_PROTOCOL_H +HECI_PROTOCOL *mHeci = NULL; +#else +EFI_HECI_PROTOCOL *mHeci = NULL; +#endif +EFI_PHYSICAL_ADDRESS RomBuffer = NULL; +EFI_PHYSICAL_ADDRESS BlockBuffer = NULL; + +EFI_GUID mMeFwUpdLclProtocolGuid = ME_FW_UPD_LOCAL_PROTOCOL_GUID; +ME_FW_UPDATE_LOCAL_PROTOCOL *mMeFwUpdateLocalProtocol = NULL; +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: GET_FW_VERSION +// +// Description: Get ME FW Version. +// +// Input: NONE +// +// Output: EFI_STATUS +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS GET_FW_VERSION( + IN UINT16 *MeFwVersionData +) +{ + EFI_STATUS Status; + UINT32 Length; + GEN_GET_FW_VER *MsgGenGetFwVersion; + GEN_GET_FW_VER GenGetFwVersion; + UINT32 MeMode; + GEN_GET_FW_VER_ACK MsgGenGetFwVersionAck; + + Status = mHeci->GetMeMode (&MeMode); + if (EFI_ERROR (Status) || (MeMode != ME_MODE_NORMAL)) { + return EFI_UNSUPPORTED; + } + + // + // Allocate MsgGenGetFwVersion data structure + // + MsgGenGetFwVersion = &GenGetFwVersion; + MsgGenGetFwVersion->MKHIHeader.Data = 0; + MsgGenGetFwVersion->MKHIHeader.Fields.GroupId = MKHI_GEN_GROUP_ID; + MsgGenGetFwVersion->MKHIHeader.Fields.Command = GEN_GET_FW_VERSION_CMD; + MsgGenGetFwVersion->MKHIHeader.Fields.IsResponse = 0; + Length = sizeof (GEN_GET_FW_VER); + // + // Send Get Firmware Version Request to ME + Status = mHeci->SendMsg ( + (UINT32 *) MsgGenGetFwVersion, + Length, + BIOS_FIXED_HOST_ADDR, + HECI_CORE_MESSAGE_ADDR + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Length = sizeof (GEN_GET_FW_VER_ACK); + Status = mHeci->ReadMsg ( + BLOCKING, + (UINT32 *) &MsgGenGetFwVersionAck, + &Length + ); + if (EFI_ERROR (Status)) { + return Status; + } + + MeFwVersionData[0] = MsgGenGetFwVersionAck.Data.CodeMajor; + MeFwVersionData[1] = MsgGenGetFwVersionAck.Data.CodeMinor; + MeFwVersionData[2] = MsgGenGetFwVersionAck.Data.CodeHotFix; + MeFwVersionData[3] = MsgGenGetFwVersionAck.Data.CodeBuildNo; + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: GetHFS +// +// Description: Get Host Firmware Status pass to MEUD +// +// Input: NONE +// +// Output: Host Firmware Status +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT32 GetHFS(VOID) +{ + UINT32 R_HFS; + EFI_STATUS Status; + if(mHeci == NULL) + { + R_HFS = 0; + return R_HFS; + } + Status = mHeci->GetMeStatus(&R_HFS); + if (EFI_ERROR (Status)) { + R_HFS = 0; + } + return R_HFS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: HMRFPO_ENABLE_MSG +// +// Description: Send Enable HECI message to enable Ignition Firmwate update. +// +// Input: NONE +// +// Output: NONE +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS HMRFPO_ENABLE_MSG(VOID) +{ + EFI_STATUS Status = EFI_SUCCESS; + MKHI_HMRFPO_ENABLE HmrfpoEnableRequest; + MKHI_HMRFPO_ENABLE_RESPONSE HmrfpoEnableResponse; + UINT32 HeciLength; + + // Function 1 and 4 will call this function, check is ME or Ignition. + if(Is_MEFW) + { + // If ME FW check GPIO33 assert or not + if(Is_SECOVR_JMPR) + return EFI_SUCCESS; + else + return EFI_UNSUPPORTED; + } + if(mHeci == NULL) + return EFI_NOT_READY; + + HmrfpoEnableRequest.MkhiHeader.Fields.GroupId = MKHI_SPI_GROUP_ID; + HmrfpoEnableRequest.MkhiHeader.Fields.Command = HMRFPO_ENABLE_CMD_ID; + HmrfpoEnableRequest.MkhiHeader.Fields.IsResponse = 1; + + MemSet( &HmrfpoEnableRequest.Nonce ,8,0); + + HeciLength = sizeof (MKHI_HMRFPO_ENABLE); + + Status = mHeci->SendMsg ( + (UINT32 *) &HmrfpoEnableRequest, + HeciLength, + BIOS_FIXED_HOST_ADDR, + HECI_CORE_MESSAGE_ADDR + ); + if (EFI_ERROR (Status)) { + IoWrite8(0x80, 0xA0); + return Status; + } + + HeciLength = sizeof (MKHI_HMRFPO_ENABLE_RESPONSE); + + Status = mHeci->ReadMsg ( + BLOCKING, + (UINT32 *) &HmrfpoEnableResponse, + &HeciLength + ); + if (EFI_ERROR (Status)) { + IoWrite8(0x80, 0xA1); + return Status; + } + + return Status; + +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: HMRFPO_LOCK_MSG +// +// Description: Send LOCK HECI message and lock ME. +// +// Input: NONE +// +// Output: NONE +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS HMRFPO_LOCK_MSG(VOID) +{ + EFI_STATUS Status; + MKHI_HMRFPO_LOCK HmrfpoLockRequest; + MKHI_HMRFPO_LOCK_RESPONSE HmrfpoLockResponse; + UINT32 HeciLength; + // Function 1 and 4 will call this function, check is ME or Ignition. + if(Is_MEFW) + { + // If ME FW check GPIO33 assert or not + if(Is_SECOVR_JMPR) + return EFI_SUCCESS; + else + return EFI_UNSUPPORTED; + } + if(mHeci == NULL) + return EFI_NOT_READY; + HmrfpoLockRequest.MkhiHeader.Fields.GroupId = MKHI_SPI_GROUP_ID; + HmrfpoLockRequest.MkhiHeader.Fields.Command = HMRFPO_LOCK_CMD_ID; + HmrfpoLockRequest.MkhiHeader.Fields.IsResponse = 1; + + HeciLength = sizeof (MKHI_HMRFPO_LOCK); + Status = mHeci->SendMsg ( + (UINT32 *) &HmrfpoLockRequest, + HeciLength, + BIOS_FIXED_HOST_ADDR, + HECI_CORE_MESSAGE_ADDR + ); + if (EFI_ERROR (Status)) { + IoWrite8(0x80, 0xA0); + return Status; + } + + HeciLength = sizeof (MKHI_HMRFPO_LOCK_RESPONSE); + Status = mHeci->ReadMsg ( + BLOCKING, + (UINT32 *) &HmrfpoLockResponse, + &HeciLength + ); + if (EFI_ERROR (Status)) { + IoWrite8(0x80, 0xA1); + return Status; + } else { + Factory_Base = HmrfpoLockResponse.FactoryDefaultBase; + Factory_Limit = HmrfpoLockResponse.FactoryDefaultLimit; + } + + return Status; + +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: GetRegionOffset +// +// Description: Get GBE Region Offet of whole FlashPart +// +// Input: +// VOID +// Output: +// UINT32 The offset of GBE Region +// +// Returns: +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +GetRegionOffset( + UINT8 Region, + UINT32* Offset, + UINT32* Length +) +{ + volatile UINT32 *FDOC; + volatile UINT32 *FDOD; + UINT32 FlashDescriptorSig = 0x0FF0A55A; + UINT32 Buffer32, RegionStart, RegionEnd; + + + FDOC = (UINT32*)(pSPIBASE + 0xB0); + FDOD = (UINT32*)(pSPIBASE + 0xB4); + *FDOC = 0; + + if (*FDOD != FlashDescriptorSig) + return EFI_UNSUPPORTED; + + switch(Region) + { + // Flash Descriptor + case 0: + *FDOC = 0x2000; + break; + + // BIOS + case 1: + *FDOC = 0x2004; + break; + + // ME + case 2: + *FDOC = 0x2008; + break; + + // GBE + case 3: + *FDOC = 0x200C; + break; + + // Platform Data + case 4: + *FDOC = 0x2010; + break; + + default: + return EFI_UNSUPPORTED; + break; + } + Buffer32 = *FDOD; + RegionEnd = Buffer32 >> 16; + RegionStart = Buffer32 & 0xFFFF; + + *Offset = RegionStart << 12; + *Length = (RegionEnd - RegionStart + 1) << 12; + if((Region == 0) && (RegionEnd == 0)) + { + *Length = 0x1000; + return EFI_SUCCESS; + } + if(RegionEnd == 0) + { + *Length = 0; + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: GetFlashCapacity +// +// Description: Send a HECI message to lock ME. +// +// Input: NONE +// +// Output: FlashDensity - Real Flash Size +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT32 GetFlashCapacity(VOID) +{ + volatile UINT32 *FDOC; + volatile UINT32 *FDOD; + UINT32 FlashDescriptorSig = 0x0FF0A55A; + UINT16 Components; + UINT8 i,j; + static UINT32 FlashDensity = 0; + + if(FlashDensity) + return FlashDensity; + + FDOC = (UINT32*)(pSPIBASE + 0xB0); + FDOD = (UINT32*)(pSPIBASE + 0xB4); + *FDOC = 0; + + if (*FDOD != FlashDescriptorSig) + return 0; + + *FDOC = 0x04; + Components = (*FDOD >> 8) & 0x03; + + *FDOC = 0x1000; + j = *FDOD; + + + for (i=0; i<(Components + 1); i++) + { + switch (j & 0x07) + { + case 0: + FlashDensity += 0x80000; + break; + case 1: + FlashDensity += 0x100000; + break; + case 2: + FlashDensity += 0x200000; + break; + case 3: + FlashDensity += 0x400000; + break; + case 4: + FlashDensity += 0x800000; + break; + case 5: + FlashDensity += 0x1000000; + break; + default: + break; + } +#if BITS_OF_SPI_DENSITY + j = j >> 4; +#else + j = j >> 3; +#endif + } + return FlashDensity; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: CSP_ReportMEInfo +// +// Description: Report ME Base address and Length to AFU +// +// Input: BASE_Address - address of ME region to be updated +// Length - Length of ME region to be updated +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS CSP_ReportMEInfo +( + IN UINT8 Func_Num, + IN OUT UINT32* BASE_Address, + IN OUT UINT32* Length +) +{ + switch (Func_Num) + { + case 0: + + *BASE_Address = 0; + *Length = GetFlashCapacity() - FLASH_SIZE; + return EFI_UNSUPPORTED; + + break; + case 3: + // Flash the whole SPI but BIOS region + *BASE_Address = 0; + *Length = GetFlashCapacity() - FLASH_SIZE; + if (Is_SECOVR_JMPR && Is_MEFW) + return EFI_SUCCESS; + else + return EFI_UNSUPPORTED; + break; + default: + return EFI_UNSUPPORTED; + break; + } + return EFI_SUCCESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: HeciCallback +// +// Description: Locate Heci protocol callback +// +// Input: +// IN EFI_EVENT Event +// IN VOID *Context +// +// Output: +// VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID HeciCallback( + IN EFI_EVENT Event, + IN VOID *Context +) +{ + EFI_STATUS Status; + + Status = pBS->LocateProtocol ( + &gEfiHeciProtocolGuid, + NULL, + &mHeci + ); + + if(EFI_ERROR(Status)) + mHeci = NULL; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: MeFwUpdLclCallback +// +// Description: Locate ME Firmware update local protocol callback +// +// Input: +// IN CONST EFI_GUID *Protocol +// IN VOID *Interface +// IN EFI_HANDLE Handle +// +// Output: +// VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS MeFwUpdLclCallback ( + IN CONST EFI_GUID *Protocol, + IN VOID *Interface, + IN EFI_HANDLE Handle +) +{ + EFI_STATUS Status; + + Status = gSmst->SmmLocateProtocol( + &mMeFwUpdLclProtocolGuid , NULL, + &mMeFwUpdateLocalProtocol ); + if( EFI_ERROR(Status) ) + mMeFwUpdateLocalProtocol = NULL; + + return Status; +} +#if defined SecSMIFlash_SUPPORT && SecSMIFlash_SUPPORT == 1 +/** + * Callback funciotn on Secure SmiFlash Protocol for saving FW Capsule Buffer address. + * @param Protocol OPTIONAL + * @param Interface OPTIONAL + * @param Handle OPTIONAL + * @retval EFI_SUCCESS Secure SmiFlash Protocol installed. + * @retval EFI_NOT_FOUND Secure SmiFlash Protocol not install yet. +**/ +static +EFI_STATUS +SecSmiFlashProtocolCallback ( + IN const EFI_GUID *Protocol, + IN VOID *Interface, + IN EFI_HANDLE Handle +) +{ + EFI_SEC_SMI_FLASH_PROTOCOL *SecSmiFlash = NULL; + if (EFI_ERROR(pBS->LocateProtocol( \ + &gEfiSecSmiFlashProtocolGuid, NULL, &SecSmiFlash))) + return EFI_NOT_FOUND; + gFwCapsuleAddress = SecSmiFlash->pFwCapsule; + return EFI_SUCCESS; +} +#endif +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: CSP_MEUDInSmm +// +// Description: Get Host Firmware Status. +// If needed, Send LOCK if needed in SMM. +// +// Input: NONE +// +// Output: NONE +// +// Returns: NONE +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID CSP_MEUDInSmm(VOID) +{ + UINT32 Buffer32; + EFI_STATUS Status; + VOID *MeFwUpdLclReg = NULL; + +#if PI_SPECIFICATION_VERSION >= 0x1000A + + Status = pBS->LocateProtocol(&gEfiSmmBase2ProtocolGuid, NULL, &gSmmBase2); + if (EFI_ERROR(Status)) return; + + Status = gSmmBase2->GetSmstLocation (gSmmBase2, &gSmst); + if (EFI_ERROR(Status)) return; + +#endif + + Buffer32 = *(volatile UINT32 *)((UINTN)PCIEX_BASE_ADDRESS + \ + (UINTN)(HECI_BUS << 20) + (UINTN)(HECI_DEV << 15) + \ + (UINTN)(HECI_FUN << 12) + (UINTN)(0x40)); + + if(Buffer32 == 0xFFFFFFFF) + { + UINT8* pRCBA_DIS2 = (UINT8*)(SB_RCRB_BASE_ADDRESS + R_PCH_RCRB_FD2); + // Enable HECI Device + *pRCBA_DIS2 &= 0xFD; + // Read Again + pBS->Stall (1000);//1ms + Buffer32 = *(volatile UINT32 *)((UINTN)PCIEX_BASE_ADDRESS + \ + (UINTN)(HECI_BUS << 20) + (UINTN)(HECI_DEV << 15) + \ + (UINTN)(HECI_FUN << 12) + (UINTN)(0x40)); + // Follow Spec ,Disable HECI Device + *pRCBA_DIS2 |= 0x02; + } + // Check If Ignition FW + // ME 8.0 is no more Ignition FW, It should alway be FALSE + if (((Buffer32 >> 16) & 0x0F) == 1) + IsIgnition = TRUE; + else + IsIgnition = FALSE; + + // Check If GPIO33 Assert + if ( (((Buffer32 >> 16) & 0x0F) == 4) || (((Buffer32 >> 16) & 0x0F) == 5)) + { + Is_SECOVR_JMPR = TRUE; + Status = pBS->AllocatePages(AllocateAnyPages, + EfiReservedMemoryType, + EFI_SIZE_TO_PAGES (GetFlashCapacity()), + &RomBuffer); + if(EFI_ERROR(Status)) + RomBuffer = NULL; + + Status = pBS->AllocatePages(AllocateAnyPages, + EfiReservedMemoryType, + EFI_SIZE_TO_PAGES (FLASH_BLOCK_SIZE), + &BlockBuffer); + if(EFI_ERROR(Status)) + BlockBuffer = NULL; + }else + Is_SECOVR_JMPR = FALSE; + + // Check If ME FW + if ((((Buffer32 >> 16) & 0x0F) == 0) || + (((Buffer32 >> 16) & 0x0F) == 3) || + (((Buffer32 >> 16) & 0x0F) == 4) || + (((Buffer32 >> 16) & 0x0F) == 5)) + Is_MEFW = TRUE; + else + Is_MEFW = FALSE; + + //ME Firmware update local + Status = gSmst->SmmLocateProtocol( &mMeFwUpdLclProtocolGuid , NULL, + &mMeFwUpdateLocalProtocol ); + if( EFI_ERROR(Status) ) + { + gSmst->SmmRegisterProtocolNotify( &mMeFwUpdLclProtocolGuid, + MeFwUpdLclCallback, + &MeFwUpdLclReg ); + } + +#if defined SecSMIFlash_SUPPORT && SecSMIFlash_SUPPORT == 1 + { + //VOID *Registration; + // Create SecSmiFlash Protocol Callback to get and save the FwCapsule + // Address, because of the address could be cleared after calling the + // functions of Secure SMI Flash protocol. + //pSmst->SmmRegisterProtocolNotify(&gEfiSecSmiFlashProtocolGuid, \ + // SecSmiFlashProtocolCallback, &Registration); + SecSmiFlashProtocolCallback(NULL, NULL, NULL); + } +#endif +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: MEProcessHandleResult +// +// Description: Handle ME Process +// +// Input: +// UpdateResult +// Message +// Output: +// VOID +// +// Returns: +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +MEProcessHandleResult( + IN UINT16 Result, + IN CHAR8* Message +) +{ + StructPtr->UpdateResult = Result; + MemCpy((UINT8*)(StructPtr->ddMessageBuffer), + Message, Strlen(Message)); + + *(CHAR8*)(StructPtr->ddMessageBuffer + Strlen(Message)) = 0; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: HandleBuffer +// +// Description: Init the Length and Offset need to be updated +// If needed, send ENABLE MESSAGE +// +// Input: +// UpdateResult +// Message +// Output: +// VOID +// +// Returns: +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +HandleBuffer( + IN OUT UINT32* ProgramOffset, + IN OUT UINT32* ProgramLength, + IN OUT UINT8* Step, + IN BOOLEAN InSmm +) +{ + EFI_STATUS Status; + UINT32 Offset, Length; + UINT32 HFS = GetHFS(); + + switch(StructPtr->bBlockType) + { + case FDT_BLK: + Status = GetRegionOffset(0, &Offset, &Length); + *Step = 0; + break; + + case PDR_BLK: + Status = GetRegionOffset(4, &Offset, &Length); + if(Status == EFI_NOT_FOUND) + return EFI_UNSUPPORTED; + *Step = 0; + break; + + case GBE_BLK: + Status = GetRegionOffset(3, &Offset, &Length); + if(Status == EFI_NOT_FOUND) + return EFI_UNSUPPORTED; + // Store Mac address + if(Length) + { + UINT8* Address = (UINT8*)FLASH_BASE_ADDRESS(Offset); + FlashRead(Address, MacAddr, 6); + } + *Step = 0; + break; + + case ME_BLK: + Status = GetRegionOffset(2, &Offset, &Length); + if((HFS & BIT05) || (HFS & BIT10)) + *Step = 2; + else + *Step = 1; + + break; + default: + *Step = 0; + return EFI_UNSUPPORTED; + break; + } + *ProgramOffset = Offset; + *ProgramLength = Length; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: UpdateRegions +// +// Description: UpdateRegions +// +// Input: +// Buffer +// +// Output: +// VOID +// +// Returns: +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +UpdateRegions( + IN UINT8* Buffer, + IN BOOLEAN InSmm +) +{ + static UINT32 Offset, Length; + UINT8* Address; + EFI_STATUS Status; + BOOLEAN FlashStatus = TRUE, NeedToVerify = FALSE; + static UINT8 Step = 0; + static BOOLEAN NewRegion; + UINTN Counter = 0; + static UINT8* ProgramBuffer; + UINT8* BufferForVerify = (UINT8*)BlockBuffer; + UINT32 i; + // Prepare Offset and Length to be updated + // If BIT02 , update buffer + if((StructPtr->bHandleRequest & BIT02)) + { + Status = HandleBuffer(&Offset, &Length, &Step, InSmm); + if(EFI_ERROR(Status)) + { + MEProcessHandleResult(BIT03, + "UN SUPPORT TYPE"); + return Status; + } + // Frist In + NewRegion = TRUE; + ProgramBuffer = (UINT8*)(Phy_Address + Offset); + } + + // Set MAC address to buffer + if(((StructPtr->bBlockType) == GBE_BLK) && NewRegion) + MemCpy((Buffer + Offset),MacAddr,6); + + if(NewRegion) + { + NewRegion = FALSE; + } + + Address = (UINT8*)FLASH_BASE_ADDRESS(Offset); + FlashBlockWriteEnable(Address); + + FlashEraseCommand(Address); + + // System hangs when using physical address. + // So, verify erase complete or not. + FlashStatus = TRUE; + FlashReadCommand(Address, BufferForVerify, FLASH_BLOCK_SIZE); + + for(i = 0 ; (i < FLASH_BLOCK_SIZE) && (*(BufferForVerify + i) == 0xFF) ; i++); + if(i != FLASH_BLOCK_SIZE) + FlashStatus = FALSE; + if(FlashStatus) + { + FlashProgramCommand(Address, ProgramBuffer, FLASH_BLOCK_SIZE); + FlashReadCommand(Address, BufferForVerify, FLASH_BLOCK_SIZE); + for(i = 0 ; (i < FLASH_BLOCK_SIZE) && (*(BufferForVerify + i) == *(BufferForVerify + i)) ; i++); + if(i != FLASH_BLOCK_SIZE) + FlashStatus = FALSE; + if(FlashStatus) + Status = EFI_SUCCESS; + else + Status = EFI_DEVICE_ERROR; + }else + Status = EFI_DEVICE_ERROR; + FlashBlockWriteDisable(Address); + ProgramBuffer = ProgramBuffer + FLASH_BLOCK_SIZE; + Length -= FLASH_BLOCK_SIZE; + Offset += FLASH_BLOCK_SIZE; + + // End of Region Update + if(Length == 0) + { + NewRegion = TRUE; + } + // TODO : + // OEM can output message here in every block updated. + // Remember to Set BIT02 + else + { + MEProcessHandleResult((BIT01), + " "); + return EFI_SUCCESS; + } + // Show Strings + if(!EFI_ERROR(Status)) + { + + switch(StructPtr->bBlockType) + { + case FDT_BLK: + MEProcessHandleResult((BIT03 | BIT02), + "Update success for /FDT!!"); + break; + case PDR_BLK: + MEProcessHandleResult((BIT03 | BIT02), + "Update success for /PDR!!"); + break; + case GBE_BLK: + MEProcessHandleResult((BIT03 | BIT02), + "Update success for /GBE!!"); + break; + + case ME_OPR_BLK: + MEProcessHandleResult((BIT03 | BIT02), + "Update success for /OPR!!"); + break; + + default: + MEProcessHandleResult((BIT03 | BIT02), + "Update success for /MER!!"); + break; + } + }else + { + switch(StructPtr->bBlockType) + { + case FDT_BLK: + MEProcessHandleResult((BIT03 | BIT02), + "/FDT is Locked !!"); + break; + + default: + MEProcessHandleResult((BIT00 | BIT02), + "Update Fail !!"); + break; + } + } + + return EFI_SUCCESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: MEProcessHandler +// +// Description: Handle ME Process +// +// Input: +// VOID +// Output: +// OFBD_TC_55_ME_PROCESS_STRUCT +// +// Returns: +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +MEProcessHandler +( + IN OUT OFBD_TC_55_ME_PROCESS_STRUCT **MEProcessStructPtr +) +{ + EFI_STATUS Status; + static UINTN NumberOfPages; + static UINT32 SizeCopied; + static BOOLEAN UseSmmMem = FALSE; + static EFI_PHYSICAL_ADDRESS SMM_Address; + static UINT8 HeciIsHide = 0; + static BOOLEAN UseMeFwUpdLcl = FALSE; + static UINTN BufferLength = 0; + + StructPtr = *MEProcessStructPtr; + switch(StructPtr->bHandleRequest) + { + // Allocate Buffer + case 1: +/* + if ((Mmio32(SB_RCBA, 0x3428) & BIT01) != 0) + { + MmioRW32((SB_RCBA+0x3428), 0, BIT01); + HeciIsHide = 1; + } +*/ + NumberOfPages = StructPtr->TotalBlocks; +#if PI_SPECIFICATION_VERSION >= 0x1000A + Status = gSmst->SmmAllocatePages(AllocateAnyPages, +#else + Status = pSmst->SmmAllocatePages(AllocateAnyPages, +#endif + EfiRuntimeServicesData, NumberOfPages, &SMM_Address); + if(!EFI_ERROR(Status)) + { + UseSmmMem = TRUE; + Phy_Address = SMM_Address; + }else + Phy_Address = RomBuffer; + // No memory allocated + if(!Phy_Address) + { + if( ( mMeFwUpdateLocalProtocol != NULL ) && + ( mMeFwUpdateLocalProtocol->FwUpdBufferAddress != NULL ) ) + { + UseMeFwUpdLcl = TRUE; + Phy_Address = mMeFwUpdateLocalProtocol->FwUpdBufferAddress; + BufferLength = mMeFwUpdateLocalProtocol->FwUpdBufferLength; + SizeCopied = 0; + break; + } + MEProcessHandleResult((BIT00 | BIT02), + "Error : No Memory Allocated!!"); + } + SizeCopied = 0; + break; + + // Recieve Data from AFU + case 2: + if( UseMeFwUpdLcl && + ( SizeCopied + StructPtr->ddMeDataSize > BufferLength ) ) + { + MEProcessHandleResult((BIT00 | BIT02), + "Error : No Memory Allocated!!"); + SizeCopied = 0; + break; + } + MemCpy((UINT8*)(Phy_Address + SizeCopied), + (UINT8*)StructPtr->ddMeDataBuffer,StructPtr->ddMeDataSize); + SizeCopied += StructPtr->ddMeDataSize; + + break; + + // Update + case 4: +#if (OFBD_VERSION >= 0x0220) + DoNotConvert = TRUE; +#endif + UpdateRegions((UINT8*)Phy_Address, TRUE); + break; + + // Continue.... + case 8: + UpdateRegions((UINT8*)Phy_Address, TRUE); + break; + + // Free Buffer + case 0x10: +#if (OFBD_VERSION >= 0x0220) + DoNotConvert = FALSE; +#endif + if(UseSmmMem) +#if PI_SPECIFICATION_VERSION >= 0x1000A + gSmst->SmmFreePages(Phy_Address, NumberOfPages); +#else + pSmst->SmmFreePages(Phy_Address, NumberOfPages); +#endif + + +// if (HeciIsHide) +// MmioRW32((SB_RCBA+0x3428), BIT01, 0); + break; + + case 0x20: + if( UseMeFwUpdLcl ) + mMeFwUpdateLocalProtocol->FwUpdLcl( mMeFwUpdateLocalProtocol, (UINT8*)Phy_Address, SizeCopied ); + break; + +#if defined SecSMIFlash_SUPPORT && SecSMIFlash_SUPPORT == 1 + // ME FW Capsule Update functions. + case 3: // ME FW Capsule Update. (ME FW only) + case 5: // ME FW Capsule Update. (BIOS + ME FW) + if (!gFwCapsuleAddress) { + MEProcessHandleResult((BIT00 | BIT02), "Error : Functon Not Supported!!"); + break; + } + Phy_Address = 0; + if ((StructPtr->bHandleRequest == 3) && \ + (StructPtr->TotalBlocks <= EFI_SIZE_TO_PAGES(FWCAPSULE_IMAGE_SIZE))) { + // Function#3 : ME FW Update only, upload ME FW capsule from the beggining. + Phy_Address = (EFI_PHYSICAL_ADDRESS)gFwCapsuleAddress; + } + if ((StructPtr->bHandleRequest == 5) && \ + (StructPtr->TotalBlocks <= \ + EFI_SIZE_TO_PAGES(FWCAPSULE_IMAGE_SIZE - FLASH_SIZE))) { + // Function#5 : BIOS + ME FW Update, upload capsule from the end of BIOS. + Phy_Address = (EFI_PHYSICAL_ADDRESS)gFwCapsuleAddress + FLASH_SIZE; + } + if (!Phy_Address) MEProcessHandleResult((BIT00 | BIT02), "Error : Buffer Too Small!!"); + break; +#endif // #if SecSMIFlash_SUPPORT == 1 + } +} +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2005, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 6145-F Northbelt Pkwy, Norcross, GA 30071 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Chipset/eM/ME/MEUD/CSP_MEUD.cif b/Chipset/eM/ME/MEUD/CSP_MEUD.cif new file mode 100644 index 0000000..be0b236 --- /dev/null +++ b/Chipset/eM/ME/MEUD/CSP_MEUD.cif @@ -0,0 +1,14 @@ +<component> + name = "CSP : ME 8.0 Firmware Update" + category = ModulePart + LocalRoot = "\Chipset\eM\ME\MEUD" + RefName = "CSP_MEUD" +[files] +"CSP_MEUD.c" +"CSP_MEUD.h" +"CSP_MEUD.sdl" +"CSP_MEUD.mak" +[parts] +"MEFwUpdLcl" +"MeFwCapsule" +<endComponent> diff --git a/Chipset/eM/ME/MEUD/CSP_MEUD.h b/Chipset/eM/ME/MEUD/CSP_MEUD.h new file mode 100644 index 0000000..85b511c --- /dev/null +++ b/Chipset/eM/ME/MEUD/CSP_MEUD.h @@ -0,0 +1,86 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2009, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* +//************************************************************************* +// $Header: /Alaska/SOURCE/Modules/OFBD Intel ME Update/CSP_MEUD/ME80/CSP_MEUD.h 2 5/16/13 6:30a Klzhan $ +// +// $Revision: 2 $ +// +// $Date: 5/16/13 6:30a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/OFBD Intel ME Update/CSP_MEUD/ME80/CSP_MEUD.h $ +// +// 2 5/16/13 6:30a Klzhan +// [TAG] EIPNone +// [Category] Improvement +// [Description] Add define for flash commands. +// +// 1 4/22/11 2:47a Klzhan +// Initial check - in +// +// +//********************************************************************** +//<AMI_FHDR_START> +// +// Name: CSP_MEUD.h +// +// Description: +// +//<AMI_FHDR_END> +//********************************************************************** +#ifndef _EFI_CSP_MEUD_H_ +#define _EFI_CSP_MEUD_H_ +#ifdef __cplusplus +extern "C" { +#endif + +VOID +FlashReadCommand ( + IN volatile UINT8* pByteAddress, + OUT UINT8 *Byte, + IN UINT32 Length +); + +VOID +FlashProgramCommand ( + IN volatile UINT8* pByteAddress, + IN UINT8 *Byte, + IN UINT32 Length +); + +VOID +FlashEraseCommand ( + IN volatile UINT8* pBlockAddress +); + +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2009, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/eM/ME/MEUD/CSP_MEUD.mak b/Chipset/eM/ME/MEUD/CSP_MEUD.mak new file mode 100644 index 0000000..bc4e861 --- /dev/null +++ b/Chipset/eM/ME/MEUD/CSP_MEUD.mak @@ -0,0 +1,133 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2009, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* +#************************************************************************* +# $Header: /Alaska/SOURCE/Modules/OFBD Intel ME Update/CSP_MEUD/ME80/CSP_MEUD.mak 5 5/14/15 4:33a Tristinchou $ +# +# $Revision: 5 $ +# +# $Date: 5/14/15 4:33a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/OFBD Intel ME Update/CSP_MEUD/ME80/CSP_MEUD.mak $ +# +# 5 5/14/15 4:33a Tristinchou +# [TAG] EIP215437 +# [Category] New Feature +# [Description] ME capsule update support on SharkBay +# +# 4 8/23/13 4:14a Tristinchou +# [TAG] EIPNone +# [Category] Improvement +# [Description] Fix build error with CrescentBay project. +# +# 3 9/07/12 4:46a Klzhan +# Support ME 9. +# +# 2 3/08/12 6:00a Klzhan +# Support AFU new command +# +# 1 4/22/11 2:47a Klzhan +# Initial check - in +# +# +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: CSP_MEUD.mak +# +# Description: +# +#<AMI_FHDR_END> +#********************************************************************** +#--------------------------------------------------------------------------- +# Create CSP ME FW Update Component +#--------------------------------------------------------------------------- +all : CSP_MEUD + +CSP_MEUD : $(BUILD_DIR)\CSP_MEUD.mak CSP_MEUDBin + +$(BUILD_DIR)\CSP_MEUD.mak : $(MEUD_CSP_DIR)\CSP_MEUD.cif $(MEUD_CSP_DIR)\CSP_MEUD.mak $(BUILD_RULES) + $(CIF2MAK) $(MEUD_CSP_DIR)\CSP_MEUD.cif $(CIF2MAK_DEFAULTS) + +CSP_MEUD_DEFINES=\ + $(MY_DEFINES) /D __EDKII_GLUE_BASE_MEMORY_LIB__\ + /D __EDKII_GLUE_EDK_DXE_RUNTIME_DRIVER_LIB__\ + /D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__\ + +CSP_MEUD_INCLUDES = \ + $(EdkIIGlueLib_INCLUDES)\ + $(ME_INCLUDES) \ + $(EdkIIGlueLib_INCLUDES) \ + $(ME_INCLUDES) \ + $(MeLibSmm_DIR) \ + $(MeProtocolLib_DIR) \ + $(MeProtocolLib_DIR)\SmmHeci \ + /I$(PROJECT_DIR)\Core\EM\OFBD\ +!IFDEF INTEL_COUGAR_POINT_INCLUDE_DIR + /I$(INTEL_COUGAR_POINT_INCLUDE_DIR) +!ELSE + /I$(INTEL_PCH_INCLUDE_DIR) +!ENDIF + + +CSP_MEUD_LIBS=\ + $(MeLibSmm_LIB)\ + $(EfiScriptLib_LIB)\ + $(EdkIIGlueBaseLib_LIB)\ + $(EDKFRAMEWORKPROTOCOLLIB)\ + $(EFIPROTOCOLLIB)\ +!IF "$(x64_BUILD)"=="1" + $(EdkIIGlueBaseLibX64_LIB)\ +!ELSE + $(EdkIIGlueBaseLibIA32_LIB)\ +!ENDIF + $(EdkIIGlueDxeReportStatusCodeLib_LIB)\ + $(EdkIIGluePeiDxeDebugLibReportStatusCode_LIB)\ + $(EdkIIGlueUefiBootServicesTableLib_LIB)\ + $(EdkIIGlueUefiDevicePathLib_LIB)\ + $(EdkIIGlueBasePciLibPciExpress_LIB)\ + $(EdkIIGlueBasePciExpressLib_LIB)\ + $(EdkIIGlueDxeMemoryAllocationLib_LIB)\ + $(EFIGUIDLIB)\ + $(EDKPROTOCOLLIB)\ + $(EdkIIGlueBaseIoLibIntrinsic_LIB)\ + $(EdkIIGlueBaseMemoryLib_LIB)\ + $(EdkIIGlueEdkDxeRuntimeDriverLib_LIB)\ + $(EdkIIGlueUefiLib_LIB)\ + $(EdkIIGlueDxeHobLib_LIB)\ + +CSP_MEUDBin : $(CSP_MEUD_LIBS) + @set INCLUDE=%%INCLUDE%% + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\CSP_MEUD.mak all\ + "MY_INCLUDES=$(CSP_MEUD_INCLUDES)" \ + "MY_DEFINES=$(CSP_MEUD_DEFINES)"\ + NAME=CSP_MEUD \ + TYPE=LIBRARY LIBRARY_NAME=$(CSP_MEUDLIB) + +$(CSP_MEUDLIB) : CSP_MEUD +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2009, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/CSP_MEUD.sdl b/Chipset/eM/ME/MEUD/CSP_MEUD.sdl new file mode 100644 index 0000000..458562c --- /dev/null +++ b/Chipset/eM/ME/MEUD/CSP_MEUD.sdl @@ -0,0 +1,47 @@ +TOKEN + Name = CSP_MEUD_SUPPORT + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable ME Firmware Update Chipset function in Project" +End + +TOKEN + Name = "CSP_MEUDLIB" + Value = "$(BUILD_DIR)\CSP_MEUD.lib" + TokenType = Expression + TargetMAK = Yes +End + +MODULE + Help = "Includes MEUD.mak to Project" + File = "CSP_MEUD.mak" +End + +PATH + Name = "MEUD_CSP_DIR" +End + +ELINK + Name = "$(BUILD_DIR)\CSP_MEUD.lib" + Parent = "OFBDLISTLIB" + InvokeOrder = AfterParent +End + +TOKEN + Name = "pSPIBASE" + Value = "$(SB_RCBA) + $(SPI_BASE_ADDRESS)" + TokenType = Integer + TargetH = Yes + Help = "Fill SPI_BASE." +End + +TOKEN + Name = "BITS_OF_SPI_DENSITY" + Value = "1" + TokenType = Integer + TargetH = Yes + Help = "Please check Flash Descriptor Component Section in SPI Programming Guid, 0 = 3 BITs for Density , 1 = 4 BITs for Density" +End
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/IntelLib/FWUpdateLib.h b/Chipset/eM/ME/MEUD/MEFwUpdLcl/IntelLib/FWUpdateLib.h new file mode 100644 index 0000000..062fe89 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/IntelLib/FWUpdateLib.h @@ -0,0 +1,566 @@ +/*++ + +This file contains a 'Sample Driver' and is licensed as such +under the terms of your license agreement with Intel or your +vendor. This file may be modified by the user, subject to +the additional terms of the license agreement + +--*/ + +/*++ + +Copyright (c) 2009-13 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + + +Module Name: + + FwUpdateLib.h + +Abstract: + + FW Update Local Sample Code Header file + +--*/ + +#define INVALID_DATA_FORMAT_VERSION 0 +#define INVALID_MANIFEST_DATA 1 +#define NO_FPT_IMAGE 2 +#define MANIFEST_BUFFER 0x1000 +#define FPT_PARTITION_NAME_FPT 0x54504624 + +//===== +#define bool BOOLEAN + +extern +InitializeLib( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +); + +void _fltused(); + +typedef UINT32 STATUS; + +typedef struct { + UINT16 Major; + UINT16 Minor; + UINT16 Hotfix; + UINT16 Build; +} FWVersion; + +typedef struct { + FWVersion code; + FWVersion rcvy; +} FlashVersion; + +typedef struct +{ + unsigned long Data1; + unsigned short Data2; + unsigned short Data3; + unsigned char Data4[8]; +} _UUID; + +typedef enum +{ + FWU_ENV_MANUFACTURING = 0, // Manufacturing update + FWU_ENV_IFU, // Independent Firmware update +}FWU_ENVIRONMENT; + +enum errorValues { + FWU_ERROR_SUCCESS, + FWU_IME_NO_DEVICE = 8193, + FWU_UPD_VER_MIS = 8199, + FWU_VER_GET_ERR = 8204, + FWU_CERT_ERR = 8213, + FWU_REBOOT_NEEDED = 8703, + FWU_SKU_MISMATCH, + FWU_VER_MISMATCH, + FWU_SGN_MISMATCH, + FWU_GENERAL, + FWU_UPD_PROCESS, + FWU_NO_MEMORY = 8710, + FWU_AUTH = 8712, + FWU_IMG_HEADER, + FWU_FILE_OPEN, + FWU_HTTP_ERROR, + FWU_USAGE_ERROR, + FWU_HOSTNAME, + FWU_UPDATE_TIMEOUT, + FWU_LOCAL_DIS, + FWU_SECURE_DIS, + FWU_IME_UN_SUP_MESS = 8722, + FWU_NO_UPDATE, + FWU_IME_NOT_READY, + FWU_LAST_STATUS, + FWU_GET_VER_ERR = 8727, + FWU_IME_SMALL_BUFF, + FWU_WSMAN_NO = 8734, + FWU_UNSUPPRT_OS = 8740, + FWU_ERROR_FW, + FWU_HECI, + FWU_UNSUPPRT_PLAT, + FWU_VERIFY_OEM_ID_ERR, + FWU_INVALID_OEM_ID = 8745, + FWU_INVALID_IMG_LENGTH, + FWU_GLBL_BUFF_UNAVAILABLE, + FWU_INVALID_FW_PARAMS, + FWU_AMT_STATUS_INTERNAL_ERROR, + FWU_AMT_STATUS_NOT_READY = 8750, + FWU_AMT_STATUS_INVALID_AMT_MODE, + FWU_AMT_STATUS_INVALID_MESSAGE_LENGTH, + FWU_SAVE_RESTORE_POINT_ERROR, + FWU_FILE_WRITE, + FWU_GET_BLIST_ERROR = 8755, + FWU_CHECK_VERSION_ERROR, + FWU_DISPLAY_FW_VERSION, + FWU_IMAGE_UNDER_VCN, + FWU_IMAGE_VER_HIST_CHK_FAIL, + FWU_DOWNGRADE_VETOED = 8760, + FWU_FW_WRITE_FILE_FAIL, + FWU_FW_READ_FILE_FAIL, + FWU_FW_DELETE_FILE_FAIL, + FWU_PARTITION_LAYOUT_NOT_COMP, + FWU_DOWNGRADE_NOT_ALLOWED_DATA_MISMATCH = 8765, + FWU_UPDATE_PASSWORD_NOT_MATCHED, + FWU_UPDATE_PASSWORD_EXCEED_MAXIMUM_RETRY, + FWU_UPDATE_PASSWORD_NOT_PROVIDED, + FWU_UPDATE_POLLING_FAILED, + FWU_FILE_ALREADY_EXISTS = 8770, + FWU_FILE_INVALID, + FWU_USAGE_ERROR_B, + FWU_AUDIT_POLICY_FAILURE, + FWU_ERROR_CREATING_FT, + FWU_SAL_NOTIFICATION_ERROR = 8775, + FWU_GET_PATTRIB_ERROR, + FWU_GET_UPD_INFO_STATUS, + FWU_PID_NOT_EXPECTED, + FWU_UPDATE_INRECOVERY_MODE_RESTRICT_UPDATE_TO_ATTEMPTED_VERSION, + FWU_BUFFER_COPY_FAILED, + FWU_GET_ME_FWU_INFO, + FWU_APP_REGISTER_OS_FAILURE, + FWU_APP_UNREGISTER_OS_FAILURE, + FWU_INVALID_PARTID, + FWU_LIVE_PING_FAILURE, + FWU_SERVICE_CONNECT_FAILURE, + FWU_SERVICE_NOT_AVAILABLE, + FWU_SERVICE_BUSY, + FWU_USER_NOT_ADMIN, + FWU_WMI_FAIL, + FWU_CHK_BIT_LOCKER_FAIL, + FWU_REG_CMD_FAIL, + FWU_UPDATE_IMAGE_BLACKLISTED, + FWU_DOWNGRADE_NOT_ALLOWED_SVN_RESTRICTION +}; +//===== + + +// below structure is defiend by the fw team +// in fwucommon.h file +typedef struct _UPDATE_FLAGS_LIB +{ + unsigned int RestorePoint:1; // If set indicate restore point + unsigned int RestartOperation:1; // If set indicate restart operation, like lost hard drive etc... + unsigned int UserRollback:1; // indicates user has initiated a rollback + unsigned int Reserve:29; // +}UPDATE_FLAGS_LIB; + +// Used by the tool to perform FULL FW update +typedef enum _UPDATE_TYPE +{ + DOWNGRADE_SUCCESS = 0, + DOWNGRADE_FAILURE, + SAMEVERSION_SUCCESS, + SAMEVERSION_FAILURE, + UPGRADE_SUCCESS, + UPGRADE_PROMPT +}UPDATE_TYPE; + +//Image type to validate the binary sent to update +//For Full Update - only FULL image type is valid +//For Partial Update - only FULL and PARTIAL image type is valid +//FULL Image => Image with Flash Partition Table, FTPR, and NFTPR +//PARTIAL Image => Image with no Flash Partition Table or FTPR or NFTPR, +// only WCOD or LOCL +typedef enum _IMAGE_TYPE +{ + FULL = 0, + PARTIAL, + RESTORE, + INVALID +}IMAGE_TYPE; + +typedef enum _SKU_TYPE { + SKU_1_5_MB = 0, + SKU_5_MB, + SKU_INVALID +}SKU_TYPE; + +//Used by the tool to retrieve FW version information +typedef struct { + unsigned short Major; + unsigned short Minor; + unsigned short Hotfix; + unsigned short Build; +} VersionLib; + +//Should be used by both tool and UNS to retrieve the Updated UPV version +typedef struct _IPU_UPDATED_INFO +{ + unsigned int UpdatedUpvVer;//Version from the update image file that is for updating IPU + unsigned int Reserved[4]; +}IPU_UPDATED_INFO; + +// disable the "zero-sized array" warning +#pragma warning(disable:4200) +typedef enum _FWU_STATUS { + FWU_STATUS_SUCCESS = 0, + FWU_STATUS_NO_MEMORY = 1, + FWU_STATUS_NOT_READY = 2, + FWU_STATUS_ILLEGAL_LENGTH = 3, + FWU_STATUS_AUTHENTICATION_FAILED = 4, + FWU_STATUS_INTERNAL_ERROR = 5, + FWU_STATUS_SKU_FAILURE = 6, + FWU_STATUS_VERSION_FAILURE = 7 +}FWU_STATUS; + +// From FWU_if.h + +#pragma pack(1) + +/** + * FWU_GET_INFO_MESSAGE - get version + * + * @MessageType: FWU_MESSAGE_TYPE_GET_INFO + */ +typedef struct { + UINT32 MessageType; +} FWU_GET_INFO_MESSAGE; + +/** + * FWU_DATA_MESSAGE - data fragment of the image + * + * @MessageType: FWU_MESSAGE_TYPE_DATA + * @Length: The length of the data field, in Little Endian + * @Reserved: Reserved, must be 0 + * @Data: The data of the image fragment + */ +typedef struct { + UINT32 MessageType; + UINT32 Length; + UINT8 Reserved[3]; +#ifndef _DOS + UINT8 Data[0]; +#endif +} FWU_DATA_MESSAGE; + +#pragma pack() + +bool +IsUpdateStatusPending ( + IN UINT32 status +) +/*++ + +Routine Description: + + Checks if ME FW Update client is ready to accept an update + +Arguments: + + +Returns: + + true if ready + +--*/ +; + +unsigned int +CheckPolicyBuffer ( + IN char* buffer, + IN int bufferLength, + IN int AllowSV, + IN UPDATE_TYPE *Upd_Type, + IN VersionLib *ver +) +/*++ + +Routine Description: + + This routine determines if the update is allowed given the ME Upgrade/downgrade/same version policy + +Arguments: + +Returns: + + FWU_ERROR_SUCCESS if operation allowed + +--*/ +; + +unsigned int +FwUpdateFullBuffer ( + IN char *buffer, + IN unsigned int bufferLength, + IN char *_pwd, + IN int _forceResetLib, + IN unsigned int UpdateEnvironment, + IN _UUID OemID, + IN UPDATE_FLAGS_LIB update_flags, + IN void(*func)(float, float) +) +/*++ + +Routine Description: + + This routine sends the buffer to the ME FW Update Client + +Arguments: + +Returns: + + FWU_ERROR_SUCCESS if operation allowed + +--*/ +; + +unsigned int +FWUpdate_QueryStatus_Get_Response ( + IN unsigned int *UpdateStatus, + IN unsigned int *TotalStages, + IN unsigned int *PercentWritten, + IN unsigned int *LastUpdateStatus, + IN unsigned int *LastResetType +) +/*++ + +Routine Description: + + This routine queries the ME Kernel for the update status + +Arguments: + +Returns: + + FWU_ERROR_SUCCESS if operation allowed + +--*/ +; + +bool +VerifyOemId( + IN _UUID id +) +/*++ + +Routine Description: + + The ME FW when created has an OEM ID embedded in it. For security + reasons, we need to verify that the OEM ID of the application (mOemID) + matches the OEM ID of the ME FW. + + NOTE: A connection to the client is required before this routine is + executed. + +Arguments: + + UUID to check + + +Returns: + + true or false indicating if the match was succesfull + +--*/ +; + +EFI_STATUS +GetLastStatus( + OUT UINT32 *LastFwUpdateStatus +) +/*++ + +Routine Description: + + Get the last status of the FW Update Client - this is used to determine if a previous update + requires a reboot + +Arguments: + + UINT32 pointer for results of previous update. + + +Returns: + + EFI Error code + +--*/ +; + +EFI_STATUS +GetLastUpdateResetType ( + OUT UINT32 *LastResetType +)/*++ + +Routine Description: + + Get the last status of the FW Update Client - this is used to determine if a previous update + requires a reboot + +Arguments: + + UINT32 pointer for results of previous update. + + +Returns: + + EFI Error code + +--*/ +; + +EFI_STATUS +GetInterfaces ( + OUT UINT16 *interfaces +) +; + +EFI_STATUS +CheckVersion( + IN UINT8 *FileBuffer, + IN BOOLEAN AllowSV, + OUT FlashVersion *FlashVersion, + OUT UINT32 *LastFwUpdateStatus +) +/*++ + +Routine Description: + + Policy routine to verify if the current FW version is older + than the version in the image. + + The routine will return the result of a previous ME FW Update. If a reset is required + before an update can occur, the return value will indicate it + + NOTE: A connection to the client is required before this routine is + executed. + +Arguments: + + UINT8 pointer to update image + BOOLEAN indicating TRUE for same version update + FlashVersion pointer for return version numbers of FW Update image + UINT32 pointer for results of previous update. + + +Returns: + + EFI_UNSUPPORTED if version is of update image is not supported + +--*/ +; + +EFI_STATUS +StartUpdate( + IN UINT8 *FileBuffer, + IN UINT32 FileLength, + IN CHAR8 *Password, + IN VOID (*DataProgressProc)(), + IN UINT32 DataProgessSteps, + OUT STATUS *FWU_Status +) +/*++ + +Routine Description: + + Start the update process by asking the ME FW Update client + to allocate a buffer for the image. Note that the ME does not update the flash until + the FWU_END message is received. + + If the current ME Flash image is password protected, then that password is required to unlock + the update process + + Because the process of downloading the image is time consuming, a callback is provided for each + chunk of data sent to the ME FW Update client. If desired, the caller can specify the number of steps + that the total data send will have (e.g. 100 means a total of 100 callbacks for the entire duration). The + number of steps supplied will be divided by the total result of (FileLength / Chunksize) + 1. + +Arguments: + + UINT8 pointer to FW Update Image + UINT32 FW Update image length + CHAR16 pointer to password (if no password then NULL) + VOID pointer to callback function (if no callback then NULL) + UINT32 callback steps (1 means each packet sent will trigger a callback) + UINT32 pointer to ME FW Update Client return status + +Returns: + + EFI_STATUS + +--*/ +; + +EFI_STATUS +EndUpdate ( + IN VOID (*EndProgressProc)(), + IN UINT32 EndProgressSteps, + OUT STATUS *FWU_Status +) +/*++ + +Routine Description: + + Send the FWU_END message to the ME after a successful data download. + This operation will request the ME to validate the image and update the + flash. Depending on flash speed, the operation may take serveral minutes + to finish. Be patient... + + Because the process of updating the image is time consuming, a callback is provided each delay (5 seconds) + that occurs waiting for the ME FW Update client to respond. If desired, the caller can specify a number of timeouts before + a callback (e.g. 1 means send wait 5 seconds then invoke the callback routine). + +Arguments: + + VOID pointer to callback function (if no callback then NULL) + UINT32 callback ratio (1 means wait 5 seconds and then trigger a callback) + UINT32 pointer to ME FW Update Client return status + +Returns: + + EFI_STATUS + +--*/ +; + +EFI_STATUS +GetFwFlashVersion( + IN FWVersion *fwVersion +) +/*++ + +Routine Description: + + Get the FW version of the currently running ME FW + + NOTE: A connection to the client is required before this routine is + executed. + +Arguments: + + FWVersion pointer to FW Flash version + +Returns: + + EFI_STATUS + +--*/ +;
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/IntelLib/FWUpdateLib.lib b/Chipset/eM/ME/MEUD/MEFwUpdLcl/IntelLib/FWUpdateLib.lib Binary files differnew file mode 100644 index 0000000..267f5a6 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/IntelLib/FWUpdateLib.lib diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/IntelLib/me_status.h b/Chipset/eM/ME/MEUD/MEFwUpdLcl/IntelLib/me_status.h new file mode 100644 index 0000000..5a66448 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/IntelLib/me_status.h @@ -0,0 +1,986 @@ +/*++ + +INTEL CONFIDENTIAL +Copyright 2005-2013 Intel Corporation All Rights Reserved. + +The source code contained or described herein and all documents +related to the source code ("Material") are owned by Intel Corporation +or its suppliers or licensors. Title to the Material remains with +Intel Corporation or its suppliers and licensors. The Material +contains trade secrets and proprietary and confidential information of +Intel or its suppliers and licensors. The Material is protected by +worldwide copyright and trade secret laws and treaty provisions. No +part of the Material may be used, copied, reproduced, modified, +published, uploaded, posted, transmitted, distributed, or disclosed in +any way without Intel's prior express written permission. + +No license under any patent, copyright, trade secret or other +intellectual property right is granted to or conferred upon you by +disclosure or delivery of the Materials, either expressly, by +implication, inducement, estoppel or otherwise. Any license under such +intellectual property rights must be express and approved by Intel in +writing. + +File Name: + + me_status.h + +Abstract: + + Defines the ME Status codes + +Authors: + + Hemaprabhu Jayanna + +--*/ + +#ifndef _ME_STATUS_H_ +#define _ME_STATUS_H_ + +/////////////////////////////////////////////////////////////////////////////// +// ERROR & STATUS CODE RANGES // +/////////////////////////////////////////////////////////////////////////////// +// RANGE // DESCRIPTION // +/////////////////////////////////////////////////////////////////////////////// +// 0x0000FFFF - 0x00000000 // Pre-defined standard error values used by all // +// // ME Components and interfaces // +/////////////////////////////////////////////////////////////////////////////// +// 0x0001FFFF - 0x00010000 // Capability Module specific error codes // +/////////////////////////////////////////////////////////////////////////////// +// 0xFFFFFFFF - 0x00020000 // Reserved for future use. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// KERNEL STATUS AND ERROR CODES // +//The following are the status and error codes returned by the ME Kernel. // +//ThreadX Codes range from (0x00 to 0x7F) // +//Other Kernel codes range from (0x80 to 0xFF) // +/////////////////////////////////////////////////////////////////////////////// + + + + +// +//STATUS_SUCCESS +// The operation completed successfully. +// + +/** + * @brief The operation completed successfully. + */ +#define STATUS_SUCCESS 0x0 + +// +//STATUS_DELETED +// The requested object has been deleted. +// +#define STATUS_DELETED 0x1 + +// +//STATUS_POOL_ERROR +// An invalid memory pool pointer (NULL) was given or the pool is +// already created. +// +#define STATUS_POOL_ERROR 0x2 + +// +//STATUS_PTR_ERROR +// An invalid pointer was provided. +// +#define STATUS_PTR_ERROR 0x3 + +// +//STATUS_WAIT_ERROR +// The specified wait option is invalid. +// +#define STATUS_WAIT_ERROR 0x4 + +// +//STATUS_SIZE_ERROR +// The size of the specified object (memory pool, stack, message queue, +// etc.) is invalid. +// +#define STATUS_SIZE_ERROR 0x5 + +// +//STATUS_GROUP_ERROR +// An invalid group pointer was provided. The pointer is NULL or points +// to an already created group. +// +#define STATUS_GROUP_ERROR 0x6 + +// +//STATUS_NO_EVENTS +// The requested event could not be found. +// +#define STATUS_NO_EVENTS 0x7 + +// +//STATUS_OPTION_ERROR +// Invalid event flag set option (AND, OR). +// +#define STATUS_OPTION_ERROR 0x8 + +// +//STATUS_QUEUE_ERROR +// An invalid queue pointer passed or the queue is already created. +// +#define STATUS_QUEUE_ERROR 0x9 + +// +//STATUS_QUEUE_EMPTY +// The requested queue is empty. +// +#define STATUS_QUEUE_EMPTY 0xA + +// +//STATUS_QUEUE_FULL +// The requested queue is full. +// +#define STATUS_QUEUE_FULL 0xB + +// +//STATUS_SEMAPHORE_ERROR +// An invalid semaphore pointer provided or the semaphore is already created. +// +#define STATUS_SEMAPHORE_ERROR 0xC + +// +//STATUS_NO_INSTANCE +// The requested instance was not found (semaphore count is 0x0). +// +#define STATUS_NO_INSTANCE 0xD + +// +//STATUS_THREAD_ERROR +// An invalid thread control pointer provided or the thread is already created. +// +#define STATUS_THREAD_ERROR 0xE + +// +//STATUS_PRIORITY_ERROR +// An invalid thread priority level has been given. +// +#define STATUS_PRIORITY_ERROR 0xF + +// +//STATUS_START_ERROR +// An invalid auto-start selection was given during thread creation. +// NOTE: This value is the same a as STATUS_NO_MEMORY. +// +#define STATUS_START_ERROR 0x10 + +// +//STATUS_DELETE_ERROR +// The requested object can not be deleted. This can occur if an attempt is +// made to delete a thread that is not in a terminated or completed state. +// +#define STATUS_DELETE_ERROR 0x11 + +// +//STATUS_RESUME_ERROR +// The thread can not be resumed (e.g. the specified thread is not in a +// suspended state or was suspended by a driver other than the RTOS protocol). +// +#define STATUS_RESUME_ERROR 0x12 + +// +//STATUS_CALLER_ERROR +// Invalid caller of this service. +// +#define STATUS_CALLER_ERROR 0x13 + +// +//STATUS_SUSPEND_ERROR +// The thead can not be suspended (e.g. the specified thread is in a +// terminated or completed state). +// +#define STATUS_SUSPEND_ERROR 0x14 + +// +//STATUS_TIMER_ERROR +// An invalid timer object pointer was given. +// +#define STATUS_TIMER_ERROR 0x15 + +// +//STATUS_TICK_ERROR +// An invalid value (0x0) supplied for the initial tick count. +// +#define STATUS_TICK_ERROR 0x16 + +// +//STATUS_ACTIVATE_ERROR +// The object is already active. +// +#define STATUS_ACTIVATE_ERROR 0x17 + +// +//STATUS_THRESH_ERROR +// An invalid preemption threashold was specified. +// +#define STATUS_THRESH_ERROR 0x18 + +// +//STATUS_SUSPEND_LIFTED +// An attempt to resume a thread marked for delayed suspension has +// occurred. +// +#define STATUS_SUSPEND_LIFTED 0x19 + +// +//STATUS_WAIT_ABORTED +// The wait condition on which the thread is waiting has been aborted. +// +#define STATUS_WAIT_ABORTED 0x1A + +// +//STATUS_WAIT_ABORT_ERROR +// An attempt to abort a waiting thread was attempted on a thread that is +// not in a waiting condition (terminated, ready, completed, etc.). +// +#define STATUS_WAIT_ABORT_ERROR 0x1B + +// +//STATUS_MUTEX_ERROR +// An invalid mutex pointer was provided. +// +#define STATUS_MUTEX_ERROR 0x1C + +// +//STATUS_NOT_AVAILABLE +// An attempt to remove a mutex on which a thread is suspended has been +// attempted. +// +#define STATUS_NOT_AVAILABLE 0x1D + +// +//STATUS_NOT_OWNED +// An attempt to access a mutex not owned by the caller was made. +// +#define STATUS_NOT_OWNED 0x1E + +// +//STATUS_INHERIT_ERROR +// An invalid inherit option was given when trying to create a mutex. +// +#define STATUS_INHERIT_ERROR 0x1F + +// +//STATUS_TIMER_RUNNING +// An attempt to set an alarm was made while alarm is already enabled. +// +#define STATUS_TIMER_RUNNING 0x20 + +// +//STATUS_INVALID_FUNCTION +// The requested function was not found. +// +#define STATUS_INVALID_FUNCTION 0x80 + +// +//STATUS_NOT_FOUND +// The requested item could not be found. +// +#define STATUS_NOT_FOUND 0x81 + +// +//STATUS_ACCESS_DENIED +// Access to the requested object could not be granted. +// +#define STATUS_ACCESS_DENIED 0x82 + +// +//STATUS_INVALID_HANDLE +// The provided handle does not exist. +// +#define STATUS_INVALID_HANDLE 0x83 + +// +//STATUS_INVALID_ACCESS +// An attempt was made to access an inaccessible or unavailable object. +// +#define STATUS_INVALID_ACCESS 0x84 + +// +//STATUS_INVALID_PARAMS +// One or more parameters are invalid. +// +#define STATUS_INVALID_PARAMS 0x85 + +// +//STATUS_INVALID_PARAMS +// Request could not be processed because a Power Management event is already +// in progress. +// +#define STATUS_PM_EVENT_IN_PROGRESS 0x86 + +// +//STATUS_WRITE_PROTECTED +// The media is write protected. When writing to flash, this means +// the flash block is write protected. +// +#define STATUS_WRITE_PROTECTED 0x87 + +// +//STATUS_NOT_READY +// The h/w device is not ready. +// +#define STATUS_NOT_READY 0x88 + +// +//STATUS_NOT_SUPPORTED +// The function, message or request is not recognized or supported. +// +#define STATUS_NOT_SUPPORTED 0x89 + +// +//STATUS_NETWORK_BUSY +// The network device is busy. +// +#define STATUS_NETWORK_BUSY 0x8A + +// +//STATUS_DEVICE_ERROR +// The h/w device reported an error while attempting the operation. +// +#define STATUS_DEVICE_ERROR 0x8B + +// +//STATUS_INVALID_ADDRESS +// The address provided in invalid. +// +#define STATUS_INVALID_ADDRESS 0x8C + +// +//STATUS_INVALID_COMMAND +// The requested command is unrecognized or invalid. +// +#define STATUS_INVALID_COMMAND 0x8D + +// +//STATUS_STACK_OVERFLOW +// The request caused a stack overflow. +// +#define STATUS_STACK_OVER_FLOW 0x8E + +// +//STATUS_BUFFER_TOO_SMALL +// The provided buffer is too small to hold the requested data. +// +#define STATUS_BUFFER_TOO_SMALL 0x8F + +// +//STATUS_LOAD_ERROR +// The image failed to load. +// +#define STATUS_LOAD_ERROR 0x90 + +// +//STATUS_INVALID_BUFFER +// The buffer was not the proper size for the request. +// +#define STATUS_INVALID_BUFFER 0x91 + +// +//STATUS_NO_RESPONSE +// No response was received from the requested target. +// +#define STATUS_NO_RESPONSE 0x92 + +// +//STATUS_TIMED_OUT +// The device or object timed out and was unable to complete the request. +// +#define STATUS_TIMED_OUT 0x93 + +// +//STATUS_NOT_STARTED +// The requested operation could not be started. For protocols, this +// error indicates the protocol has not been started. +// +#define STATUS_NOT_STARTED 0x94 + +// +//STATUS_ALREADY_STARTED +// The requested operation has already been started. +// - For protocols, this error +// indicates the protocol has already been started. +// - For Policy Manager this error means +// that the MKHI group ID is already registered. +// For FW update, we only allow one process to do the update at a time, this means error +// case where FW update is already in progress, the current process will have to try later. +// +#define STATUS_ALREADY_STARTED 0x95 + +// +//STATUS_PROTOCOL_ERROR +// The protocol in use has generated an error. For network traffic this error +// means the networking protocol returned and error. When returned from a +// protocol this means the protocol itself generated an error. +// +#define STATUS_PROTOCOL_ERROR 0x96 + +// +//STATUS_INCOMPATIBLE_VERSION +// The version of the object is incompatible with the request. For protocols, +// this indicates that the protocol version number is not supported. +// +#define STATUS_INCOMPATIBLE_VERSION 0x97 + +// +//STATUS_SECURITY_VIOLATION +// A security violation has occurred. +// +#define STATUS_SECURITY_VIOLATION 0x98 + +// +//STATUS_AUTHENTICATION_FAIL +// The authentication of an object has failed. +// +#define STATUS_AUTHENTICATION_FAIL 0x99 + +// +//STATUS_INVALID_MEM_TYPE +// The target memory is invalid for the requested operation (e.g. DMA to +// ROM or cypto DMA from system memory). +// +#define STATUS_INVALID_MEM_TYPE 0x9A + +// +//STATUS_MODE_NOT_SUPPORTED +// The type of blocking mode is not supported. Refer to the documentation on +// the specific interface. +// +#define STATUS_MODE_NOT_SUPPORTED 0x9B + +// +//STATUS_RESOURCE_BUSY +// The requested resource is busy or can not be acquired. +// +#define STATUS_RESOURCE_BUSY 0x9C + +// +//STATUS_OUT_OF_RESOURCES +// Insufficient resources to perform the request. Used by components operating +// in non-blocking mode. A caller will be returned this error when a component +// does not have enough resources like command buffers, PRDs etc... to entertain +// a new request. +// +#define STATUS_OUT_OF_RESOURCES 0x9D + +// +//STATUS_FAILURE +// A unknown error encountered while performing a requested transaction. +// +#define STATUS_FAILURE 0x9E + +// +//STATUS_QUEUED +// A requested has been successfully placed in a command queue. This status +// is returned by non-blocking components after successfully queuing a request +// in their command queue. +// +#define STATUS_QUEUED 0x9F + +// +//STATUS_WEAR_OUT_VIOLATION +// The partition manager returns this error code when it can not perform a +// requested erase operation due to flash wear out constraints. +#define STATUS_WEAR_OUT_VIOLATION 0xA0 + +// +//STATUS_GENERAL_ERROR +// This is a general error code used for errors that do not require a specific +// code. +#define STATUS_GENERAL_ERROR 0xA1 + +// +//STATUS_SMB_EMPTY +// The smbus slave circular buffer does not contain any smbus transactions data. +#define STATUS_SMB_EMPTY 0xA2 + +// +//STATUS_SMB_NO_MORE_ENTRIES +// The smbus slave has reached its maximal number of registered transactions. +// New transactions can not be added until the removal of one of the current +// registered ones. +#define STATUS_SMB_NO_MORE_ENTRIES 0xA3 + +// +//STATUS_BUS_ERROR +// Generic error code for bus errors. Common cause could be losing arbitration +// on a multi-mastered bus. +#define STATUS_BUS_ERROR 0xA4 + +// +//STATUS_IMAGE_INVALID +// The FW Update image content is invalid. +#define STATUS_IMAGE_INVALID 0xA5 + +// +//STATUS_UPDATE_AUTH_FAILED +// The FW Update image authentication failed. +#define STATUS_UPDATE_AUTH_FAILED 0xA6 + +// +//STATUS_UPDATE_ALLOWED +// Used in the policy manager to indicate whether a policy can be updated at +// the time of this request. +#define STATUS_UPDATE_ALLOWED 0xA7 + +// +//STATUS_UPDATE_NOT_ALLOWED +// Used in the policy manager to indicate that a policy cannot be updated at +// the time of this request. +#define STATUS_UPDATE_NOT_ALLOWED 0xA8 + +// +//STATUS_LOCKED +// Indicates policy element has been already locked and cannot be updated. +#define STATUS_LOCKED 0xA9 + +// +//STATUS_NOT_INITIALIZED +// Indicates that SDM core is not initialized +#define STATUS_NOT_INITIALIZED 0xAA //REQUIRES COORDINATION!!! + +// +//STATUS_END_OF_FILE +// Indicates that EOF is reached while accessing a file +#define STATUS_END_OF_FILE 0xAB //REQUIRES COORDINATION!!! + +// +//STATUS_NO_STORAGE_AVAILABLE +// Indicates policy element could not be stored in the NVAR. +#define STATUS_NO_STORAGE_AVAILABLE 0xB0 + +// +//STATUS_LOCKING_NOT_ALLOWED +// Indicates policy element cannot be locked. +#define STATUS_LOCKING_NOT_ALLOWED 0xB1 + +// +//STATUS_UNKNOWN_LAN_FUSE_CAPS +// Indicates a unknown capability of the LAN device is being set. +#define STATUS_UNKNOWN_LAN_FUSE_CAPS 0xB2 + +// +//STATUS_INVALID_FEATURE_ID +// Indicates an invalid feature ID. +#define STATUS_INVALID_FEATURE_ID 0xB3 + +// +//STATUS_PET_TRANSMIT_DISABLED +// The transmission of pet packets is disabled. +#define STATUS_PET_TRANSMIT_DISABLED 0xB4 + +// STATUS_MAX_KERB_DOMAIN_REACHED +// indicates that in the kerberos ACL there are users from MAX DOMAINS (4). +#define STATUS_MAX_KERB_DOMAIN_REACHED 0xB5 + +// STATUS_UPDATE_MISMATCH_HW_SKU +// Indicates that there is a mismatch between the current HW SKU and the +// one in the new image. +#define STATUS_UPDATE_MISMATCH_HW_SKU 0xB6 + +// STATUS_UPDATE_MISMATCH_FW_SKU +// Indicates that there is a mismatch between the current FW SKU and the +// one in the new image. +#define STATUS_UPDATE_MISMATCH_FW_SKU 0xB7 + +// STATUS_UPDATE_MISMATCH_VERSION +// Indicates that there is a mismatch between the current FW version and the +// one in the new image. +#define STATUS_UPDATE_MISMATCH_VERSION 0xB8 + +// STATUS_EVENT_DISABLED_CONFIG +// This wake event is configured to be disabled (via MEBx setup or remote +// configuration). +#define STATUS_EVENT_DISABLED_CONFIG 0xB9 + +// STATUS_NOT_REGISTERED +// Caller is trying to use an interface that requires registration, but the +// registration process has not been completed. +#define STATUS_NOT_REGISTERED 0xBA + + +// STATUS_INVALID_EVENT +// Caller is trying to use a wake event code which is invalid +#define STATUS_INVALID_EVENT 0xBB + +// STATUS_INVALID_EVENT +// Caller is trying to use an event context which is invalid +#define STATUS_BAD_CONTEXT 0xBC + + +// +//STATUS_NET_RESTART_NEEDED +// The network stack need restart to continue working. +#define STATUS_NET_RESTART_NEEDED 0xBD + +// +//STATUS_OUT_OF_MEMORY +// This error can be returned for the following reasons: +// 1.Attempt to allocate memory and no memory is available +// 2.Attempt to free a memory block on which a thread is suspended +// NOTE: This value is the same a as STATUS_START_ERROR. +// +#define STATUS_OUT_OF_MEMORY 0xBE + + +// +//STATUS_COUNTER_ROLLOVER +// This error can be returned by MC_PROTOCOL IncrementCounter() +// if given monotonic counter reaches maximum value. +// Along with error, counter will be initialized with value "1" +// +// The value will also be returned by TIME_PROTOCOL GetPRTC() +// if the PRTC rolls over +#define STATUS_COUNTER_ROLLOVER 0xBF + + +// +// BLOB SERVICE SPECIFIC FAILURES +// +// STATUS_BLOB_INTEGRITY_FAILED +// STATUS_BLOB_CONFIDENTIALITY_FAILED +// STATUS_BLOB_AR_FAILED +#define STATUS_BLOB_INTEGRITY_FAILED 0xC0 +#define STATUS_BLOB_CONFIDENTIALITY_FAILED 0xC1 +#define STATUS_BLOB_AR_FAILED 0xC2 + + + +//STATUS_PROCESSING +// Caller is asking for process result that is not already finished +#define STATUS_PROCESSING 0xC3 + +//STATUS_REGISTERED +// Caller registered for something that itself or others already did +#define STATUS_REGISTERED 0xC4 +// +//STATUS_EAC_NOT_PERMITTED +// This error can be returned for the following reasons: +// 1.Attempt to enable EAC when sign certificate is not set + +// +#define STATUS_EAC_NOT_PERMITTED 0xC5 + +// +//STATUS_EAC_NO_ASSOCIATION +// This error can be returned for the following reasons: +// 1.Attempt to receive a posture or posture hash sign certificate is not set + +// +#define STATUS_EAC_NO_ASSOCIATION 0xC6 + +// +//STATUS_AUDIT_FAIL +// This error can be returned when these conditions are met: +// 1. The action should be logged to the Audit Log +// 2. The event was defined as critical +// 3. The Audit Log is enabled +// 4. Either: +// a. The Audit Log is currently Locked +// b. The storage for the Audit Log is full + +// +#define STATUS_AUDIT_FAIL 0xC7 + +#define STATUS_DUPLICATED 0xC8 + +// +//STATUS_IPP_INTERNAL_ERROR +// This error can bb returned in case of internal IPP function failed. +#define STATUS_IPP_INTERNAL_ERROR 0xC9 + +// +//STATUS_IPP_CORRUPTED_KEY +// This error can be returned when trying to load or validate corrupted RSA key +// using the IPP stack. +// Can be returned RsaEncryptDecrypt and RsaValidateKey functions. +#define STATUS_IPP_CORRUPTED_KEY 0xCA + +// +//STATUS_IPP_DATA_NOT_ALIGNED +// This error can be returned when trying to load, create or validate RSA key using the +// IPP stack, and the data is not aligned. +// Can be returned RsaGenerateKey, RsaEncryptDecrypt and RsaValidateKey functions. +#define STATUS_IPP_DATA_NOT_ALIGNED 0xCB + +// +//STATUS_IPP_OPERATION_ABORTED +// This error will be returned if the IPP aborted key generation before completion. +#define STATUS_IPP_OPERATION_ABORTED 0xCC + +// +//STATUS_IPP_CACHE_CONVERTION_FAILED +// This error can be returned if the TRAMD-Cache conversion failed. +#define STATUS_IPP_CACHE_CONVERTION_FAILED 0xCD + +// +//STATUS_IPP_EXPONENT_CHANGED +// This error will be returned if the IPP decided to use differnt exponent (E) +// than the one the caller supplied. +#define STATUS_IPP_EXPONENT_CHANGED 0xCE + +// STATUS_PERMIT_EXPIRED +// iCLS Permit has expired +#define STATUS_PERMIT_EXPIRED 0xCF + +// STATUS_PERMIT_RESET_REQUIRED +// iCLS permit is invalid in some way (for example expired) +// and HW fuses are overided by permit still +#define STATUS_PERMIT_RESET_REQUIRED 0xD0 + +// STATUS_CLOSED_BY_HOST +// HECI will return this in the event that AddBuffer call is failing because +// the connection is in a close pending status. +// This will indicate that freeing the SendBufferQ and BufferQ is not permitted at +// this time and the client should wait for a HIE_CLOSED message to cleanup HECI_CONNECTION. +#define STATUS_CLOSED_BY_HOST 0xD1 + + +// STATUS_DISABLED_BY_POLICY +// This error will be returned if the call is blocked by previous defined policy +#define STATUS_DISABLED_BY_POLICY 0xD2 + +//STATUS_INVALID_COMP_HANDLE +// The provided component handle does not exist. +// +#define STATUS_INVALID_COMP_HANDLE 0xD3 + +// +//Status Codes used by state manager to indicate ME Database status +//and general Client/Daemon registration problems in state manager +//that prohibit the Daemon from returning more exact status. +// + +// +//STATUS_ALREADY_REGISTERED +// This error is used to indicate if a Daemon is already +// registered with state manager. +#define STATUS_ALREADY_REGISTERED 0xD4 + +// +//STATUS_DATABASE_IN_USE +// This error is used to indicate if a ME Database is currently in +// use when a delete is called on it. +#define STATUS_DATABASE_IN_USE 0xD5 + +// +//STATUS_ENTRY_IN_USE +// This error is used to indicate if an entry in a ME Database is +// currently in use when a release is called on it. +#define STATUS_ENTRY_IN_USE 0xD6 + +// +//STATUS_UNABLE_TO_REGISTER +// This error is used to indicate that a Daemon cannot register +// with state manager. +#define STATUS_UNABLE_TO_REGISTER 0xD7 + +// +// STATUS_TLB_ENTRY_NOT_FOUND +// This error indicates that a free TLB entry or the specified TLB entry +// could not be found. +// +#define STATUS_TLB_ENTRY_NOT_FOUND 0xD8 + +// +//STATUS_UNABLE_TO_UNREGISTER +// This error code is used to indicate that a Daemon cannot +// unregister with the state manager. +#define STATUS_UNABLE_TO_UNREGISTER 0xD9 + +// +//STATUS_TIMER_VALUE_NOT_SET +// Error used by PRTC to indicate the alarm value +// has not been set prior to enabling the alarm. +#define STATUS_TIMER_VALUE_NOT_SET 0xDA + +// +//STATUS_ICV_CHECK_ERROR +// HW reported an ICV check failure +#define STATUS_ICV_CHECK_ERROR 0xDB + +// STATUS_SUCCESS_WITH_ERRORS +// This error will be returned if the opration completed but had some errors (e,eg Transfer AHCI for DT) +// It is shared between Danbury components +#define STATUS_SUCCESS_WITH_ERRORS 0xDC + +// STATUS_SUCCESS_HOST_RESET_REQUIRED +// This status will be returned by FwUpdateMgr after successfully updating FW +// if Danbury is enabled +#define STATUS_SUCCESS_HOST_RESET_REQUIRED 0xDD + +// STATUS_FIPS_FAILURE +// This status will be returned by when FIPS self-tests fail +#define STATUS_FIPS_FAILURE 0xDE + +//STATUS_PRIVILEGE_CHECK +// Privileged component access +#define STATUS_PRIVILEGE_CHECK 0xDF + +// STATUS_INCOMPLETE +// This error indicates that the operation is incomplete +#define STATUS_INCOMPLETE 0xE0 + +// STATUS_RETRY +// This error indicates that the operation is being retried or needs to be retried +#define STATUS_RETRY 0xE1 + +#define STATUS_NOT_RUN 0xE2 + +#define STATUS_NOT_IMPLEMENTED 0xE3 + + +#define STATUS_INVALID_INDEX 0xE4 +#define STATUS_SLOT_IN_USE 0xE5 +#define STATUS_SLOT_EMPTY 0xE6 + +// STATUS_OVERRIDDEN +// This error indicates that the operation can't be performed because +// it was overridden by some other logic/request +#define STATUS_OVERRIDDEN 0xE7 + +//STATUS_PERMIT_IS_DEACTIVE +// iCLS Permit has been deactivated +#define STATUS_PERMIT_IS_DEACTIVE 0xF0 + +//Return this if it is a Patsburg chipset +#define STATUS_UNKNOWN_CPUID 0xF1 + +#define STATUS_CRC_ERROR 0xF2 + +#if 1 +//STATUS for task isolation +#define STATUS_HECI_CONNECTION_ACCEPT 0xF3 +#define STATUS_HECI_CONNECTION_REJECT 0xF4 +#define STATUS_RETURN_NOT_AVAILABLE 0xF5 +#endif +//STATUS for PG +#define STATUS_PG_ENTRY_IN_PROGRESS 0xF6 + +// Intel Secret Key Unavailable +// RCR CCG0100111613 +#define STATUS_BLOB_UNAVAILABLE 0xF6 + +#define STATUS_FPF_READ_MISMATCH 0xF7 +#define STATUS_FPF_ARRAY_FULL 0xF8 +#define STATUS_FPF_WRITE_FAILED 0xF9 +#define STATUS_FPF_FILE_INVALID 0xFA +#define STATUS_FPF_FILE_FULL 0xFB +#define STATUS_FPF_FILE_LOCKED 0xFC +#define STATUS_FPF_NOT_AVAILABLE 0xFD +#define STATUS_FPF_BUSY 0xFE // FPF write currently in progress +#define STATUS_FPF_FATAL_ERROR 0xFF // Fatal error, fuses are no longer valid (bad PCH) +#define STATUS_FPF_FILE_EMPTY 0x100 // File has not been written to +#define STATUS_FPF_ALREADY_COMMITTED 0x101 +#define STATUS_FPF_COMMIT_FAILED_EOM_NOT_SET 0x102 +#define STATUS_FPF_INVALID_SB_VALUES 0x103 +#define STATUS_FPF_NOT_COMMITTED 0x104 +#define STATUS_FPF_NVAR_MISMATCH 0x105 +#define STATUS_FPF_FILE_UNLOCKED 0x106 +#define STATUS_FPF_COMMIT_NOT_ALLOWED 0x107 +#define STATUS_FPF_CANARY_FAILURE 0x108 +#define STATUS_FPF_SENSE_FAILED 0x109 +#if 1 +// STATUS for FWU kernel between 0x200 to 0x2FF +#define FW_UPDATE_STATUS UINT32 + +#define NO_UPDATE 0 +#define STATUS_UPDATE_SUCCESS 0x0 // Zero for sucess anything else is consider failures +#define STATUS_UPDATE_IMAGE_INVALID 0x201 +#define STATUS_UPDATE_INTEGRITY_FAILURE 0x202 +#define STATUS_UPDATE_SKU_MISMATCH 0x203 +#define STATUS_UPDATE_FW_VERSION_MISMATCH 0x204 +#define STATUS_UPDATE_GENERAL_FAILURE 0x205 +#define STATUS_UPDATE_OUT_OF_RESOURCES 0x206 +#define STATUS_UPDATE_AUDIT_POLICY_FAILURE 0x207 +#define STATUS_UPDATE_ERROR_CREATING_FT 0x208 +#define STATUS_UPDATE_SAL_NOTIFICATION_ERROR 0x209 +#define STATUS_UPDATE_IMG_LOADING 0x20A +#define STATUS_UPDATE_IMG_AUTHENTICATING 0x20B +#define STATUS_UPDATE_IMG_PROCESSING 0x20C +#define STATUS_UPDATE_CREATING_FT 0x20D +#define STATUS_UPDATE_UPDATING_CODE 0x20E +#define STATUS_UPDATE_UPDATING_NFT 0x20F +#define STATUS_UPDATE_FLASH_CODE_PARTITION_INVALID 0x210 +#define STATUS_UPDATE_FLASH_NFT_PARTITION_INVALID 0x211 +#define STATUS_UPDATE_ILLEGAL_IMAGE_LENGTH 0x212 +#define STATUS_UPDATE_NOT_READY 0x213 + +#define STATUS_UPDATE_HOST_RESET_REQUIRED 0x214 +#define STATUS_INVALID_GLUT 0x215 +#define STATUS_INVALID_OEM_ID 0x216 + +// New for CPT add below here +#define STATUS_UPDATE_IMAGE_BLACKLISTED 0x217 +#define STATUS_UPDATE_IMAGE_VERSION_HISTORY_CHECK_FAILURE 0x218 +#define STATUS_UPDATE_DOWNGRADE_VETOED 0x219 +#define STATUS_UPDATE_WRITE_FILE_FAILURE 0x22A +#define STATUS_UPDATE_READ_FILE_FAILURE 0x22B +#define STATUS_UPDATE_DELETE_FILE_FAILURE 0x22C +#define STATUS_UPDATE_PARTITION_LAYOUT_NOT_COMPATIBLE 0x22D // FW Update is not possible due to partition move +#define STATUS_DOWNGRADE_NOT_ALLOWED_DATA_MISMATCHED 0x22E +#define STATUS_UPDATE_FW_UPDATE_IS_DISABLED 0x22F +#define STATUS_UPDATE_PASSWORD_NOT_MATCHED 0x230 +#define STATUS_UPDATE_PASSWORD_EXCEED_MAXIMUM_RETRY 0x231 +#define STATUS_UPDATE_INRECOVERY_MODE_RESTRICT_UPDATE_TO_ATTEMPTED_VERSION 0x232 // They have to update with the same image that they started with. + + +// New for Partial FW update +#define STATUS_UPDATE_UPV_VERSION_MISMATCHED 0x233 // UPV version mismatched update is not allow +#define STATUS_UPDATE_INSTID_IS_NOT_EXPECTED_ID 0x234 // Reject update, instance ID sent is not one of expected ID +#define STATUS_UPDATE_INFO_NOT_AVAILABLE 0x235 // While in the middle of update IPU attrib info will bot be available +#define STATUS_UPDATE_REJ_IPU_FULL_UPDATE_NEEDED 0x236 // Can't do IPU update while we are in Full recovery mode. +#define STATUS_UPDATE_IPU_NAMEID_NOT_FOUND 0x237 // IPU name not found when compare with UPV extension + +#define STATUS_UPDATE_RESTORE_POINT_INVALID 0x238 +#define STATUS_UPDATE_RESTORE_POINT_VALID_BUT_NOT_LATEST 0x239 +#define STATUS_UPDATE_RESTORE_POINT_OPERATION_NOT_ALLOWED 0x23A +#define STATUS_DOWNGRADE_NOT_ALLOWED_SVN_RESTRICTION 0x23B +#define STATUS_DOWNGRADE_NOT_ALLOWED_VCN_RESTRICTION 0x23C +#define STATUS_INVALID_SVN 0x23D +#define STATUS_UPDATE_OUT_OF_SVN_RESOURCES 0x23E +#define STATUS_UPDATE_REJECT_RESTORE_POINT_REQUEST_FLASH_IN_RECOVERY 0x23F +#define STATUS_UPDATE_REJECTED_BY_UPDATE_POLICY 0x240 +#define STATUS_UPDATE_REJECTED_INCOMPATIBLE_TOOL_USAGE 0x241 +#define STATUS_UPDATE_REJECTED_CROSSPOINT_UPDATE_NOT_ALLOWED 0x242 +#define STATUS_UPDATE_REJECTED_CROSSHOTFIX_UPDATE_NOT_ALLOWED 0x243 +#define STATUS_UPDATE_REJECTED_CURRENT_FW_NOT_ELIGIBLE_FOR_UPDATE 0x244 +#define STATUS_UPDATE_REJECTED_WRONG_UPDATE_OPERATION 0x245 +#define STATUS_UPDATE_REJECTED_WRONG_UPDATE_IMAGE_FOUND 0x246 +#define STATUS_UPDATE_REJECTED_IFR_UPDATE_NOT_ALLOWED 0x247 +#define STATUS_UPDATE_FAILURE_OCCURRED_DURING_ROLLBACK 0x248 + +//......................................................................... +//......................................................................... // Reserve for FWU usage +#define STATUS_UPDATE_LAST_STATUS_CODE 0x2FF + +// Hotham-specific error codes +#define STATUS_HTM_HOST_NOT_RDY 0x300 +#define STATUS_HTM_INTERNAL_ERROR 0x301 +#define STATUS_HTM_REQ_IN_PROGRESS 0x302 +#define STATUS_HTM_RESP_IN_PROGRESS 0x303 +#define STATUS_HTM_INVALID_FRAGMENT 0x304 +#define STATUS_HTM_RESP_NONE_ACTIVE 0x305 +#define STATUS_HTM_NOT_CONNECTED 0x306 +//... +//... Reserved for future use +#define STATUS_HTM_LAST_STATUS_CODE 0x31F + + + + +// means internal FW operation errors +//#define STATUS_UPDATE_UNKNOWN = 0xFFFFFFFF + + +#endif + + +#endif // _ME_STATUS_H_ diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.c b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.c new file mode 100644 index 0000000..d5caea8 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.c @@ -0,0 +1,701 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2015, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** +#include <Token.h> +#include <AmiDxeLib.h> +#include <Protocol\Heci\Heci.h> +#include <Protocol\PchPlatformPolicy\PchPlatformPolicy.h> +#include <Protocol\PchReset\PchReset.h> +#include <Protocol\MeBiosPayloadData\MeBiosPayloadData.h> +#include <Protocol\Decompress.h> +#include <Protocol\GuidedSectionExtraction.h> +#include <Protocol\ConsoleControl.h> +#include <Protocol\AMIPostMgr.h> + +#ifdef _HECI_PROTOCOL_H +//Broadwell RC +#include <Library\MeDxeLib.h> +#include <Library\MeChipsetLib.h> +#else +//Haswell RC +#undef EFI_PROTOCOL_DEFINITION +#define EFI_STRINGIZE(a) #a +#define EFI_PROTOCOL_DEFINITION(a) EFI_STRINGIZE (Protocol/a/a.h) +#include "HeciMsgLib.h" +#include "MeChipsetLib.h" +#endif + +#include <Guid\FirmwareFileSystem2.h> + + +#include "IntelLib\FWUpdateLib.h" +#include "IntelLib\me_status.h" +#include "MeFwUpdLclProtocol.h" +#include "EdkIICommon.h" + +_UUID mOemId = {0x00000000, 0x0000, 0x0000, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + +// Last Reset Types +#define NORESET 0 +#define HOSTRESET 1 +#define MERESET 2 +#define GLOBALRESET 3 + +// Get Interface +#define FW_UPDATE_DISABLED 0 +#define FW_UPDATE_ENABLED 1 +#define FW_UPDATE_PASSWORD_PROTECTED 2 + +#ifdef _HECI_PROTOCOL_H +//Broadwell RC +typedef struct _PCH_PLATFORM_POLICY PRIVATE_PCH_PLATFORM_POLICY_PROTOCOL; +#else +//Haswell RC +typedef struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL PRIVATE_PCH_PLATFORM_POLICY_PROTOCOL; +#define HECI_PROTOCOL EFI_HECI_PROTOCOL +#define MBP_DATA_PROTOCOL DXE_MBP_DATA_PROTOCOL +#define PCH_PLATFORM_POLICY_PROTOCOL_GUID DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID +#endif + +#ifndef MAX_ADDRESS +#define MAX_ADDRESS 0xFFFFFFFF +#endif +#define ME_UPD_LCL_SIGNATURE SIGNATURE_32 ('_', 'M', 'U', 'L') + +EFI_GUID mAmiGlobalVariableGuid = AMI_GLOBAL_VARIABLE_GUID; + +EFI_GUID mEfiHeciProtocolGuid = HECI_PROTOCOL_GUID; +EFI_GUID mMeFwUpdLclProtocolGuid = ME_FW_UPD_LOCAL_PROTOCOL_GUID; +EFI_GUID mPchPlatformPolicyProtocolGuid = PCH_PLATFORM_POLICY_PROTOCOL_GUID; +EFI_GUID mPchResetProtocolGuid = PCH_RESET_PROTOCOL_GUID; +EFI_GUID mMeBiosPayloadDataProtocolGuid = ME_BIOS_PAYLOAD_DATA_PROTOCOL_GUID; +EFI_GUID mConOutStartedProtocolGuid = CONSOLE_OUT_DEVICES_STARTED_PROTOCOL_GUID; + +EFI_GUID mMeRegionFfsGuid = \ +{0xDE90FFA8, 0xB985, 0x4575, 0xAB, 0x8D, 0xAD, 0xE5, 0x2C, 0x36, 0x2C, 0xA3}; + +ME_FW_UPDATE_LOCAL_PROTOCOL *mMeFwUpdateLclProtocol = NULL; +PRIVATE_PCH_PLATFORM_POLICY_PROTOCOL *mPchPlatformPolicy = NULL; + +EFI_BOOT_SERVICES *BS = NULL; +EFI_RESET_SYSTEM mSavedResetSystem = NULL; + +ME_FW_UPD_VERSION mMeFwImgVersion[] = ME_FW_IMAGE_VERSION; + +void _fltused() +{ +} + +VOID * +SetMem ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINT8 Value +) +{ + MemSet( Buffer, Length, Value); + return Buffer; +} + +INTN +EFIAPI +CompareMem ( + IN VOID *DestinationBuffer, + IN VOID *SourceBuffer, + IN UINTN Length + ) +{ + return MemCmp( DestinationBuffer, SourceBuffer, Length ); +} + +VOID* AllocatePool( + IN UINTN AllocationSize) +{ + VOID *p; + EFI_STATUS Status; + + Status = BS->AllocatePool(EfiBootServicesData, AllocationSize, &p); + return (EFI_ERROR(Status)) ? NULL : p; +} + +VOID FreePool( + IN VOID *Buffer) +{ + BS->FreePool(Buffer); +} + +VOID * +EFIAPI +CopyMem ( + OUT VOID *Destination, + IN VOID *Source, + IN UINTN Length + ) +{ + MemCpy( Destination, Source, Length); + return Destination; +} + +VOID * +EFIAPI +ZeroMem ( + OUT VOID *Buffer, + IN UINTN Length + ) +{ + ASSERT (!(Buffer == NULL && Length > 0)); + ASSERT (Length <= (MAX_ADDRESS - (UINTN)Buffer + 1)); + return SetMem (Buffer, Length, 0); +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MeUpdPlatformUnlock +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MeUpdPlatformUnlock ( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This, + IN UINT32 UnlockType +) +{ + if( mPchPlatformPolicy != NULL ) +#ifdef _HECI_PROTOCOL_H + //Broadwell RC + mPchPlatformPolicy->LockDownConfig.BiosLock = 0; +#else + //Haswell RC + mPchPlatformPolicy->LockDownConfig->BiosLock = 0; +#endif + + // Patch disabling IDE_R if ME is Disabled for system assert if DEBUG_MODE is ON. + // The IDE-R device will be disabled if ME is in Normal state (HeciInit.c), + // Here ME is in ME_MODE_SECOVER, the IDE-R is active and could cause assert error + // in IdeBus.Start proceduce. + MeDeviceControl( IDER, Disabled ); + + return EFI_SUCCESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MeUpdPlatformReset +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MeUpdPlatformReset ( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This, + IN EFI_RESET_TYPE ResetType +) +{ + EFI_STATUS Status; + PCH_RESET_PROTOCOL *PchReset; + // Reset system to re-start ME FW.. + Status = pBS->LocateProtocol( + &mPchResetProtocolGuid, + NULL, + (VOID**)&PchReset); + if( !EFI_ERROR(Status) ) + PchReset->Reset(PchReset, EfiResetCold); + + return EFI_SUCCESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MeCheckFwState +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MeCheckFwState( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This, + IN ME_FW_STATE MeFwState +) +{ + EFI_STATUS Status; + UINT32 MeMode; + HECI_PROTOCOL *Heci = NULL; + + Status = pBS->LocateProtocol( + &mEfiHeciProtocolGuid, NULL, (VOID**)&Heci); + if (EFI_ERROR(Status)) return EFI_UNSUPPORTED; + Status = Heci->GetMeMode (&MeMode); + if (EFI_ERROR(Status)) return EFI_UNSUPPORTED; + if (((MeFwState == MeModeNormal) && (MeMode == ME_MODE_NORMAL)) || \ + ((MeFwState == MeModeDebug) && (MeMode == ME_MODE_DEBUG)) || \ + ((MeFwState == MeModeTempDisabled) && (MeMode == ME_MODE_TEMP_DISABLED)) || \ + ((MeFwState == MeModeSecOver) && (MeMode == ME_MODE_SECOVER)) || \ + ((MeFwState == MeModeFailed) && (MeMode == ME_MODE_FAILED))) return EFI_SUCCESS; + return EFI_UNSUPPORTED; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MeGetFwVersion +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MeGetFwVersion ( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This, + IN OUT ME_FW_UPD_VERSION *MeFwVersion +) +{ + EFI_STATUS Status; + MBP_DATA_PROTOCOL *MbpData; + + // Get ME Firmware Version from MBP, then save for future used. + Status = pBS->LocateProtocol ( \ + &mMeBiosPayloadDataProtocolGuid, NULL, (VOID **)&MbpData); + if (!EFI_ERROR (Status)) { + MemCpy(MeFwVersion, \ + &MbpData->MeBiosPayload.FwVersionName, sizeof(ME_FW_UPD_VERSION)); + } + return Status; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MeUpdHmrfpoEnable +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MeUpdHmrfpoEnable ( + ME_FW_UPDATE_LOCAL_PROTOCOL *This +) +{ + EFI_STATUS Status; + UINT8 HeciHmrfpoEnableResult; + HeciHmrfpoEnableResult = HMRFPO_ENABLE_UNKNOWN_FAILURE; + Status = HeciHmrfpoEnable (0, &HeciHmrfpoEnableResult); + if ((Status == EFI_SUCCESS) && (HeciHmrfpoEnableResult == HMRFPO_ENABLE_SUCCESS)) { + /// (A6) The BIOS sends the GLOBAL RESET MEI message + HeciSendCbmResetRequest (CBM_RR_REQ_ORIGIN_BIOS_POST, CBM_HRR_GLOBAL_RESET); + MeUpdPlatformReset(This, EfiResetCold); + //CpuDeadLoop(); + while(1); + } + return Status; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: DisplaySendStatus +// +// Description: +// +// Input: +// float BytesSent +// float BytestobeSent +// Output: +// None +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +void +DisplaySendStatus ( + float BytesSent, + float BytestobeSent + ) +{ +// float value = (BytesSent / BytestobeSent) * 100; +// UINT32 pValue = (UINT32)value; +// +// if (pValue != 100) +// { +// DEBUG ((D_ERROR, "Sending the update image to FW for verification: [ %d%% ]\r", pValue)); +// } +// else +// { +// DEBUG ((D_ERROR, "Sending the update image to FW for verification: [ COMPLETE ] \n")); +// } +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: FwUpdLclFunc +// +// Description: The main function to update ME firmware. +// It will call Intel's API to update ME firmware. +// +// Input: +// IN ME_FW_UPDATE_LOCAL_PROTOCOL *This +// IN UINT8 *FileBuffer +// IN UINTN FileLength +// Output: +// None +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +FwUpdLclFunc ( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This, + IN UINT8 *FileBuffer, + IN UINTN FileLength +) +{ + EFI_STATUS Status; + UINTN ImageLength = 0; + UINT8 *ImageBuffer = NULL; + UPDATE_FLAGS_LIB update_flags; + CHAR8 Password[9]; + UINT32 FWUpdateStatus; + UINT32 QueryStatus; + UINT32 UpdateStatus = 0; + UINT32 TotalStages = 0; + UINT32 PercentWritten = 0; + UINT32 LastStatus; + UINT32 LastResetType; + UINT16 Interfaces; + UINT8 Symbol; + UINT32 Index; + UINT32 CheckPolicyStatus = 0; + BOOLEAN AllowSV = FALSE; + UPDATE_TYPE UpdType; + VersionLib Ver; + VOID *DisplayHandle; + AMI_POST_MGR_KEY OutKey; + + BS = pBS; + + ImageBuffer = FileBuffer; + ImageLength = FileLength; + + ZeroMem( &update_flags, sizeof(UPDATE_FLAGS_LIB) ); + + Status = GetLastStatus( &LastStatus ); + if( EFI_ERROR(Status) ) + { + return Status; + } + + if( LastStatus == STATUS_UPDATE_HOST_RESET_REQUIRED ) + { + //DEBUG ((D_ERROR, "PLEASE REBOOT YOUR SYSTEM. ")); + //DEBUG ((D_ERROR, "Firmware update cannot be initiated without a reboot.\n")); + return EFI_SUCCESS; + } + + if( IsUpdateStatusPending(LastStatus) ) + { + //DEBUG ((D_ERROR, "Firmware Update operation not initiated ")); + //DEBUG ((D_ERROR, "because a firmware update is already in progress\n")); + return EFI_SUCCESS; + } + + Status = GetLastUpdateResetType( &LastResetType ); + if( EFI_ERROR(Status) ) return Status; + switch( LastResetType ) + { + case HOSTRESET: + case GLOBALRESET: + //DEBUG ((D_ERROR, "PLEASE REBOOT YOUR SYSTEM. ")); + //DEBUG ((D_ERROR, "Firmware update cannot be initiated without a reboot.\n")); + return EFI_SUCCESS; + break; + default: + break; + } + + Status = GetInterfaces( &Interfaces ); + if( EFI_ERROR(Status) ) return Status; + switch( Interfaces ) + { + case FW_UPDATE_DISABLED: + //DEBUG ((D_ERROR, "Local FWUpdate is Disabled\n")); + return EFI_SUCCESS; + case FW_UPDATE_PASSWORD_PROTECTED: + //DEBUG ((D_ERROR, "Local FWUpdate is Password Protected\n")); + break; + case FW_UPDATE_ENABLED: + break; + default: + break; + } + + //DEBUG ((D_ERROR, "Checking firmware parameters...\n")); + + CheckPolicyStatus = CheckPolicyBuffer( (char *)ImageBuffer, + (INT32)ImageLength, + (INT32)AllowSV, + &UpdType, + &Ver ); + switch( UpdType ) + { + case DOWNGRADE_SUCCESS: + case SAMEVERSION_SUCCESS: + case UPGRADE_SUCCESS: + break; + + case DOWNGRADE_FAILURE: + //DEBUG ((D_ERROR, "FW Update downgrade not allowed\n")); + return EFI_SUCCESS; + break; + + case SAMEVERSION_FAILURE: + //DEBUG ((D_ERROR, "FW Update same version not allowed, specify /s on command line\n")); + return EFI_SUCCESS; + + default: + break; + } + + ZeroMem( &Password, sizeof(Password) ); + + if( This->AmiPostMgr != NULL ) + { + This->AmiPostMgr->DisplayProgress( + AMI_PROGRESS_BOX_INIT, + L"ME FW update", + L"Flash New ME Firmware", + NULL, + 0, + &DisplayHandle, + &OutKey ); + } + + FWUpdateStatus = FwUpdateFullBuffer( + (char*)ImageBuffer, + (unsigned int)ImageLength, + Password, + 0, + FWU_ENV_MANUFACTURING, + mOemId, + update_flags, + &DisplaySendStatus ); + if( FWUpdateStatus != FWU_ERROR_SUCCESS ) + { + //DEBUG ((D_ERROR, "FWUpdateStatus: %x\n", FWUpdateStatus)); + //if( ImageBuffer ) + // FreePool( ImageBuffer ); + return EFI_SUCCESS; + } + + //if( ImageBuffer ) + //{ + // Status = FreePool( ImageBuffer ); + //} + + Index = 0; + do + { + Symbol = (++Index % 2 == 0) ? '|':'-'; + + QueryStatus = FWUpdate_QueryStatus_Get_Response( + &UpdateStatus, + &TotalStages, + &PercentWritten, + &LastStatus, + &LastResetType ); + if( QueryStatus == FWU_ERROR_SUCCESS ) + { + //DEBUG ((D_ERROR, "FW Update: [ %d%% (Stage: %d of %d) (%c)]\r", PercentWritten, UpdateStatus, TotalStages, Symbol)); + if( This->AmiPostMgr != NULL ) + { + This->AmiPostMgr->DisplayProgress( + AMI_PROGRESS_BOX_UPDATE, + L"ME FW update", + L"Flash New ME Firmware", + NULL, + PercentWritten, + &DisplayHandle, + &OutKey ); + } + } + else if ( LastStatus != STATUS_UPDATE_NOT_READY ) + { + //DEBUG ((D_ERROR, "\nLastStatus: %x\n", LastStatus)); + break; + } + BS->Stall(100000); + } while( (PercentWritten != 100) && (QueryStatus == FWU_ERROR_SUCCESS) ); + + if( This->AmiPostMgr != NULL ) + { + This->AmiPostMgr->DisplayProgress( + AMI_PROGRESS_BOX_CLOSE, + L"ME FW update", + L"Flash New ME Firmware", + NULL, + 0, + &DisplayHandle, + &OutKey ); + } + + return EFI_SUCCESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MeFwUpdateProtocolEvent +// +// Description: The driver entry +// +// Input: +// +// Output: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MeFwUpdateProtocolEvent ( + IN EFI_EVENT Event, + IN EFI_HANDLE ImageHandle + ) +{ + UINT32 Dummy = 0; + UINTN VariableSize = sizeof(UINT8); + EFI_STATUS Status; + ME_FW_UPD_VERSION MeFwVersion; + + if (mMeFwImgVersion->MajorVersion != 0) { + Status = MeGetFwVersion(mMeFwUpdateLclProtocol, &MeFwVersion); + if (!EFI_ERROR (Status)) { + VariableSize = sizeof(ME_FW_UPD_VERSION); + // Set MbpMeFwVersion to "NV+BS", because MBP could be not available if + // Capsule Update mode. + pRS->SetVariable(L"MbpMeFwVersion", \ + &mAmiGlobalVariableGuid, \ + EFI_VARIABLE_NON_VOLATILE | \ + EFI_VARIABLE_BOOTSERVICE_ACCESS, \ + sizeof(ME_FW_UPD_VERSION), \ + &MeFwVersion); + } + } + // Check "MeAutoUpdateReq" variable if ME Auto Update is requested. + VariableSize = sizeof(UINT32); + Status = pRS->GetVariable(L"MeAutoUpdateReq", \ + &mAmiGlobalVariableGuid, NULL, &VariableSize, &Dummy); + if (EFI_ERROR(Status)) return EFI_SUCCESS; + + return EFI_SUCCESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MEFwUpdLclEntry +// +// Description: The driver entry +// +// Input: +// IN EFI_HANDLE ImageHandle +// OUT EFI_SYSTEM_TABLE *SystemTable +// Output: +// None +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MEFwUpdLclEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINT32 Dummy; + UINTN VariableSize = sizeof(UINT32); + EFI_HANDLE pHandle = NULL; + EFI_STATUS Status; + + InitAmiLib( ImageHandle, SystemTable ); + + Status = pBS->LocateProtocol( + &mPchPlatformPolicyProtocolGuid, + NULL, + &mPchPlatformPolicy ); + if( EFI_ERROR(Status) ) return EFI_SUCCESS; + + //Prepare ME firmware update local protocol + Status = pBS->AllocatePool( + EfiBootServicesData, + sizeof(ME_FW_UPDATE_LOCAL_PROTOCOL), + (VOID**)&mMeFwUpdateLclProtocol ); + if( EFI_ERROR(Status) ) + return Status; + + mMeFwUpdateLclProtocol->FwUpdBufferAddress = 0; + mMeFwUpdateLclProtocol->FwUpdBufferLength = 0; + mMeFwUpdateLclProtocol->FwUpdLcl = FwUpdLclFunc; + mMeFwUpdateLclProtocol->MeFwCheckMode = MeCheckFwState; + mMeFwUpdateLclProtocol->MeFwGetVersion = MeGetFwVersion; + mMeFwUpdateLclProtocol->HmrfpoEnable = MeUpdHmrfpoEnable; + mMeFwUpdateLclProtocol->PlatformReset = MeUpdPlatformReset; + mMeFwUpdateLclProtocol->PlatformUnlock = MeUpdPlatformUnlock; + mMeFwUpdateLclProtocol->AmiPostMgr = NULL; + + Status = pBS->InstallProtocolInterface( + &pHandle, + &mMeFwUpdLclProtocolGuid, + EFI_NATIVE_INTERFACE, + mMeFwUpdateLclProtocol ); + + MeFwUpdateProtocolEvent( NULL, NULL ); + + Status = pRS->GetVariable( + L"MeAutoUpdateReq", + &mAmiGlobalVariableGuid, + NULL, + &VariableSize, + &Dummy ); + if( EFI_ERROR(Status) || (Dummy == ME_UPD_LCL_SIGNATURE) ) + return EFI_SUCCESS; + + return EFI_SUCCESS; +} +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2015, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.cif b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.cif new file mode 100644 index 0000000..675fb33 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.cif @@ -0,0 +1,17 @@ +<component> + name = "ME Firmware Update Local" + category = ModulePart + LocalRoot = "\Chipset\eM\ME\MEUD\MEFwUpdLcl\" + RefName = "MEFwUpdLcl" +[files] +"MEFwUpdLcl.c" +"MeFwUpdLclProtocol.h" +"MEFwUpdLcl.sdl" +"MEFwUpdLcl.dxs" +"MEFwUpdLcl_SBY.dxs" +"MEFwUpdLcl.mak" +"MEFwUpdLclUpdateHooks.c" +"IntelLib\FWUpdateLib.h" +"IntelLib\me_status.h" +"IntelLib\FWUpdateLib.lib" +<endComponent> diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.dxs b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.dxs new file mode 100644 index 0000000..077fe27 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.dxs @@ -0,0 +1,9 @@ +#include <Protocol\HeciProtocol.h> +#include <Protocol\MeBiosPayloadData.h> +#include <Protocol\PchPlatformPolicy.h> +#include "MeFwUpdLclProtocol.h" + +DEPENDENCY_START + HECI_PROTOCOL_GUID AND + PCH_PLATFORM_POLICY_PROTOCOL_GUID +DEPENDENCY_END
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.mak b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.mak new file mode 100644 index 0000000..3eb64c2 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.mak @@ -0,0 +1,118 @@ +#********************************************************************** +#********************************************************************** +#** ** +#** (C)Copyright 1985-2010, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#********************************************************************** +#********************************************************************** + +#********************************************************************** +# $Header: /Alaska/SOURCE/Modules/OFBD Intel ME Update/CSP_MEUD/ME80/MEFwUpdLcl/MEFwUpdLcl.mak 2 5/14/15 4:28a Tristinchou $ +# +# $Revision: 2 $ +# +# $Date: 5/14/15 4:28a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/OFBD Intel ME Update/CSP_MEUD/ME80/MEFwUpdLcl/MEFwUpdLcl.mak $ +# +# 2 5/14/15 4:28a Tristinchou +# [TAG] EIP215437 +# [Category] New Feature +# [Description] ME capsule update support on SharkBay +# [Files] MEFwUpdLcl.c +# MeFwUpdLclProtocol.h +# MEFwUpdLcl.sdl +# MEFwUpdLcl.dxs +# MEFwUpdLcl.mak +# MEFwUpdLcl.cif +# +# 1 3/05/14 3:16a Tristinchou +# [TAG] EIP147099 +# [Category] Improvement +# [Description] Support ME FWUpdate API +# [Files] MEFwUpdLcl.cif +# MEFwUpdLcl.c +# MeFwUpdLclProtocol.h +# MEFwUpdLcl.sdl +# MEFwUpdLcl.dxs +# MEFwUpdLcl.mak +# IntelLib\FWUpdateLib.h +# IntelLib\me_status.h +# IntelLib\FWUpdateLib.lib +# +# 6 1/13/10 2:13p Felixp +# +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: <ComponentName>.mak +# +# Description: +# +#<AMI_FHDR_END> +#********************************************************************** +all : MEFwUpdLcl + +MEFwUpdLcl_LIBS=\ + $(EFIPROTOCOLLIB)\ + $(INTEL_FWUPDATE_LIB)\ + $(AMIDXELIB)\ + $(MeChipsetDxeLib_LIB)\ + $(MeLibDxe_LIB)\ + $(PchPlatformLib_LIB)\ + $(PchPlatformDxeLib_LIB)\ + $(EdkIIGlueBaseDebugLibNull_LIB) + +MEFwUpdLcl_INCLUDES=\ + $(ME_INCLUDES)\ + /I Core\ + +MEFwUpdLcl_OBJ = \ + $(BUILD_DIR)\$(MEFwUpdLcl_DIR)\MEFwUpdLcl.obj + +MEFwUpdLcl : $(BUILD_DIR)\MEFwUpdLcl.mak MEFwUpdLclBin + +$(BUILD_DIR)\MEFwUpdLcl.mak : $(MEFwUpdLcl_DIR)\$(@B).cif $(MEFwUpdLcl_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(MEFwUpdLcl_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +MEFwUpdLclBin : $(MEFwUpdLcl_LIBS) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\MEFwUpdLcl.mak all\ + "MY_INCLUDES=$(MEFwUpdLcl_INCLUDES)"\ + GUID=a11585b7-8fa2-4f1c-aa6f-dd6309469613\ + OBJECTS="$(MEFwUpdLcl_OBJ)" \ + ENTRY_POINT=MEFwUpdLclEntry\ + TYPE=BS_DRIVER \ +!IF "$(MEFWUPDLCL_ON_SHARKBAY_PLATFORM)"=="0" + DEPEX1=$(MEFwUpdLcl_DIR)\MEFwUpdLcl.dxs \ +!ELSE + DEPEX1=$(MEFwUpdLcl_DIR)\MEFwUpdLcl_SBY.dxs \ +!ENDIF + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + COMPRESS=1\ + +ReFlashBin : $(BUILD_DIR)\MEFwUpdLclUpdateHooks.obj + +$(BUILD_DIR)\MEFwUpdLclUpdateHooks.obj : $(MEFwUpdLcl_DIR)\MEFwUpdLclUpdateHooks.c + $(CC) /Fo$(BUILD_DIR)\MEFwUpdLclUpdateHooks.obj $(CFLAGS) $(MEFwUpdLcl_DIR)\MEFwUpdLclUpdateHooks.c +#********************************************************************** +#********************************************************************** +#** ** +#** (C)Copyright 1985-2010, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#********************************************************************** +#**********************************************************************
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.sdl b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.sdl new file mode 100644 index 0000000..6844616 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.sdl @@ -0,0 +1,51 @@ +TOKEN + Name = MEFwUpdLcl_SUPPORT + Value = 0 + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable MEFwUpdLcl support in Project" +End + +TOKEN + Name = "MEFWUPDLCL_ON_SHARKBAY_PLATFORM" + Value = "0" + TokenType = Boolean + TargetMAK = Yes +End + +MODULE + Help = "Includes MEFwUpdLcl.mak to Project" + File = "MEFwUpdLcl.mak" +End + +PATH + Name = "MEFwUpdLcl_DIR" +End + +TOKEN + Name = "INTEL_FWUPDATE_LIB" + Value = "$(MEFwUpdLcl_DIR)\IntelLib\FWUpdateLib.lib" + TokenType = Expression + TargetMAK = Yes +End + +ELINK + Name = "$(BUILD_DIR)\MEFwUpdLcl.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + +ELINK + Name = "AutoMeudBeforeReflashHook," + Parent = "OemBeforeFlashUpdateList" + InvokeOrder = AfterParent +End + +ELINK + Name = "AutoMeudAfterReflashHook," + Parent = "OemAfterFlashUpdateList" + InvokeOrder = AfterParent + Priority = -100 +End
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLclUpdateHooks.c b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLclUpdateHooks.c new file mode 100644 index 0000000..0ec4b8e --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLclUpdateHooks.c @@ -0,0 +1,596 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2015, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* +#include <AmiDxeLib.h> +#include <AmiHobs.h> +#include <Capsule.h> +#include <Token.h> +#include <Protocol/Decompress.h> +#include <Protocol/GuidedSectionExtraction.h> +#include <Protocol/AmiPostMgr.h> + +#include "MeFwUpdLclProtocol.h" + +#define SECTION_SIZE(SectionHeaderPtr) \ + ((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) SectionHeaderPtr)->Size) & 0x00ffffff)) +#define SIGNATURE_16(A, B) ((A) | (B << 8)) +#define SIGNATURE_32(A, B, C, D) (SIGNATURE_16 (A, B) | (SIGNATURE_16 (C, D) << 16)) + +#define EFI_CUSTOMIZED_DECOMPRESS_PROTOCOL_GUID \ + { 0x9a44198e, 0xa4a2, 0x44e6, 0x8a, 0x1f, 0x39, 0xbe, 0xfd, 0xac, 0x89, 0x6f } +#define ME_UPD_LCL_SIGNATURE SIGNATURE_32 ('_', 'M', 'U', 'L') +#define FV_GUID_OFFSET 0x60 + +extern EFI_GUID gAmiGlobalVariableGuid; +EFI_GUID mMeRegionFfsGuid = \ + { 0xDE90FFA8, 0xB985, 0x4575, 0xAB, 0x8D, 0xAD, 0xE5, 0x2C, 0x36, 0x2C, 0xA3 }; +EFI_GUID mMeVersionFfsFileGuid = \ + { 0x0B4AE6BE, 0x6DA6, 0x4908, 0x8A, 0x71, 0x7E, 0x6A, 0x8A, 0x33, 0xB1, 0x1C }; +EFI_GUID mMeVersionFfsSectionGuid = \ + { 0x6A6D576A, 0x8F38, 0x45E7, 0x97, 0xC0, 0x8A, 0xCD, 0x9E, 0x99, 0x26, 0x74 }; +EFI_GUID mEfiCustomizedDecompressProtocolGuid = \ + { 0X9A44198E, 0XA4A2, 0X44E6, 0X8A, 0X1F, 0X39, 0XBE, 0XFD, 0XAC, 0X89, 0X6F }; +static EFI_GUID mAmiPostManagerProtocolGuid = AMI_POST_MANAGER_PROTOCOL_GUID; +static AMI_POST_MANAGER_PROTOCOL *mAmiPostMgr = NULL; +ME_FW_UPD_VERSION mMeFwImgVersion[] = ME_FW_IMAGE_VERSION; +ME_FW_UPD_VERSION MbpMeFwVer; + +extern UINT8 *RecoveryBuffer; + +UINT8* +FvFindFfsFileByGuid ( + UINT8 *FvAddress, + EFI_GUID *pGuid +); + +VOID +AutoMeudBeforeReflashHook( + VOID +); + +VOID +AutoMeudAfterReflashHook( + VOID +); + +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: DecompressBinary +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +DecompressBinary( + IN UINTN *BinaryBuffer, + IN UINTN BinaryBufferSize, + OUT UINTN **DecompressBuffer, + OUT UINTN *DecompressBufferSize + ) +{ + EFI_STATUS Status; + EFI_FFS_FILE_HEADER *FfsFileHeader = NULL; + EFI_COMMON_SECTION_HEADER *SectionHeader = NULL; + UINTN NvarSize = 0; + VOID *NvarBuffer = NULL; + EFI_COMPRESSION_SECTION *CompressSection = NULL; + EFI_GUID_DEFINED_SECTION *GuidedSection = NULL; + EFI_DECOMPRESS_PROTOCOL *Decompress = NULL; + EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL *GuidedExtraction = NULL; + VOID *CompressionSource = NULL; + UINT32 CompressionSourceSize = 0; + UINT32 UncompressedLength = 0; + UINT8 CompressionType; + VOID *ScratchBuffer = NULL; + UINT32 ScratchSize = 0; + VOID *NewBuffer = NULL; + UINTN NewBufferSize = 0; + UINT32 AuthenticationStatus = 0; + + FfsFileHeader = (EFI_FFS_FILE_HEADER*)BinaryBuffer; + SectionHeader = (EFI_COMMON_SECTION_HEADER*)((UINT8*)FfsFileHeader + sizeof(EFI_FFS_FILE_HEADER)); + + if( FfsFileHeader->Type == EFI_FV_FILETYPE_RAW ) { + //The binary is the NVRAM ffs without any section, + //allocate the memory and copy it. + + NvarSize = BinaryBufferSize - sizeof(EFI_FFS_FILE_HEADER); + + Status = pBS->AllocatePool( EfiBootServicesData, + NvarSize, + &NvarBuffer ); + if( EFI_ERROR(Status) ) + return Status; + + MemCpy( NvarBuffer, (VOID*)SectionHeader, NvarSize ); + + *DecompressBuffer = NvarBuffer; + *DecompressBufferSize = NvarSize; + + return EFI_SUCCESS; + } + //The binary is the NVRAM ffs with section, + //determine the section type. + + switch( SectionHeader->Type ) + { + case EFI_SECTION_COMPRESSION: + //The section is compressed by PI_STD + CompressSection = (EFI_COMPRESSION_SECTION*)SectionHeader; + + CompressionSource = (VOID*)((UINT8*)CompressSection + sizeof(EFI_COMPRESSION_SECTION)); + CompressionSourceSize = (UINT32)(SECTION_SIZE(CompressSection) - sizeof(EFI_COMPRESSION_SECTION)); + UncompressedLength = CompressSection->UncompressedLength; + CompressionType = CompressSection->CompressionType; + + if( UncompressedLength > 0 ) + { + NewBufferSize = UncompressedLength; + + Status = pBS->AllocatePool( EfiBootServicesData, + NewBufferSize, + &NewBuffer ); + if( EFI_ERROR(Status) ) + return Status; + + if( CompressionType == EFI_NOT_COMPRESSED ) + { + MemCpy( NewBuffer, (VOID*)CompressionSource, NewBufferSize ); + } + else if ( CompressionType == EFI_STANDARD_COMPRESSION || + CompressionType == EFI_CUSTOMIZED_COMPRESSION ) + { + + if( CompressionType == EFI_STANDARD_COMPRESSION ) + { + Status = pBS->LocateProtocol( + &gEfiDecompressProtocolGuid, + NULL, + &Decompress ); + } + else + { + Status = pBS->LocateProtocol( + &mEfiCustomizedDecompressProtocolGuid, + NULL, + &Decompress ); + } + if( EFI_ERROR(Status) ) + { + pBS->FreePool( NewBuffer ); + return Status; + } + + Status = Decompress->GetInfo( Decompress, + CompressionSource, + CompressionSourceSize, + (UINT32 *)&NewBufferSize, + &ScratchSize ); + if( EFI_ERROR(Status) || (NewBufferSize != UncompressedLength)) + { + pBS->FreePool( NewBuffer ); + if(!EFI_ERROR (Status)) + Status = EFI_BAD_BUFFER_SIZE; + return Status; + } + + Status = pBS->AllocatePool( EfiBootServicesData, + ScratchSize, + &ScratchBuffer ); + if( EFI_ERROR(Status) ) + { + pBS->FreePool( NewBuffer ); + return Status; + } + + Status = Decompress->Decompress( Decompress, + CompressionSource, + CompressionSourceSize, + NewBuffer, + (UINT32)NewBufferSize, + ScratchBuffer, + ScratchSize ); + pBS->FreePool( ScratchBuffer ); + if( EFI_ERROR(Status) ) + { + pBS->FreePool( NvarBuffer ); + return Status; + } + + //The decompressed data is the EFI_SECTION_RAW + //Add the section header length to get data + SectionHeader = (EFI_COMMON_SECTION_HEADER*)NewBuffer; + + NvarSize = SECTION_SIZE(SectionHeader) - sizeof(EFI_COMMON_SECTION_HEADER); + NvarBuffer = (VOID*)((UINT8*)NewBuffer + sizeof(EFI_COMMON_SECTION_HEADER)); + } + } + + break; + + case EFI_SECTION_GUID_DEFINED: + + //The section is compressed by LZMA + GuidedSection = (EFI_GUID_DEFINED_SECTION*)SectionHeader; + + Status = pBS->LocateProtocol( &(GuidedSection->SectionDefinitionGuid), + NULL, + &GuidedExtraction ); + if( EFI_ERROR(Status) ) + return Status; + + Status = GuidedExtraction->ExtractSection( + GuidedExtraction, + GuidedSection, + &NewBuffer, + &NewBufferSize, + &AuthenticationStatus ); + if( EFI_ERROR(Status) ) + return Status; + + //The decompressed data is the EFI_SECTION_RAW + //Add the section header length to get data + SectionHeader = (EFI_COMMON_SECTION_HEADER*)NewBuffer; + + NvarSize = SECTION_SIZE(SectionHeader) - sizeof(EFI_COMMON_SECTION_HEADER); + NvarBuffer = (VOID*)((UINT8*)NewBuffer + sizeof(EFI_COMMON_SECTION_HEADER)); + + break; + + case EFI_SECTION_RAW: + + //The section is not compressed. + NvarSize = BinaryBufferSize - (sizeof(EFI_FFS_FILE_HEADER) + sizeof(EFI_COMMON_SECTION_HEADER)); + + Status = pBS->AllocatePool( EfiBootServicesData, + NvarSize, + &NvarBuffer ); + if( EFI_ERROR(Status) ) + return Status; + + MemCpy( NvarBuffer, (VOID*)((UINT8*)SectionHeader + sizeof(EFI_COMMON_SECTION_HEADER)), NvarSize ); + + break; + + default: + + NvarBuffer = NULL; + NvarSize = 0; + + break; + } + + *DecompressBuffer = NvarBuffer; + *DecompressBufferSize = NvarSize; + + return Status; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MeFwUpdateViaIntelLib +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MeFwUpdateViaIntelLib( + IN UINT8 *pBuffer, + IN AMI_POST_MANAGER_PROTOCOL *AmiPostMgr + ) +{ + EFI_STATUS Status; + UINTN *pMeRegionFile, *UcMeBuffer, UcMeBufferSize; + EFI_GUID mMeFwUpdLclProtocolGuid = ME_FW_UPD_LOCAL_PROTOCOL_GUID; + ME_FW_UPDATE_LOCAL_PROTOCOL *mMeFwUpdateLclProtocol = NULL; + EFI_FFS_FILE_HEADER *pHdr; + + // Locate ME FW Update Local Protocol. + Status = pBS->LocateProtocol (&mMeFwUpdLclProtocolGuid, \ + NULL, (VOID**)&mMeFwUpdateLclProtocol); + if(EFI_ERROR(Status) || (pBuffer == NULL)) return Status; + + // Check ME is in Normal mode. + Status = mMeFwUpdateLclProtocol->MeFwCheckMode(mMeFwUpdateLclProtocol, MeModeNormal); + if(EFI_ERROR(Status)) return Status; + + // Search the ME FW file from buffer. + if (((UINT8*)pMeRegionFile = FvFindFfsFileByGuid( \ + pBuffer, &mMeRegionFfsGuid)) == NULL) return Status; + + // Decompress the ME FW file.. + pHdr = (EFI_FFS_FILE_HEADER*)pMeRegionFile; + Status = DecompressBinary ( pMeRegionFile, \ + (UINTN)(*(UINT32*)pHdr->Size & 0xffffff), \ + &UcMeBuffer, &UcMeBufferSize); + if (EFI_ERROR(Status)) return Status; + + // Update reflash progress bar only if Secure flash capsule update. + // Do not display any messages if Windwos Firmware Update Capsule. + mMeFwUpdateLclProtocol->AmiPostMgr = NULL; + if (AmiPostMgr != NULL) mMeFwUpdateLclProtocol->AmiPostMgr = AmiPostMgr; + Status = mMeFwUpdateLclProtocol->FwUpdLcl(mMeFwUpdateLclProtocol, \ + (UINT8*)UcMeBuffer, UcMeBufferSize); + return Status; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: GetFvMeFwRegionAddress +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8* +GetFvMeFwRegionAddress( + UINT8 *StartAddress + ) +{ + EFI_GUID mMeFwCapsuleFirmwareVolumeGuid = ME_FW_CAPSULE_FIRMWARE_VOLUME_GUID; + if (!guidcmp((UINT8*)StartAddress + FV_GUID_OFFSET, \ + &mMeFwCapsuleFirmwareVolumeGuid)) return StartAddress; + if (!guidcmp((UINT8*)StartAddress + FLASH_SIZE + FV_GUID_OFFSET, \ + &mMeFwCapsuleFirmwareVolumeGuid)) return StartAddress + FLASH_SIZE; + return NULL; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: FvFindFfsFileByGuid +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8* +FvFindFfsFileByGuid( + UINT8 *FvAddress, + EFI_GUID *pGuid + ) +{ + EFI_FFS_FILE_HEADER *pFfsFile; + UINT32 i, FvLength = FLASH_SIZE, FileSize; + UINT8 *p = (UINT8*)NULL; + EFI_GUID EfiFirmwareFileSystem2Guid = EFI_FIRMWARE_FILE_SYSTEM2_GUID; + + if ((p = GetFvMeFwRegionAddress(FvAddress)) == NULL) return NULL; + FvLength = (UINT32)((EFI_FIRMWARE_VOLUME_HEADER*)p)->FvLength; + for (i = 0; (i + 16) < FvLength; i += 16) { + if (guidcmp (&((EFI_FIRMWARE_VOLUME_HEADER*)(p + i))->FileSystemGuid, \ + &EfiFirmwareFileSystem2Guid)) continue; + FileSize = ((EFI_FIRMWARE_VOLUME_HEADER*)(p + i))->HeaderLength; + pFfsFile = (EFI_FFS_FILE_HEADER*)(p + i + FileSize); + do { + if (!guidcmp (&((EFI_FFS_FILE_HEADER*)pFfsFile)->Name, pGuid)) { + return ((UINT8*)pFfsFile); + } + FileSize = *(UINT32 *)pFfsFile->Size & 0x00FFFFFF; + pFfsFile = (EFI_FFS_FILE_HEADER*)((UINT32)pFfsFile + FileSize); + pFfsFile = (EFI_FFS_FILE_HEADER*)(((UINT32)pFfsFile + 7) & 0xfffffff8); + } while(((*(UINT32 *)pFfsFile->Size & 0x00FFFFFF) != 0xFFFFFF) && \ + ((*(UINT32 *)pFfsFile->Size & 0x00FFFFFF) != 0)); + i += (UINT32)(((EFI_FIRMWARE_VOLUME_HEADER*)(p + i))->FvLength - 16); + } + return ((UINT8*)NULL); +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: CheckMeFirmwareVersion +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +BOOLEAN +CheckMeFirmwareVersion( + UINT8 *pFileSection + ) +{ + UINT8 *p = pFileSection + sizeof(EFI_COMMON_SECTION_HEADER); + ME_FW_UPD_VERSION *NewMeFwVer; + + if (guidcmp (p, &mMeVersionFfsSectionGuid)) return FALSE; + NewMeFwVer = (ME_FW_UPD_VERSION*)(p + sizeof (EFI_GUID)); + + // ??? PORTING REQUEST ??? [TO DO] if can't get ME FW version from MBP ?? + // ==== PORTING REQUEST ==== >> + if (MbpMeFwVer.MajorVersion != NewMeFwVer->MajorVersion) return FALSE; + if (MbpMeFwVer.MinorVersion < NewMeFwVer->MinorVersion) return FALSE; + if ((UINT32)((NewMeFwVer->HotfixVersion << 16) + NewMeFwVer->BuildVersion) > + (UINT32)((MbpMeFwVer.HotfixVersion << 16) + MbpMeFwVer.BuildVersion)) { + return TRUE; + } + // << ==== PORTING REQUEST ==== + return FALSE; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: IsMeFirmawareUpgraded +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +BOOLEAN +IsMeFirmawareUpgraded( + EFI_GUID *pGuid + ) +{ + UINT8 *pFfsFile; + if ((pFfsFile = FvFindFfsFileByGuid(RecoveryBuffer, pGuid)) == NULL) return FALSE; + return CheckMeFirmwareVersion (pFfsFile + sizeof(EFI_FFS_FILE_HEADER)); +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: IsWindowsFwUpdate +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +BOOLEAN +IsWindowsFwUpdate( + VOID + ) +{ + EFI_STATUS Status; + EFI_CAPSULE_HEADER *Capsule; + EFI_HOB_UEFI_CAPSULE *Hob; + static EFI_GUID ImageCapsuleGuid = W8_SCREEN_IMAGE_CAPSULE_GUID; + static EFI_GUID HobListGuid = HOB_LIST_GUID; + + if ((Hob = GetEfiConfigurationTable(pST, &HobListGuid)) == NULL) return FALSE; + do { + Status = FindNextHobByType(EFI_HOB_TYPE_UEFI_CAPSULE, &Hob); + if(!EFI_ERROR(Status)) { + Capsule = (EFI_CAPSULE_HEADER *)(VOID *)(UINTN)Hob->BaseAddress; + if(!guidcmp(&(Capsule->CapsuleGuid), &ImageCapsuleGuid)) return TRUE; + } + } while(!EFI_ERROR(Status)); + return FALSE; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: AutoMeudBeforeReflashHook +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +AutoMeudBeforeReflashHook( + VOID + ) +{ + UINTN Length = sizeof(ME_FW_UPD_VERSION); + EFI_STATUS Status; + + // Save "MeAutoUpdateReq" variable here for avoiding NVRAM could be updated later. + Status = pRS->GetVariable (L"MbpMeFwVersion", \ + &gAmiGlobalVariableGuid, NULL, &Length, &MbpMeFwVer); + if (EFI_ERROR(Status)) MemSet(&MbpMeFwVer, sizeof(ME_FW_UPD_VERSION), 0); + + // Start ME FW update process here if ME FW Capsule only. + if (RecoveryBuffer == GetFvMeFwRegionAddress(RecoveryBuffer)) { + EFI_EVENT event; + AutoMeudAfterReflashHook(); + if (mAmiPostMgr != NULL) + mAmiPostMgr->DisplayInfoBox(L"ME FW update", L"ME FW update completed, Press any key to reset the system", 5, &event); + pRS->ResetSystem(EfiResetCold, EFI_SUCCESS, 0, NULL); + } + + return; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: AutoMeudAfterReflashHook +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +AutoMeudAfterReflashHook( + VOID + ) +{ + EFI_STATUS Status = EFI_VOLUME_CORRUPTED; + UINT32 MeMode; + + if ((mMeFwImgVersion->MajorVersion != 0) && \ + (!IsMeFirmawareUpgraded(&mMeVersionFfsFileGuid))) return ; + if (!IsWindowsFwUpdate()) + Status = pBS->LocateProtocol(&mAmiPostManagerProtocolGuid, NULL, &mAmiPostMgr); + // ME FW Update API could returns error "EFI_VOLUME_CORRUPTED" if capsule mode + // in S3 resume path, so, we set the MeAutoUpdateReq variable to "_MUL" for + // trying update ME FW again if error. + MeMode = ME_UPD_LCL_SIGNATURE; + Status = MeFwUpdateViaIntelLib (RecoveryBuffer, mAmiPostMgr); + if (EFI_ERROR(Status)) + { + pRS->SetVariable (L"MeAutoUpdateReq", + &gAmiGlobalVariableGuid, + EFI_VARIABLE_NON_VOLATILE | \ + EFI_VARIABLE_BOOTSERVICE_ACCESS, \ + sizeof(UINT32), \ + &MeMode); + } + return; +} +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2015, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//*************************************************************************
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl_SBY.dxs b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl_SBY.dxs new file mode 100644 index 0000000..5728a1c --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl_SBY.dxs @@ -0,0 +1,14 @@ +#define HECI_PROTOCOL_GUID \ + { \ + 0xcfb33810, 0x6e87, 0x4284, 0xb2, 0x3, 0xa6, 0x6a, 0xbe, 0x7, 0xf6, 0xe8 \ + } + +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID \ + { \ + 0x9797aaf8, 0xe49b, 0x4f02, 0xa3, 0x68, 0xc8, 0x14, 0x8d, 0x2b, 0xc9, 0xe7 \ + } + +DEPENDENCY_START + HECI_PROTOCOL_GUID AND + DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID +DEPENDENCY_END
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/MeFwUpdLclProtocol.h b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MeFwUpdLclProtocol.h new file mode 100644 index 0000000..66c805e --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MeFwUpdLclProtocol.h @@ -0,0 +1,109 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2014, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** +#include <Protocol/AmiPostMgr.h> + +#define SEC_SMI_FLASH_GUID \ + { 0x3bf4af16, 0xab7c, 0x4b43, 0x89, 0x8d, 0xab, 0x26, 0xac, 0x5d, 0xdc, 0x6c } + +//{ DCA334AB-56E3-4EDE-B9B3-8EAE2ACF5E78 } +#define ME_FW_UPD_LOCAL_PROTOCOL_GUID \ + { 0xDCA334AB, 0x56E3, 0x4EDE, 0xB9, 0xB3, 0x8E, 0xAE, 0x2A, 0xCF, 0x5E, 0x78 } + +//{ 9F8B1DEF-B62B-45F3-8282-BFD7EA19801B } +#define ME_FW_CAPSULE_FIRMWARE_VOLUME_GUID \ + { 0x9F8B1DEF, 0xB62B, 0x45F3, 0x82, 0x82, 0xBF, 0xD7, 0xEA, 0x19, 0x80, 0x1B } + +typedef struct _ME_FW_UPD_VERSION { + UINT32 MajorVersion : 16; + UINT32 MinorVersion : 16; + UINT32 HotfixVersion : 16; + UINT32 BuildVersion : 16; +} ME_FW_UPD_VERSION; + +typedef enum { + MeModeNormal, + MeModeDebug, + MeModeTempDisabled, + MeModeSecOver, + MeModeFailed +} ME_FW_STATE; + +typedef struct _ME_FW_UPDATE_LOCAL_PROTOCOL ME_FW_UPDATE_LOCAL_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *ME_FW_UPD_LOCAL_FUNC) ( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This, + IN UINT8 *FileBuffer, + IN UINTN FileLength +); + +typedef +EFI_STATUS +(EFIAPI *ME_FW_CHECK_MODE) ( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This, + IN ME_FW_STATE MeFwState +); + +typedef +EFI_STATUS +(EFIAPI *ME_FW_CHECK_VERSION) ( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This, + IN ME_FW_UPD_VERSION *MeFwVerion +); + +typedef +EFI_STATUS +(EFIAPI *ME_MEI_HMRFPO_ENABLE) ( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This +); + +typedef +EFI_STATUS +(EFIAPI *PLATFORM_RESET) ( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This, + IN EFI_RESET_TYPE ResetType +); + +typedef +EFI_STATUS +(EFIAPI *PLATFORM_UNLOCK) ( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This, + IN UINT32 UnlockType OPTIONAL +); + +typedef struct _ME_FW_UPDATE_LOCAL_PROTOCOL { + EFI_PHYSICAL_ADDRESS FwUpdBufferAddress; + UINTN FwUpdBufferLength; + ME_FW_UPD_LOCAL_FUNC FwUpdLcl; + ME_FW_CHECK_MODE MeFwCheckMode; + ME_FW_CHECK_VERSION MeFwGetVersion; + ME_MEI_HMRFPO_ENABLE HmrfpoEnable; + PLATFORM_RESET PlatformReset; + PLATFORM_UNLOCK PlatformUnlock; + AMI_POST_MANAGER_PROTOCOL *AmiPostMgr; +}; +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2014, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//**********************************************************************
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsule.cif b/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsule.cif new file mode 100644 index 0000000..1858b65 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsule.cif @@ -0,0 +1,11 @@ +<component> + name = "MeFwCapsule" + category = ModulePart + LocalRoot = "\Chipset\eM\ME\MEUD\MeFwCapsule\" + RefName = "MeFwCapsule" +[files] +"MeFwCapsule.sdl" +"MeFwCapsule.mak" +"MeFwCapsulePei.c" +"MeFwCapsulePei.dxs" +<endComponent>
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsule.mak b/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsule.mak new file mode 100644 index 0000000..f605eda --- /dev/null +++ b/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsule.mak @@ -0,0 +1,348 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2014, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#********************************************************************** +# $Header: /Alaska/SOURCE/Modules/OFBD Intel ME Update/CSP_MEUD/ME80/MeFwCapsule/MeFwCapsule.mak 3 6/03/15 7:22a Tristinchou $ +# +# $Revision: 3 $ +# +# $Date: 6/03/15 7:22a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/OFBD Intel ME Update/CSP_MEUD/ME80/MeFwCapsule/MeFwCapsule.mak $(BUILD_DIR)\MeFwCapsulePei.mak MeFwCapsulePeiBin +# +# 3 6/03/15 7:22a Tristinchou +# [TAG] EIPNone +# [Category] Improvement +# [Description] Fix ME update capsule can't be generated. +# +# 2 5/14/15 5:08a Tristinchou +# +# 1 5/14/15 4:24a Tristinchou +# [TAG] EIP215437 +# [Category] New Feature +# [Description] ME capsule update support +# [Files] MeFwCapsule.cif +# MeFwCapsule.sdl +# MeFwCapsule.mak +# MeFwCapsulePei.c +# MeFwCapsulePei.dxs +# +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: +# +# Description: +# +#<AMI_FHDR_END> +#********************************************************************** +all : MeFwCapsulePei MeFwCapsule + +MeFwCapsulePei : $(BUILD_DIR)\MeFwCapsulePei.mak MeFwCapsulePeiBin + +MeFwCapsulePei_OBJ = \ + $(BUILD_DIR)\$(MeFwCapsule_DIR)\MeFwCapsulePei.obj + +$(BUILD_DIR)\MeFwCapsulePei.mak : $(MeFwCapsule_DIR)\MeFwCapsule.mak $(MeFwCapsule_DIR)\MeFwCapsule.cif $(BUILD_RULES) + $(CIF2MAK) $(MeFwCapsule_DIR)\MeFwCapsule.cif $(CIF2MAK_DEFAULTS) + +MeFwCapsulePeiBin : $(AMIPEILIB) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS) \ + /f $(BUILD_DIR)\MeFwCapsulePei.mak all \ + NAME=MeFwCapsulePei \ + MAKEFILE=$(BUILD_DIR)\MeFwCapsulePei.mak \ + GUID=FD27652D-F758-4EFC-B1A9-283EFE51F4E9 \ + ENTRY_POINT=MeFwCapsulePeiEntry \ + OBJECTS="$(MeFwCapsulePei_OBJ)" \ + DEPEX1="$(MeFwCapsule_DIR)\MeFwCapsulePei.dxs" DEPEX1_TYPE=EFI_SECTION_PEI_DEPEX \ + TYPE=PEIM \ + COMPRESS=0\ + +MeFwCapsule : MeFwExt MeFwCapsuleHdr MeFwCapFid MeFwVer MeFwLayout MeFwRegion MeFwFv + +MeFwExt : $(BUILD_DIR)\MeFwExt.ffs + +$(BUILD_DIR)\MeFwExt.obj: $(BUILD_DIR)\MeFwCapsule.mak + $(SILENT)copy << $(BUILD_DIR)\MeFwExt.c > NUL +#include <EFI.h> + +#define ME_CAPSULE_GUID \ + { 0x9F8B1DEF, 0xB62B, 0x45F3, 0x82, 0x82, 0xBF, 0xD7, 0xEA, 0x19, 0x80, 0x1B} + +static EFI_GUID MeCapsuleGuid = ME_CAPSULE_GUID; +static UINT32 Length = 0x14; +static UINT32 Pad = 0xFFFFFFFF; +<<KEEP + $(CC) /Fo$@ $(CFLAGS) $(BUILD_DIR)\MeFwExt.c + +$(BUILD_DIR)\MeFwExt.ffs : $(BUILD_DIR)\MeFwExt.obj + $(MAKE) /$(MAKEFLAGS) EXT_OBJS= $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\MeFwCapsule.mak bin\ + NAME=MeFwExt OBJECTS=$(BUILD_DIR)\MeFwExt.obj\ + MAKEFILE=$(BUILD_DIR)\MeFwCapsule.mak \ + TYPE=BINARY + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=FFFFFFFF-FFFF-FFFF-FFFF-FFFFFFFFFFFF \ + TYPE=EFI_FV_FILETYPE_RAW FFS_CHECKSUM=0\ + RAWFILE=$(BUILD_DIR)\MeFwExt.bin\ + FFSFILE=$@ COMPRESS=0 NAME=$(@B) + +#--------------------------------------------------------------------------- +# Generic MAK dependencies +#--------------------------------------------------------------------------- +$(BUILD_DIR)\MeFwCapsule.mak : $(MeFwCapsule_DIR)\MeFwCapsule.mak $(MeFwCapsule_DIR)\MeFwCapsule.cif $(BUILD_RULES) + $(CIF2MAK) $(MeFwCapsule_DIR)\MeFwCapsule.cif $(CIF2MAK_DEFAULTS) + +#--------------------------------------------------------------------------- +# Generic GUID defines. Aptio Tools must support these GUIDs +#--------------------------------------------------------------------------- +#GUID used to identify FW Capsule Hdr FFS file within the Firmware Volume. +FWCAPSULE_FFS_GUID = 414D94AD-998D-47D2-BFCD-4E882241DE32 +#Section GUID used to identify FW Capsule Hdr section within FwCap FFS file. +FWCAPSULE_FFS_SECTION_GUID = 5A88641B-BBB9-4AA6-80F7-498AE407C31F + +MeFwCapsuleHdr : $(BUILD_DIR)\MeFwCapsule.mak $(BUILD_DIR)\MeFwCapsuleHdr.ffs + +$(BUILD_DIR)\MeFwCapsuleHdr.obj: $(BUILD_DIR)\MeFwCapsule.mak + $(SILENT)copy << $(BUILD_DIR)\MeFwCapsuleHdr.c > NUL +#include <AmiCertificate.h> +#pragma pack(1) +APTIO_FW_CAPSULE_HEADER dummyHdr = + { { APTIO_FW_CAPSULE_GUID, + $(FWCAPSULE_MAX_HDR_SIZE), + CAPSULE_FLAGS_PERSIST_ACROSS_RESET | + CAPSULE_FLAGS_FWCERTBLOCK_VALID, // 1 - sig is invalid + $(FWCAPSULE_MAX_HDR_SIZE)}, + $(FWCAPSULE_MAX_HDR_SIZE), // Rom Offs + sizeof(APTIO_FW_CAPSULE_HEADER) // RomLayout Offs + }; +char pad[$(FWCAPSULE_MAX_HDR_SIZE)-sizeof(APTIO_FW_CAPSULE_HEADER)] = {0x55, 0xAA}; +<<KEEP + $(CC) /Fo$@ $(CFLAGS) $(BUILD_DIR)\MeFwCapsuleHdr.c + +$(BUILD_DIR)\MeFwCapsuleHdr.ffs : $(BUILD_DIR)\MeFwCapsuleHdr.obj $(BUILD_DIR)\MeFwCapsule.mak + $(MAKE) /$(MAKEFLAGS) EXT_OBJS= $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\MeFwCapsule.mak bin\ + NAME=MeFwCapsuleHdr OBJECTS=$(BUILD_DIR)\MeFwCapsuleHdr.obj\ + MAKEFILE=$(BUILD_DIR)\MeFwCapsule.mak \ + TYPE=BINARY + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=$(FWCAPSULE_FFS_GUID) \ + TYPE=EFI_FV_FILETYPE_FREEFORM FFS_CHECKSUM=0\ + SECTION_GUID=$(FWCAPSULE_FFS_SECTION_GUID) \ + RESOURCE=$(BUILD_DIR)\MeFwCapsuleHdr.bin \ + FFSFILE=$@ COMPRESS=0 NAME=$(@B) + +CSP_LIB_DIR = Core\CspLib + +MeFwCapFid : $(BUILD_DIR)\MeFwCapsule.mak $(BUILD_DIR)\MeFwCapFid.ffs + +$(BUILD_DIR)\MeFwCapFid.ffs : $(BUILD_DIR)\AMICspLib.mak + $(MAKE) /$(MAKEFLAGS) EXT_OBJS= $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\AMICspLib.mak bin\ + NAME=MeFwCapFid OBJECTS=$(BUILD_DIR)\$(CSP_LIB_DIR)\Fid.obj\ + MAKEFILE=$(BUILD_DIR)\AMICspLib.mak \ + TYPE=BINARY + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=3FD1D3A2-99F7-420b-BC69-8BB1D492A332 \ + TYPE=EFI_FV_FILETYPE_FREEFORM \ + FFSFILE=$@ COMPRESS=0 NAME=$(@B)\ + RESOURCE=$(BUILD_DIR)\Fid.bin \ + SECTION_GUID=2EBE0275-6458-4AF9-91ED-D3F4EDB100AA \ + +MeFwVer : $(BUILD_DIR)\MeFwCapsule.mak $(BUILD_DIR)\MeFwVer.ffs + +$(BUILD_DIR)\MeFwVer.obj: $(BUILD_DIR)\MeFwCapsule.mak + $(SILENT)copy << $(BUILD_DIR)\MeFwVer.c > NUL +#include <EFI.h> +#include <Token.h> + +typedef struct _FW_VERSION_NAME { + UINT32 MajorVersion : 16; + UINT32 MinorVersion : 16; + UINT32 HotfixVersion : 16; + UINT32 BuildVersion : 16; +} ME_FW_UPD_VERSION; + +const ME_FW_UPD_VERSION MeFwVersion[] = ME_FW_IMAGE_VERSION; +<<KEEP + $(CC) /Fo$@ $(CFLAGS) $(BUILD_DIR)\MeFwVer.c + +$(BUILD_DIR)\MeFwVer.ffs : $(BUILD_DIR)\MeFwVer.obj + $(MAKE) /$(MAKEFLAGS) EXT_OBJS= $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\MeFwCapsule.mak bin\ + NAME=MeFwVer OBJECTS=$(BUILD_DIR)\MeFwVer.obj\ + MAKEFILE=$(BUILD_DIR)\MeFwCapsule.mak \ + TYPE=BINARY + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=0B4AE6BE-6DA6-4908-8A71-7E6A8A33B11C \ + TYPE=EFI_FV_FILETYPE_FREEFORM FFS_CHECKSUM=0\ + SECTION_GUID=6A6D576A-8F38-45E7-97C0-8ACD9E992674 \ + RESOURCE=$(BUILD_DIR)\MeFwVer.bin \ + FFSFILE=$@ COMPRESS=0 NAME=$(@B) + +MeFwLayout : $(BUILD_DIR)\MeFwCapsule.mak $(BUILD_DIR)\MeFwLayout.ffs + +$(BUILD_DIR)\MeFwLayout.obj: $(BUILD_DIR)\MeFwCapsule.mak + $(SILENT)copy << $(BUILD_DIR)\MeFwLayout.c > NUL +#include <Token.h> +#include <RomLayout.h> + +ROM_AREA MeLayout[2] = {\ + { 0, 0, FV_MEFWCAP_SIZE, 0, 0x20A}, + { 0, 0, 0, 0, 0} +}; +<<KEEP + $(CC) /Fo$@ $(CFLAGS) $(BUILD_DIR)\MeFwLayout.c + +$(BUILD_DIR)\MeFwLayout.ffs : $(BUILD_DIR)\MeFwLayout.obj + $(MAKE) /$(MAKEFLAGS) EXT_OBJS= $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\MeFwCapsule.mak bin\ + NAME=MeFwLayout OBJECTS=$(BUILD_DIR)\MeFwLayout.obj\ + MAKEFILE=$(BUILD_DIR)\MeFwCapsule.mak \ + TYPE=BINARY + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=0DCA793A-EA96-42d8-BD7B-DC7F684E38C1 \ + TYPE=EFI_FV_FILETYPE_FREEFORM FFS_CHECKSUM=0\ + SECTION_GUID=88A15A4F-977D-4682-B17C-DA1F316C1F32 \ + RESOURCE=$(BUILD_DIR)\MeFwLayout.bin \ + FFSFILE=$@ COMPRESS=0 NAME=$(@B) + +MeFwRegion : $(BUILD_DIR)\MeFwRegion.ffs + +$(BUILD_DIR)\MeFwRegion.ffs : $(ME_BIN_FILE) + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=DE90FFA8-B985-4575-AB8D-ADE52C362CA3 \ + TYPE=EFI_FV_FILETYPE_FREEFORM \ + BINFILE=$** FFSFILE=$@ COMPRESS=1 NAME=$(**B) + +MeFwFv : MeFwExt MeFwCapsuleHdr MeFwCapFid MeFwVer MeFwLayout MeFwRegion $(BUILD_DIR)\FWkey.ffs +!IF EXIST ($(BUILD_DIR)\FV_MEFWCAP_VOL.inf ) + del $(BUILD_DIR)\FV_MEFWCAP_VOL.inf +!ENDIF + echo [options] >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf +# This is a dummy base address to store logos in ROMHOLE.This address has no effect in ROMHOLE. + echo EFI_BASE_ADDRESS = $(FV_MEFWCAP_BASE) >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_FILE_NAME = $(BUILD_DIR)\FV_MEFWCAP_VOL.FV >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_NUM_BLOCKS = $(FV_MEFWCAP_NUMBER_OF_BLOCK) >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_BLOCK_SIZE = $(FV_MEFWCAP_BLOCK_SIZE) >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo IGNORE_COMPRESSION = FALSE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo [attributes] >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_READ_DISABLED_CAP = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_READ_ENABLED_CAP = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_READ_STATUS = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_WRITE_DISABLED_CAP = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_WRITE_ENABLED_CAP = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_WRITE_STATUS = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_LOCK_CAP = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_LOCK_STATUS = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_STICKY_WRITE = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_MEMORY_MAPPED = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ERASE_POLARITY = 1 >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_CAP = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_2 = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_4 = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_8 = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_16 = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_32 = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_64 = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_128 = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_256 = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_512 = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_1K = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_2K = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_4K = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_8K = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_16K = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_32K = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_64K = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_READ_LOCK_CAP = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_READ_LOCK_STATUS = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_WRITE_LOCK_CAP = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_WRITE_LOCK_STATUS = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_FVB2_ALIGNMENT = 8 >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo [files] >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_FILE_NAME = $(BUILD_DIR)\MeFwExt__.pkg >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_FILE_NAME = $(BUILD_DIR)\MeFwCapsuleHdr__.pkg >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_FILE_NAME = $(BUILD_DIR)\MeFwCapFid__.pkg >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_FILE_NAME = $(BUILD_DIR)\MeFwVer__.pkg >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_FILE_NAME = $(BUILD_DIR)\MeFwLayout__.pkg >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf +!IF $(CREATE_FWCAPSULE) == 1 + echo EFI_FILE_NAME = $(BUILD_DIR)\FWkey__.pkg >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf +!ENDIF + echo EFI_FILE_NAME = $(BUILD_DIR)\MeFwRegion__.pkg >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf +!IF $(PI_SPECIFICATION_VERSION) >= 0x00010000 + $(FWBUILD) $(UNSIGNED_MEFW_CAPSULE) /f $(BUILD_DIR)\FV_MEFWCAP_VOL.inf /p 1.0 +!ELSE + $(FWBUILD) $(UNSIGNED_MEFW_CAPSULE) /f $(BUILD_DIR)\FV_MEFWCAP_VOL.inf +!ENDIF + if exist $(BIOS_MEFW_CAPSULE_FILE) @del $(BIOS_MEFW_CAPSULE_FILE) + if exist $(MEFW_CAPSULE_FILE) @del $(MEFW_CAPSULE_FILE) + +End : CombineFwCapsule +BUILD_ME : SignMeFwCapsule + +ME_FW_LAYOUT_EX = $(BUILD_DIR)\MeFwLayoutEx.bin + +CombineFwCapsule : + $(SILENT)copy /b $(UNSIGNED_BIOS_ROM)+$(UNSIGNED_MEFW_CAPSULE) $(UNSIGNED_MEFW_CAPSULE)2 + +$(ME_FW_LAYOUT_EX) : $(UNSIGNED_MEFW_CAPSULE) + @if not exist $@ $(FWBUILD) $(UNSIGNED_MEFW_CAPSULE) /s /m $(ME_FW_LAYOUT_EX) + +!IF "$(MEFWUPDLCL_ON_SHARKBAY_PLATFORM)"=="0" +SignMeFwCapsule : $(UNSIGNED_BIOS_ROM) $(ROM_LAYOUT_EX) MeFwFv $(ME_FW_LAYOUT_EX) +!ELSE +SignMeFwCapsule : $(UNSIGNED_BIOS_ROM) $(ROM_LAYOUT_EX) MeFwFv $(ME_FW_LAYOUT_EX) CombineFwCapsule +!ENDIF + @echo ---------------------------------------------------------------- + @echo ----- create Signed BIOS + ME FW Capsule : "$(BIOS_MEFW_CAPSULE_FILE)" ------ + @echo ---------------------------------------------------------------- +!IF !EXIST($(FWpriv)) || ("$(FWCAPSULE_CERT_FORMAT)"=="0" && !EXIST($(FWrootKey))) + @echo ----- WARNING!!! Missing RSA private key FWpriv=$(FWpriv) to sign BIOS + ME FW Capsule image. +!ELSE + $(CRYPTCON) -c2 -y -r$(ROM_LAYOUT_EX) -l$(FWCAPSULE_MAX_HDR_SIZE) -f $(UNSIGNED_MEFW_CAPSULE)2 -o $(UNSIGNED_MEFW_CAPSULE)2 + $(CRYPTCON) $(CRYPTOCON_CMDLINE_MEFWCAP) -f $(UNSIGNED_MEFW_CAPSULE)2 -o $(BIOS_MEFW_CAPSULE_FILE) +!ENDIF + @echo ---------------------------------------------------------------- + @echo ----- create Signed ME FW Capsule : "$(MEFW_CAPSULE_FILE)" ------------- + @echo ---------------------------------------------------------------- +!IF !EXIST($(FWpriv)) || ("$(FWCAPSULE_CERT_FORMAT)"=="0" && !EXIST($(FWrootKey))) + @echo ----- WARNING!!! Missing RSA private key FWpriv=$(FWpriv) to sign ME FW Capsule image. +!ELSE + $(CRYPTCON) -c2 -y -r$(ME_FW_LAYOUT_EX) -l$(FWCAPSULE_MAX_HDR_SIZE) -f $(UNSIGNED_MEFW_CAPSULE) -o $(UNSIGNED_MEFW_CAPSULE).Sig + $(CRYPTCON) $(CRYPTOCON_CMDLINE_MEFWCAP) -f $(UNSIGNED_MEFW_CAPSULE).Sig -o $(MEFW_CAPSULE_FILE) +!ENDIF + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2014, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsule.sdl b/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsule.sdl new file mode 100644 index 0000000..7ee2650 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsule.sdl @@ -0,0 +1,115 @@ +TOKEN + Name = MeFwCapsule_SUPPORT + Value = 1 + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Help = "Main switch to enable MeFwCapsule support in Project" + Master = Yes + Token = "MEFwUpdLcl_SUPPORT" "=" "1" +End + +TOKEN + Name = "ME_BIN_FILE" + Value = "$(ROM_IMAGE_DIR)\ME\ME9.1_5M_Production.BIN" + TokenType = Expression + TargetH = Yes + TargetMAK = Yes +End + +TOKEN + Name = "ME_FW_IMAGE_VERSION" + Value = "{9, 1, 25, 1005}" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "FV_MEFWCAP_SIZE" + Value = "0x400000" + TokenType = Integer + TargetH = Yes + TargetMAK = Yes +End + +TOKEN + Name = "BIOS_MEFW_CAPSULE_FILE" + Value = "BIOSMEFW.CAP" + Help = "File name of the BIOS + ME FW image to be signed." + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "MEFW_CAPSULE_FILE" + Value = "MEFW.CAP" + Help = "File name of the ME FW image to be signed." + TokenType = Expression + TargetMAK = Yes +End + +MODULE + Help = "Includes MeFwCapsule.mak to Project" + File = "MeFwCapsule.mak" +End + +PATH + Name = "MeFwCapsule_DIR" +End + +TOKEN + Name = "UNSIGNED_MEFW_CAPSULE" + Value = "$(BUILD_DIR)\FV_MEFWCAP.fv" + Help = "File name of the BIOS image to be signed." + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "CRYPTOCON_CMDLINE_MEFWCAP" + Value = "-c $(FWrootKey) -k $(FWpriv) -n -y -l $(FWCAPSULE_MAX_HDR_SIZE) -q -r2" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "FV_MEFWCAP_BASE" + Value = "0xFFFFFFFF-$(FV_MEFWCAP_SIZE)+1" + Help = "Number of Block used for ROMHOLE" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes +End + +TOKEN + Name = "FV_MEFWCAP_BLOCK_SIZE" + Value = "0x1000" + Help = "Size of Block used for ROMHOLE" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes +End + +TOKEN + Name = "FV_MEFWCAP_NUMBER_OF_BLOCK" + Value = "$(FV_MEFWCAP_SIZE) / $(FV_MEFWCAP_BLOCK_SIZE)" + Help = "Number of Block used for ROMHOLE" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes +End + +TOKEN + Name = "FWCAPSULE_IMAGE_SIZE" + Value = "$(FLASH_SIZE)+$(FWCAPSULE_MAX_HDR_SIZE)+$(FV_MEFWCAP_SIZE)" + TokenType = Integer + TargetH = Yes + Token = "MeFwCapsule_SUPPORT" "=" "1" +End + +ELINK + Name = "$(BUILD_DIR)\MeFwCapsulePei.ffs" + Parent = "FV_BB" + #Priority = 10 + InvokeOrder = AfterParent +End
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsulePei.c b/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsulePei.c new file mode 100644 index 0000000..db54c27 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsulePei.c @@ -0,0 +1,185 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2015, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* +/** @file MeFwCapsulePei.c + ME FW Capsule Update Pei driver. +**/ +//********************************************************************** +//---------------------------------------------------------------------------- +// Includes +// Statements that include other files +#include <PEI.h> +#include <AmiPeiLib.h> +#include <FlashUpd.h> +#include <Token.h> +#include <PPI\NBPPI.h> +#include <FlashUpd.h> +#include <AmiHobs.h> +//---------------------------------------------------------------------------- +// Function Externs +EFI_GUID mFlashUpdBootModePpiGuid = EFI_PEI_BOOT_IN_FLASH_UPDATE_MODE_PEIM_PPI; +EFI_GUID mAmiPeiBeforeMrcGuid = AMI_PEI_BEFORE_MRC_GUID; +EFI_GUID mAmiCapsuleHobGuid = AMI_CAPSULE_HOB_GUID; +//---------------------------------------------------------------------------- +// Local prototypes +EFI_STATUS +MeFwBootOnFlashUpdateNotify ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *NullPpi +); +EFI_STATUS +MeFwBeforeMrcNotify ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *NullPpi +); + +// PPI to be installed +static +EFI_PEI_NOTIFY_DESCRIPTOR +MeFwBootOnFlashUpdateNotifyList[] = { + { EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | \ + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, \ + &mFlashUpdBootModePpiGuid, MeFwBootOnFlashUpdateNotify }, +}; + +static +EFI_PEI_NOTIFY_DESCRIPTOR +MeFwBeforeMrcNotifyList[] = { + { EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | \ + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &mAmiPeiBeforeMrcGuid, MeFwBeforeMrcNotify } +}; + +//---------------------------------------------------------------------------- +// Local Variables + +//---------------------------------------------------------------------------- +// Function Definitions +#define R_PCH_ACPI_PM1_STS 0x00 +#define B_PCH_ACPI_PM1_STS_WAK 0x8000 +#define R_PCH_ACPI_PM1_CNT 0x04 +#define B_PCH_ACPI_PM1_CNT_SLP_TYP 0x00001C00 +#define R_PCH_RST_CNT 0xCF9 +#define V_PCH_RST_CNT_SOFTRESET 0x04 +#define V_PCH_RST_CNT_SOFTSTARTSTATE 0x00 + +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MeFwBootOnFlashUpdateNotify +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MeFwBootOnFlashUpdateNotify ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *NullPpi +) +{ + VOID *p; + + for ((*PeiServices)->GetHobList(PeiServices,&p); \ + !(FindNextHobByGuid(&mAmiCapsuleHobGuid, &p)); ) { + // When the gFlashUpdBootModePpi is installed, bios identify the Capsule Guid + // either APTIO FW or Windows FW Capsule, so, we just check the Capsule Length + // for determine whether contains the ME FW. + if ((((AMI_CAPSULE_HOB*)p)->CapsuleLength != FWCAPSULE_IMAGE_SIZE) && \ + (((AMI_CAPSULE_HOB*)p)->CapsuleLength != \ + (FV_MEFWCAP_SIZE + FWCAPSULE_MAX_HDR_SIZE))) continue; + // Clear Wake Status (WAK_STS) and Sleep Type (SLP_TYP) + IoWrite16(PM_BASE_ADDRESS + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_WAK); + IoWrite16(PM_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, \ + IoRead16(PM_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT) & ~B_PCH_ACPI_PM1_CNT_SLP_TYP); + // Since, HECI interface not work if S3 resume path, to generate a Soft Reset + // to re-activate HECI. + IoWrite8(R_PCH_RST_CNT, V_PCH_RST_CNT_SOFTSTARTSTATE); + IoWrite8(R_PCH_RST_CNT, V_PCH_RST_CNT_SOFTRESET); + EFI_DEADLOOP() + } + return EFI_SUCCESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MeFwBeforeMrcNotify +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MeFwBeforeMrcNotify ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *NullPpi +) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + + Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode); + if (EFI_ERROR(Status) || (BootMode != BOOT_ON_S3_RESUME)) return EFI_SUCCESS; + (*PeiServices)->NotifyPpi (PeiServices, MeFwBootOnFlashUpdateNotifyList); + return EFI_SUCCESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MeFwCapsulePeiEntry +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MeFwCapsulePeiEntry ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices +) +{ + (*PeiServices)->NotifyPpi (PeiServices, MeFwBeforeMrcNotifyList); + return EFI_SUCCESS; +} +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2015, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsulePei.dxs b/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsulePei.dxs new file mode 100644 index 0000000..16c6253 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsulePei.dxs @@ -0,0 +1,3 @@ +DEPENDENCY_START + TRUE +DEPENDENCY_END
\ No newline at end of file |