diff options
| author | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
|---|---|---|
| committer | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
| commit | b7c51c9cf4864df6aabb99a1ae843becd577237c (patch) | |
| tree | eebe9b0d0ca03062955223097e57da84dd618b9a /Chipset | |
| download | zprj-b7c51c9cf4864df6aabb99a1ae843becd577237c.tar.xz | |
Diffstat (limited to 'Chipset')
210 files changed, 72496 insertions, 0 deletions
diff --git a/Chipset/NB/GOP/Haswell/IntelGopDriver.efi b/Chipset/NB/GOP/Haswell/IntelGopDriver.efi Binary files differnew file mode 100644 index 0000000..04f8cc0 --- /dev/null +++ b/Chipset/NB/GOP/Haswell/IntelGopDriver.efi diff --git a/Chipset/NB/GOP/Haswell/vbt.bin b/Chipset/NB/GOP/Haswell/vbt.bin Binary files differnew file mode 100644 index 0000000..0fca66b --- /dev/null +++ b/Chipset/NB/GOP/Haswell/vbt.bin diff --git a/Chipset/NB/GOP/IntelGopDriver.dxs b/Chipset/NB/GOP/IntelGopDriver.dxs new file mode 100644 index 0000000..40408e8 --- /dev/null +++ b/Chipset/NB/GOP/IntelGopDriver.dxs @@ -0,0 +1,61 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2015, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelGopDriver.dxs 2 1/27/15 11:17p Dennisliu $ +// +// $Revision: 2 $ +// +// $Date: 1/27/15 11:17p $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelGopDriver.dxs $ +// +// 2 1/27/15 11:17p Dennisliu +// [TAG] EIP202457 +// [Category] Improvement +// [Description] Implement Loading Intel GOP driver Condition +// [Files] +// Chipset\NB\GOP\IntelGopDriver.dxs +// Chipset\NB\GOP\IntelSaGopDriver.mak +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: IntelGopDriver.dxs +// +// Description: Dependency expression file for Intel GOP driver. +// +//<AMI_FHDR_END> +//************************************************************************* +#include <Protocol\IntelSaGopDriver.h> + +DEPENDENCY_START + EFI_PLATFORM_GOP_POLICY_PROTOCOL_GUID +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2015, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/GOP/IntelSaGopDriver.cif b/Chipset/NB/GOP/IntelSaGopDriver.cif new file mode 100644 index 0000000..4b181d4 --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopDriver.cif @@ -0,0 +1,17 @@ +<component> + name = "Intel SA GOP Driver" + category = ModulePart + LocalRoot = "Chipset\NB\GOP\" + RefName = "IntelSaGopDriver" +[files] +"IntelSaGopDriver.sdl" +"IntelSaGopDriver.mak" +"IntelSaGopPolicy.c" +"IntelSaGopDriver.dxs" +"IntelGopDriver.dxs" +"Haswell\IntelGopDriver.efi" +"Haswell\vbt.bin" +[parts] +"IntelSaGopSetup" +"IntelSaGopDriverProtocol" +<endComponent> diff --git a/Chipset/NB/GOP/IntelSaGopDriver.dxs b/Chipset/NB/GOP/IntelSaGopDriver.dxs new file mode 100644 index 0000000..9074cbc --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopDriver.dxs @@ -0,0 +1,61 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelSaGopDriver.dxs 1 3/08/12 10:54p Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 3/08/12 10:54p $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelSaGopDriver.dxs $ +// +// 1 3/08/12 10:54p Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Create Haswell Intel SA GOP Driver module part. +// Notice : IntelGopDriver.efi and vbt.bin is dummy files. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: IntelSaGopDriver.dxs +// +// Description: Dependency expression file for Platform GOP Policy driver. +// +//<AMI_FHDR_END> +//************************************************************************* +#include <Protocol\CpuIo.h> +#include <PlatformInfo.h> + +DEPENDENCY_START + EFI_CPU_IO_PROTOCOL_GUID AND + EFI_PLATFORM_INFO_PROTOCOL_GUID +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/GOP/IntelSaGopDriver.mak b/Chipset/NB/GOP/IntelSaGopDriver.mak new file mode 100644 index 0000000..0dfa205 --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopDriver.mak @@ -0,0 +1,69 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +all : IntelSaGopDriver IgbGOPDriver + +IntelSaGopDriver : $(BUILD_DIR)\IntelSaGopDriver.mak IntelSaGopDriverBin + +IgbGOPDriver: $(BUILD_DIR)\BmpDummyName.ffs $(BUILD_DIR)\IntelGopDriver.ffs + + +$(BUILD_DIR)\IntelSaGopDriver.mak : $(IntelSaGopDriver_DIR)\$(@B).cif $(IntelSaGopDriver_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(IntelSaGopDriver_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +IntelSaGopDriver_INCLUDES=\ + $(PLATFORM_INFO_INCLUDES)\ + $(DxeKscLib_INCLUDES)\ + $(INTEL_MCH_INCLUDES)\ + +IntelSaGopDriverBin : $(AMIDXELIB) $(DxeKscLib_LIB) $(AMICSPLib) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\IntelSaGopDriver.mak all\ + GUID=5c266089-e103-4d43-9ab5-12d7095be2af\ + "MY_INCLUDES=$(IntelSaGopDriver_INCLUDES)"\ + ENTRY_POINT=IntelSaGopPolicyEntryPoint\ + DEPEX1=$(IntelSaGopDriver_DIR)\IntelSaGopDriver.dxs \ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + TYPE=BS_DRIVER\ + COMPRESS=1 + +$(BUILD_DIR)\BmpDummyName.ffs : $(OEM_INTEL_GOP_VBT_BIN_FILE) + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=878AC2CC-5343-46F2-B563-51F89DAF56BA \ + TYPE=EFI_FV_FILETYPE_RAW \ + RAWFILE=$** FFSFILE=$@ COMPRESS=0 NAME=BmpDummyName + +$(BUILD_DIR)\IntelGopDriver.ffs : $(OEM_INTEL_GOP_EFI_DRIVER_FILE) + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=5BBA83E6-F027-4ca7-BFD0-16358CC9E123 \ + TYPE=EFI_FV_FILETYPE_DRIVER \ + DEPEX1=$(IntelSaGopDriver_DIR)\IntelGopDriver.dxs\ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + PEFILE=$** FFSFILE=$@ COMPRESS=0 NAME=IntelGopDriver + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/NB/GOP/IntelSaGopDriver.sdl b/Chipset/NB/GOP/IntelSaGopDriver.sdl new file mode 100644 index 0000000..551c88a --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopDriver.sdl @@ -0,0 +1,59 @@ +TOKEN + Name = "IntelSaGopDriver_SUPPORT" + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Master = Yes + Help = "Main switch to enable IntelSaGopDriver support in Project" +End + +PATH + Name = "IntelSaGopDriver_DIR" +End + +MODULE + Help = "Includes IntelSaGopDriver.mak to Project" + File = "IntelSaGopDriver.mak" +End + +TOKEN + Name = "====== Haswell ======" + TokenType = Expression +End + +TOKEN + Name = "OEM_INTEL_GOP_VBT_BIN_FILE" + Value = "$(IntelSaGopDriver_DIR)\Haswell\Vbt.bin" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "OEM_INTEL_GOP_EFI_DRIVER_FILE" + Value = "$(IntelSaGopDriver_DIR)\Haswell\IntelGopDriver.efi" + TokenType = Expression + TargetMAK = Yes +End + +ELINK + Name = "$(BUILD_DIR)\IntelSaGopDriver.ffs" + Parent = "FV_MAIN" + InvokeOrder = BeforeParent +End + +ELINK + Name = "$(BUILD_DIR)\IntelGopDriver.ffs" + Parent = "FV_MAIN" + InvokeOrder = BeforeParent +End + +ELINK + Name = "$(BUILD_DIR)\BmpDummyName.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + + + diff --git a/Chipset/NB/GOP/IntelSaGopPolicy.c b/Chipset/NB/GOP/IntelSaGopPolicy.c new file mode 100644 index 0000000..ccc3b8d --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopPolicy.c @@ -0,0 +1,405 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelSaGopPolicy.c 5 5/13/14 10:42p Dennisliu $ +// +// $Revision: 5 $ +// +// $Date: 5/13/14 10:42p $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelSaGopPolicy.c $ +// +// 5 5/13/14 10:42p Dennisliu +// [TAG] EIP167027 +// [Category] Improvement +// [Description] [SharkBay Aptio4]Variable's attribute needs to be +// reviewed by SA component driver +// [Files] NBDXEBoard.c; IntelSaGopSetup.c; IntelSaGopPolicy.c; +// NBDxe.c; NbPciCSP.c; PciHostBridge.c; +// +// 4 10/31/12 6:33a Jeffch +// [TAG] None +// [Category] Improvement +// [Description] Add update GOP VBT address event. +// +// 3 8/14/12 5:42a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Implemented BIOS Integration Guide Rev 1.0 to Intel SA +// GOP driver. +// [Files] IntelSaGopDriver.cif, IntelSaGopDriver.mak, +// IntelSaGopDriver.sdl, +// IntelSaGopPolicy.c, IntelSaGopSetup.c, IntelSaGopSetup.h, +// IntelSaGopSetup.mak, IntelSaGopSetup.sd, IntelSaGopSetup.sdl, +// IntelSaGopSetup.uni, IntelSaGopSwitch.c, +// IntelSaGopDriver.h, +// NBPlatformData.h +// +// 2 7/27/12 7:42a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Fix building error after update 4.6.5.4_Csm_OptOut_03. +// [Files] IntelSaGopPolicy.c +// +// 1 3/08/12 10:54p Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Create Haswell Intel SA GOP Driver module part. +// Notice : IntelGopDriver.efi and vbt.bin is dummy files. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: IntelSaGopPolicy.c +// +// Description: This file initialises and Installs TerminalPlatformPolicy Protocol. +// +//<AMI_FHDR_END> +//********************************************************************** +#include <Token.h> +#include <AmiDxeLib.h> +#include <KscLib.h> +#include <Setup.h> +#include <AmiCspLib.h> +#include <Protocol\IntelSaGopDriver.h> +#include <Protocol\NBPlatformData.h> +#if defined(CsmOptOut_SUPPORT) && (CsmOptOut_SUPPORT == 1) +#include <AmiLoadCsmPolicy.h> +#endif +#define _SA_COMMON_DEFINITIONS_H_ +#include <Protocol\SaPlatformPolicy\SaPlatformPolicy.h> + +EFI_GUID gPlatformGOPPolicyGuid = EFI_PLATFORM_GOP_POLICY_PROTOCOL_GUID; +EFI_GUID gDxePlatformSaPolicyGuid = DXE_PLATFORM_SA_POLICY_GUID; +EFI_GUID gSetupGuid = SETUP_GUID; +#if defined(CsmOptOut_SUPPORT) && (CsmOptOut_SUPPORT == 1) +EFI_GUID gAmiOpromPolicyProtocolGuid = AMI_OPROM_POLICY_PROTOCOL_GUID; +EFI_GUID gAmiLoadCsmGuid = AMI_LOAD_CSM_GUID; +#endif + +PLATFORM_GOP_POLICY_PROTOCOL mPlatformGOPPolicy; +DXE_PLATFORM_SA_POLICY_PROTOCOL *gDxePlatformSaPolicy; +#if defined(CsmOptOut_SUPPORT) && (CsmOptOut_SUPPORT == 1) +AMI_OPROM_POLICY_PROTOCOL *gAmiOpRomPolicyProtocol = NULL; +VOID *gInterface = NULL; +#endif +// +// Function implementations +// + +EFI_STATUS +GetPlatformLidStatus ( + OUT LID_STATUS *CurrentLidStatus +) +{ +#if defined CRB_EC_SUPPORT && CRB_EC_SUPPORT == 1 + EFI_STATUS Status; + UINT8 PortDataOut; + Status = InitializeKscLib (); + + if (Status == EFI_SUCCESS) { + Status = SendKscCommand(KSC_C_READ_MEM); + if (Status == EFI_SUCCESS) { + Status = SendKscData(0x03); + if (Status == EFI_SUCCESS) { + Status = ReceiveKscData (&PortDataOut); + if (Status == EFI_SUCCESS) { + // + // Bit6 = Lid State (1 = Open, 0 = Closed) + // + if ((PortDataOut & BIT6) >> 6) + *CurrentLidStatus = LidOpen; + else + *CurrentLidStatus = LidClosed; + return EFI_SUCCESS; + } + } + } + } +#endif + + return EFI_UNSUPPORTED; +} + +EFI_STATUS +GetVbtData ( + OUT EFI_PHYSICAL_ADDRESS *VbtAddress, + OUT UINT32 *VbtSize +) +{ + EFI_STATUS Status; + UINTN FvProtocolCount; + EFI_HANDLE *FvHandles; +#if (PI_SPECIFICATION_VERSION < 0x00010000) + EFI_FIRMWARE_VOLUME_PROTOCOL *Fv; +#else + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv; +#endif + UINTN Index; + UINT32 AuthenticationStatus; + EFI_FV_FILETYPE FileType; + EFI_FV_FILE_ATTRIBUTES FileAttributes; + + UINT8 *Buffer; + UINTN VbtBufferSize; + EFI_GUID BmpImageGuid = { 0x878AC2CC, 0x5343, 0x46F2, 0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA }; + + Buffer = NULL; + FvHandles = NULL; + Status = pBS->LocateHandleBuffer ( + ByProtocol, + #if (PI_SPECIFICATION_VERSION < 0x00010000) + &gEfiFirmwareVolumeProtocolGuid, + #else + &gEfiFirmwareVolume2ProtocolGuid, + #endif + NULL, + &FvProtocolCount, + &FvHandles + ); + if (!EFI_ERROR (Status)) { + for (Index = 0; Index < FvProtocolCount; Index++) { + Status = pBS->HandleProtocol ( + FvHandles[Index], + #if (PI_SPECIFICATION_VERSION < 0x00010000) + &gEfiFirmwareVolumeProtocolGuid, + #else + &gEfiFirmwareVolume2ProtocolGuid, + #endif + (VOID **) &Fv + ); + + Status = Fv->ReadFile ( + Fv, + &BmpImageGuid, + &Buffer, + &VbtBufferSize, + &FileType, + &FileAttributes, + &AuthenticationStatus + ); + + if (!EFI_ERROR (Status)) { + *VbtAddress = (EFI_PHYSICAL_ADDRESS)Buffer; + *VbtSize = (UINT32)VbtBufferSize; + Status = EFI_SUCCESS; + break; + } + } + } else { + Status = EFI_NOT_FOUND; + } + + if (FvHandles != NULL) { + pBS->FreePool (FvHandles); + FvHandles = NULL; + } + + return Status; +} + +EFI_STATUS +GetPlatformDockStatus ( + OUT DOCK_STATUS CurrentDockStatus +) +{ + + return EFI_UNSUPPORTED; +} + +VOID IntelGopVbtUpdateNotify ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS VbtAddress; + UINT32 VbtSize; + + Status = pBS->LocateProtocol ( + &gDxePlatformSaPolicyGuid, + NULL, + (VOID **) &gDxePlatformSaPolicy + ); + if (!EFI_ERROR (Status)) { + + Status = GetVbtData(&VbtAddress, &VbtSize); + if (!EFI_ERROR (Status)) { + gDxePlatformSaPolicy->IgdConfig->VbtAddress = VbtAddress; + gDxePlatformSaPolicy->IgdConfig->Size = VbtSize; + } + } + // Kill event + pBS->CloseEvent(Event); + +} + +EFI_STATUS +EFIAPI +IntelSaGopPolicyEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +/*++ + +Routine Description: + + Entry point for the Platform GOP Policy Driver. + +Arguments: + + ImageHandle Image handle of this driver. + SystemTable Global system service table. + +Returns: + + EFI_SUCCESS Initialization complete. + EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. + +--*/ +{ + EFI_STATUS Status; + NB_PLATFORM_DATA NBPlatformData = {0}; + UINTN VariableSize; + SETUP_DATA *SetupData = NULL; + EFI_EVENT DxePlatformSaPolicyEvent; + VOID *DxePlatformSaPolicyReg; + UINT32 Attributes = 0; // [ EIP167027 ] + + + InitAmiLib (ImageHandle, SystemTable); + + // Read the NB Platform Data + VariableSize = sizeof (NB_PLATFORM_DATA); + //Status = pRS->GetVariable ( // [ EIP167027 ] + // L"NBPlatformData", + // &gSetupGuid, + // NULL, + // &VariableSize, + // &NBPlatformData + // ); + Status = pRS->GetVariable ( + L"NBPlatformData", + &gSetupGuid, + &Attributes, + &VariableSize, + &NBPlatformData + ); + if (EFI_ERROR(Status)) + Attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS; + + VariableSize = sizeof(SETUP_DATA); + Status = GetEfiVariable( + L"Setup", + &gSetupGuid, + NULL, + &VariableSize, + &SetupData + ); + +#if (defined(CSM_SUPPORT) && (CSM_SUPPORT != 0)) +#if defined(CsmOptOut_SUPPORT) && (CsmOptOut_SUPPORT == 1) + + Status = pBS->LocateProtocol( &gAmiLoadCsmGuid, \ + NULL, \ + &gInterface ); + if(!EFI_ERROR(Status)) + { + if ((SetupData->VideoOpRom == 0) || (SetupData->VideoOpRom == 2)) return EFI_UNSUPPORTED; + } + +#else + +#if defined(CORE_COMBINED_VERSION) && (CORE_COMBINED_VERSION <= 0x4028b) +{ + if ((SetupData->VideoOpRom) == 1) return EFI_UNSUPPORTED; +} +#else + return EFI_UNSUPPORTED; +#endif // CORE_COMBINED_VERSION +#endif // CsmOptOut_SUPPORT +#endif // CSM_SUPPORT + + pBS->SetMem (&mPlatformGOPPolicy, sizeof (PLATFORM_GOP_POLICY_PROTOCOL), 0); + + mPlatformGOPPolicy.Revision = PLATFORM_GOP_POLICY_PROTOCOL_REVISION_02; + mPlatformGOPPolicy.GetPlatformLidStatus = GetPlatformLidStatus; + mPlatformGOPPolicy.GetVbtData = GetVbtData; + mPlatformGOPPolicy.GetPlatformDockStatus = GetPlatformDockStatus; + + // + // Install protocol to allow access to this Policy. + // + Status = pBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gPlatformGOPPolicyGuid, + &mPlatformGOPPolicy, + NULL + ); + + //NbSetupdata Pass to SaGlobalNvsArea. + Status = pBS->CreateEvent ( + EFI_EVENT_NOTIFY_SIGNAL, + TPL_CALLBACK, + IntelGopVbtUpdateNotify, + NULL, + &DxePlatformSaPolicyEvent + ); + + if (!EFI_ERROR (Status)) { + Status = pBS->RegisterProtocolNotify ( + &gDxePlatformSaPolicyGuid, + DxePlatformSaPolicyEvent, + &DxePlatformSaPolicyReg + ); + } + + + NBPlatformData.IGFXGopAvailable = 1; + + // Save SETUP variables. + //Status = pRS->SetVariable ( // [ EIP167027 ] + // L"NBPlatformData", + // &gSetupGuid, + // EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, + // sizeof (NB_PLATFORM_DATA), + // &NBPlatformData + // ); + Status = pRS->SetVariable ( + L"NBPlatformData", + &gSetupGuid, + Attributes, + sizeof (NB_PLATFORM_DATA), + &NBPlatformData + ); + + ASSERT_EFI_ERROR (Status); + + return Status; +} +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.c b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.c new file mode 100644 index 0000000..0253aeb --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.c @@ -0,0 +1,871 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelSaGopSetup/IntelSaGopSetup.c 6 7/11/14 3:48a Dennisliu $ +// +// $Revision: 6 $ +// +// $Date: 7/11/14 3:48a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelSaGopSetup/IntelSaGopSetup.c $ +// +// 6 7/11/14 3:48a Dennisliu +// [TAG] None +// [Category] Improvement +// [Description] Problem: #if directive for TSE_BUILD=0x1208 (EIP176870) +// [Files] +// Board\NB\NBSetup\NBSetup.c +// Chipset\NB\GOP\IntelSaGopSetup\IntelSaGopSetup.c +// +// 5 5/13/14 10:44p Dennisliu +// [TAG] EIP167027 +// [Category] Improvement +// [Description] [SharkBay Aptio4]Variable's attribute needs to be +// reviewed by SA component driver +// [Files] NBDXEBoard.c; IntelSaGopSetup.c; IntelSaGopPolicy.c; +// NBDxe.c; NbPciCSP.c; PciHostBridge.c; +// +// 4 4/23/13 8:02a Ireneyang +// [TAG] None +// [Severity] Improvement +// [Description] Support for BIST (Built-In Self Test) Protocol. +// [Files] IntelSaGopSetup.c; IntelSaGopSetup.h; +// IntelSaGopSetup.sd; +// IntelSaGopSetup.sd; IntelSaGopSetup.sdl; +// IntelSaGopSetup.uni; IntelSaGopDriver.h; +// +// 3 4/08/13 6:31a Ireneyang +// +// 2 8/14/12 5:47a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Implemented BIOS Integration Guide Rev 1.0 to Intel SA +// GOP driver. +// [Files] IntelSaGopDriver.cif, IntelSaGopDriver.mak, +// IntelSaGopDriver.sdl, IntelSaGopPolicy.c, +// IntelSaGopSetup.c, +// IntelSaGopSetup.h, IntelSaGopSetup.mak, +// IntelSaGopSetup.sd, +// IntelSaGopSetup.sdl, IntelSaGopSetup.uni, +// IntelSaGopSwitch.c, IntelSaGopDriver.h, NBPlatformData.h +// +// 1 3/08/12 10:55p Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Create Haswell Intel SA GOP Driver module part. +// Notice : IntelGopDriver.efi and vbt.bin is dummy files. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: IntelSaGopSetup.c +// +// Description: GOP Setup Rountines +// +//<AMI_FHDR_END> +//************************************************************************* + +//---------------------------------------------------------------------------- +// Include(s) +//---------------------------------------------------------------------------- +#include <Token.h> +#include <Setup.h> +#include <SetupStrTokens.h> +#include <AmiDxeLib.h> +#include <AmiCspLib.h> +#include <Protocol\ComponentName2.h> +#include <Protocol\GraphicsOutput.h> +#include <Protocol\IntelSaGopDriver.h> +#include "IntelSaGopSetup.h" + +static EFI_GUID gEfiVariableGuid = EFI_GLOBAL_VARIABLE; +static EFI_GUID gSetupGuid = SETUP_GUID; +static EFI_GUID gGopDisplayBrightnessProtocolGuid = GOP_DISPLAY_BRIGHTNESS_PROTOCOL_GUID; +static EFI_GUID gGopDisplayBistProtocolGuid = GOP_DISPLAY_BIST_PROTOCOL_GUID; + +EFI_STATUS AmiGopDeviceCheck ( + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE DriverBindingHandle, + IN EFI_PCI_IO_PROTOCOL *PciIo +); + +EFI_STATUS GetIntelSaGopSetupDriverBindingHandle ( + IN EFI_HANDLE ControllerHandle, + OUT EFI_HANDLE *DriverBindingHandle +); + +EFI_STATUS GetChildDeviceHandlesControledByDriver ( + IN EFI_HANDLE DriverBindingHandle, + IN EFI_HANDLE ControllerHandle, + OUT UINTN *ChildControllerHandleCount, + OUT EFI_HANDLE **ChildControllerHandleBuffer +); + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Name: GetIntelSaGopSetupDriverBindingHandle +// +// Description: None. +// +// Input: None. +// +// Output: None. +// +// Notes: None. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +GetIntelSaGopSetupDriverBindingHandle ( + IN EFI_HANDLE ControllerHandle, + OUT EFI_HANDLE *DriverBindingHandle ) +{ + EFI_STATUS Status; + UINTN HandleCount; + EFI_HANDLE *HandleBuffer; + UINTN HandleIndex; + EFI_GUID **ProtocolGuidArray; + UINTN ArrayCount; + UINTN ProtocolIndex; + EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfo; + UINTN OpenInfoCount; + UINTN OpenInfoIndex; + UINTN Index; + + Status = pBS->LocateHandleBuffer( + AllHandles, + NULL, + NULL, + &HandleCount, + &HandleBuffer); + if (EFI_ERROR(Status)) return EFI_NOT_FOUND; + + for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) { + ProtocolGuidArray = NULL; + Status = pBS->ProtocolsPerHandle( + HandleBuffer[HandleIndex], + &ProtocolGuidArray, + &ArrayCount); + if (EFI_ERROR(Status)) continue; + + for (ProtocolIndex = 0; ProtocolIndex < ArrayCount; ProtocolIndex++) { + Status = pBS->OpenProtocolInformation( + HandleBuffer[HandleIndex], + ProtocolGuidArray[ProtocolIndex], + &OpenInfo, + &OpenInfoCount); + if (EFI_ERROR(Status)) continue; + + for (OpenInfoIndex = 0; OpenInfoIndex < OpenInfoCount; OpenInfoIndex++) { + if (OpenInfo[OpenInfoIndex].ControllerHandle == ControllerHandle) { + if ((OpenInfo[OpenInfoIndex].Attributes & EFI_OPEN_PROTOCOL_BY_DRIVER) == EFI_OPEN_PROTOCOL_BY_DRIVER) { + for(Index = 0; Index < HandleCount; Index++) { + if(HandleBuffer[Index] == OpenInfo[OpenInfoIndex].AgentHandle) { + *DriverBindingHandle=HandleBuffer[Index]; + pBS->FreePool(OpenInfo); + pBS->FreePool(ProtocolGuidArray); + pBS->FreePool(HandleBuffer); + return EFI_SUCCESS; + } + } + } + } + } + if (OpenInfo != NULL) pBS->FreePool(OpenInfo); + } + if (ProtocolGuidArray != NULL) pBS->FreePool(ProtocolGuidArray); + } + if (HandleBuffer != NULL) pBS->FreePool(HandleBuffer); + return EFI_NOT_FOUND; +} + +// <AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Name: GetChildDeviceHandlesControledByDriver +// +// Description: +// Get all child device handles which are being opened by a specific driver. +// The rountine will allocate pool buffer for the found child device handles, +// and it is the caller's responsibility to safe free the buffer. +// +// Input: +// IN EFI_HANDLE DriverBindingHandle - the handle of a driver which +// contains the binding protocol +// IN EFI_HANDLE ControllerHandle - the device controller handle be opened +// by its child device +// OUT UINTN ChildControllerHandleCount - the number of available +// device handles returned in +// ControllerHandleBuffer +// OUT EFI_HANDLE ChildControllerHandleBuffer - a pointer to the buffer to +// return the array of child +// device handles +// +// Output: +// EFI_STATUS +// If returned status is not succeful or find no available device, +// the *ChildControllerHandleBuffer will be NULL +// +// Modified: +// +// Referrals: +// +// Notes: +// +//---------------------------------------------------------------------------- +// <AMI_PHDR_END> + +EFI_STATUS +GetChildDeviceHandlesControledByDriver ( + IN EFI_HANDLE DriverBindingHandle, + IN EFI_HANDLE ControllerHandle, + OUT UINTN *ChildControllerHandleCount, + OUT EFI_HANDLE **ChildControllerHandleBuffer ) +{ + UINTN HandleCount; + EFI_HANDLE *HandleBuffer; + BOOLEAN *HandleBufferMap; + EFI_STATUS Status; + UINTN HandleIndex; + UINTN AvailableIndex; + EFI_GUID **ProtocolGuidArray; + UINTN ArrayCount; + UINTN ProtocolIndex; + EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfo; + UINTN OpenInfoCount; + UINTN OpenInfoIndex; + + *ChildControllerHandleCount = 0; + *ChildControllerHandleBuffer = NULL; + HandleCount = 0; + HandleBuffer = NULL; + + if ((DriverBindingHandle == NULL) || (ControllerHandle == NULL)) { + Status = EFI_INVALID_PARAMETER; + goto Error; + } + + // + // Retrieve the list of all handles from the handle database + // + Status = pBS->LocateHandleBuffer ( + AllHandles, + NULL, + NULL, + &HandleCount, + &HandleBuffer); + if (EFI_ERROR(Status)) goto Error; + + // + // Create a map for HandleBuffer. If a handle in HandleBuffer is the wanted device handle, its map item is true. + // + HandleBufferMap = MallocZ (sizeof (BOOLEAN) * HandleCount); + for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) { + HandleBufferMap[HandleIndex] = FALSE; + } + + // + // Retrieve the list of all the protocols on each handle + // + Status = pBS->ProtocolsPerHandle ( + ControllerHandle, + &ProtocolGuidArray, + &ArrayCount); + if (!EFI_ERROR (Status)) { + for (ProtocolIndex = 0; ProtocolIndex < ArrayCount; ProtocolIndex++) { + // + // Retrieve the list of agents that have opened each protocol + // + Status = pBS->OpenProtocolInformation ( + ControllerHandle, + ProtocolGuidArray[ProtocolIndex], + &OpenInfo, + &OpenInfoCount); + if (!EFI_ERROR (Status)) { + for (OpenInfoIndex = 0; OpenInfoIndex < OpenInfoCount; OpenInfoIndex++) { + if (OpenInfo[OpenInfoIndex].AgentHandle == DriverBindingHandle) { + if ((OpenInfo[OpenInfoIndex].Attributes & EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) == EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) { + // + // OpenInfo[OpenInfoIndex].ControllerHandle is the wanted child device handle, find it in the handlebuffer + // A bus driver maybe open a Controller with BY_CHILD_CONTROLLER attribute for different protocol many times, + // + for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) { + if (OpenInfo[OpenInfoIndex].ControllerHandle == HandleBuffer[HandleIndex]) { + HandleBufferMap[HandleIndex] = TRUE; + } + } + } + } + } + pBS->FreePool (OpenInfo); + } + } + pBS->FreePool (ProtocolGuidArray); + } + + // + // count how many device handles are found + // + for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) { + if (HandleBufferMap[HandleIndex]) { + (*ChildControllerHandleCount)++; + } + } + + if (*ChildControllerHandleCount > 0) { + // + // Copy the found device handle to returned buffer + // + *ChildControllerHandleBuffer = MallocZ (sizeof (EFI_HANDLE) * (*ChildControllerHandleCount)); + for (HandleIndex = 0, AvailableIndex = 0; HandleIndex < HandleCount; HandleIndex++) { + if (HandleBufferMap[HandleIndex]) { + (*ChildControllerHandleBuffer)[AvailableIndex] = HandleBuffer[HandleIndex]; + AvailableIndex++; + } + } + } + + if (HandleBuffer != NULL) pBS->FreePool (HandleBuffer); + return EFI_SUCCESS; + +Error: + if (HandleBuffer != NULL) pBS->FreePool (HandleBuffer); + return Status; +} + +//<AMI_PHDR_START> +//--------------------------------------------------------------------------- +// Name: IntelSaGopSetupInfo +// +// Description: This function will display Brightness Option in setup menu, +// if the system GOP supports it. +// +// Input: EFI_HII_HANDLE HiiHandle +// +// Output: VOID +//--------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +IntelSaGopSetupInfo( + EFI_HII_HANDLE HiiHandle, + UINT16 Class +) +{ + EFI_STATUS Status; + UINTN SetupSize; + NB_GOP_PLATFORM_DATA NBGopPlatformData = {0}; + + UINTN ControllerHandleIndex; + EFI_HANDLE ControllerHandle; + UINTN ControllerHandleCount = 0; + EFI_HANDLE *ControllerHandleBuffer = NULL; + + EFI_HANDLE DriverBindingHandle; + + EFI_PCI_IO_PROTOCOL *PciIo; + + UINTN ChildHandleCount = 0; + EFI_HANDLE *ChildHandleBuffer = NULL; + EFI_HANDLE ChildHandle; + UINTN ChildHandleIndex = 0; + UINT8 GopBistEnable; + UINT32 CurrentBrightness = 255; + GOP_DISPLAY_BRIGHTNESS_PROTOCOL *GopDisplayBrightnessProtocol = NULL; + GOP_DISPLAY_BIST_PROTOCOL *GopDisplayBistProtocol = NULL; + SETUP_DATA SetupData; + + SetupSize = sizeof (SETUP_DATA); + Status = pRS->GetVariable ( + L"Setup", + &gSetupGuid, + NULL, + &SetupSize, + &SetupData + ); + + GopBistEnable = (Status == EFI_SUCCESS) ? SetupData.EnableBIST : FALSE; + + // + // Get all drivers handles which has PCI IO Protocol + // + Status = pBS->LocateHandleBuffer( + ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &ControllerHandleCount, + &ControllerHandleBuffer); + if (EFI_ERROR(Status)) return; + + for (ControllerHandleIndex = 0; ControllerHandleIndex < ControllerHandleCount; ControllerHandleIndex++) { + + ControllerHandle = ControllerHandleBuffer[ControllerHandleIndex]; + Status = pBS->HandleProtocol (ControllerHandle, &gEfiPciIoProtocolGuid, &PciIo); + if (EFI_ERROR(Status)) continue; + + // + // Get Driver Binding Protocol for this VGA + // + Status = GetIntelSaGopSetupDriverBindingHandle (ControllerHandle, &DriverBindingHandle); + if (EFI_ERROR(Status)) continue; + + Status = AmiGopDeviceCheck (ControllerHandle, DriverBindingHandle, PciIo); + if (EFI_ERROR(Status)) continue; + + Status = GetChildDeviceHandlesControledByDriver (DriverBindingHandle, ControllerHandle, &ChildHandleCount, &ChildHandleBuffer); + + if (!EFI_ERROR(Status)) { + for (ChildHandleIndex = 0; ChildHandleIndex < ChildHandleCount; ChildHandleIndex++) { + ChildHandle = ChildHandleBuffer[ChildHandleIndex]; + + // + // Check if this device have Graphic Output Portocol. + // If it does, the system would support Brightness option in setup Menu. + // + Status = pBS->OpenProtocol ( + ChildHandle, + &gEfiGraphicsOutputProtocolGuid, + NULL, + NULL, + NULL, + EFI_OPEN_PROTOCOL_TEST_PROTOCOL); + + if (!EFI_ERROR(Status)) { + + Status = pBS->OpenProtocol ( + ChildHandle, + &gGopDisplayBrightnessProtocolGuid, + (VOID**)&GopDisplayBrightnessProtocol, + NULL, + NULL, + EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL); + + if (!EFI_ERROR(Status)) { + + if(GopDisplayBrightnessProtocol->Revision >= GOP_DISPLAY_BRIGHTNESS_PROTOCOL_REVISION_01) { + + NBGopPlatformData.BrightnessAvailable = 1; + Status = GopDisplayBrightnessProtocol->GetCurrentBrightnessLevel(GopDisplayBrightnessProtocol, &CurrentBrightness); + + if (EFI_ERROR(Status)) CurrentBrightness = 255; + }//if(GopDisplayBrightnessProtocol->Revision >= GOP_DISPLAY_BRIGHTNESS_PROTOCOL_REVISION_01) + } + + Status = pBS->OpenProtocol ( + ChildHandle, + &gGopDisplayBistProtocolGuid, + (VOID**)&GopDisplayBistProtocol, + NULL, + NULL, + EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL); + + if (!EFI_ERROR(Status)) { + + if(GopDisplayBistProtocol->Revision >= GOP_DISPLAY_BIST_PROTOCOL_REVISION_01) { + + NBGopPlatformData.GopBistAvailable = 1; + + if (GopBistEnable == 1) + Status = GopDisplayBistProtocol->EnableBist(GopDisplayBistProtocol); + else + Status = GopDisplayBistProtocol->DisableBist(GopDisplayBistProtocol); + }//if(GopDisplayBistProtocol->Revision >= GOP_DISPLAY_BIST_PROTOCOL_REVISION_01) + } + + } + + //Status = pRS->SetVariable ( // [ EIP167027 ] + // L"NBGopPlatformData", + // &gSetupGuid, + // EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, + // sizeof (NB_GOP_PLATFORM_DATA), + // &NBGopPlatformData + // ); + Status = pRS->SetVariable ( + L"NBGopPlatformData", + &gSetupGuid, + EFI_VARIABLE_BOOTSERVICE_ACCESS, + sizeof (NB_GOP_PLATFORM_DATA), + &NBGopPlatformData + ); + + }//for (ChildHandleIndex = 0; ChildHandleIndex < ChildHandleCount; ChildHandleIndex++) + }//if (!EFI_ERROR(Status)) + }//for (ControllerHandleIndex = 0; ControllerHandleIndex < ControllerHandleCount; ControllerHandleIndex++) + return; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Name: IntelGopSwitchFunction +// +// Description: For overriding ELink, AmiDefaultGopSwitchFunction. +// If it's Intel Device, the system should do this function, IntelGopSwitchFunction. +// +// Input: None. +// +// Output: None. +// +// Notes: None. +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +IntelGopSwitchFunction ( + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE DriverBindingHandle, + IN SETUP_DATA *SetupData, + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINTN ChildHandleCount = 0; + EFI_HANDLE *ChildHandleBuffer = NULL; + UINTN ChildHandleIndex = 0; + EFI_HANDLE OutPutDevHandle; + + EFI_DEVICE_PATH_PROTOCOL *GopDevicePath = NULL; + EFI_DEVICE_PATH_PROTOCOL *GopAcpiAdrDPNode = NULL; + ACPI_ADR_DEVICE_PATH *AcpiDPNode; + + UINTN SetupSize; + NB_GOP_PLATFORM_DATA NBGopPlatformData = {0}; + GOP_DISPLAY_BRIGHTNESS_PROTOCOL *GopDisplayBrightnessProtocol = NULL; + GOP_DISPLAY_BIST_PROTOCOL *GopDisplayBistProtocol = NULL; + UINT32 MaxBrightness = 255; + UINT32 CurrentBrightness = 255; + + EFI_PCI_IO_PROTOCOL *PciIo; + PCI_DEV_INFO *Dev; + + Status = pBS->HandleProtocol (ControllerHandle, &gEfiPciIoProtocolGuid, &PciIo); + if (EFI_ERROR(Status)) return Status; + + Dev = (PCI_DEV_INFO*)PciIo; + + // + // If it's not Intel VGA, don't do this part. + // + if (Dev->DevVenId.VenId != 0x8086) { + return EFI_UNSUPPORTED; + } + + SetupSize = sizeof (NB_GOP_PLATFORM_DATA); + + AcpiDPNode = (ACPI_ADR_DEVICE_PATH*)GopAcpiAdrDPNode = DPGetLastNode(DevicePath); + Status = pBS->ConnectController( ControllerHandle, NULL, GopAcpiAdrDPNode, TRUE ); + +// Status = GetChildDeviceHandlesControledByDriver (DriverBindingHandle, ControllerHandle, &ChildHandleCount, &ChildHandleBuffer); + + if (!EFI_ERROR(Status)) { + // + // Find out Current Installed GOP Device + // +// for (ChildHandleIndex = 0; ChildHandleIndex < ChildHandleCount; ChildHandleIndex++) { +// if (SetupData->GopOutputSelect == ChildHandleIndex) { +// +// Status = pBS->OpenProtocol ( +// ChildHandleBuffer[ChildHandleIndex], +// &gEfiDevicePathProtocolGuid, +// (VOID**)&GopDevicePath, +// NULL, +// NULL, +// EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL); +// if (EFI_ERROR(Status)) break; +// +// // +// // If Current installed GOP is Intels', conncect it. +// // +// if (!EFI_ERROR(Status)) { +// AcpiDPNode = (ACPI_ADR_DEVICE_PATH*)GopAcpiAdrDPNode = DPGetLastNode(GopDevicePath); +// Status = pBS->ConnectController( ControllerHandle, NULL, GopAcpiAdrDPNode, TRUE ); +// } +// +// // +// // Check if this device have Graphic Output Portocol. +// // If it does, the system would support Brightness option in setup Menu. +// // +// Status = pBS->OpenProtocol ( +// ChildHandleBuffer[ChildHandleIndex], +// &gEfiGraphicsOutputProtocolGuid, +// NULL, +// NULL, +// NULL, +// EFI_OPEN_PROTOCOL_TEST_PROTOCOL); + Status = pBS->LocateDevicePath(&gGopDisplayBrightnessProtocolGuid, &DevicePath, &OutPutDevHandle); + + if (!EFI_ERROR(Status)) { + + Status = pBS->OpenProtocol ( + OutPutDevHandle, + &gGopDisplayBrightnessProtocolGuid, + (VOID**)&GopDisplayBrightnessProtocol, + NULL, + NULL, + EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL); + if (!EFI_ERROR(Status)) { + if(GopDisplayBrightnessProtocol->Revision >= GOP_DISPLAY_BRIGHTNESS_PROTOCOL_REVISION_01) { + NBGopPlatformData.BrightnessAvailable = 1; + Status = GopDisplayBrightnessProtocol->GetMaxBrightnessLevel(GopDisplayBrightnessProtocol, &MaxBrightness); + if (!EFI_ERROR(Status)) { + if (SetupData->GopBrightness > MaxBrightness) { + SetupData->GopBrightness = MaxBrightness; +#if defined(EFI_SPECIFICATION_VERSION) && EFI_SPECIFICATION_VERSION > 0x20000 + Status = HiiLibSetBrowserData (SetupSize, SetupData, &gSetupGuid, L"Setup"); +#endif + } + Status = GopDisplayBrightnessProtocol->GetCurrentBrightnessLevel(GopDisplayBrightnessProtocol, &CurrentBrightness); + if (!EFI_ERROR(Status)) { + if(CurrentBrightness != SetupData->GopBrightness) + Status = GopDisplayBrightnessProtocol->SetBrightnessLevel(GopDisplayBrightnessProtocol, SetupData->GopBrightness); + } + } + } // GOP_DISPLAY_BRIGHTNESS_PROTOCOL_REVISION_01 + } //OpenProtocol gGopDisplayBrightnessProtocol + + Status = pBS->OpenProtocol ( + OutPutDevHandle, + &gGopDisplayBistProtocolGuid, + (VOID**)&GopDisplayBistProtocol, + NULL, + NULL, + EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL); + + if (!EFI_ERROR(Status)) { + + if(GopDisplayBistProtocol->Revision >= GOP_DISPLAY_BIST_PROTOCOL_REVISION_01) { + + NBGopPlatformData.GopBistAvailable = 1; + + if (SetupData->EnableBIST == 1) + Status = GopDisplayBistProtocol->EnableBist(GopDisplayBistProtocol); + else + Status = GopDisplayBistProtocol->DisableBist(GopDisplayBistProtocol); + }//if(GopDisplayBistProtocol->Revision >= GOP_DISPLAY_BIST_PROTOCOL_REVISION_01) + } //OpenProtocol gGopDisplayBistProtocolGuid + + } +// }// if (SetupData->GopOutputSelect == ChildHandleIndex) +// }// for (ChildHandleIndex = 0; ChildHandleIndex < ChildHandleCount; ChildHandleIndex++) + } + + Status = HiiLibSetBrowserData ( + sizeof (NB_GOP_PLATFORM_DATA), + &NBGopPlatformData, + &gSetupGuid, + L"NBGopPlatformData" + ); + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Name: IntelGopMultifunctionCallback +// +// Description: If the device support Multifunction, it supports its key +// callbak funtion. +// +// Input: None. +// +// Output: None. +// +// Notes: None. +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS IntelGopMultifunctionCallback ( + IN EFI_HII_HANDLE HiiHandle, + IN UINT16 Class, + IN UINT16 SubClass, + IN UINT16 Key ) +{ + + EFI_STATUS Status = EFI_SUCCESS; + SETUP_DATA *SetupData = NULL; + CALLBACK_PARAMETERS *CallbackParameters = NULL; + UINTN SetupSize; + EFI_STATUS NBGopPlatformDataStatus = EFI_UNSUPPORTED; + NB_GOP_PLATFORM_DATA NBGopPlatformData = {0}; + UINTN ControllerHandleIndex; + EFI_HANDLE ControllerHandle; + UINTN ControllerHandleCount = 0; + EFI_HANDLE *ControllerHandleBuffer = NULL; + + EFI_HANDLE DriverBindingHandle; + + EFI_PCI_IO_PROTOCOL *PciIo; + + UINTN ChildHandleCount = 0; + EFI_HANDLE *ChildHandleBuffer = NULL; + EFI_HANDLE ChildHandle; + UINTN ChildHandleIndex = 0; + + UINT32 CurrentBrightness = 255; + GOP_DISPLAY_BRIGHTNESS_PROTOCOL *GopDisplayBrightnessProtocol = NULL; + GOP_DISPLAY_BIST_PROTOCOL *GopDisplayBistProtocol = NULL; + + UINT32 MaxBrightness = 255; + + SetupSize = sizeof (SETUP_DATA); + + CallbackParameters = GetCallbackParameters(); + +#if ((TSE_BUILD >= 0x1224) && (EFI_SPECIFICATION_VERSION >= 0x2000A)) + if (CallbackParameters->Action != EFI_BROWSER_ACTION_CHANGED) return Status; +#elif ((TSE_BUILD > 0x1208) && (EFI_SPECIFICATION_VERSION >= 0x2000A)) + if (CallbackParameters->Action != EFI_BROWSER_ACTION_CHANGING) return Status; +#endif + + Status = pBS->AllocatePool (EfiBootServicesData, SetupSize, &SetupData); + if(EFI_ERROR(Status)) return Status; + +#if defined(EFI_SPECIFICATION_VERSION) && EFI_SPECIFICATION_VERSION > 0x20000 + Status = HiiLibGetBrowserData (&SetupSize, SetupData, &gSetupGuid, L"Setup"); + if(EFI_ERROR(Status)) return Status; +#else + SetupData = (SETUP_DATA*)CallbackParameters->Data->NvRamMap; +#endif + +#if defined(EFI_SPECIFICATION_VERSION) && EFI_SPECIFICATION_VERSION > 0x20000 + SetupSize = sizeof (NB_GOP_PLATFORM_DATA); + NBGopPlatformDataStatus = HiiLibGetBrowserData (&SetupSize, &NBGopPlatformData, &gSetupGuid, L"NBGopPlatformData"); +#endif + // + // Get all drivers handles which has PCI IO Protocol + // + Status = pBS->LocateHandleBuffer( + ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &ControllerHandleCount, + &ControllerHandleBuffer); + if (EFI_ERROR(Status)) return Status; + + for (ControllerHandleIndex = 0; ControllerHandleIndex < ControllerHandleCount; ControllerHandleIndex++) { + + ControllerHandle = ControllerHandleBuffer[ControllerHandleIndex]; + Status = pBS->HandleProtocol (ControllerHandle, &gEfiPciIoProtocolGuid, &PciIo); + if (EFI_ERROR(Status)) continue; + + Status = GetIntelSaGopSetupDriverBindingHandle (ControllerHandle, &DriverBindingHandle); + if (EFI_ERROR(Status)) continue; + + Status = AmiGopDeviceCheck (ControllerHandle, DriverBindingHandle, PciIo); + if (EFI_ERROR(Status)) continue; + + Status = GetChildDeviceHandlesControledByDriver (DriverBindingHandle, ControllerHandle, &ChildHandleCount, &ChildHandleBuffer); + + if (!EFI_ERROR(Status)) { + for (ChildHandleIndex = 0; ChildHandleIndex < ChildHandleCount; ChildHandleIndex++) { + ChildHandle = ChildHandleBuffer[ChildHandleIndex]; + + // + // Check if this device have Graphic Output Portocol. + // If it does, the system would support Brightness option in setup Menu. + // + Status = pBS->OpenProtocol ( + ChildHandle, + &gEfiGraphicsOutputProtocolGuid, + NULL, + NULL, + NULL, + EFI_OPEN_PROTOCOL_TEST_PROTOCOL); + + if (!EFI_ERROR(Status)) { + + if (Key == AGP_BRIGHTNESS_KEY) { + Status = pBS->OpenProtocol ( + ChildHandle, + &gGopDisplayBrightnessProtocolGuid, + (VOID**)&GopDisplayBrightnessProtocol, + NULL, + NULL, + EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL); + if (!EFI_ERROR(Status)) { + if(GopDisplayBrightnessProtocol->Revision >= GOP_DISPLAY_BRIGHTNESS_PROTOCOL_REVISION_01) { + NBGopPlatformData.BrightnessAvailable = 1; + Status = GopDisplayBrightnessProtocol->GetMaxBrightnessLevel(GopDisplayBrightnessProtocol, &MaxBrightness); + if (!EFI_ERROR(Status)) { + if (SetupData->GopBrightness > MaxBrightness) { + SetupData->GopBrightness = MaxBrightness; +#if defined(EFI_SPECIFICATION_VERSION) && EFI_SPECIFICATION_VERSION > 0x20000 + SetupSize = sizeof (SETUP_DATA); + Status = HiiLibSetBrowserData (SetupSize, SetupData, &gSetupGuid, L"Setup"); +#endif + } + Status = GopDisplayBrightnessProtocol->GetCurrentBrightnessLevel(GopDisplayBrightnessProtocol, &CurrentBrightness); + if (!EFI_ERROR(Status)) { + if(CurrentBrightness != SetupData->GopBrightness) + Status = GopDisplayBrightnessProtocol->SetBrightnessLevel(GopDisplayBrightnessProtocol, SetupData->GopBrightness); + } + } + } // GOP_DISPLAY_BRIGHTNESS_PROTOCOL_REVISION_01 + } //OpenProtocol GopDisplayBrightnessProtocol + } // AGP_BRIGHTNESS_KEY + + if (Key == AGP_BIST_KEY) { + Status = pBS->OpenProtocol ( + ChildHandle, + &gGopDisplayBistProtocolGuid, + (VOID**)&GopDisplayBistProtocol, + NULL, + NULL, + EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL); + + if (!EFI_ERROR(Status)) { + + if(GopDisplayBistProtocol->Revision >= GOP_DISPLAY_BIST_PROTOCOL_REVISION_01) { + + NBGopPlatformData.GopBistAvailable = 1; + + if (SetupData->EnableBIST == 1) + Status = GopDisplayBistProtocol->EnableBist(GopDisplayBistProtocol); + else + Status = GopDisplayBistProtocol->DisableBist(GopDisplayBistProtocol); + }//if(GopDisplayBistProtocol->Revision >= GOP_DISPLAY_BIST_PROTOCOL_REVISION_01) + } //OpenProtocol gGopDisplayBistProtocolGuid + } // AGP_BIST_KEY + }//OpenProtocol gEfiGraphicsOutputProtocolGuid + + }//for (ChildHandleIndex = 0; ChildHandleIndex < ChildHandleCount; ChildHandleIndex++) + }//if (!EFI_ERROR(Status)) + }//for (ControllerHandleIndex = 0; ControllerHandleIndex < ControllerHandleCount; ControllerHandleIndex++) + +#if defined(EFI_SPECIFICATION_VERSION) && EFI_SPECIFICATION_VERSION > 0x20000 + if(!EFI_ERROR(NBGopPlatformDataStatus)) { + HiiLibSetBrowserData ( + sizeof (NB_GOP_PLATFORM_DATA), + &NBGopPlatformData, + &gSetupGuid, + L"NBGopPlatformData" + ); + } +#endif + return Status; +} +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.cif b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.cif new file mode 100644 index 0000000..429afd0 --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.cif @@ -0,0 +1,13 @@ +<component> + name = "IntelSaGopSetup" + category = ModulePart + LocalRoot = "Chipset\NB\GOP\IntelSaGopSetup" + RefName = "IntelSaGopSetup" +[files] +"IntelSaGopSetup.sdl" +"IntelSaGopSetup.mak" +"IntelSaGopSetup.sd" +"IntelSaGopSetup.uni" +"IntelSaGopSetup.c" +"IntelSaGopSetup.h" +<endComponent> diff --git a/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.h b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.h new file mode 100644 index 0000000..c46eef8 --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.h @@ -0,0 +1,96 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelSaGopSetup/IntelSaGopSetup.h 3 4/23/13 8:01a Ireneyang $ +// +// $Revision: 3 $ +// +// $Date: 4/23/13 8:01a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelSaGopSetup/IntelSaGopSetup.h $ +// +// 3 4/23/13 8:01a Ireneyang +// [TAG] None +// [Severity] Improvement +// [Description] Support for BIST (Built-In Self Test) Protocol. +// [Files] IntelSaGopSetup.c; IntelSaGopSetup.h; +// IntelSaGopSetup.sd; +// IntelSaGopSetup.sd; IntelSaGopSetup.sdl; +// IntelSaGopSetup.uni; IntelSaGopDriver.h; +// +// 2 8/14/12 5:47a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Implemented BIOS Integration Guide Rev 1.0 to Intel SA +// GOP driver. +// [Files] IntelSaGopDriver.cif, IntelSaGopDriver.mak, +// IntelSaGopDriver.sdl, IntelSaGopPolicy.c, +// IntelSaGopSetup.c, +// IntelSaGopSetup.h, IntelSaGopSetup.mak, +// IntelSaGopSetup.sd, +// IntelSaGopSetup.sdl, IntelSaGopSetup.uni, +// IntelSaGopSwitch.c, IntelSaGopDriver.h, NBPlatformData.h +// +// 1 3/08/12 10:55p Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Create Haswell Intel SA GOP Driver module part. +// Notice : IntelGopDriver.efi and vbt.bin is dummy files. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: IntelSaGopSetup.h +// +// Description: GOP Specific Setup Variables and Structures +// +//<AMI_FHDR_END> +//************************************************************************* +#ifndef _NB_GOP_PLATFORM_DATA_H_ +#define _NB_GOP_PLATFORM_DATA_H_ +#ifdef __cplusplus +extern "C" { +#endif + + #pragma pack(1) + + typedef struct _NB_GOP_PLATFORM_DATA + { + UINT8 BrightnessAvailable; + UINT8 GopBistAvailable; + }NB_GOP_PLATFORM_DATA; + + #pragma pack() + +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.mak b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.mak new file mode 100644 index 0000000..49cf3fe --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.mak @@ -0,0 +1,49 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: IntelSaGopSetup.mak +# +# Description: This make file builds north bridge Setup +# components and link them to respective binary +# +#<AMI_FHDR_END> +#************************************************************************* +All : IntelSaGopSetup + +IntelSaGopSetup : $(BUILD_DIR)\IntelSaGopSetup.mak + +$(BUILD_DIR)\IntelSaGopSetup.mak : $(IntelSaGopSetup_DIR)\$(@B).cif $(IntelSaGopSetup_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(IntelSaGopSetup_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +SetupBin : $(BUILD_DIR)\IntelSaGopSetup.obj + +$(BUILD_DIR)\IntelSaGopSetup.obj : $(IntelSaGopSetup_DIR)\IntelSaGopSetup.c $(BUILD_DIR)\SetupStrTokens.h + $(CC) $(CFLAGS) /Fo$(BUILD_DIR)\ $(IntelSaGopSetup_DIR)\IntelSaGopSetup.c + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.sd b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.sd new file mode 100644 index 0000000..b62c2af --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.sd @@ -0,0 +1,306 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelSaGopSetup/IntelSaGopSetup.sd 7 8/06/14 10:28p Dennisliu $ +// +// $Revision: 7 $ +// +// $Date: 8/06/14 10:28p $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelSaGopSetup/IntelSaGopSetup.sd $ +// +// 7 8/06/14 10:28p Dennisliu +// [TAG] EIP180652 +// [Category] Improvement +// [Description] IntelSaGopSetup needs updated to support latest +// AmiGopPolicy. +// [Files] Chipset\NB\GOP\IntelSaGopSetup\IntelSaGopSetup.sd +// +// 6 4/11/14 5:26a Dennisliu +// [TAG] None +// [Severity] Improvement +// [Description] Fixed coding error. +// [Files] IntelSaGopSetup.sd; +// +// 4 1/20/14 9:30p Ireneyang +// [TAG] None +// [Severity] Improvement +// [Description] Fix showing messages, +// "invalid token near line xxx (text was '\')", +// when building code. +// [Files] IntelSaGopSetup.sd; +// +// 3 4/23/13 8:03a Ireneyang +// [TAG] None +// [Severity] Improvement +// [Description] Support for BIST (Built-In Self Test) Protocol. +// [Files] IntelSaGopSetup.c; IntelSaGopSetup.h; +// IntelSaGopSetup.sd; +// IntelSaGopSetup.sd; IntelSaGopSetup.sdl; +// IntelSaGopSetup.uni; IntelSaGopDriver.h; +// +// 2 8/14/12 5:47a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Implemented BIOS Integration Guide Rev 1.0 to Intel SA +// GOP driver. +// [Files] IntelSaGopDriver.cif, IntelSaGopDriver.mak, +// IntelSaGopDriver.sdl, IntelSaGopPolicy.c, +// IntelSaGopSetup.c, +// IntelSaGopSetup.h, IntelSaGopSetup.mak, +// IntelSaGopSetup.sd, +// IntelSaGopSetup.sdl, IntelSaGopSetup.uni, +// IntelSaGopSwitch.c, IntelSaGopDriver.h, NBPlatformData.h +// +// 1 3/08/12 10:55p Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Create Haswell Intel SA GOP Driver module part. +// Notice : IntelGopDriver.efi and vbt.bin is dummy files. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: IntelSaGopSetup.sd +// +// Description: GOP setup form +// +//<AMI_FHDR_END> +//************************************************************************* + +#ifdef SETUP_DATA_DEFINITION +//---------------------------------------------------------------------------- +// Put NVRAM data definitions here. +// For example: UINT8 Data1; +// These definitions will be converted by the build process +// to a definitions of SETUP_DATA fields. +//---------------------------------------------------------------------------- + UINT8 GopOutputSelect; + UINT32 GopBrightness; + UINT8 EnableBIST; +#endif //SETUP_DATA_DEFINITION + +#ifdef FORM_SET_TYPEDEF + #include "IntelSaGopSetup.h" + #include "Board\EM\AmiGopPolicy\AmiGopPolicy.h" +#endif + +//Select Top level menu itmem (forset) for you pages +#ifdef ADVANCED_FORM_SET + #ifndef SUPPRESS_GRAYOUT_ENDIF //old Core + #define SUPPRESS_GRAYOUT_ENDIF endif; + #endif + + #ifdef FORM_SET_VARSTORE + varstore AMI_GOP_POLICY_SETUP_DATA, + key = AUTO_ID(AMI_GOP_POLICY_SETUP_DATA_ID), + name = AmiGopPolicySetupData, + guid = AMI_GOP_POLICY_VARIABLE_GUID; + + varstore NB_GOP_PLATFORM_DATA, + key = AUTO_ID(NB_GOP_PLATFORM_DATA_ID), + name = NBGopPlatformData, + guid = SETUP_GUID; + #endif + +#ifdef FORM_SET_GOTO +// Define goto commands for the forms defined in this file +// goto ID_OF_MY_FORM, +// prompt = STRING_TOKEN(STR_FORM_TITLE), +// help = STRING_TOKEN(STR_FORM_HELP); + suppressif ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x0; + goto AGP_FORM_ID, + prompt = STRING_TOKEN(STR_TITLE), + help = STRING_TOKEN(STR_TITLE_HELP); + endif; //suppressif GopDeviceCount < 1 +#endif //FORM_SET_GOTO + +#ifdef FORM_SET_FORM +// Define forms +// form formid = AUTO_ID(ID_OF_MY_FORM), +// title = STRING_TOKEN(STR_FORM_TITLE); +// endform; + form formid = AUTO_ID(AGP_FORM_ID), + title = STRING_TOKEN(STR_TITLE); + + //suppressif ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x0; + SUBTITLE(STRING_TOKEN(STR_GOP_DEVICE_NAME_0)) + SUBTITLE(STRING_TOKEN(STR_GOP_DRIVER_NAME_0)) + + suppressif NOT ideqval AMI_GOP_POLICY_SETUP_DATA.GopOutputCount == 0x1; + oneof varid = SETUP_DATA.GopOutputSelect, + prompt = STRING_TOKEN(STR_GOP_OUTPUT_SELECT), + help = STRING_TOKEN(STR_GOP_OUTPUT_HELP), + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_0), value = 0, flags = DEFAULT | MANUFACTURING | INTERACTIVE, key = AUTO_ID(AGP_KEY_0); + endoneof; + endif; //suppressif GopOutputCount != 1 + + suppressif NOT ideqval AMI_GOP_POLICY_SETUP_DATA.GopOutputCount == 0x2; + oneof varid = SETUP_DATA.GopOutputSelect, + prompt = STRING_TOKEN(STR_GOP_OUTPUT_SELECT), + help = STRING_TOKEN(STR_GOP_OUTPUT_HELP), + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_0), value = 0, flags = DEFAULT | MANUFACTURING | INTERACTIVE, key = AUTO_ID(AGP_KEY_1); + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_1), value = 1, flags = 0; + endoneof; + endif; //suppressif GopOutputCount != 2 + + suppressif NOT ideqval AMI_GOP_POLICY_SETUP_DATA.GopOutputCount == 0x3; + oneof varid = SETUP_DATA.GopOutputSelect, + prompt = STRING_TOKEN(STR_GOP_OUTPUT_SELECT), + help = STRING_TOKEN(STR_GOP_OUTPUT_HELP), + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_0), value = 0, flags = DEFAULT | MANUFACTURING | INTERACTIVE, key = AUTO_ID(AGP_KEY_2); + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_1), value = 1, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_2), value = 2, flags = 0; + endoneof; + endif; //suppressif GopOutputCount != 3 + + suppressif NOT ideqval AMI_GOP_POLICY_SETUP_DATA.GopOutputCount == 0x4; + oneof varid = SETUP_DATA.GopOutputSelect, + prompt = STRING_TOKEN(STR_GOP_OUTPUT_SELECT), + help = STRING_TOKEN(STR_GOP_OUTPUT_HELP), + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_0), value = 0, flags = DEFAULT | MANUFACTURING | INTERACTIVE, key = AUTO_ID(AGP_KEY_3); + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_1), value = 1, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_2), value = 2, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_3), value = 3, flags = 0; + endoneof; + endif; //suppressif GopOutputCount != 4 + + suppressif NOT ideqval AMI_GOP_POLICY_SETUP_DATA.GopOutputCount == 0x5; + oneof varid = SETUP_DATA.GopOutputSelect, + prompt = STRING_TOKEN(STR_GOP_OUTPUT_SELECT), + help = STRING_TOKEN(STR_GOP_OUTPUT_HELP), + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_0), value = 0, flags = DEFAULT | MANUFACTURING | INTERACTIVE, key = AUTO_ID(AGP_KEY_4); + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_1), value = 1, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_2), value = 2, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_3), value = 3, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_4), value = 4, flags = 0; + endoneof; + endif; //suppressif GopOutputCount != 5 + + suppressif NOT ideqval AMI_GOP_POLICY_SETUP_DATA.GopOutputCount == 0x6; + oneof varid = SETUP_DATA.GopOutputSelect, + prompt = STRING_TOKEN(STR_GOP_OUTPUT_SELECT), + help = STRING_TOKEN(STR_GOP_OUTPUT_HELP), + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_0), value = 0, flags = DEFAULT | MANUFACTURING | INTERACTIVE, key = AUTO_ID(AGP_KEY_5); + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_1), value = 1, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_2), value = 2, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_3), value = 3, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_4), value = 4, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_5), value = 5, flags = 0; + endoneof; + endif; //suppressif GopOutputCount != 6 + + suppressif NOT ideqval AMI_GOP_POLICY_SETUP_DATA.GopOutputCount == 0x7; + oneof varid = SETUP_DATA.GopOutputSelect, + prompt = STRING_TOKEN(STR_GOP_OUTPUT_SELECT), + help = STRING_TOKEN(STR_GOP_OUTPUT_HELP), + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_0), value = 0, flags = DEFAULT | MANUFACTURING | INTERACTIVE, key = AUTO_ID(AGP_KEY_6); + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_1), value = 1, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_2), value = 2, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_3), value = 3, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_4), value = 4, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_5), value = 5, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_6), value = 6, flags = 0; + endoneof; + endif; //suppressif GopOutputCount != 7 + + suppressif NOT ideqval AMI_GOP_POLICY_SETUP_DATA.GopOutputCount == 0x8; + oneof varid = SETUP_DATA.GopOutputSelect, + prompt = STRING_TOKEN(STR_GOP_OUTPUT_SELECT), + help = STRING_TOKEN(STR_GOP_OUTPUT_HELP), + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_0), value = 0, flags = DEFAULT | MANUFACTURING | INTERACTIVE, key = AUTO_ID(AGP_KEY_7); + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_1), value = 1, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_2), value = 2, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_3), value = 3, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_4), value = 4, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_5), value = 5, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_6), value = 6, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_7), value = 7, flags = 0; + endoneof; + endif; //suppressif GopOutputCount != 8 + + + suppressif ideqval NB_GOP_PLATFORM_DATA.BrightnessAvailable == 0x00; + numeric varid = SETUP_DATA.GopBrightness, + prompt = STRING_TOKEN(STR_GOP_BRIGHTNESS), + help = STRING_TOKEN(STR_GOP_BRIGHTNESS_HELP), + flags = INTERACTIVE, key = AUTO_ID(AGP_BRIGHTNESS_KEY), + minimum = 0, + maximum = 0xffffffff, + step = 1, + default = 255, + option text = STRING_TOKEN (STR_GOP_BRIGHTNESS), value = 0, flags = MANUFACTURING | INTERACTIVE; + endnumeric; + endif; + + suppressif ideqval NB_GOP_PLATFORM_DATA.GopBistAvailable == 0x00; + oneof varid = SETUP_DATA.EnableBIST, + prompt = STRING_TOKEN(STR_GOP_BIST_ENABLE), + help = STRING_TOKEN(STR_GOP_BIST_ENABLE_HELP), + option text = STRING_TOKEN(STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED | DEFAULT | MANUFACTURING | INTERACTIVE, key = AUTO_ID(AGP_BIST_KEY); + option text = STRING_TOKEN(STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED; + endoneof; + endif; //suppressif GopBistAvailable == 0 + + //endif; //suppressif GopDeviceCount < 1 +/* + SEPARATOR + + suppressif ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x0 OR + ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x1; + SUBTITLE(STRING_TOKEN(STR_GOP_DEVICE_NAME_1)) + SUBTITLE(STRING_TOKEN(STR_GOP_DRIVER_NAME_1)) + endif; //suppressif GopDeviceCount < 2 + + SEPARATOR + + suppressif ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x0 OR + ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x1 OR + ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x2; + SUBTITLE(STRING_TOKEN(STR_GOP_DEVICE_NAME_2)) + SUBTITLE(STRING_TOKEN(STR_GOP_DRIVER_NAME_2)) + endif; //suppressif GopDeviceCount < 3 + + SEPARATOR + + suppressif ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x0 OR + ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x1 OR + ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x2 OR + ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x3; + SUBTITLE(STRING_TOKEN(STR_GOP_DEVICE_NAME_3)) + SUBTITLE(STRING_TOKEN(STR_GOP_DRIVER_NAME_3)) + endif; //suppressif GopDeviceCount < 4 +*/ + endform; + +#endif //FORM_SET_FORM + +#endif //ADVANCED_FORM_SET + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.sdl b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.sdl new file mode 100644 index 0000000..ebfe462 --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.sdl @@ -0,0 +1,72 @@ +TOKEN + Name = "IntelSaGopSetup_SUPPORT" + Value = "1" + Help = "Main switch to enable IntelSaGopSetup support in Project" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Master = Yes + Token = "AmiGopPolicy" "=" "1" +End + +PATH + Name = "IntelSaGopSetup_DIR" +End + +MODULE + Help = "Includes IntelSaGopSetup.mak to Project" + File = "IntelSaGopSetup.mak" +End + +ELINK + Name = "IntelSaGopSetupInfo," + Parent = "InitAmiGopPolicyStrings," + InvokeOrder = AfterParent +End + +ELINK + Name = "/I$(IntelSaGopSetup_DIR)" + Parent = "$(GLOBAL_DEFINES)" + InvokeOrder = AfterParent +End + +TOKEN + Name = "====== For Intel Brightness ======" + TokenType = Expression +End + +ELINK + Name = "$(IntelSaGopSetup_DIR)\IntelSaGopSetup.sd" + Parent = "$(AMIGOPPOLICY_DIR)\AmiGopPolicy.sd" + InvokeOrder = ReplaceParent + Token = "AmiGopPolicy" "=" "1" +End + +ELINK + Name = "$(IntelSaGopSetup_DIR)\IntelSaGopSetup.uni" + Parent = "$(AMIGOPPOLICY_DIR)\AmiGopPolicy.uni" + InvokeOrder = ReplaceParent + Token = "AmiGopPolicy" "=" "1" +End + +ELINK + Name = "IntelGopSwitchFunction," + Parent = "AmiDefaultGopSwitchFunction," + InvokeOrder = ReplaceParent + Token = "AmiGopPolicy" "=" "1" +End + +ELINK + Name = "ITEM_CALLBACK(ADVANCED_FORM_SET_CLASS,0,AGP_BRIGHTNESS_KEY,IntelGopMultifunctionCallback)," + Parent = "SetupItemCallbacks" + InvokeOrder = AfterParent + Token = "AmiGopPolicy" "=" "1" +End + + +ELINK + Name = "ITEM_CALLBACK(ADVANCED_FORM_SET_CLASS,0,AGP_BIST_KEY,IntelGopMultifunctionCallback)," + Parent = "SetupItemCallbacks" + InvokeOrder = AfterParent + Token = "AmiGopPolicy" "=" "1" +End diff --git a/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.uni b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.uni Binary files differnew file mode 100644 index 0000000..55eef78 --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.uni diff --git a/Chipset/NB/LegacyRegion/LegacyRegion.c b/Chipset/NB/LegacyRegion/LegacyRegion.c new file mode 100644 index 0000000..1dd32b6 --- /dev/null +++ b/Chipset/NB/LegacyRegion/LegacyRegion.c @@ -0,0 +1,552 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2005, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 6145-F Northbelt Pkwy, Norcross, GA 30071 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/LegacyRegion/LegacyRegion.c 1 4/02/13 6:27a Ireneyang $ +// +// $Revision: 1 $ +// +// $Date: 4/02/13 6:27a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/LegacyRegion/LegacyRegion.c $ +// +// 1 4/02/13 6:27a Ireneyang +// Support CSM Label 80. +// +// 3 12/25/12 4:41a Abelwu +// Updated for supporting PI 1.x +// +// 2 12/25/12 3:57a Abelwu +// Update for supporting PI 1.x +// +// 1 12/25/12 3:03a Abelwu +// Move Legacy Region from CSM to NB eChipset +// +// 1 12/20/12 12:35p Olegi +// +// 18 6/16/11 6:30p Olegi +// Added variable that was accidently removed during previous check-in. +// +// 17 5/27/11 11:46a Olegi +// [TAG] EIP56524 +// [Category] New Feature +// [Description] Support for LEGACY_REGION2_PROTOCOL +// [Files] LegacyRegion.c, LegacyRegion2.h +// +// 16 10/14/09 11:21a Krishnakumarg +// CloseEvent funtion used instead of a static variable in callback +// routines - EIP 27065 +// +// 15 6/26/09 11:12a Olegi +// +// 14 6/26/09 10:00a Olegi +// gPciRootBridgeIo defined as "static". EIP#23538 +// +// 13 4/27/07 5:45p Olegi +// +// 12 4/27/07 5:42p Olegi +// +// 11 4/27/07 5:21p Olegi +// CSM.CHM preparations. +// +// 10 10/13/06 12:32a Felixp +// UEFI2.0 compliance: use CreateReadyToBootEvent instead of +// CreateEvent(READY_TO_BOOT) +// +// 9 4/24/06 12:47p Olegi +// +// 3 4/24/06 12:43p Olegi +// +// 2 4/18/06 12:11p Olegi +// +// 8 3/31/06 9:43a Olegi +// +// 7 3/31/06 9:06a Olegi +// +// 6 5/27/05 4:24p Markw +// Added Boot Script. +// +// 5 5/06/05 11:27a Yakovlevs +// +// 3 5/06/05 11:02a Yakovlevs +// +// 4 4/19/05 2:42p Sivagarn +// Included pointer to Boot & Runtime Services in PAM programming +// +// 3 4/04/05 4:21p Sivagarn +// Updated to latest template +// +// 2 2/22/05 10:00a Sivagarn +// - Updated to latest labeled CSM & Core +// +// 2 1/18/05 3:22p Felixp +// PrintDebugMessage renamed to Trace +// +// 1 10/26/04 9:48a Olegi +// +// +//********************************************************************** +//<AMI_FHDR_START> +// +// Name: LegacyRegion.c +// +// Description: Legacy Region functions implementation +// +//<AMI_FHDR_END> +//********************************************************************** + +#include <efi.h> +#include <Token.h> +#include <AmiDxeLib.h> +#include <AmiCspLib.h> +#include <Protocol\LegacyRegion.h> +#include <Protocol\LegacyRegion2.h> +#include <Protocol\PciRootBridgeIo.h> +#include <Protocol\BootScriptSave.h> +#include <Protocol\cpu.h> + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A) +EFI_GUID gAmiS3SaveProtocolGuid = EFI_S3_SAVE_STATE_PROTOCOL_GUID; +#else +EFI_GUID gAmiS3SaveProtocolGuid = EFI_BOOT_SCRIPT_SAVE_GUID; +#endif + +EFI_GUID gCpu = EFI_CPU_ARCH_PROTOCOL_GUID; + +EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *gPciRootBridgeIo; + +EFI_EVENT gEvtBootScript; +EFI_CPU_ARCH_PROTOCOL Cpu; +EFI_CPU_ARCH_PROTOCOL *pCpu; + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure: CallbackBootScript +// +// Description: Saves the PAM registers to Boot Script +// +// Input: +// IN EFI_EVENT Event +// IN VOID *Context +// Output: +// None +// +//<AMI_PHDR_END> +//********************************************************************** +VOID CallbackBootScript(IN EFI_EVENT Event, IN VOID *Context) +{ + EFI_STATUS Status; +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A) + EFI_S3_SAVE_STATE_PROTOCOL *BootScriptSave; +#else + EFI_BOOT_SCRIPT_SAVE_PROTOCOL *BootScriptSave; +#endif + + Status = pBS->LocateProtocol( + &gAmiS3SaveProtocolGuid, + NULL, + &BootScriptSave + ); + if (EFI_ERROR(Status)) return; + + NBPAMWriteBootScript(BootScriptSave); + + // + //Kill the Event + // + pBS->CloseEvent(Event); + +} + + +#define LEGACY_REGION_LOCK 0 +#define LEGACY_REGION_BOOT_LOCK 1 +#define LEGACY_REGION_UNLOCK 2 +#define LEGACY_REGION_DECODE_ROM 3 + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ProgramPamRegisters +// +// Description: Program 0xc0000 - 0xfffff regions to Lock/Unlock. +// +// Input: UINT32 StartAddress +// UINT32 Length +// UINT8 Setting +// UINT32 *Granularity +// +// Output: Status of the operation +// +// Notes: Here is the control flow of this function: +// 1. Search the structure for the first entry matching +// the StartAddress. +// 2. If not found, return EFI_INVALID_PARAMETER. +// 3. Find the last entry in structure for the region to program, +// by adding the lengths of the entries. +// 4. If not found, return EFI_INVALID_PARAMETER. +// 5. Read/Write each register for the entry to set region. +// 6. Return the Granularity for the region. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS ProgramPamRegisters( + UINT32 StartAddress, + UINT32 Length, + UINT8 Setting, + UINT32 *Granularity) +{ + EFI_STATUS Status; + UINT64 Attributes; + + Status = NBProgramPAMRegisters (pBS, pRS, StartAddress, Length, Setting, Granularity); + if (Status != EFI_SUCCESS) return Status; + + Status = CPUProgramPAMRegisters (pBS, pRS, StartAddress, Length, Setting, Granularity); + if (Status != EFI_SUCCESS) return Status; + +// Program the MTRRs + switch (Setting) { + + case LEGACY_REGION_LOCK: + Attributes = EFI_MEMORY_WP; + break; + + case LEGACY_REGION_BOOT_LOCK: + Attributes = EFI_MEMORY_WP; + break; + + case LEGACY_REGION_UNLOCK: + Attributes = EFI_MEMORY_WT; + break; + + default: + Attributes = EFI_MEMORY_UC; + + } + +// Status=DxeSvcTbl->SetMemorySpaceAttributes(StartAddress,Length,Attributes); + pCpu->SetMemoryAttributes(pCpu, StartAddress, Length, Attributes); + + return Status; +} + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure: Decode +// +// Description: Program chipset to allow decoding of 0xc0000 - 0xfffff. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This, +// IN UINT32 Start, +// IN UINT32 Length, +// IN BOOLEAN *On +// +// Output: +// Status of the operation +// +//<AMI_PHDR_END> +//********************************************************************** +EFI_STATUS Decode( + IN EFI_LEGACY_REGION_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + IN BOOLEAN *On +) +{ + UINT32 Granularity; + if (*On) { + return ProgramPamRegisters(Start, Length, LEGACY_REGION_UNLOCK, &Granularity); + } else { + return ProgramPamRegisters(Start, Length, LEGACY_REGION_DECODE_ROM, &Granularity); + } +} + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure: LegacyRegionDecode +// +// Description: Program chipset to allow decoding of 0xc0000 - 0xfffff. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This, +// IN UINT32 Start, +// IN UINT32 Length, +// OUT UINT32 *Granularity, +// IN BOOLEAN *On +// +// Output: +// Status of the operation +// +//<AMI_PHDR_END> +//********************************************************************** +EFI_STATUS LegacyRegionDecode( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity, + IN BOOLEAN *On +) +{ + if (*On) { + return ProgramPamRegisters(Start, Length, LEGACY_REGION_UNLOCK, Granularity); + } else { + return ProgramPamRegisters(Start, Length, LEGACY_REGION_DECODE_ROM, Granularity); + } +} + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure: Lock +// +// Description: To disallow writes to memory 0xc0000 - 0xfffff. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This, +// IN UINT32 Start, +// IN UINT32 Length, +// OUT UINT32 *Granularity OPTIONAL +// +// Output: +// Status of the operation +// +//<AMI_PHDR_END> +//********************************************************************** +EFI_STATUS Lock( + IN EFI_LEGACY_REGION_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity OPTIONAL +) +{ + return ProgramPamRegisters(Start, Length, LEGACY_REGION_LOCK, Granularity); +} + +EFI_STATUS LegacyRegionLock( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity OPTIONAL +) +{ + return ProgramPamRegisters(Start, Length, LEGACY_REGION_LOCK, Granularity); +} + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure: BootLock +// +// Description: To permanently disallow writes to memory 0xc0000 - 0xffff. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This, +// IN UINT32 Start, +// IN UINT32 Length, +// OUT UINT32 *Granularity OPTIONAL +// +// Output: +// Status of the operation +// +//<AMI_PHDR_END> +//********************************************************************** +EFI_STATUS BootLock( + IN EFI_LEGACY_REGION_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity OPTIONAL +) +{ + //Can't lock Region permanently. + return ProgramPamRegisters(Start, Length, LEGACY_REGION_BOOT_LOCK, Granularity); +} + +EFI_STATUS LegacyRegionBootLock( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity OPTIONAL +) +{ + return ProgramPamRegisters(Start, Length, LEGACY_REGION_BOOT_LOCK, Granularity); +} + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure: Unlock +// +// Description: To allow read/write of memory 0xc0000-0xfffff. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This, +// IN UINT32 Start, +// IN UINT32 Length, +// OUT UINT32 *Granularity OPTIONAL +// +// Output: +// Status of the operation +// +//<AMI_PHDR_END> +//********************************************************************** +EFI_STATUS Unlock( + IN EFI_LEGACY_REGION_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity OPTIONAL +) +{ + return ProgramPamRegisters(Start, Length, LEGACY_REGION_UNLOCK, Granularity); +} + +EFI_STATUS LegacyRegionUnlock( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity OPTIONAL +) +{ + return ProgramPamRegisters(Start, Length, LEGACY_REGION_UNLOCK, Granularity); +} + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure: GetLegacyRegionInfo +// +// Description: +// This function is used to discover the granularity of the attributes +// for the memory in the legacy region. Each attribute may have a different +// granularity and the granularity may not be the same for all memory ranges +// in the legacy region. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This +// -- Indicates the EFI_LEGACY_REGION_PROTOCOL instance. +// +// Output: +// EFI_UNSUPPORTED - This function is not supported +// EFI_SUCCESS - The following information structure is returned: +// OUT UINT32 *DescriptorCount +// -- The number of region descriptor entries returned in the Descriptor +// buffer. See EFI_LEGACY_REGION_DESCRIPTOR definition for reference. +// OUT EFI_LEGACY_REGION_DESCRIPTOR **Descriptor +// -- A pointer to a pointer used to return a buffer where the legacy +// region information is deposited. This buffer will contain a list +// of DescriptorCount number of region descriptors. This function will +// provide the memory for the buffer. +// +//<AMI_PHDR_END> +//********************************************************************** +EFI_STATUS GetLegacyRegionInfo( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + OUT UINT32 *DescriptorCount, + OUT EFI_LEGACY_REGION_DESCRIPTOR **Descriptor +) +{ + return EFI_UNSUPPORTED; // Note: to support this function there is a need + // to update NB template. +} + +EFI_LEGACY_REGION_PROTOCOL gLegacyRegionProtocol = +{ + Decode, Lock, BootLock, Unlock +}; + +EFI_LEGACY_REGION2_PROTOCOL gLegacyRegion2Protocol = +{ + LegacyRegionDecode, LegacyRegionLock, + LegacyRegionBootLock, LegacyRegionUnlock, + GetLegacyRegionInfo +}; + + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure: InitializeLegacyRegion +// +// Description: Install the legacy region protocol. +// +// Input: +// IN EFI_HANDLE ImageHandle, +// IN EFI_SYSTEM_TABLE *SystemTable +// +// Output: +// Status of the operation +// +// Notes: +// Here is the control flow of this function: +// 1. Get root bridge io protocol. +// 2. Install legacy region protocol. +// +//<AMI_PHDR_END> +//********************************************************************** +EFI_STATUS InitializeLegacyRegion( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + InitAmiLib(ImageHandle, SystemTable); + + pCpu = &Cpu; + Status = pBS->LocateProtocol(&gCpu, NULL, &pCpu); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) return Status; + + Status = pBS->LocateProtocol( + &gEfiPciRootBridgeIoProtocolGuid, + NULL, + &gPciRootBridgeIo); + ASSERT_EFI_ERROR(Status); + + //Create event for boot script + Status = CreateReadyToBootEvent( + TPL_NOTIFY, + CallbackBootScript, + NULL, + &gEvtBootScript + ); + ASSERT_EFI_ERROR(Status); + + return pBS->InstallMultipleProtocolInterfaces( + &ImageHandle, + &gEfiLegacyRegionProtocolGuid, &gLegacyRegionProtocol, + &gEfiLegacyRegion2ProtocolGuid, &gLegacyRegion2Protocol, + NULL + ); +} + + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2005, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 6145-F Northbelt Pkwy, Norcross, GA 30071 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Chipset/NB/LegacyRegion/LegacyRegion.cif b/Chipset/NB/LegacyRegion/LegacyRegion.cif new file mode 100644 index 0000000..e3c2d24 --- /dev/null +++ b/Chipset/NB/LegacyRegion/LegacyRegion.cif @@ -0,0 +1,14 @@ +<component> + name = "LegacyRegion" + category = ModulePart + LocalRoot = "Chipset\NB\LegacyRegion\" + RefName = "NBLegacyRegion" +[files] +"LegacyRegion.sdl" +"LegacyRegion.mak" +"LegacyRegion.dxs" +"LegacyRegion.c" +[parts] +"LEGACY_REGION_PROTOCOLS" +"LEGACY_REGION_PROTOCOLS" +<endComponent> diff --git a/Chipset/NB/LegacyRegion/LegacyRegion.dxs b/Chipset/NB/LegacyRegion/LegacyRegion.dxs new file mode 100644 index 0000000..b1670e2 --- /dev/null +++ b/Chipset/NB/LegacyRegion/LegacyRegion.dxs @@ -0,0 +1,83 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2004, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 6145-F Northbelt Pkwy, Norcross, GA 30071 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/LegacyRegion/LegacyRegion.dxs 1 4/02/13 6:27a Ireneyang $ +// +// $Revision: 1 $ +// +// $Date: 4/02/13 6:27a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/LegacyRegion/LegacyRegion.dxs $ +// +// 1 4/02/13 6:27a Ireneyang +// Support CSM Label 80. +// +// 2 12/26/12 6:01a Abelwu +// Support PI 1.x +// +// 1 12/25/12 3:03a Abelwu +// Move Legacy Region from CSM to NB eChipset +// +// 1 12/20/12 12:35p Olegi +// +// 4 4/27/07 5:21p Olegi +// CSM.CHM preparations. +// +// 3 5/01/06 2:22p Olegi +// +//********************************************************************** +//<AMI_FHDR_START> +// +// Name: LegacyRegion.dxs +// +// Description: Legacy Region dependency file +// +//<AMI_FHDR_END> +//********************************************************************** + +#include <Token.h> +#include <Protocol\PciRootBridgeIo.h> +#include <Protocol\Cpu.h> +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A) +#include <Protocol\S3SaveState.h> +#else +#include <Protocol\BootScriptSave.h> +#endif + +DEPENDENCY_START + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID AND + EFI_CPU_ARCH_PROTOCOL_GUID AND +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A) + EFI_S3_SAVE_STATE_PROTOCOL_GUID +#else + EFI_BOOT_SCRIPT_SAVE_GUID +#endif +DEPENDENCY_END + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2004, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 6145-F Northbelt Pkwy, Norcross, GA 30071 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Chipset/NB/LegacyRegion/LegacyRegion.mak b/Chipset/NB/LegacyRegion/LegacyRegion.mak new file mode 100644 index 0000000..7b47cfa --- /dev/null +++ b/Chipset/NB/LegacyRegion/LegacyRegion.mak @@ -0,0 +1,96 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#********************************************************************** +# $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/LegacyRegion/LegacyRegion.mak 1 4/02/13 6:27a Ireneyang $ +# +# $Revision: 1 $ +# +# $Date: 4/02/13 6:27a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/LegacyRegion/LegacyRegion.mak $ +# +# 1 4/02/13 6:27a Ireneyang +# Support CSM Label 80. +# +# 2 12/26/12 6:05a Abelwu +# Move LegacyRegion from CSM to NB eChipset. +# +# 1 12/25/12 3:03a Abelwu +# Move Legacy Region from CSM to NB eChipset +# +# 1 12/20/12 12:35p Olegi +# +# 6 3/17/06 6:03p Felixp +# +# 5 12/02/05 11:44a Felixp +# +# 4 4/04/05 4:20p Sivagarn +# Included CSP Library in the build process +# +# 2 2/22/05 10:00a Sivagarn +# - Updated to latest labeled CSM & Core +# +# 3 1/18/05 3:22p Felixp +# PrintDebugMessage renamed to Trace +# +# 2 12/17/04 9:12a Olegi +# +# 1 10/26/04 9:48a Olegi +# +# 1 8/30/04 8:17p Markw +# +# 1 8/13/04 2:39p Markw +# +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: LegacyRegion_mak +# +# Description: +# +#<AMI_FHDR_END> +#********************************************************************** +all : LegacyRegion + +LegacyRegion : $(BUILD_DIR)\NBLegacyRegion.mak LegacyRegionBin + +$(BUILD_DIR)\NBLegacyRegion.mak : $(LEGACY_REGION_DIR)\LegacyRegion.cif $(LEGACY_REGION_DIR)\LegacyRegion.mak $(BUILD_RULES) + $(CIF2MAK) $(LEGACY_REGION_DIR)\LegacyRegion.cif $(CIF2MAK_DEFAULTS) + +LegacyRegionBin : $(AMIDXELIB) $(AMICSPLib) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\NBLegacyRegion.mak all\ + GUID=59242DD8-E7CF-4979-B60E-A6067E2A185F \ + ENTRY_POINT=InitializeLegacyRegion \ + DEPEX1=$(LEGACY_REGION_DIR)\LegacyRegion.dxs\ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + TYPE=BS_DRIVER \ + COMPRESS=1\ + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/NB/LegacyRegion/LegacyRegion.sdl b/Chipset/NB/LegacyRegion/LegacyRegion.sdl new file mode 100644 index 0000000..8966091 --- /dev/null +++ b/Chipset/NB/LegacyRegion/LegacyRegion.sdl @@ -0,0 +1,25 @@ +TOKEN + Name = "NB_LegacyRegion_SUPPORT" + Value = "0" + Help = "Main switch to enable North Bridge LegacyRegion support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes +End + +PATH + Name = "LEGACY_REGION_DIR" +End + +MODULE + Help = "Includes LegacyRegion.mak to Project" + File = "LegacyRegion.mak" +End + +ELINK + Name = "$(BUILD_DIR)\NBLegacyRegion.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + diff --git a/Chipset/NB/NB.ASL b/Chipset/NB/NB.ASL new file mode 100644 index 0000000..d9dfd61 --- /dev/null +++ b/Chipset/NB/NB.ASL @@ -0,0 +1,160 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB.ASL 6 5/06/13 7:12a Ireneyang $ +// +// $Revision: 6 $ +// +// $Date: 5/06/13 7:12a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB.ASL $ +// +// 6 5/06/13 7:12a Ireneyang +// [TAG] EIP105358 +// [Category] Improvement +// [Description] Save and restore the missed 81~86 reg lower nibbles for +// S3. +// [Files] NB.ASL; +// +// 5 10/14/12 11:39a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Follow SA RC 0.71. +// [Files] NBPei.c, NBDxe.c; NBGeneric.c; NBCspLib.h; NBSetup.c; +// Nb.sd; GetSetupData.c +// +// 4 8/14/12 4:32a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Change for SystemAgent RefCode Revision: 0.6.1. +// [Files] NB.sdl, NB.sd, NBCSP.CIF, NBDxe.c, NB.ASL, SaAudio.asl +// +// 3 7/03/12 6:39a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Change the Save/Restore NB Registers position. +// [Files] NB.ASL, NBAcpi.c, NBDxe.c +// +// 2 6/14/12 4:39a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Support token to disable PEG 0 ~ 2. +// [Description] NB.sdl, NB.sd, NB.ASL, HOST_BUS.ASL +// +// 1 2/08/12 4:34a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: NB.asl +// +// Description: The ASL file is for North Bridge specific function. +// +//<AMI_FHDR_END> +//************************************************************************* + +Scope(\_SB.PCI0) +{ + // Save/Restore NB Shadow Register(s) Buffer + Name (PA0H, 0) + Name (PA1H, 0) + Name (PA1L, 0) + Name (PA2H, 0) + Name (PA2L, 0) + Name (PA3H, 0) + Name (PA3L, 0) + Name (PA4H, 0) + Name (PA4L, 0) + Name (PA5H, 0) + Name (PA5L, 0) + Name (PA6H, 0) + Name (PA6L, 0) +/* +;<AMI_PHDR_START> +;------------------------------------------------------------------------ +; +; Procedure: NPTS +; Description: METHOD IS CALLED BY OS PRIOR TO ENTER ANY SLEEP STATE +; Input: Arg0 = Arg0 = Sleep state System about to enter +; Output: Nothing +; +;------------------------------------------------------------------------- +;<AMI_PHDR_END> +*/ + Method (NPTS, 1) { + Store(PM0H,PA0H) // 0x80 + Store(PM1H,PA1H) // 0x81 + Store(PM1L,PA1L) + Store(PM2H,PA2H) // 0x82 + Store(PM2L,PA2L) + Store(PM3H,PA3H) // 0x83 + Store(PM3L,PA3L) + Store(PM4H,PA4H) // 0x84 + Store(PM4L,PA4L) + Store(PM5H,PA5H) // 0x85 + Store(PM5L,PA5L) + Store(PM6H,PA6H) // 0x86 + Store(PM6L,PA6L) + } + +/* +;<AMI_PHDR_START> +;------------------------------------------------------------------------ +; +; Procedure: NWAK +; Description: METHOD CALLED ON WAKE UP FROM ANY SLEEP STATE +; Input: Arg0 = Sleep state System is resuming from +; Output: Nothing +; +;------------------------------------------------------------------------- +;<AMI_PHDR_END> +*/ + Method (NWAK, 1) { + Store(PA0H,PM0H) // 0x80 + Store(PA1H,PM1H) // 0x81 + Store(PA1L,PM1L) + Store(PA2H,PM2H) // 0x82 + Store(PA2L,PM2L) + Store(PA3H,PM3H) // 0x83 + Store(PA3L,PM3L) + Store(PA4H,PM4H) // 0x84 + Store(PA4L,PM4L) + Store(PA5H,PM5H) // 0x85 + Store(PA5L,PM5L) + Store(PA6H,PM6H) // 0x86 + Store(PA6L,PM6L) + } + + +}//Scope(\_SB.PCI0) + +//----------------------------------------------------------------------- +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + diff --git a/Chipset/NB/NB.cif b/Chipset/NB/NB.cif new file mode 100644 index 0000000..ab53dd2 --- /dev/null +++ b/Chipset/NB/NB.cif @@ -0,0 +1,13 @@ +<component> + name = "Intel System Agent" + category = eChipset + LocalRoot = "Chipset\NB\" + RefName = "Intel System Agent" +[files] +"ReleaseNotes.chm" +[parts] +"Intel SystemAgent NB Board" +"Intel SystemAgent NB Chipset" +"Intel SystemAgent NB Refcode" +"IntelSaGopDriver" +<endComponent> diff --git a/Chipset/NB/NBAcpi.c b/Chipset/NB/NBAcpi.c new file mode 100644 index 0000000..11024b4 --- /dev/null +++ b/Chipset/NB/NBAcpi.c @@ -0,0 +1,138 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBAcpi.c 2 7/03/12 6:39a Yurenlai $ +// +// $Revision: 2 $ +// +// $Date: 7/03/12 6:39a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBAcpi.c $ +// +// 2 7/03/12 6:39a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Change the Save/Restore NB Registers position. +// [Files] NB.ASL, NBAcpi.c, NBDxe.c +// +// 1 2/08/12 4:34a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: NBACPI.c +// +// Description: This file contains 2 eLinks for all North Bridge ACPI +// Enabled/Disabled events. +// +//<AMI_FHDR_END> +//************************************************************************* + +//---------------------------------------------------------------------------- +// Include(s) +//---------------------------------------------------------------------------- + +#include <Token.h> +#include <AmiDxeLib.h> +#include <AmiCspLib.h> +#include <Protocol\SmmSwDispatch.h> + +//---------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//---------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//---------------------------------------------------------------------------- +// Variable and External Declaration(s) +//---------------------------------------------------------------------------- +// Variable Declaration(s) + +// GUID Definition(s) + +// Protocol Definition(s) + +// External Declaration(s) + +// Function Definition(s) + +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbAcpiEnabled +// +// Description: This routine will be called when ACPI enabled. +// +// Input: DispatchHandle - Handle to the Dispatcher +// DispatchContext - SW SMM dispatcher context +// +// Output: None +// +// Notes: Porting if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbAcpiEnabled ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext ) +{ + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbAcpiDisabled +// +// Description: This routine will be called when ACPI disabled. +// +// Input: DispatchHandle - Handle to the Dispatcher +// DispatchContext - SW SMM dispatcher context +// +// Output: None +// +// Notes: Porting if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbAcpiDisabled ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext ) +{ +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/NBCSP.CIF b/Chipset/NB/NBCSP.CIF new file mode 100644 index 0000000..2bc8825 --- /dev/null +++ b/Chipset/NB/NBCSP.CIF @@ -0,0 +1,22 @@ +<component> + name = "Intel SystemAgent NB Chipset" + category = ModulePart + LocalRoot = "Chipset\NB\" + RefName = "Intel SystemAgent NB Chipset" +[files] +"NBDxe.c" +"NBPEI.c" +"NBGeneric.c" +"NBCspLib.h" +"NbPciCSP.c" +"NBAcpi.c" +"NBSmm.c" +"hsw_VBios.dat" +"NB.ASL" +[parts] +"NBSMI" +"NB Protocols" +"NB PPI" +"SystemAgentWrap" +"NBLegacyRegion" +<endComponent> diff --git a/Chipset/NB/NBCspLib.h b/Chipset/NB/NBCspLib.h new file mode 100644 index 0000000..adac4ee --- /dev/null +++ b/Chipset/NB/NBCspLib.h @@ -0,0 +1,1278 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBCspLib.h 5 10/14/12 5:17a Jeffch $ +// +// $Revision: 5 $ +// +// $Date: 10/14/12 5:17a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBCspLib.h $ +// +// 5 10/14/12 5:17a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Follow SA RC 0.71. +// [Files] NBPei.c, NBDxe.c; NBGeneric.c; NBCspLib.h; NBSetup.c; +// Nb.sd; GetSetupData.c; +// +// 4 10/14/12 12:20a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Update by XTU4.0. +// [Files] NBPei.c, NBDxe.c, NBCspLib.h, NBGeneric.c +// +// 2 4/26/12 2:39a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Fixed PeiRamBootSupport = 1 warm boot system is hang. +// [Description] NBPEI.c, NBCspLib.h +// +// 1 2/08/12 4:34a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: NbCspLib.h +// +// Description: This file contains North Bridge chipset porting functions +// and data structures definition for both PEI & DXE stage. +// +//<AMI_FHDR_END> +//************************************************************************* + +#ifndef __NBLIB_H__ +#define __NBLIB_H__ + +#include <Efi.h> +#include <Pei.h> +#include <Token.h> +#include <Protocol\PciHostBridgeResourceAllocation.h> +#include <Protocol\PciRootBridgeIo.h> +#include <PciHostBridge.h> +#include <AmiDxeLib.h> +#include <PciBus.h> + + +#if ACPI_SUPPORT + #if defined(PI_SPECIFICATION_VERSION) && (PI_SPECIFICATION_VERSION >= 0x0001000A) + #include <Protocol\S3SaveState.h> + #else + #include <Protocol\BootScriptSave.h> + #endif +#endif + +#ifndef AMI_S3_SAVE_PROTOCOL + #if defined(PI_SPECIFICATION_VERSION) && (PI_SPECIFICATION_VERSION >= 0x0001000A) + #define AMI_S3_SAVE_PROTOCOL EFI_S3_SAVE_STATE_PROTOCOL + #define AMI_S3_SAVE_PROTOCOL_GUID &gEfiS3SaveStateProtocolGuid + #else + #define AMI_S3_SAVE_PROTOCOL EFI_BOOT_SCRIPT_SAVE_PROTOCOL + #define AMI_S3_SAVE_PROTOCOL_GUID &gEfiBootScriptSaveGuid + #endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#if CSM_SUPPORT +#define LEGACY_REGION_LOCK 0 +#define LEGACY_REGION_BOOT_LOCK 1 +#define LEGACY_REGION_UNLOCK 2 +#define LEGACY_REGION_DECODE_ROM 3 +#endif + +typedef struct { + UINT8 Bus; + UINT8 Dev; + UINT8 Fun; + UINT8 Reg; + EFI_BOOT_SCRIPT_WIDTH Width; + UINT32 Mask; +} BOOT_SCRIPT_NB_PCI_REG_SAVE; + +typedef struct { + UINT8 Register; + UINT8 Mask; + UINT32 StartAddress; + UINT32 Length; +} NB_PAM_STRUCT; + +UINT8 +NbFrequencyToRatio ( + UINT32 Frequency, + UINT8 RefClk, + UINT32 RefBClk +); + +UINT32 +NbRatioToFrequency ( + UINT8 Ratio, + UINT8 RefClk, + UINT32 RefBClk +); + +EFI_STATUS NBProgramPAMRegisters ( + EFI_BOOT_SERVICES *pBS, + EFI_RUNTIME_SERVICES *pRS, + UINT32 StartAddress, + UINT32 Length, + UINT8 Setting, + UINT32 *Granularity +); + +EFI_STATUS NBPeiProgramPAMRegisters ( + EFI_PEI_SERVICES **PeiServices, + UINT32 StartAddress, + UINT32 Length, + UINT8 Setting, + UINT32 *Granularity OPTIONAL +); + +VOID NBRetrainLinkPciDevice ( + IN UINT8 PciBus, + IN UINT8 PciDev, + IN UINT8 PciFun, + IN UINT8 CapPtr +); + +EFI_STATUS NBProtectedPciDevice ( + IN PCI_DEV_INFO *PciDevice +); + +EFI_STATUS NBProgramPciDevice ( + IN PCI_DEV_INFO *PciDevice +); + +EFI_STATUS NBUpdatePciDeviceAttributes ( + IN PCI_DEV_INFO *PciDevice, + IN OUT UINT64 *Attributes, + IN UINT64 Capabilities, + IN BOOLEAN Set +); + +EFI_STATUS NBPAMWriteBootScript( + IN AMI_S3_SAVE_PROTOCOL *BootScriptSave +); + +VOID NbRuntimeShadowRamWrite( + IN BOOLEAN Enable +); + +BOOLEAN +CheckPeiFvCopyToRam ( + IN EFI_PEI_SERVICES **PeiServices +); + +#if (CORE_COMBINED_VERSION >= 0x4027C) // 4.6.3.6 +#if AMI_ROOT_BRIDGE_SUPPORT == 1 +UINTN HbCspMapRootBrgToHost( + IN PCI_BUS_XLAT_HDR *RootBrgXlatHdr, + IN UINT64 *AllocationAttr, + IN UINT64 *RbSuportedAttr +); + +EFI_STATUS HbCspAllocateResources( + IN PCI_HOST_BRG_DATA *HostBrgData, + IN PCI_ROOT_BRG_DATA *RootBrgData, + IN UINTN RootBrgIndex +); +#endif +#else +UINTN HbCspMapRootBrgToHost( + IN PCI_BUS_XLAT_HDR *RootBrgXlatHdr +); +#endif + +UINT32 NBGetTsegBase ( VOID ); + +VOID NBEnableEmrr( + IN UINT32 IedStart, + IN UINT32 IedSize +); + +UINT32 NbFindCapPtr( + IN UINT64 PciAddress, + IN UINT8 CapId +); + + +VOID +WritePci8S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT8 WriteValue8 +); + +VOID +WritePci16S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT16 WriteValue16 +); + +VOID +WritePci32S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT32 WriteValue32 +); + +VOID +RwPci8S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT8 SetBit8, + IN UINT8 ResetBit8 +); + +VOID +RwPci16S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT16 SetBit16, + IN UINT16 ResetBit16 +); + +VOID +RwPci32S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT32 SetBit32, + IN UINT32 ResetBit32 +); + +VOID +WriteMem8S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT8 Value +); + +VOID +WriteMem16S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT16 Value +); + +VOID +WriteMem32S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT32 Value +); + +VOID +RwMem8S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT8 SetBit8, + IN UINT8 ResetBit8 +); + +VOID +RwMem16S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT16 SetBit16, + IN UINT16 ResetBit16 +); + +VOID +RwMem32S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT32 SetBit32, + IN UINT32 ResetBit32 +); + +UINT8 +ReadPci8( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg +); + +UINT16 +ReadPci16( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg +); + +UINT32 +ReadPci32( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg +); + +VOID +WritePci8( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT8 Value8 +); + +VOID +WritePci16( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT16 Value16 +); + +VOID +WritePci32( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT32 Value32 +); + +VOID +RwPci8( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT8 SetBit8, + IN UINT8 ResetBit8 +); + +VOID +RwPci16( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT16 SetBit16, + IN UINT16 ResetBit16 +); + +VOID +RwPci32( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT32 SetBit32, + IN UINT32 ResetBit32 +); + +VOID +WriteMem8 ( + IN UINT64 Address, + IN UINT8 Value8 +); + +VOID +WriteMem16 ( + IN UINT64 Address, + IN UINT16 Value16 +); + +VOID +WriteMem32 ( + IN UINT64 Address, + IN UINT32 Value32 +); + +VOID +RwMem8( + IN UINT64 Address, + IN UINT8 SetBit8, + IN UINT8 ResetBit8 +); + +VOID +RwMem16( + IN UINT64 Address, + IN UINT16 SetBit16, + IN UINT16 ResetBit16 +); + +VOID +RwMem32( + IN UINT64 Address, + IN UINT32 SetBit32, + IN UINT32 ResetBit32 +); + +//---------------------------------------------------------------------------- +// Standard PCI Macros, No Porting Required. +//---------------------------------------------------------------------------- + +#define READ_PCI8(Bx, Dx, Fx, Rx) ReadPci8(Bx, Dx, Fx, Rx) +#define READ_PCI16(Bx, Dx, Fx, Rx) ReadPci16(Bx, Dx, Fx, Rx) +#define READ_PCI32(Bx, Dx, Fx, Rx) ReadPci32(Bx, Dx, Fx, Rx) +#define WRITE_PCI8(Bx, Dx, Fx, Rx, bVal) WritePci8(Bx, Dx, Fx, Rx, bVal) +#define WRITE_PCI16(Bx, Dx, Fx, Rx, wVal) WritePci16(Bx, Dx, Fx, Rx, wVal) +#define WRITE_PCI32(Bx, Dx, Fx, Rx, dVal) WritePci32(Bx, Dx, Fx, Rx, dVal) +#define RW_PCI8(Bx, Dx, Fx, Rx, Set, Rst) \ + WritePci8(Bx, Dx, Fx, Rx, ReadPci8(Bx, Dx, Fx, Rx) & ~(Rst) | (Set)) +#define RW_PCI16(Bx, Dx, Fx, Rx, Set, Rst) \ + WritePci16(Bx, Dx, Fx, Rx, ReadPci16(Bx, Dx, Fx, Rx) & ~(Rst)|(Set)) +#define RW_PCI32(Bx, Dx, Fx, Rx, Set, Rst) \ + WritePci32(Bx, Dx, Fx, Rx, ReadPci32(Bx, Dx, Fx, Rx) & ~(Rst)|(Set)) +#define SET_PCI8(Bx, Dx, Fx, Rx, bSet) \ + WritePci8(Bx, Dx, Fx, Rx, ReadPci8(Bx, Dx, Fx, Rx) | (bSet)) +#define SET_PCI16(Bx, Dx, Fx, Rx, wSet) \ + WritePci16(Bx, Dx, Fx, Rx, ReadPci16(Bx, Dx, Fx, Rx) | (wSet)) +#define SET_PCI32(Bx, Dx, Fx, Rx, dSet) \ + WritePci32(Bx, Dx, Fx, Rx, ReadPci32(Bx, Dx, Fx, Rx) | (dSet)) +#define RESET_PCI8(Bx, Dx, Fx, Rx, bReset) \ + WritePci8(Bx, Dx, Fx, Rx, ReadPci8(Bx, Dx, Fx, Rx) & ~(bReset)) +#define RESET_PCI16(Bx, Dx, Fx, Rx, wRst) \ + WritePci16(Bx, Dx, Fx, Rx, ReadPci16(Bx, Dx, Fx, Rx) & ~(wRst)) +#define RESET_PCI32(Bx, Dx, Fx, Rx, dRst) \ + WritePci32(Bx, Dx, Fx, Rx, ReadPci32(Bx, Dx, Fx, Rx) & ~(dRst)) + +#define WRITE_PCI8_S3(mBtScSv, Bx, Dx, Fx, Rx, bValue) \ + WritePci8S3(mBtScSv, Bx, Dx, Fx, Rx, bValue) +#define SET_PCI8_S3(mBtScSv, Bx, Dx, Fx, Rx, bSet) \ + RwPci8S3(mBtScSv, Bx, Dx, Fx, Rx, bSet, 0) +#define RESET_PCI8_S3(mBtScSv, Bx, Dx, Fx, Rx, bReset) \ + RwPci8S3(mBtScSv, Bx, Dx, Fx, Rx, 0, bReset) +#define RW_PCI8_S3(mBtScSv, Bx, Dx, Fx, Rx, bSet, bRst) \ + RwPci8S3(mBtScSv, Bx, Dx, Fx, Rx, bSet, bRst) +#define WRITE_PCI16_S3(mBtScSv, Bx, Dx, Fx, Rx, wValue) \ + WritePci16S3(mBtScSv, Bx, Dx, Fx, Rx, wValue) +#define SET_PCI16_S3(mBtScSv, Bx, Dx, Fx, Rx, wSet) \ + RwPci16S3(mBtScSv, Bx, Dx, Fx, Rx, wSet, 0) +#define RESET_PCI16_S3(mBtScSv, Bx, Dx, Fx, Rx, wReset) \ + RwPci16S3(mBtScSv, Bx, Dx, Fx, Rx, 0, wReset) +#define RW_PCI16_S3(mBtScSv, Bx, Dx, Fx, Rx, wSet, wRst) \ + RwPci16S3(mBtScSv, Bx, Dx, Fx, Rx, wSet, wRst) +#define WRITE_PCI32_S3(mBtScSv, Bx, Dx, Fx, Rx, dValue) \ + WritePci32S3(mBtScSv, Bx, Dx, Fx, Rx, dValue) +#define SET_PCI32_S3(mBtScSv, Bx, Dx, Fx, Rx, dSet) \ + RwPci32S3(mBtScSv, Bx, Dx, Fx, Rx, dSet, 0) +#define RESET_PCI32_S3(mBtScSv, Bx, Dx, Fx, Rx, dReset) \ + RwPci32S3(mBtScSv, Bx, Dx, Fx, Rx, 0, dReset) +#define RW_PCI32_S3(mBtScSv, Bx, Dx, Fx, Rx, dSet, dRst) \ + RwPci32S3(mBtScSv, Bx, Dx, Fx, Rx, dSet, dRst) + +//---------------------------------------------------------------------------- +// Standard Memory Macros, No Porting Required. +//---------------------------------------------------------------------------- + +#define READ_MEM8(Addr64) MMIO_READ8(Addr64) +#define MEM_READ8(Addr64) MMIO_READ8(Addr64) +#define READ_MMIO8(Addr64) MMIO_READ8(Addr64) +#define WRITE_MEM8(Addr64, bValue) WriteMem8(Addr64, bValue) +#define MEM_WRITE8(Addr64, bValue) WriteMem8(Addr64, bValue) +#define WRITE_MMIO8(Addr64, bValue) WriteMem8(Addr64, bValue) +#define SET_MEM8(Addr64, bSet) RwMem8(Addr64, bSet, 0) +#define MEM_SET8(Addr64, bSet) RwMem8(Addr64, bSet, 0) +#define SET_MMIO8(Addr64, bSet) RwMem8(Addr64, bSet, 0) +#define MMIO_SET8(Addr64, bSet) RwMem8(Addr64, bSet, 0) +#define RESET_MEM8(Addr64, bReset) RwMem8(Addr64, 0, bReset) +#define MEM_RESET8(Addr64, bReset) RwMem8(Addr64, 0, bReset) +#define RESET_MMIO8(Addr64, bReset) RwMem8(Addr64, 0, bReset) +#define MMIO_RESET8(Addr64, bReset) RwMem8(Addr64, 0, bReset) +#define RW_MEM8(Addr64, bSet, bReset) RwMem8(Addr64, bSet, bReset) +#define MEM_RW8(Addr64, bSet, bReset) RwMem8(Addr64, bSet, bReset) +#define RW_MMIO8(Addr64, bSet, bReset) RwMem8(Addr64, bSet, bReset) +#define MMIO_RW8(Addr64, bSet, bReset) RwMem8(Addr64, bSet, bReset) + +#define READ_MEM16(Addr64) MMIO_READ16(Addr64) +#define MEM_READ16(Addr64) MMIO_READ16(Addr64) +#define READ_MMIO16(Addr64) MMIO_READ16(Addr64) +#define WRITE_MEM16(Addr64, wValue) WriteMem16(Addr64, wValue) +#define MEM_WRITE16(Addr64, wValue) WriteMem16(Addr64, wValue) +#define WRITE_MMIO16(Addr64, wValue) WriteMem16(Addr64, wValue) +#define SET_MEM16(Addr64, wSet) RwMem16(Addr64, wSet, 0) +#define MEM_SET16(Addr64, wSet) RwMem16(Addr64, wSet, 0) +#define SET_MMIO16(Addr64, wSet) RwMem16(Addr64, wSet, 0) +#define MMIO_SET16(Addr64, wSet) RwMem16(Addr64, wSet, 0) +#define RESET_MEM16(Addr64, wReset) RwMem16(Addr64, 0, wReset) +#define MEM_RESET16(Addr64, wReset) RwMem16(Addr64, 0, wReset) +#define RESET_MMIO16(Addr64, wReset) RwMem16(Addr64, 0, wReset) +#define MMIO_RESET16(Addr64, wReset) RwMem16(Addr64, 0, wReset) +#define RW_MEM16(Addr64, wSet, wReset) RwMem16(Addr64, wSet, wReset) +#define MEM_RW16(Addr64, wSet, wReset) RwMem16(Addr64, wSet, wReset) +#define RW_MMIO16(Addr64, wSet, wReset) RwMem16(Addr64, wSet, wReset) +#define MMIO_RW16(Addr64, wSet, wReset) RwMem16(Addr64, wSet, wReset) + +#define READ_MEM32(Addr64) MMIO_READ32(Addr64) +#define MEM_READ32(Addr64) MMIO_READ32(Addr64) +#define READ_MMIO32(Addr64) MMIO_READ32(Addr64) +#define WRITE_MEM32(Addr64, dValue) WriteMem32(Addr64, dValue) +#define MEM_WRITE32(Addr64, dValue) WriteMem32(Addr64, dValue) +#define WRITE_MMIO32(Addr64, dValue) WriteMem32(Addr64, dValue) +#define SET_MEM32(Addr64, dSet) RwMem32(Addr64, dSet, 0) +#define MEM_SET32(Addr64, dSet) RwMem32(Addr64, dSet, 0) +#define SET_MMIO32(Addr64, dSet) RwMem32(Addr64, dSet, 0) +#define MMIO_SET32(Addr64, dSet) RwMem32(Addr64, dSet, 0) +#define RESET_MEM32(Addr64, dReset) RwMem32(Addr64, 0, dReset) +#define MEM_RESET32(Addr64, dReset) RwMem32(Addr64, 0, dReset) +#define RESET_MMIO32(Addr64, dReset) RwMem32(Addr64, 0, dReset) +#define MMIO_RESET32(Addr64, dReset) RwMem32(Addr64, 0, dReset) +#define RW_MEM32(Addr64, dSet, dReset) RwMem32(Addr64, dSet, dReset) +#define MEM_RW32(Addr64, dSet, dReset) RwMem32(Addr64, dSet, dReset) +#define RW_MMIO32(Addr64, dSet, dReset) RwMem32(Addr64, dSet, dReset) +#define MMIO_RW32(Addr64, dSet, dReset) RwMem32(Addr64, dSet, dReset) + +//---------------------------------------------------------------------------- + +#define WRITE_MEM8_S3(mBtScSv, Addr64, bValue) \ + WriteMem8S3(mBtScSv, Addr64, bValue) +#define MEM_WRITE8_S3(mBtScSv, Addr64, bValue) \ + WriteMem8S3(mBtScSv, Addr64, bValue) +#define WRITE_MMIO8_S3(mBtScSv, Addr64, bValue) \ + WriteMem8S3(mBtScSv, Addr64, bValue) +#define MMIO_WRITE8_S3(mBtScSv, Addr64, bValue) \ + WriteMem8S3(mBtScSv, Addr64, bValue) +#define SET_MEM8_S3(mBtScSv, Addr64, bSet) \ + RwMem8S3(mBtScSv, Addr64, bSet, 0) +#define MEM_SET8_S3(mBtScSv, Addr64, bSet) \ + RwMem8S3(mBtScSv, Addr64, bSet, 0) +#define SET_MMIO8_S3(mBtScSv, Addr64, bSet) \ + RwMem8S3(mBtScSv, Addr64, bSet, 0) +#define MMIO_SET8_S3(mBtScSv, Addr64, bSet) \ + RwMem8S3(mBtScSv, Addr64, bSet, 0) +#define RESET_MEM8_S3(mBtScSv, Addr64, bReset) \ + RwMem8S3(mBtScSv, Addr64, 0, bReset) +#define MEM_RESET8_S3(mBtScSv, Addr64, bReset) \ + RwMem8S3(mBtScSv, Addr64, 0, bReset) +#define RESET_MMIO8_S3(mBtScSv, Addr64, bReset) \ + RwMem8S3(mBtScSv, Addr64, 0, bReset) +#define MMIO_RESET8_S3(mBtScSv, Addr64, bReset) \ + RwMem8S3(mBtScSv, Addr64, 0, bReset) +#define RW_MEM8_S3(mBtScSv, Addr64, bSet, bReset) \ + RwMem8S3(mBtScSv, Addr64, bSet, bReset) +#define MEM_RW8_S3(mBtScSv, Addr64, bSet, bReset) \ + RwMem8S3(mBtScSv, Addr64, bSet, bReset) +#define RW_MMIO8_S3(mBtScSv, Addr64, bSet, bReset) \ + RwMem8S3(mBtScSv, Addr64, bSet, bReset) +#define MMIO_RW8_S3(mBtScSv, Addr64, bSet, bReset) \ + RwMem8S3(mBtScSv, Addr64, bSet, bReset) +#define WRITE_MEM16_S3(mBtScSv, Addr64, wValue) \ + WriteMem16S3(mBtScSv, Addr64, wValue) +#define MEM_WRITE16_S3(mBtScSv, Addr64, wValue) \ + WriteMem16S3(mBtScSv, Addr64, wValue) +#define WRITE_MMIO16_S3(mBtScSv, Addr64, wValue) \ + WriteMem16S3(mBtScSv, Addr64, wValue) +#define MMIO_WRITE16_S3(mBtScSv, Addr64, wValue) \ + WriteMem16S3(mBtScSv, Addr64, wValue) +#define SET_MEM16_S3(mBtScSv, Addr64, wSet) \ + RwMem16S3(mBtScSv, Addr64, wSet, 0) +#define MEM_SET16_S3(mBtScSv, Addr64, wSet) \ + RwMem16S3(mBtScSv, Addr64, wSet, 0) +#define SET_MMIO16_S3(mBtScSv, Addr64, wSet) \ + RwMem16S3(mBtScSv, Addr64, wSet, 0) +#define MMIO_SET16_S3(mBtScSv, Addr64, wSet) \ + RwMem16S3(mBtScSv, Addr64, wSet, 0) +#define RESET_MEM16_S3(mBtScSv, Addr64, wReset) \ + RwMem16S3(mBtScSv, Addr64, 0, wReset) +#define MEM_RESET16_S3(mBtScSv, Addr64, wReset) \ + RwMem16S3(mBtScSv, Addr64, 0, wReset) +#define RESET_MMIO16_S3(mBtScSv, Addr64, wReset) \ + RwMem16S3(mBtScSv, Addr64, 0, wReset) +#define MMIO_RESET16_S3(mBtScSv, Addr64, wReset) \ + RwMem16S3(mBtScSv, Addr64, 0, wReset) +#define RW_MEM16_S3(mBtScSv, Addr64, wSet, wReset) \ + RwMem16S3(mBtScSv, Addr64, wSet, wReset) +#define MEM_RW16_S3(mBtScSv, Addr64, wSet, wReset) \ + RwMem16S3(mBtScSv, Addr64, wSet, wReset) +#define RW_MMIO16_S3(mBtScSv, Addr64, wSet, wReset) \ + RwMem16S3(mBtScSv, Addr64, wSet, wReset) +#define MMIO_RW16_S3(mBtScSv, Addr64, wSet, wReset) \ + RwMem16S3(mBtScSv, Addr64, wSet, wReset) +#define WRITE_MEM32_S3(mBtScSv, Addr64, dValue) \ + WriteMem32S3(mBtScSv, Addr64, dValue) +#define MEM_WRITE32_S3(mBtScSv, Addr64, dValue) \ + WriteMem32S3(mBtScSv, Addr64, dValue) +#define WRITE_MMIO32_S3(mBtScSv, Addr64, dValue) \ + WriteMem32S3(mBtScSv, Addr64, dValue) +#define MMIO_WRITE32_S3(mBtScSv, Addr64, dValue) \ + WriteMem32S3(mBtScSv, Addr64, dValue) +#define SET_MEM32_S3(mBtScSv, Addr64, dSet) \ + RwMem32S3(mBtScSv, Addr64, dSet, 0) +#define MEM_SET32_S3(mBtScSv, Addr64, dSet) \ + RwMem32S3(mBtScSv, Addr64, dSet, 0) +#define SET_MMIO32_S3(mBtScSv, Addr64, dSet) \ + RwMem32S3(mBtScSv, Addr64, dSet, 0) +#define MMIO_SET32_S3(mBtScSv, Addr64, dSet) \ + RwMem32S3(mBtScSv, Addr64, dSet, 0) +#define RESET_MEM32_S3(mBtScSv, Addr64, dReset) \ + RwMem32S3(mBtScSv, Addr64, 0, dReset) +#define MEM_RESET32_S3(mBtScSv, Addr64, dReset) \ + RwMem32S3(mBtScSv, Addr64, 0, dReset) +#define RESET_MMIO32_S3(mBtScSv, Addr64, dReset) \ + RwMem32S3(mBtScSv, Addr64, 0, dReset) +#define MMIO_RESET32_S3(mBtScSv, Addr64, dReset) \ + RwMem32S3(mBtScSv, Addr64, 0, dReset) +#define RW_MEM32_S3(mBtScSv, Addr64, dSet, dReset) \ + RwMem32S3(mBtScSv, Addr64, dSet, dReset) +#define MEM_RW32_S3(mBtScSv, Addr64, dSet, dReset) \ + RwMem32S3(mBtScSv, Addr64, dSet, dReset) +#define RW_MMIO32_S3(mBtScSv, Addr64, dSet, dReset) \ + RwMem32S3(mBtScSv, Addr64, dSet, dReset) +#define MMIO_RW32_S3(mBtScSv, Addr64, dSet, dReset) \ + RwMem32S3(mBtScSv, Addr64, dSet, dReset) + +//---------------------------------------------------------------------------- +// Chipset PCI Macros, Porting Required. +//---------------------------------------------------------------------------- + +#define READ_PCI8_NB(Rx) READ_PCI8(NB_BUS, NB_DEV, NB_FUN, Rx) +#define WRITE_PCI8_NB(Rx, Val) WRITE_PCI8(NB_BUS, NB_DEV, NB_FUN, Rx, Val) +#define SET_PCI8_NB(Rx, Set) SET_PCI8(NB_BUS, NB_DEV, NB_FUN, Rx, Set) +#define RESET_PCI8_NB(Rx, Rst) RESET_PCI8(NB_BUS, NB_DEV, NB_FUN, Rx, Rst) +#define RW_PCI8_NB(Rx, St, Rt) RW_PCI8(NB_BUS, NB_DEV, NB_FUN, Rx, St, Rt) +#define READ_PCI16_NB(Rx) READ_PCI16(NB_BUS, NB_DEV, NB_FUN, Rx) +#define WRITE_PCI16_NB(Rx, Val) WRITE_PCI16(NB_BUS, NB_DEV, NB_FUN, Rx, Val) +#define SET_PCI16_NB(Rx, Set) SET_PCI16(NB_BUS, NB_DEV, NB_FUN, Rx, Set) +#define RESET_PCI16_NB(Rx, Rst) RESET_PCI16(NB_BUS, NB_DEV, NB_FUN, Rx, Rst) +#define RW_PCI16_NB(Rx, St, Rt) RW_PCI16(NB_BUS, NB_DEV, NB_FUN, Rx, St, Rt) +#define READ_PCI32_NB(Rx) READ_PCI32(NB_BUS, NB_DEV, NB_FUN, Rx) +#define WRITE_PCI32_NB(Rx, Val) WRITE_PCI32(NB_BUS, NB_DEV, NB_FUN, Rx, Val) +#define SET_PCI32_NB(Rx, Set) SET_PCI32(NB_BUS, NB_DEV, NB_FUN, Rx, Set) +#define RESET_PCI32_NB(Rx, Rst) RESET_PCI32(NB_BUS, NB_DEV, NB_FUN, Rx, Rst) +#define RW_PCI32_NB(Rx, St, Rt) RW_PCI32(NB_BUS, NB_DEV, NB_FUN, Rx, St, Rt) + +//---------------------------------------------------------------------------- + +#define READ_PCI8_PCIEBRN(Rx) \ + READ_PCI8(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx) +#define WRITE_PCI8_PCIEBRN(Rx, Val) \ + WRITE_PCI8(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Val) +#define SET_PCI8_PCIEBRN(Rx, Set) \ + SET_PCI8(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Set) +#define RESET_PCI8_PCIEBRN(Rx, Rst) \ + RESET_PCI8(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Rst) +#define RW_PCI8_PCIEBRN(Rx, St, Rt) \ + RW_PCI8(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, St, Rt) +#define READ_PCI16_PCIEBRN(Rx) \ + READ_PCI16(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx) +#define WRITE_PCI16_PCIEBRN(Rx, Vx) \ + WRITE_PCI16(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Vx) +#define SET_PCI16_PCIEBRN(Rx, Set) \ + SET_PCI16(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Set) +#define RESET_PCI16_PCIEBRN(Rx, Rt) \ + RESET_PCI16(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Rt) +#define RW_PCI16_PCIEBRN(Rx, St, Rt) \ + RW_PCI16(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, St,Rt) +#define READ_PCI32_PCIEBRN(Rx) \ + READ_PCI32(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx) +#define WRITE_PCI32_PCIEBRN(Rx, Vx) \ + WRITE_PCI32(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Vx) +#define SET_PCI32_PCIEBRN(Rx, Set) \ + SET_PCI32(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Set) +#define RESET_PCI32_PCIEBRN(Rx, Rt) \ + RESET_PCI32(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Rt) +#define RW_PCI32_PCIEBRN(Rx, St, Rt) \ + RW_PCI32(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, St,Rt) + +//---------------------------------------------------------------------------- + +#define READ_PCI8_IGD(Rx) READ_PCI8(IGD_BUS, IGD_DEV, IGD_FUN, Rx) +#define WRITE_PCI8_IGD(Rx, Val) WRITE_PCI8(IGD_BUS, IGD_DEV, IGD_FUN, Rx, Val) +#define SET_PCI8_IGD(Rx, Set) SET_PCI8(IGD_BUS, IGD_DEV, IGD_FUN, Rx, Set) +#define RESET_PCI8_IGD(Rx, Rst) RESET_PCI8(IGD_BUS, IGD_DEV, IGD_FUN, Rx, Rst) +#define RW_PCI8_IGD(Rx, St, Rt) RW_PCI8(IGD_BUS, IGD_DEV, IGD_FUN, Rx, St, Rt) +#define READ_PCI16_IGD(Rx) READ_PCI16(IGD_BUS, IGD_DEV, IGD_FUN, Rx) +#define WRITE_PCI16_IGD(Rx, Vx) WRITE_PCI16(IGD_BUS, IGD_DEV, IGD_FUN, Rx, Vx) +#define SET_PCI16_IGD(Rx, Set) SET_PCI16(IGD_BUS, IGD_DEV, IGD_FUN, Rx, Set) +#define RESET_PCI16_IGD(Rx, Rt) RESET_PCI16(IGD_BUS, IGD_DEV, IGD_FUN, Rx, Rt) +#define RW_PCI16_IGD(Rx, St,Rt) RW_PCI16(IGD_BUS, IGD_DEV, IGD_FUN, Rx, St,Rt) +#define READ_PCI32_IGD(Rx) READ_PCI32(IGD_BUS, IGD_DEV, IGD_FUN, Rx) +#define WRITE_PCI32_IGD(Rx, Vx) WRITE_PCI32(IGD_BUS, IGD_DEV, IGD_FUN, Rx, Vx) +#define SET_PCI32_IGD(Rx, Set) SET_PCI32(IGD_BUS, IGD_DEV, IGD_FUN, Rx, Set) +#define RESET_PCI32_IGD(Rx, Rt) RESET_PCI32(IGD_BUS, IGD_DEV, IGD_FUN, Rx, Rt) +#define RW_PCI32_IGD(Rx, St,Rt) RW_PCI32(IGD_BUS, IGD_DEV, IGD_FUN, Rx, St,Rt) + +//---------------------------------------------------------------------------- + +#define WRITE_PCI8_NB_S3(mBoot, Rx, Val) \ + WRITE_PCI8_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Val) +#define SET_PCI8_NB_S3(mBoot, Rx, Set) \ + SET_PCI8_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Set) +#define RESET_PCI8_NB_S3(mBoot, Rx, Reset) \ + RESET_PCI8_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Reset) +#define RW_PCI8_NB_S3(mBoot, Rx, Set, Rst) \ + RW_PCI8_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Set, Rst) +#define WRITE_PCI16_NB_S3(mBoot, Rx, Val) \ + WRITE_PCI16_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Val) +#define SET_PCI16_NB_S3(mBoot, Rx, Set) \ + SET_PCI16_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Set) +#define RESET_PCI16_NB_S3(mBoot, Rx, Reset) \ + RESET_PCI16_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Reset) +#define RW_PCI16_NB_S3(mBoot, Rx, Set, Rst) \ + RW_PCI16_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Set, Rst) +#define WRITE_PCI32_NB_S3(mBoot, Rx, Val) \ + WRITE_PCI32_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Val) +#define SET_PCI32_NB_S3(mBoot, Rx, Set) \ + SET_PCI32_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Set) +#define RESET_PCI32_NB_S3(mBoot, Rx, Reset) \ + RESET_PCI32_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Reset) +#define RW_PCI32_NB_S3(mBoot, Rx, Set, Rst) \ + RW_PCI32_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Set, Rst) + +//---------------------------------------------------------------------------- + +#define WRITE_PCI8_PCIEBRN_S3(mBoot, Rx, Val) \ + WRITE_PCI8_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Val) +#define SET_PCI8_PCIEBRN_S3(mBoot, Rx, Set) \ + SET_PCI8_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Set) +#define RESET_PCI8_PCIEBRN_S3(mBoot, Rx, Rst) \ + RESET_PCI8_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Rst) +#define RW_PCI8_PCIEBRN_S3(mBoot, Rx, St, Rt) \ + RW_PCI8_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, St, Rt) +#define WRITE_PCI16_PCIEBRN_S3(mBoot, Rx, Val) \ + WRITE_PCI16_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Val) +#define SET_PCI16_PCIEBRN_S3(mBoot, Rx, Set) \ + SET_PCI16_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Set) +#define RESET_PCI16_PCIEBRN_S3(mBoot, Rx, Rst) \ + RESET_PCI16_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Rst) +#define RW_PCI16_PCIEBRN_S3(mBoot, Rx, St, Rt) \ + RW_PCI16_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, St, Rt) +#define WRITE_PCI32_PCIEBRN_S3(mBoot, Rx, Val) \ + WRITE_PCI32_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Val) +#define SET_PCI32_PCIEBRN_S3(mBoot, Rx, Set) \ + SET_PCI32_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Set) +#define RESET_PCI32_PCIEBRN_S3(mBoot, Rx, Reset) \ + RESET_PCI32_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Rst) +#define RW_PCI32_PCIEBRN_S3(mBoot, Rx, St, Rt) \ + RW_PCI32_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, St, Rt) + +//---------------------------------------------------------------------------- + +#define WRITE_PCI8_IGD_S3(mBoot, Rx, Val) \ + WRITE_PCI8_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Val) +#define SET_PCI8_IGD_S3(mBoot, Rx, Set) \ + SET_PCI8_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Set) +#define RESET_PCI8_IGD_S3(mBoot, Rx, Reset) \ + RESET_PCI8_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Reset) +#define RW_PCI8_IGD_S3(mBoot, Rx, Set, Rst) \ + RW_PCI8_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Set, Rst) +#define WRITE_PCI16_IGD_S3(mBoot, Rx, Val) \ + WRITE_PCI16_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Val) +#define SET_PCI16_IGD_S3(mBoot, Rx, Set) \ + SET_PCI16_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Set) +#define RESET_PCI16_IGD_S3(mBoot, Rx, Reset) \ + RESET_PCI16_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Reset) +#define RW_PCI16_IGD_S3(mBoot, Rx, Set, Rst) \ + RW_PCI16_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Set, Rst) +#define WRITE_PCI32_IGD_S3(mBoot, Rx, Val) \ + WRITE_PCI32_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Val) +#define SET_PCI32_IGD_S3(mBoot, Rx, Set) \ + SET_PCI32_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Set) +#define RESET_PCI32_IGD_S3(mBoot, Rx, Reset) \ + RESET_PCI32_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Reset) +#define RW_PCI32_IGD_S3(mBoot, Rx, Set, Rst) \ + RW_PCI32_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Set, Rst) + +//---------------------------------------------------------------------------- +// Chipset MMIO Macros, Porting Required. +//---------------------------------------------------------------------------- + +#define READ_MEM8_EP(wReg) READ_MEM8(NB_EP_BASE_ADDRESS | wReg) +#define READ_MMIO8_EP(wReg) READ_MEM8(NB_EP_BASE_ADDRESS | wReg) +#define WRITE_MEM8_EP(wReg, bVal) WRITE_MEM8(NB_EP_BASE_ADDRESS | wReg,bVal) +#define WRITE_MMIO8_EP(wReg, bVal) WRITE_MEM8(NB_EP_BASE_ADDRESS | wReg,bVal) +#define SET_MEM8_EP(wReg, Set) RW_MEM8(NB_EP_BASE_ADDRESS | wReg, Set, 0) +#define SET_MMIO8_EP(wReg, Set) RW_MEM8(NB_EP_BASE_ADDRESS | wReg, Set, 0) +#define RESET_MEM8_EP(wReg, Rst) RW_MEM8(NB_EP_BASE_ADDRESS | wReg, 0, Rst) +#define RESET_MMIO8_EP(wReg, Rst) RW_MEM8(NB_EP_BASE_ADDRESS | wReg, 0, Rst) +#define RW_MEM8_EP(wReg, Set, Rst) RW_MEM8(NB_EP_BASE_ADDRESS|wReg, Set, Rst) +#define RW_MMIO8_EP(wReg, Set, Rst) RW_MEM8(NB_EP_BASE_ADDRESS|wReg, Set, Rst) +#define READ_MEM16_EP(wReg) READ_MEM16(NB_EP_BASE_ADDRESS | wReg) +#define READ_MMIO16_EP(wReg) READ_MEM16(NB_EP_BASE_ADDRESS | wReg) +#define WRITE_MEM16_EP(wReg, wVal) WRITE_MEM16(NB_EP_BASE_ADDRESS|wReg, wVal) +#define WRITE_MMIO16_EP(wReg, wVal) WRITE_MEM16(NB_EP_BASE_ADDRESS|wReg, wVal) +#define SET_MEM16_EP(wReg, Set) RW_MEM16(NB_EP_BASE_ADDRESS|wReg, Set, 0) +#define SET_MMIO16_EP(wReg, Set) RW_MEM16(NB_EP_BASE_ADDRESS|wReg, Set, 0) +#define RESET_MEM16_EP(wReg, Rst) RW_MEM16(NB_EP_BASE_ADDRESS | wReg, 0,Rst) +#define RESET_MMIO16_EP(wReg, Rst) RW_MEM16(NB_EP_BASE_ADDRESS | wReg, 0,Rst) +#define RW_MEM16_EP(wReg, Set, Rst) RW_MEM16(NB_EP_BASE_ADDRESS|wReg, Set,Rst) +#define RW_MMIO16_EP(wReg, Set,Rst) RW_MEM16(NB_EP_BASE_ADDRESS|wReg, Set,Rst) +#define READ_MEM32_EP(wReg) READ_MEM32(NB_EP_BASE_ADDRESS | wReg) +#define READ_MMIO32_EP(wReg) READ_MEM32(NB_EP_BASE_ADDRESS | wReg) +#define WRITE_MEM32_EP(wReg, dVal) WRITE_MEM32(NB_EP_BASE_ADDRESS|wReg, dVal) +#define WRITE_MMIO32_EP(wReg, dVal) WRITE_MEM32(NB_EP_BASE_ADDRESS|wReg, dVal) +#define SET_MEM32_EP(wReg, Set) RW_MEM32(NB_EP_BASE_ADDRESS|wReg, Set, 0) +#define SET_MMIO32_EP(wReg, Set) RW_MEM32(NB_EP_BASE_ADDRESS|wReg, Set, 0) +#define RESET_MEM32_EP(wReg, Rst) RW_MEM32(NB_EP_BASE_ADDRESS|wReg, 0, Rst) +#define RESET_MMIO32_EP(wReg, Rst) RW_MEM32(NB_EP_BASE_ADDRESS|wReg, 0, Rst) +#define RW_MEM32_EP(wReg, Set, Rst) RW_MEM32(NB_EP_BASE_ADDRESS|wReg, Set,Rst) +#define RW_MMIO32_EP(wReg, Set,Rst) RW_MEM32(NB_EP_BASE_ADDRESS|wReg, Set,Rst) + +//---------------------------------------------------------------------------- + +#define READ_MEM8_MCH(wReg) READ_MEM8(NB_MCH_BASE_ADDRESS | wReg) +#define READ_MMIO8_MCH(wReg) READ_MEM8(NB_MCH_BASE_ADDRESS | wReg) +#define WRITE_MEM8_MCH(wReg, bVal) WRITE_MEM8(NB_MCH_BASE_ADDRESS| wReg,bVal) +#define WRITE_MMIO8_MCH(wReg, bVal) WRITE_MEM8(NB_MCH_BASE_ADDRESS| wReg,bVal) +#define SET_MEM8_MCH(wReg, Set) RW_MEM8(NB_MCH_BASE_ADDRESS | wReg, Set,0) +#define SET_MMIO8_MCH(wReg, Set) RW_MEM8(NB_MCH_BASE_ADDRESS | wReg, Set,0) +#define RESET_MEM8_MCH(wReg, Rst) RW_MEM8(NB_MCH_BASE_ADDRESS | wReg,0, Rst) +#define RESET_MMIO8_MCH(wReg, Rst) RW_MEM8(NB_MCH_BASE_ADDRESS | wReg,0, Rst) +#define RW_MEM8_MCH(wReg, Set, Rst) RW_MEM8(NB_MCH_BASE_ADDRESS|wReg, Set,Rst) +#define RW_MMIO8_MCH(wReg, Set,Rst) RW_MEM8(NB_MCH_BASE_ADDRESS|wReg, Set,Rst) +#define READ_MEM16_MCH(wReg) READ_MEM16(NB_MCH_BASE_ADDRESS | wReg) +#define READ_MMIO16_MCH(wReg) READ_MEM16(NB_MCH_BASE_ADDRESS | wReg) +#define WRITE_MEM16_MCH(wReg, wVal) WRITE_MEM16(NB_MCH_BASE_ADDRESS|wReg,wVal) +#define WRITE_MMIO16_MCH(wReg,wVal) WRITE_MEM16(NB_MCH_BASE_ADDRESS|wReg,wVal) +#define SET_MEM16_MCH(wReg, Set) RW_MEM16(NB_MCH_BASE_ADDRESS|wReg,Set, 0) +#define SET_MMIO16_MCH(wReg, Set) RW_MEM16(NB_MCH_BASE_ADDRESS|wReg,Set, 0) +#define RESET_MEM16_MCH(wReg, Rst) RW_MEM16(NB_MCH_BASE_ADDRESS | wReg,0,Rst) +#define RESET_MMIO16_MCH(wReg, Rst) RW_MEM16(NB_MCH_BASE_ADDRESS | wReg,0,Rst) +#define RW_MEM16_MCH(wReg, Set,Rst) RW_MEM16(NB_MCH_BASE_ADDRESS|wReg,Set,Rst) +#define RW_MMIO16_MCH(wReg,Set,Rst) RW_MEM16(NB_MCH_BASE_ADDRESS|wReg,Set,Rst) +#define READ_MEM32_MCH(wReg) READ_MEM32(NB_MCH_BASE_ADDRESS | wReg) +#define READ_MMIO32_MCH(wReg) READ_MEM32(NB_MCH_BASE_ADDRESS | wReg) +#define WRITE_MEM32_MCH(wReg, dVal) WRITE_MEM32(NB_MCH_BASE_ADDRESS|wReg,dVal) +#define WRITE_MMIO32_MCH(wReg,dVal) WRITE_MEM32(NB_MCH_BASE_ADDRESS|wReg,dVal) +#define SET_MEM32_MCH(wReg, Set) RW_MEM32(NB_MCH_BASE_ADDRESS|wReg, Set, 0) +#define SET_MMIO32_MCH(wReg, Set) RW_MEM32(NB_MCH_BASE_ADDRESS|wReg, Set, 0) +#define RESET_MEM32_MCH(wReg, Rst) RW_MEM32(NB_MCH_BASE_ADDRESS|wReg, 0, Rst) +#define RESET_MMIO32_MCH(wReg, Rst) RW_MEM32(NB_MCH_BASE_ADDRESS|wReg, 0, Rst) +#define RW_MEM32_MCH(wReg, Set,Rst) RW_MEM32(NB_MCH_BASE_ADDRESS|wReg,Set,Rst) +#define RW_MMIO32_MCH(wReg,Set,Rst) RW_MEM32(NB_MCH_BASE_ADDRESS|wReg,Set,Rst) + +//---------------------------------------------------------------------------- + +#define READ_MEM8_DMI(wReg) READ_MEM8(NB_DMI_BASE_ADDRESS | wReg) +#define READ_MMIO8_DMI(wReg) READ_MEM8(NB_DMI_BASE_ADDRESS | wReg) +#define WRITE_MEM8_DMI(wReg, bVal) WRITE_MEM8(NB_DMI_BASE_ADDRESS| wReg,bVal) +#define WRITE_MMIO8_DMI(wReg, bVal) WRITE_MEM8(NB_DMI_BASE_ADDRESS| wReg,bVal) +#define SET_MEM8_DMI(wReg, Set) RW_MEM8(NB_DMI_BASE_ADDRESS | wReg, Set,0) +#define SET_MMIO8_DMI(wReg, Set) RW_MEM8(NB_DMI_BASE_ADDRESS | wReg, Set,0) +#define RESET_MEM8_DMI(wReg, Rst) RW_MEM8(NB_DMI_BASE_ADDRESS | wReg,0, Rst) +#define RESET_MMIO8_DMI(wReg, Rst) RW_MEM8(NB_DMI_BASE_ADDRESS | wReg,0, Rst) +#define RW_MEM8_DMI(wReg, Set, Rst) RW_MEM8(NB_DMI_BASE_ADDRESS|wReg, Set,Rst) +#define RW_MMIO8_DMI(wReg, Set,Rst) RW_MEM8(NB_DMI_BASE_ADDRESS|wReg, Set,Rst) +#define READ_MEM16_DMI(wReg) READ_MEM16(NB_DMI_BASE_ADDRESS | wReg) +#define READ_MMIO16_DMI(wReg) READ_MEM16(NB_DMI_BASE_ADDRESS | wReg) +#define WRITE_MEM16_DMI(wReg, wVal) WRITE_MEM16(NB_DMI_BASE_ADDRESS|wReg,wVal) +#define WRITE_MMIO16_DMI(wReg,wVal) WRITE_MEM16(NB_DMI_BASE_ADDRESS|wReg,wVal) +#define SET_MEM16_DMI(wReg, Set) RW_MEM16(NB_DMI_BASE_ADDRESS|wReg,Set, 0) +#define SET_MMIO16_DMI(wReg, Set) RW_MEM16(NB_DMI_BASE_ADDRESS|wReg,Set, 0) +#define RESET_MEM16_DMI(wReg, Rst) RW_MEM16(NB_DMI_BASE_ADDRESS | wReg,0,Rst) +#define RESET_MMIO16_DMI(wReg, Rst) RW_MEM16(NB_DMI_BASE_ADDRESS | wReg,0,Rst) +#define RW_MEM16_DMI(wReg, Set,Rst) RW_MEM16(NB_DMI_BASE_ADDRESS|wReg,Set,Rst) +#define RW_MMIO16_DMI(wReg,Set,Rst) RW_MEM16(NB_DMI_BASE_ADDRESS|wReg,Set,Rst) +#define READ_MEM32_DMI(wReg) READ_MEM32(NB_DMI_BASE_ADDRESS | wReg) +#define READ_MMIO32_DMI(wReg) READ_MEM32(NB_DMI_BASE_ADDRESS | wReg) +#define WRITE_MEM32_DMI(wReg, dVal) WRITE_MEM32(NB_DMI_BASE_ADDRESS|wReg,dVal) +#define WRITE_MMIO32_DMI(wReg,dVal) WRITE_MEM32(NB_DMI_BASE_ADDRESS|wReg,dVal) +#define SET_MEM32_DMI(wReg, Set) RW_MEM32(NB_DMI_BASE_ADDRESS|wReg, Set, 0) +#define SET_MMIO32_DMI(wReg, Set) RW_MEM32(NB_DMI_BASE_ADDRESS|wReg, Set, 0) +#define RESET_MEM32_DMI(wReg, Rst) RW_MEM32(NB_DMI_BASE_ADDRESS|wReg, 0, Rst) +#define RESET_MMIO32_DMI(wReg,Rst) RW_MEM32(NB_DMI_BASE_ADDRESS|wReg, 0, Rst) +#define RW_MEM32_DMI(wReg, Set,Rst) RW_MEM32(NB_DMI_BASE_ADDRESS|wReg,Set,Rst) +#define RW_MMIO32_DMI(wReg,Set,Rst) RW_MEM32(NB_DMI_BASE_ADDRESS|wReg,Set,Rst) + +//---------------------------------------------------------------------------- + +#define WRITE_MEM8_EP_S3(mBoot, wReg, bVal) \ + WRITE_MEM8_S3(mBoot, NB_EP_BASE_ADDRESS | wReg,bVal) +#define WRITE_MMIO8_EP_S3(mBoot, wReg, bVal) \ + WRITE_MEM8_S3(mBoot, NB_EP_BASE_ADDRESS | wReg,bVal) +#define SET_MEM8_EP_S3(mBoot, wReg, Set) \ + RW_MEM8_S3(mBoot, NB_EP_BASE_ADDRESS | wReg, Set, 0) +#define SET_MMIO8_EP_S3(mBoot, wReg, Set) \ + RW_MEM8_S3(mBoot, NB_EP_BASE_ADDRESS | wReg, Set, 0) +#define RESET_MEM8_EP_S3(mBoot, wReg, Rst) \ + RW_MEM8_S3(mBoot, NB_EP_BASE_ADDRESS | wReg, 0, Rst) +#define RESET_MMIO8_EP_S3(mBoot, wReg, Rst) \ + RW_MEM8_S3(mBoot, NB_EP_BASE_ADDRESS | wReg, 0, Rst) +#define RW_MEM8_EP_S3(mBoot, wReg, Set, Rst) \ + RW_MEM8_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, Set, Rst) +#define RW_MMIO8_EP_S3(mBoot, wReg, Set, Rst) \ + RW_MEM8_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, Set, Rst) +#define WRITE_MEM16_EP_S3(mBoot, wReg, wVal) \ + WRITE_MEM16_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, wVal) +#define WRITE_MMIO16_EP_S3(mBoot, wReg, wVal) \ + WRITE_MEM16_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, wVal) +#define SET_MEM16_EP_S3(mBoot, wReg, Set) \ + RW_MEM16_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, Set, 0) +#define SET_MMIO16_EP_S3(mBoot, wReg, Set) \ + RW_MEM16_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, Set, 0) +#define RESET_MEM16_EP_S3(mBoot, wReg, Rst) \ + RW_MEM16_S3(mBoot, NB_EP_BASE_ADDRESS | wReg, 0,Rst) +#define RESET_MMIO16_EP_S3(mBoot, wReg, Rst) \ + RW_MEM16_S3(mBoot, NB_EP_BASE_ADDRESS | wReg, 0,Rst) +#define RW_MEM16_EP_S3(mBoot, wReg, Set, Rst) \ + RW_MEM16_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, Set,Rst) +#define RW_MMIO16_EP_S3(mBoot, wReg, Set, Rst) \ + RW_MEM16_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, Set,Rst) +#define WRITE_MEM32_EP_S3(mBoot, wReg, dVal) \ + WRITE_MEM32_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, dVal) +#define WRITE_MMIO32_EP_S3(mBoot, wReg, dVal) \ + WRITE_MEM32_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, dVal) +#define SET_MEM32_EP_S3(mBoot, wReg, Set) \ + RW_MEM32_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, Set, 0) +#define SET_MMIO32_EP_S3(mBoot, wReg, Set) \ + RW_MEM32_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, Set, 0) +#define RESET_MEM32_EP_S3(mBoot, wReg, Rst) \ + RW_MEM32_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, 0, Rst) +#define RESET_MMIO32_EP_S3(mBoot, wReg, Rst) \ + RW_MEM32_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, 0, Rst) +#define RW_MEM32_EP_S3(mBoot, wReg, Set, Rst) \ + RW_MEM32_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, Set,Rst) +#define RW_MMIO32_EP_S3(mBoot, wReg, Set, Rst) \ + RW_MEM32_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, Set,Rst) + +//---------------------------------------------------------------------------- + +#define WRITE_MEM8_MCH_S3(mBoot, wReg, bVal) \ + WRITE_MEM8_S3(mBoot, NB_MCH_BASE_ADDRESS | wReg,bVal) +#define WRITE_MMIO8_MCH_S3(mBoot, wReg, bVal) \ + WRITE_MEM8_S3(mBoot, NB_MCH_BASE_ADDRESS | wReg,bVal) +#define SET_MEM8_MCH_S3(mBoot, wReg, Set) \ + RW_MEM8_S3(mBoot, NB_MCH_BASE_ADDRESS | wReg, Set, 0) +#define SET_MMIO8_MCH_S3(mBoot, wReg, Set) \ + RW_MEM8_S3(mBoot, NB_MCH_BASE_ADDRESS | wReg, Set, 0) +#define RESET_MEM8_MCH_S3(mBoot, wReg, Rst) \ + RW_MEM8_S3(mBoot, NB_MCH_BASE_ADDRESS | wReg, 0, Rst) +#define RESET_MMIO8_MCH_S3(mBoot, wReg, Rst) \ + RW_MEM8_S3(mBoot, NB_MCH_BASE_ADDRESS | wReg, 0, Rst) +#define RW_MEM8_MCH_S3(mBoot, wReg, Set, Rst) \ + RW_MEM8_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, Set, Rst) +#define RW_MMIO8_MCH_S3(mBoot, wReg, Set, Rst) \ + RW_MEM8_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, Set, Rst) +#define WRITE_MEM16_MCH_S3(mBoot, wReg, wVal) \ + WRITE_MEM16_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, wVal) +#define WRITE_MMIO16_MCH_S3(mBoot, wReg, wVal) \ + WRITE_MEM16_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, wVal) +#define SET_MEM16_MCH_S3(mBoot, wReg, Set) \ + RW_MEM16_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, Set, 0) +#define SET_MMIO16_MCH_S3(mBoot, wReg, Set) \ + RW_MEM16_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, Set, 0) +#define RESET_MEM16_MCH_S3(mBoot, wReg, Rst) \ + RW_MEM16_S3(mBoot, NB_MCH_BASE_ADDRESS | wReg, 0,Rst) +#define RESET_MMIO16_MCH_S3(mBoot, wReg, Rst) \ + RW_MEM16_S3(mBoot, NB_MCH_BASE_ADDRESS | wReg, 0,Rst) +#define RW_MEM16_MCH_S3(mBoot, wReg, Set, Rst) \ + RW_MEM16_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, Set,Rst) +#define RW_MMIO16_MCH_S3(mBoot, wReg, Set, Rst) \ + RW_MEM16_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, Set,Rst) +#define WRITE_MEM32_MCH_S3(mBoot, wReg, dVal) \ + WRITE_MEM32_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, dVal) +#define WRITE_MMIO32_MCH_S3(mBoot, wReg, dVal) \ + WRITE_MEM32_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, dVal) +#define SET_MEM32_MCH_S3(mBoot, wReg, Set) \ + RW_MEM32_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, Set, 0) +#define SET_MMIO32_MCH_S3(mBoot, wReg, Set) \ + RW_MEM32_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, Set, 0) +#define RESET_MEM32_MCH_S3(mBoot, wReg, Rst) \ + RW_MEM32_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, 0, Rst) +#define RESET_MMIO32_MCH_S3(mBoot, wReg, Rst) \ + RW_MEM32_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, 0, Rst) +#define RW_MEM32_MCH_S3(mBoot, wReg, Set, Rst) \ + RW_MEM32_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, Set,Rst) +#define RW_MMIO32_MCH_S3(mBoot, wReg, Set, Rst) \ + RW_MEM32_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, Set,Rst) + +//---------------------------------------------------------------------------- + +#define WRITE_MEM8_DMI_S3(mBoot, wReg, bVal) \ + WRITE_MEM8_S3(mBoot, NB_DMI_BASE_ADDRESS | wReg,bVal) +#define WRITE_MMIO8_DMI_S3(mBoot, wReg, bVal) \ + WRITE_MEM8_S3(mBoot, NB_DMI_BASE_ADDRESS | wReg,bVal) +#define SET_MEM8_DMI_S3(mBoot, wReg, Set) \ + RW_MEM8_S3(mBoot, NB_DMI_BASE_ADDRESS | wReg, Set, 0) +#define SET_MMIO8_DMI_S3(mBoot, wReg, Set) \ + RW_MEM8_S3(mBoot, NB_DMI_BASE_ADDRESS | wReg, Set, 0) +#define RESET_MEM8_DMI_S3(mBoot, wReg, Rst) \ + RW_MEM8_S3(mBoot, NB_DMI_BASE_ADDRESS | wReg, 0, Rst) +#define RESET_MMIO8_DMI_S3(mBoot, wReg, Rst) \ + RW_MEM8_S3(mBoot, NB_DMI_BASE_ADDRESS | wReg, 0, Rst) +#define RW_MEM8_DMI_S3(mBoot, wReg, Set, Rst) \ + RW_MEM8_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, Set, Rst) +#define RW_MMIO8_DMI_S3(mBoot, wReg, Set, Rst) \ + RW_MEM8_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, Set, Rst) +#define WRITE_MEM16_DMI_S3(mBoot, wReg, wVal) \ + WRITE_MEM16_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, wVal) +#define WRITE_MMIO16_DMI_S3(mBoot, wReg, wVal) \ + WRITE_MEM16_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, wVal) +#define SET_MEM16_DMI_S3(mBoot, wReg, Set) \ + RW_MEM16_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, Set, 0) +#define SET_MMIO16_DMI_S3(mBoot, wReg, Set) \ + RW_MEM16_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, Set, 0) +#define RESET_MEM16_DMI_S3(mBoot, wReg, Rst) \ + RW_MEM16_S3(mBoot, NB_DMI_BASE_ADDRESS | wReg, 0,Rst) +#define RESET_MMIO16_DMI_S3(mBoot, wReg, Rst) \ + RW_MEM16_S3(mBoot, NB_DMI_BASE_ADDRESS | wReg, 0,Rst) +#define RW_MEM16_DMI_S3(mBoot, wReg, Set, Rst) \ + RW_MEM16_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, Set,Rst) +#define RW_MMIO16_DMI_S3(mBoot, wReg, Set, Rst) \ + RW_MEM16_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, Set,Rst) +#define WRITE_MEM32_DMI_S3(mBoot, wReg, dVal) \ + WRITE_MEM32_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, dVal) +#define WRITE_MMIO32_DMI_S3(mBoot, wReg, dVal) \ + WRITE_MEM32_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, dVal) +#define SET_MEM32_DMI_S3(mBoot, wReg, Set) \ + RW_MEM32_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, Set, 0) +#define SET_MMIO32_DMI_S3(mBoot, wReg, Set) \ + RW_MEM32_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, Set, 0) +#define RESET_MEM32_DMI_S3(mBoot, wReg, Rst) \ + RW_MEM32_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, 0, Rst) +#define RESET_MMIO32_DMI_S3(mBoot, wReg, Rst) \ + RW_MEM32_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, 0, Rst) +#define RW_MEM32_DMI_S3(mBoot, wReg, Set, Rst) \ + RW_MEM32_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, Set,Rst) +#define RW_MMIO32_DMI_S3(mBoot, wReg, Set, Rst) \ + RW_MEM32_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, Set,Rst) + +//---------------------------------------------------------------------------- +// Chipset I/O Macros, Porting Required if needed. +//---------------------------------------------------------------------------- + +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- + +//To Exclude AMI Native Root Bridge Driver HOOKS from CSP LIB +#if AMI_ROOT_BRIDGE_SUPPORT == 1 + +//---------------------------------------------------------------------------- +//Function Prototypes for PciRootBridgeIo +//---------------------------------------------------------------------------- + +extern DXE_SERVICES *gDxeSvcTbl; + +EFI_STATUS HbResAllocNotifyPhase ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase +); + +EFI_STATUS HbResAllocGetNextRootBridge ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN OUT EFI_HANDLE *RootBridgeHandle +); + +EFI_STATUS HbResAllocGetAllocAttributes ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT UINT64 *Attributes +); + +EFI_STATUS HbResAllocStartBusEnumeration ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT VOID **Configuration +); + +EFI_STATUS HbResAllocSetBusNumbers ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN VOID *Configuration +); + +EFI_STATUS HbResAllocSubmitResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN VOID *Configuration +); + +EFI_STATUS HbResAllocGetProposedResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT VOID **Configuration +); + +EFI_STATUS HbResAllocPreprocessController ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_CONFIGURATION_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase +); + +EFI_STATUS HbNotifyCspBeforeEnumeration ( + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + UINTN RbCount +); + +EFI_STATUS HbNotifyCspBeginBusAllocation ( + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + UINTN RbCount +); + +EFI_STATUS HbNotifyCspEndBusAllocation ( + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + UINTN RbCount +); + +EFI_STATUS HbNotifyCspBeginResourceAllocation ( + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + UINTN RbCount +); + +EFI_STATUS HbNotifyCspAllocateResources ( + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + UINTN RbCount +); + +EFI_STATUS HbNotifyCspSetResources ( + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + UINTN RbCount +); + +EFI_STATUS HbNotifyCspEndResourceAllocation ( + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + UINTN RbCount +); + +EFI_STATUS HbCspStartBusEnumeration ( + PCI_HOST_BRG_DATA *HostBrgData, + PCI_ROOT_BRG_DATA *RootBrgData, + UINTN RootBrgIndex +); + +EFI_STATUS HbCspSetBusNnumbers ( + PCI_HOST_BRG_DATA *HostBrgData, + PCI_ROOT_BRG_DATA *RootBrgData, + UINTN RootBrgIndex +); + +EFI_STATUS HbCspSubmitResources ( + PCI_HOST_BRG_DATA *HostBrgData, + PCI_ROOT_BRG_DATA *RootBrgData, + UINTN RootBrgIndex +); + +EFI_STATUS HbCspAdjustMemoryMmioOverlap ( + PCI_HOST_BRG_DATA *HostBrgData, + PCI_ROOT_BRG_DATA *RootBrgData, + UINTN RootBrgIndex +); + +EFI_STATUS HbCspBasicChipsetInit ( + PCI_HOST_BRG_DATA *HostBrg0 +); + +UINTN HbCspGetPciSegment ( + UINTN HostBridgeNumber, + UINTN RootBridgeNumber +); + +EFI_STATUS HbCspPreprocessController ( + PCI_HOST_BRG_DATA *HostBrgData, + PCI_ROOT_BRG_DATA *RootBrgData, + UINTN RootBrgNumber, + EFI_PCI_CONFIGURATION_ADDRESS PciAddress, + EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase +); + +EFI_STATUS RbCspIoPciMap ( + IN PCI_ROOT_BRG_DATA *RbData, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, + IN EFI_PHYSICAL_ADDRESS HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping +); + +EFI_STATUS RbCspIoPciUnmap ( + IN PCI_ROOT_BRG_DATA *RbData, + IN PCI_ROOT_BRIDGE_MAPPING *Mapping +); + +EFI_STATUS RbCspIoPciAttributes( + IN PCI_ROOT_BRG_DATA *RbData, + IN UINT64 Attributes, + IN OUT UINT64 *ResourceBase OPTIONAL, + IN OUT UINT64 *ResourceLength OPTIONAL +); + +EFI_STATUS RootBridgeIoPciRW ( + IN PCI_ROOT_BRG_DATA *RbData, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer, + IN BOOLEAN Write +); + +EFI_STATUS RbCspIoPciUnmap ( + IN PCI_ROOT_BRG_DATA *RbData, + OUT PCI_ROOT_BRIDGE_MAPPING *Mapping +); + +EFI_STATUS RbCspIoPciMap ( + IN PCI_ROOT_BRG_DATA *RbData, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, + IN EFI_PHYSICAL_ADDRESS HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping +); + +//-------------------------------------- +//#if AMI_ROOT_BRIDGE_SUPPORT == 1 +#endif + +#ifdef __cplusplus +} +#endif +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/NBDxe.c b/Chipset/NB/NBDxe.c new file mode 100644 index 0000000..15dbbd0 --- /dev/null +++ b/Chipset/NB/NBDxe.c @@ -0,0 +1,4650 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBDxe.c 50 12/02/14 3:20a Dennisliu $ +// +// $Revision: 50 $ +// +// $Date: 12/02/14 3:20a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBDxe.c $ +// +// 50 12/02/14 3:20a Dennisliu +// [TAG] EIP194524 +// [Category] Spec Update +// [Description] Shark Bay SA Reference Code Production Version 1.9.0 +// +// 49 5/28/14 3:03a Dennisliu +// [TAG] EIP161790 +// [Category] Improvement +// [Description] DRAM Init BIT should be set after saving MRC S3 data to +// NVRAM in DXE Phase as Intel suggested. +// [Files] NBPei.c; NBDxe.c; +// +// 48 5/13/14 10:40p Dennisliu +// [TAG] EIP167027 +// [Category] Improvement +// [Description] [SharkBay Aptio4]Variable's attribute needs to be +// reviewed by SA component driver +// [Files] NBDXEBoard.c; IntelSaGopSetup.c; IntelSaGopPolicy.c; +// NBDxe.c; NbPciCSP.c; PciHostBridge.c; +// +// 47 7/16/13 6:57a Jeffch +// [TAG] None +// [Severity] Improvement +// [Description] Remove same offset acpi device. +// [Files] NBDXE.c; +// +// 46 7/09/13 4:23a Ireneyang +// [TAG] EIP128014 +// [Category] BrugFix +// [Symptom] When populating PC3L DIMM x2 or upper DIMM slot only, +// DMI type17 has wrong values. +// [RootCause] When using Dimm with SPD funciton, there's no need to +// use when using memorydown way to get spd data. +// [Solution] Only when using memorydown Dimm needs to get SPD data. +// [Files] NBDxe.c; +// +// 45 5/24/13 6:21a Jeffch +// [TAG] None +// [Severity] BugFix +// [Description] Fix smbios type 17 data is incorrect for memory down +// system . +// [Files] NBDxe.c; +// +// 44 4/01/13 11:47p Ireneyang +// # [TAG] None +// [Severity] Improvement +// [Description] Reduce boot time through PEG. +// [Files] NB.mak; NBDxe.c; NBPEI.c; NBPPI.h; Sa.asl; +// PcieComplex.c; GraphicsInit.c; PciExpressInit.c; +// +// 43 3/15/13 1:56a Ireneyang +// [TAG] EIP118133 +// [Severity] BugFix +// [Description] Fix and restructure PlatformConfig setting of SA policy. +// [Files] NBDxe.c; GetSetupData.c; NbSetupData.h; +// +// 42 3/12/13 2:30a Ireneyang +// [TAG] None +// [Severity] Improvement +// [Description] Remove related SaSsdt acpi data to DSDT +// [Files] SaInit.c; INTELGFX.ASL; Sa.asl; SaSsdt.asl; +// SaSsdtTables.sdl; NBDxe.c; NB.mak; +// +// 41 3/07/13 2:20a Ireneyang +// [TAG] None +// [Severity] Bug Fix +// [Description] Intel Display Device disappear after S3 resume. +// [Files] NBDXE.c; +// +// 39 2/09/13 10:23a Jeffch +// [TAG] None +// [Severity] Spec update +// [Description] Update SA RC 1.1.0 +// [Files] NBPei.c; GetSetupData.c; NbSetupData.h; NBDXE.c; +// +// 38 1/28/13 5:53a Jeffch +// [TAG] None +// [Severity] Spec update +// [Description] Update SA RC 1.0. +// [Files] NBPei.c; GetSetupData.c; NbSetupData.h; NBDXE.c; +// NB.sd; NB.uni; NBDxeBoard.c +// +// 37 1/11/13 1:49a Jeffch +// [TAG] None +// [Severity] Bug Fix +// [Description] Fixed Peg error log init bug. +// [Files] NBDXE.c; +// +// 36 1/10/13 6:00a Jeffch +// [TAG] None +// [Severity] Bug Fix +// [Description] Fixed not program HDA codec for SaHDAVerbtable link bug. +// [Files] NBDXE.c; GetSetupData.c; NbSetupData.h +// +// 35 1/03/13 7:30a Jeffch +// [TAG] None +// [Severity] Improvement +// [Description] added SaHDAVerbtable link to OEM. +// [Files] NBDxe.c; NbSetupData.h; GetSetupData.c; +// +// 34 12/24/12 3:16a Jeffch +// [TAG] None +// [Category] Bug Fix +// [Description] fixed XTU not have create XMP GACI table. +// [Files] NBDxe.c; +// +// 33 12/24/12 3:06a Jeffch +// [TAG] None +// [Category] Bug Fix +// [Description] fixed XTU build fail issue. +// [Files] NBDxe.c; +// +// 32 12/24/12 2:55a Jeffch +// [TAG] None +// [Category] Improvement +// [Description] added ULT SKU auto disable PEG. +// [Files] NBPei.c; NBDxe.c; NbPlatform.h; NB.sd; +// [TAG] None +// [Category] Bug Fix +// [Description] Remove tRPab and fixed XTU build fail issue. +// [Files] NBPei.c; NBDxe.c; NB.sd; +// +// 31 12/22/12 2:28a Jeffch +// [TAG] None +// [Severity] Bug Fix +// [Description] Fxied anyway show Memory Timing default value. +// [Files] NBPei.c; +// +// 30 12/19/12 7:15a Jeffch +// [TAG] VddVoltage +// [Severity] Bug Fix +// [Description] Fixed show error Memory Voltage value. +// [Files] NBDxe.c; +// +// 29 12/18/12 5:14a Jeffch +// [TAG] None +// [Severity] Spec update +// [Description] Update SA RC 0.81. +// [Files] NBDxe.c; NBPei.c +// +// 28 12/14/12 5:29a Jeffch +// // [TAG] None +// // [Severity] Important +// // [Description] Show memory voltage. +// // [Files] NB.sd; NB.uni; NBDxe.c. +// +// 27 12/03/12 5:57a Jeffch +// [TAG] None +// [Category] Improvement +// [Description] optimize DetectNonComplaint function. +// [Description] NBPEI.c, NBPPI.h, NBDxe.c +// +// 2 11/29/12 3:41a Jeffch +// +// 26 11/29/12 2:32a Jeffch +// [TAG] None +// [Category] Improvement +// [Description] added bootime check IGFX Available. +// [Files] NBDxe.c; NbPlatform.h; NB.sd; +// +// 23 11/20/12 2:57a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Update SA RC 0.80. +// [Files] NBDxe.c; NBPei.c +// +// 22 11/14/12 5:38a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Update XTU4.x function +// [Files] NBPei.c; GetSetupData.c; NbSetupData.h; NBDXE.c; NB.sd; +// NB.uni +// +// 21 11/07/12 6:22a Jeffch +// [TAG] EIP106013 +// [Severity] Important +// [Description] Sound and image abnormal with HDMI. +// [Files] NBDxe.c; +// +// 20 10/30/12 7:02a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Update SA RC 0.72. +// [Files] NBDxe.c; NBPei.c +// +// 19 10/16/12 9:39a Jeffch +// [TAG] None +// [Severity] Important +// [Description] SA RC 0.71 for support ULT. +// [Files] NBDxe.c; +// +// 18 10/14/12 5:17a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Follow SA RC 0.71. +// [Files] NBPei.c, NBDxe.c; NBGeneric.c; NBCspLib.h; NBSetup.c; +// Nb.sd; GetSetupData.c +// +// 17 10/14/12 12:22a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Update by XTU4.0. +// [Files] NBPei.c, NBDxe.c, NBCspLib.h, NBGeneric.c +// [TAG] None +// [Severity] Important +// [Description] Follow Update by Mahobay. +// [Files] NBPei.c, NBDxe.c; +// +// 16 9/28/12 4:12a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] BDAT function support. +// [Files] NB.sd, NBDxe.c, NBPEI.c, SystemAgent.sdl, +// BdatAccessHandler.sdl +// +// 15 9/12/12 6:17a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Restore Performance Tuning the skip part +// [Files] NBDxe.c +// +// 14 8/31/12 2:32a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Update Board ID for Haswell platform. +// [Files] NBDxe.c +// +// 13 8/24/12 8:13a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Corrected GTT reference define. +// [Files] NBDxe.c, NBPEI.c +// +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Remove useless iME_SUPPORT. +// [Files] NBDxe.c +// +// 12 8/14/12 4:32a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Change for SystemAgent RefCode Revision: 0.6.1. +// [Files] NB.sdl, NB.sd, NBCSP.CIF, NBDxe.c, NB.ASL, SaAudio.asl +// +// 11 7/27/12 8:38a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] IGfx Fource Disable Support. +// [Files] GetSetupData.c, NB.sdl, NB.sd, NB.uni, NbSetupData.h, +// NBDxe.c, NBPEI.c +// +// [TAG] None +// [Category] Improvement +// [Description] Adjusted NB policy debault. +// [Files] NB.sd, NBDxe.c +// +// [TAG] None +// [Category] Improvement +// [Description] Change to before Dxe SaInit to set maximum payload. +// [Files] NBDxe.c +// +// 10 7/03/12 6:44a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Change for SystemAgent RefCode Revision: 0.6.0. +// [Files] NBPEI.DXS, NB.sd, NBDxe.c, NBPEI.c +// +// 9 7/03/12 6:39a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Change the Save/Restore NB Registers position. +// [Files] NB.ASL, NBAcpi.c, NBDxe.c +// +// 8 6/14/12 4:56a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Set Max Payload Size for EDS. +// [Description] NBDxe.c +// +// 7 6/14/12 4:55a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Fix some devices work abnormal in the PEG slot. +// [Description] NBDxe.c +// +// 6 4/26/12 2:52a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Adjust Intel System Agent module the Setup item and +// Policy. +// [Description] GetSetupData.c, NB.sdl, NB.sd, NB.uni, NBDxe.c, +// NBPEI.c, +// NBSetup.c, NBSetupReset.c, NbSetupData.h +// +// 5 4/05/12 5:45a Yurenlai +// [TAG] None +// [Category] New Feature +// [Severity] Normal +// [Description] Enabled GDXC feature. +// [Files] NBDxe.c, NBPEI.c +// +// 3 4/05/12 5:12a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Correct the Memory Info. +// [Files] NBDxe.c +// +// 2 4/05/12 2:34a Yurenlai +// [TAG] EIP87103 +// [Category] Spec Update +// [Severity] Important +// [Description] Change for SystemAgent RefCode Revision: 0.5.5 . +// [Files] NBDxe.c, NBPEI.c, NBSMI.C, NBGeneric.cm NB.sd, NBSetup.c, +// GetSetupData.c, NbSetupData.h +// +// 1 2/08/12 4:34a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: NBDXE.C +// +// Description: This file contains code for North Bridge initialization +// in the DXE stage +// +//<AMI_FHDR_END> +//************************************************************************* + +//---------------------------------------------------------------------------- +// Include(s) +//---------------------------------------------------------------------------- + +#include <Efi.h> +#include <Token.h> +#include <DXE.h> +#include <AmiDxeLib.h> +#include <AmiHobs.h> +#include <Setup.h> +#include <AmiCspLib.h> +#include <PciBus.h> +//#include "NbS3Save.h" +#include <Acpi20.h> +#include <AMIVfr.h> +#include <ppi\NBPPI.h> +// Consumed Protocols +#include <Protocol\PciRootBridgeIo.h> +#include <Protocol\NBPlatformData.h> + +#if ACPI_SUPPORT + #if defined(PI_SPECIFICATION_VERSION) && (PI_SPECIFICATION_VERSION >= 0x00010014) + #include <Protocol\AcpiSystemDescriptionTable.h> + #else + #include <Protocol\AcpiSupport.h> + #endif +#endif + +#define _SA_COMMON_DEFINITIONS_H_ +#include <Protocol\SaPlatformPolicy\SaPlatformPolicy.h> +#include <Protocol\AmiUsbController.h> +#include <SaDataHob\SaDataHob.h> +#include <Hob.h> +#include "MemInfoHob.h" +#include <Protocol\MemInfo\MemInfo.h> + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C +#include <PerfTune.h> +#include <Protocol\PerfTuneProtocol.h> +#endif +#endif + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 0 +#include <Protocol\Wdt\Wdt.h> +#endif + +#include <Protocol\PchS3Support\PchS3Support.h> + +#if NB_ERROR_LOG_SUPPORT +#include <Protocol\GenericElog.h> +#endif + +#include <Protocol\ConsoleControl.h> +#include <Protocol\SmBus.h> +#include <AmiLoadCsmPolicy.h> + +#include <SaGlobalNvsArea\SaGlobalNvsArea.h> +#include <Protocol\GlobalNvsArea\GlobalNvsArea.h> + +#ifndef EFI_SIGNATURE_16 +#define EFI_SIGNATURE_16(A, B) ((A) | (B << 8)) +#endif + +#ifndef EFI_SIGNATURE_32 +#define EFI_SIGNATURE_32(A, B, C, D) (EFI_SIGNATURE_16 (A, B) | (EFI_SIGNATURE_16 (C, D) << 16)) +#endif + +//---------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//---------------------------------------------------------------------------- +// Constant Definition(s) + +#ifndef SMM_SUPPORT + #define SMM_SUPPORT 0 +#endif + +#define NB_TEMP_PCI_BUS 0x10 + +// Macro Definition(s) + +// Type Definition(s) +typedef struct { + UINT8 Bus; + UINT8 Dev; + UINT8 Fun; + VOID *Process; +} DEVICES_AFTER_PCIIO; + + +#define RC_EFI_ACPI_VARIABLE_GUID \ + { \ + 0xc020489e, 0x6db2, 0x4ef2, 0x9a, 0xa5, 0xca, 0x6, 0xfc, 0x11, 0xd3, 0x6a \ + } + +#define EFI_PCI_ENUMERATION_COMPLETE_GUID \ + { \ + 0x30cfe3e7, 0x3de1, 0x4586, { 0xbe, 0x20, 0xde, 0xab, 0xa1, 0xb3, 0xb7, 0x93 } \ + } + +typedef struct { + /// + /// Acpi Related variables + /// + EFI_PHYSICAL_ADDRESS AcpiReservedMemoryBase; + UINT32 AcpiReservedMemorySize; + EFI_PHYSICAL_ADDRESS S3ReservedLowMemoryBase; + EFI_PHYSICAL_ADDRESS AcpiBootScriptTable; + EFI_PHYSICAL_ADDRESS RuntimeScriptTableBase; + EFI_PHYSICAL_ADDRESS AcpiFacsTable; + UINT64 SystemMemoryLength; + ACPI_CPU_DATA AcpiCpuData; + /// + /// VGA OPROM to support Video Re-POST for Linux S3 + /// + EFI_PHYSICAL_ADDRESS VideoOpromAddress; + UINT32 VideoOpromSize; + + /// + /// S3 Debug extension + /// + EFI_PHYSICAL_ADDRESS S3DebugBufferAddress; + EFI_PHYSICAL_ADDRESS S3ResumeNvsEntryPoint; +} RC_ACPI_VARIABLE_SET; + + +// Function Prototype(s) + +EFI_STATUS NBDXE_BoardInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable, + IN NB_SETUP_DATA *SetupData +); + +VOID NbInitAfterDeviceInstall ( + IN EFI_EVENT Event, + IN VOID *Context +); + +VOID InitNbRegsBeforeBoot ( + IN EFI_EVENT Event, + IN VOID *Context +); + +VOID InitRcAcpiVariableSet( + IN EFI_EVENT Event, + IN VOID *Context +); + +EFI_STATUS InstallNbMemoryInfo ( + IN EFI_SYSTEM_TABLE *SystemTable +); + +VOID CreateNbAcpiComponent ( VOID ); + +EFI_STATUS NbSmmInit ( + IN EFI_EVENT Event, + IN VOID *Context); + +#ifdef CSM_OPRROM_POLICY_GUID +VOID NbCheckOprom ( + IN EFI_EVENT Event, + IN VOID *Context +); +#endif + +VOID NbSetupNvramUpdatedCallback ( + IN EFI_EVENT Event, + IN VOID *Context +); + +VOID NbPciEnumerationCompleteProtocolCallback ( + IN EFI_EVENT Event, + IN VOID *Context +); + +VOID NbExitPmAuthProtocolCallback ( + IN EFI_EVENT Event, + IN VOID *Context +); + +EFI_STATUS InstallDxePlatformSaPolicy (VOID); + +EFI_STATUS +RmrrUpdateCallback ( + IN EFI_EVENT Event, + IN VOID *Context +); + +EFI_STATUS NBDXE_ShadowRam ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +); + +// (P20121012A) >> Update XTU 4.0 +EFI_STATUS NbReportXmpInfo( + IN EFI_EVENT Event, + IN VOID *Context +); + +typedef struct { + UINT32 tCK; + MrcFrequency DDRFreq; + UINT8 RefClkFlag; // 0 = invalid freq. 1 = valid only at 133 RefClk, 2 = valid only at 100 RefClk, 3 = valid at both. +} NbTRangeTable; + +typedef struct { + MrcFrequency DDRFreq; + MrcTiming TimingData; +} NbXmpProfileData; + +typedef struct { + NbXmpProfileData XmpProfileTiming[2]; +} XmpDimmData; + +//NbXmpProfileData XmpProfileTiming[2] = {0}; +//XmpDimmData XmpDimm[4] = {0}; +//XmpDimmData XmpChannel[2] = {0}; + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C +VOID NbXTUSetGACITable( + IN EFI_EVENT Event, + IN VOID *Context +); + +DDDT_PRESENT_FLAG_HOB *gDddtPresentFlagHob = NULL; +#endif +#endif +// (P20121012A) << Update XTU 4.0 +//---------------------------------------------------------------------------- +// Variable and External Declaration(s) +//---------------------------------------------------------------------------- +// Variable Declaration(s) + +EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *gPciRootBridgeIo = NULL; +AMI_S3_SAVE_PROTOCOL *gBootScript = NULL; +EFI_EVENT gEvent; +EFI_EVENT gEvtBootScript; +VOID *gNBInitNotifyReg = NULL; +VOID *gUpdateCsmProtocolNotifyReg = NULL; +NB_SETUP_DATA *gNbSetupData = NULL; +VOID *gCsmOpromReg = NULL; +VOID *gNbSetupNvramUpdatedReg = NULL; +VOID *gPciEnumerationCompleteProtocolReg = NULL; +VOID *gNbExitPmAuthProtocolReg = NULL; +VOID *gInterface = NULL; +MEM_INFO_PROTOCOL gMemInfoHobProtocol; +NB_PLATFORM_DATA NBPlatformData = {0}; +UINT32 gBClkFrequency = 0; +BOOLEAN gHideIGFXdevice; +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C +PERF_TUNE_ASL_PROTOCOL *gPerfTuneAslProtocol = NULL; +#endif +#endif +MrcProfile MemoryProfile = 0; +MrcTiming *NBMrcTimingData; + + +// GUID Definition(s) + +EFI_GUID gEfiPciRootBridgeIoProtocolGuid = \ + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID; +EFI_GUID gEfiPciIoProtocolGuid = EFI_PCI_IO_PROTOCOL_GUID; +EFI_GUID gSetupNvramUpdatedGuid = AMITSE_NVRAM_UPDATE_GUID; +EFI_GUID gHobListGuid = HOB_LIST_GUID; +//EFI_GUID gMrcS3ResumeDataHobGuid = AMI_MRC_S3_RESUME_DATA_HOB_GUID; +EFI_GUID gDxePlatformSaPolicyGuid = DXE_PLATFORM_SA_POLICY_GUID; +EFI_GUID gMemInfoProtocolGuid = MEM_INFO_PROTOCOL_GUID; +EFI_GUID gMemRestoreDataGuid = EFI_MEMORY_RESTORE_DATA_GUID; +EFI_GUID gAmiNbPegGen3PresetSearchGuid = AMI_NB_PEG_GEN3_PRESET_SEARCH_GUID; +EFI_GUID gMrcInfoHobGuid = AMI_MRC_INFO_HOB_GUID; +EFI_GUID gSetupGuid = SETUP_GUID; +EFI_GUID gAmiLoadCsmGuid = AMI_LOAD_CSM_GUID; +EFI_GUID gConOutStartedCheckGuid = CONSOLE_OUT_DEVICES_STARTED_PROTOCOL_GUID; +EFI_GUID gExitPmAuthProtocolGuid = EXIT_PM_AUTH_PROTOCOL_GUID; +EFI_GUID gEfiSmbusProtocolGuid = EFI_SMBUS_HC_PROTOCOL_GUID; +EFI_GUID gAmiNbPegInfoGuid = AMI_NB_PEG_INFO_GUID; +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C +EFI_GUID gPerfTuneAslProtocolGuid = PERF_TUNE_ASL_PROTOCOL_GUID; +EFI_GUID gAmiPerfTuneDataHobGuid = AMI_PERF_TUNE_DATA_HOB_GUID; +EFI_GUID gAmiInternalFactoryTdcTdpHobGuid = AMI_INTERNAL_FACTORY_TDC_TDP_HOB_GUID; +#endif +#endif + +#ifdef CSM_OPRROM_POLICY_GUID +EFI_GUID gCsmOpromPolicyGuid = CSM_OPRROM_POLICY_GUID; +#endif + +#if NB_ERROR_LOG_SUPPORT +EFI_GUID gElogProtocolGuid = EFI_SM_ELOG_PROTOCOL_GUID; +#endif + +extern EFI_GUID gSaDataHobGuid; +extern EFI_GUID gEfiSmmAccessProtocolGuid; + +#if (CORE_VERSION >= 4600) +//---------------------------------------------------------------------------- +//THIS TABLE MUST BE FILLED WITH RESOURCE REGIONS DECODED BY THE NB FOR ITSELF +//!!! NOTE :Use Attributes field == -1 to mark an IO Space Resource. +// you must provide valid attributes for Memory Mapped IO regions. +//---------------------------------------------------------------------------- + +CSP_RES_ITEM gNbCspResTable[] = { +//---------------------------------------------------------------------------- +// UINT64 ResBase UINTN ResLength GCD_MEMORY_TYPE ResType UINT64 Attributes +//---------------------------------------------------------------------------- +//Add PCI Express region +{ PCIEX_BASE_ADDRESS, PCIEX_LENGTH,EfiGcdMemoryTypeMemoryMappedIo , \ + (EFI_MEMORY_UC|EFI_MEMORY_RUNTIME)}, +//Local APICs dedicated Space +{ LOCAL_APIC_BASE , 0x00001000 ,EfiGcdMemoryTypeMemoryMappedIo , \ + (EFI_MEMORY_UC|EFI_MEMORY_RUNTIME)}, +//Egress Port Base Address Region +{ NB_EP_BASE_ADDRESS, 4*1024 ,EfiGcdMemoryTypeMemoryMappedIo , \ + EFI_MEMORY_UC}, +//MCH Memory Mapped Base Address Region +{ NB_MCH_BASE_ADDRESS, 16*1024 ,EfiGcdMemoryTypeMemoryMappedIo , \ + EFI_MEMORY_UC}, +//Root Complex Base Address Region +{ NB_DMI_BASE_ADDRESS, 4*1024 ,EfiGcdMemoryTypeMemoryMappedIo , \ + EFI_MEMORY_UC}, +//Edram Base Address Region +{ NB_DERAM_BASE_ADDRESS, 16*1024 ,EfiGcdMemoryTypeMemoryMappedIo , \ + EFI_MEMORY_UC}, +//GDXC Base Address Region +{ NB_GDXC_BASE_ADDRESS, 4*1024 ,EfiGcdMemoryTypeMemoryMappedIo , \ + EFI_MEMORY_UC}, +//Here Goes Reserved IO Space +//IO Used for PCI Config access +{ NB_PCICFG_SPACE_INDEX_REG , 8 ,EfiGcdIoTypeIo , -1 }, + +}; + +UINTN gNbCspResCount = sizeof(gNbCspResTable) / sizeof(CSP_RES_ITEM); + +#endif + + +DEVICES_AFTER_PCIIO gDevicesTable[] = { + { PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, NULL }, + { PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN1, NULL }, + { PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN2, NULL }, + { 0xFF, 0xFF, 0xFF, NULL } +}; + +UINTN gEventCount = sizeof(gDevicesTable) / sizeof(DEVICES_AFTER_PCIIO); + +PCIE_ASPM_DEV_INFO mPcieAspmDevsOverride[] = { + /// + /// Tekoa w/o iAMT + /// + {0x8086, 0x108b, 0xff, 2, 2}, + /// + /// Tekoa A2 + /// + {0x8086, 0x108c, 0x00, 0, 0}, + /// + /// Tekoa others + /// + {0x8086, 0x108c, 0xff, 2, 2}, + /// + /// Vidalia + /// + {0x8086, 0x109a, 0xff, 2, 2}, + /// + /// 3945ABG + /// + {0x8086, 0x4222, 0xff, 2, 3}, + /// + /// 3945ABG + /// + {0x8086, 0x4227, 0xff, 2, 3}, + /// + /// 3945ABG + /// + {0x8086, 0x4228, 0xff, 2, 3}, + /// + /// End of table + /// + {SA_PCIE_DEV_END_OF_TABLE, 0, 0, 0, 0} +}; + +PCIE_LTR_DEV_INFO mPcieLtrDevsOverride[] = { + /// + /// Place holder for PCIe devices with correct LTR requirements + /// + /// + /// End of table + /// + {SA_PCIE_DEV_END_OF_TABLE, 0, 0, 0, 0} +}; +// Protocol Definition(s) + +// External Declaration(s) + +// Function Definition(s) + +//---------------------------------------------------------------------------- + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBDXE_Init +// +// Description: This function is the entry point for this DXE. This function +// initializes the chipset NB before PCI Bus enumeration. +// +// Input: ImageHandle - Image handle +// SystemTable - Pointer to the system table +// +// Output: Return Status based on errors that occurred while waiting for +// time to expire. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBDXE_Init ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status = EFI_SUCCESS; + CPUINFO_HOB *CpuInfoHob = NULL; + EFI_GUID AmiCpuinfoHobGuid = AMI_CPUINFO_HOB_GUID; + UINT8 i = 0; + UINTN VariableSize; + EFI_EVENT Event; + VOID *HobData; + VOID *VariableData; + UINTN S3DataOffset; + UINT16 McDeviceId; + UINT16 LpcDeviceId; + VOID *Protocol = NULL; + VOID *NotifyReg = NULL; + UINT32 Attributes = 0; // [ EIP167027 ] + + + InitAmiLib(ImageHandle, SystemTable); + + PROGRESS_CODE (DXE_NB_INIT); + + Status = pBS->LocateProtocol( &gEfiPciRootBridgeIoProtocolGuid, \ + NULL, \ + &gPciRootBridgeIo ); + ASSERT_EFI_ERROR(Status); + + Status = pBS->LocateProtocol( AMI_S3_SAVE_PROTOCOL_GUID, \ + NULL, \ + &gBootScript ); + ASSERT_EFI_ERROR(Status); + + VariableData = NULL; + S3DataOffset = 0; + + HobData = (EFI_HOB_GENERIC_HEADER *) GetEfiConfigurationTable (pST, &gHobListGuid); + if (!HobData)ASSERT_EFI_ERROR (EFI_NOT_FOUND); + + Status = FindNextHobByGuid (&gSaDataHobGuid, &HobData); + if (Status == EFI_SUCCESS) { + + // Use the hob to save PegGen3PresetSearch Configuration Data + S3DataOffset = (UINTN) &(((SA_DATA_HOB *) 0)->PegData); + + //Status = pRS->SetVariable ( // [ EIP167027 ] + // L"PegGen3PresetSearchData", + // &gAmiNbPegGen3PresetSearchGuid, + // (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS), + // sizeof(SA_PEG_DATA), + // (UINT8 *) HobData + S3DataOffset + // ); + Status = pRS->SetVariable ( + L"PegGen3PresetSearchData", + &gAmiNbPegGen3PresetSearchGuid, + (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS), + sizeof(SA_PEG_DATA), + (UINT8 *) HobData + S3DataOffset + ); + ASSERT_EFI_ERROR(Status); + + } + + HobData = (EFI_HOB_GENERIC_HEADER *) GetEfiConfigurationTable (pST, &gHobListGuid); + if (!HobData)ASSERT_EFI_ERROR (EFI_NOT_FOUND); + + Status = FindNextHobByGuid (&gMemRestoreDataGuid, &HobData); + if (Status == EFI_SUCCESS) { + + // Use the hob to save Memory Configuration Data + S3DataOffset = (UINTN) &(((HOB_SAVE_MEMORY_DATA *) 0)->MrcData.SysSave); + + //Status = pRS->SetVariable ( // [ EIP167027 ] + // L"MrcS3Resume", + // &gMemRestoreDataGuid, + // (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS), + // sizeof(SysSave), + // (UINT8 *) HobData + S3DataOffset + // ); + Status = pRS->SetVariable ( + L"MrcS3Resume", + &gMemRestoreDataGuid, + (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS), + sizeof(SysSave), + (UINT8 *) HobData + S3DataOffset + ); + ASSERT_EFI_ERROR(Status); + + } + + // Set DRAM Initialization Bit. // [ EIP161790 ] + if ((READ_PCI8_SB(SB_REG_GEN_PMCON_2) & BIT07) == 0) + { + SET_PCI8_SB(SB_REG_GEN_PMCON_2, BIT07); // 0xA2 + } + + // Read the NB Setup Data + VariableSize = sizeof (NB_SETUP_DATA); + Status = pBS->AllocatePool( EfiBootServicesData, \ + VariableSize, \ + &gNbSetupData ); + ASSERT_EFI_ERROR(Status); + + GetNbSetupData( pRS, gNbSetupData, FALSE ); + + // Read the NB Platform Data + VariableSize = sizeof (NB_PLATFORM_DATA); + //Status = pRS->GetVariable ( // [ EIP167027 ] + // L"NBPlatformData", + // &gSetupGuid, + // NULL, + // &VariableSize, + // &NBPlatformData + // ); + Status = pRS->GetVariable ( + L"NBPlatformData", + &gSetupGuid, + &Attributes, + &VariableSize, + &NBPlatformData + ); + if (EFI_ERROR(Status)) + Attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS; + + // Check CPU is Support IGFX. + NBPlatformData.IGFXCapability = (READ_PCI32_NB (R_SA_MC_CAPID0_A_OFFSET) & BIT11) ? FALSE : TRUE; + + NBPlatformData.PegAvailable = (GetPchSeries() == PchLp) ? FALSE : TRUE; + // Check IGFX is Available. + NBPlatformData.IGFXAvailable = (READ_PCI32_IGD (R_SA_IGD_VID) != 0xFFFFFFFF) ? TRUE : FALSE; + +#if defined NB_IGFX_FORCE_DISABLE_SUPPORT && NB_IGFX_FORCE_DISABLE_SUPPORT == 1 + if(gNbSetupData->IGfxForceDisable == 1) + NBPlatformData.IGFXAvailable = 0; +#endif // NB_IGFX_FORCE_DISABLE_SUPPORT + + // Read MC device ID + McDeviceId = READ_PCI16_NB(R_SA_MC_DEVICE_ID); + + // Read PCH device ID + LpcDeviceId = READ_PCI16_SB(R_PCH_LPC_DEVICE_ID); + + NBPlatformData.PresentCPU = 2; + + // Mobile - 0; Desktop - 2; UpServer - 3; FlavorWorkStation - 4; + if(IS_SA_DEVICE_ID_MOBILE(McDeviceId)) { + NBPlatformData.UserBoard = FlavorMobile; + } else if(IS_SA_DEVICE_ID_DESKTOP (McDeviceId) | IS_SA_DEVICE_ID_SERVER(McDeviceId)) { + if(IS_PCH_LPT_LPC_DEVICE_ID_WS (LpcDeviceId)) { + NBPlatformData.UserBoard = FlavorWorkStation; + } else if(IS_PCH_LPT_LPC_DEVICE_ID_SERVER (LpcDeviceId)) { + NBPlatformData.UserBoard = FlavorUpServer; + } else { + NBPlatformData.UserBoard = FlavorDesktop; + } + } else { + NBPlatformData.UserBoard = FlavorDesktop; + } + + Status = NBDXE_BoardInit(ImageHandle, SystemTable, gNbSetupData); + + // + // Detect if CSM is exist. If it's not, the shawdow ram can be set. + // + Status = pBS->LocateProtocol( &gAmiLoadCsmGuid, \ + NULL, \ + &gInterface ); + if(EFI_ERROR(Status)) + { + Status = NBDXE_ShadowRam(ImageHandle, SystemTable); + } + +#if PciHostBridge_SUPPORT + CreateNbAcpiComponent(); +#endif + + Status = RegisterProtocolCallback( &gEfiPciIoProtocolGuid, \ + NbInitAfterDeviceInstall, \ + NULL, &gEvent, &gNBInitNotifyReg ); + ASSERT_EFI_ERROR(Status); + + Status = RegisterProtocolCallback( &gConOutStartedCheckGuid, + NbPciEnumerationCompleteProtocolCallback, + NULL, &gEvent, &gPciEnumerationCompleteProtocolReg ); + ASSERT_EFI_ERROR(Status); + + Status = RegisterProtocolCallback( &gExitPmAuthProtocolGuid, \ + NbExitPmAuthProtocolCallback, \ + NULL, \ + &Event, \ + &gNbExitPmAuthProtocolReg ); + ASSERT_EFI_ERROR(Status); + + Status = CreateReadyToBootEvent( TPL_NOTIFY, InitNbRegsBeforeBoot, \ + NULL, &gEvent ); + ASSERT_EFI_ERROR(Status); + + Status = CreateReadyToBootEvent( + (TPL_CALLBACK - 1), + InitRcAcpiVariableSet, + NULL, + &Event); + ASSERT_EFI_ERROR(Status); + + Status = InstallDxePlatformSaPolicy (); + ASSERT_EFI_ERROR(Status); + + Status = InstallNbMemoryInfo ( SystemTable ); + ASSERT_EFI_ERROR(Status); + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C + if(!EFI_ERROR(Status)) + { + EFI_EVENT Event; + VOID *Reg; + + Status = pBS->LocateProtocol (&gPerfTuneAslProtocolGuid, NULL, &gPerfTuneAslProtocol); + if(Status == EFI_SUCCESS) + { + NbXTUSetGACITable(NULL,NULL); + }else{ + //Create event for Notify XTU setting + Status = RegisterProtocolCallback( + &gPerfTuneAslProtocolGuid, + NbXTUSetGACITable, + NULL, &Event, &Reg); + ASSERT_EFI_ERROR(Status); + } + } +#endif +#endif + +#ifdef CSM_OPRROM_POLICY_GUID + Status = RegisterProtocolCallback( &gCsmOpromPolicyGuid, \ + NbCheckOprom, \ + NULL, \ + &Event, \ + &gCsmOpromReg ); + + ASSERT_EFI_ERROR(Status); +#endif + + Status = RegisterProtocolCallback( &gSetupNvramUpdatedGuid, + NbSetupNvramUpdatedCallback, + NULL, + &Event, + &gNbSetupNvramUpdatedReg ); + +#if (CORE_VERSION >= 4600) + Status = LibAllocCspResource( gNbCspResTable, \ + gNbCspResCount, \ + ImageHandle, \ + SystemTable ); +#endif + +#if SMM_SUPPORT + Status = pBS->LocateProtocol(&gEfiSmmAccessProtocolGuid, NULL, &Protocol); + if (EFI_ERROR(Status)) + { + Status = RegisterProtocolCallback( + &gEfiSmmAccessProtocolGuid, + NbSmmInit, + NULL, + &Event, + &NotifyReg); + ASSERT_EFI_ERROR(Status); + } + else + { + Status = NbSmmInit(NULL, NULL); + ASSERT_EFI_ERROR(Status); + } +#endif + +#ifndef OVERRIDE_FOR_SET_MAX_PAYLOAD + { + UINTN PegAddress; + UINT8 PegBus; + UINT8 PegDev; + UINT8 PegFun; + UINTN i; + + for ( i = 0; gDevicesTable[i].Bus != 0xff; i++) + { + PegBus = gDevicesTable[i].Bus; + PegDev = gDevicesTable[i].Dev; + PegFun = gDevicesTable[i].Fun; + + if (READ_PCI32 (PegBus, PegDev, PegFun, PCI_VID) == 0xFFFFFFFF) continue; + + // Haswell EDS 2.19.35 + // Default indicates 256B max supported payload for + // Transaction Layer Packets (TLP) for x16 PEG only. + // x8 and x4 PEG are limited to 128B support. + PegAddress = NB_PCIE_CFG_ADDRESS(PegBus, PegDev, PegFun, 0); + if (((READ_MMIO16 (PegAddress + R_SA_PEG_LSTS_OFFSET) & 0x01F0) >> 4) != 0x10) + RESET_MMIO8 (PegAddress + R_SA_PEG_DCAP_OFFSET, BIT0 + BIT1 + BIT2); + } + } +#endif // OVERRIDE_FOR_SET_MAX_PAYLOAD + + // Save SETUP variables. + //Status = pRS->SetVariable ( // [ EIP167027 ] + // L"NBPlatformData", + // &gSetupGuid, + // EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, + // sizeof (NB_PLATFORM_DATA), + // &NBPlatformData + // ); + Status = pRS->SetVariable ( + L"NBPlatformData", + &gSetupGuid, + Attributes, + sizeof (NB_PLATFORM_DATA), + &NBPlatformData + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitNbRegsBeforeBoot +// +// Description: This function can initialize any NB registers before DXE +// stage exiting. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID InitNbRegsBeforeBoot ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ +//#if defined Remove_SaSsdt_Data_To_Dsdt && Remove_SaSsdt_Data_To_Dsdt + UINT32 Index; + EFI_ACPI_SUPPORT_PROTOCOL *As; + FACP_20 *Table = NULL; + EFI_ACPI_TABLE_VERSION Version; + UINTN Handle; + ACPI_HDR *DsdtPtr = NULL; + EFI_STATUS Status; + ASL_OBJ_INFO ObjInfo; + UINT16 ASLDeviceOP; + UINT8 ASLDeviceOPLength; + UINT8 *ptr; + UINT8 i; + UINT8 j; +#if defined Remove_SaSsdt_Data_To_Dsdt && Remove_SaSsdt_Data_To_Dsdt + UINT8 *GlobalSaptr, *SAptr; + SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL *SaGlobalNvsArea, *GlobalSaNvsArea; + EFI_GUID gSaGlobalNvsAreaProtocolGuid = SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL_GUID; + EFI_GUID gEfiGlobalSaNvsAreaProtocolGuid = EFI_GLOBAL_SANVS_AREA_PROTOCOL_GUID; +#endif + UINT8 *ptr1; + UINT16 PXSXASLDeviceOP; + UINT8 PXSXASLDeviceOPLength; + UINT8 HPMEASLMethodOPLength; + UINT16 HPMEASLMethodOPLength16; + UINT16 ASLDeviceOPLength16; + UINT32 *Signature; + +#if NB_ERROR_LOG_SUPPORT == 1 +#if NB_ECC_ERROR_LOG_SUPPORT == 1 + + if(gNbSetupData->EccSupport) { + + if (((READ_MEM32_MCH(0x5004) & (BIT24 | BIT25)) != 0) || + ((READ_MEM32_MCH(0x5008) & (BIT24 | BIT25)) != 0)) + { + RW_MEM32_MCH(0x40B8, 0, (BIT14 | BIT16 | BIT17)); + RW_MEM32_MCH(0x44B8, 0, (BIT14 | BIT16 | BIT17)); + + // Disable Error and SCI Commands + RW_PCI16_NB(0xCA, 0, (BIT00 | BIT01)); + RW_PCI16_NB(0xCE, 0, (BIT00 | BIT01)); + + // Enable SMI Command + //SET_PCI8_NB(0xC8, BIT00); + RW_PCI16_NB(0xCC, (BIT00 | BIT01), 0); + } + + } + +#endif +#endif + +#if defined Remove_SaSsdt_Data_To_Dsdt && Remove_SaSsdt_Data_To_Dsdt + /// + /// Locate the SA SSDT NVS Protocol. + /// + Status = pBS->LocateProtocol ( + &gSaGlobalNvsAreaProtocolGuid, + NULL, + &SaGlobalNvsArea + ); + ASSERT_EFI_ERROR (Status); + + // + // Locate the SA Global NVS Protocol. + // + Status = pBS->LocateProtocol ( + &gEfiGlobalSaNvsAreaProtocolGuid, + NULL, + &GlobalSaNvsArea + ); + ASSERT_EFI_ERROR (Status); + + // Update SA SSDT GNVS data to Global DSDT SA GNVS + SAptr = (UINT8*)(SaGlobalNvsArea->Area); + GlobalSaptr = (UINT8*)(GlobalSaNvsArea->Area); + TRACE((TRACE_ALWAYS, "Global SA GNVS PTR=0x%08X, SA SSDT GNVS PTR=0x%08X\n", GlobalSaptr, SAptr)); + + for (Index = 0; Index < sizeof (SYSTEM_AGENT_GLOBAL_NVS_AREA); Index++) { + *(UINT8*)(GlobalSaptr + Index) = (UINT8)*(UINT8*)(SAptr + Index); + } + +#endif + + // It must be only one instance of such protocol + Status = pBS->LocateProtocol(&gEfiAcpiSupportGuid, NULL, &As); + if(EFI_ERROR(Status)) { + TRACE((-1, "ACPI Support Protocol is not ready for NB components\n")); + return; + } + TRACE((-1,"NB Locate Protocol(ACPISupport)- %r Success\n", Status)); + + // Find DSDT ACPI Table + for (Index = 0; Index < ACPI_RSDT_TABLE_NUM; Index++) { + Status = As->GetAcpiTable(As, Index, &Table, &Version, &Handle); + if (EFI_ERROR(Status)) break;//no more tables left + if ((Table->Header.Signature == FACP_SIG) && (DsdtPtr == NULL)) { + DsdtPtr = (ACPI_HDR*)Table->DSDT; + + TRACE((-1, "NBDxe: Found DSDT Table at 0x%08X\n", DsdtPtr)); + + + break; + } + } + + Status = GetAslObj( (UINT8*)(DsdtPtr + 1), DsdtPtr->Length - sizeof(ACPI_HDR) - 1, + "P0P2", otDevice, &ObjInfo ); + + if (!EFI_ERROR(Status)) + { + ptr = (UINT8*)(ObjInfo.DataStart) - 7; + (UINT16)ASLDeviceOP = *(UINT32*)(ptr); + (UINT8)ASLDeviceOPLength = *(UINT32*)(ptr + 2); + + TRACE((TRACE_ALWAYS, "SA POP2 Device PTR=0x%08X, ASLDeviceOP=0x%X, ASLDeviceOPLength=0x%X\n", ptr, (UINT16)ASLDeviceOP, (UINT8)ASLDeviceOPLength)); + if (ASLDeviceOP == 0x825B) // Is DeviceOP ? + { + for ( i = 0; i < ASLDeviceOPLength + 2; i++) { + *(UINT8*)(ptr + i) = 0; + } + } + } + + Status = GetAslObj( (UINT8*)(DsdtPtr + 1), DsdtPtr->Length - sizeof(ACPI_HDR) - 1, + "P0PA", otDevice, &ObjInfo ); + + if (!EFI_ERROR(Status)) + { + ptr = (UINT8*)(ObjInfo.DataStart) - 7; + (UINT16)ASLDeviceOP = *(UINT32*)(ptr); + (UINT8)ASLDeviceOPLength = *(UINT32*)(ptr + 2); + + TRACE((TRACE_ALWAYS, "SA POPA Device PTR=0x%08X, ASLDeviceOP=0x%X, ASLDeviceOPLength=0x%X\n", ptr, (UINT16)ASLDeviceOP, (UINT8)ASLDeviceOPLength)); + if (ASLDeviceOP == 0x825B) // Is ASL DeviceOP ? + { + for ( i = 0; i < ASLDeviceOPLength + 2; i++) { + *(UINT8*)(ptr + i) = 0; + } + } + } + + Status = GetAslObj( (UINT8*)(DsdtPtr + 1), DsdtPtr->Length - sizeof(ACPI_HDR) - 1, + "P0PB", otDevice, &ObjInfo ); + + if (!EFI_ERROR(Status)) + { + ptr = (UINT8*)(ObjInfo.DataStart) - 7; + (UINT16)ASLDeviceOP = *(UINT32*)(ptr); + (UINT8)ASLDeviceOPLength = *(UINT32*)(ptr + 2); + + TRACE((TRACE_ALWAYS, "SA POPB Device PTR=0x%08X, ASLDeviceOP=0x%X, ASLDeviceOPLength=0x%X\n", ptr, (UINT16)ASLDeviceOP, (UINT8)ASLDeviceOPLength)); + if (ASLDeviceOP == 0x825B) // Is ASL DeviceOP ? + { + for ( i = 0; i < ASLDeviceOPLength + 2; i++) { + *(UINT8*)(ptr + i) = 0; + } + } + } + + if (GetPchSeries() == PchLp) { + if(gNbSetupData->PrimaryDisplay == 4) { + + Status = GetAslObj( (UINT8*)(DsdtPtr + 1), DsdtPtr->Length - sizeof(ACPI_HDR) - 1, + "RP05", otDevice, &ObjInfo ); + if (!EFI_ERROR(Status)) + { + ptr = (UINT8*)(ObjInfo.DataStart) - 8; + (UINT16)ASLDeviceOP = *(UINT32*)(ptr); + (UINT8)ASLDeviceOPLength = *(UINT32*)(ptr + 2); + ASLDeviceOPLength16 = (ASLDeviceOPLength & 0x0F); + (UINT8)ASLDeviceOPLength = *(UINT32*)(ptr + 3); + ASLDeviceOPLength16 = (ASLDeviceOPLength << 4) | ASLDeviceOPLength16; + + TRACE((TRACE_ALWAYS, "RP05 Device PTR=0x%08X, ASLDeviceOP=0x%X, ASLDeviceOPLength=0x%X\n", ptr, (UINT16)ASLDeviceOP, (UINT16)ASLDeviceOPLength16)); + if (ASLDeviceOP == 0x825B) // Is ASL DeviceOP ? + { + Status = GetAslObj( (UINT8*)(ptr + 1), ASLDeviceOPLength16 - sizeof(ACPI_HDR) - 1, + "_STA", otMethod, &ObjInfo ); + if (!EFI_ERROR(Status)) + { + ptr1 = (UINT8*)(ObjInfo.DataStart) - 5; + TRACE((TRACE_ALWAYS, "_STA Method PTR=0x%08X\n", ptr1)); + *(UINT8*)ptr1 = 'X'; + } + + //remove device PXSX + Status = GetAslObj( (UINT8*)(ptr + 1), ASLDeviceOPLength16 - sizeof(ACPI_HDR) - 1, + "PXSX", otDevice, &ObjInfo ); + if (!EFI_ERROR(Status)) + { + + ptr1 = (UINT8*)(ObjInfo.DataStart) - 7; + (UINT16)PXSXASLDeviceOP = *(UINT32*)(ptr1); + (UINT8)PXSXASLDeviceOPLength = *(UINT32*)(ptr1 + 2); + TRACE((TRACE_ALWAYS, "PXSX Device PTR=0x%08X, ASLDeviceOP=0x%X, ASLDeviceOPLength=0x%X\n", ptr1, (UINT16)PXSXASLDeviceOP, (UINT8)PXSXASLDeviceOPLength)); + + if (PXSXASLDeviceOP == 0x825B) // Is ASL DeviceOP ? + { + for ( i = 0; i < PXSXASLDeviceOPLength + 2; i++) { + *(UINT8*)(ptr1 + i) = 0; + } + } + } + + Status = GetAslObj( (UINT8*)(ptr + 1), ASLDeviceOPLength16 - sizeof(ACPI_HDR) - 1, + "HPME", otMethod, &ObjInfo ); + if (!EFI_ERROR(Status)) + { + ptr1 = (UINT8*)(ObjInfo.DataStart) - 8; + (UINT8)HPMEASLMethodOPLength = *(UINT32*)(ptr1 + 1); + HPMEASLMethodOPLength16 = (HPMEASLMethodOPLength & 0x0F); + (UINT8)HPMEASLMethodOPLength = *(UINT32*)(ptr1 + 2); + HPMEASLMethodOPLength16 = (HPMEASLMethodOPLength << 4) | HPMEASLMethodOPLength16; + TRACE((TRACE_ALWAYS, "HPME Method PTR=0x%08X,HPMEASLMethodOPLength16=0x%X\n", ptr1,(UINT16)HPMEASLMethodOPLength16)); + + for ( i = 0; i < HPMEASLMethodOPLength16 ; i++) { + Signature = (UINT32 *) (ptr1 + i); + //TRACE((TRACE_ALWAYS, "PXSX Notify PTR%d = 0x%08X\n", i,Signature)); + if(*Signature == EFI_SIGNATURE_32 ('P', 'X', 'S', 'X')){ + TRACE((TRACE_ALWAYS, "PXSX Notify PTR = 0x%08X\n", Signature)); + for ( j = 0; j < 7 ; j++) { + *(UINT8*)(ptr1 + i + j -1) = 0; + } + } + } + } + + + } + } + }// if(gNbSetupData->PrimaryDisplay == 4) { + }//if (GetPchSeries() == PchLp) + + //Kill the Event + pBS->CloseEvent(Event); + +} + +VOID InitRcAcpiVariableSet( + IN EFI_EVENT Event, + IN VOID *Context) +{ + EFI_STATUS Status; + EFI_GUID mEfiAcpiVariableGuid = EFI_ACPI_VARIABLE_GUID; + EFI_GUID mRcEfiAcpiVariableGuid = RC_EFI_ACPI_VARIABLE_GUID; + ACPI_VARIABLE_SET *pAcpiVariableSet = NULL; + RC_ACPI_VARIABLE_SET *pRcAcpiVariableSet = NULL; + UINTN VariableSize = sizeof(UINT32); + UINT32 Attributes; + + //Status = pRS->GetVariable ( // [ EIP167027 ] + // L"AcpiGlobalVariable", + // &mEfiAcpiVariableGuid, + // NULL, + // &VariableSize, + // &pAcpiVariableSet + // ); + Status = pRS->GetVariable ( + L"AcpiGlobalVariable", + &mEfiAcpiVariableGuid, + &Attributes, + &VariableSize, + &pAcpiVariableSet + ); + if (EFI_ERROR(Status)) + { + return; + } + + Status = pBS->AllocatePool( + EfiACPIMemoryNVS, + sizeof(RC_ACPI_VARIABLE_SET), + &pRcAcpiVariableSet + ); + ASSERT_EFI_ERROR(Status); + + pBS->SetMem(pRcAcpiVariableSet, sizeof(RC_ACPI_VARIABLE_SET), 0); + + pRcAcpiVariableSet->AcpiReservedMemoryBase = pAcpiVariableSet->AcpiReservedMemoryBase; + pRcAcpiVariableSet->AcpiReservedMemorySize = pAcpiVariableSet->AcpiReservedMemorySize; + pRcAcpiVariableSet->S3ReservedLowMemoryBase = pAcpiVariableSet->S3ReservedLowMemoryBase; + pRcAcpiVariableSet->AcpiBootScriptTable = pAcpiVariableSet->AcpiBootScriptTable; + pRcAcpiVariableSet->RuntimeScriptTableBase = pAcpiVariableSet->RuntimeScriptTableBase; + pRcAcpiVariableSet->AcpiFacsTable = pAcpiVariableSet->AcpiFacsTable[0]; + pRcAcpiVariableSet->SystemMemoryLength = pAcpiVariableSet->SystemMemoryLength; + pRcAcpiVariableSet->AcpiCpuData = pAcpiVariableSet->AcpiCpuData; + + //Status = pRS->SetVariable( // [ EIP167027 ] + // L"AcpiGlobalVariable", + // &mRcEfiAcpiVariableGuid, + // EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, + // sizeof(UINT64), + // &pRcAcpiVariableSet + // ); + Status = pRS->SetVariable( + L"AcpiGlobalVariable", + &mRcEfiAcpiVariableGuid, + Attributes, + sizeof(UINT64), + &pRcAcpiVariableSet + ); + ASSERT_EFI_ERROR(Status); + + //Kill the Event + Status = pBS->CloseEvent(Event); + ASSERT_EFI_ERROR(Status); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetExtCapStrucAddr +// +// Description: This routine is called to get the 16-bit offset of a +// structure which can be located using the PCI Extended +// Capabilities Pointer mechanism. +// +// Input: Bus - The PCI bus number of the PCI device. +// Dev - The PCI device number of the PCI device. +// Fun - The PCI function number of the PCI device. +// FindCapNo - The Extended Capability ID to be found. +// CapPtr16 - The offset address of desired structure +// +// Output: EFI_STATUS +// EFI_NOT_FOUND - The desired structure is not found. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS GetExtCapStrucAddr ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 FindCapNo, + OUT UINT16 *CapPtr16 ) +{ + UINT32 Buffer32; + + *CapPtr16 = 0x100; + + Buffer32 = READ_PCI32(Bus, Dev, Fun, *CapPtr16); + while (Buffer32 != 0xffffffff) { + if ((UINT16)Buffer32 == FindCapNo) return EFI_SUCCESS; + *CapPtr16 = (UINT16)((Buffer32 >> 20) & 0xfffc); + if (*CapPtr16 == 0) break; + Buffer32 = READ_PCI32(Bus, Dev, Fun, *CapPtr16); + } + return EFI_NOT_FOUND; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetLegCapStrucAddr +// +// Description: This routine is called to get the 16-bit offset of a +// structure which can be located using the PCI Legacy +// Capabilities Pointer mechanism. +// +// Input: Bus - The PCI bus number of the PCI device. +// Dev - The PCI device number of the PCI device. +// Fun - The PCI function number of the PCI device. +// FindCapNo - The Legacy Capability ID to be found. +// CapPtr16 - The offset address of desired structure +// +// Output: EFI_STATUS +// EFI_NOT_FOUND - The desired structure is not found. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS GetLegCapStrucAddr ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT8 FindCapNo, + OUT UINT16 *CapPtr16 ) +{ + UINT8 Buffer8; + + if (READ_PCI32(Bus, Dev, Fun, PCI_VID) != 0xffffffff) { + if (READ_PCI16(Bus, Dev, Fun, 6) & 0x10) { + *CapPtr16 = ((READ_PCI8(Bus, Dev, Fun, 14) & 0x7f) == 2) ? \ + 0x14:0x34; + *CapPtr16 = (UINT16)READ_PCI8(Bus, Dev, Fun, *CapPtr16); + if (*CapPtr16 == 0) return EFI_NOT_FOUND; + Buffer8 = READ_PCI8(Bus, Dev, Fun, *CapPtr16); + while (Buffer8 != 0) { + if (Buffer8 == FindCapNo) return EFI_SUCCESS; + Buffer8 = (UINT8)(*CapPtr16) + 1; + *CapPtr16 = (UINT16)(READ_PCI8(Bus, Dev, Fun, Buffer8)); + if (*CapPtr16 == 0) break; + Buffer8 = READ_PCI8(Bus, Dev, Fun, *CapPtr16); + } + } + } + return EFI_NOT_FOUND; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: FindPciGraphicAdapter +// +// Description: This routine tries to find any PCI graphic adapter on the +// PCI bus. +// +// Input: None +// +// Output: EFI_STATUS +// EFI_NOT_FOUND - No PCI Graphic Adapter to be found. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS FindPciGraphicAdapter (VOID) +{ + UINT8 StartBus; + UINT8 EndBus; + UINT8 Bus; + UINT8 Dev; + UINT8 Fun; + UINT8 EndFun; + UINT8 Buffer8; + UINT32 Vid32; + + StartBus = READ_PCI8(PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, PCIBR_REG_SBUSN); + EndBus = READ_PCI8(PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, PCIBR_REG_SUBUSN); + + for (Bus = StartBus; Bus <= EndBus; Bus++) { + for (Dev = 0; Dev <= PCI_MAX_DEVICE; Dev++) { + Vid32 = READ_PCI32(Bus, Dev, 0, PCI_VID); + if (Vid32 != 0xffffffff) { + Buffer8 = READ_PCI8(Bus, Dev, 0, PCI_HDR); + EndFun = (Buffer8 & 0x80) ? 8 : 1; + for (Fun = 0; Fun < EndFun; Fun++) { + Vid32 = READ_PCI32(Bus, Dev, Fun, PCI_VID); + if (Vid32 != 0xffffffff) { + Buffer8=READ_PCI8(Bus, Dev, Fun, PCI_BCC); + if (Buffer8 == 3) return EFI_SUCCESS; + } + } + } + } + } + + return EFI_NOT_FOUND; +} +#if NB_PCIE_ERROR_LOG_SUPPORT + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbEnablePciDevErr +// +// Description: Enable the error register of PCI-Express Device. +// +// Input: IN UINT64 Address - PCIE devices Address +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID NbEnablePciDevErr( + IN UINT64 Address +) +{ + UINT32 DevBaseAddr = (UINT32)Address; + UINT8 CapPtr; + + // Clear Error Status + WRITE_MEM8_S3(gBootScript, DevBaseAddr + 0x07, 0xff);//(BIT0 | BIT1 | BIT2 | BIT3)); + + CapPtr = NbFindCapPtr(DevBaseAddr, 0x10); + if(CapPtr != 0) + { + // Clear Device Error Status + SET_MEM8_S3(gBootScript, DevBaseAddr + CapPtr + 0x0A, (BIT0 | BIT1 | BIT2)); + // Enable the error bits of Device Control + SET_MEM8_S3(gBootScript, DevBaseAddr + CapPtr + 0x08, (BIT0 | BIT1 | BIT2)); + } + + // Root? +// if ((READ_MEM8(DevBaseAddr + CapPtr + 0x02) & 0xF0) == 0x40) + // if device is bridge + if (READ_MEM16(DevBaseAddr + 0x0A) == 0x0604) + { + WRITE_MEM8_S3(gBootScript, DevBaseAddr + 0x1F, 0xff);//(BIT0 | BIT1 | BIT2 | BIT3)); + if(CapPtr != 0) + SET_MEM8_S3(gBootScript, DevBaseAddr + CapPtr + 0x1C, (BIT0 | BIT1 | BIT2)); + } + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: NbPciExpressDeviceInitialize +// +// Description: Init NB Pcie devices error register +// +// Input: IN UINT64 Address - PCIE devices Address +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID NbPciExpressDeviceInitialize( + IN UINT64 Address +) +{ + UINT8 Dev; + UINT8 Func; + UINT8 CurrentBus; + UINT16 Buffer16; + UINT64 DevAddress; + UINT8 PciFun = (Address >> 12) & 0x07; + UINT8 CapPtr; + UINT8 Buffer8; + + CapPtr = NbFindCapPtr(Address, 0x10); + Buffer8 = READ_MEM8(Address + CapPtr + 0x08); + Buffer8 &= 0xF0; + Buffer8 |= (BIT03 | BIT02 | BIT01 | BIT00); + + WRITE_MEM8_S3( gBootScript, \ + Address + CapPtr + 0x08, \ + Buffer8 ); + + CurrentBus = READ_MEM8((UINT32)Address + PCIBR_REG_SBUSN); + + for (Dev = 0; Dev < 32; Dev++) + { + for (Func = 0; Func < 8; Func++) + { + DevAddress = (UINT64)NB_PCIE_CFG_ADDRESS(CurrentBus, Dev, Func, 0); + + if (READ_MEM16(DevAddress) == 0xFFFF) + continue; + + NbEnablePciDevErr(DevAddress); + + Buffer16 = READ_MEM16((UINT32)NB_PCIE_CFG_ADDRESS(CurrentBus, Dev, 0, 0) + PCI_SCC); + if (Buffer16 == 0x0604) + { + DevAddress = (UINT64)NB_PCIE_CFG_ADDRESS(CurrentBus, Dev, 0, 0); + NbPciExpressDeviceInitialize(DevAddress); + } + } + } +} +#endif +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbInitAfterDeviceInstall +// +// Description: This callback function is called when a PCI I/O Protocol is +// installed. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbInitAfterDeviceInstall ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + EFI_PCI_IO_PROTOCOL *PciIo; + UINTN BufferSize = 20 * sizeof(EFI_HANDLE); + UINTN PciSeg; + UINTN PciBus; + UINTN PciDev; + UINTN PciFun; + UINT8 PciSeg8; + UINT8 PciBus8; + UINT8 PciDev8; + UINT8 PciFun8; + static UINT8 BrBus = 0; + UINT16 CapPtr16 = 0; + PCI_DEV_INFO *PciDevInfo = NULL; + + Status = pBS->LocateHandle( ByRegisterNotify, NULL, gNBInitNotifyReg, \ + &BufferSize, &Handle ); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) return; + + // Locate PciIo protocol installed on Handle + + Status = pBS->HandleProtocol( Handle, &gEfiPciIoProtocolGuid, &PciIo ); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) return; + + // Get PCI Device Bus/Device/Function Numbers + Status = PciIo->GetLocation(PciIo, &PciSeg, &PciBus, &PciDev, &PciFun); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) return; + + PciSeg8 = (UINT8)PciSeg; + PciBus8 = (UINT8)PciBus; + PciDev8 = (UINT8)PciDev; + PciFun8 = (UINT8)PciFun; + + if (NB_PCI_CFG_ADDRESS(PciBus, PciDev, PciFun, 0) == NB_PCIEBRN_BUS_DEV_FUN) + { + + } + + if (NB_PCI_CFG_ADDRESS(PciBus, PciDev, PciFun, 0) == NB_IGD_BUS_DEV_FUN) { + + } + + if ((BrBus != 0) && (PciBus == BrBus)) { + + } + + if (((UINT8)PciBus == PCIEBRN_BUS) && \ + ((UINT8)PciDev == PCIEBRN_DEV) && \ + (((UINT8)PciFun >= PCIEBRN_FUN) || ((UINT8)PciFun <= PCIEBRN_FUN2))) { + + } + + pBS->CloseEvent(Event); + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RegisterDisplayDIMMPopulationErrMsg +// +// Description: Notification function on SimpleIn protocol Installation +// +// Input: SystemTable - Pointer to the System Table +// +// +// Output: EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +EFIAPI +RegisterDisplayDIMMPopulationErrMsg ( + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InstallNbMemoryInfo +// +// Description: This function collects all memory information and creates a +// structure use for other DXE drivers. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS InstallNbMemoryInfo ( + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle=NULL; + EFI_GUID MemInfoHobGuid = EFI_MEMORY_RESTORE_DATA_GUID; + HOB_SAVE_MEMORY_DATA *MemInfoHob; + UINT8 node; + UINT8 Ch; + UINT8 Dimm; + UINT8 Slot0; + UINT8 Slot1; + UINT8 Slot2; + UINT8 Slot3; + VOID *FirstHob; + BOOLEAN MemoryTimingValuesInitialized; + + // + // Get the HOB list and install MemInfo protocol + // + FirstHob = GetEfiConfigurationTable(SystemTable,&gHobListGuid); + if (!FirstHob)return EFI_INVALID_PARAMETER; + + MemInfoHob = (HOB_SAVE_MEMORY_DATA *) FirstHob; + + while (!EFI_ERROR (Status = FindNextHobByType (EFI_HOB_TYPE_GUID_EXTENSION, &MemInfoHob))) { + if (guidcmp (&MemInfoHob->EfiHobGuidType.Name, &MemInfoHobGuid) == 0) { + break; + } + } + + MemoryTimingValuesInitialized = FALSE; + + if (Status == EFI_SUCCESS) { + gMemInfoHobProtocol.MemInfoData.memSize = (UINT16)MemInfoHob->MrcData.SysOut.Outputs.MemoryMapData.TotalPhysicalMemorySize; + gMemInfoHobProtocol.MemInfoData.ddrFreq = (UINT16)MemInfoHob->MrcData.SysOut.Outputs.Frequency; + gMemInfoHobProtocol.MemInfoData.VddVoltage[0] = (UINT16)MemInfoHob->MrcData.SysOut.Outputs.VddVoltage[0]; + + gMemInfoHobProtocol.MemInfoData.EccSupport = MemInfoHob->MrcData.SysOut.Outputs.EccSupport; + gMemInfoHobProtocol.MemInfoData.RefClk = MemInfoHob->MrcData.SysOut.Outputs.RefClk; + gMemInfoHobProtocol.MemInfoData.Ratio = MemInfoHob->MrcData.SysOut.Outputs.Ratio; + NBPlatformData.DDR3Type = MemInfoHob->MrcData.SysOut.Outputs.DdrType; + gBClkFrequency = MemInfoHob->MrcData.SysIn.Inputs.BClkFrequency; + MemoryProfile = gMemInfoHobProtocol.MemInfoData.Profile = MemInfoHob->MrcData.SysIn.Inputs.MemoryProfile; + + // + // Getting the tRAS + // See MRC_TimingConfiguration.c for tRAS algorithm + // + for (node = 0; node < NODE_NUM; node++) { + for (Ch = 0; Ch < CH_NUM; Ch++) { + for (Dimm = 0; Dimm < DIMM_NUM; Dimm++) { + gMemInfoHobProtocol.MemInfoData.dimmSize[(node << 2) + (Ch << 1) + Dimm] = (UINT16) MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Dimm[Dimm].DimmCapacity; + TRACE ( + (TRACE_ALWAYS, + "Node %d Ch %d Dimm %d Size: %d\n", + node, + Ch, + Dimm, + gMemInfoHobProtocol.MemInfoData.dimmSize[(node << 2) + (Ch << 1) + Dimm]) + ); + gMemInfoHobProtocol.MemInfoData.DimmExist[(node << 2) + (Ch << 1) + Dimm] = (MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Dimm[Dimm].Status == DIMM_PRESENT) ? TRUE : FALSE; + gMemInfoHobProtocol.MemInfoData.RankInDimm[(node << 2) + (Ch << 1) + Dimm] = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Dimm[Dimm].RankInDIMM; + gMemInfoHobProtocol.MemInfoData.DimmsSpdData[(node << 2) + (Ch << 1) + Dimm] = NULL; + + // + // Updating tCL, tRCD and tRP to MemInfoHobProtocol from MemInfoHob + // + if (MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Dimm[Dimm].Status == DIMM_PRESENT) { + gMemInfoHobProtocol.MemInfoData.Timing[0].tCL = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tCL; + gMemInfoHobProtocol.MemInfoData.Timing[0].tCWL = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tCWL; + gMemInfoHobProtocol.MemInfoData.Timing[0].tFAW = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tFAW; + gMemInfoHobProtocol.MemInfoData.Timing[0].tRAS = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tRAS; + gMemInfoHobProtocol.MemInfoData.Timing[0].tRC = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tRC; + gMemInfoHobProtocol.MemInfoData.Timing[0].tRCD = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tRCD; + gMemInfoHobProtocol.MemInfoData.Timing[0].tREFI = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tREFI; + gMemInfoHobProtocol.MemInfoData.Timing[0].tRFC = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tRFC; + gMemInfoHobProtocol.MemInfoData.Timing[0].tRP = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tRP; + gMemInfoHobProtocol.MemInfoData.Timing[0].tRRD = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tRRD; + gMemInfoHobProtocol.MemInfoData.Timing[0].tRTP = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tRTP; + gMemInfoHobProtocol.MemInfoData.Timing[0].tWR = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tWR; + gMemInfoHobProtocol.MemInfoData.Timing[0].tWTR = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tWTR; + gMemInfoHobProtocol.MemInfoData.Timing[0].tRPab = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tRPab; + + NBMrcTimingData = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing; + + NBPlatformData.XmpProfile1 = (NBMrcTimingData[2].tCK != 0) ? TRUE : FALSE; + NBPlatformData.XmpProfile2 = (NBMrcTimingData[3].tCK != 0) ? TRUE : FALSE; + + // + // mrc input spd send to smbios memory spd data. + // + if(gNbSetupData->IsRunMemoryDown) + gMemInfoHobProtocol.MemInfoData.DimmsSpdData[(node << 2) + (Ch << 1) + Dimm] = (UINT8*)&MemInfoHob->MrcData.SysIn.Inputs.Controller[0].Channel[Ch].Dimm[Dimm].Spd; + +// gMemInfoHobProtocol.MemInfoData.NMode = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing.NMode; + // + // Since we have only one setup varaiable to keep track of each memory timing, We inititialize the Memory Info HOB with the first occurence of data + // + MemoryTimingValuesInitialized = TRUE; + } + } + } + } + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 0 +#if defined APAC_NB_SETUP_SUPPORT || defined NB_SETUP_SUPPORT +#if APAC_NB_SETUP_SUPPORT == 1 || NB_SETUP_SUPPORT == 1 +{ + SETUP_DATA *SetupData = NULL; + EFI_GUID SetupGuid = SETUP_GUID; + UINTN VarSize = 0; + WDT_PROTOCOL *WdtProtocol = NULL; + EFI_GUID WdtProtocolGuid = WDT_PROTOCOL_GUID; + UINT32 Attributes; // [ EIP167027 ] + + + if (MemoryTimingValuesInitialized) { + //Status = GetEfiVariable(L"Setup", &SetupGuid, NULL, &VarSize, &SetupData); // [ EIP167027 ] + Status = GetEfiVariable(L"Setup", &SetupGuid, &Attributes, &VarSize, &SetupData); + if (!EFI_ERROR(Status)) { + // + + Status = pBS->LocateProtocol(&WdtProtocolGuid, NULL, &WdtProtocol); + if (!EFI_ERROR(Status)) { + if (WdtProtocol->CheckStatus() == V_PCH_OC_WDT_CTL_STATUS_FAILURE) + SetupData->SpdProfileSelected = 0; // Auto + } + + SetupData->tCL = NBMrcTimingData[MemoryProfile].tCL; + SetupData->tCWL = NBMrcTimingData[MemoryProfile].tCWL; + SetupData->tFAW = NBMrcTimingData[MemoryProfile].tFAW; + SetupData->tRAS = NBMrcTimingData[MemoryProfile].tRAS; + SetupData->tRC = NBMrcTimingData[MemoryProfile].tRC; + SetupData->tRCD = NBMrcTimingData[MemoryProfile].tRCD; + SetupData->tREFI = NBMrcTimingData[MemoryProfile].tREFI; + SetupData->tRFC = NBMrcTimingData[MemoryProfile].tRFC; + SetupData->tRP = NBMrcTimingData[MemoryProfile].tRP; + SetupData->tRRD = NBMrcTimingData[MemoryProfile].tRRD; + SetupData->tRTP = NBMrcTimingData[MemoryProfile].tRTP; + SetupData->tWR = NBMrcTimingData[MemoryProfile].tWR; + SetupData->tWTR = NBMrcTimingData[MemoryProfile].tWTR; + SetupData->tRPab = NBMrcTimingData[MemoryProfile].tRPab; + + SetupData->OcDdrFreqLimit = gMemInfoHobProtocol.MemInfoData.ddrFreq; + + //Status = pRS->SetVariable ( // [ EIP167027 ] + // L"Setup", + // &SetupGuid, + // EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, + // sizeof(SETUP_DATA), + // SetupData); + Status = pRS->SetVariable ( + L"Setup", + &SetupGuid, + Attributes, + sizeof(SETUP_DATA), + SetupData); + ASSERT_EFI_ERROR (Status); + } + } +} +#endif +#endif +#endif + + // Mobile - 0; Desktop - 2; UpServer - 3; FlavorWorkStation - 4; + if (NBPlatformData.UserBoard != FlavorMobile) { + + Slot0 = (MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[0].Dimm[0].Status == DIMM_PRESENT) ? TRUE : FALSE; + Slot1 = (MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[0].Dimm[1].Status == DIMM_PRESENT) ? TRUE : FALSE; + Slot2 = (MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[1].Dimm[0].Status == DIMM_PRESENT) ? TRUE : FALSE; + Slot3 = (MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[1].Dimm[1].Status == DIMM_PRESENT) ? TRUE : FALSE; + + // + // Channel 0 Channel 1 + // Slot0 Slot1 Slot0 Slot1 - Population AIO board + // 0 0 0 0 - Invalid - Invalid + // 0 0 0 1 - Valid - Invalid + // 0 0 1 0 - Invalid - Valid + // 0 0 1 1 - Valid - Valid + // 0 1 0 0 - Valid - Invalid + // 0 1 0 1 - Valid - Invalid + // 0 1 1 0 - Invalid - Invalid + // 0 1 1 1 - Valid - Invalid + // 1 0 0 0 - Invalid - Valid + // 1 0 0 1 - Invalid - Invalid + // 1 0 1 0 - Invalid - Valid + // 1 0 1 1 - Invalid - Valid + // 1 1 0 0 - Valid - Valid + // 1 1 0 1 - Valid - Invalid + // 1 1 1 0 - Invalid - Valid + // 1 1 1 1 - Valid - Valid + // + if ((Slot0 && (Slot1 == 0)) || (Slot2 && (Slot3 == 0))) { + RegisterDisplayDIMMPopulationErrMsg (SystemTable); + } + } + + Status = pBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gMemInfoProtocolGuid, + &gMemInfoHobProtocol, + NULL + ); + } + + return EFI_SUCCESS; +} + +#ifdef CSM_OPRROM_POLICY_GUID +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbCheckOprom +// +// Description: This callback function is called before/after processing all +// PCI optonal ROM. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbCheckOprom ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + EFI_STATUS Status; + UINTN BufferSize = sizeof(EFI_HANDLE); + EFI_HANDLE Handle; + CSM_PLATFORM_POLICY_DATA *Data; + UINTN Seg; + UINTN Bus; + UINTN Dev; + UINTN Fun; + + Status = pBS->LocateHandle( ByRegisterNotify, \ + NULL, \ + gCsmOpromReg, \ + &BufferSize, \ + &Handle ); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) return; + + // Locate CSM Platform Policy data + Status = pBS->HandleProtocol( Handle, &gCsmOpromPolicyGuid, &Data ); + + if ( EFI_ERROR(Status) ) return; + if (Data == NULL) return; + if (Data->ExecuteThisRom == FALSE) return; + if(Data->PciIo == NULL) return; + + Status = Data->PciIo->GetLocation( Data->PciIo, &Seg, &Bus, &Dev, &Fun ); + + // Close the event if needed. + // pBS->CloseEvent(Event); +} +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbSetupNvramUpdatedCallback +// +// Description: This callback function is called after Setup NVRAM variable +// being updated. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbSetupNvramUpdatedCallback ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + EFI_STATUS Status; + NB_SETUP_DATA *NBSetupData = NULL; + UINTN VariableSize = sizeof(NB_SETUP_DATA); + + Status = pBS->AllocatePool( EfiBootServicesData, \ + VariableSize, \ + &NBSetupData ); + ASSERT_EFI_ERROR(Status); + + GetNbSetupData( pRS, NBSetupData, FALSE ); + + // Free memory used for setup data + pBS->FreePool( NBSetupData ); + + pBS->CloseEvent(Event); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbPciEnumerationCompleteProtocolCallback +// +// Description: Install gEfiPciEnumerationCompleteProtocolGuid Protocol. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbPciEnumerationCompleteProtocolCallback ( + IN EFI_EVENT Event, + IN VOID *Context) +{ + EFI_STATUS Status; + EFI_GUID gEfiPciEnumerationCompleteProtocolGuid = EFI_PCI_ENUMERATION_COMPLETE_GUID; + EFI_HANDLE Handle = NULL; + + Status = pBS->InstallProtocolInterface ( + &Handle, + &gEfiPciEnumerationCompleteProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL); + ASSERT_EFI_ERROR(Status); + + pBS->CloseEvent(Event); + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbExitPmAuthProtocolCallback +// +// Description: This callback function is called after ExitPmAuthProtocol +// being installed. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbExitPmAuthProtocolCallback ( + IN EFI_EVENT Event, + IN VOID *Context) +{ + EFI_STATUS Status; + VOID *ProtocolPointer; + UINTN PegAddress; + UINT32 Data32And; + UINT32 Data32Or; + UINT32 Data32; + UINT16 Data16; + UINT8 PegBus; + UINT8 PegDev; + UINT8 PegFun; + UINTN i; +#if NB_PCIE_ERROR_LOG_SUPPORT + UINT8 CapPtr = 0; + EFI_SM_ELOG_PROTOCOL *GenericElogProtocol = NULL; +#endif + // + // Check whether this is real ExitPmAuth notification, or just a SignalEvent + // + Status = pBS->LocateProtocol (&gExitPmAuthProtocolGuid, NULL, &ProtocolPointer); + if (EFI_ERROR (Status)) return; + + + for ( i = 0; gDevicesTable[i].Bus != 0xff; i++) + { + + PegBus = gDevicesTable[i].Bus; + PegDev = gDevicesTable[i].Dev; + PegFun = gDevicesTable[i].Fun; + + Data32 = READ_PCI32 (PegBus, PegDev, PegFun, PCI_VID); + + if (Data32 == 0xFFFFFFFF) continue; + + // + // 6.3.7 Virtual Channel Configuration of PCI Express Port + // Set the VC0RCTL register D1:F0 Offset 114h [7:1] = 7Fh + // + PegAddress = NB_PCIE_CFG_ADDRESS(PegBus, PegDev, PegFun, 0); + Data32And = 0xFFFFFF00 + BIT0; + Data32Or = BIT1 + BIT2 + BIT3 + BIT4 + BIT5 +BIT6 + BIT7; + RW_MEM32_S3(gBootScript, (PegAddress + R_SA_PEG_VC0RCTL0_OFFSET), Data32Or, ~Data32And); + + // + // Store the Root port Bus assignemnt for S3 resume path + // + PegAddress = NB_PCIE_CFG_ADDRESS(PegBus, PegDev, PegFun, PCI_PBUS); + Data32 = READ_MEM32 (PegAddress); + + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( \ + gBootScript, \ + EfiBootScriptWidthUint32, \ + PegAddress, \ + 1, \ + &Data32 ); + + PegAddress = NB_PCIE_CFG_ADDRESS(PegBus, PegDev, PegFun, PCI_BAR3); + Data16 = READ_MEM16 (PegAddress); + + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( \ + gBootScript, \ + EfiBootScriptWidthUint16, \ + PegAddress, \ + 1, \ + &Data16 ); + +#if NB_PCIE_ERROR_LOG_SUPPORT + Status = pBS->LocateProtocol( &gElogProtocolGuid, + NULL, + &GenericElogProtocol ); + if (!EFI_ERROR (Status)) { + PegAddress = NB_PCIE_CFG_ADDRESS(PegBus, PegDev, PegFun, 0); + // if enable PCI SERR and PERR + if((READ_MEM16(PegAddress + PCI_CMD) & (BIT6 | BIT8)) == (BIT6 | BIT8)) + { + NbPciExpressDeviceInitialize(PegAddress); + + // Clear Error status + WRITE_MEM8_S3(gBootScript, PegAddress + 0x07, 0xff); + WRITE_MEM8_S3(gBootScript, PegAddress + 0x1F, 0xff); + + CapPtr = NbFindCapPtr(PegAddress, 0x10); + + if (CapPtr != 0) + { + // Clear Device Error status + SET_MEM8_S3(gBootScript, PegAddress + CapPtr + 0x0A, (BIT0 | BIT1 | BIT2)); + // Enable the error bits of Device Control + SET_MEM8_S3(gBootScript, PegAddress + CapPtr + 0x08, (BIT0 | BIT1 | BIT2)); + // Enable the error bits of Root Control + SET_MEM8_S3(gBootScript, PegAddress + CapPtr + 0x1C, (BIT2)); + } + } + } +#endif + + } + + pBS->CloseEvent(Event); + +} + +//---------------------------------------------------------------------------- +#if (ACPI_SUPPORT) + +UINT8 ACPI_OEM_ID[6] = CONVERT_TO_STRING(T_ACPI_OEM_ID); +UINT8 ACPI_OEM_TBL_ID[8] = CONVERT_TO_STRING(T_ACPI_OEM_TBL_ID); + +UINTN mMcfgTblHandle=0; +EFI_EVENT mAcpiEvent; +VOID *mAcpiReg; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: CreateNbAcpiCallback +// +// Description: This function will create all ACPI components for NB when +// ACPI support protocol is available. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID CreateNbAcpiCallback ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + EFI_STATUS Status = EFI_SUCCESS; + MCFG_20 *mcfg; + EFI_ACPI_TABLE_PROTOCOL *At; + UINT8 i; + UINTN TableKey; + + // It must be only one instance of such protocol + Status = pBS->LocateProtocol( &gEfiAcpiTableProtocolGuid, NULL, &At ); + TRACE((-1,"PciHostCSHooks: LocateProtocol(ACPITableProtocol) = %r\n", Status)); + if(EFI_ERROR(Status)) return; + +//-------------------------------- + //it must be only one instance of such protocol + mcfg=MallocZ(sizeof(MCFG_20)); + ASSERT(mcfg); + if(!mcfg) return; + + //Fill Table header; + mcfg->Header.Signature=MCFG_SIG; + mcfg->Header.Length=sizeof(MCFG_20); + mcfg->Header.Revision=1; + mcfg->Header.Checksum=0; + for (i=0;i<6;i++) { + mcfg->Header.OemId[i]=ACPI_OEM_ID[i]; + } + + for (i=0;i<8;i++) { + mcfg->Header.OemTblId[i]=ACPI_OEM_TBL_ID[i]; + } + mcfg->Header.OemRev=ACPI_OEM_REV; + mcfg->Header.CreatorId=0x5446534d; // "MSFT" 4D 53 46 54 + mcfg->Header.CreatorRev=0x97; + + //fill MCFG Fields + mcfg->BaseAddr=PCIEX_BASE_ADDRESS; // Base address of 256MB extended config space + mcfg->PciSeg=0; // Segment # of PCI Bus + mcfg->StartBus=0; // Start bus number of PCI segment + mcfg->EndBus=(UINT8)((PCIEX_LENGTH >> 20) - 1);// End bus number of PCI segment + + // Add table + Status = At->InstallAcpiTable( At, mcfg, sizeof(MCFG_20), &TableKey ); + TRACE((-1,"PciHostCSHooks: ACPITable->InstallAcpiTable(MCFG)=%r\n",Status)); + ASSERT_EFI_ERROR(Status); + + //free memory used for table image + pBS->FreePool(mcfg); + + //Kill the Event + pBS->CloseEvent(Event); + +} + +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: CreateNbAcpiComponent +// +// Description: This function creates all ACPI components supported by NB. +// +// Input: None +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID CreateNbAcpiComponent (VOID) +{ + EFI_STATUS Status = EFI_SUCCESS; + +#if (ACPI_SUPPORT) + Status = RegisterProtocolCallback( &gEfiAcpiTableProtocolGuid, \ + CreateNbAcpiCallback, \ + NULL, \ + &mAcpiEvent, \ + &mAcpiReg ); + // If System Description Table Protocol has been installed we can use + // it rigth on the way + pBS->SignalEvent( mAcpiEvent ); +#endif + +} + +// Protocols that are installed +DXE_PLATFORM_SA_POLICY_PROTOCOL mDxePlatformSaPolicy = { 0 }; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InstallDxePlatformSaPolicy +// +// Description: This Function installs the SNB SA POLICY PROTOCOL +// +// Input: None +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS InstallDxePlatformSaPolicy (VOID) +{ + VOID *Registration; + EFI_EVENT Event; + EFI_STATUS Status; + EFI_STATUS FindNbPegHobStatus = EFI_NOT_FOUND; + EFI_HANDLE Handle; + VOID *HobData; + SB_SETUP_DATA *SBSetupData = NULL; + UINTN VariableSize = sizeof(SB_SETUP_DATA); + UINT8 Index; + UINT16 McDeviceId; + UINT32 RegEax, RegEbx, RegEcx, RegEdx, CpuSteppingId, CpuFamilyId; + + Status = pBS->AllocatePool( EfiBootServicesData, \ + VariableSize, \ + &SBSetupData ); + ASSERT_EFI_ERROR(Status); + + // Read the Setup Data + GetSbSetupData( pRS, SBSetupData, FALSE ); + + Status = pBS->AllocatePool ( + EfiBootServicesData, + sizeof (SA_VTD_CONFIGURATION), + &(mDxePlatformSaPolicy.Vtd) + ); + ASSERT_EFI_ERROR (Status); + + Status = pBS->AllocatePool ( + EfiBootServicesData, + sizeof (SA_MEMORY_CONFIGURATION), + &(mDxePlatformSaPolicy.MemoryConfig) + ); + ASSERT_EFI_ERROR (Status); + + Status = pBS->AllocatePool ( + EfiBootServicesData, + (sizeof (UINT8) * DIMM_SLOT_NUM), + (VOID **) &mDxePlatformSaPolicy.MemoryConfig->SpdAddressTable + ); + ASSERT_EFI_ERROR (Status); + + Status = pBS->AllocatePool (EfiBootServicesData, + sizeof (SA_PCIE_CONFIGURATION), + &(mDxePlatformSaPolicy.PcieConfig) + ); + ASSERT_EFI_ERROR (Status); + + Status = pBS->AllocatePool (EfiBootServicesData, + sizeof (SA_IGD_CONFIGURATION), + &(mDxePlatformSaPolicy.IgdConfig) + ); + ASSERT_EFI_ERROR (Status); + + Status = pBS->AllocatePool (EfiBootServicesData, + sizeof (SA_MISC_CONFIGURATION), + &(mDxePlatformSaPolicy.MiscConfig) + ); + ASSERT_EFI_ERROR (Status); + + Status = pBS->AllocatePool ( + EfiBootServicesData, + sizeof (SA_DEFAULT_SVID_SID), + (VOID **) &mDxePlatformSaPolicy.MiscConfig->DefaultSvidSid + ); + ASSERT_EFI_ERROR (Status); + + Status = pBS->AllocatePool ( + EfiBootServicesData, + sizeof (SA_HDA_VERB_TABLE), + (VOID **) &mDxePlatformSaPolicy.MiscConfig->SaHdaVerbTable + ); + ASSERT_EFI_ERROR (Status); +#if ( defined(SwitchableGraphics_SUPPORT) && (SwitchableGraphics_SUPPORT == 1) ) + Status = pBS->AllocatePool ( + EfiBootServicesData, + sizeof (SA_DEFAULT_SVID_SID), + (VOID **) &mDxePlatformSaPolicy.VbiosConfig + ); + ASSERT_EFI_ERROR (Status); +#endif + + // RMRR Base and Limit Address for USB + Status = pBS->AllocatePool ( + EfiBootServicesData, + (sizeof (EFI_PHYSICAL_ADDRESS) * 2), + (VOID **) &mDxePlatformSaPolicy.Vtd->RmrrUsbBaseAddress + ); + ASSERT_EFI_ERROR (Status); + + // Read MC device ID + McDeviceId = READ_PCI16_NB(R_SA_MC_DEVICE_ID); + + CPULib_CpuID(1, &RegEax, &RegEbx, &RegEcx, &RegEdx); + + CpuSteppingId = RegEax & 0x0000000F; + CpuFamilyId = RegEax & 0x0FFF0FF0; + + NBPlatformData.VTdAvailable = (READ_PCI32_NB(0xe4) & BIT23) ? 0 : 1; + + + mDxePlatformSaPolicy.MemoryConfig->SpdAddressTable[0] = DIMM1_SMBUS_ADDRESS; + mDxePlatformSaPolicy.MemoryConfig->SpdAddressTable[1] = DIMM2_SMBUS_ADDRESS; + mDxePlatformSaPolicy.MemoryConfig->SpdAddressTable[2] = DIMM3_SMBUS_ADDRESS; + mDxePlatformSaPolicy.MemoryConfig->SpdAddressTable[3] = DIMM4_SMBUS_ADDRESS; + + mDxePlatformSaPolicy.MemoryConfig->ChannelASlotMap = 0x03; + mDxePlatformSaPolicy.MemoryConfig->ChannelBSlotMap = 0x03; + +#if A1_MEMORY_SOCKETS == 2 + mDxePlatformSaPolicy.MemoryConfig->ChannelASlotMap = 0x01; + mDxePlatformSaPolicy.MemoryConfig->ChannelBSlotMap = 0x01; +#endif + +#if A1_MEMORY_SOCKETS == 6 + mDxePlatformSaPolicy.MemoryConfig->ChannelASlotMap = 0x07; + mDxePlatformSaPolicy.MemoryConfig->ChannelBSlotMap = 0x07; +#endif + + + mDxePlatformSaPolicy.Vtd->BaseAddress[0] = NB_VTD_BASE_ADDRESS; + mDxePlatformSaPolicy.Vtd->BaseAddress[1] = NB_VTD_BASE_ADDRESS + 0x1000; + + // System Agent Configuration Misc + + mDxePlatformSaPolicy.MiscConfig->ChapDeviceEnable = gNbSetupData->SaDevice7;; + mDxePlatformSaPolicy.MiscConfig->Device4Enable = (gNbSetupData->SaDevice4); + mDxePlatformSaPolicy.MiscConfig->CridEnable = gNbSetupData->EnableNbCrid; + mDxePlatformSaPolicy.MiscConfig->DefaultSvidSid->SubSystemVendorId = gNbSetupData->NBDxeSubSystemVendorId; + mDxePlatformSaPolicy.MiscConfig->DefaultSvidSid->SubSystemId = gNbSetupData->NBDxeSubSystemId; + + mDxePlatformSaPolicy.MiscConfig->AudioEnable = gNbSetupData->SaAudioEnable; + mDxePlatformSaPolicy.MiscConfig->FviReport = 1; // Default Enable FVI SMBIOS Report + mDxePlatformSaPolicy.MiscConfig->FviSmbiosType = 0xDD; // Default SMBIOS Type 221 + + // Port B +// gNbSaHdaVerbTableData[4] &= 0xFFFFFF00; +// if (gNbSetupData->SaHdmiCodecPortB == 0) +// gNbSaHdaVerbTableData[4] |= 0x58; +// else +// gNbSaHdaVerbTableData[4] |= 0x18; + + // Port C +// gNbSaHdaVerbTableData[8] &= 0xFFFFFF00; +// if (gNbSetupData->SaHdmiCodecPortC == 0) +// gNbSaHdaVerbTableData[8] |= 0x58; +// else +// gNbSaHdaVerbTableData[8] |= 0x18; + + // Port D +// gNbSaHdaVerbTableData[12] &= 0xFFFFFF00; +// if (gNbSetupData->SaHdmiCodecPortD == 0) +// gNbSaHdaVerbTableData[12] |= 0x58; +// else +// gNbSaHdaVerbTableData[12] |= 0x18; + +// if ((CpuFamilyId == 0x000306C0) && (CpuSteppingId < 2)) { // B0 + + if (gNbSetupData->NbSaHdaVerbTable != NULL) { + mDxePlatformSaPolicy.MiscConfig->SaHdaVerbTableNum = gNbSetupData->NbSaHdaVerbTableNum; + (pBS->CopyMem) (&mDxePlatformSaPolicy.MiscConfig->SaHdaVerbTable[0], &gNbSetupData->NbSaHdaVerbTable[0], sizeof (SA_HDA_VERB_TABLE_HEADER)); + mDxePlatformSaPolicy.MiscConfig->SaHdaVerbTable[0].VerbTableData = gNbSetupData->NbSaHdaVerbTable[0].VerbTableData; + } + +// } else { +// mDxePlatformSaPolicy.MiscConfig->SaHdaVerbTable[0].VerbTableData = &(gNbSaHdaVerbTableData[1]); +// } + + // + // BIOS must update USB RMRR base address + // + mDxePlatformSaPolicy.Vtd->RmrrUsbBaseAddress[0] = 0x3E2E0000; + mDxePlatformSaPolicy.Vtd->RmrrUsbBaseAddress[1] = 0x3E2FFFFF; + + // Protocol revision number + mDxePlatformSaPolicy.Revision = DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_8; + + // Init DxePlaformSaPolicy if Setup Variable is exist + mDxePlatformSaPolicy.Vtd->VtdEnable = gNbSetupData->EnableVtd; + + // PCIE related Setup data + mDxePlatformSaPolicy.PcieConfig->DmiAspm = gNbSetupData->NBDmiAspm; + mDxePlatformSaPolicy.PcieConfig->DmiExtSync = gNbSetupData->NBDmiExtSync; + mDxePlatformSaPolicy.PcieConfig->DmiDeEmphasis = gNbSetupData->DmiDeEmphasis; + mDxePlatformSaPolicy.PcieConfig->DmiIot = gNbSetupData->DmiIot; + mDxePlatformSaPolicy.PcieConfig->C7Allowed = gNbSetupData->C7Allowed; + for (Index = 0; Index < SA_PEG_MAX_FUN; Index++) { + mDxePlatformSaPolicy.PcieConfig->PegPwrOpt[Index].LtrEnable = gNbSetupData->LtrEnable[Index]; + mDxePlatformSaPolicy.PcieConfig->PegPwrOpt[Index].LtrMaxSnoopLatency = gNbSetupData->LtrMaxSnoopLatency[Index];//V_SA_LTR_MAX_SNOOP_LATENCY_VALUE; + mDxePlatformSaPolicy.PcieConfig->PegPwrOpt[Index].LtrMaxNoSnoopLatency = gNbSetupData->LtrMaxNoSnoopLatency[Index];//V_SA_LTR_MAX_NON_SNOOP_LATENCY_VALUE; + mDxePlatformSaPolicy.PcieConfig->PegPwrOpt[Index].ObffEnable = gNbSetupData->ObffEnable[Index]; + } + + + + if (gNbSetupData->DetectNonComplaint == 1) { + HobData = (EFI_HOB_GENERIC_HEADER *) GetEfiConfigurationTable (pST, &gHobListGuid); + if (HobData) { + FindNbPegHobStatus = FindNextHobByGuid (&gAmiNbPegInfoGuid, &HobData); + } + } + + for (Index = 0; Index < 3; Index++) { + mDxePlatformSaPolicy.PcieConfig->PegAspm[Index] = gNbSetupData->PegAspm[Index]; + mDxePlatformSaPolicy.PcieConfig->PegAspmL0s[Index] = gNbSetupData->PegAspmL0s[Index]; + if (EFI_ERROR (FindNbPegHobStatus)) { + mDxePlatformSaPolicy.PcieConfig->PegDeEmphasis[Index] = gNbSetupData->PegDeEmphasis[Index]; + } else { + mDxePlatformSaPolicy.PcieConfig->PegDeEmphasis[Index] = ((NB_PEG_INFO_HOB *)HobData)->PegDeOverride[Index]; + } + } + + mDxePlatformSaPolicy.PcieConfig->PcieAspmDevsOverride = mPcieAspmDevsOverride; + mDxePlatformSaPolicy.PcieConfig->PcieLtrDevsOverride = mPcieLtrDevsOverride; + + // IGD related Setup data + mDxePlatformSaPolicy.IgdConfig->RenderStandby = gNbSetupData->RenderStandby; + + mDxePlatformSaPolicy.IgdConfig->DeepRenderStandby = gNbSetupData->DeepRenderStandby; + + if (GetPchSeries() == PchLp) { + mDxePlatformSaPolicy.IgdConfig->CdClk = 1; + } else { + mDxePlatformSaPolicy.IgdConfig->CdClk = 2; // (EIP106013) + } + + + mDxePlatformSaPolicy.IgdConfig->PlatformConfig = gNbSetupData->AcpiLowPowerS0Idle; + + +#ifdef BDAT_SUPPORT + mDxePlatformSaPolicy.MemoryConfig->RmtBdatEnable = gNbSetupData->BdatAcpiTableSupport; +#endif + +#if ( defined(SwitchableGraphics_SUPPORT) && (SwitchableGraphics_SUPPORT == 1) ) + /// + /// Initialize the Switchable Graphics DXE Policies + /// + + /// + /// 1 = Load secondary display device VBIOS + /// 0 = Do not load + /// + mDxePlatformSaPolicy.VbiosConfig->LoadVbios = 0; // Shark Bay SA Reference Code Production Version 1.9.0 [ EIP194524 ] + /// + /// 1 = Execute the secondary display device VBIOS (only if LoadVbios == 1) + /// 0 = Do no execute + /// + mDxePlatformSaPolicy.VbiosConfig->ExecuteVbios = 0; + /// + /// 1 = secondary display device VBIOS Source is PCI Card + /// 0 = secondary display device VBIOS Source is FW Volume + /// + mDxePlatformSaPolicy.VbiosConfig->VbiosSource = 1; +#endif + + Handle = NULL; + // Install protocol to to allow access to this Policy. + Status = pBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gDxePlatformSaPolicyGuid, + &mDxePlatformSaPolicy, + NULL + ); + ASSERT_EFI_ERROR (Status); + + + // Register Callback function for updating USB Rmrr address + Status = pBS->CreateEvent ( + EFI_EVENT_NOTIFY_SIGNAL, + TPL_CALLBACK, + RmrrUpdateCallback, + NULL, + &Event + ); + + if (!EFI_ERROR (Status)) { + Status = pBS->RegisterProtocolNotify ( + &gEfiUsbProtocolGuid, + Event, + &Registration + ); + } + + // Free memory used for setup data + pBS->FreePool( SBSetupData ); + + return Status; + +} + +//<AMI_PHDR_START> +//------------------------------------------------------------------------------------------------- +// +// Procedure: RmrrUpdateCallback +// +// Description: This Function is update IGD & USB Rmrr BaseAddress +// +// Input: Event A pointer to the Event that triggered the callback. +// Context A pointer to private data registered with the callback function. +// +// Output: None +//-------------------------------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +RmrrUpdateCallback ( + IN EFI_EVENT Event, + IN VOID *Context +) +{ + EFI_STATUS Status; + EFI_USB_PROTOCOL *UsbProtocol; + DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy; + UINT16 IgdMode; + UINT16 GttMode; + UINT32 IgdMemSize; + UINT32 GttMemSize; + EFI_PHYSICAL_ADDRESS RmrrIGDBaseAddress; + EFI_PHYSICAL_ADDRESS RmrrIGDSize; + DXE_SERVICES *DxeSvcTbl = NULL; + EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdMemorySpaceDescriptor; + UINT64 Attributes; + + pBS->CloseEvent(Event); + // + // Update USB Reserved Memory Base Address and Limit Address for VT-d. + // + Status = pBS->LocateProtocol (&gDxePlatformSaPolicyGuid, NULL, &DxePlatformSaPolicy); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = pBS->LocateProtocol (&gEfiUsbProtocolGuid, NULL, &UsbProtocol); + if (!EFI_ERROR (Status)) + { + + Status = UsbProtocol->UsbGetRuntimeRegion ( + &DxePlatformSaPolicy->Vtd->RmrrUsbBaseAddress[0], + &DxePlatformSaPolicy->Vtd->RmrrUsbBaseAddress[1] + ); + + TRACE ((TRACE_ALWAYS, "RmrrUsbBaseAddress = 0x%X\n", DxePlatformSaPolicy->Vtd->RmrrUsbBaseAddress[0])); + TRACE ((TRACE_ALWAYS, "RmrrUsbLimitAddress = 0x%X\n", DxePlatformSaPolicy->Vtd->RmrrUsbBaseAddress[1])); + } + + if (READ_PCI32_IGD (R_SA_IGD_VID) == 0xFFFFFFFF) return Status; + + Status = LibGetDxeSvcTbl(&DxeSvcTbl); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) return Status; + + // + // Calculate IGD memsize + // + IgdMode = (READ_PCI16_NB (R_SA_GGC) & B_SA_GGC_GMS_MASK) >> 3; + if (IgdMode <= V_SA_GGC_GMS_512MB) + { + IgdMemSize = IgdMode * 32 * (1024) * (1024); + } else if (IgdMode >= 0x11) // V_SA_GGC_GMS_1024MB + { + IgdMemSize = 0x20 * 32 * (1024) * (1024); + } else { + IgdMemSize = 0; + } + + // + // Calculate GTT mem size + // + GttMode = (READ_PCI16_NB (R_SA_GGC) & B_SA_GGC_GGMS_MASK) >> N_SA_GGC_GGMS_OFFSET; + if (GttMode <= V_SA_GGC_GGMS_2MB) + { + GttMemSize = GttMode * (1024) * (1024); + } else { + GttMemSize = 0; + } + + if ((IgdMemSize + GttMemSize) == 0) return Status; + + RmrrIGDBaseAddress = (EFI_PHYSICAL_ADDRESS)((READ_PCI32_NB (R_SA_TOLUD) & ~(0x01)) - IgdMemSize - GttMemSize); + RmrrIGDSize = (EFI_PHYSICAL_ADDRESS)(IgdMemSize + GttMemSize); + + Status = DxeSvcTbl->GetMemorySpaceDescriptor (RmrrIGDBaseAddress, &GcdMemorySpaceDescriptor); + ASSERT_EFI_ERROR (Status); + + Attributes = GcdMemorySpaceDescriptor.Attributes | EFI_MEMORY_RUNTIME; + + Status=DxeSvcTbl->SetMemorySpaceAttributes(RmrrIGDBaseAddress,RmrrIGDSize,Attributes); + ASSERT_EFI_ERROR(Status); + + TRACE ((TRACE_ALWAYS, "RmrrIGDBaseAddress = 0x%X\n", RmrrIGDBaseAddress)); + TRACE ((TRACE_ALWAYS, "RmrrIGDSize = 0x%X\n", RmrrIGDSize)); + + return Status; +} + +//<AMI_PHDR_START> +//------------------------------------------------------------------------------------------------- +// +// Procedure: NBDXE_ShadowRam +// +// Description: For setting PAM0\PAM5\PAM6 to "Disable", "Read Only", "Write Only", or "R/W Enable" +// under not using legacy. +// +// Input: EFI_HANDLE +// EFI_SYSTEM_TABL +// +// Output: None +//-------------------------------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBDXE_ShadowRam ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINT8 Default_PAM0 = (UINT8)(NB_F0000_PAM0 << 4); + UINT8 Default_PAM5 = (UINT8)((NB_E0000_PAM5 << 4) | NB_E0000_PAM5); + UINT8 Default_PAM6 = (UINT8)((NB_E8000_PAM6 << 4) | NB_E8000_PAM6); + + // + // Set "Disable", "Read Only", "Write Only", or "R/W Enable" as Token value into PAM0\PAM5\PAM6. + // + WRITE_PCI8_NB (0x80, Default_PAM0); + WRITE_PCI8_NB (0x85, Default_PAM5); + WRITE_PCI8_NB (0x86, Default_PAM6); + + return Status; +} + + +#if defined (PERF_TUNE_SUPPORT) && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C +#define OC_MAILBOX_MSR 0x00000150 +#define MAILBOX_WAIT_TIMEOUT 1000 ///< 1 millisecond +#define OC_LIB_CMD_GET_OC_CAPABILITIES 0x01 +#define OC_LIB_CMD_GET_VOLTAGE_FREQUENCY 0x10 +#define OC_LIB_COMPLETION_CODE_SUCCESS 0x00 +#define BIT0_MASK 0x1 +#define MAX_RATIO_MASK 0x000000FF +#define VOLTAGE_TARGET_MASK 0x000FFF00 +#define VOLTAGE_TARGET_OFFSET 8 +#define VOLTAGE_MODE_MASK 0x00100000 +#define VOLTAGE_MODE_OFFSET 20 +#define VOLTAGE_OFFSET_MASK 0xFFE00000 +#define VOLTAGE_OFFSET_OFFSET 21 + +#define MILLIVOLTS_PER_VOLT 1000 +#define MAX_TARGET_MV 4095 +#define MAX_OFFSET_MV 500 + +#define CONVERT_TO_FIXED_POINT_VOLTS 0 +#define CONVERT_TO_BINARY_MILLIVOLT 1 + +#define OC_CAPS_MAX_RATIO_MASK 0x000000FF +#define OC_CAPS_RATIO_SUPPORT_MASK 0x00000100 +#define OC_CAPS_RATIO_SUPPORT_OFFSET 8 +#define OC_CAPS_OVERRIDE_SUPPORT_MASK 0x00000200 +#define OC_CAPS_OVERRIDE_SUPPORT_OFFSET 9 +#define OC_CAPS_OFFSET_SUPPORT_MASK 0x00000400 +#define OC_CAPS_OFFSET_SUPPORT_OFFSET 10 +// +// Bit 10 is the S11.0.10V sign bit +// +#define FIXED_POINT_SIGN_BIT_MASK 0x0400 +#define INT16_SIGN_BIT_MASK 0x8000 + +// +// tCL Macro definitions +// +#ifndef tCL_MINIMUM +#define tCL_MINIMUM 4 +#endif +#ifndef tCL_MAXIMUM +#define tCL_MAXIMUM 18 +#endif +#define tCL_NumOfValues tCL_MAXIMUM - tCL_MINIMUM + 1 +// +// tRP Macro definitions +// +#ifndef tRP_MINIMUM +#define tRP_MINIMUM 4 +#endif +#ifndef tRP_MAXIMUM +#define tRP_MAXIMUM 15 +#endif +#define tRP_NumOfValues tRP_MAXIMUM - tRP_MINIMUM + 1 +// +// tRCD Macro definitions +// +#ifndef tRCD_MINIMUM +#define tRCD_MINIMUM 4 +#endif +#ifndef tRCD_MAXIMUM +#define tRCD_MAXIMUM 20 +#endif +#define tRCD_NumOfValues tRCD_MAXIMUM - tRCD_MINIMUM + 1 +// +// tRAS Macro definitions +// +#ifndef tRAS_MINIMUM +#define tRAS_MINIMUM 10 +#endif +#ifndef tRAS_MAXIMUM +#define tRAS_MAXIMUM 40 +#endif +#define tRAS_NumOfValues tRAS_MAXIMUM - tRAS_MINIMUM + 1 +// +// tWR Macro definitions +// +#ifndef tWR_MINIMUM +#define tWR_MINIMUM 5 +#endif +#ifndef tWR_MAXIMUM +#define tWR_MAXIMUM 30 +#endif +#define tWR_NumOfValues tWR_MAXIMUM - tWR_MINIMUM + 1 +// +// tRFC Macro definitions +// +#ifndef tRFC_MINIMUM +#define tRFC_MINIMUM 1 +#endif +#ifndef tRFC_MAXIMUM +#define tRFC_MAXIMUM 511 +#endif +#define tRFC_NumOfValues tRFC_MAXIMUM - tRFC_MINIMUM + 1 +// +// tRRD Macro definitions +// +#ifndef tRRD_MINIMUM +#define tRRD_MINIMUM 4 +#endif +#ifndef tRRD_MAXIMUM +#define tRRD_MAXIMUM 7 +#endif +#define tRRD_NumOfValues tRRD_MAXIMUM - tRRD_MINIMUM + 1 +// +// tWTR Macro definitions +// +#ifndef tWTR_MINIMUM +#define tWTR_MINIMUM 4 +#endif +#ifndef tWTR_MAXIMUM +#define tWTR_MAXIMUM 10 +#endif +#define tWTR_NumOfValues tWTR_MAXIMUM - tWTR_MINIMUM + 1 +// +// tRTP Macro definitions +// +#ifndef tRTP_MINIMUM +#define tRTP_MINIMUM 4 +#endif +#ifndef tRTP_MAXIMUM +#define tRTP_MAXIMUM 15 +#endif + +#define tRTP_NumOfValues tRTP_MAXIMUM - tRTP_MINIMUM + 1 +// +// tFAW Macro definitions +// +#ifndef tFAW_MINIMUM +#define tFAW_MINIMUM 10 +#endif +#ifndef tFAW_MAXIMUM +#define tFAW_MAXIMUM 54 +#endif +#define tFAW_NumOfValues tFAW_MAXIMUM - tFAW_MINIMUM + 1 +// +// tRC Macro definitions +// +#ifndef tRC_MINIMUM +#define tRC_MINIMUM 1 +#endif +#ifndef tRC_MAXIMUM +#define tRC_MAXIMUM 4095 +#endif +#define tRC_NumOfValues tRC_MAXIMUM - tRC_MINIMUM + 1 +// +// +// tCWL Macro definitions +// +#ifndef tCWL_MINIMUM +#define tCWL_MINIMUM 5 +#endif +#ifndef tCWL_MAXIMUM +#define tCWL_MAXIMUM 12 +#endif +#define tCWL_NumOfValues tCWL_MAXIMUM - tCWL_MINIMUM + 1 +// +// tREFI Macro definitions +// +#ifndef tREFI_MINIMUM +#define tREFI_MINIMUM 1 +#endif +#ifndef tREFI_MAXIMUM +#define tREFI_MAXIMUM 10000 +#endif +#define tREFI_NumOfValues tREFI_MAXIMUM - tREFI_MINIMUM + 1 +// +// tRPab Macro definitions +// +#ifndef tRPab_MINIMUM +#define tRPab_MINIMUM 4 +#endif +#ifndef tRPab_MAXIMUM +#define tRPab_MAXIMUM 18 +#endif +#define tRPab_NumOfValues tRPab_MAXIMUM - tRPab_MINIMUM + 1 +// +// +// iGfxRatio Macro definitions +// +#ifndef iGfxRatio_MINIMUM +#define iGfxRatio_MINIMUM 17 +#endif +#ifndef iGfxRatio_MAXIMUM +#define iGfxRatio_MAXIMUM 60 +#endif +#define iGfxRatio_NumOfValues iGfxRatio_MAXIMUM - iGfxRatio_MINIMUM + 1 + +// +// iGfxVolt Macro definitions +// +#ifndef iGfxVoltOverride_MINIMUM +#define iGfxVoltOverride_MINIMUM 0 +#endif +#ifndef iGfxVoltOverride_MAXIMUM +#define iGfxVoltOverride_MAXIMUM 2000 +#endif +#define iGfxVoltOverride_NumOfValues iGfxVoltOverride_MAXIMUM - iGfxVoltOverride_MINIMUM + 1 + +#ifndef iGfxVoltOffset_MINIMUM +#define iGfxVoltOffset_MINIMUM 0 +#endif +#ifndef iGfxVoltOffset_MAXIMUM +#define iGfxVoltOffset_MAXIMUM 1000 +#endif +#define iGfxVoltOffset_NumOfValues iGfxVoltOffset_MAXIMUM - iGfxVoltOffset_MINIMUM + 1 + +#ifndef SaVoltOffset_MINIMUM +#define SaVoltOffset_MINIMUM 0 +#endif +#ifndef SaVoltOffset_MAXIMUM +#define SaVoltOffset_MAXIMUM 1000 +#endif +#define SaVoltOffset_NumOfValues SaVoltOffset_MAXIMUM - SaVoltOffset_MINIMUM + 1 + +#ifndef IoaVoltOffset_MINIMUM +#define IoaVoltOffset_MINIMUM 0 +#endif +#ifndef IoaVoltOffset_MAXIMUM +#define IoaVoltOffset_MAXIMUM 1000 +#endif +#define IoaVoltOffset_NumOfValues IoaVoltOffset_MAXIMUM - IoaVoltOffset_MINIMUM + 1 + +#ifndef IodVoltOffset_MINIMUM +#define IodVoltOffset_MINIMUM 0 +#endif +#ifndef IodVoltOffset_MAXIMUM +#define IodVoltOffset_MAXIMUM 1000 +#endif +#define IodVoltOffset_NumOfValues IodVoltOffset_MAXIMUM - IodVoltOffset_MINIMUM + 1 + +//========================================== GACI TABLE ====================================================== + +// GACI_DATA DevNameGaciData {ControlID,NumberOfValues,\ +// Precision,Flags,DefaultDataValue,MinDataValue,MaxDataValue,MinDisplayValue,MaxDisplayValue} +static GACI_DATA tCLGaciData = {BIOS_TCL_IMPLEMENTATION,\ + tCL_NumOfValues, 0, 0, 0, tCL_MINIMUM, tCL_MAXIMUM, tCL_MINIMUM, tCL_MAXIMUM}; + +static GACI_DATA tCWLGaciData = {BIOS_TCWL_IMPLEMENTATION,\ + tCWL_NumOfValues, 0, 0, 0, tCWL_MINIMUM, tCWL_MAXIMUM, tCWL_MINIMUM, tCWL_MAXIMUM}; + +static GACI_DATA tREFIGaciData = {BIOS_TREFI_IMPLEMENTATION,\ + tREFI_NumOfValues, 0, 0, 0, tREFI_MINIMUM, tREFI_MAXIMUM, tREFI_MINIMUM, tREFI_MAXIMUM}; + +static GACI_DATA tRASGaciData = {BIOS_TRAS_IMPLEMENTATION,\ + tRAS_NumOfValues, 0, 0, 0, tRAS_MINIMUM, tRAS_MAXIMUM, tRAS_MINIMUM, tRAS_MAXIMUM}; + +static GACI_DATA tRPGaciData = {BIOS_TRP_IMPLEMENTATION,\ + tRP_NumOfValues, 0, 0, 0, tRP_MINIMUM, tRP_MAXIMUM, tRP_MINIMUM, tRP_MAXIMUM}; + +static GACI_DATA tRCDGaciData = {BIOS_TRCD_IMPLEMENTATION,\ + tRCD_NumOfValues, 0, 0, 0, tRCD_MINIMUM, tRCD_MAXIMUM, tRCD_MINIMUM, tRCD_MAXIMUM}; + +static GACI_DATA tWRGaciData = {BIOS_TWR_IMPLEMENTATION,\ + tWR_NumOfValues, 0, 0, 0, tWR_MINIMUM, tWR_MAXIMUM, tWR_MINIMUM, tWR_MAXIMUM}; + +static GACI_DATA tRFCGaciData = {BIOS_TRFC_IMPLEMENTATION,\ + tRFC_NumOfValues, 0, 0, 0, tRFC_MINIMUM, tRFC_MAXIMUM, tRFC_MINIMUM, tRFC_MAXIMUM}; + +static GACI_DATA tRRDGaciData = {BIOS_TRRD_IMPLEMENTATION,\ + tRRD_NumOfValues, 0, 0, 0, tRRD_MINIMUM, tRRD_MAXIMUM, tRRD_MINIMUM, tRRD_MAXIMUM}; + +static GACI_DATA tWTRGaciData = {BIOS_TWTR_IMPLEMENTATION,\ + tWTR_NumOfValues, 0, 0, 0, tWTR_MINIMUM, tWTR_MAXIMUM, tWTR_MINIMUM, tWTR_MAXIMUM}; + +static GACI_DATA tRTPGaciData = {BIOS_TRTP_IMPLEMENTATION,\ + tRTP_NumOfValues, 0, 0, 0, tRTP_MINIMUM, tRTP_MAXIMUM, tRTP_MINIMUM, tRTP_MAXIMUM}; + +static GACI_DATA tFAWGaciData = {BIOS_TFAW_IMPLEMENTATION,\ + tFAW_NumOfValues, 0, 0, 0, tFAW_MINIMUM, tFAW_MAXIMUM, tFAW_MINIMUM, tFAW_MAXIMUM}; + +static GACI_DATA tRCGaciData = {BIOS_TRC_IMPLEMENTATION,\ + tRC_NumOfValues, 0, 0, 0, tRC_MINIMUM, tRC_MAXIMUM, tRC_MINIMUM, tRC_MAXIMUM}; + +//static GACI_DATA tRPabGaciData = {BIOS_TRPAB_IMPLEMENTATION,\ +// tRPab_NumOfValues, 0, 0, 0, tRPab_MINIMUM, tRPab_MAXIMUM, tRPab_MINIMUM, tRPab_MAXIMUM}; + +static GACI_DATA DramMultiGaciData = {BIOS_DDR_MULT_IMPLEMENTATION,\ + 0xFFFF, 2, 0, 0, 0, 0, 0, 0}; + +static GACI_DATA XmpProfSelData = {BIOS_XMP_PROFILE_SELECTION_IMPLEMENTATION,\ + 3, 0, 0, 0, 0, 3, 0, 3}; + +static GACI_DATA CpuRuntimeTurbo = {BIOS_RUNTIME_TURBO_OVERRIDE_IMPLEMENTATION,\ + 0, 0, 0, 0, 0, 0, 0, 0}; + +static GACI_DATA iGfxTurboRatioData = {BIOS_GRAPHICS_TURBO_RATIO_LIMIT_IMPLEMENTATION,\ + iGfxRatio_NumOfValues, 1, 0, 0, 0, iGfxRatio_MAXIMUM, 0, iGfxRatio_MAXIMUM}; + +//static GACI_DATA iGfxVoltageData = {BIOS_GRAPHICS_CORE_VOLTAGE_IMPLEMENTATION,\ +// iGfxVolt_NumOfValues, 0, 0, 0, iGfxVolt_MINIMUM, iGfxVolt_MAXIMUM, iGfxVolt_MINIMUM, iGfxVolt_MAXIMUM}; + +static GACI_DATA iGfxVoltageOverride = {BIOS_GRAPHICS_CORE_VOLTAGE_OVERRIDE_IMPLEMENTATION,\ + iGfxVoltOverride_NumOfValues, 3, 0, 0, iGfxVoltOverride_MINIMUM, iGfxVoltOverride_MAXIMUM, iGfxVoltOverride_MINIMUM, iGfxVoltOverride_MAXIMUM}; + +static GACI_DATA iGfxVoltageMode = {BIOS_GRAPHICS_CORE_VOLTAGE_MODE_IMPLEMENTATION,\ + 1, 0, 0, 0, 0, 1, 0, 1}; + +static GACI_DATA iGfxVoltageOffset = {BIOS_GRAPHICS_CORE_VOLTAGE_OFFSET_IMPLEMENTATION,\ + 2001, 0, 0, 1000, 0, 2000, 0xFFFFFc18, 1000}; + +static GACI_DATA SaVoltageOffset = {BIOS_SYSTEM_AGENT_VOLTAGE_OFFSET_IMPLEMENTATION,\ + 2001, 0, 0, 1000, 0, 2000, 0xFFFFFc18, 1000}; + +static GACI_DATA IoaVoltageOffset = {BIOS_IO_ANALOG_VOLTAGE_OFFSET_IMPLEMENTATION,\ + 2001, 0, 0, 1000, 0, 2000, 0xFFFFFc18, 1000}; + +static GACI_DATA IodVoltageOffset = {BIOS_IO_DIGITAL_VOLTAGE_OFFSET_IMPLEMENTATION,\ + 2001, 0, 0, 1000, 0, 2000, 0xFFFFFc18, 1000}; + +static GACI_DATA MemClockMultiplier = {BIOS_MEM_CLOCK_MULTIPLIER_IMPLEMENTATION,\ + 0xFFFF, 2, 0, 0, 0, 0, 0, 0}; + +//========================================== XMP Profile TABLE ====================================================== +//Profile 1 data +// GXDV DevNameGxdvData = {ControlID, Reserved, Precision, DisplayValue}; +static GXDV_DATA Pro1tCLGxdvData = {BIOS_TCL_IMPLEMENTATION, 0, 0, 8}; +static GXDV_DATA Pro1tRASGxdvData = {BIOS_TRAS_IMPLEMENTATION, 0, 0, 23}; +static GXDV_DATA Pro1tRPGxdvData = {BIOS_TRP_IMPLEMENTATION, 0, 0, 8}; +static GXDV_DATA Pro1tRCDGxdvData = {BIOS_TRCD_IMPLEMENTATION, 0, 0, 8}; +static GXDV_DATA Pro1tWRGxdvData = {BIOS_TWR_IMPLEMENTATION, 0, 0, 9}; +static GXDV_DATA Pro1tRFCGxdvData = {BIOS_TRFC_IMPLEMENTATION, 0, 0, 73}; +static GXDV_DATA Pro1tRRDGxdvData = {BIOS_TRRD_IMPLEMENTATION, 0, 0, 4}; +static GXDV_DATA Pro1tWTRGxdvData = {BIOS_TWTR_IMPLEMENTATION, 0, 0, 5}; +static GXDV_DATA Pro1tRTPGxdvData = {BIOS_TRTP_IMPLEMENTATION, 0, 0, 5}; +static GXDV_DATA Pro1tFAWGxdvData = {BIOS_TFAW_IMPLEMENTATION, 0, 0, 20}; +static GXDV_DATA Pro1tRCGxdvData = {BIOS_TRC_IMPLEMENTATION, 0, 0, 20}; +static GXDV_DATA Pro1tREFIGxdvData = {BIOS_TREFI_IMPLEMENTATION, 0, 0, 1000}; +static GXDV_DATA Pro1tCWLGxdvData = {BIOS_TCWL_IMPLEMENTATION, 0, 0, 8}; +//static GXDV_DATA Pro1tRPabGxdvData = {BIOS_TRPAB_IMPLEMENTATION, 0, 0, 4}; +static GXDV_DATA Pro1DdrMulGxdvData = {BIOS_DDR_MULT_IMPLEMENTATION, 0, 0, 16}; +static GXDV_DATA Pro1DdrClkMulGxdvData = {BIOS_MEM_CLOCK_MULTIPLIER_IMPLEMENTATION, 0,2, 133}; + +//profile 2 data +// GXDV DevNameGxdvData = {ControlID, Reserved, Precision, DisplayValue}; +static GXDV_DATA Pro2tCLGxdvData = {BIOS_TCL_IMPLEMENTATION, 0, 0, 7}; +static GXDV_DATA Pro2tRASGxdvData = {BIOS_TRAS_IMPLEMENTATION, 0, 0, 22}; +static GXDV_DATA Pro2tRPGxdvData = {BIOS_TRP_IMPLEMENTATION, 0, 0, 7}; +static GXDV_DATA Pro2tRCDGxdvData = {BIOS_TRCD_IMPLEMENTATION, 0, 0, 7}; +static GXDV_DATA Pro2tWRGxdvData = {BIOS_TWR_IMPLEMENTATION, 0, 0, 8}; +static GXDV_DATA Pro2tRFCGxdvData = {BIOS_TRFC_IMPLEMENTATION, 0, 0, 72}; +static GXDV_DATA Pro2tRRDGxdvData = {BIOS_TRRD_IMPLEMENTATION, 0, 0, 4}; +static GXDV_DATA Pro2tWTRGxdvData = {BIOS_TWTR_IMPLEMENTATION, 0, 0, 5}; +static GXDV_DATA Pro2tRTPGxdvData = {BIOS_TRTP_IMPLEMENTATION, 0, 0, 5}; +static GXDV_DATA Pro2tFAWGxdvData = {BIOS_TFAW_IMPLEMENTATION, 0, 0, 20}; +static GXDV_DATA Pro2tRCGxdvData = {BIOS_TRC_IMPLEMENTATION, 0, 0, 20}; +static GXDV_DATA Pro2tREFIGxdvData = {BIOS_TREFI_IMPLEMENTATION, 0, 0, 1000}; +static GXDV_DATA Pro2tCWLGxdvData = {BIOS_TCWL_IMPLEMENTATION, 0, 0, 8}; +//static GXDV_DATA Pro2tRPabGxdvData = {BIOS_TRPAB_IMPLEMENTATION, 0, 0, 4}; +static GXDV_DATA Pro2DdrMulGxdvData = {BIOS_DDR_MULT_IMPLEMENTATION, 0, 0, 18}; +static GXDV_DATA Pro2DdrClkMulGxdvData = {BIOS_MEM_CLOCK_MULTIPLIER_IMPLEMENTATION, 0,2, 133}; +//=================================================================================================================== + + +static +MrcFrequency +NbGetDimmFrequency ( + IN UINT32 tCK + ); + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: GetIGDSettings +// +// Description: Update XTU GACI Table function . +// +// Input: +// IN EFI_EVENT Event +// IN VOID *Context +// +// Output: +// VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT32 GetIGDSettings(void) +{ + UINT32 GTTMMADR;// = 0xF7800000; + UINT32 Data32; + + // + // Program GT PM Settings if GTTMMADR allocation is Successful + // + GTTMMADR = (UINT32)NB_TEMP_MMIO_BASE; + WRITE_PCI32_IGD (R_SA_IGD_GTTMMADR, (GTTMMADR | BIT02)); // 0x10 + + // + // Enable Bus Master, I/O and Memory access on 0:2:0 + // + SET_PCI8_IGD (R_SA_IGD_CMD , (BIT02 | BIT01)); // 0x04 + + TRACE((-1,"GT Overclocking Support is enabled in BIOS Setup\n")); + + // + // Wait for Mailbox ready + // + while (READ_MEM32 ((UINTN)(GTTMMADR + 0x138124)) & BIT31) { + Data32 = READ_MEM32 ((UINTN)(GTTMMADR + 0x138124)); + }; + + // + // Mailbox Command - MAILBOX_GTDRIVER_CMD_READ_OVERCLOCK_PARAMS to READ OC SUPPORT + // + Data32 = 0x8000000C; + WRITE_MEM32 ((UINTN)(GTTMMADR + 0x138124), Data32); + + // + // Wait for Mailbox ready + // + while (READ_MEM32 ((UINTN)(GTTMMADR + 0x138124)) & BIT31) { + Data32 = READ_MEM32 ((UINTN)(GTTMMADR + 0x138124)); + }; + + + if (READ_MEM32 ((UINTN)(GTTMMADR + 0x138128)) & BIT31) + { + Data32 = READ_MEM32 ((UINTN)(GTTMMADR + 0x138128)); + return Data32; + } + return Data32; +} + +EFI_STATUS GetDddtPresentFlagHob() +{ + EFI_STATUS Status; + EFI_GUID gDddtPreFlagHobGuid = AMI_DDDT_PRESENT_FLAG_HOB_GUID; + VOID *gDddtPreFlagHobList = NULL; + UINTN FlagCount = (sizeof(BIOS_SETTING_DATA) - sizeof(BIOS_SETTING_HDR))/sizeof(UINT16); + +// Get Hob List + gDddtPreFlagHobList = GetEfiConfigurationTable(pST, &gHobListGuid); + if (!gDddtPreFlagHobList) return EFI_NOT_FOUND; + +// Find CPUID Checksum Data Hob. + gDddtPresentFlagHob = (DDDT_PRESENT_FLAG_HOB*)gDddtPreFlagHobList; + while (!EFI_ERROR(Status = FindNextHobByType(EFI_HOB_TYPE_GUID_EXTENSION, &gDddtPresentFlagHob))) + { + if (guidcmp(&gDddtPresentFlagHob->EfiHobGuidType.Name, &gDddtPreFlagHobGuid) == 0) + break; + } + + if (EFI_ERROR(Status)) return EFI_NOT_FOUND; + return Status; +} + +typedef union _OC_MAILBOX_INTERFACE { + UINT32 InterfaceData; + struct { + UINT8 CommandCompletion:8; + UINT8 Param1:8; + UINT8 Param2:8; + UINT8 Reserved:7; + UINT8 RunBusy:1; + } Fields; +} OC_MAILBOX_INTERFACE; + +typedef struct _OC_MAILBOX_FULL { + UINT32 Data; + OC_MAILBOX_INTERFACE Interface; +} OC_MAILBOX_FULL; + +typedef struct { + UINT8 MaxOcRatio; + UINT8 VoltageTargetMode; + UINT16 VoltageTarget; + INT16 VoltageOffset; +} VOLTAGE_FREQUENCY_SETTINGS; + +typedef struct { + VOLTAGE_FREQUENCY_SETTINGS VfSettings; + UINT8 DomainId; +} VOLTAGE_FREQUENCY_ITEM; + +typedef struct { + UINT8 MaxOcRatioLimit; + BOOLEAN RatioOcSupported; + BOOLEAN VoltageOverridesSupported; + BOOLEAN VoltageOffsetSupported; + UINT8 DomainId; +} OC_CAPABILITIES_ITEM; + +typedef union _OC_MAILBOX_COMMAND { + UINT32 InterfaceData; + struct { + UINT8 CommandCompletion:8; + UINT8 Param1:8; + UINT8 Param2:8; + UINT8 Reserved:7; + UINT8 RunBusy:1; + } Fields; +} OC_MAILBOX_COMMAND; + +typedef struct _OC_MAILBOX_ITEM { + UINT32 Data; + OC_MAILBOX_COMMAND Interface; +} OC_MAILBOX_ITEM; + + +EFI_STATUS +EFIAPI PollOcMailboxReady ( + ) +/** + + Poll the run/busy bit of the mailbox until available or timeout expires. + + @param[IN] MailboxType, + + @retval EFI_STATUS + +**/ +{ + EFI_STATUS Status; + UINT16 StallCount; + UINT8 RunBusyBit; + UINT64 MsrData; + OC_MAILBOX_FULL OcMailboxFull; + + Status = EFI_SUCCESS; + StallCount = 0; + RunBusyBit = 1; + + do { +// case MAILBOX_TYPE_OC: + /// + /// Read the OC mailbox run/busy state + /// + MsrData = ReadMsr(OC_MAILBOX_MSR); + pBS->CopyMem (&OcMailboxFull.Data, &MsrData, sizeof(OcMailboxFull)); + RunBusyBit = OcMailboxFull.Interface.Fields.RunBusy; +// break; + // + // Wait for 1us + // + CountTime(4, PM_BASE_ADDRESS); + StallCount++; + } + while ((RunBusyBit == 1) && (StallCount < MAILBOX_WAIT_TIMEOUT)); + + if ((RunBusyBit == 0) && (StallCount == MAILBOX_WAIT_TIMEOUT)) { + TRACE ((TRACE_ALWAYS, "(MAILBOX) Mailbox interface timed out.\n")); + Status = EFI_TIMEOUT; + } + return Status; +} + + +EFI_STATUS +EFIAPI OcMailboxRead ( + IN UINT32 MailboxCommand, + OUT UINT32 *MailboxDataPtr, + OUT UINT32 *MailboxStatus + + ) +/** + + Generic Mailbox function for mailbox read commands. This function will write + the read request, and populate the read results in the output data. + + @param[IN] MailboxType, + @param[IN] MailboxCommand, + @param[OUT] *MailboxDataPtr, + @param[OUT] *MailboxStatus + + @retval EFI_STATUS + +**/ +{ + EFI_STATUS Status; + UINT64 MsrData; + OC_MAILBOX_FULL OcMailboxFull; + OC_MAILBOX_FULL OcMailboxFullVerify; + + /// + /// Poll the run/busy to ensure the interface is available + /// + Status = PollOcMailboxReady(); + if (EFI_ERROR(Status)) { + return Status; + } + + TRACE ((TRACE_ALWAYS, "(MAILBOX) Mailbox Read Command = %2X\n", (UINT8)MailboxCommand)); + + // MAILBOX_TYPE_OC: + /// + /// Set the Run/Busy bit to signal mailbox data is ready to process + /// + OcMailboxFull.Interface.InterfaceData = MailboxCommand; + OcMailboxFull.Data = *MailboxDataPtr; + OcMailboxFull.Interface.Fields.RunBusy = 1; + pBS->CopyMem (&MsrData, &OcMailboxFull, sizeof(MsrData)); + + /// + /// Write mailbox command to OC mailbox + /// + WriteMsr (OC_MAILBOX_MSR, MsrData); + + /// + /// Poll run/busy to indicate the completion of write request + /// + PollOcMailboxReady(); + + /// + /// Read the OC mailbox to verify read completion success. + /// Mailbox protocol requires software to read back the interface twice + /// to ensure the read results are consistent. + /// + MsrData = ReadMsr (OC_MAILBOX_MSR); + pBS->CopyMem (&OcMailboxFull, &MsrData, sizeof(OcMailboxFull)); + + CountTime(40000, PM_BASE_ADDRESS); // 10ms + + MsrData = ReadMsr (OC_MAILBOX_MSR); + pBS->CopyMem (&OcMailboxFullVerify, &MsrData, sizeof(OcMailboxFullVerify)); + + /// + /// If the data is inconsistent, we cannot trust the results + /// + if (OcMailboxFull.Interface.InterfaceData != OcMailboxFullVerify.Interface.InterfaceData ){ + if (OcMailboxFull.Data != OcMailboxFullVerify.Data) { + TRACE ((TRACE_ALWAYS, "(MAILBOX) Mailbox read data is corrupted.\n")); + return EFI_INVALID_PARAMETER; + } + } + + /// + /// Copy Overclocking mailbox completion code and read results + /// + *MailboxStatus = OcMailboxFull.Interface.Fields.CommandCompletion; + pBS->CopyMem(MailboxDataPtr, &OcMailboxFull.Data, sizeof(UINT32)); + + + TRACE ((TRACE_ALWAYS, "(MAILBOX) Mailbox Status = %2X\n", *MailboxStatus)); + + return Status; +} + +VOID +ConvertVoltageTarget ( + IN UINT16 InputVoltageTarget, + OUT UINT16* OutputVoltageTarget, + IN UINT8 ConversionType + ) +/** + + Converts the input voltage target to the fixed point U12.2.10 Volt format or + the Binary millivolts representation based on the ConversionType + +@param[IN] InputVoltageTarget +@param[OUT] *OutputVoltageTarget +@param[IN] ConversionType - 0:fixed point, 1:Binary millivolts + +**/ +{ + /// Fixed point representation: + /// + /// U12.2.10V format + /// | | | | + /// | | | v + /// | | v Exponent + /// | v Significand Size + /// v Size + /// Signed/Unsigned + /// + /// Float Value = Significand x (Base ^ Exponent) + /// (Base ^ Exponent) = 2 ^ 10 = 1024 + /// + + if (InputVoltageTarget == 0){ + *OutputVoltageTarget = 0; + return; + } + + if(ConversionType == CONVERT_TO_FIXED_POINT_VOLTS){ + /// + /// Input Voltage is in number of millivolts. Clip the input Voltage + /// to the max allowed by the fixed point format + /// + if (InputVoltageTarget > MAX_TARGET_MV) + InputVoltageTarget = MAX_TARGET_MV; + + /// + /// InputTargetVoltage is the significand in mV. Need to convert to Volts + /// + *OutputVoltageTarget = (InputVoltageTarget * 1024)/ MILLIVOLTS_PER_VOLT; + + } + else if (ConversionType == CONVERT_TO_BINARY_MILLIVOLT){ + /// + /// InputVoltage is specified in fixed point representation, need to + /// convert to millivolts + /// + *OutputVoltageTarget = (InputVoltageTarget * MILLIVOLTS_PER_VOLT)/1024; + } + + return; +} + +VOID +ConvertVoltageOffset ( + IN INT16 InputVoltageOffset, + OUT INT16* OutputVoltageOffset, + IN UINT8 ConversionType + ) +/** + + Converts the input votlage Offset to the fixed point S11.0.10 Volt format or + to Binary illivolts representation based on the ConversionType. + +@param[IN] InputVoltageTarget +@param[OUT] *OutputVoltageTarget +@param[IN] ConversionType - 0:fixed point, 1:Signed Binary millivolts + + +**/ +{ + BOOLEAN NumIsNegative; + /// Fixed point representation: + /// + /// S11.0.10V format + /// | | | | + /// | | | v + /// | | v Exponent + /// | v Significand Size + /// v Size + /// Signed/Unsigned + /// + /// Float Value = Significand x (Base ^ Exponent) + /// (Base ^ Exponent) = 2 ^ 10 = 1024 + /// + *OutputVoltageOffset = 0; + NumIsNegative = FALSE; + + if (InputVoltageOffset == 0){ + *OutputVoltageOffset = 0; + return; + } + + if (ConversionType == CONVERT_TO_FIXED_POINT_VOLTS){ + /// + /// Input Voltage is in INT16 representation. Check if numenr is negative + /// + if ( (InputVoltageOffset & INT16_SIGN_BIT_MASK) != 0){ + NumIsNegative = TRUE; + /// + /// Need to 2's complement adjust to make this number positive for + /// voltage calculation + /// + InputVoltageOffset = (~InputVoltageOffset+1) & (INT16_SIGN_BIT_MASK -1); + } + + /// + /// Clip the input Voltage Offset to 500mv + /// + if (InputVoltageOffset > MAX_OFFSET_MV) { + InputVoltageOffset = MAX_OFFSET_MV; + } + + /// + /// Convert to fixed point representation + /// + *OutputVoltageOffset = (InputVoltageOffset * 1024)/ MILLIVOLTS_PER_VOLT; + if (NumIsNegative){ + /// 2's complement back to a negative number + *OutputVoltageOffset = ~(*OutputVoltageOffset) + 1; + } + } + else if (ConversionType == CONVERT_TO_BINARY_MILLIVOLT){ + /// + /// Input Voltage is in fixed point representation. Check if number negative + /// + if( (InputVoltageOffset & FIXED_POINT_SIGN_BIT_MASK)!= 0){ + NumIsNegative = TRUE; + /// + /// Need to 2's complement adjust to make this number positive for + /// voltage calculation + /// + InputVoltageOffset = (~InputVoltageOffset+1) & (FIXED_POINT_SIGN_BIT_MASK -1); + } + + /// + /// Convert to INT16 representation in millivolts + /// + *OutputVoltageOffset = (InputVoltageOffset * MILLIVOLTS_PER_VOLT)/1024; + if (NumIsNegative){ + /// 2's complement back to a negative number + *OutputVoltageOffset = ~(*OutputVoltageOffset) + 1; + } + } + + return; +} + +EFI_STATUS +EFIAPI GetOcCapabilities ( + OUT OC_CAPABILITIES_ITEM *OcCapabilities, + OUT UINT32 *LibStatus + ) +/** + Get the overclocking capabilities for a given CPU Domain + + @param[OUT] *OcCapabilities + @param[OUT] *LibStatus + + @retval EFI_STATUS +**/ +{ + EFI_STATUS Status; + UINT32 CommandId; + OC_MAILBOX_ITEM OcCapsMsg; + + Status = EFI_SUCCESS; + +// ZeroMem(&OcCapsMsg,sizeof(OC_MAILBOX_ITEM)); + + /// + /// Convert OC capabilties message to Mailbox command format + /// + CommandId = OC_LIB_CMD_GET_OC_CAPABILITIES; + //ConvertToMailboxFormat((VOID *)OcCapabilities, &OcCapsMsg, CommandId); + OcCapsMsg.Data = 0; + OcCapsMsg.Interface.Fields.CommandCompletion = CommandId; + OcCapsMsg.Interface.Fields.Param1 = 1; + /// + /// Read From the OC Library + /// + Status = OcMailboxRead(OcCapsMsg.Interface.InterfaceData, &OcCapsMsg.Data, LibStatus); + + /// + /// Copy mailbox data to OC Capabilities structure + /// + if ( (Status == EFI_SUCCESS) && (*LibStatus == OC_LIB_COMPLETION_CODE_SUCCESS)) { + OcCapabilities->MaxOcRatioLimit = + (UINT8) OcCapsMsg.Data & OC_CAPS_MAX_RATIO_MASK; + + OcCapabilities->RatioOcSupported = + (UINT8) ((OcCapsMsg.Data & OC_CAPS_RATIO_SUPPORT_MASK) >> OC_CAPS_RATIO_SUPPORT_OFFSET); + + OcCapabilities->VoltageOverridesSupported = + (UINT8) ((OcCapsMsg.Data & OC_CAPS_OVERRIDE_SUPPORT_MASK) >> OC_CAPS_OVERRIDE_SUPPORT_OFFSET); + + OcCapabilities->VoltageOffsetSupported = + (UINT8) ((OcCapsMsg.Data & OC_CAPS_OFFSET_SUPPORT_MASK) >> OC_CAPS_OFFSET_SUPPORT_OFFSET); + } + + return Status; +} + +EFI_STATUS +EFIAPI GetVoltageFrequencyItem ( + OUT VOLTAGE_FREQUENCY_ITEM * VfSettings, + OUT UINT32 *LibStatus + ) +/** + + Gets the Voltage and Frequency information for a given CPU domain + + @param[OUT] *VfSettings + @param[OUT] *LibStatus + + @retval EFI_STATUS + +**/ +{ + EFI_STATUS Status; + UINT32 CommandId; + UINT16 TempVoltageTarget; + INT16 TempVoltageOffset; + OC_MAILBOX_ITEM VfMsg; + + Status = EFI_SUCCESS; + + /// + /// Convert v/f command to Mailbox command format + /// + CommandId = OC_LIB_CMD_GET_VOLTAGE_FREQUENCY; + +// ConvertToMailboxFormat((VOID*)VfSettings, &VfMsg, CommandId); + + /// + /// Voltage Frequency Settings are on a per domain basis + /// + VfMsg.Data = 0; + VfMsg.Interface.Fields.CommandCompletion = CommandId; + VfMsg.Interface.Fields.Param1 = 1; + + /// + /// Read From the OC Library + /// + Status = OcMailboxRead(VfMsg.Interface.InterfaceData, &VfMsg.Data, LibStatus); + + /// + /// Copy mailbox data to VfSettings + /// + if ( (Status == EFI_SUCCESS) && (*LibStatus == OC_LIB_COMPLETION_CODE_SUCCESS)){ + VfSettings->VfSettings.MaxOcRatio = (UINT8) (VfMsg.Data & MAX_RATIO_MASK); + VfSettings->VfSettings.VoltageTargetMode = (UINT8) ( (VfMsg.Data & VOLTAGE_MODE_MASK) >> VOLTAGE_MODE_OFFSET); + + TempVoltageTarget = (UINT16) (VfMsg.Data & VOLTAGE_TARGET_MASK) >> VOLTAGE_TARGET_OFFSET; + ConvertVoltageTarget(TempVoltageTarget, &VfSettings->VfSettings.VoltageTarget, CONVERT_TO_BINARY_MILLIVOLT); + + TempVoltageOffset = (INT16)((VfMsg.Data & VOLTAGE_OFFSET_MASK) >> VOLTAGE_OFFSET_OFFSET); + ConvertVoltageOffset(TempVoltageOffset, &VfSettings->VfSettings.VoltageOffset, CONVERT_TO_BINARY_MILLIVOLT); + } + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: NbXTUSetGACITable +// +// Description: Update XTU GACI Table function . +// +// Input: +// IN EFI_EVENT Event +// IN VOID *Context +// +// Output: +// VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbXTUSetGACITable( + IN EFI_EVENT Event, + IN VOID *Context +) +{ + EFI_STATUS Status = EFI_UNSUPPORTED; + UINT8 *Buffer = NULL; + UINTN Len = 0; + UINT8 channel = 0; + EFI_GUID gXtuDataHobGuid = AMI_PERF_TUNE_DATA_HOB_GUID; + UINT8 NumOcBins = (UINT8)(ReadMsr(0x194) >> 17) & 0x7; + VOID *FirstHob; + AMI_INTERNAL_FACTORY_TDC_TDP_HOB *TdcTdpHob = NULL; + BOOLEAN TdcTdpHobFound = FALSE, OcDataHobFound = FALSE; + UINT16 OneCoreRatioLimit; + UINT16 MaxNonTurboRatio; + UINT8 MemRatio, RefClkRatio; + UINT32 CurrentRatio; + OC_CAPABILITIES_ITEM OcCaps; + UINT32 LibStatus; + PERF_TUNE_DATA_HOB *PerfTuneDataHob = NULL; + UINT32 MemFreq; + MrcFrequency DDRFrequency[2] = {fNoInit}; + + if (gPerfTuneAslProtocol == NULL) + { + Status = pBS->LocateProtocol(&gPerfTuneAslProtocolGuid, NULL, &gPerfTuneAslProtocol); + if(EFI_ERROR(Status))goto Done; + } + + FirstHob = GetEfiConfigurationTable(pST, &gHobListGuid); + + TdcTdpHob = (AMI_INTERNAL_FACTORY_TDC_TDP_HOB*)FirstHob; + while (!EFI_ERROR(Status = FindNextHobByType(EFI_HOB_TYPE_GUID_EXTENSION, &TdcTdpHob))) { + if (guidcmp(&TdcTdpHob->EfiHobGuidType.Name, &gAmiInternalFactoryTdcTdpHobGuid) == 0) { + TdcTdpHobFound = TRUE; + break; + } + } + + FirstHob = GetEfiConfigurationTable(pST, &gHobListGuid); + + PerfTuneDataHob = (PERF_TUNE_DATA_HOB*)FirstHob; + while (!EFI_ERROR(Status = FindNextHobByType(EFI_HOB_TYPE_GUID_EXTENSION, &PerfTuneDataHob))) { + if (guidcmp(&PerfTuneDataHob->EfiHobGuidType.Name, &gXtuDataHobGuid) == 0) { + OcDataHobFound = TRUE; + break; + } + } + +//========================== GACI TABLE ============================================= +//------------------------- tCL Setting ---------------------------------------- + Len = sizeof(tCLGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tCLGaciData.DefaultDataValue = NBMrcTimingData[0].tCL;//DefaultData.tCL; + + MemCpy(Buffer, &tCLGaciData, sizeof(tCLGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tCL); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tCWL Setting --------------------------------------- + Len = sizeof(tCWLGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tCWLGaciData.DefaultDataValue = NBMrcTimingData[0].tCWL;//DefaultData.tCWL; + + MemCpy(Buffer, &tCWLGaciData, sizeof(tCWLGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tCWL); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tREFI Setting --------------------------------------- + Len = sizeof(tREFIGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tREFIGaciData.DefaultDataValue = NBMrcTimingData[0].tREFI;//DefaultData.tREFI; + + MemCpy(Buffer, &tREFIGaciData, sizeof(tREFIGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tREFI); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tRCD Setting --------------------------------------- + Len = sizeof(tRCDGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tRCDGaciData.DefaultDataValue = NBMrcTimingData[0].tRCD;//DefaultData.tRCD; + + MemCpy(Buffer, &tRCDGaciData, sizeof(tRCDGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tRCD); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tRP Setting ---------------------------------------- + Len = sizeof(tRPGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tRPGaciData.DefaultDataValue = NBMrcTimingData[0].tRP;//DefaultData.tRP; + + MemCpy(Buffer, &tRPGaciData, sizeof(tRPGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tRP); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tRAS Setting --------------------------------------- + Len = sizeof(tRASGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tRASGaciData.DefaultDataValue = NBMrcTimingData[0].tRAS;//DefaultData.tRAS; + + MemCpy(Buffer, &tRASGaciData, sizeof(tRASGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tRAS); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tWR Setting --------------------------------------- + Len = sizeof(tWRGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tWRGaciData.DefaultDataValue = NBMrcTimingData[0].tWR;//DefaultData.tWR; + + MemCpy(Buffer, &tWRGaciData, sizeof(tWRGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tWR); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tRFC Setting --------------------------------------- + Len = sizeof(tRFCGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tRFCGaciData.DefaultDataValue = NBMrcTimingData[0].tRFC;//DefaultData.tRFC; + + MemCpy(Buffer, &tRFCGaciData, sizeof(tRFCGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tRFC); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tRRD Setting --------------------------------------- + Len = sizeof(tRRDGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + tRRDGaciData.DefaultDataValue = NBMrcTimingData[0].tRRD;//DefaultData.tRRD; + + MemCpy(Buffer, &tRRDGaciData, sizeof(tRRDGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tRRD); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tWTR Setting --------------------------------------- + Len = sizeof(tWTRGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tWTRGaciData.DefaultDataValue = NBMrcTimingData[0].tWTR;//DefaultData.tWTR; + + MemCpy(Buffer, &tWTRGaciData, sizeof(tWTRGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tWTR); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tRTP Setting --------------------------------------- + Len = sizeof(tRTPGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tRTPGaciData.DefaultDataValue = NBMrcTimingData[0].tRTP;//DefaultData.tRTP; + + MemCpy(Buffer, &tRTPGaciData, sizeof(tRTPGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tRTP); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tFAW Setting --------------------------------------- + Len = sizeof(tFAWGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tFAWGaciData.DefaultDataValue = NBMrcTimingData[0].tFAW;//DefaultData.tFAW; + + MemCpy(Buffer, &tFAWGaciData, sizeof(tFAWGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tFAW); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tRC Setting --------------------------------------- + Len = sizeof(tRCGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tRCGaciData.DefaultDataValue = NBMrcTimingData[0].tRC;//DefaultData.tRC; + + MemCpy(Buffer, &tRCGaciData, sizeof(tRCGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tRC); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tRPab Setting --------------------------------------- +// Len = sizeof(tRPabGaciData); +// Buffer = MallocZ(Len); +// if(!Buffer) goto Done; + +// tRPabGaciData.DefaultDataValue = NBMrcTimingData[0].tRPab;//DefaultData.tRPab; + +// MemCpy(Buffer, &tRPabGaciData, sizeof(tRPabGaciData)); +// Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tRPab); +// Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); +// pBS->FreePool(Buffer); +//----------------------------- iGfX Core Ratio Limit --------------------------- + if (READ_PCI32_IGD (R_SA_IGD_VID) != 0xFFFFFFFF) { + + Status = GetOcCapabilities(&OcCaps,&LibStatus); + if ( (Status == EFI_SUCCESS) && (LibStatus == OC_LIB_COMPLETION_CODE_SUCCESS)) { + + Len = sizeof(iGfxTurboRatioData); + Buffer = MallocZ(Len); + + + CurrentRatio = OcCaps.MaxOcRatioLimit; + + iGfxTurboRatioData.MinDataValue = READ_MEM8_MCH(0x5998); // Rpm + iGfxTurboRatioData.MaxDataValue = CurrentRatio; + iGfxTurboRatioData.DefaultDataValue = READ_MEM8_MCH(0x5998); // Rpm + + + iGfxTurboRatioData.MinDisplayValue = iGfxTurboRatioData.MinDataValue * 5; + iGfxTurboRatioData.MaxDisplayValue = iGfxTurboRatioData.MaxDataValue * 5; + iGfxTurboRatioData.NumberOfValues = iGfxTurboRatioData.MaxDataValue - iGfxTurboRatioData.MinDataValue + 1; + + + MemCpy(Buffer, &iGfxTurboRatioData, sizeof(iGfxTurboRatioData)); + + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------------- iGfX Voltage mode ------------------------------- + Len = sizeof(iGfxVoltageMode); + Buffer = MallocZ(Len); + + iGfxVoltageMode.MaxDataValue = 1; + iGfxVoltageMode.MaxDisplayValue = 1; + iGfxVoltageMode.NumberOfValues = 2; + + MemCpy(Buffer, &iGfxVoltageMode, sizeof(iGfxVoltageMode)); + + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------------- iGfX Voltage ------------------------------- +// Len = sizeof(iGfxVoltageData); +// Buffer = MallocZ(Len); + + //GtOcVolt = CurrentVfItem.VfSettings.VoltageTarget; + +// MemCpy(Buffer, &iGfxVoltageData, sizeof(iGfxVoltageData)); + + //Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)GtOcVolt); + +// Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); +// pBS->FreePool(Buffer); +//------------------------------- iGfX Voltage Override------------------------------- + Len = sizeof(iGfxVoltageOverride); + Buffer = MallocZ(Len); + + + MemCpy(Buffer, &iGfxVoltageOverride, sizeof(iGfxVoltageOverride)); + + + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); + +//------------------------------- iGfX Voltage Offset------------------------------- + Len = sizeof(iGfxVoltageOffset); + Buffer = MallocZ(Len); + + + MemCpy(Buffer, &iGfxVoltageOffset, sizeof(iGfxVoltageOffset)); + + + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); + } // GetVoltageFrequencyItem + } // if have IGFX ? +//------------------------------- Sa Voltage Offset ------------------------------- + Len = sizeof(SaVoltageOffset); + Buffer = MallocZ(Len); + + MemCpy(Buffer, &SaVoltageOffset, sizeof(SaVoltageOffset)); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); + +//------------------------------- IOA Voltage Offset ------------------------------- + Len = sizeof(IoaVoltageOffset); + Buffer = MallocZ(Len); + + MemCpy(Buffer, &IoaVoltageOffset, sizeof(IoaVoltageOffset)); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); + +//------------------------------- IOD Voltage Offset ------------------------------- + Len = sizeof(IodVoltageOffset); + Buffer = MallocZ(Len); + + MemCpy(Buffer, &IodVoltageOffset, sizeof(IodVoltageOffset)); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------------- Runtime Turbo ------------------------------- + if (TdcTdpHobFound) { + + Len = sizeof(CpuRuntimeTurbo); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + OneCoreRatioLimit = (UINT16)(TdcTdpHob->OneCoreRatioLimit); + MaxNonTurboRatio = ((UINT16)ReadMsr(0xCE) >> 8) & 0xFF; + + if(OcDataHobFound) { + if(PerfTuneDataHob->PerfTuneDataHob.RuntimeTurboEanble == 0x1) { + if(PerfTuneDataHob->PerfTuneDataHob.RuntimeTurbo == 0xFFFF) + WRITE_MEM8_MCH(0x5990, (UINT8)OneCoreRatioLimit); + else + WRITE_MEM8_MCH(0x5990, (UINT8)PerfTuneDataHob->PerfTuneDataHob.RuntimeTurbo); + } else { + WRITE_MEM8_MCH(0x5990, 0xFF); + } + } + + CpuRuntimeTurbo.DefaultDataValue = OneCoreRatioLimit; + + if (NumOcBins == 7) { + CpuRuntimeTurbo.MaxDataValue = 0x3b; //max ratio is 59. + CpuRuntimeTurbo.MaxDisplayValue = 0x3b; + } else if((NumOcBins > 0) && (NumOcBins < 7)) { + CpuRuntimeTurbo.MaxDataValue = OneCoreRatioLimit + NumOcBins; + CpuRuntimeTurbo.MaxDisplayValue = OneCoreRatioLimit + NumOcBins; + } + + CpuRuntimeTurbo.MinDataValue = MaxNonTurboRatio; + CpuRuntimeTurbo.MinDisplayValue = MaxNonTurboRatio; + CpuRuntimeTurbo.NumberOfValues = CpuRuntimeTurbo.MaxDataValue - CpuRuntimeTurbo.MinDataValue + 1; + + MemCpy(Buffer, &CpuRuntimeTurbo, sizeof(CpuRuntimeTurbo)); + + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); + } +//-------------------------- Mem Freq Setting ---------------------------------------- + Len = sizeof(DramMultiGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + MemFreq = gMemInfoHobProtocol.MemInfoData.ddrFreq; + MemRatio = (NbFrequencyToRatio(MemFreq, gMemInfoHobProtocol.MemInfoData.RefClk, gBClkFrequency)*2); + DramMultiGaciData.DefaultDataValue = (UINT32)MemRatio; + + MemCpy(Buffer, &DramMultiGaciData, sizeof(DramMultiGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, MemRatio); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//----------------------------Memory Clock Multiplier----------------------- + Len = sizeof(MemClockMultiplier); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + if(gMemInfoHobProtocol.MemInfoData.RefClk == MRC_REF_CLOCK_100){ + RefClkRatio = 100; + }else{ + RefClkRatio = 133; + } + + MemClockMultiplier.DefaultDataValue = (UINT32)RefClkRatio; + MemCpy(Buffer, &MemClockMultiplier, sizeof(MemClockMultiplier)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, RefClkRatio); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//-------------------------- XMP Profile Selection ------------------------- + + Len = sizeof(XmpProfSelData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + //Add core to Update the Minimum and Maximum. + //According to XMP profile count. + + // Default + XmpProfSelData.MaxDataValue = 1; + XmpProfSelData.MaxDisplayValue = 1; + XmpProfSelData.NumberOfValues = 2; + + DDRFrequency[0] = NbGetDimmFrequency(NBMrcTimingData[2].tCK); + DDRFrequency[1] = NbGetDimmFrequency(NBMrcTimingData[3].tCK); + + if (DDRFrequency[0] != fNoInit && DDRFrequency[1] == fNoInit) { // Porfile 1 + XmpProfSelData.MaxDataValue = 2; + XmpProfSelData.MaxDisplayValue = 2; + XmpProfSelData.NumberOfValues = 3; + } else if (DDRFrequency[0] != fNoInit && DDRFrequency[1] != fNoInit) { // Both Profile + XmpProfSelData.MaxDataValue = 3; + XmpProfSelData.MaxDisplayValue = 3; + XmpProfSelData.NumberOfValues = 4; + } + + MemCpy(Buffer, &XmpProfSelData, Len); + + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//---------------------------- GXDV START ----------------------------------- + + Len = sizeof(GXDV_DATA); + Len = (UINTN)Mul64(Len, 30); // 32 mean, define GXDV count. + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + //Add code to change profile 1 display value + if (DDRFrequency[0] != fNoInit) { + MemRatio = NbFrequencyToRatio(DDRFrequency[0], gMemInfoHobProtocol.MemInfoData.RefClk, gBClkFrequency); + + Pro1tCLGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tCL; + Pro1tRASGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tRAS; + Pro1tRPGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tRP; + Pro1tRCDGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tRCD; + Pro1tWRGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tWR; + Pro1tRFCGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tRFC; + Pro1tRRDGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tRRD; + Pro1tWTRGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tWTR; + Pro1tRTPGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tRTP; + Pro1tFAWGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tFAW; + Pro1tRCGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tRC; + Pro1tREFIGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tREFI; + Pro1tCWLGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tCWL; +// Pro1tRPabGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tRPab; + Pro1DdrMulGxdvData.DisplayValue = (UINT32)DDRFrequency[0]; + Pro1DdrMulGxdvData.DisplayValue = (UINT32)MemRatio * 2; + Pro1DdrClkMulGxdvData.DisplayValue = (UINT32)RefClkRatio; + + } + + //Add code to change Profile 2 display value + if (DDRFrequency[1] != fNoInit) { + MemRatio = NbFrequencyToRatio(DDRFrequency[1], gMemInfoHobProtocol.MemInfoData.RefClk, gBClkFrequency); + + Pro2tCLGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tCL; + Pro2tRASGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tRAS; + Pro2tRPGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tRP; + Pro2tRCDGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tRCD; + Pro2tWRGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tWR; + Pro2tRFCGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tRFC; + Pro2tRRDGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tRRD; + Pro2tWTRGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tWTR; + Pro2tRTPGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tRTP; + Pro2tFAWGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tFAW; + Pro2tRCGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tRC; + Pro2tREFIGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tREFI; + Pro2tCWLGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tCWL; +// Pro1tRPabGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tRPab; + Pro2DdrMulGxdvData.DisplayValue = (UINT32)DDRFrequency[1]; + Pro2DdrMulGxdvData.DisplayValue = (UINT32)MemRatio * 2; + Pro2DdrClkMulGxdvData.DisplayValue = (UINT32)RefClkRatio; + } + + MemCpy(Buffer, &Pro1tCLGxdvData, Len); + + if (DDRFrequency[0] == fNoInit && DDRFrequency[1] == fNoInit) // Default + Status = gPerfTuneAslProtocol->SetGxdvData(XmpNotSupport,Buffer, Len); + else if (DDRFrequency[0] != fNoInit && DDRFrequency[1] == fNoInit) // Profile 1 + Status = gPerfTuneAslProtocol->SetGxdvData(Profiles1,Buffer, Len); + else if (DDRFrequency[0] != fNoInit && DDRFrequency[1] != fNoInit) // Both Profile + Status = gPerfTuneAslProtocol->SetGxdvData(Both,Buffer, Len); + + pBS->FreePool(Buffer); + +//---------------------------- GXDV END ----------------------------------- + +Done: + // Kill event + pBS->CloseEvent(Event); +} +#endif +#endif + + +EFI_STATUS ReadSpdData ( + IN EFI_SMBUS_HC_PROTOCOL *Smbus, + IN UINT8 SpdSalveAddr, + IN UINT8 Offset, + IN UINTN Count, + OUT UINT8 *Buffer + ) +{ + EFI_STATUS Status; + UINTN Index; + UINTN Length; + EFI_SMBUS_OPERATION Operation; + EFI_SMBUS_DEVICE_COMMAND Command; + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + + SlaveAddress.SmbusDeviceAddress = SpdSalveAddr >> 1; + + + for (Index = 0; Index < Count; Index++) + { + Command = Offset + Index; + + Length = 1; + Operation = EfiSmbusReadByte; + Status = Smbus->Execute (Smbus, + SlaveAddress, + Command, + Operation, + FALSE, + &Length, + &Buffer[Index] ); + if (EFI_ERROR(Status)) return Status; + } + + return EFI_SUCCESS; +} + +#define MRC_FREQUENCY_MTB_OFFSET 1000000 +#define MRC_FREQUENCY_FTB_OFFSET 1000 +#define MRC_DDR3_800_TCK_MIN 2500000 /// 1/(800/2) femtoseconds +#define MRC_DDR3_1000_TCK_MIN 2000000 /// 1/(1000/2) femtoseconds +#define MRC_DDR3_1067_TCK_MIN 1875000 /// 1/(1067/2) femtoseconds +#define MRC_DDR3_1200_TCK_MIN 1666666 /// 1/(1200/2) femtoseconds +#define MRC_DDR3_1333_TCK_MIN 1500000 /// 1/(1333/2) femtoseconds +#define MRC_DDR3_1400_TCK_MIN 1428571 /// 1/(1400/2) femtoseconds +#define MRC_DDR3_1600_TCK_MIN 1250000 /// 1/(1600/2) femtoseconds +#define MRC_DDR3_1800_TCK_MIN 1111111 /// 1/(1800/2) femtoseconds +#define MRC_DDR3_1867_TCK_MIN 1071428 /// 1/(1867/2) femtoseconds +#define MRC_DDR3_2000_TCK_MIN 1000000 /// 1/(2000/2) femtoseconds +#define MRC_DDR3_2133_TCK_MIN 937500 /// 1/(2133/2) femtoseconds +#define MRC_DDR3_2200_TCK_MIN 909090 /// 1/(2200/2) femtoseconds +#define MRC_DDR3_2400_TCK_MIN 833333 /// 1/(2400/2) femtoseconds +#define MRC_DDR3_2600_TCK_MIN 769230 /// 1/(2600/2) femtoseconds +#define MRC_DDR3_2667_TCK_MIN 750000 /// 1/(2667/2) femtoseconds +#define MRC_DDR3_2800_TCK_MIN 714285 /// 1/(2800/2) femtoseconds +#define TREFIMULTIPLIER 1000 /// tREFI value defined in XMP 1.3 spec is actually in thousands of MTB units. +#define MAX(a,b) (((a) > (b)) ? (a) : (b)) +#define MIN(a,b) (((a) < (b)) ? (a) : (b)) + +const NbTRangeTable NbRange[] = { + { 0xFFFFFFFF, fUnSupport, (0 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_800_TCK_MIN, f800, (1 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1000_TCK_MIN, f1000, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1067_TCK_MIN, f1067, (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1200_TCK_MIN, f1200, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1333_TCK_MIN, f1333, (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1400_TCK_MIN, f1400, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1600_TCK_MIN, f1600, (1 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1800_TCK_MIN, f1800, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1867_TCK_MIN, f1867, (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2000_TCK_MIN, f2000, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2133_TCK_MIN, f2133, (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2200_TCK_MIN, f2200, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2400_TCK_MIN, f2400, (1 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2600_TCK_MIN, f2600, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2667_TCK_MIN, f2667, (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { 0, fNoInit, (0 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) } +}; + +static BOOLEAN +NbGetDimmTimeBase ( + IN SPD_EXTREME_MEMORY_PROFILE *const XmpSpd, + IN UINT8 MemoryProfile, + OUT INT32 *const Mtb, + OUT INT32 *const Ftb + ) +{ + UINT8 SpdMtbDividend; + UINT8 SpdMtbDivisor; + UINT8 SpdFtbDividend; + UINT8 SpdFtbDivisor; + + + SpdFtbDividend = XmpSpd->Header.FineTimeBase.Bits.Dividend; + SpdFtbDivisor = XmpSpd->Header.FineTimeBase.Bits.Divisor; + SpdMtbDividend = XmpSpd->Header.MediumTimeBase[MemoryProfile].Dividend.Bits.Dividend; + SpdMtbDivisor = XmpSpd->Header.MediumTimeBase[MemoryProfile].Divisor.Bits.Divisor; + + *Ftb = (SpdFtbDivisor == 0) ? 0 : (SpdFtbDividend * MRC_FREQUENCY_FTB_OFFSET) / SpdFtbDivisor; + *Mtb = (SpdMtbDivisor == 0) ? 0 : (SpdMtbDividend * MRC_FREQUENCY_MTB_OFFSET) / SpdMtbDivisor; + + return (*Mtb == 0) ? FALSE : TRUE; +} + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C + +static +MrcFrequency +NbGetDimmFrequency ( + IN UINT32 tCK + ) +{ + UINT32 Index; + MrcFrequency XmpFrequency = fNoInit; + UINT32 NbRangeSize = (sizeof (NbRange) / sizeof (NbTRangeTable)) - 1; + + if(tCK == 0 || tCK == 0xffffffff) return fNoInit; + + for (Index = 0; Index < NbRangeSize; Index++) { + if ((tCK <= NbRange[Index].tCK) && (tCK > NbRange[Index + 1].tCK)) { + XmpFrequency = NbRange[Index].DDRFreq; + break; + } + } + + while (Index) { + if ((NbRange[Index].RefClkFlag & (1 << gMemInfoHobProtocol.MemInfoData.RefClk)) == MRC_REF_CLOCK_133) { + XmpFrequency = NbRange[--Index].DDRFreq; + } else break; + } + + return XmpFrequency; +} +/* +static +BOOLEAN +NbGetDimmFrequency ( + IN SPD_EXTREME_MEMORY_PROFILE *const XmpSpd, + IN UINT8 MemoryProfile, + IN UINT8 DimmCount + ) +{ + INT32 MediumTimebase; + INT32 FineTimebase; + INT32 tCKminMtb; + INT32 tCKminFine; + INT32 tCKmin; + UINT32 NbRangeSize = (sizeof (NbRange) / sizeof (NbTRangeTable)) - 1; + UINT32 Index; + UINT32 TimingMTB; + INT32 TimingFTB; + SPD_EXTREME_MEMORY_PROFILE_DATA *ExtremeData; + NbXmpProfileData *ProfileTimingData; + MrcFrequency XmpFrequency; + UINT32 Calculated; + UINT32 tAAmin; + UINT32 tAAminFine; + + XmpFrequency = fNoInit; + tCKmin = 0; + tCKminMtb = 0; + tCKminFine = 0; + TimingMTB = 0; + TimingFTB = 0; + Calculated = 0; + tAAmin = 0; + tAAminFine = 0; + + ProfileTimingData = &XmpDimm[DimmCount].XmpProfileTiming[MemoryProfile]; + + if(NbGetDimmTimeBase (XmpSpd, MemoryProfile, &MediumTimebase, &FineTimebase)) { + ExtremeData = &XmpSpd->Data[MemoryProfile]; + tCKminMtb = ExtremeData->tCKmin.Bits.tCKmin; + tCKminFine = ExtremeData->tCKminFine.Bits.tCKminFine; + tCKmin = (MediumTimebase * tCKminMtb) + (FineTimebase * tCKminFine); + + for (Index = 0; Index < NbRangeSize; Index++) { + if ((tCKmin <= NbRange[Index].tCK) && (tCKmin > NbRange[Index + 1].tCK)) { + XmpFrequency = NbRange[Index].DDRFreq; + ProfileTimingData->TimingData.tCK = NbRange[Index].tCK; + break; + } + } + + while (Index) { + if ((NbRange[Index].RefClkFlag & (1 << gMemInfoHobProtocol.MemInfoData.RefClk)) == MRC_REF_CLOCK_133) { + XmpFrequency = NbRange[--Index].DDRFreq; + } else break; + } +// *tCKminIndex = Index; + + // tCL + tAAmin = ExtremeData->tAAmin.Bits.tAAmin; + tAAminFine = ExtremeData->tAAminFine.Bits.tAAminFine; + tAAmin = (MediumTimebase * tAAmin) + (FineTimebase * tAAminFine); + ProfileTimingData->TimingData.tCL = (UINT16) ((tAAmin + (ProfileTimingData->TimingData.tCK - 1)) / ProfileTimingData->TimingData.tCK); + ProfileTimingData->TimingData.tCL = MIN (ProfileTimingData->TimingData.tCL, tCL_MAXIMUM); + // tCWL + TimingMTB = ExtremeData->tCWLmin.Bits.tCWLmin; + ProfileTimingData->TimingData.tCWL = ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin; + ProfileTimingData->TimingData.tCWL = MIN (ProfileTimingData->TimingData.tCWL, tCWL_MAXIMUM); + // tWR + TimingMTB = ExtremeData->tWRmin.Bits.tWRmin; + Calculated = ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin; + // + // Special case, tWRmin values of 9, 11, 13, and 15 are not supported by DDR3 Mode Register 0 (MR0). + // If we see one of these values, then add one clock to it in order to make it valid. + // + if ((9 == Calculated) || (11 == Calculated) || (13 == Calculated) || (15 == Calculated)) { + Calculated++; + } + ProfileTimingData->TimingData.tWR = Calculated; + ProfileTimingData->TimingData.tWR = MIN (ProfileTimingData->TimingData.tWR, tWR_MAXIMUM); + // tRRD + TimingMTB = ExtremeData->tRRDmin.Bits.tRRDmin; + ProfileTimingData->TimingData.tRRD = ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin; + ProfileTimingData->TimingData.tRRD = MIN (ProfileTimingData->TimingData.tRRD, tRRD_MAXIMUM); + // tRCD + TimingMTB = ExtremeData->tRCDmin.Bits.tRCDmin; + TimingFTB = ExtremeData->tRCDminFine.Bits.tRCDminFine; + ProfileTimingData->TimingData.tRCD = ((MediumTimebase * TimingMTB) + (FineTimebase * TimingFTB) + (tCKmin - 1)) / tCKmin; + ProfileTimingData->TimingData.tRCD = MIN (ProfileTimingData->TimingData.tRCD, tRCD_MAXIMUM); + // tRP + TimingMTB = ExtremeData->tRPmin.Bits.tRPmin; + TimingFTB = ExtremeData->tRPminFine.Bits.tRPminFine; + ProfileTimingData->TimingData.tRP = ((MediumTimebase * TimingMTB) + (FineTimebase * TimingFTB) + (tCKmin - 1)) / tCKmin; + ProfileTimingData->TimingData.tRP = MIN (ProfileTimingData->TimingData.tRP, tRP_MAXIMUM); + // tRAS + TimingMTB = ((UINT32) (ExtremeData->tRASMintRCMinUpper.Bits.tRASminUpper) << 8) | (UINT32) (ExtremeData->tRASmin.Bits.tRASmin); + ProfileTimingData->TimingData.tRAS = ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin; + ProfileTimingData->TimingData.tRAS = MIN (ProfileTimingData->TimingData.tRAS, tRAS_MAXIMUM); + // tRFC + TimingMTB = ExtremeData->tRFCmin.Bits.tRFCmin; + ProfileTimingData->TimingData.tRFC = ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin; + ProfileTimingData->TimingData.tRFC = MIN (ProfileTimingData->TimingData.tRFC, tRFC_MAXIMUM); + + // tWTR + TimingMTB = ExtremeData->tWTRmin.Bits.tWTRmin; + ProfileTimingData->TimingData.tWTR = ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin; + ProfileTimingData->TimingData.tWTR = MIN (ProfileTimingData->TimingData.tWTR, tWTR_MAXIMUM); + + // tRTP + TimingMTB = ExtremeData->tRTPmin.Bits.tRTPmin; + ProfileTimingData->TimingData.tRTP = ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin; + ProfileTimingData->TimingData.tRTP = MIN (ProfileTimingData->TimingData.tRTP, tRTP_MAXIMUM); + + // tFAW + TimingMTB = ((UINT32) (ExtremeData->tFAWMinUpper.Bits.tFAWminUpper) << 8) | (UINT32) (ExtremeData->tFAWmin.Bits.tFAWmin); + ProfileTimingData->TimingData.tFAW = ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin; + ProfileTimingData->TimingData.tFAW = MIN (ProfileTimingData->TimingData.tFAW, tFAW_MAXIMUM); + + // tRC + TimingMTB = ((UINT32) (ExtremeData->tRASMintRCMinUpper.Bits.tRCminUpper) << 8) | (UINT32) (ExtremeData->tRCmin.Bits.tRCmin); + TimingFTB = ExtremeData->tRCminFine.Bits.tRCminFine; + ProfileTimingData->TimingData.tRC = ((MediumTimebase * TimingMTB) + (FineTimebase * TimingFTB) + (tCKmin - 1)) / tCKmin; + ProfileTimingData->TimingData.tRC = MIN (ProfileTimingData->TimingData.tRC, tRC_MAXIMUM); + + // tREFI + TimingMTB = ExtremeData->tREFImin.Bits.tREFImin; + ProfileTimingData->TimingData.tREFI = (UINT32)Div64 (((Mul64 (MediumTimebase, TimingMTB * TREFIMULTIPLIER) + (tCKmin - 1))), tCKmin, NULL); + ProfileTimingData->TimingData.tREFI = MIN (ProfileTimingData->TimingData.tREFI, tREFI_MAXIMUM); + //NMode + TimingMTB = ExtremeData->SystemCmdRate.Bits.NMode; + if (TimingMTB > 0) { + ProfileTimingData->TimingData.NMode = ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin; + } + } + + ProfileTimingData->DDRFreq = XmpFrequency; + + if (XmpFrequency != fNoInit) return TRUE; + + return FALSE; +} +*/ +#endif +#endif + +EFI_STATUS NbReportXmpInfo( + IN EFI_EVENT Event, + IN VOID *Context +) +{ +/* + EFI_STATUS Status; + EFI_SMBUS_HC_PROTOCOL *Smbus; + SPD_EXTREME_MEMORY_PROFILE XmpSpd; + VOID *SpdData = &XmpSpd; + UINT8 i, DimmCount; + + Status = pBS->LocateProtocol( &gEfiSmbusProtocolGuid, \ + NULL, \ + &Smbus ); + if (EFI_ERROR(Status))return Status; + + + for (i = DIMM1_SMBUS_ADDRESS, DimmCount = 0; DimmCount < 4; i += 2, DimmCount++) { + Status = ReadSpdData(Smbus, i, 176, 2, (UINT8*)SpdData); + if (EFI_ERROR(Status) || (XmpSpd.Header.XmpId != 0x4A0C)) continue; + Status = ReadSpdData(Smbus, i, 176, 79, (UINT8*)SpdData); + if (EFI_ERROR(Status)) continue; + + if(XmpSpd.Header.XmpOrgConf.Bits.ProfileEnable1) { + NBPlatformData.XmpProfile1 = 1; +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C + NbGetDimmFrequency (SpdData, 0, DimmCount); +#endif +#endif + } else continue; + + if(XmpSpd.Header.XmpOrgConf.Bits.ProfileEnable2) { + NBPlatformData.XmpProfile2 = 1; +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C + NbGetDimmFrequency (SpdData, 1, DimmCount); +#endif +#endif + } + } + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C + // Channel 0 XmpProfile 1~2 + XmpChannel[0].XmpProfileTiming[0].DDRFreq = MAX(XmpDimm[0].XmpProfileTiming[0].DDRFreq, XmpDimm[1].XmpProfileTiming[0].DDRFreq); + XmpChannel[0].XmpProfileTiming[1].DDRFreq = MAX(XmpDimm[0].XmpProfileTiming[1].DDRFreq, XmpDimm[1].XmpProfileTiming[1].DDRFreq); + XmpChannel[0].XmpProfileTiming[0].TimingData.tCL = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tCL, XmpDimm[1].XmpProfileTiming[0].TimingData.tCL); + XmpChannel[0].XmpProfileTiming[1].TimingData.tCL = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tCL, XmpDimm[1].XmpProfileTiming[1].TimingData.tCL); + XmpChannel[0].XmpProfileTiming[0].TimingData.tCWL = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tCWL, XmpDimm[1].XmpProfileTiming[0].TimingData.tCWL); + XmpChannel[0].XmpProfileTiming[1].TimingData.tCWL = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tCWL, XmpDimm[1].XmpProfileTiming[1].TimingData.tCWL); + XmpChannel[0].XmpProfileTiming[0].TimingData.tWR = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tWR, XmpDimm[1].XmpProfileTiming[0].TimingData.tWR); + XmpChannel[0].XmpProfileTiming[1].TimingData.tWR = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tWR, XmpDimm[1].XmpProfileTiming[1].TimingData.tWR); + XmpChannel[0].XmpProfileTiming[0].TimingData.tRRD = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tRRD, XmpDimm[1].XmpProfileTiming[0].TimingData.tRRD); + XmpChannel[0].XmpProfileTiming[1].TimingData.tRRD = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tRRD, XmpDimm[1].XmpProfileTiming[1].TimingData.tRRD); + XmpChannel[0].XmpProfileTiming[0].TimingData.tRCD = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tRCD, XmpDimm[1].XmpProfileTiming[0].TimingData.tRCD); + XmpChannel[0].XmpProfileTiming[1].TimingData.tRCD = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tRCD, XmpDimm[1].XmpProfileTiming[1].TimingData.tRCD); + XmpChannel[0].XmpProfileTiming[0].TimingData.tRP = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tRP, XmpDimm[1].XmpProfileTiming[0].TimingData.tRP); + XmpChannel[0].XmpProfileTiming[1].TimingData.tRP = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tRP, XmpDimm[1].XmpProfileTiming[1].TimingData.tRP); + XmpChannel[0].XmpProfileTiming[0].TimingData.tRAS = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tRAS, XmpDimm[1].XmpProfileTiming[0].TimingData.tRAS); + XmpChannel[0].XmpProfileTiming[1].TimingData.tRAS = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tRAS, XmpDimm[1].XmpProfileTiming[1].TimingData.tRAS); + XmpChannel[0].XmpProfileTiming[0].TimingData.tRFC = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tRFC, XmpDimm[1].XmpProfileTiming[0].TimingData.tRFC); + XmpChannel[0].XmpProfileTiming[1].TimingData.tRFC = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tRFC, XmpDimm[1].XmpProfileTiming[1].TimingData.tRFC); + XmpChannel[0].XmpProfileTiming[0].TimingData.tWTR = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tWTR, XmpDimm[1].XmpProfileTiming[0].TimingData.tWTR); + XmpChannel[0].XmpProfileTiming[1].TimingData.tWTR = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tWTR, XmpDimm[1].XmpProfileTiming[1].TimingData.tWTR); + XmpChannel[0].XmpProfileTiming[0].TimingData.tRTP = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tRTP, XmpDimm[1].XmpProfileTiming[0].TimingData.tRTP); + XmpChannel[0].XmpProfileTiming[1].TimingData.tRTP = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tRTP, XmpDimm[1].XmpProfileTiming[1].TimingData.tRTP); + XmpChannel[0].XmpProfileTiming[0].TimingData.tFAW = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tRC, XmpDimm[1].XmpProfileTiming[0].TimingData.tFAW); + XmpChannel[0].XmpProfileTiming[1].TimingData.tFAW = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tRC, XmpDimm[1].XmpProfileTiming[1].TimingData.tFAW); + XmpChannel[0].XmpProfileTiming[0].TimingData.tREFI = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tREFI, XmpDimm[1].XmpProfileTiming[0].TimingData.tREFI); + XmpChannel[0].XmpProfileTiming[1].TimingData.tREFI = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tREFI, XmpDimm[1].XmpProfileTiming[1].TimingData.tREFI); + XmpChannel[0].XmpProfileTiming[0].TimingData.tRC = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tRC, XmpDimm[1].XmpProfileTiming[0].TimingData.tRC); + XmpChannel[0].XmpProfileTiming[1].TimingData.tRC = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tRC, XmpDimm[1].XmpProfileTiming[1].TimingData.tRC); + XmpChannel[0].XmpProfileTiming[0].TimingData.NMode = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.NMode, XmpDimm[1].XmpProfileTiming[0].TimingData.NMode); + XmpChannel[0].XmpProfileTiming[1].TimingData.NMode = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.NMode, XmpDimm[1].XmpProfileTiming[1].TimingData.NMode); + + // Channel 1 XmpProfile 1~2 + XmpChannel[1].XmpProfileTiming[0].DDRFreq = MAX(XmpDimm[2].XmpProfileTiming[0].DDRFreq, XmpDimm[3].XmpProfileTiming[0].DDRFreq); + XmpChannel[1].XmpProfileTiming[1].DDRFreq = MAX(XmpDimm[2].XmpProfileTiming[1].DDRFreq, XmpDimm[3].XmpProfileTiming[1].DDRFreq); + XmpChannel[1].XmpProfileTiming[0].TimingData.tCL = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tCL, XmpDimm[3].XmpProfileTiming[0].TimingData.tCL); + XmpChannel[1].XmpProfileTiming[1].TimingData.tCL = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tCL, XmpDimm[3].XmpProfileTiming[1].TimingData.tCL); + XmpChannel[1].XmpProfileTiming[0].TimingData.tCWL = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tCWL, XmpDimm[3].XmpProfileTiming[0].TimingData.tCWL); + XmpChannel[1].XmpProfileTiming[1].TimingData.tCWL = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tCWL, XmpDimm[3].XmpProfileTiming[1].TimingData.tCWL); + XmpChannel[1].XmpProfileTiming[0].TimingData.tWR = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tWR, XmpDimm[3].XmpProfileTiming[0].TimingData.tWR); + XmpChannel[1].XmpProfileTiming[1].TimingData.tWR = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tWR, XmpDimm[3].XmpProfileTiming[1].TimingData.tWR); + XmpChannel[1].XmpProfileTiming[0].TimingData.tRRD = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tRRD, XmpDimm[3].XmpProfileTiming[0].TimingData.tRRD); + XmpChannel[1].XmpProfileTiming[1].TimingData.tRRD = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tRRD, XmpDimm[3].XmpProfileTiming[1].TimingData.tRRD); + XmpChannel[1].XmpProfileTiming[0].TimingData.tRCD = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tRCD, XmpDimm[3].XmpProfileTiming[0].TimingData.tRCD); + XmpChannel[1].XmpProfileTiming[1].TimingData.tRCD = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tRCD, XmpDimm[3].XmpProfileTiming[1].TimingData.tRCD); + XmpChannel[1].XmpProfileTiming[0].TimingData.tRP = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tRP, XmpDimm[3].XmpProfileTiming[0].TimingData.tRP); + XmpChannel[1].XmpProfileTiming[1].TimingData.tRP = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tRP, XmpDimm[3].XmpProfileTiming[1].TimingData.tRP); + XmpChannel[1].XmpProfileTiming[0].TimingData.tRAS = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tRAS, XmpDimm[3].XmpProfileTiming[0].TimingData.tRAS); + XmpChannel[1].XmpProfileTiming[1].TimingData.tRAS = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tRAS, XmpDimm[3].XmpProfileTiming[1].TimingData.tRAS); + XmpChannel[1].XmpProfileTiming[0].TimingData.tRFC = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tRFC, XmpDimm[3].XmpProfileTiming[0].TimingData.tRFC); + XmpChannel[1].XmpProfileTiming[1].TimingData.tRFC = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tRFC, XmpDimm[3].XmpProfileTiming[1].TimingData.tRFC); + XmpChannel[1].XmpProfileTiming[0].TimingData.tWTR = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tWTR, XmpDimm[3].XmpProfileTiming[0].TimingData.tWTR); + XmpChannel[1].XmpProfileTiming[1].TimingData.tWTR = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tWTR, XmpDimm[3].XmpProfileTiming[1].TimingData.tWTR); + XmpChannel[1].XmpProfileTiming[0].TimingData.tRTP = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tRTP, XmpDimm[3].XmpProfileTiming[0].TimingData.tRTP); + XmpChannel[1].XmpProfileTiming[1].TimingData.tRTP = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tRTP, XmpDimm[3].XmpProfileTiming[1].TimingData.tRTP); + XmpChannel[1].XmpProfileTiming[0].TimingData.tFAW = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tRC, XmpDimm[3].XmpProfileTiming[0].TimingData.tFAW); + XmpChannel[1].XmpProfileTiming[1].TimingData.tFAW = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tRC, XmpDimm[3].XmpProfileTiming[1].TimingData.tFAW); + XmpChannel[1].XmpProfileTiming[0].TimingData.tREFI = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tREFI, XmpDimm[3].XmpProfileTiming[0].TimingData.tREFI); + XmpChannel[1].XmpProfileTiming[1].TimingData.tREFI = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tREFI, XmpDimm[3].XmpProfileTiming[1].TimingData.tREFI); + XmpChannel[1].XmpProfileTiming[0].TimingData.tRC = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tRC, XmpDimm[3].XmpProfileTiming[0].TimingData.tRC); + XmpChannel[1].XmpProfileTiming[1].TimingData.tRC = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tRC, XmpDimm[3].XmpProfileTiming[1].TimingData.tRC); + XmpChannel[1].XmpProfileTiming[0].TimingData.NMode = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.NMode, XmpDimm[3].XmpProfileTiming[0].TimingData.NMode); + XmpChannel[1].XmpProfileTiming[1].TimingData.NMode = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.NMode, XmpDimm[3].XmpProfileTiming[1].TimingData.NMode); + + // Output XmpProfile 1~2 + XmpProfileTiming[0].DDRFreq = MAX(XmpChannel[0].XmpProfileTiming[0].DDRFreq, XmpChannel[1].XmpProfileTiming[0].DDRFreq); + XmpProfileTiming[1].DDRFreq = MAX(XmpChannel[0].XmpProfileTiming[1].DDRFreq, XmpChannel[1].XmpProfileTiming[1].DDRFreq); + XmpProfileTiming[0].TimingData.tCL = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tCL, XmpChannel[1].XmpProfileTiming[0].TimingData.tCL); + XmpProfileTiming[1].TimingData.tCL = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tCL, XmpChannel[1].XmpProfileTiming[1].TimingData.tCL); + XmpProfileTiming[0].TimingData.tCWL = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tCWL, XmpChannel[1].XmpProfileTiming[0].TimingData.tCWL); + XmpProfileTiming[1].TimingData.tCWL = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tCWL, XmpChannel[1].XmpProfileTiming[1].TimingData.tCWL); + XmpProfileTiming[0].TimingData.tWR = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tWR, XmpChannel[1].XmpProfileTiming[0].TimingData.tWR); + XmpProfileTiming[1].TimingData.tWR = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tWR, XmpChannel[1].XmpProfileTiming[1].TimingData.tWR); + XmpProfileTiming[0].TimingData.tRRD = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tRRD, XmpChannel[1].XmpProfileTiming[0].TimingData.tRRD); + XmpProfileTiming[1].TimingData.tRRD = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tRRD, XmpChannel[1].XmpProfileTiming[1].TimingData.tRRD); + XmpProfileTiming[0].TimingData.tRCD = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tRCD, XmpChannel[1].XmpProfileTiming[0].TimingData.tRCD); + XmpProfileTiming[1].TimingData.tRCD = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tRCD, XmpChannel[1].XmpProfileTiming[1].TimingData.tRCD); + XmpProfileTiming[0].TimingData.tRP = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tRP, XmpChannel[1].XmpProfileTiming[0].TimingData.tRP); + XmpProfileTiming[1].TimingData.tRP = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tRP, XmpChannel[1].XmpProfileTiming[1].TimingData.tRP); + XmpProfileTiming[0].TimingData.tRAS = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tRAS, XmpChannel[1].XmpProfileTiming[0].TimingData.tRAS); + XmpProfileTiming[1].TimingData.tRAS = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tRAS, XmpChannel[1].XmpProfileTiming[1].TimingData.tRAS); + XmpProfileTiming[0].TimingData.tRFC = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tRFC, XmpChannel[1].XmpProfileTiming[0].TimingData.tRFC); + XmpProfileTiming[1].TimingData.tRFC = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tRFC, XmpChannel[1].XmpProfileTiming[1].TimingData.tRFC); + XmpProfileTiming[0].TimingData.tWTR = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tWTR, XmpChannel[1].XmpProfileTiming[0].TimingData.tWTR); + XmpProfileTiming[1].TimingData.tWTR = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tWTR, XmpChannel[1].XmpProfileTiming[1].TimingData.tWTR); + XmpProfileTiming[0].TimingData.tRTP = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tRTP, XmpChannel[1].XmpProfileTiming[0].TimingData.tRTP); + XmpProfileTiming[1].TimingData.tRTP = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tRTP, XmpChannel[1].XmpProfileTiming[1].TimingData.tRTP); + XmpProfileTiming[0].TimingData.tFAW = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tFAW, XmpChannel[1].XmpProfileTiming[0].TimingData.tFAW); + XmpProfileTiming[1].TimingData.tFAW = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tFAW, XmpChannel[1].XmpProfileTiming[1].TimingData.tFAW); + XmpProfileTiming[0].TimingData.tREFI = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tREFI, XmpChannel[1].XmpProfileTiming[0].TimingData.tREFI); + XmpProfileTiming[1].TimingData.tREFI = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tREFI, XmpChannel[1].XmpProfileTiming[1].TimingData.tREFI); + XmpProfileTiming[0].TimingData.tRC = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tRC, XmpChannel[1].XmpProfileTiming[0].TimingData.tRC); + XmpProfileTiming[1].TimingData.tRC = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tRC, XmpChannel[1].XmpProfileTiming[1].TimingData.tRC); + XmpProfileTiming[0].TimingData.NMode = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.NMode, XmpChannel[1].XmpProfileTiming[0].TimingData.NMode); + XmpProfileTiming[1].TimingData.NMode = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.NMode, XmpChannel[1].XmpProfileTiming[1].TimingData.NMode); +#endif +#endif + + Status = pRS->SetVariable ( + L"NBPlatformData", + &gSetupGuid, + EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, + sizeof (NB_PLATFORM_DATA), + &NBPlatformData + ); + ASSERT_EFI_ERROR (Status); + + // Kill event + pBS->CloseEvent(Event); +*/ + return EFI_SUCCESS; +} +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/NBGeneric.c b/Chipset/NB/NBGeneric.c new file mode 100644 index 0000000..6f9a95f --- /dev/null +++ b/Chipset/NB/NBGeneric.c @@ -0,0 +1,1782 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBGeneric.c 6 10/14/12 5:17a Jeffch $ +// +// $Revision: 6 $ +// +// $Date: 10/14/12 5:17a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBGeneric.c $ +// +// 6 10/14/12 5:17a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Follow SA RC 0.71. +// [Files] NBPei.c, NBDxe.c; NBGeneric.c; NBCspLib.h; NBSetup.c; +// Nb.sd; GetSetupData.c +// +// 5 10/14/12 12:20a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Update by XTU4.0. +// [Files] NBPei.c, NBDxe.c, NBCspLib.h, NBGeneric.c +// +// 4 9/12/12 6:20a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Fixed some pcie card compatibility issue. <from Jeffch> +// [Files] NBGeneric.c +// +// 3 8/24/12 8:09a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Remove useless SB_SHADOW_CONTROL. +// [Files] NBGeneric.c +// +// 2 4/05/12 2:45a Yurenlai +// [TAG] EIP87103 +// [Category] Spec Update +// [Severity] Important +// [Description] Change for SystemAgent RefCode Revision: 0.5.5 . +// [Files] NBDxe.c, NBPEI.c, NBSMI.C, NBGeneric.cm NB.sd, NBSetup.c, +// GetSetupData.c, NbSetupData. +// +// 1 2/08/12 4:34a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: NBGeneric.C +// +// Description: This file contains generic NB code that is common between +// various components such as NB PEI, DXE etc +// +// Notes: MAKE SURE NO PEI OR DXE SPECIFIC CODE IS NEEDED +// +//<AMI_FHDR_END> +//************************************************************************* + +//---------------------------------------------------------------------------- +// Include(s) +//---------------------------------------------------------------------------- + +#include <Efi.h> +#include <token.h> +#include <AmiLib.h> +#include <AmiCspLib.h> +#include <AmiDxeLib.h> +#include <Protocol\PciRootBridgeIo.h> + +//---------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//---------------------------------------------------------------------------- +// Constant Definition(s) +//--------------------EMRR Support-------------------------------------------- +#define MAX_NR_BUS ((PCIEX_LENGTH/0x100000)-1) +#define UNCORE_CR_MCSEG_BASE0 (volatile UINT64*)NB_PCIE_CFG_ADDRESS(MAX_NR_BUS, 0, 1, 0x60) +#define UNCORE_CR_MCSEG_MASK0_LOW (volatile UINT32*)NB_PCIE_CFG_ADDRESS(MAX_NR_BUS, 0, 1, 0x68) +#define UNCORE_CR_MCSEG_MASK0_HIGH (volatile UINT32*)NB_PCIE_CFG_ADDRESS(MAX_NR_BUS, 0, 1, 0x6C) +#define UNCORE_CR_MCSEG_BASE1 (volatile UINT64*)NB_PCIE_CFG_ADDRESS((MAX_NR_BUS - 1), 0, 1, 0x60) +#define UNCORE_CR_MCSEG_MASK1_LOW (volatile UINT32*)NB_PCIE_CFG_ADDRESS((MAX_NR_BUS - 1), 0, 1, 0x68) +#define UNCORE_CR_MCSEG_MASK1_HIGH (volatile UINT32*)NB_PCIE_CFG_ADDRESS((MAX_NR_BUS - 1), 0, 1, 0x6C) +//---------------------------------------------------------------------------- + +#if CSM_SUPPORT +#define ATTR_DISABLED 0 // Shadow RAM Disabled +#define ATTR_READ 1 // Shadow RAM Read Enabled +#define ATTR_WRITE 2 // Shadow RAM Write Enabled +#define ATTR_READ_WRITE 3 // Shadow RAM Read/Write Enabled +#endif + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//---------------------------------------------------------------------------- +// Variable and External Declaration(s) +//---------------------------------------------------------------------------- +// Variable Declaration(s) + +EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *gPciRootBridgeIo; + +EFI_RUNTIME_SERVICES *pRS; + +//---------------------------------------------------------------------------- +// The following table contains the information regarding the shadow RAM +// registers and other North Bridge registers that need to be restored +// during the S3 wakeup. +// Mention all register address (bus, device, function , register), specify +// the size of the register ans the mask also. +//---------------------------------------------------------------------------- +BOOT_SCRIPT_NB_PCI_REG_SAVE gNbRegsSaveTbl[] = { + {SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_PAM0, EfiBootScriptWidthUint8, 0x33}, + {SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_PAM1, EfiBootScriptWidthUint8, 0x33}, + {SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_PAM2, EfiBootScriptWidthUint8, 0x33}, + {SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_PAM3, EfiBootScriptWidthUint8, 0x33}, + {SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_PAM4, EfiBootScriptWidthUint8, 0x33}, + {SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_PAM5, EfiBootScriptWidthUint8, 0x33}, + {SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_PAM6, EfiBootScriptWidthUint8, 0x33}, + // {SAD_BUS, SAD_DEV, SAD_FUN, SAD_REG_SMRAM, EfiBootScriptWidthUint8, 0xff}, +}; + +#define NUM_NB_PCI_REG_SAVE \ + sizeof(gNbRegsSaveTbl)/sizeof(BOOT_SCRIPT_NB_PCI_REG_SAVE) + +#if CSM_SUPPORT + +/** Porting required for the following structure **/ +NB_PAM_STRUCT gPamStruct[] = +{ + {R_SA_PAM1, 0xfc, 0xc0000, 0x4000}, + {R_SA_PAM1, 0xcf, 0xc4000, 0x4000}, + {R_SA_PAM2, 0xfc, 0xc8000, 0x4000}, + {R_SA_PAM2, 0xcf, 0xcc000, 0x4000}, + {R_SA_PAM3, 0xfc, 0xd0000, 0x4000}, + {R_SA_PAM3, 0xcf, 0xd4000, 0x4000}, + {R_SA_PAM4, 0xfc, 0xd8000, 0x4000}, + {R_SA_PAM4, 0xcf, 0xdc000, 0x4000}, + {R_SA_PAM5, 0xfc, 0xe0000, 0x4000}, + {R_SA_PAM5, 0xcf, 0xe4000, 0x4000}, + {R_SA_PAM6, 0xfc, 0xe8000, 0x4000}, + {R_SA_PAM6, 0xcf, 0xec000, 0x4000}, + {R_SA_PAM0, 0xcf, 0xf0000,0x10000} +}; + +#define NUM_PAM_ENTRIES (sizeof(gPamStruct) / sizeof(NB_PAM_STRUCT)) + +//---------------------------------------------------------------------------- +// Start OF CSM Related Porting Hooks +//---------------------------------------------------------------------------- + +// The following data structure specifies the PCI device/function number of +// the root bridge(s). Number of entries in this table defined by +// ROOT_BRIDGE_COUNT. +// This table is a missing link between RootBridgeIo and PciIo, which allows +// to update BusNumXlat table with actual bus numbers. +// Each entry in the table is a pair of RootBridge UID (UINT32), provided in +// RootBridge device path, and PCI Dev/Func number (UINT8) that can be used +// to access Root Bridge on +// PCI bus. + +// PORTING PORTING - Include device function number of RB + +ROOT_BRIDGE_MAPPING_ENTRY RbMap[ROOT_BRIDGE_COUNT] = { +// RB ID Device function number + {0x00, (UINT8)((NB_DEV << 3) + NB_FUN)} +}; +UINTN RbCount = ROOT_BRIDGE_COUNT; + +#endif +/* +typedef enum { + fNoInit = 0, + f800 = 800, + f1000 = 1000, + f1067 = 1067, + f1200 = 1200, + f1333 = 1333, + f1400 = 1400, + f1600 = 1600, + f1800 = 1800, + f1867 = 1867, + f2000 = 2000, + f2133 = 2133, + f2200 = 2200, + f2400 = 2400, + f2600 = 2600, + f2667 = 2667, + fUnSupport= 0x7FFFFFFF +} NbFrequency; +*/ +#define BCLK_DEFAULT (100 * 1000 * 1000) +#define fNoInit (0) +#define f800 (800) +#define f1000 (1000) +#define f1067 (1067) +#define f1200 (1200) +#define f1333 (1333) +#define f1400 (1400) +#define f1600 (1600) +#define f1800 (1800) +#define f1867 (1867) +#define f2000 (2000) +#define f2133 (2133) +#define f2200 (2200) +#define f2400 (2400) +#define f2600 (2600) +#define f2667 (2667) +#define fUnSupport (0x7FFFFFFF) +typedef UINT32 NbFrequency; +typedef UINT8 NbClockRatio; + +// GUID Definition(s) + +// Protocol Definition(s) + +// External Declaration(s) + +// Function Definition(s) + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: NbFrequencyToRatio +// +// Description: Convert the given frequency and reference clock to a clock ratio. +// +// Input: +// IN Frequency - The memory frequency. +// IN The memory reference clock. +// IN RefBClk - The base system reference clock. +// +// Output: +// Returns the memory clock ratio. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8 +NbFrequencyToRatio ( + UINT32 Frequency, + UINT8 RefClk, + UINT32 RefBClk +) +{ + UINT64 Value; + UINT64 FreqValue; + UINT32 RefClkValue; + UINT32 BClkValue; + + BClkValue = (RefBClk == 0) ? (BCLK_DEFAULT / 100000) : (RefBClk / 100000); + RefClkValue = (RefClk == 1) ? 200000 : 266667; + FreqValue = Mul64 (Frequency, 1000000000ULL); + Value = Div64 (FreqValue, (RefClkValue * BClkValue), NULL); + Value = ((UINT32) Value + 500) / 1000; + + return ((NbClockRatio) Value); + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: NbRatioToFrequency +// +// Description: Convert the given ratio and reference clock to a memory frequency. +// +// Input: +// IN Ratio - The memory ratio. +// IN RefClk - The memory reference clock. +// IN RefBClk - The base system reference clock. +// +// Output: +// Returns the memory frequency. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT32 +NbRatioToFrequency ( + UINT8 Ratio, + UINT8 RefClk, + UINT32 RefBClk +) +{ + + UINT64 Value; + UINT32 BClkValue; + UINT32 RefClkValue; + + BClkValue = (RefBClk == 0) ? BCLK_DEFAULT : RefBClk; + RefClkValue = (RefClk == 1) ? 200000000 : 266666667; + Value = Mul64 (RefClkValue, Ratio * BClkValue); + Value += 50000000000000ULL; + Value = Div64 (Value, (UINTN)100000000000000ULL, NULL); + return ((NbFrequency) Value); +} +//---------------------------------------------------------------------------- +#if CSM_SUPPORT + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: NBGetPamStartEndIndex +// +// Description: Helper function to get the Start and End Index for +// PAM register table. +// +// Input: StartAddress - Shadow RAM start address to be programed +// Length - Shadow RAM length to be programed +// *StartIndex - Pointer a variable for the Start index +// *EndIndex - Pointer a variable for the End index +// +// Output: EFI_STATUS +// EFI_INVALID_PARAMETER - Input Parameter is invalid. +// EFI_SUCCESS - Get indexs from PAM register +// table successfully. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBGetPamStartEndIndex ( + IN UINT32 StartAddress, + IN UINT32 Length, + OUT UINT32 *StartIndex, + OUT UINT32 *EndIndex ) +{ + UINT32 StartIdx; + UINT32 EndIdx; + UINT32 TotalLength = 0; + + if (StartAddress < gPamStruct[0].StartAddress) + return EFI_INVALID_PARAMETER; + + for(StartIdx = 0; StartIdx < NUM_PAM_ENTRIES; ++StartIdx) { + if (StartAddress <= gPamStruct[StartIdx].StartAddress) break; + } + if (StartAddress < gPamStruct[StartIdx].StartAddress) StartIdx--; + + if (StartIdx == NUM_PAM_ENTRIES) return EFI_INVALID_PARAMETER; + + // Adjust the length of the requested region if starting address is + // out of bounds. + Length += (StartAddress - gPamStruct[StartIdx].StartAddress); + + for(EndIdx = StartIdx; EndIdx < NUM_PAM_ENTRIES; ++EndIdx) { + TotalLength += gPamStruct[EndIdx].Length; + if (TotalLength >= Length) break; + } + if (EndIdx == NUM_PAM_ENTRIES) return EFI_INVALID_PARAMETER; + + *StartIndex = StartIdx; + *EndIndex = EndIdx; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBProgramPAMRegisters +// +// Description: Program 0xc0000 - 0xfffff regions to Lock/Unlock. +// +// Input: pBS - Pointer to Boot Service Table +// pRS - Pointer to Runtime Service Table +// StartAddress - Shadow RAM start address to be programed +// Length - Shadow RAM length to be programed +// Setting - Shadow RAM Lock/Unlock status to program +// *Granularity - The granularity for this region +// +// Output: EFI_STATUS +// EFI_INVALID_PARAMETER - Input Parameter is invalid. +// EFI_SUCCESS - Program successfully. +// +// Notes: Here is the control flow of this function: +// 1. Search the structure for the first entry matching +// the StartAddress. +// 2. If not found, return EFI_INVALID_PARAMETER. +// 3. Find the last entry in structure for the region to program, +// by adding the lengths of the entries. +// 4. If not found, return EFI_INVALID_PARAMETER. +// 5. Read/Write each register for the entry to set region. +// 6. Return the Granularity for the region. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBProgramPAMRegisters ( + IN EFI_BOOT_SERVICES *pBS, + IN EFI_RUNTIME_SERVICES *pRS, + IN UINT32 StartAddress, + IN UINT32 Length, + IN UINT8 Setting, + IN OUT UINT32 *Granularity ) +{ + // NB shadow programming. + // Note: For this routine to work, the gPamStruct regions must + // be continuous. + + EFI_STATUS Status = EFI_SUCCESS; + UINT32 StartIndex; + UINT32 EndIndex; + UINTN i; + UINT8 Data; + UINT8 Shift; + + Status = NBGetPamStartEndIndex( StartAddress, \ + Length, \ + &StartIndex, \ + &EndIndex ); + if (EFI_ERROR(Status)) return Status; + + + for (i = StartIndex; i <= EndIndex; ++i) { + //Bus 0, Device 0, Function 0 + Data = READ_PCI8_NB(gPamStruct[i].Register); + Data &= gPamStruct[i].Mask; + Shift = (gPamStruct[i].Mask == 0xfc) ? 0 : 4; + switch (Setting) { + case 0 : // Read Only + case 1 : // Read Only (Permanently) + Data |= (ATTR_READ << Shift); + break; + case 2 : // Read/Write + Data |= (ATTR_READ_WRITE << Shift); + break; + case 3 : // Disabled + default: + break; + } + WRITE_PCI8_NB(gPamStruct[i].Register, Data); + } + + if (Granularity) + *Granularity = ( (StartAddress+Length) < 0xf0000 ) ? 0x4000 : 0x10000; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBPeiProgramPAMRegisters +// +// Description: Program 0xc0000 - 0xfffff regions to Lock/Unlock. +// +// Input: PeiServices - The PEI core services table. +// StartAddress - Shadow RAM start address to be programed +// Length - Shadow RAM length to be programed +// Setting - Shadow RAM Lock/Unlock status to program +// *Granularity - The granularity for this region +// +// Output: EFI_STATUS +// EFI_INVALID_PARAMETER - Input Parameter is invalid. +// EFI_SUCCESS - Program successfully. +// +// Notes: Here is the control flow of this function: +// 1. Search the structure for the first entry matching +// the StartAddress. +// 2. If not found, return EFI_INVALID_PARAMETER. +// 3. Find the last entry in structure for the region to program, +// by adding the lengths of the entries. +// 4. If not found, return EFI_INVALID_PARAMETER. +// 5. Read/Write each register for the entry to set region. +// 6. Return the Granularity for the region. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBPeiProgramPAMRegisters ( + IN EFI_PEI_SERVICES **PeiServices, + IN UINT32 StartAddress, + IN UINT32 Length, + IN UINT8 Setting, + IN OUT UINT32 *Granularity OPTIONAL ) +{ + // NB shadow programming. + // Note: For this routine to work, the gPamStruct regions must + // be continuous. + + EFI_STATUS Status = EFI_SUCCESS; + UINT32 StartIndex; + UINT32 EndIndex; + UINTN i; + UINT8 Data; + UINT8 Shift; + + Status = NBGetPamStartEndIndex( StartAddress, \ + Length, \ + &StartIndex, \ + &EndIndex ); + if (EFI_ERROR(Status)) return Status; + + + for (i = StartIndex; i <= EndIndex; ++i) { + //Bus 0, Device 0, Function 0 + Data = READ_PCI8_NB(gPamStruct[i].Register); + Data &= gPamStruct[i].Mask; + Shift = (gPamStruct[i].Mask == 0xfc) ? 0 : 4; + switch (Setting) { + case 0 : // Read Only + case 1 : // Read Only (Permanently) + Data |= (ATTR_READ << Shift); + break; + case 2 : // Read/Write + Data |= (ATTR_READ_WRITE << Shift); + break; + case 3 : // Disabled + default: + break; + } + WRITE_PCI8_NB(gPamStruct[i].Register, Data); + } + + if (Granularity) + *Granularity = ( (StartAddress+Length) < 0xf0000 ) ? 0x4000 : 0x10000; + + return EFI_SUCCESS; +} + +//---------------------------------------------------------------------------- +#endif // END OF CSM Related Porting Hooks +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBPAMWriteBootScript +// +// Description: Writes the final settings of NB registers to the BOOT Script +// +// Input: *BootScriptSave - Pointer to Boot Script Save Protocal +// +// Output: EFI_STATUS +// EFI_SUCCESS +// +// Notes: Here is the control flow of this function: +// 1. From the Pci register save table, read the pci register +// to save. +// 2. Write to the boot script the value. +// 3. Repeat 1 & 2 for all table entries. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBPAMWriteBootScript ( + IN AMI_S3_SAVE_PROTOCOL *BootScriptSave ) +{ + UINT8 PciBus8; + UINT8 PciSubBus8; + UINTN i; + UINT32 Value32; + UINT64 Address64; + + //Porting required: Write Boot Script + + for (i = 0; i < NUM_NB_PCI_REG_SAVE; ++i) { + Address64 = NB_PCI_CFG_ADDRESS( gNbRegsSaveTbl[i].Bus, \ + gNbRegsSaveTbl[i].Dev, \ + gNbRegsSaveTbl[i].Fun, \ + gNbRegsSaveTbl[i].Reg ); + gPciRootBridgeIo->Pci.Read( gPciRootBridgeIo, \ + gNbRegsSaveTbl[i].Width, \ + Address64, \ + 1, \ + &Value32 ); + Value32 &= gNbRegsSaveTbl[i].Mask; + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( BootScriptSave, \ + gNbRegsSaveTbl[i].Width, \ + Address64, \ + 1, \ + &Value32 ); + } + + PciBus8 = READ_PCI8_PCIEBRN(PCIEBRN_REG_SBUSN); // 0x19 + // Check nVIDIA PCIe VGA card + if (READ_PCI16(PciBus8, 0, 0, PCI_VID) == 0x10de) { + Value32 = READ_PCI32(PciBus8, 0, 0, PCI_SVID); // 0x2c + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( \ + BootScriptSave, \ + EfiBootScriptWidthUint8, \ + PCIEBRN_REG(PCIEBRN_REG_SBUSN), \ + 1, \ + &PciBus8 ); + PciSubBus8 = READ_PCI8_PCIEBRN(PCIEBRN_REG_SUBUSN); // 0x1a + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( \ + BootScriptSave, \ + EfiBootScriptWidthUint8, \ + PCIEBRN_REG(PCIEBRN_REG_SUBUSN), \ + 1, \ + &PciSubBus8 ); + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( \ + BootScriptSave, \ + EfiBootScriptWidthUint32, \ + NB_PCI_CFG_ADDRESS(PciBus8, 0 ,0, 0x40),\ + 1, \ + &Value32 ); + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: NbFindCapPtr +// +// Description: This function searches the PCI address space for the PCI +// device specified for a particular capability ID and returns +// the offset in the PCI address space if one found +// +// Input: UINT64 PciAddress, +// UINT8 CapId +// +// Output: Capability ID Address if one found +// Otherwise returns 0 +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT32 NbFindCapPtr( + IN UINT64 PciAddress, + IN UINT8 CapId +) +{ + UINT8 Value; + UINT32 Address = (UINT32)PciAddress; + + Address = (Address & 0xffffff00) | 6; //PCI Status Register. + Value = READ_MEM8(Address + 0); + + if (Value == 0xff) return 0; // No device. + if (!(Value & (1 << 4))) return 0; // Check if capabilities list. + + *(UINT8*)&Address = 0x34; // Register to First capabilities pointer + // if 0, then capabilities + for(;;) + { + Value = READ_MEM8(Address + 0); + if (Value == 0) return 0; + + *(UINT8*)&Address = Value; // PciAddress = ptr to CapID + Value = READ_MEM8(Address + 0); // New cap ptr. + + //If capablity ID, return register that points to it. + if (Value == CapId) return Address; + + ++Address; // Equals to next capability pointer. + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBRetrainLinkPciDevice +// +// Description: This function is Retrain Link NB Pci Device. +// +// Input: PciBus - PCI Bus Number. +// PciDev - PCI Device Number. +// PciFun - PCI Function Number. +// PciCapPtr - PCI CapPtr Number. +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID NBRetrainLinkPciDevice ( + IN UINT8 PciBus, + IN UINT8 PciDev, + IN UINT8 PciFun, + IN UINT8 CapPtr ) +{ + // Disable Link + SET_PCI8(PciBus, PciDev, PciFun, CapPtr + 0x10, BIT04); + + // Retrain Link + RW_PCI8(PciBus, PciDev, PciFun, CapPtr + 0x10 , BIT05, BIT04); + + // Wait Link States + while (READ_PCI16(PciBus, PciDev, PciFun, CapPtr + 0x12) & BIT11); + + // if Retrain Link Anyway 1, Clear Retrain Link + if (READ_PCI8(PciBus, PciDev, PciFun, CapPtr + 0x10) & BIT05) { + RESET_PCI8(PciBus, PciDev, PciFun, CapPtr + 0x10 , BIT05); + } + + // Wait Link States + while (READ_PCI16(PciBus, PciDev, PciFun, CapPtr + 0x12) & BIT11); +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBProtectedPciDevice +// +// Description: This function is called by PCI Bus Driver before configuring +// or disabling any PCI device. This function should examine the +// Vendor/Device ID or PCI Bus, Device and Function numbers to +// make sure it is not a north bridge device or any other device +// which should no be configured by PCI Bus Driver. +// +// Input: *PciDevice - Pointer to PCI Device Info structure. +// +// Output: EFI_STATUS +// EFI_SUCCESS - SKIP this device, do not touch +// PCI Command register. +// EFI_UNSUPPORTED - DON'T SKIP this device do complete +// enumeration as usual. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBProtectedPciDevice ( + IN PCI_DEV_INFO *PciDevice ) +{ + +//####if ((PciDevice->Address.Addr.Bus == NB_BUS) && \ +//#### (PciDevice->Address.Addr.Device == NB_DEV) && \ +//#### (PciDevice->Address.Addr.Function == NB_FUN)) { +//#### +//#### return EFI_SUCCESS; +//####} + + return EFI_UNSUPPORTED; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBProgramPciDevice +// +// Description: This function is called by PCI Bus Driver before installing +// Protocol Interface for the input device. +// +// Input: *PciDevice - Pointer to PCI Device Info structure. +// +// Output: EFI_SUCCESS +// +// Notes: All resource in the device had been assigned, but the command +// register is disabled. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBProgramPciDevice ( + IN PCI_DEV_INFO *PciDevice ) +{ + +//####if ((PciDevice->Address.Addr.Bus == NB_BUS) && \ +//#### (PciDevice->Address.Addr.Device == NB_DEV) && \ +//#### (PciDevice->Address.Addr.Function == NB_FUN)) { +//#### // Do any porting if needed. +//####} + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBUpdatePciDeviceAttributes +// +// Description: This function is called by PCI Bus Driver, can be used to +// the attributes of the PCI device. +// +// Input: *PciDevice - Pointer to PCI Device Info structure. +// *Attributes - Attributes bitmask which caller whants to +// change. +// Capabilities - The PCI device supports Capabilityes +// Set - Specifies weathere to set or reset given +// "Attributes". +// +// Output: EFI_SUCCESS +// +// Notes: This routine may be invoked twice depend on the device type, +// the first time is at BDS phase, the second is before +// legacy boot. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBUpdatePciDeviceAttributes ( + IN PCI_DEV_INFO *PciDevice, + IN OUT UINT64 *Attributes, + IN UINT64 Capabilities, + IN BOOLEAN Set ) +{ + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBGetTsegBase +// +// Description: Returns the base address of TSEG. +// +// Input: None +// +// Output: UINT32 - The Base Address of TSEG. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT32 NBGetTsegBase (VOID) +{ + return (READ_PCI32_NB(0xB8) & 0xFFF00000); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBEnableEmrr +// +// Description: Enable and lock CPU EMRR. +// +// Input: UINT32 IedStart - Intel Enhanced Debug start. +// UINT32 IedSize - Intel Enhanced Debug size. +// +// Output: VOID +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NBEnableEmrr( + IN UINT32 IedStart, + IN UINT32 IedSize +) +{ + if ((*UNCORE_CR_MCSEG_MASK0_LOW & (1 << 11)) == 0 ) { + *UNCORE_CR_MCSEG_BASE0 = (UINT32)IedStart + 0x200000; + *UNCORE_CR_MCSEG_MASK0_LOW = 0xffe00000; + *UNCORE_CR_MCSEG_MASK0_HIGH = 0xff; + *UNCORE_CR_MCSEG_MASK0_LOW |= (1 << 11); //Enable bit. + *UNCORE_CR_MCSEG_MASK0_LOW |= (1 << 10); //Lock bit. + } + + if ((*UNCORE_CR_MCSEG_MASK1_LOW & (1 << 11)) == 0 ) { + *UNCORE_CR_MCSEG_BASE1 = (UINT32)IedStart + 0x300000; + *UNCORE_CR_MCSEG_MASK1_LOW = 0xffe00000; + *UNCORE_CR_MCSEG_MASK1_HIGH = 0xff; + *UNCORE_CR_MCSEG_MASK1_LOW |= (1 << 11); //Enable bit. + *UNCORE_CR_MCSEG_MASK1_LOW |= (1 << 10); //Lock bit. + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbRuntimeShadowRamWrite +// +// Description: This function provides runtime interface to enable/disable +// writing in E000-F000 segment +// +// Input: IN BOOLEAN Enable - if TRUE - enable writing, if FALSE - disable +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbRuntimeShadowRamWrite( + IN BOOLEAN Enable +) +{ + // Porting Required. + static UINT8 F000Reg = 0xff; // 0x80 + static UINT8 E000Reg = 0xff; // 0x85 + static UINT8 E800Reg = 0xff; // 0x86 + + if (Enable) { + F000Reg = READ_PCI8_NB(R_SA_PAM0); // 0x80 + SET_PCI8_NB(R_SA_PAM0, 0x30); + + E000Reg = READ_PCI8_NB(R_SA_PAM5); // 0x85 + E800Reg = READ_PCI8_NB(R_SA_PAM6); // 0x86 + SET_PCI8_NB(R_SA_PAM5, 0x33); + SET_PCI8_NB(R_SA_PAM6, 0x33); + } else { + if (F000Reg != 0xff) { + WRITE_PCI8_NB(R_SA_PAM0, F000Reg); // 0x80 + WRITE_PCI8_NB(R_SA_PAM5, E000Reg); // 0x85 + WRITE_PCI8_NB(R_SA_PAM6, E800Reg); // 0x86 + } + } + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: CheckPeiFvCopyToRam +// +// Description: Check system is cold or warm boot +// +// Input: PeiServices - The PEI core services table. +// +// Output: PeiFvCopyToRam - TRUE for cold boot. +// - FALSE for warm boot. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN +CheckPeiFvCopyToRam ( + IN EFI_PEI_SERVICES **PeiServices +) +{ + + UINT16 Buff16; + BOOLEAN PeiFvCopyToRam; + + + Buff16 = READ_PCI16_SB(0xA2); + + if (((Buff16 & BIT5) != 0) && ((Buff16 & BIT7) != 0)) + { + PeiFvCopyToRam = FALSE; + + } else { + + PeiFvCopyToRam = TRUE; + } + + if (READ_MEM32_MCH(0x5D10) == 0)PeiFvCopyToRam = TRUE; + + return PeiFvCopyToRam; + +} + +//---------------------------------------------------------------------------- +// Standard PCI Access Routines, No Porting Required. +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ReadPci8 +// +// Description: This function reads an 8bits data from the specific PCI +// register. +// +// Input: Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// +// Output: UINT8 +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT8 ReadPci8 ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg ) +{ + if (Reg >= 0x100) { + return MMIO_READ8(NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg)); + } else { + IoWrite32(NB_PCICFG_SPACE_INDEX_REG, \ + BIT31 | (Bus << 16) | (Dev << 11) | (Fun << 8) | (Reg & 0xfc)); + return IoRead8(NB_PCICFG_SPACE_DATA_REG | (UINT8)(Reg & 3)); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ReadPci16 +// +// Description: This function reads a 16bits data from the specific PCI +// register. +// +// Input: Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// +// Output: UINT16 +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT16 ReadPci16 ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg ) +{ + if (Reg >= 0x100) { + return MMIO_READ16(NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg)); + } else { + IoWrite32(NB_PCICFG_SPACE_INDEX_REG, \ + BIT31 | (Bus << 16) | (Dev << 11) | (Fun << 8) | (Reg & 0xfc)); + return IoRead16(NB_PCICFG_SPACE_DATA_REG | (UINT8)(Reg & 2)); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ReadPci32 +// +// Description: This function reads a 32bits data from the specific PCI +// register. +// +// Input: Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// +// Output: UINT32 +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT32 ReadPci32 ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg ) +{ + if (Reg >= 0x100) { + return MMIO_READ32(NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg)); + } else { + IoWrite32(NB_PCICFG_SPACE_INDEX_REG, \ + BIT31 | (Bus << 16) | (Dev << 11) | (Fun << 8) | (Reg & 0xfc)); + return IoRead32(NB_PCICFG_SPACE_DATA_REG); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WritePci8 +// +// Description: This function writes an 8bits data to the specific PCI +// register. +// +// Input: Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// Value8 - An 8 Bits data will be written to the specific +// PCI register. +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WritePci8 ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT8 Value8 ) +{ + if (Reg >= 0x100) { + WriteMem8((UINT64)NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg), Value8); + } else { + IoWrite32(NB_PCICFG_SPACE_INDEX_REG, \ + BIT31 | (Bus << 16) | (Dev << 11) | (Fun << 8) | (Reg & 0xfc)); + IoWrite8(NB_PCICFG_SPACE_DATA_REG | (UINT8)(Reg & 3), Value8); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WritePci16 +// +// Description: This function writes a 16bits data to the specific PCI +// register. +// +// Input: Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// Value16 - A 16 Bits data will be written to the specific +// PCI register. +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WritePci16 ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT16 Value16 ) +{ + if (Reg >= 0x100) { + WriteMem16((UINT64)NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg), Value16); + } else { + IoWrite32(NB_PCICFG_SPACE_INDEX_REG, \ + BIT31 | (Bus << 16) | (Dev << 11) | (Fun << 8) | (Reg & 0xfc)); + IoWrite16(NB_PCICFG_SPACE_DATA_REG | (UINT8)(Reg & 2), Value16); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WritePci32 +// +// Description: This function writes a 32bits data to the specific PCI +// register. +// +// Input: Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// Value32 - A 32 Bits data will be written to the specific +// PCI register. +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WritePci32 ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT32 Value32 ) +{ + if (Reg >= 0x100) { + WriteMem32((UINT64)NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg), Value32); + } else { + IoWrite32(NB_PCICFG_SPACE_INDEX_REG, \ + BIT31 | (Bus << 16) | (Dev << 11) | (Fun << 8) | (Reg & 0xfc)); + IoWrite32(NB_PCICFG_SPACE_DATA_REG, Value32); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WritePci8S3 +// +// Description: This function writes an 8bits data to the specific PCI +// register and Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// Value8 - An 8 Bits data will be written to the +// specific PCI register and Boot Script. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WritePci8S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT8 Value8 ) +{ + WritePci8(Bus, Dev, Fun, Reg, Value8); + + if (Reg >= 0x100) + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint8, \ + NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + 1, \ + &Value8 ); + else + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint8, \ + NB_PCI_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + 1, \ + &Value8 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WritePci16S3 +// +// Description: This function writes a 16bits data to the specific PCI +// register and Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// Value16 - A 16 Bits data will be written to the +// specific PCI register and Boot Script. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WritePci16S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT16 Value16 ) +{ + + WritePci16(Bus, Dev, Fun, Reg, Value16); + + if (Reg >= 0x100) + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint16, \ + NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + 1, \ + &Value16 ); + else + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint16, \ + NB_PCI_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + 1, \ + &Value16 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WritePci32S3 +// +// Description: This function writes a 32bits data to the specific PCI +// register and Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// Value32 - A 32 Bits data will be written to the +// specific PCI register and Boot Script. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WritePci32S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT32 Value32 ) +{ + + WritePci32(Bus, Dev, Fun, Reg, Value32); + + if (Reg >= 0x100) + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint32, \ + NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + 1, \ + &Value32 ); + else + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint32, \ + NB_PCI_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + 1, \ + &Value32 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwPci8S3 +// +// Description: This function reads an 8bits data from the specific PCI +// register, applies masks, and writes it back, also writes it +// to Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// SetBit8 - Mask of bits to set (1 = Set) +// ResetBit8 - Mask of bits to clear (1 = clear) +// +// Output: None. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwPci8S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT8 SetBit8, + IN UINT8 ResetBit8 ) +{ + RW_PCI8(Bus, Dev, Fun, Reg, SetBit8, ResetBit8); + + ResetBit8 = ~ResetBit8; + + if (Reg >= 0x100) + BOOT_SCRIPT_S3_MEM_READ_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint8, \ + NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + &SetBit8, \ + &ResetBit8 ); + else + BOOT_SCRIPT_S3_PCI_CONFIG_READ_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint8, \ + NB_PCI_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + &SetBit8, \ + &ResetBit8 ); + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwPci16S3 +// +// Description: This function reads a 16bits data from the specific PCI +// register, applies masks, and writes it back, also writes it +// to Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// SetBit16 - Mask of bits to set (1 = Set) +// ResetBit16 - Mask of bits to clear (1 = clear) +// +// Output: None. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwPci16S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT16 SetBit16, + IN UINT16 ResetBit16 ) +{ + RW_PCI16(Bus, Dev, Fun, Reg, SetBit16, ResetBit16); + + ResetBit16 = ~ResetBit16; + + if (Reg >= 0x100) + BOOT_SCRIPT_S3_MEM_READ_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint16, \ + NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + &SetBit16, \ + &ResetBit16 ); + else + BOOT_SCRIPT_S3_PCI_CONFIG_READ_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint16, \ + NB_PCI_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + &SetBit16, \ + &ResetBit16 ); + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwPci32S3 +// +// Description: This function reads a 32bits data from the specific PCI +// register, applies masks, and writes it back, also writes it +// to Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// SetBit32 - Mask of bits to set (1 = Set) +// ResetBit32 - Mask of bits to clear (1 = clear) +// +// Output: None. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwPci32S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT32 SetBit32, + IN UINT32 ResetBit32 ) +{ + RW_PCI32(Bus, Dev, Fun, Reg, SetBit32, ResetBit32); + + ResetBit32 = ~ResetBit32; + + if (Reg >= 0x100) + BOOT_SCRIPT_S3_MEM_READ_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint32, \ + NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + &SetBit32, \ + &ResetBit32 ); + else + BOOT_SCRIPT_S3_PCI_CONFIG_READ_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint32, \ + NB_PCI_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + &SetBit32, \ + &ResetBit32 ); + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteMem8 +// +// Description: This function writes an 8bits data to the specific memory +// (or MMIO) register. +// +// Input: Address - An 64Bits Memory (or MMIO) address +// Value8 - An 8 Bits data will be written to the specific +// PCI register. +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteMem8 ( + IN UINT64 Address, + IN UINT8 Value8 ) +{ + MMIO_WRITE8(Address, Value8); + Value8 = MMIO_READ8(Address); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteMem16 +// +// Description: This function writes a 16bits data to the specific memory +// (or MMIO) register. +// +// Input: Address - A 64Bits Memory (or MMIO) address +// Value16 - A 16 Bits data will be written to the specific +// PCI register. +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteMem16 ( + IN UINT64 Address, + IN UINT16 Value16 ) +{ + MMIO_WRITE16(Address, Value16); + Value16 = MMIO_READ16(Address); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteMem32 +// +// Description: This function writes a 32bits data to the specific memory +// (or MMIO) register. +// +// Input: Address - A 64Bits Memory (or MMIO) address +// Value32 - A 32 Bits data will be written to the specific +// PCI register. +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteMem32 ( + IN UINT64 Address, + IN UINT32 Value32 ) +{ + MMIO_WRITE32(Address, Value32); + Value32 = MMIO_READ32(Address); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwMem8 +// +// Description: This function reads an 8bits data from a specific memory +// (or MMIO) address, applies masks, and writes it back. +// +// Input: Address - A 64Bits Memory (or MMIO) address +// SetBit8 - Mask of bits to set (1 = Set) +// ResetBit8 - Mask of bits to clear (1 = clear) +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwMem8 ( + IN UINT64 Address, + IN UINT8 SetBit8, + IN UINT8 ResetBit8 ) +{ + UINT8 Buffer8 = MMIO_READ8(Address) & ~ResetBit8 | SetBit8; + + WriteMem8(Address, Buffer8); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwMem16 +// +// Description: This function reads a 16bits data from a specific memory +// (or MMIO) address, applies masks, and writes it back. +// +// Input: Address - A 64Bits Memory (or MMIO) address +// SetBit16 - Mask of bits to set (1 = Set) +// ResetBit16 - Mask of bits to clear (1 = clear) +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwMem16 ( + IN UINT64 Address, + IN UINT16 SetBit16, + IN UINT16 ResetBit16 ) +{ + UINT16 Buffer16 = MMIO_READ16(Address) & ~ResetBit16 | SetBit16; + + WriteMem16(Address, Buffer16); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwMem32 +// +// Description: This function reads a 32bits data from a specific memory +// (or MMIO) address, applies masks, and writes it back. +// +// Input: Address - A 64Bits Memory (or MMIO) address +// SetBit32 - Mask of bits to set (1 = Set) +// ResetBit32 - Mask of bits to clear (1 = clear) +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwMem32 ( + IN UINT64 Address, + IN UINT32 SetBit32, + IN UINT32 ResetBit32 ) +{ + UINT32 Buffer32 = MMIO_READ32(Address) & ~ResetBit32 | SetBit32; + + WriteMem32(Address, Buffer32); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteMem8S3 +// +// Description: This function writes an 8bits data to a specific memory +// (or MMIO) address and Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Address - A 64Bits Memory (or MMIO) address +// Value8 - An 8Bits data writes to the address. +// +// Output: None. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteMem8S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT8 Value8 ) +{ + + WriteMem8(Address, Value8); + + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( mBootScriptSave, \ + EfiBootScriptWidthUint8, \ + Address, \ + 1, \ + &Value8 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteMem16S3 +// +// Description: This function writes a 16bits data to a specific memory +// (or MMIO) address and Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Address - A 64Bits Memory (or MMIO) address +// Value16 - A 16Bits data writes to the address. +// +// Output: None. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteMem16S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT16 Value16 ) +{ + WriteMem16(Address, Value16); + + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( mBootScriptSave, \ + EfiBootScriptWidthUint16, \ + Address, \ + 1, \ + &Value16 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteMem32S3 +// +// Description: This function writes a 32bits data to a specific memory +// (or MMIO) address and Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Address - A 64Bits Memory (or MMIO) address +// Value32 - A 32Bits data writes to the address. +// +// Output: None. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteMem32S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT32 Value32 ) +{ + + WriteMem32(Address, Value32); + + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( mBootScriptSave, \ + EfiBootScriptWidthUint32, \ + Address, \ + 1, \ + &Value32 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwMem8S3 +// +// Description: This function reads an 8bits data from a specific memory +// (or MMIO) address, applies masks, and writes it back, also +// writes it to Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Address - A 64Bits Memory (or MMIO) address +// SetBit8 - Mask of bits to set (1 = Set) +// ResetBit8 - Mask of bits to clear (1 = clear) +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwMem8S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT8 SetBit8, + IN UINT8 ResetBit8 ) +{ + RwMem8(Address, SetBit8, ResetBit8); + + ResetBit8 = ~ResetBit8; + BOOT_SCRIPT_S3_MEM_READ_WRITE_MACRO( mBootScriptSave, \ + EfiBootScriptWidthUint8, \ + Address, \ + &SetBit8, \ + &ResetBit8 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwMem16S3 +// +// Description: This function reads a 16bits data from a specific memory +// (or MMIO) address, applies masks, and writes it back, also +// writes it to Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Address - A 64Bits Memory (or MMIO) address +// SetBit16 - Mask of bits to set (1 = Set) +// ResetBit16 - Mask of bits to clear (1 = clear) +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwMem16S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT16 SetBit16, + IN UINT16 ResetBit16 ) +{ + RwMem16(Address, SetBit16, ResetBit16); + + ResetBit16 = ~ResetBit16; + BOOT_SCRIPT_S3_MEM_READ_WRITE_MACRO( mBootScriptSave, \ + EfiBootScriptWidthUint16, \ + Address, \ + &SetBit16, \ + &ResetBit16 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwMem32S3 +// +// Description: This function reads a 32bits data from a specific memory +// (or MMIO) address, applies masks, and writes it back, also +// writes it to Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Address - A 64Bits Memory (or MMIO) address +// SetBit32 - Mask of bits to set (1 = Set) +// ResetBit32 - Mask of bits to clear (1 = clear) +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwMem32S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT32 SetBit32, + IN UINT32 ResetBit32 ) +{ + RwMem32(Address, SetBit32, ResetBit32); + + ResetBit32 = ~ResetBit32; + BOOT_SCRIPT_S3_MEM_READ_WRITE_MACRO( mBootScriptSave, \ + EfiBootScriptWidthUint32, \ + Address, \ + &SetBit32, \ + &ResetBit32 ); +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/NBPEI.c b/Chipset/NB/NBPEI.c new file mode 100644 index 0000000..52f61f4 --- /dev/null +++ b/Chipset/NB/NBPEI.c @@ -0,0 +1,3039 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBPEI.c 57 5/28/14 3:03a Dennisliu $ +// +// $Revision: 57 $ +// +// $Date: 5/28/14 3:03a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBPEI.c $ +// +// 57 5/28/14 3:03a Dennisliu +// [TAG] EIP161790 +// [Category] Improvement +// [Description] DRAM Init BIT should be set after saving MRC S3 data to +// NVRAM in DXE Phase as Intel suggested. +// [Files] NBPei.c; NBDxe.c; +// +// 56 8/14/13 6:44a Ireneyang +// [TAG] EIP129631 +// [Category] BrugFix +// [Symptom] RBU function is not working +// [Description] 1. The current make file doesn¡¦t build *.hdr file, +// we can use that file to verify RBU function under DOS. +// 2. We could build *.hdr file manually, and also verified +// the RBU function under DOS. But the RBU function is +// not working. +// [Files] MemoryInit.sdl; MemoryInit.c; NBPEI.c; +// +// 55 6/26/13 4:35a Ireneyang +// [TAG] None +// [Category] Improvement +// [Description] Add new related items into structure. +// [Files] NBPEI.c; +// +// 53 6/03/13 2:04a Ireneyang +// [TAG] None +// [Category] Improvement +// [Description] Fix some PEG cards can't be detected. +// [Files] NBPEI.c; +// +// 52 5/22/13 6:41a Ireneyang +// [TAG] None +// [Category] Improvement +// [Description] Add Token SG_GPIO_SUPPORT for GpioSupport. +// [Files] NB.sdl; NBPEI.c; +// +// 51 5/13/13 6:26a Ireneyang +// [TAG] None +// [Category] Improvement +// [Description] Add PanelPowerEnable for enabling/disabling VDD force +// bit. +// (Required only for early enabling of eDP panel) +// [Files] NBSetup.c; GetSetupData.c; NbSetupData.h; NBPEI.c; +// +// 50 5/09/13 7:20a Ireneyang +// [TAG] EIP119332 +// [Category] BrugFix +// [Symptom] Some PEG Lan Cards on NorthBridge would cause hanging +// issue when waking through them. +// [RootCause] These Lan cards on NorthBridge do not clear PME for Nb's +// slots. Therefore, this causes hanging issue. +// [Solution] Checking if this PEG card is Lan card. If it's, then +// clear PME status. +// [Files] NBPEI.c; +// +// 48 5/09/13 7:08a Ireneyang +// [TAG] EIP118377 +// [Category] BugFix +// [Symptom] System became resuming from S5 when system is resuming +// from S4. +// [Description] Reproducing steps (UEFI OS) +// 1. Boot into USB key, run afudos.exe +// 2. Remove USB key. +// 3. Warm reset and don't press any key. +// 4. Screen will show "Reboot and select proper Boot +// device... +// No boot option" +// 5. Warm reset and press DEL to enter BIOS setup. +// 6. Change "Launch Video OpROM policy" to "UEFI only". +// 7. Save and reset. +// 8. Press DEL key to enter BIOS setup. +// 9. Change "Launch CSM" to "Disable" +// 10. Save and reset,enter OS(UEFI WIN8) +// 11. Open any file and do "Hibernate" to enter inot S4. +// 12. Power on, resuming back from S4 to desktop, the file +// would be disappeared. It looks like it doesn't resume +// back from S4 but S5. +// [RootCause] It's out of variable type for S4 resume. +// [Solution] The variable type should be +// "PreviousMemoryTypeInformation" +// but MemoryTypeInformation. +// [Files] NBPEI.c +// +// 47 4/01/13 11:48p Ireneyang +// [TAG] None +// [Severity] Improvement +// [Description] Reduce boot time through PEG. +// [Files] NB.mak; NBDxe.c; NBPEI.c; NBPPI.h; Sa.asl; +// PcieComplex.c; GraphicsInit.c; PciExpressInit.c; +// +// 46 3/14/13 1:37a Ireneyang +// [TAG] None +// [Severity] Improvement +// [Description] Fix some PEG card with no VGA can't work normally under +// SG mode. +// [Files] NBPEI.c; +// +// 45 3/07/13 6:14a Ireneyang +// [TAG] None +// [Severity] Improvement +// [Description] Make some default SaPlatformPolicy items flexible. +// Define some SaPlatformPolicy items into NB_SETUP_DATA +// structure. +// [Files] NbSetupData.h; GetSetupData.c; NBPEI.c; +// +// 44 3/07/13 3:53a Ireneyang +// [TAG] None +// [Severity] Improvement +// [Description] Add "Hot only" option for Memory Refresh 2x support to +// meet Intel Spec. +// [Files] NBPEI.c; NB.uni; NB.sd; NbSetupData.h; GetSetupData.c; +// +// 43 3/04/13 3:16a Ireneyang +// [TAG] EIP115090 +// [Category] Improvement +// [Description] Memory data hasn't been cleared after running MRC base +// memory test. +// [Files] NB.sdl; NBPEI.c; +// +// 41 2/09/13 10:23a Jeffch +// [TAG] None +// [Severity] Spec update +// [Description] Update SA RC 1.1.0 +// [Files] NBPei.c; GetSetupData.c; NbSetupData.h; NBDXE.c; +// +// 40 1/28/13 5:54a Jeffch +// [TAG] None +// [Severity] Spec update +// [Description] Update SA RC 1.0. +// [Files] NBPei.c; GetSetupData.c; NbSetupData.h; NBDXE.c; +// NB.sd; NB.uni; NBDxeBoard.c +// +// 39 1/21/13 3:55a Jeffch +// [TAG] None +// [Severity] Bug Fix +// [Description] Fixed RMT memory type error issue for ULT. +// [Files] NBPei.c; +// +// 38 1/15/13 4:07a Jeffch +// [TAG] None +// [Severity] Bug Fix +// [Description] Changed MRC error report status for SA RC 0.90. +// [Files] NBPei.c; MemoryInit.c; +// +// 37 1/14/13 6:06a Jeffch +// [TAG] None +// [Severity] Spec update +// [Description] Create setup item for SA RC 0.90. +// [Files] NBPei.c; GetNbSetupData.c NB.sd; NB.uni; +// +// 36 1/10/13 5:57a Jeffch +// +// [TAG] None +// [Severity] Important +// [Description] Create DDR PowerDown and idle counter for setup item. +// [Files] NBPei.c; NB.sd; NB.uni; GetSetupData.c; NbSetupData.h +// +// 35 1/03/13 7:27a Jeffch +// [TAG] None +// [Severity] Spec update +// [Description] Follow MRC error report status. +// [Files] NBPei.c +// [TAG] None +// [Severity] Improvement +// [Description] Use SG GPIO ULT by token. +// [Files] NBPei.c +// +// 34 12/24/12 2:55a Jeffch +// [TAG] None +// [Category] Improvement +// [Description] added ULT SKU auto disable PEG. +// [Files] NBPei.c; NBDxe.c; NbPlatform.h; NB.sd; +// [TAG] None +// [Category] Bug Fix +// [Description] Remove tRPab and fixed XTU build fail issue. +// [Files] NBPei.c; NBDxe.c; NB.sd; +// +// 33 12/22/12 2:26a Jeffch +// [TAG] None +// [Severity] Spec update +// [Description] Create setup item for SA RC 0.81. +// [Files] NBPei.c; GetNbSetupData.c NB.sd; NB.uni; +// [TAG] None +// [Severity] Bug Fix +// [Description] Fxied XTU MRC Timing bug. +// [Files] NBPei.c; +// +// 32 12/18/12 5:14a Jeffch +// [TAG] None +// [Severity] Spec update +// [Description] Update SA RC 0.81. +// [Files] NBDxe.c; NBPei.c +// +// 31 12/03/12 5:56a Jeffch +// [TAG] None +// [Category] Improvement +// [Description] optimize DetectNonComplaint function. +// [Description] NBPEI.c, NBPPI.h, NBDxe.c +// [TAG] None +// [Category] Improvement +// [Description] Change for mxm SgDgpuPwrEnable->Active = +// ACTIVE_dGPU_PWR_EN. +// [Description] NBPEI.c, NBPPI.h, NBDxe.c +// +// 30 11/28/12 9:52p Jeffch +// [TAG] DetectNonComplaint +// [Category] Improvement +// [Description] added peg DetectNonComplaint function. +// +// 29 11/20/12 2:41a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Update SA RC 0.80. +// [Files] NBDxe.c; NBPei.c +// +// 28 11/14/12 5:37a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Update XTU4.x function +// [Files] NBPei.c; GetSetupData.c; NbSetupData.h; NBDXE.c; NB.sd; +// NB.uni +// +// 27 11/12/12 12:11a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Change name SMRAMC to R_SA_SMRAMC for build error. +// [Files] NBPei.c; +// +// 26 11/07/12 6:19a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Support ULT one BIOS +// [Files] NBPei.c; GetSetupData.c; NbSetupData.h +// +// 25 10/30/12 7:05a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Update SA RC 0.72. +// [Files] NBDxe.c; NBPei.c +// +// 2 10/22/12 6:38a Jeffch +// +// 24 10/18/12 11:04p Jeffch +// [TAG] None +// [Severity] Important +// [Description] Support Disable AB SEG. +// [Files] NBPei.c; +// +// 23 10/16/12 9:38a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Remove invalid code. +// [Files] NBPei.c; +// +// 22 10/14/12 5:17a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Follow SA RC 0.71. +// [Files] NBPei.c, NBDxe.c; NBGeneric.c; NBCspLib.h; NBSetup.c; +// Nb.sd; GetSetupData.c +// +// 21 10/14/12 12:21a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Update by XTU4.0. +// [Files] NBPei.c, NBDxe.c, NBCspLib.h, NBGeneric.c +// [TAG] None +// [Severity] Important +// [Description] Follow Update by Mahobay. +// [Files] NBPei.c, NBDxe.c; +// +// 20 9/28/12 4:12a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] BDAT function support. +// [Files] NB.sd, NBDxe.c, NBPEI.c, SystemAgent.sdl, +// BdatAccessHandler.sdl +// +// 19 9/26/12 9:20a Yurenlai +// [TAG] None +// [Category] Update +// [Severity] Important +// [Description] Changed for Shark Bay SA Framework Reference Code Beta +// Version 0.7.0. +// [Files] NBPEI.c +// +// [TAG] EIP101495 +// [Category] Improvement +// [Severity] Important +// [Description] Initialize SSID of B0:D3:F0 and B0:D2:F0/F1. +// [Files] NB.h, NB.sdl, NBPEI.c +// +// 18 9/12/12 6:15a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Add RxCEM Loop back setup item. +// [Files] GetSetupData.c, NB.sd, NB.uni, NBPEI.c, NbSetupData.h, +// NBPEI.c, +// +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Modified for Switchable Graphics support. +// [Files] NBPEI.c, SwitchableGraphicsInit.c, SystemAgent.sdl +// +// 17 8/24/12 8:15a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Corrected GTT reference define. +// [Files] NBDxe.c, NBPEI.c +// +// 16 7/27/12 8:34a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] IGfx Fource Disable Support. +// [Files] GetSetupData.c, NB.sdl, NB.sd, NB.uni, NbSetupData.h, +// NBDxe.c, NBPEI.c +// +// 15 7/03/12 11:25p Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Fix building error. +// [Files] NBPEI.c +// +// 14 7/03/12 6:44a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Change for SystemAgent RefCode Revision: 0.6.0. +// [Files] NBPEI.DXS, NB.sd, NBDxe.c, NBPEI.c +// +// 13 6/14/12 4:49a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Add Notify BeforeMrc and AfterMrc. +// [Description] NBPEI.c, NBPPI.h, MemoryInit. +// +// 12 6/14/12 4:47a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Fixed S4 resume fail. +// [Description] NBPEI.c +// +// 11 4/26/12 2:52a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Adjust Intel System Agent module the Setup item and +// Policy. +// [Description] GetSetupData.c, NB.sdl, NB.sd, NB.uni, NBDxe.c, +// NBPEI.c, +// NBSetup.c, NBSetupReset.c, NbSetupData.h +// +// 10 4/26/12 2:39a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Fixed PeiRamBootSupport = 1 warm boot system is hang. +// [Description] NBPEI.c, NBCspLib.h +// +// 9 4/26/12 2:35a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Support Locate MRC error Report. +// [Description] NBPEI.c, MemoryInit.c +// +// 8 4/05/12 4:46a Yurenlai +// +// [TAG] None +// [Category] New Feature +// [Severity] Normal +// [Description] Enabled GDXC feature. +// [Files] NBPEI.c +// +// 7 4/05/12 2:43a Yurenlai +// [TAG] EIP87103 +// [Category] Spec Update +// [Severity] Important +// [Description] Add routine RetrieveGdxcMemorySize to support GDXC +// feature and SA RC rev. 0.5.5. +// [Files] NBPEI.c +// +// 6 4/05/12 2:39a Yurenlai +// [TAG] EIP87103 +// [Category] Spec Update +// [Severity] Important +// [Description] Change for SystemAgent RefCode Revision: 0.5.5 . +// [Files] NBDxe.c, NBPEI.c, NBSMI.C, NBGeneric.c, NB.sd, NBSetup.c, +// GetSetupData.c, NbSetupData.h +// +// 5 3/23/12 3:32a Yurenlai +// Fixed the build error of Help Builder. +// +// 4 3/22/12 11:08p Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Fixed MRC_DEBUG_PRINT = 0 for not send MRC debug message. +// [Files] NBPEI.c, MemoryInit.sdl, MrcOemDebugPrint.h +// +// 3 3/08/12 10:30p Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Support MRC debug message print information and RMT +// message. +// [Files] NBPEI.c +// +// 2 2/23/12 6:45a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Adjusted North Bridge the policy configuration. +// +// 1 2/08/12 4:34a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: NBPEI.C +// +// Description: This file contains code for North Bridge initialization +// in the PEI stage +// +//<AMI_FHDR_END> +//************************************************************************* + +//---------------------------------------------------------------------------- +// Include(s) +//---------------------------------------------------------------------------- + +#include <Efi.h> +#include <Pei.h> +#include <token.h> +#include <HOB.h> +#include <StatusCodes.h> +#include <AmiLib.h> +#include <AmiPeiLib.h> +#include <AmiCspLib.h> + +#include <ppi\PciCfg2.h> +#include <ppi\CpuIo.h> +#include <ppi\NBPPI.h> +#include <ppi\CspLibPpi.h> +#include <ppi\smbus.h> +#include <ppi\ReadOnlyVariable2.h> +#include <Setup.h> +#include <CpuHobs.h> + +#include <Core\EM\ACPI\AcpiS3.h> + +#include <Protocol\NBMemInfo.h> + +#include <Core\GUID\MemoryTypeInformation.h> + +// Produced PPIs +#include <ppi\BaseMemorytest.h> + +#if SystemAgent_SUPPORT +#include <PchAccess.h> +#include <MemInfoHob.h> +#include <SaDataHob\SaDataHob.h> +#define _SA_COMMON_DEFINITIONS_H_ +#include <Ppi\SaPlatformPolicy\SaPlatformPolicy.h> +#include <SampleCode\Ppi\PlatformMemorySize\PlatformMemorySize.h> +#include <SampleCode\Ppi\PlatformMemoryRange\PlatformMemoryRange.h> +#endif + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C +#include <PPI\PerfTunePpi.h> +#endif +#endif + +#if SB_STALL_PPI_SUPPORT +#include <Ppi\Stall.h> +#endif + +#include <Ppi\Wdt\Wdt.h> + +#ifdef SSA_FLAG +#define __EDKII_GLUE_PEIM_H__ +#include "SsaCallbackPeim.h" +#include "MrcOem.h" +#endif // SSA_FLAG + +//---------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//---------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +VOID NBResetCpuOnly ( // Do CPU Only Reset + IN EFI_PEI_SERVICES **PeiServices +); + +VOID ProgramNBSubId ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg +); + +EFI_STATUS BaseMemoryTest ( + IN EFI_PEI_SERVICES **PeiServices, + IN struct _PEI_BASE_MEMORY_TEST_PPI *This, + IN EFI_PHYSICAL_ADDRESS BeginAddress, + IN UINT64 MemoryLength, + IN PEI_MEMORY_TEST_OP Operation, + OUT EFI_PHYSICAL_ADDRESS *ErrorAddress +); + +EFI_STATUS +EFIAPI +ChooseRanges ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_PLATFORM_MEMORY_RANGE_PPI *This, + IN OUT PEI_MEMORY_RANGE_OPTION_ROM *OptionRomMask, + IN OUT PEI_MEMORY_RANGE_SMRAM *SmramMask, + IN OUT PEI_MEMORY_RANGE_GRAPHICS_MEMORY *GraphicsMemoryMask, + IN OUT PEI_MEMORY_RANGE_PCI_MEMORY *PciMemoryMask +); + +EFI_STATUS +EFIAPI +GetPlatformMemorySize ( + IN EFI_PEI_SERVICES **PeiServices, + IN struct _PEI_PLATFORM_MEMORY_SIZE_PPI *This, + IN OUT UINT64 *MemorySize +); + +EFI_STATUS NBPeiBeforeMrcPei ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *InvokePpi +); + +EFI_STATUS NBPeiEndOfMrcPei ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *InvokePpi +); + +EFI_STATUS ProgramNBRegBeforeEndofPei ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *InvokePpi +); + +EFI_STATUS CreateCPUHob( + IN EFI_PEI_SERVICES **PeiServices +); + +VOID +GtOcInit ( + IN EFI_PEI_SERVICES **PeiServices, + IN NB_SETUP_DATA *NbSetupData +); + +EFI_STATUS +InstallSaPlatformPolicyPpi ( + IN EFI_PEI_SERVICES **PeiServices, + IN NB_SETUP_DATA *NbSetupData +); + +#ifdef SSA_FLAG +MrcStatus +AmiSsaCallbackPpi ( + EFI_PEI_SERVICES **PeiServices, + struct _SSA_BIOS_CALLBACKS_PPI *SsaBiosCallBacksPpi, + MRC_OEM_STATUS_COMMAND StatusCommand, + VOID *CheckpointData +); +#endif // SSA_FLAG + +EFI_STATUS +MemoryErrorRead ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_MEMORY_ERROR_REPORT_PPI *This, + IN OUT UINT32 MemErrData +); + + +//---------------------------------------------------------------------------- +// Variable and External Declaration(s) +//---------------------------------------------------------------------------- +// Variable Declaration(s) + +// GUID Definition(s) +EFI_GUID gAmiNbPegInfoGuid = AMI_NB_PEG_INFO_GUID; +EFI_GUID gAmiPEINbInitPolicyGuid = AMI_PEI_NBINIT_POLICY_PPI_GUID; +EFI_GUID gBaseMemoryTestGuid = PEI_BASE_MEMORY_TEST_GUID; +EFI_GUID gEfiPeiEndOfPeiPhasePpiGuid = EFI_PEI_END_OF_PEI_PHASE_PPI_GUID; +EFI_GUID gAmiNbInfoHobGuid = AMI_NB_INFO_HOB_GUID; +EFI_GUID gMrcInfoHobGuid = AMI_MRC_INFO_HOB_GUID; +//EFI_GUID gEfiNBMemoryInfoGuid = EFI_NB_MEMORY_INFO_GUID; +EFI_GUID gEfiNbMrcS3DataGuid = EFI_NB_MRC_S3_DATA_GUID; +EFI_GUID gSetupGuid = SETUP_GUID; +EFI_GUID gAmiMemoryErrorReportPpiGuid = AMI_MEMORY_ERROR_REPORT_PPI_GUID; +EFI_GUID gWdtPpiGuid = WDT_PPI_GUID; +#if SB_STALL_PPI_SUPPORT +EFI_GUID gStallPpiGuid = EFI_PEI_STALL_PPI_GUID; +#endif +#if SystemAgent_SUPPORT +EFI_GUID gSaPlatformPolicyPpiGuid = SA_PLATFORM_POLICY_PPI_GUID; +EFI_GUID gMemRestoreDataGuid = EFI_MEMORY_RESTORE_DATA_GUID; +EFI_GUID gAmiNbPegGen3PresetSearchGuid = AMI_NB_PEG_GEN3_PRESET_SEARCH_GUID; +EFI_GUID gPlatformMemorySizeGuid = PEI_PLATFORM_MEMORY_SIZE_PPI_GUID; +EFI_GUID gPlatformMemoryRangeGuid = PEI_PLATFORM_MEMORY_RANGE_PPI_GUID; +EFI_GUID gEfiMemoryTypeInformationGuid = EFI_MEMORY_TYPE_INFORMATION_GUID; +#endif +EFI_GUID gEfiGlobalVariableGuid = EFI_GLOBAL_VARIABLE; + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C +static EFI_GUID gPerfTunePpiGuid = PERF_TUNE_PPI_GUID; +EFI_GUID gAmiDddtPreFlagHobGuid = AMI_DDDT_PRESENT_FLAG_HOB_GUID; +#endif +#endif + +// PPI Definition(s) + +// PPI that are installed +static AMI_PEI_NBINIT_POLICY_PPI gAMIPEINBInitPolicyPpi = { + TRUE +}; + +static PEI_PLATFORM_MEMORY_SIZE_PPI mMemorySize = { + GetPlatformMemorySize +}; + +static PEI_PLATFORM_MEMORY_RANGE_PPI mPlatformMemoryRange = { + ChooseRanges +}; + + +static PEI_BASE_MEMORY_TEST_PPI gBaseMemoryTest = { + BaseMemoryTest +}; + +static EFI_PEI_NB_CPU_ONLY_RESET_PPI gNBCpuOnlyResetPpi = { + NBResetCpuOnly +}; + + +#ifdef SSA_FLAG +static SSA_BIOS_CALLBACKS_PPI gAmiSsaCallbackPpi = { + 0, + AmiSsaCallbackPpi, + NULL +}; +#endif // SSA_FLAG +static PEI_MEMORY_ERROR_REPORT_PPI gPeiMemoryErrorReportPpi = { + MemoryErrorRead +}; + + +// Include any additional PPI needed for memory detection in this +// list and define the functions in this file + +static EFI_PEI_PPI_DESCRIPTOR mPpiList[] = { +#ifdef SSA_FLAG + { EFI_PEI_PPI_DESCRIPTOR_PPI, + &gSsaBiosCallBacksPpiGuid, + &gAmiSsaCallbackPpi}, +#endif // SSA_FLAG + { EFI_PEI_PPI_DESCRIPTOR_PPI, + &gAmiMemoryErrorReportPpiGuid, + &gPeiMemoryErrorReportPpi }, + + { EFI_PEI_PPI_DESCRIPTOR_PPI, \ + &gPlatformMemorySizeGuid, \ + &mMemorySize }, + { EFI_PEI_PPI_DESCRIPTOR_PPI, \ + &gPlatformMemoryRangeGuid, \ + &mPlatformMemoryRange }, + { EFI_PEI_PPI_DESCRIPTOR_PPI, \ + &gBaseMemoryTestGuid, \ + &gBaseMemoryTest }, + { EFI_PEI_PPI_DESCRIPTOR_PPI, \ + &gAmiPeiNBCpuOnlyResetPpiGuid, \ + &gNBCpuOnlyResetPpi }, + { (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), \ + &gAmiPEINbInitPolicyGuid, \ + &gAMIPEINBInitPolicyPpi } +}; + +// PPI that are notified + +static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = { + { EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK, \ + &gAmiPeiBeforeMrcGuid, NBPeiBeforeMrcPei }, + { EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK, \ + &gAmiPeiEndOfMemDetectGuid, NBPeiEndOfMrcPei }, + { EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | \ + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, \ + &gEfiPeiEndOfPeiPhasePpiGuid, ProgramNBRegBeforeEndofPei }, +}; + +// External Declaration(s) + +// Function Definition(s) + +UINT32 NBPcieBridge[] = +{ + {(UINT32)NB_PCIE_CFG_ADDRESS(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, PCI_VID)}, + {(UINT32)NB_PCIE_CFG_ADDRESS(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN1, PCI_VID)}, + {(UINT32)NB_PCIE_CFG_ADDRESS(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN2, PCI_VID)}, + {0xFFFFFFFF} +}; +// << (EIP69780) + +//(EIP96114) +// Type Definition(s) +typedef struct { + UINT8 Bus; + UINT8 Dev; + UINT8 Fun; + UINT16 PegBitOffset; +} DEVICES_AFTER_PCIIO; + +DEVICES_AFTER_PCIIO gDevicesTable[] = { + { PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN2, B_SA_DEVEN_D1F2EN_MASK }, + { PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN1, B_SA_DEVEN_D1F1EN_MASK }, + { PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, B_SA_DEVEN_D1F0EN_MASK }, + { 0xFF, 0xFF, 0xFF, 0, }, +}; + +UINTN gDevicesTableCount = sizeof(gDevicesTable) / sizeof(DEVICES_AFTER_PCIIO); +//(EIP96114) + +#ifdef RC_PEG_0 +DEVICES_AFTER_PCIIO gDisablePegDevicesTable[] = { +#if RC_PEG_0 == 0 + { PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, NULL }, +#endif +#if !(defined RC_PEG_1) || RC_PEG_1 == 0 + { PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN1, NULL }, +#endif +#if !(defined RC_PEG_2) || RC_PEG_2 == 0 + { PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN2, NULL }, +#endif + { 0xFF, 0xFF, 0xFF, NULL } +}; + +UINTN gDisablePegCount = sizeof(gDisablePegDevicesTable) / sizeof(DEVICES_AFTER_PCIIO); +#endif + +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBPEI_Init +// +// Description: This function is the entry point for this PEI. +// it must be ported to do NB specific programming needed +// at power-on, both in wakeup path as well as power-on path. +// +// Input: FfsHeader Pointer to the FFS file header +// PeiServices Pointer to the PEI services table +// +// Output: Return Status based on errors that occurred while waiting for +// time to expire. +// +// Notes: This function should initialize North Bridge before memory +// detection. +// Install AMI_PEI_NBINIT_POLICY_PPI to indicate that NB Init +// PEIM is installed +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EFIAPI NBPEI_Init ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices ) +{ + + EFI_STATUS Status; + EFI_PEI_PCI_CFG2_PPI *PciCfg; + EFI_PEI_CPU_IO_PPI *CpuIo; + NB_SETUP_DATA *NbSetupData = NULL; +#if defined SIO_SUPPORT && SIO_SUPPORT == 1// For SIO off. Without this compiler fails +#if defined SIO_Smsc1007 && SIO_Smsc1007 == 1 + UINT8 GpioDataReg3; +#endif +#endif + + // Get pointer to the PCI config PPI + PciCfg = (*PeiServices)->PciCfg; + CpuIo = (*PeiServices)->CpuIo; + + PEI_PROGRESS_CODE (PeiServices, PEI_CAR_NB_INIT); + + //Create CPU HOB + CreateCPUHob(PeiServices); + + // + // Allocate buffer for setup data variable. + // + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (NB_SETUP_DATA), &NbSetupData); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) NbSetupData, sizeof (NB_SETUP_DATA), 0); + + GetNbSetupData( PeiServices, NbSetupData, TRUE ); + + // Disable IGFX for UpSever +#if defined NB_IGFX_FORCE_DISABLE_SUPPORT && NB_IGFX_FORCE_DISABLE_SUPPORT == 1 + if(NbSetupData->IGfxForceDisable == 1) + { + NbSetupData->InternalGraphics = 0; // disable IGFX + NbSetupData->PrimaryDisplay = 1; // PEG Only + } +#endif // NB_IGFX_FORCE_DISABLE_SUPPORT + +#if defined SMM_THUNK_IN_CSM && SMM_THUNK_IN_CSM == 0 + // Enable Global SMRAM + SET_PCI8_NB(R_SA_SMRAMC, 8); // 0x88 +#else +#if defined SMM_THUNK_NO_AB_SEG && SMM_THUNK_NO_AB_SEG == 1 + // Enable Global SMRAM + SET_PCI8_NB(R_SA_SMRAMC, 8); // 0x88 +#endif +#endif + + // Install the NB Init Policy PPI + Status = (*PeiServices)->InstallPpi(PeiServices, &mPpiList[0]); + ASSERT_PEI_ERROR (PeiServices, Status); + + // Set up necessary PPI notifications + Status = (*PeiServices)->NotifyPpi( PeiServices, &mNotifyList[0] ); + ASSERT_PEI_ERROR ( PeiServices, Status ); + + // Program SSID + ProgramNBSubId( PeiServices, PciCfg ); + + // Install SaPlatformPolicyPpi + InstallSaPlatformPolicyPpi (PeiServices, NbSetupData); + +#if defined SIO_SUPPORT && SIO_SUPPORT == 1// For SIO off. Without this compiler fails +#if defined SIO_Smsc1007 && SIO_Smsc1007 == 1 + // Set up PWM or GMBus(I2C) panel backlight inverter. + // General Purpose I/O Data Register 3, this is not a config reg, so no need to enter config mode. + // From CRB schematic BIOS Note: Disable both BKLTSEL lines before enabling one. + GpioDataReg3 = READ_IO8(Smsc1007_PME_BASE_ADDRESS + 0x0E); + GpioDataReg3 |= (BIT07 | BIT01); + WRITE_IO8(Smsc1007_PME_BASE_ADDRESS + 0x0E, GpioDataReg3); + + // Program SIO to switch inverter + if ((NbSetupData->IgdLcdBlc == 0) || (NbSetupData->IgdLcdBlc == 2)) { + + // PWM backlight control + // Choose L_BKLTSEL0# via GPIO37 to enable PWM backlight control + GpioDataReg3 &= ~BIT07; // L_BKLTSEL0# + } else { + + // GMBus backlight control(also known as I2C) + // Choose L_BKLTSEL1# via GPIO31 to enable GMBus to support backlight control + GpioDataReg3 &= ~BIT01; // L_BKLTSEL1# + } + + WRITE_IO8(Smsc1007_PME_BASE_ADDRESS + 0x0E, GpioDataReg3); +#endif +#endif + + return EFI_SUCCESS; +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBResetCpuOnly +// +// Description: This function issues a CPU only reset. +// +// Input: PeiServices - Pointer to the PEI services table +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NBResetCpuOnly ( // Do CPU Only Reset + IN EFI_PEI_SERVICES **PeiServices ) +{ + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ProgramNBSubId +// +// Description: This function programs NB PCI devices sub-vendor ID and +// sub-system ID. +// +// Input: PeiServices - Pointer to the PEI services table +// PciCfg - Pointer to the PCI Configuration PPI +// +// Output: VOID +// +// Notes: 1. This routine only programs the PCI device in NB, hence, we +// have to check the bus/device/function numbers whether they +// are a NB PCI device or not. +// 2. This routine is invoked by PEI phase.(After PEI permantent +// memory be installed) +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID ProgramNBSubId ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg ) +{ + EFI_STATUS Status = EFI_SUCCESS; + AMI_PEI_NB_CUSTOM_PPI *NBPeiOemPpi; + UINTN i = 0; + UINT8 SsidReg = 0; + UINT32 PciSid = 0xffffffff; + AMI_NB_PCI_SSID_TABLE_STRUCT DefaultSIdTbl[] = {NB_PCI_DEVICES_SSID_TABLE}; + AMI_NB_PCI_SSID_TABLE_STRUCT *SsidTblPtr = DefaultSIdTbl; + + Status = (*PeiServices)->LocatePpi( PeiServices, \ + &gAmiPeiNBCustomPpiGuid, \ + 0, \ + NULL, \ + &NBPeiOemPpi ); + + if (Status == EFI_SUCCESS) { + if (NBPeiOemPpi->SsidTable != NULL) + SsidTblPtr = NBPeiOemPpi->SsidTable; + } + + while (SsidTblPtr[i].PciAddr != 0xffffffffffffffff) { + if ((SsidTblPtr[i].PciAddr == NB_BUS_DEV_FUN) || \ + (SsidTblPtr[i].PciAddr == NB_IGD_BUS_DEV_FUN) || \ + (SsidTblPtr[i].PciAddr == NB_IGD_BUS_DEV_FUN1) || \ + (SsidTblPtr[i].PciAddr == NB_HDA_BUS_DEV_FUN) || \ + (SsidTblPtr[i].PciAddr == NB_PCIEBRNx16_BUS_DEV_FUN) || \ + (SsidTblPtr[i].PciAddr == NB_PCIEBRNx8_BUS_DEV_FUN) || \ + (SsidTblPtr[i].PciAddr == NB_PCIEBRNx4_BUS_DEV_FUN)) \ + { + if (SsidTblPtr[i].Sid == 0xffffffff) { + Status = PciCfg->Read( PeiServices, + PciCfg, + EfiPeiPciCfgWidthUint32, + SsidTblPtr[i].PciAddr, + &PciSid); + } else { + PciSid = SsidTblPtr[i].Sid; + } + + SsidReg = PCI_SVID; + + if((SsidTblPtr[i].PciAddr == NB_PCIEBRNx16_BUS_DEV_FUN) || \ + (SsidTblPtr[i].PciAddr == NB_PCIEBRNx8_BUS_DEV_FUN) || \ + (SsidTblPtr[i].PciAddr == NB_PCIEBRNx4_BUS_DEV_FUN) || \ + (SsidTblPtr[i].PciAddr == NB_PCIEBRN_BUS_DEV6_FUN)) + { + SsidReg = R_SA_PEG_SS_OFFSET; + } + + Status = PciCfg->Write( PeiServices, + PciCfg, + EfiPeiPciCfgWidthUint32, + SsidTblPtr[i].PciAddr | SsidReg, + &PciSid); + + } + + i++; + } + + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBPeiBeforeMrcPei +// +// Description: This function can be Call NB PEI before Mrc. +// +// Input: PeiServices - Pointer to the PEI services table +// NotifyDescriptor - Pointer to the descriptor for the +// notification event. +// InvokePpi - Pointer to the PPI that was installed +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBPeiBeforeMrcPei ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *InvokePpi ) +{ + EFI_STATUS Status = EFI_SUCCESS; + EFI_PEI_CPU_IO_PPI *CpuIo; + EFI_PEI_PCI_CFG2_PPI *PciCfg; + + CpuIo = (*PeiServices)->CpuIo; + PciCfg = (*PeiServices)->PciCfg; + + PEI_TRACE((TRACE_ALWAYS, PeiServices, "NBPeiBeforeMrc Start.\n")); + + PEI_TRACE((TRACE_ALWAYS, PeiServices, "NBPeiBeforeMrc end.\n")); + + return Status; +} + +//(EIP96114) +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbPegDetectNonComplaint +// +// Description: This function is Detect peg NonComplaint devices. +// +// Input: PeiServices - Pointer to the PEI services table +// NB_SETUP_DATA - NbSetupData - NB Setup data stored in NVRAM +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID NbPegDetectNonComplaint ( + IN EFI_PEI_SERVICES **PeiServices, + IN NB_SETUP_DATA *NbSetupData +) +{ +// UINT16 DetectCount; +// UINT16 Count; + UINT16 i; + UINT8 PegBus; + UINT8 PegDev; + UINT8 PegFun; + UINT16 PegBitMap = 0; + EFI_STATUS Status = EFI_SUCCESS; + NB_PEG_INFO_HOB *NbPegInfoHob; + BOOLEAN CardDetect[sizeof(gDevicesTable) / sizeof(DEVICES_AFTER_PCIIO)] = {FALSE}; + + Status = (*PeiServices)->CreateHob (PeiServices, EFI_HOB_TYPE_GUID_EXTENSION, sizeof (NB_PEG_INFO_HOB), (VOID **) &NbPegInfoHob); + if (EFI_ERROR (Status)) return ; + + NbPegInfoHob->Header.Name = gAmiNbPegInfoGuid; + + for ( i = 0; i < gDevicesTableCount; i++) + { + PegBus = gDevicesTable[i].Bus; + PegDev = gDevicesTable[i].Dev; + PegFun = gDevicesTable[i].Fun; + NbPegInfoHob->PegDeOverride[PegFun] = NbSetupData->PegDeEmphasis[PegFun]; + + if (READ_PCI32(PegBus, PegDev, PegFun, 0) == 0xffffffff) continue; + + WRITE_PCI32 (PegBus, PegDev, PegFun, PCI_PBUS, 0x00010100); + WRITE_PCI16 (1, 0, 0, PCI_VID, 0); + CountTime(4000, PM_BASE_ADDRESS); // 1ms + if(READ_PCI8 (PegBus, PegDev, PegFun, R_SA_PEG_SLOTSTS_OFFSET) & BIT06) { + if(READ_PCI16 (1, 0, 0, PCI_VID) != 0xffff) { + WRITE_PCI32 (PegBus, PegDev, PegFun, PCI_PBUS, 0x00000000); + CardDetect[i] = TRUE; + continue; + } + } + + RW_PCI8(PegBus, PegDev, PegFun, 0xD0, 0x01, 0xff); // Gen 1 + CountTime(4000, PM_BASE_ADDRESS); // 1ms + if(READ_PCI8 (PegBus, PegDev, PegFun, R_SA_PEG_SLOTSTS_OFFSET) & BIT06) { + if(READ_PCI16 (1, 0, 0, PCI_VID) != 0xffff) { + NbPegInfoHob->PegDeOverride[PegFun] = 0; // Set 6DB. + CardDetect[i] = TRUE; + } + } + + WRITE_PCI32 (PegBus, PegDev, PegFun, PCI_PBUS, 0x00000000); + } + if (NbSetupData->AlwaysEnablePeg != 1) { + + for ( i = 0; i < gDevicesTableCount; i++) { + + PegBus = gDevicesTable[i].Bus; + PegDev = gDevicesTable[i].Dev; + PegFun = gDevicesTable[i].Fun; + + if (READ_PCI32(PegBus, PegDev, PegFun, 0) == 0xffffffff) continue; + + if (CardDetect[i]) { + continue; + } else { + + // if devices insert D1 F1 or F2, do not disable F0. + if(PegFun == 0 && (CardDetect[0] || CardDetect[1])) break; + PegBitMap |= gDevicesTable[i].PegBitOffset; + SET_MEM8 (NB_PCIE_CFG_ADDRESS(PegBus, PegDev, PegFun, R_SA_PEG_LCTL_OFFSET), BIT4); + SET_MEM8 (NB_PCIE_CFG_ADDRESS(PegBus, PegDev, PegFun, R_SA_PEG_DEBUP2_OFFSET), BIT0); + } + } + + // Disable Peg + RESET_PCI16_NB(R_SA_DEVEN, PegBitMap); // 0x54 + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbClearPegCtrlRegVgaEnable +// +// Description: This function is Clear PEG 0x3E bit3 for 3D card. +// +// Input: PeiServices - Pointer to the PEI services table +// NB_SETUP_DATA - NbSetupData - NB Setup data stored in NVRAM +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID NbClearPegCtrlRegVgaEnable ( + IN EFI_PEI_SERVICES **PeiServices, + IN NB_SETUP_DATA *NbSetupData +) +{ + UINT16 i; + UINT8 PegBus; + UINT8 PegDev; + UINT8 PegFun; + + for ( i = 0; i < gDevicesTableCount; i++) + { + PegBus = gDevicesTable[i].Bus; + PegDev = gDevicesTable[i].Dev; + PegFun = gDevicesTable[i].Fun; + if (READ_PCI32(PegBus, PegDev, PegFun, 0) == 0xffffffff) continue; + if ((READ_PCI8 (PegBus, PegDev, PegFun, R_SA_PEG_SLOTSTS_OFFSET) & BIT06) == 0) continue; // 0xBA + + WRITE_PCI32 (PegBus, PegDev, PegFun, PCI_PBUS, 0x00010100); + WRITE_PCI16 (1, 0, 0, PCI_VID, 0); + + // Clear Peg VgaEnable + RESET_PCI8(PegBus, PegDev, PegFun, PCI_BRIDGE_CNTL, BIT03); + WRITE_PCI32 (PegBus, PegDev, PegFun, PCI_PBUS, 0x00000000); + } +} +//(EIP73801) +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBPeiEndOfMrcPei +// +// Description: This function can be Call NB PEI after Mrc. +// +// Input: PeiServices - Pointer to the PEI services table +// NotifyDescriptor - Pointer to the descriptor for the +// notification event. +// InvokePpi - Pointer to the PPI that was installed +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBPeiEndOfMrcPei ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *InvokePpi ) +{ + EFI_STATUS Status = EFI_SUCCESS; + EFI_PEI_CPU_IO_PPI *CpuIo; + EFI_PEI_PCI_CFG2_PPI *PciCfg; + NB_SETUP_DATA *NbSetupData = NULL; +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 0 + WDT_PPI *WdtPpi = NULL; +#endif + EFI_BOOT_MODE BootMode; // [ EIP161790 ] + + + CpuIo = (*PeiServices)->CpuIo; + PciCfg = (*PeiServices)->PciCfg; + + PEI_TRACE((TRACE_ALWAYS, PeiServices, "NBPeiAfterMrc Start.\n")); + + // + // Allocate buffer for setup data variable. + // + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (NB_SETUP_DATA), &NbSetupData); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) NbSetupData, sizeof (NB_SETUP_DATA), 0); + + GetNbSetupData( PeiServices, NbSetupData, TRUE ); + + + // Set DRAM Initialization Bit. + //if ((READ_PCI8_SB(SB_REG_GEN_PMCON_2) & BIT07) == 0) // [ EIP161790 ] + //{ + // SET_PCI8_SB(SB_REG_GEN_PMCON_2, BIT07); // 0xA2 + //} + Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode); + if ((!EFI_ERROR (Status)) && (BootMode == BOOT_ON_S3_RESUME)) + { + if ((READ_PCI8_SB(SB_REG_GEN_PMCON_2) & BIT07) == 0) + { + SET_PCI8_SB(SB_REG_GEN_PMCON_2, BIT07); // 0xA2 + } + } + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 0 + // + // Locate WDT PPI for access to Wdt->Disable() + // + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gWdtPpiGuid, + 0, + NULL, + &WdtPpi + ); + if (!EFI_ERROR (Status)) { + WdtPpi->Disable(); + } +#endif + +//(EIP96114) + +#if (defined RC_PEG_0) && RC_PEG_0 == 1 + if (NbSetupData->DetectNonComplaint && NbSetupData->AlwaysEnablePeg != 2) + { + // Peg Detect NonComplaint devices. + NbPegDetectNonComplaint(PeiServices, NbSetupData); + } +#endif + + // if SG and have pGPU + if (READ_PCI32(0, 2, 0, 0) != 0xffffffff && NbSetupData->PrimaryDisplay == 4) { + // Clear PEG 0x3E bit3 for SG mode. + NbClearPegCtrlRegVgaEnable(PeiServices, NbSetupData); + } + + PEI_TRACE((TRACE_ALWAYS, PeiServices, "NBPeiAfterMrc end.\n")); + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ProgramNBRegBeforeEndofPei +// +// Description: This function can be used to program any NB regisater before +// end of PEI phase. +// +// Input: PeiServices - Pointer to the PEI services table +// NotifyDescriptor - Pointer to the descriptor for the +// notification event. +// InvokePpi - Pointer to the PPI that was installed +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS ProgramNBRegBeforeEndofPei ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *InvokePpi ) +{ + EFI_STATUS Status = EFI_SUCCESS; + EFI_PEI_CPU_IO_PPI *CpuIo; + EFI_PEI_PCI_CFG2_PPI *PciCfg; + EFI_BOOT_MODE BootMode; + UINTN PegAddress; + UINT8 CapPtr = 0; + UINT8 i = 0; + UINT8 PrimaryBus, SecondaryBus; + CpuIo = (*PeiServices)->CpuIo; + PciCfg = (*PeiServices)->PciCfg; + + Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode); + + if (BootMode == BOOT_ON_S3_RESUME) { + // Porting if needed. + + for (i = 0; NBPcieBridge[i] != 0xFFFFFFFF; i++) + { + if (READ_MEM32(NBPcieBridge[i]) == 0xFFFFFFFF) continue; + if (!(READ_MEM8(NBPcieBridge[i] + R_SA_PEG_SLOTSTS_OFFSET) & BIT06)) continue; + + PrimaryBus = READ_MEM8 (NBPcieBridge[i] + PCI_PBUS + 1); + SecondaryBus = READ_MEM8 (NBPcieBridge[i] + PCI_PBUS + 2); + + for (; PrimaryBus <= SecondaryBus; PrimaryBus++) { + PegAddress = NB_PCIE_CFG_ADDRESS(PrimaryBus, 0, 0, 0); + + // Network Card. + if (READ_MEM8(PegAddress + 0x0B) == 0x02) { + // Find Cap ID 0x01 + CapPtr = NbFindCapPtr(PegAddress, 0x01); + if(CapPtr != 0) { + // Clear PME status + SET_MEM16((PegAddress + CapPtr + 0x04), BIT15); + } + } + } + + // Clear root port PME status + SET_MEM8((NBPcieBridge[i] + 0xC2), BIT01); + } + + } + + return EFI_SUCCESS; +} + +//---------------------------------------------------------------------------- +// BaseMemoryTest +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: BaseMemoryTest +// +// Description: This function performs the base memory test. +// +// Input: PeiServices - Pointer to the PEI services table +// This - Pointer to the Base Memory Test PPI +// BeginAddress - The begin address for test. +// MemoryLength - The length in byte for test. +// Operation - The memort test operated policy. +// ErrorAddress - The error address when test is failed. +// +// Output: EFI_STATUS +// EFI_DEVICE_ERROR - Tge base memory test is failure. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS BaseMemoryTest ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_BASE_MEMORY_TEST_PPI *This, + IN EFI_PHYSICAL_ADDRESS BeginAddress, + IN UINT64 MemoryLength, + IN PEI_MEMORY_TEST_OP Operation, + OUT EFI_PHYSICAL_ADDRESS *ErrorAddress ) +{ + +#if defined PEI_MRC_BASE_MEMORY_TEST_ENABLE && PEI_MRC_BASE_MEMORY_TEST_ENABLE == 1 + UINT32 TestPattern; + UINT32 TestMask; + UINT32 SpanSize; + EFI_PHYSICAL_ADDRESS TempAddress; + +#if defined PeiRamBootSupport && PeiRamBootSupport == 1 + if(!CheckPeiFvCopyToRam(PeiServices)) return EFI_SUCCESS; +#endif + + (*PeiServices)->ReportStatusCode ( + PeiServices, + EFI_PROGRESS_CODE, + EFI_COMPUTING_UNIT_MEMORY + EFI_CU_MEMORY_PC_TEST, + 0, + NULL, + NULL + ); + + TestPattern = 0x5A5A5A5A; + TestMask = 0; + SpanSize = 0; + + // + // Make sure we don't try and test anything above the max physical address range + // + ASSERT_PEI_ERROR (PeiServices, BeginAddress + MemoryLength < 0xFFFFFFFFFFFFFFFF); + + switch (Operation) { + case Extensive: + SpanSize = 0x4; + break; + case Sparse: + case Quick: + SpanSize = 0x40000; + break; + case Ignore: + return EFI_SUCCESS; + } + + // + // Write the test pattern into memory range + // + TempAddress = BeginAddress; + while (TempAddress < BeginAddress + MemoryLength) { + (*(UINT32*)(UINTN)TempAddress) = TestPattern; + TempAddress += SpanSize; + } + + // + // Read pattern from memory and compare it + // + TempAddress = BeginAddress; + while (TempAddress < BeginAddress + MemoryLength) { + if ((*(UINT32*)(UINTN)TempAddress) != TestPattern) { + *ErrorAddress = TempAddress; + (*PeiServices)->ReportStatusCode ( + PeiServices, + EFI_ERROR_CODE + EFI_ERROR_UNRECOVERED, + EFI_COMPUTING_UNIT_MEMORY + EFI_CU_MEMORY_EC_UNCORRECTABLE, + 0, + NULL, + NULL + ); + return EFI_DEVICE_ERROR; + } else { + (*(UINT32*)(UINTN)TempAddress) = 0; + } + TempAddress += SpanSize; + } +#endif + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ChooseRanges +// +// Description: Find out which memory ranges to reserve on this platform +// +// Input: PeiServices - Pointer to the PEI services table. +// This - Pointer to the Pei platform memory range ppi. +// OptionRomMask - The reserve for option ROM usage. +// SmramMask - The reserve for smram usage. +// GraphicsMemoryMask - The reserve for graphics memory usage. +// PciMemoryMask - The reserve for Pei Memory usage. +// +// Output: +// EFI_STATUS - EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +ChooseRanges ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_PLATFORM_MEMORY_RANGE_PPI *This, + IN OUT PEI_MEMORY_RANGE_OPTION_ROM *OptionRomMask, + IN OUT PEI_MEMORY_RANGE_SMRAM *SmramMask, + IN OUT PEI_MEMORY_RANGE_GRAPHICS_MEMORY *GraphicsMemoryMask, + IN OUT PEI_MEMORY_RANGE_PCI_MEMORY *PciMemoryMask + ) +{ + UINT16 GraphicsControlRegister; + UINT32 IgdSize; + UINT32 GttSize; + EFI_STATUS Status; + SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi; +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C + VOID *FirstHob; + DDDT_PRESENT_FLAG_HOB *DddtPreFlagHob; + UINT8 NumOcBins = (UINT8)(ReadMsr(0x194) >> 17) & 0x7; + Status = (*PeiServices)->GetHobList(PeiServices, &FirstHob); + ASSERT_PEI_ERROR(PeiServices, Status); + + // Get XTU devices Present HOB + DddtPreFlagHob = (DDDT_PRESENT_FLAG_HOB*) FirstHob; + while (!EFI_ERROR(Status = FindNextHobByType(EFI_HOB_TYPE_GUID_EXTENSION, &DddtPreFlagHob))) { + if (guidcmp(&((EFI_HOB_GUID_TYPE*)DddtPreFlagHob)->Name, &gAmiDddtPreFlagHobGuid) == 0) { + break; + } + } + + // default XTU graphics Present is disable + DddtPreFlagHob->PresentFlag[BIOS_GRAPHICS_TURBO_RATIO_LIMIT_IMPLEMENTATION] = 0; + DddtPreFlagHob->PresentFlag[BIOS_GRAPHICS_CORE_VOLTAGE_IMPLEMENTATION] = 0; + + //If cpu is lock version then clear runtime turbo DDD table flag. + if(NumOcBins == 0) + DddtPreFlagHob->PresentFlag[BIOS_RUNTIME_TURBO_OVERRIDE_IMPLEMENTATION] = 0; +#endif +#endif + + // + // Get platform policy settings through the SaPlatformPolicy PPI + // + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gSaPlatformPolicyPpiGuid, + 0, + NULL, + &SaPlatformPolicyPpi + ); + if (EFI_ERROR (Status))SaPlatformPolicyPpi->GtConfig->InternalGraphics = 2; + // + // Choose regions to reserve for Option ROM usage. + // + *OptionRomMask = PEI_MR_OPTION_ROM_NONE; + + // + // Choose regions to reserve for SMM usage. + // Each block is 128KB which is defined in PlatformRange PPI. + // Needs to convert the value of TSEG_SIZE from bytes to blocks. + // + *SmramMask = (TSEG_SIZE >> 17) | PEI_MR_SMRAM_CACHEABLE_MASK | +#if defined SMM_THUNK_IN_CSM && SMM_THUNK_IN_CSM == 0 + PEI_MR_SMRAM_ABSEG_MASK | +#else +#if defined SMM_THUNK_NO_AB_SEG && SMM_THUNK_NO_AB_SEG == 1 + PEI_MR_SMRAM_ABSEG_MASK | +#endif +#endif + PEI_MR_SMRAM_TSEG_MASK; + + // + // Choose regions to reserve for Graphics Memory usage. + // + *GraphicsMemoryMask = PEI_MR_GRAPHICS_MEMORY_NONE; + + GraphicsControlRegister = READ_PCI16_NB (R_SA_GGC); + if (((GraphicsControlRegister & B_SA_GGC_IVD_MASK) == 0) || (SaPlatformPolicyPpi->GtConfig->InternalGraphics == 1)) { + // + // IGD is enabled, fill the IGD and GTT stolen memory sizes. + // + IgdSize = (GraphicsControlRegister & B_SA_GGC_GMS_MASK) >> N_SA_GGC_GMS_OFFSET; + + // + // Add a w/a to handle 1G Stolen Memory - As per SNB ConfigDB definition, + // Max No of bits to support this encoding is '5' 0/0/0/GGC[7:3] which can + // hold a value of '1Fh'. + // For 1G, suggested encoding is '11h'. Set the GraphicsMemoryMask as '2048' + // to reserve 1G stolen memory. + // + // *GraphicsMemoryMask = IgdSize * PEI_MR_GRAPHICS_MEMORY_32M_NOCACHE; + // *GraphicsMemoryMask = 32 * 64 + // *GraphicsMemoryMask = 2048 + + if (IgdSize == 0x11) { + IgdSize = 0x20; + } + + *GraphicsMemoryMask = IgdSize * PEI_MR_GRAPHICS_MEMORY_32M_NOCACHE; + + // + // Add GTT memory to reserved graphics memory + // + GttSize = (GraphicsControlRegister & B_SA_GGC_GGMS_MASK) >> N_SA_GGC_GGMS_OFFSET; + + switch (GttSize) { + case 1: + *GraphicsMemoryMask += PEI_MR_GRAPHICS_MEMORY_1M_NOCACHE; + break; + + case 2: + *GraphicsMemoryMask += PEI_MR_GRAPHICS_MEMORY_2M_NOCACHE; + break; + } + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C + // if IGD is enabled ,XTU graphics Present is enable + DddtPreFlagHob->PresentFlag[BIOS_GRAPHICS_TURBO_RATIO_LIMIT_IMPLEMENTATION] = 1; + DddtPreFlagHob->PresentFlag[BIOS_GRAPHICS_CORE_VOLTAGE_IMPLEMENTATION] = 1; +#endif +#endif + } + + *PciMemoryMask = 0; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RetrieveGdxcMemorySize +// +// Description: Determine the memory size desired by GDXC +// +// Input: PeiServices - Pointer to the PEI services table. +// MotSize - Gdxc Mot memory size to return. +// GdxcSize - Gdxc Required memory size to return. +// +// Output: +// VOID +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +RetrieveGdxcMemorySize ( + IN EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *MotSize, + IN OUT UINT64 *GdxcSize) +{ + UINT32 MchBar; + UINT32 GdxcBar; + UINT32 TempMotSize; + UINT32 TempOclaSize; + + // + // Get MchBAR + // + MchBar = MmPci32(0, 0, 0, R_SA_MCHBAR) & B_SA_MCHBAR_MCHBAR_MASK; + // + // Get GdxcBar + // + GdxcBar = MmioRead32(MchBar+NCDECS_CR_GDXCBAR_NCU_REG); + GdxcBar &= NCDECS_CR_GDXCBAR_NCU_MAX; + // + // Determine Gdxc size: Includes MOT\PSMI\IOT (OCLA) + // + TempMotSize = MmioRead32(GdxcBar+0x18); + *GdxcSize = (((TempMotSize & 0xFFFF0000) >> 16) - (TempMotSize & 0x0000FFFF) + 1) << 23; + *MotSize = *GdxcSize; + + TempOclaSize = MmioRead32(GdxcBar+0x28); + *GdxcSize += (((TempOclaSize & 0xFFFF0000) >> 16) - (TempOclaSize & 0x0000FFFF)) << 23; + + // Add 16MB if some allocated to MOT and/or IOT + if (*GdxcSize != 0) + *GdxcSize += (16 << 20); +} + +EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = { + { EfiACPIReclaimMemory, 0x5 }, + { EfiACPIMemoryNVS, 0x280 }, + { EfiReservedMemoryType, 0x500}, + { EfiRuntimeServicesData, 0x2A}, +#ifdef EFI_DEBUG + { EfiRuntimeServicesCode, 0x80 }, + { EfiBootServicesCode, 0x1000}, +#else + { EfiRuntimeServicesCode, 0x3A}, + { EfiBootServicesCode, 0x1000}, +#endif + { EfiMaxMemoryType, 0 } +}; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetPlatformMemorySize +// +// Description: Get the platform for the minimum memory size +// +// Input: PeiServices - Pointer to the PEI services table. +// This - Pointer to the Pei platform memory range ppi. +// MemorySize - Platform for the minimum memory size. +// +// Output: +// EFI_STATUS - Status +// EFI_ERROR - Create hob fail +// EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +GetPlatformMemorySize ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_PLATFORM_MEMORY_SIZE_PPI *This, + IN OUT UINT64 *MemorySize + ) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable; + UINTN DataSize; + EFI_MEMORY_TYPE_INFORMATION MemoryData [EfiMaxMemoryType + 1]; + UINTN Index; + EFI_BOOT_MODE BootMode; + EFI_HOB_GUID_TYPE *Hob; +// UINT64 GdxcRequiredMemSize; +// UINT64 GdxcMotMemSize; + + // RetrieveGdxcMemorySize(PeiServices, &GdxcMotMemSize, &GdxcRequiredMemSize); + + // Accumulate maximum amount of memory needed + // *MemorySize = (READ_PCI32_NB (R_SA_TSEGMB) & B_SA_TSEGMB_TSEGMB_MASK) - 0x1000000; + // *MemorySize -= GdxcRequiredMemSize; + + *MemorySize = PEI_MIN_MEMORY_SIZE; + + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + &Variable + ); + ASSERT_PEI_ERROR (PeiServices, Status); + + Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode); + ASSERT_PEI_ERROR (PeiServices, Status); + + DataSize = sizeof (MemoryData); + + Status = Variable->GetVariable ( + Variable, + (BootMode == BOOT_ON_S4_RESUME) + ? L"PreviousMemoryTypeInformation" + : EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME, + &gEfiMemoryTypeInformationGuid, + NULL, + &DataSize, + &MemoryData + ); + + if (EFI_ERROR (Status) || ( BootMode == BOOT_ON_FLASH_UPDATE )) { + if ( BootMode == BOOT_IN_RECOVERY_MODE ) { + return EFI_SUCCESS; + } + + // Use default value to avoid memory fragment. OS boot/installation fails + // if there is not enough continuous memory available + DataSize = sizeof (mDefaultMemoryTypeInformation); + (*PeiServices)->CopyMem (MemoryData, mDefaultMemoryTypeInformation, DataSize); + } + + for (Index = 0; Index < DataSize / sizeof (EFI_MEMORY_TYPE_INFORMATION); Index++) { + *MemorySize += MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE; + } + + // Build the GUID'd HOB for DXE + Status = (*PeiServices)->CreateHob ( + PeiServices, + EFI_HOB_TYPE_GUID_EXTENSION, + (UINT16) (sizeof (EFI_HOB_GUID_TYPE) + DataSize), + &Hob + ); + if (EFI_ERROR (Status))return Status; + + ((EFI_HOB_GUID_TYPE *)(Hob))->Name = gEfiMemoryTypeInformationGuid; + + Hob++; + + // Copy memory data to Hob + (*PeiServices)->CopyMem (Hob, MemoryData, DataSize); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: CreateCPUHob +// +// Description: Create Cpu Hob and initialize it. +// +// Input: +// IN EFI_PEI_SERVICES **PeiServices +// +// Output: +// EFI_STATUS - EFI_SUCCESS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS CreateCPUHob( + IN EFI_PEI_SERVICES **PeiServices +) +{ + EFI_HOB_CPU *pCpu = NULL; + EFI_STATUS Status; + + Status = (*PeiServices)->CreateHob( PeiServices, \ + EFI_HOB_TYPE_CPU, \ + sizeof(EFI_HOB_CPU), \ + &pCpu ); + if (Status == EFI_SUCCESS) { + pCpu->SizeOfMemorySpace = 36; + pCpu->SizeOfIoSpace = 16; + MemSet(pCpu->Reserved, 6, 0); + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: DisablePegDevices +// +// Description: Check Disable Peg Devices. +// +// Input: +// +// Output: +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID DisablePegDevices() +{ + UINT16 PegDisFun; + UINT16 i; +#ifdef RC_PEG_0 + for ( i = 0; gDisablePegDevicesTable[i].Bus != 0xff; i++) + { + UINTN PegAddress; + UINT8 PegBus; + UINT8 PegDev; + UINT8 PegFun; + + PegBus = gDisablePegDevicesTable[i].Bus; + PegDev = gDisablePegDevicesTable[i].Dev; + PegFun = gDisablePegDevicesTable[i].Fun; + + PegAddress = NB_PCIE_CFG_ADDRESS(PegBus, PegDev, PegFun, 0); + + if (READ_MEM32(PegAddress) == 0xFFFFFFFF) continue; + + // Disable Link +// CapPtr = NbFindCapPtr(PegAddress, 0x10); +// SET_MEM8((PegAddress + CapPtr + 0x10), BIT04); + SET_MEM8 ((PegAddress + R_SA_PEG_LCTL_OFFSET), BIT4); + SET_MEM8 ((PegAddress + R_SA_PEG_DEBUP2_OFFSET), BIT0); + SET_MEM32 ((PegAddress + R_SA_PEG_PEGCOMLCGCTRL_OFFSET), BIT30); + } + + PegDisFun = 0 +#if RC_PEG_0 == 0 + | B_SA_DEVEN_D1F0EN_MASK +#endif +#if !(defined RC_PEG_1) || RC_PEG_1 == 0 + | B_SA_DEVEN_D1F1EN_MASK +#endif +#if !(defined RC_PEG_2) || RC_PEG_2 == 0 + | B_SA_DEVEN_D1F2EN_MASK +#endif + ; + + // Disable PEG + if(PegDisFun != 0) + RESET_PCI16_NB(R_SA_DEVEN, PegDisFun); // 0x54 + +#endif //#ifdef RC_PEG_0 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: InstallSaPlatformPolicyPpi +// +// Description: InstallSaPlatformPolicyPpi: This Function installs the SNB SA POLICY PPI +// +// Parameters: +// PeiServices - General purpose services available to every PEIM +// NbSetupData - NB Setup data stored in NVRAM +// +// Returns: +// Status: Return Status +// Notes: +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +InstallSaPlatformPolicyPpi ( + IN EFI_PEI_SERVICES **PeiServices, + IN NB_SETUP_DATA *NbSetupData +) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices = NULL; + UINTN VariableSize; + VOID *MrcS3ResumeData; + VOID *PegGen3Data; + EFI_PEI_CPU_IO_PPI *CpuIo; + EFI_PEI_PPI_DESCRIPTOR *SaPlatformPolicyPpiDesc; + SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi; + SA_PLATFORM_DATA *PlatformData; + GT_CONFIGURATION *GtConfig; + MEMORY_CONFIGURATION *MemConfig; + PCIE_CONFIGURATION *PcieConfig; + OVERCLOCKING_CONFIGURATION *OcConfig; + PEG_GPIO_DATA *PegGpioData; + SA_GPIO_INFO *SaPegReset; +#if defined SwitchableGraphics_SUPPORT && SwitchableGraphics_SUPPORT == 1 + SG_GPIO_DATA *SgGpioData; + SA_GPIO_INFO *SgDgpuPwrOK; + SA_GPIO_INFO *SgDgpuHoldRst; + SA_GPIO_INFO *SgDgpuPwrEnable; + SA_GPIO_INFO *SgDgpuPrsnt; +#endif + UINTN MemoryCeiling = 0; + UINT16 LpcDeviceId; + UINT16 McDeviceId; + UINTN i = 0; + UINT16 CapPtr = 0; + + CpuIo = (*PeiServices)->CpuIo; + + // Locate Variable Ppi + Status = (*PeiServices)->LocatePpi (PeiServices, &gEfiPeiReadOnlyVariable2PpiGuid, 0, NULL, &VariableServices); + ASSERT_PEI_ERROR (PeiServices, Status); + + // Allocate descriptor and PPI structures + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (SA_PLATFORM_POLICY_PPI), &SaPlatformPolicyPpi); + ASSERT_PEI_ERROR (PeiServices, Status); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (EFI_PEI_PPI_DESCRIPTOR), &SaPlatformPolicyPpiDesc); + ASSERT_PEI_ERROR (PeiServices, Status); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (SA_PLATFORM_DATA), &PlatformData); + ASSERT_PEI_ERROR (PeiServices, Status); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (GT_CONFIGURATION), &GtConfig); + ASSERT_PEI_ERROR (PeiServices, Status); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (MEMORY_CONFIGURATION), &MemConfig); + ASSERT_PEI_ERROR (PeiServices, Status); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCIE_CONFIGURATION), &PcieConfig); + ASSERT_PEI_ERROR (PeiServices, Status); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PEG_GPIO_DATA), &PegGpioData); + ASSERT_PEI_ERROR (PeiServices, Status); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (OVERCLOCKING_CONFIGURATION), &OcConfig); + ASSERT_PEI_ERROR (PeiServices, Status); + +#if defined SwitchableGraphics_SUPPORT && SwitchableGraphics_SUPPORT == 1 + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (SG_GPIO_DATA), &SgGpioData); + ASSERT_PEI_ERROR (PeiServices, Status); +#endif + + // Set Default to Variable not found + (*PeiServices)->SetMem ((VOID*) PlatformData, sizeof (SA_PLATFORM_DATA), 0); + (*PeiServices)->SetMem ((VOID*) SaPlatformPolicyPpiDesc, sizeof (EFI_PEI_PPI_DESCRIPTOR), 0); + (*PeiServices)->SetMem ((VOID*) GtConfig, sizeof (GT_CONFIGURATION), 0); + (*PeiServices)->SetMem ((VOID*) MemConfig, sizeof (MEMORY_CONFIGURATION), 0); + (*PeiServices)->SetMem ((VOID*) PcieConfig, sizeof (PCIE_CONFIGURATION), 0); + (*PeiServices)->SetMem ((VOID*) SaPlatformPolicyPpi, sizeof (SA_PLATFORM_POLICY_PPI), 0); + (*PeiServices)->SetMem ((VOID*) PegGpioData, sizeof (PEG_GPIO_DATA), 0); + (*PeiServices)->SetMem ((VOID*) OcConfig, sizeof (OVERCLOCKING_CONFIGURATION), 0); +#if defined SwitchableGraphics_SUPPORT && SwitchableGraphics_SUPPORT == 1 + (*PeiServices)->SetMem ((VOID*) SgGpioData, sizeof (SG_GPIO_DATA), 0); +#endif + + SaPlatformPolicyPpi->PlatformData = PlatformData; + SaPlatformPolicyPpi->GtConfig = GtConfig; + SaPlatformPolicyPpi->MemConfig = MemConfig; + SaPlatformPolicyPpi->PcieConfig = PcieConfig; + SaPlatformPolicyPpi->PcieConfig->PegGpioData = PegGpioData; + SaPlatformPolicyPpi->OcConfig = OcConfig; +#if defined SwitchableGraphics_SUPPORT && SwitchableGraphics_SUPPORT == 1 + SaPlatformPolicyPpi->SgGpioData = SgGpioData; +#endif + SaPlatformPolicyPpi->S3DataPtr = NULL; + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (SA_GPIO_INFO), &SaPegReset); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) SaPegReset, sizeof (SA_GPIO_INFO), 0); + SaPlatformPolicyPpi->PcieConfig->PegGpioData->SaPegReset = SaPegReset; + +#if defined SwitchableGraphics_SUPPORT && SwitchableGraphics_SUPPORT == 1 + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (SA_GPIO_INFO), &SgDgpuPwrOK); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) SgDgpuPwrOK, sizeof (SA_GPIO_INFO), 0); + SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrOK = SgDgpuPwrOK; + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (SA_GPIO_INFO), &SgDgpuPwrEnable); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) SgDgpuPwrEnable, sizeof (SA_GPIO_INFO), 0); + SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrEnable = SgDgpuPwrEnable; + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (SA_GPIO_INFO), &SgDgpuHoldRst); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) SgDgpuHoldRst, sizeof (SA_GPIO_INFO), 0);; + SaPlatformPolicyPpi->SgGpioData->SgDgpuHoldRst = SgDgpuHoldRst; + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (SA_GPIO_INFO), &SgDgpuPrsnt); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) SgDgpuPrsnt, sizeof (SA_GPIO_INFO), 0); + SaPlatformPolicyPpi->SgGpioData->SgDgpuPrsnt = SgDgpuPrsnt; +#endif + + // + // Initialize the PPI + // + SaPlatformPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + SaPlatformPolicyPpiDesc->Guid = &gSaPlatformPolicyPpiGuid; + SaPlatformPolicyPpiDesc->Ppi = SaPlatformPolicyPpi; + + // Read MC device ID + McDeviceId = READ_PCI16_NB(R_SA_MC_DEVICE_ID); + + // Read PCH device ID + LpcDeviceId = READ_PCI16_SB(R_PCH_LPC_DEVICE_ID); + + // Update the REVISION number + SaPlatformPolicyPpi->Revision = SA_PLATFORM_POLICY_PPI_REVISION_15; + + // Get the Platform Configuration from NbSetupData + SaPlatformPolicyPpi->PlatformData->SpdAddressTable[0] = DIMM1_SMBUS_ADDRESS; + SaPlatformPolicyPpi->PlatformData->SpdAddressTable[1] = DIMM2_SMBUS_ADDRESS; + SaPlatformPolicyPpi->PlatformData->SpdAddressTable[2] = DIMM3_SMBUS_ADDRESS; + SaPlatformPolicyPpi->PlatformData->SpdAddressTable[3] = DIMM4_SMBUS_ADDRESS; + SaPlatformPolicyPpi->PlatformData->MchBar = (UINT32)NB_MCH_BASE_ADDRESS; + SaPlatformPolicyPpi->PlatformData->DmiBar = (UINT32)NB_DMI_BASE_ADDRESS; + SaPlatformPolicyPpi->PlatformData->EpBar = (UINT32)NB_EP_BASE_ADDRESS; + SaPlatformPolicyPpi->PlatformData->PciExpressBar = (UINT32)PCIEX_BASE_ADDRESS; + SaPlatformPolicyPpi->PlatformData->SmbusBar = (UINT32)SMBUS_BASE_ADDRESS; + SaPlatformPolicyPpi->PlatformData->EdramBar = (UINT32)NB_DERAM_BASE_ADDRESS; + SaPlatformPolicyPpi->PlatformData->GdxcBar = (UINT32)NB_GDXC_BASE_ADDRESS; + SaPlatformPolicyPpi->PlatformData->TsegSize = (UINT32)TSEG_SIZE; + SaPlatformPolicyPpi->PlatformData->IedSize = (UINT32)IED_SIZE; + SaPlatformPolicyPpi->PlatformData->FastBoot = NbSetupData->MrcFastBoot; + + if(NbSetupData->IsRunMemoryDown) { + SaPlatformPolicyPpi->PlatformData->BoardId = 0; + } else { + SaPlatformPolicyPpi->PlatformData->BoardId = 0xff; + } + + SaPlatformPolicyPpi->MemConfig->MrcFastBoot = NbSetupData->MrcFastBoot; + + SaPlatformPolicyPpi->MemConfig->BClkFrequency = 100 * 1000 * 1000; + SaPlatformPolicyPpi->MemConfig->MaxRttWr = NbSetupData->MaxRttWr; + SaPlatformPolicyPpi->MemConfig->PowerDownMode = NbSetupData->PowerDownMode0; + SaPlatformPolicyPpi->MemConfig->PwdwnIdleCounter = NbSetupData->PwdwnIdleCounter; + SaPlatformPolicyPpi->MemConfig->RankInterleave = NbSetupData->RankInterleave; + SaPlatformPolicyPpi->MemConfig->EnhancedInterleave = NbSetupData->EnhancedInterleave; + SaPlatformPolicyPpi->MemConfig->WeaklockEn = NbSetupData->WeaklockEn; + SaPlatformPolicyPpi->MemConfig->EnCmdRate = 7; + SaPlatformPolicyPpi->MemConfig->CmdTriStateDis = FALSE; + SaPlatformPolicyPpi->MemConfig->RefreshRate2x = NbSetupData->Refresh2X; + + SaPlatformPolicyPpi->MemConfig->McLock = NbSetupData->McLock; + + SaPlatformPolicyPpi->MemConfig->GdxcEnable = NbSetupData->GdxcEnable; + SaPlatformPolicyPpi->MemConfig->GdxcIotSize = NbSetupData->GdxcIotSize; + SaPlatformPolicyPpi->MemConfig->GdxcMotSize = NbSetupData->GdxcMotSize; + SaPlatformPolicyPpi->MemConfig->MemoryTrace = NbSetupData->MemoryTrace; + + SaPlatformPolicyPpi->MemConfig->ECT = NbSetupData->ECT; + SaPlatformPolicyPpi->MemConfig->SOT = NbSetupData->SOT; + SaPlatformPolicyPpi->MemConfig->RDMPRT = NbSetupData->RDMPRT; + SaPlatformPolicyPpi->MemConfig->RCVET = NbSetupData->RCVET; + SaPlatformPolicyPpi->MemConfig->JWRL = NbSetupData->JWRL; + SaPlatformPolicyPpi->MemConfig->FWRL = NbSetupData->FWRL; + SaPlatformPolicyPpi->MemConfig->WRTC1D = NbSetupData->WRTC1D; + SaPlatformPolicyPpi->MemConfig->RDTC1D = NbSetupData->RDTC1D; + SaPlatformPolicyPpi->MemConfig->DIMMODTT = NbSetupData->DIMMODTT; + SaPlatformPolicyPpi->MemConfig->WRDST = NbSetupData->WRDST; + SaPlatformPolicyPpi->MemConfig->WREQT = NbSetupData->WREQT; + + SaPlatformPolicyPpi->MemConfig->RDODTT = NbSetupData->RDODTT; + SaPlatformPolicyPpi->MemConfig->RDEQT = NbSetupData->RDEQT; + SaPlatformPolicyPpi->MemConfig->RDAPT = NbSetupData->RDAPT; + SaPlatformPolicyPpi->MemConfig->WRTC2D = NbSetupData->WRTC2D; + SaPlatformPolicyPpi->MemConfig->RDTC2D = NbSetupData->RDTC2D; + SaPlatformPolicyPpi->MemConfig->CMDVC = NbSetupData->CMDVC; + SaPlatformPolicyPpi->MemConfig->WRVC2D = NbSetupData->WRVC2D; + SaPlatformPolicyPpi->MemConfig->RDVC2D = NbSetupData->RDVC2D; + SaPlatformPolicyPpi->MemConfig->LCT = NbSetupData->LCT; + SaPlatformPolicyPpi->MemConfig->RTL = NbSetupData->RTL; + SaPlatformPolicyPpi->MemConfig->TAT = NbSetupData->TAT; + SaPlatformPolicyPpi->MemConfig->MEMTST = NbSetupData->MEMTST; + SaPlatformPolicyPpi->MemConfig->DIMMODTT1D = NbSetupData->DIMMODTT1D; + SaPlatformPolicyPpi->MemConfig->WRSRT = NbSetupData->WRSRT; + SaPlatformPolicyPpi->MemConfig->DIMMRONT = NbSetupData->DIMMRONT; + SaPlatformPolicyPpi->MemConfig->ALIASCHK = NbSetupData->ALIASCHK; + SaPlatformPolicyPpi->MemConfig->RCVENC1D = NbSetupData->RCVENC1D; + SaPlatformPolicyPpi->MemConfig->RMC = NbSetupData->RMC; + + /// + /// Channel Hash Configuration + /// + SaPlatformPolicyPpi->MemConfig->ChHashEnable = NbSetupData->ChHashEnable; + SaPlatformPolicyPpi->MemConfig->ChHashMask = NbSetupData->ChHashMask; + SaPlatformPolicyPpi->MemConfig->ChHashInterleaveBit = NbSetupData->ChHashInterleaveBit; + + /// + /// MrcUltPoSafeConfig + /// 1 to enable, 0 to disable + /// +// SaPlatformPolicyPpi->MemConfig->MrcUltPoSafeConfig = 0; + + if (GetPchSeries() == PchLp) { + /// + /// Interleaving mode of DQ/DQS pins - depends on board routing + /// + SaPlatformPolicyPpi->MemConfig->DqPinsInterleaved = NbSetupData->DqPinsInterleaved; + } + + // Get the Graphics configuration from the NbSetupData + SaPlatformPolicyPpi->GtConfig->IgdDvmt50PreAlloc = NbSetupData->IgdDvmt50PreAlloc; + + if (GetPchSeries() == PchLp) { + NbSetupData->AlwaysEnablePeg = 2; + } + + if (NbSetupData->AlwaysEnablePeg != 0) DisablePegDevices(); + + //if AlwaysEnablePeg Auto and Enable send to Policy , disable device + switch (NbSetupData->AlwaysEnablePeg) { + case 0: + case 1: + SaPlatformPolicyPpi->PcieConfig->AlwaysEnablePeg = NbSetupData->AlwaysEnablePeg; + break; + case 2: + // Disable Link + for (i = 0; NBPcieBridge[i] != 0xFFFFFFFF; i++) + { + if (READ_MEM32(NBPcieBridge[i]) == 0xFFFFFFFF) continue; + SET_MEM8((NBPcieBridge[i] + R_SA_PEG_LCTL_OFFSET), BIT04); + SET_MEM8 ((NBPcieBridge[i] + R_SA_PEG_DEBUP2_OFFSET), BIT0); + SET_MEM32 ((NBPcieBridge[i] + R_SA_PEG_PEGCOMLCGCTRL_OFFSET), BIT30); + + } + // Disable PEG + RESET_PCI16_NB(R_SA_DEVEN, (B_SA_DEVEN_D1F0EN_MASK | B_SA_DEVEN_D1F1EN_MASK | B_SA_DEVEN_D1F2EN_MASK)); // 0x54 + break; + } + + SaPlatformPolicyPpi->GtConfig->InternalGraphics = NbSetupData->InternalGraphics; + SaPlatformPolicyPpi->GtConfig->PrimaryDisplay = NbSetupData->PrimaryDisplay; + SaPlatformPolicyPpi->GtConfig->ApertureSize = NbSetupData->ApertureSize; + + // Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel) + SaPlatformPolicyPpi->GtConfig->PanelPowerEnable = NbSetupData->PanelPowerEnable; + + SaPlatformPolicyPpi->GtConfig->GttSize = NbSetupData->GTTSize; + SaPlatformPolicyPpi->GtConfig->GttMmAdr = NB_TEMP_MMIO_BASE; + + // Get the PciExpress Configuration from the NbSetupData + SaPlatformPolicyPpi->PcieConfig->DmiVc1 = NbSetupData->DmiVc1; + SaPlatformPolicyPpi->PcieConfig->DmiVcp = NbSetupData->DmiVcp; + SaPlatformPolicyPpi->PcieConfig->DmiVcm = NbSetupData->DmiVcm; + SaPlatformPolicyPpi->PcieConfig->DmiGen2 = NbSetupData->DmiGen2; + + SaPlatformPolicyPpi->PcieConfig->PegGenx[0] = NbSetupData->PegGenx0; + SaPlatformPolicyPpi->PcieConfig->PegGenx[1] = NbSetupData->PegGenx1; + SaPlatformPolicyPpi->PcieConfig->PegGenx[2] = NbSetupData->PegGenx2; + + for (i = 0; i < SA_PEG_MAX_FUN; i++) { + SaPlatformPolicyPpi->PcieConfig->PowerDownUnusedBundles[i] = NbSetupData->PowerDownUnusedBundles[i]; + } + + + // UserBd = Mobile - 0; Desktop/UpServer - 1; ULT - 5; + if(IS_SA_DEVICE_ID_MOBILE (McDeviceId)) { + SaPlatformPolicyPpi->PlatformData->UserBd = btCRBMB; + } else { + if (GetPchSeries() == PchLp) { + SaPlatformPolicyPpi->PlatformData->UserBd = btUser4; + } else { + SaPlatformPolicyPpi->PlatformData->UserBd = btCRBDT; + } + } + + SaPlatformPolicyPpi->MemConfig->SpdProfileSelected = NbSetupData->SpdProfileSelected; + SaPlatformPolicyPpi->MemConfig->NModeSupport = NbSetupData->NModeSupport; + SaPlatformPolicyPpi->MemConfig->RMT = NbSetupData->RmtCrosserEnable; + +#ifdef EFI_DEBUG +#if MRC_DEBUG_PRINT_SUPPORT + SaPlatformPolicyPpi->MemConfig->MrcTimeMeasure = FALSE; + SaPlatformPolicyPpi->MemConfig->SerialDebug = MSG_LEVEL_NOTE; +#else // #if MRC_DEBUG_PRINT_SUPPORT + SaPlatformPolicyPpi->MemConfig->MrcTimeMeasure = FALSE; + SaPlatformPolicyPpi->MemConfig->SerialDebug = MSG_LEVEL_WARNING; +#endif // #if MRC_DEBUG_PRINT_SUPPORT +#else // EFI_DEBUG + SaPlatformPolicyPpi->MemConfig->MrcTimeMeasure = FALSE; + SaPlatformPolicyPpi->MemConfig->SerialDebug = MSG_LEVEL_NEVER; +#endif // EFI_DEBUG + + SaPlatformPolicyPpi->MemConfig->DDR3Voltage = 0; + SaPlatformPolicyPpi->MemConfig->DDR3VoltageWaitTime = NbSetupData->DDRVoltageWaitTime; + SaPlatformPolicyPpi->MemConfig->RefClk = 0; + SaPlatformPolicyPpi->MemConfig->Ratio = 0; + + // + // Thermal Management Configuration + // + SaPlatformPolicyPpi->MemConfig->ThermalManagement = NbSetupData->MemoryThermalManagement; + SaPlatformPolicyPpi->MemConfig->PeciInjectedTemp = NbSetupData->PeciInjectedTemp; + SaPlatformPolicyPpi->MemConfig->ExttsViaTsOnBoard = NbSetupData->ExttsViaTsOnBoard; + SaPlatformPolicyPpi->MemConfig->ExttsViaTsOnDimm = NbSetupData->ExttsViaTsOnBoard; + SaPlatformPolicyPpi->MemConfig->VirtualTempSensor = NbSetupData->VirtualTempSensor; + /// + /// Options for Thermal settings + /// + SaPlatformPolicyPpi->MemConfig->EnableExtts = NbSetupData->EnableExtts; + SaPlatformPolicyPpi->MemConfig->EnableCltm = NbSetupData->EnableCltm; + SaPlatformPolicyPpi->MemConfig->EnableOltm = NbSetupData->EnableOltm; + SaPlatformPolicyPpi->MemConfig->EnablePwrDn = NbSetupData->EnablePwrDn; + SaPlatformPolicyPpi->MemConfig->Refresh2X = NbSetupData->Refresh2XMode; + SaPlatformPolicyPpi->MemConfig->LpddrThermalSensor = NbSetupData->LpddrThermalSensor; + SaPlatformPolicyPpi->MemConfig->LockPTMregs = NbSetupData->LockPTMregs; + SaPlatformPolicyPpi->MemConfig->UserPowerWeightsEn = NbSetupData->UserPowerWeightsEn; + + SaPlatformPolicyPpi->MemConfig->EnergyScaleFact = NbSetupData->EnergyScaleFact; + SaPlatformPolicyPpi->MemConfig->RaplPwrFlCh1 = NbSetupData->RaplPwrFlCh1; + SaPlatformPolicyPpi->MemConfig->RaplPwrFlCh0 = NbSetupData->RaplPwrFlCh0; + + SaPlatformPolicyPpi->MemConfig->RaplLim2Lock = NbSetupData->RaplLim2Lock; + SaPlatformPolicyPpi->MemConfig->RaplLim2WindX = NbSetupData->RaplLim2WindX; + SaPlatformPolicyPpi->MemConfig->RaplLim2WindY = NbSetupData->RaplLim2WindY; + SaPlatformPolicyPpi->MemConfig->RaplLim2Ena = NbSetupData->RaplLim2Ena; + SaPlatformPolicyPpi->MemConfig->RaplLim2Pwr = NbSetupData->RaplLim2Pwr; + SaPlatformPolicyPpi->MemConfig->RaplLim1WindX = NbSetupData->RaplLim1WindX; + SaPlatformPolicyPpi->MemConfig->RaplLim1WindY = NbSetupData->RaplLim1WindY; + SaPlatformPolicyPpi->MemConfig->RaplLim1Ena = NbSetupData->RaplLim1Ena; + SaPlatformPolicyPpi->MemConfig->RaplLim1Pwr = NbSetupData->RaplLim1Pwr; + + SaPlatformPolicyPpi->MemConfig->WarmThresholdCh0Dimm0 = NbSetupData->WarmThresholdCh0Dimm0; + SaPlatformPolicyPpi->MemConfig->WarmThresholdCh0Dimm1 = NbSetupData->WarmThresholdCh0Dimm1; + SaPlatformPolicyPpi->MemConfig->WarmThresholdCh1Dimm0 = NbSetupData->WarmThresholdCh1Dimm0; + SaPlatformPolicyPpi->MemConfig->WarmThresholdCh1Dimm1 = NbSetupData->WarmThresholdCh1Dimm1; + SaPlatformPolicyPpi->MemConfig->HotThresholdCh0Dimm0 = NbSetupData->HotThresholdCh0Dimm0; + SaPlatformPolicyPpi->MemConfig->HotThresholdCh0Dimm1 = NbSetupData->HotThresholdCh0Dimm1; + SaPlatformPolicyPpi->MemConfig->HotThresholdCh1Dimm0 = NbSetupData->HotThresholdCh1Dimm0; + SaPlatformPolicyPpi->MemConfig->HotThresholdCh1Dimm1 = NbSetupData->HotThresholdCh1Dimm1; + SaPlatformPolicyPpi->MemConfig->WarmBudgetCh0Dimm0 = NbSetupData->WarmBudgetCh0Dimm0; + SaPlatformPolicyPpi->MemConfig->WarmBudgetCh0Dimm1 = NbSetupData->WarmBudgetCh0Dimm1; + SaPlatformPolicyPpi->MemConfig->WarmBudgetCh1Dimm0 = NbSetupData->WarmBudgetCh1Dimm0; + SaPlatformPolicyPpi->MemConfig->WarmBudgetCh1Dimm1 = NbSetupData->WarmBudgetCh1Dimm1; + SaPlatformPolicyPpi->MemConfig->HotBudgetCh0Dimm0 = NbSetupData->HotBudgetCh0Dimm0; + SaPlatformPolicyPpi->MemConfig->HotBudgetCh0Dimm1 = NbSetupData->HotBudgetCh0Dimm1; + SaPlatformPolicyPpi->MemConfig->HotBudgetCh1Dimm0 = NbSetupData->HotBudgetCh1Dimm0; + SaPlatformPolicyPpi->MemConfig->HotBudgetCh1Dimm1 = NbSetupData->HotBudgetCh1Dimm1; + + SaPlatformPolicyPpi->MemConfig->IdleEnergyCh0Dimm1 = NbSetupData->IdleEnergyCh0Dimm1; + SaPlatformPolicyPpi->MemConfig->IdleEnergyCh0Dimm0 = NbSetupData->IdleEnergyCh0Dimm0; + SaPlatformPolicyPpi->MemConfig->PdEnergyCh0Dimm1 = NbSetupData->PdEnergyCh0Dimm1; + SaPlatformPolicyPpi->MemConfig->PdEnergyCh0Dimm0 = NbSetupData->PdEnergyCh0Dimm0; + SaPlatformPolicyPpi->MemConfig->ActEnergyCh0Dimm1 = NbSetupData->ActEnergyCh0Dimm1; + SaPlatformPolicyPpi->MemConfig->ActEnergyCh0Dimm0 = NbSetupData->ActEnergyCh0Dimm0; + SaPlatformPolicyPpi->MemConfig->RdEnergyCh0Dimm1 = NbSetupData->RdEnergyCh0Dimm1; + SaPlatformPolicyPpi->MemConfig->RdEnergyCh0Dimm0 = NbSetupData->RdEnergyCh0Dimm0; + SaPlatformPolicyPpi->MemConfig->WrEnergyCh0Dimm1 = NbSetupData->WrEnergyCh0Dimm1; + SaPlatformPolicyPpi->MemConfig->WrEnergyCh0Dimm0 = NbSetupData->WrEnergyCh0Dimm0; + + SaPlatformPolicyPpi->MemConfig->IdleEnergyCh1Dimm1 = NbSetupData->IdleEnergyCh1Dimm1; + SaPlatformPolicyPpi->MemConfig->IdleEnergyCh1Dimm0 = NbSetupData->IdleEnergyCh1Dimm0; + SaPlatformPolicyPpi->MemConfig->PdEnergyCh1Dimm1 = NbSetupData->PdEnergyCh1Dimm1; + SaPlatformPolicyPpi->MemConfig->PdEnergyCh1Dimm0 = NbSetupData->PdEnergyCh1Dimm0; + SaPlatformPolicyPpi->MemConfig->ActEnergyCh1Dimm1 = NbSetupData->ActEnergyCh1Dimm1; + SaPlatformPolicyPpi->MemConfig->ActEnergyCh1Dimm0 = NbSetupData->ActEnergyCh1Dimm0; + SaPlatformPolicyPpi->MemConfig->RdEnergyCh1Dimm1 = NbSetupData->RdEnergyCh1Dimm1; + SaPlatformPolicyPpi->MemConfig->RdEnergyCh1Dimm0 = NbSetupData->RdEnergyCh1Dimm0; + SaPlatformPolicyPpi->MemConfig->WrEnergyCh1Dimm1 = NbSetupData->WrEnergyCh1Dimm1; + SaPlatformPolicyPpi->MemConfig->WrEnergyCh1Dimm0 = NbSetupData->WrEnergyCh1Dimm0; + + SaPlatformPolicyPpi->MemConfig->SrefCfgEna = NbSetupData->SrefCfgEna; + SaPlatformPolicyPpi->MemConfig->SrefCfgIdleTmr = NbSetupData->SrefCfgIdleTmr; + SaPlatformPolicyPpi->MemConfig->ThrtCkeMinDefeat = NbSetupData->ThrtCkeMinDefeat; + SaPlatformPolicyPpi->MemConfig->ThrtCkeMinTmr = NbSetupData->ThrtCkeMinTmr; + + if (GetPchSeries() == PchLp) { + SaPlatformPolicyPpi->MemConfig->ThrtCkeMinDefeatLpddr = NbSetupData->ThrtCkeMinDefeatLpddr; + SaPlatformPolicyPpi->MemConfig->ThrtCkeMinTmrLpddr = NbSetupData->ThrtCkeMinTmrLpddr; + SaPlatformPolicyPpi->MemConfig->EnablePwrDnLpddr = NbSetupData->EnablePwrDnLpddr; + } + + + // + // Scrambler + // + SaPlatformPolicyPpi->MemConfig->ScramblerSupport = NbSetupData->ScramblerSupport; + + // + // Power Mode Setting + // + SaPlatformPolicyPpi->MemConfig->ForceColdReset = NbSetupData->ForceColdReset; + // + // Channel DIMM Disable + // + SaPlatformPolicyPpi->MemConfig->DisableDimmChannel[0] = NbSetupData->DisableDimmChannel0; + SaPlatformPolicyPpi->MemConfig->DisableDimmChannel[1] = NbSetupData->DisableDimmChannel1; + + SaPlatformPolicyPpi->MemConfig->AutoSelfRefreshSupport = NbSetupData->AutoSelfRefreshSupport; + SaPlatformPolicyPpi->MemConfig->ExtTemperatureSupport = NbSetupData->ExtTemperatureSupport; + + /// + /// Options for MC Register Offsets + /// + SaPlatformPolicyPpi->MemConfig->CAVrefCtlOffset = NbSetupData->CAVrefCtlOffset; + SaPlatformPolicyPpi->MemConfig->Ch0VrefCtlOffset = NbSetupData->Ch0VrefCtlOffset; + SaPlatformPolicyPpi->MemConfig->Ch1VrefCtlOffset = NbSetupData->Ch1VrefCtlOffset; + SaPlatformPolicyPpi->MemConfig->Ch0ClkPiCodeOffset = NbSetupData->Ch0ClkPiCodeOffset; + SaPlatformPolicyPpi->MemConfig->Ch1ClkPiCodeOffset = NbSetupData->Ch1ClkPiCodeOffset; + SaPlatformPolicyPpi->MemConfig->Ch0RcvEnOffset = NbSetupData->Ch0RcvEnOffset; + SaPlatformPolicyPpi->MemConfig->Ch0RxDqsOffset = NbSetupData->Ch0RxDqsOffset; + SaPlatformPolicyPpi->MemConfig->Ch0TxDqOffset = NbSetupData->Ch0TxDqOffset; + SaPlatformPolicyPpi->MemConfig->Ch0TxDqsOffset = NbSetupData->Ch0TxDqsOffset; + SaPlatformPolicyPpi->MemConfig->Ch0VrefOffset = NbSetupData->Ch0VrefOffset; + SaPlatformPolicyPpi->MemConfig->Ch1RcvEnOffset = NbSetupData->Ch1RcvEnOffset; + SaPlatformPolicyPpi->MemConfig->Ch1RxDqsOffset = NbSetupData->Ch1RxDqsOffset; + SaPlatformPolicyPpi->MemConfig->Ch1TxDqOffset = NbSetupData->Ch1TxDqOffset; + SaPlatformPolicyPpi->MemConfig->Ch1TxDqsOffset = NbSetupData->Ch1TxDqsOffset; + SaPlatformPolicyPpi->MemConfig->Ch1VrefOffset = NbSetupData->Ch1VrefOffset; + + // + // Initialize the 16bit CMOS location for scrambling seed storage when iFFS is enabled + // + SaPlatformPolicyPpi->ScramblerSeedCmosLocation = NB_CMOS_IFFS_SCRAMBLER_SEED; + + SaPlatformPolicyPpi->MemConfig->RemapEnable = NbSetupData->RemapEnable; + +#ifdef BDAT_SUPPORT + SaPlatformPolicyPpi->MemConfig->RmtBdatEnable = NbSetupData->BdatAcpiTableSupport; +#endif + + SaPlatformPolicyPpi->PcieConfig->PegGen3Equalization = NbSetupData->PegGen3Equalization; + + // + // PEG Sampler Calibration: 0 = Disabled, 1 = Enabled, 2 = Auto (default) + // + SaPlatformPolicyPpi->PcieConfig->PegSamplerCalibrate = NbSetupData->PegSamplerCalibrate;; + + // + // PEG Gen3 Equalization Phase 2: 0 = Disabled (default), 1 = Enabled + // + SaPlatformPolicyPpi->PcieConfig->PegGen3EqualizationPhase2 = NbSetupData->PegGen3EqualizationPhase2; + + // + // PEG Gen3 Preset Search: 0 = Disabled (default), 1 = Enabled + // PEG Gen3 Preset Search dwell time: 400 ms + // PEG Gen3 Preset Search Margin Steps: 2 + // PEG Gen3 Preset Search Start Margin: 15 + // PEG Gen3 Preset Search Error Target: 4 + // + SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearch = NbSetupData->PegGen3PresetSearch; + SaPlatformPolicyPpi->PcieConfig->PegGen3ForcePresetSearch = NbSetupData->PegGen3ForcePresetSearch; + SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchDwellTime = NbSetupData->PegGen3PresetSearchDwellTime; + SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchMarginSteps = NbSetupData->PegGen3PresetSearchMarginSteps; + SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchStartMargin = NbSetupData->PegGen3PresetSearchStartMargin; + SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchVoltageMarginSteps = NbSetupData->PegGen3PresetSearchVoltageMarginSteps; + SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchVoltageStartMargin = NbSetupData->PegGen3PresetSearchVoltageStartMargin; + SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchFavorTiming = NbSetupData->PegGen3PresetSearchFavorTiming; + SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchErrorTarget = NbSetupData->PegGen3PresetSearchErrorTarget; + + for (i = 0; i < 16; i++) { + // RP preset goes to bits [3:0] and [19:16] + // EP preset goes to bits [11:8] and [27:24] + // EP hint goes to bits [14:12] and [30:28] + SaPlatformPolicyPpi->PcieConfig->Gen3RootPortPreset[i] = NbSetupData->Gen3RootPortPreset[i]; + SaPlatformPolicyPpi->PcieConfig->Gen3EndPointPreset[i] = NbSetupData->Gen3EndPointPreset[i]; + SaPlatformPolicyPpi->PcieConfig->Gen3EndPointHint[i] = NbSetupData->Gen3EndPointHint[i]; + } + + /// + /// Parameters for PCIe ASPM flow control + /// InitPcieAspmAfterOprom: + /// 0 (default) - PCIe ASPM will be initialized Before Oprom + /// 1 - PCIe ASPM will be initialized After Oprom (required IOTRAP SMI handler) + /// Note: This setting should match supported mode! + /// + /// SaIotrapSmiAddress: + /// IOTRAP SMI address for SA SMI callback handler. This should be given if platform supports InitPcieAspmAfterOprom = 1 scenario (SaLateInitSmm driver was compiled) + /// + SaPlatformPolicyPpi->PcieConfig->InitPcieAspmAfterOprom = NbSetupData->InitPcieAspmAfterOprom; + SaPlatformPolicyPpi->PcieConfig->SaIotrapSmiAddress = NB_IOTRAP_SMI_ADDRESSE; + + /// + /// Parameters for PCIe Gen3 device reset + /// + SaPlatformPolicyPpi->PcieConfig->PegGpioData->GpioSupport = NbSetupData->AllowPerstGpioUsage; + if (SaPlatformPolicyPpi->PcieConfig->PegGpioData->GpioSupport) { + /// + /// PEG Reset: GPIO 50, Active Low (Mobile PDG) + /// + SaPlatformPolicyPpi->PcieConfig->PegGpioData->SaPegReset->Value = NbSetupData->AllowPerstGpio; + SaPlatformPolicyPpi->PcieConfig->PegGpioData->SaPegReset->Active = NbSetupData->AllowPerstGpioActive; + } + + /// + /// Enable/Disable RxCEM Loop back + /// 1=Enable, 0=Disable (default) + /// When enabled, Lane for loop back should be selected (0 ~ 15 and default is Lane 0) + /// + SaPlatformPolicyPpi->PcieConfig->RxCEMLoopback = NbSetupData->RxCEMLoopback; + SaPlatformPolicyPpi->PcieConfig->RxCEMLoopbackLane = NbSetupData->RxCEMLoopbackLane; + + /// + /// Gen3 RxCTLE peaking default is 8 + /// + for (i = 0; i < SA_PEG_MAX_BUNDLE; i++) { + SaPlatformPolicyPpi->PcieConfig->Gen3RxCtleP[i] = NbSetupData->Gen3RxCtleP[i]; + } + + /// + /// Initialize the SA PEG Data pointer for saved preset search results + /// + SaPlatformPolicyPpi->PcieConfig->PegDataPtr = NULL; + + SaPlatformPolicyPpi->PcieConfig->PegSwingControl = NbSetupData->SwingControl; + + SaPlatformPolicyPpi->PcieConfig->PegComplianceTestingMode = NbSetupData->PegComplianceTestingMode; + + + // + // Read DDR Frequecy setting selected in Bios setup + // + switch (NbSetupData->DdrFreqLimit) { + case DDR3_FREQ_1067: + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = 1067; + break; + + case DDR3_FREQ_1333: + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = 1333; + break; + + case DDR3_FREQ_1600: + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = 1600; + break; + + case DDR3_FREQ_1867: + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = 1867; + break; + + case DDR3_FREQ_2133: + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = 2133; + break; + + case DDR3_FREQ_2400: + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = 2400; + break; + + case DDR3_FREQ_2667: + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = 2667; + break; + + case DDR3_FREQ_AUTO: + default: + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = 0; + break; + + } + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 0 +{ + WDT_PPI *WdtPpi = NULL; + UINT8 WdtFlag = V_PCH_OC_WDT_CTL_STATUS_FAILURE; + + // + // Locate WDT PPI for access to Wdt->CheckStatus() + // + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gWdtPpiGuid, + 0, + NULL, + &WdtPpi + ); + if (!EFI_ERROR (Status)) { + WdtFlag = WdtPpi->CheckStatus(); + } + + if (WdtFlag == V_PCH_OC_WDT_CTL_STATUS_OK) { + if(NbSetupData->SpdProfileSelected == 1) { // UserDefault + if(NbSetupData->OcDdrFreqLimit != 0) + + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = NbSetupData->OcDdrFreqLimit; + // if (SettingData.MemoryClockMultiplier == 100) + // SaPlatformPolicyPpi->MemConfig->RefClk = MRC_REF_CLOCK_100; + + SaPlatformPolicyPpi->MemConfig->Ratio = \ + NbFrequencyToRatio(SaPlatformPolicyPpi->MemConfig->DdrFreqLimit, MRC_REF_CLOCK_133, SaPlatformPolicyPpi->MemConfig->BClkFrequency);//SaPlatformPolicyPpi->MemConfig->RefClk); + + SaPlatformPolicyPpi->MemConfig->tCL = NbSetupData->tCL; + SaPlatformPolicyPpi->MemConfig->tCWL = NbSetupData->tCWL; + SaPlatformPolicyPpi->MemConfig->tFAW = NbSetupData->tFAW; + SaPlatformPolicyPpi->MemConfig->tRAS = NbSetupData->tRAS; + SaPlatformPolicyPpi->MemConfig->tRC = NbSetupData->tRC; + SaPlatformPolicyPpi->MemConfig->tRCD = NbSetupData->tRCD; + SaPlatformPolicyPpi->MemConfig->tREFI = NbSetupData->tREFI; + SaPlatformPolicyPpi->MemConfig->tRFC = NbSetupData->tRFC; + SaPlatformPolicyPpi->MemConfig->tRP = NbSetupData->tRP; + SaPlatformPolicyPpi->MemConfig->tRRD = NbSetupData->tRRD; + SaPlatformPolicyPpi->MemConfig->tRTP = NbSetupData->tRTP; + SaPlatformPolicyPpi->MemConfig->tWR = NbSetupData->tWR; + SaPlatformPolicyPpi->MemConfig->tWTR = NbSetupData->tWTR; +// SaPlatformPolicyPpi->MemConfig->tWTR = NbSetupData->tRPab; + + } else if (SaPlatformPolicyPpi->MemConfig->SpdProfileSelected >= 2) { // XMP + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = 0; + } + +#ifndef EFI_DEBUG + if (WdtPpi != NULL && SaPlatformPolicyPpi->MemConfig->SpdProfileSelected != 0) { + WdtPpi->ReloadAndStart (10); // 10 Sec + } +#endif + + } else if (WdtFlag == V_PCH_OC_WDT_CTL_STATUS_FAILURE) { + SaPlatformPolicyPpi->MemConfig->SpdProfileSelected = 0; // Auto + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = 0; + } +} +#endif +// (P20121012A) >> Update XTU 4.0 +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C +{ + PERF_TUNE_PPI *PerfTunePpi; + BIOS_SETTING_DATA SettingData; + + Status = (*PeiServices)->LocatePpi( + PeiServices, + &gPerfTunePpiGuid, + 0, + NULL, + &PerfTunePpi); + if (EFI_ERROR(Status)) + { + ASSERT_PEI_ERROR(PeiServices, Status); + }else{ + + Status = PerfTunePpi->GetSettingData(PeiServices, &SettingData); + if((!EFI_ERROR (Status)) && (!PerfTunePpi->IsRunDefault(PeiServices))) + { + + SaPlatformPolicyPpi->MemConfig->SpdProfileSelected = (UINT8)SettingData.XmpProfilesSelect; + if (SettingData.XmpProfilesSelect == 1) { // UserDefault + + + if (SettingData.MemoryClockMultiplier == 100) + SaPlatformPolicyPpi->MemConfig->RefClk = MRC_REF_CLOCK_100; + + SaPlatformPolicyPpi->MemConfig->Ratio = (UINT8)SettingData.DDRMul / 2; + + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = \ + NbRatioToFrequency(SaPlatformPolicyPpi->MemConfig->Ratio, SaPlatformPolicyPpi->MemConfig->RefClk, SaPlatformPolicyPpi->MemConfig->BClkFrequency); + + SaPlatformPolicyPpi->MemConfig->tCL = SettingData.tCL; + SaPlatformPolicyPpi->MemConfig->tCWL = SettingData.tCWL; + SaPlatformPolicyPpi->MemConfig->tFAW = SettingData.tFAW; + SaPlatformPolicyPpi->MemConfig->tRAS = SettingData.tRAS; + SaPlatformPolicyPpi->MemConfig->tRC = SettingData.tRC; + SaPlatformPolicyPpi->MemConfig->tRCD = SettingData.tRCD; + SaPlatformPolicyPpi->MemConfig->tREFI = SettingData.tREFI; + SaPlatformPolicyPpi->MemConfig->tRFC = SettingData.tRFC; + SaPlatformPolicyPpi->MemConfig->tRP = SettingData.tRP; + SaPlatformPolicyPpi->MemConfig->tRRD = SettingData.tRRD; + SaPlatformPolicyPpi->MemConfig->tRTP = SettingData.tRTP; + SaPlatformPolicyPpi->MemConfig->tWR = SettingData.tWR; + SaPlatformPolicyPpi->MemConfig->tWTR = SettingData.tWTR; + //SaPlatformPolicyPpi->MemConfig->tRPab = SettingData.tRPab; + } // SettingData.XmpProfilesSelect == 1 + + WRITE_MEM8_MCH(0x5990, (UINT8)SettingData.RuntimeTurbo); + + NbSetupData->GtOcSupport = 0; // if XTU is Enable, Default = disable. + if((SettingData.GraphicTurboRatioLimit!=0xFFFF)){ + NbSetupData->GtMaxOcTurboRatio = SettingData.GraphicTurboRatioLimit; + NbSetupData->GtExtraTurboVoltage = SettingData.GraphicsCoreVoltageOverride; + + NbSetupData->GtVoltageOverride = SettingData.GraphicsCoreVoltageOverride; + NbSetupData->GtVoltageMode = (UINT8)SettingData.GraphicsCoreVoltageMode; + // GT offset + if (SettingData.GraphicsCoreVoltageOffset >=0 && \ + SettingData.GraphicsCoreVoltageOffset <= 999){ + NbSetupData->GtVoltageOffset = ~(1000 - SettingData.GraphicsCoreVoltageOffset) + 1; + }else if (SettingData.GraphicsCoreVoltageOffset >=1000 && \ + SettingData.GraphicsCoreVoltageOffset <= 1998){ + NbSetupData->GtVoltageOffset = SettingData.GraphicsCoreVoltageOffset - 1000; + } + // SA offset + if (SettingData.SystemAgentVoltageOffset >=0 && \ + SettingData.SystemAgentVoltageOffset <= 999){ + NbSetupData->SaVoltageOffset = ~(1000 - SettingData.SystemAgentVoltageOffset) + 1; + }else if (SettingData.SystemAgentVoltageOffset >=1000 && \ + SettingData.SystemAgentVoltageOffset <= 1998){ + NbSetupData->SaVoltageOffset = SettingData.SystemAgentVoltageOffset - 1000; + } + // IOA offset + if (SettingData.IOAnalogVoltageOffset >=0 && \ + SettingData.IOAnalogVoltageOffset <= 999){ + NbSetupData->IoaVoltageOffset = ~(1000 - SettingData.IOAnalogVoltageOffset) + 1; + }else if (SettingData.IOAnalogVoltageOffset >=1000 && \ + SettingData.IOAnalogVoltageOffset <= 1998){ + NbSetupData->IoaVoltageOffset = SettingData.IOAnalogVoltageOffset - 1000; + } + + // IOD offset + if (SettingData.IODigitalVoltageOffset >=0 && \ + SettingData.IODigitalVoltageOffset <= 999){ + NbSetupData->IodVoltageOffset = ~(1000 - SettingData.IODigitalVoltageOffset) + 1; + }else if (SettingData.IODigitalVoltageOffset >=1000 && \ + SettingData.IODigitalVoltageOffset <= 1998){ + NbSetupData->IodVoltageOffset = SettingData.IODigitalVoltageOffset - 1000; + } + NbSetupData->GtOcSupport = 1; + } + }else{ + NbSetupData->GtVoltageOffset = 0; + NbSetupData->GtVoltageOverride = 0; + NbSetupData->GtExtraTurboVoltage = 0; + NbSetupData->GtMaxOcTurboRatio = READ_MEM8_MCH(0x5998); + NbSetupData->SaVoltageOffset = 0; + NbSetupData->GtVoltageMode = 0; + NbSetupData->GtOcSupport = 1; + NbSetupData->IoaVoltageOffset = 0; + NbSetupData->IodVoltageOffset = 0; + } + } +} +#endif +#endif + + /// + /// Initialize the Overclocking Configuration + /// + if (NbSetupData->GtOcSupport == 0) + { + SaPlatformPolicyPpi->OcConfig->GtVoltageOffset = 0; + SaPlatformPolicyPpi->OcConfig->GtVoltageOverride = 0; + SaPlatformPolicyPpi->OcConfig->GtExtraTurboVoltage = 0; + SaPlatformPolicyPpi->OcConfig->GtMaxOcTurboRatio = 0; + SaPlatformPolicyPpi->OcConfig->SaVoltageOffset = 0; + SaPlatformPolicyPpi->OcConfig->GtVoltageMode = 0; + SaPlatformPolicyPpi->OcConfig->OcSupport = 0; + SaPlatformPolicyPpi->OcConfig->IoaVoltageOffset = 0; + SaPlatformPolicyPpi->OcConfig->IodVoltageOffset = 0; + } else { + SaPlatformPolicyPpi->OcConfig->GtVoltageOffset = NbSetupData->GtVoltageOffset; + SaPlatformPolicyPpi->OcConfig->GtVoltageOverride = NbSetupData->GtVoltageOverride; + SaPlatformPolicyPpi->OcConfig->GtExtraTurboVoltage = NbSetupData->GtExtraTurboVoltage; + SaPlatformPolicyPpi->OcConfig->GtMaxOcTurboRatio = NbSetupData->GtMaxOcTurboRatio; + SaPlatformPolicyPpi->OcConfig->SaVoltageOffset = NbSetupData->SaVoltageOffset; + SaPlatformPolicyPpi->OcConfig->GtVoltageMode = NbSetupData->GtVoltageMode; + SaPlatformPolicyPpi->OcConfig->OcSupport = 1; + SaPlatformPolicyPpi->OcConfig->IoaVoltageOffset = NbSetupData->IoaVoltageOffset; + SaPlatformPolicyPpi->OcConfig->IodVoltageOffset = NbSetupData->IodVoltageOffset; + } +// (P20121012A) << Update XTU 4.0 + // Make sure we have a PPI. + if (VariableServices != NULL) { + + // If Maximum TOLUD set to Dynamic assignment in BIOS setup, then set TOLUD/TOLM based on largest MMIO length of graphic controllers + if (NbSetupData->MaxTolud == NB_MAX_TOLUD_DYNAMIC) { + VariableSize = sizeof(UINT32); + Status = VariableServices->GetVariable( + VariableServices, + L"MemCeil.", + &gEfiNbMrcS3DataGuid, + NULL, + &VariableSize, + &MemoryCeiling); + + if(Status == EFI_NOT_FOUND) { + Status = VariableServices->GetVariable( + VariableServices, + L"MemCeil.", + &gEfiGlobalVariableGuid, + NULL, + &VariableSize, + &MemoryCeiling); + } + if(!EFI_ERROR(Status)) { + if(MemoryCeiling >= 0xE0000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_3_5G; + } else if(MemoryCeiling >= 0xD0000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_3_25G; + } else if(MemoryCeiling >= 0xC0000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_3G; + } else if(MemoryCeiling >= 0xB0000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_2_75G; + } else if(MemoryCeiling >= 0xA0000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_2_5G; + } else if(MemoryCeiling >= 0x90000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_2_25G; + } else if(MemoryCeiling >= 0x80000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_2G; + } else if(MemoryCeiling >= 0x70000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_1_75G; + } else if(MemoryCeiling >= 0x60000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_1_5G; + } else if(MemoryCeiling >= 0x50000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_1_25G; + } else if(MemoryCeiling >= 0x40000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_1G; + } else if(MemoryCeiling >= 0x30000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_0_75G; + } else if(MemoryCeiling <= 0x20000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_0_5G; + } + } else { + NbSetupData->MaxTolud = NB_MAX_TOLUD_DYNAMIC; // default value + } + } + } + + // + // Based on BIOS setup to determine maximum top of memory size below 4G, and reserved for MMIO + // + switch (NbSetupData->MaxTolud) { + case NB_MAX_TOLUD_0_5G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0xE00; + break; + + case NB_MAX_TOLUD_0_75G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0xD00; + break; + + case NB_MAX_TOLUD_1G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0xC00; + break; + + case NB_MAX_TOLUD_1_25G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0xB00; + break; + + case NB_MAX_TOLUD_1_5G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0xA00; + break; + + case NB_MAX_TOLUD_1_75G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0x900; + break; + + case NB_MAX_TOLUD_2G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0x800; + break; + + case NB_MAX_TOLUD_2_25G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0x700; + break; + + case NB_MAX_TOLUD_2_5G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0x600; + break; + + case NB_MAX_TOLUD_2_75G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0x500; + break; + + default: + + case NB_MAX_TOLUD_3G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0x400; + break; + + case NB_MAX_TOLUD_3_25G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0x300; + break; + + case NB_MAX_TOLUD_3_5G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0x200; + break; + } + + // EccSupport = 1 for UpSever and WS + if (!(IS_SA_DEVICE_ID_SERVER (McDeviceId) || IS_PCH_LPT_LPC_DEVICE_ID_SERVER(LpcDeviceId)) && + (IS_PCH_LPT_LPC_DEVICE_ID_MOBILE(LpcDeviceId) || IS_PCH_LPT_LPC_DEVICE_ID_DESKTOP(LpcDeviceId))) { + SaPlatformPolicyPpi->MemConfig->EccSupport = NbSetupData->EccSupport; + } else { + SaPlatformPolicyPpi->MemConfig->EccSupport = 1; + } + + // Get the Memory Configuration from NbSetupData + SaPlatformPolicyPpi->MemConfig->MaxTolud = NbSetupData->MaxTolud; + +#if defined SwitchableGraphics_SUPPORT && SwitchableGraphics_SUPPORT == 1 + if (NbSetupData->PrimaryDisplay == 4) // SG + { + SaPlatformPolicyPpi->PcieConfig->AlwaysEnablePeg = 1; // Enable + SaPlatformPolicyPpi->GtConfig->PrimaryDisplay = 0; // IGFX + + /// + /// Initialize the Switchable Graphics Configuration + /// + /// + /// Switchable Graphics mode set as MUXLESS (By default) + /// + SaPlatformPolicyPpi->PlatformData->SgMode = SgModeMuxless; + SaPlatformPolicyPpi->PlatformData->SgSubSystemId = 0x2112; + + /// + /// Configure below based on the OEM platfrom design + /// Switchable Graphics GPIO support - 1=Supported 0=Not Supported + /// + SaPlatformPolicyPpi->SgGpioData->GpioSupport = SG_GPIO_SUPPORT; + + if (SaPlatformPolicyPpi->SgGpioData->GpioSupport) { + /// + /// Initialzie the GPIO Configuration + /// + if (GetPchSeries() == PchLp) { + SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrOK->Value = GPIO_dGPU_PWROK_ULT; // dGPU PWROK GPIO assigned + SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrOK->Active = ACTIVE_dGPU_PWROK_ULT; // dGPU PWROK Active + SaPlatformPolicyPpi->SgGpioData->SgDgpuHoldRst->Value = GPIO_dGPU_HOLD_RST_ULT; // dGPU HLD RST GPIO assigned + SaPlatformPolicyPpi->SgGpioData->SgDgpuHoldRst->Active = ACTIVE_dGPU_HOLD_RST_ULT; // dGPU HLD RST Active + SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrEnable->Value = GPIO_dGPU_PWR_EN_ULT; // dGPU PWR Enable GPIO assigned + SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrEnable->Active = ACTIVE_dGPU_PWR_EN_ULT; // dGPU PWR Enable Active + SaPlatformPolicyPpi->SgGpioData->SgDgpuPrsnt->Value = GPIO_dGPU_PRSNT_ULT; // dGPU_PRSNT# GPIO assigned + SaPlatformPolicyPpi->SgGpioData->SgDgpuPrsnt->Active = ACTIVE_dGPU_PRSNT_ULT; // dGPU_PRSNT# Active Low + + } else{ + SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrOK->Value = GPIO_dGPU_PWROK; // dGPU PWROK GPIO assigned + SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrOK->Active = ACTIVE_dGPU_PWROK; // dGPU PWROK Active + SaPlatformPolicyPpi->SgGpioData->SgDgpuHoldRst->Value = GPIO_dGPU_HOLD_RST; // dGPU HLD RST GPIO assigned + SaPlatformPolicyPpi->SgGpioData->SgDgpuHoldRst->Active = ACTIVE_dGPU_HOLD_RST; // dGPU HLD RST Active + SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrEnable->Value = GPIO_dGPU_PWR_EN; // dGPU PWR Enable GPIO assigned + SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrEnable->Active = ACTIVE_dGPU_PWR_EN; // dGPU PWR Enable Active + SaPlatformPolicyPpi->SgGpioData->SgDgpuPrsnt->Value = GPIO_dGPU_PRSNT; // dGPU_PRSNT# GPIO assigned + SaPlatformPolicyPpi->SgGpioData->SgDgpuPrsnt->Active = ACTIVE_dGPU_PRSNT; // dGPU_PRSNT# Active Low + } + } + } +#endif + +#if (defined RC_PEG_0) && RC_PEG_0 == 1 + if (NbSetupData->DetectNonComplaint && NbSetupData->AlwaysEnablePeg != 2) + { + SaPlatformPolicyPpi->PcieConfig->AlwaysEnablePeg = 1; // Enable + } +#endif + + if (GetPchSeries() == PchLp) { + SaPlatformPolicyPpi->PcieConfig->AlwaysEnablePeg = 2; + } + + // Make sure we have a PPI. + if (VariableServices != NULL) { + + // Get variable size first. + // Set VariableSize = 0 in order to get the required size. + VariableSize = 0; + MrcS3ResumeData = NULL; + + Status = VariableServices->GetVariable ( + VariableServices, + L"MrcS3Resume", + &gMemRestoreDataGuid, + NULL, + &VariableSize, + MrcS3ResumeData + ); + + // Should fail with EFI_BUFFER_TOO_SMALL + if (Status == EFI_BUFFER_TOO_SMALL) { + + // Allocate buffer for S3 data variable. + Status = (*PeiServices)->AllocatePool (PeiServices, VariableSize, &MrcS3ResumeData); + ASSERT_PEI_ERROR (PeiServices, Status); + + Status = VariableServices->GetVariable ( + VariableServices, + L"MrcS3Resume", + &gMemRestoreDataGuid, + NULL, + &VariableSize, + MrcS3ResumeData + ); + } + + if (Status == EFI_SUCCESS) { + // MemoryConfig variable memory layout: MRC_OutputParames, MRC_S3Params + // Increment the pointer, MrcS3ResumeData, to point to MRC_S3Params + SaPlatformPolicyPpi->S3DataPtr = MrcS3ResumeData; + } + + PegGen3Data = NULL; + VariableSize = sizeof(SA_PEG_DATA); + + // Allocate buffer for PegGen3PresetSearch data variable. + Status = (*PeiServices)->AllocatePool (PeiServices, VariableSize, &PegGen3Data); + ASSERT_PEI_ERROR (PeiServices, Status); + + Status = VariableServices->GetVariable ( + VariableServices, + L"PegGen3PresetSearchData", + &gAmiNbPegGen3PresetSearchGuid, + NULL, + &VariableSize, + PegGen3Data + ); + + if (Status == EFI_SUCCESS) { + // Increment the pointer, PegGen3PresetSearch Data, to point to PegDataPtr + SaPlatformPolicyPpi->PcieConfig->PegDataPtr = PegGen3Data; + } + + } + + // Install SA Platform Policy PPI + Status = (**PeiServices).InstallPpi (PeiServices, SaPlatformPolicyPpiDesc); + ASSERT_PEI_ERROR (PeiServices, Status); + + return Status; +} + +#ifdef SSA_FLAG + +MrcStatus +AmiSsaCallbackPpi ( + EFI_PEI_SERVICES **PeiServices, + struct _SSA_BIOS_CALLBACKS_PPI *SsaBiosCallBacksPpi, + MRC_OEM_STATUS_COMMAND StatusCommand, + VOID *CheckpointData) +{ + EFI_STATUS Status; + PEI_MEMORY_ERROR_REPORT_PPI *MemoryErrorPpi; + + // if oem have reinstall gAmiMemoryErrorReportPpi, it can Locate AmiMemoryError for oem. + Status = (*PeiServices)->LocatePpi( + PeiServices, &gAmiMemoryErrorReportPpiGuid, 0, NULL, + &MemoryErrorPpi ); + + ASSERT_PEI_ERROR(PeiServices, Status); + + if (Status == EFI_SUCCESS) + MemoryErrorPpi->AmiMemoryErrorRead(PeiServices, MemoryErrorPpi, (UINT32)StatusCommand); + + return StatusCommand; +} +#endif // #ifndef SSA_FLAG +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: MemoryErrorRead +// +// Description: +// This function reports the error status after memory training. +// +// Parameters: +// IN EFI_PEI_SERVICES PeiServices - PEI Services table pointer +// IN PEI_MEMORY_ERROR_REPORT_PPI *This - Pointer to the PPI structure +// IN OUT UINT32 MemErrData - Pointer to error data buffer +// +// Returns: +// EFI_STATUS +// EFI_SUCCESS The function completed successfully. +// Notes: +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MemoryErrorRead ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_MEMORY_ERROR_REPORT_PPI *This, + IN OUT UINT32 MemErrData + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + switch (MemErrData) { + case MRC_MC_CONFIG_ERROR : + case MRC_MC_MEMORY_MAP_ERROR : + PEI_ERROR_CODE(PeiServices, PEI_MEMORY_CONFIGURING, EFI_ERROR_MAJOR); + break; + case MRC_DIMM_RON_ERROR : + case MRC_DIMM_ODT_ERROR : + case MRC_WRITE_DS_ERROR : + case MRC_WRITE_SR_ERROR : + case MRC_WRITE_EQ_ERROR : + case MRC_READ_ODT_ERROR : + case MRC_READ_EQ_ERROR : + case MRC_READ_AMP_POWER_ERROR : + case MRC_CMP_OPT_ERROR : + case MRC_PWR_MTR_ERROR : + case MRC_SPD_PROCESSING_ERROR : + PEI_ERROR_CODE(PeiServices, PEI_MEMORY_SPD_FAIL, EFI_ERROR_MAJOR); + break; + case MRC_RESET_ERROR : ///< before jedec reset + PEI_ERROR_CODE(PeiServices, PEI_MEMORY_INVALID_TYPE, EFI_ERROR_MAJOR); + break; + case MRC_PRE_TRAINING_ERROR : + case MRC_EARLY_COMMAND_ERROR : + case MRC_JEDEC_INIT_LPDDR3_ERROR : + case MRC_SENSE_AMP_OFFSET_ERROR : + case MRC_RECEIVE_ENABLE_ERROR : + case MRC_JEDEC_WRITE_LEVELING_ERROR : + case MRC_WRITE_TIMING_1D_ERROR : + case MRC_WRITE_TIMING_2D_ERROR : + case MRC_READ_TIMING_1D_ERROR : + case MRC_READ_TIMING_2D_ERROR : + PEI_ERROR_CODE(PeiServices, PEI_MEMORY_INVALID_SPEED, EFI_ERROR_MAJOR); + break; + case MRC_ECC_CLEAN_ERROR : + PEI_ERROR_CODE(PeiServices, PEI_MEMORY_ERROR, EFI_ERROR_MAJOR); + break; + case MRC_NO_MEMORY_DETECTED : + PEI_ERROR_CODE(PeiServices, PEI_MEMORY_NOT_DETECTED, EFI_ERROR_MAJOR); + break; + case MRC_MEM_INIT_DONE_WITH_ERRORS : + PEI_ERROR_CODE(PeiServices, PEI_MEMORY_TEST, EFI_ERROR_MAJOR); + break; + case MRC_WRITE_VREF_2D_ERROR : + case MRC_READ_VREF_2D_ERROR : + case MRC_LATE_COMMAND_ERROR : + case MRC_ROUND_TRIP_LAT_ERROR : + PEI_ERROR_CODE(PeiServices, PEI_MEMORY_NONE_USEFUL, EFI_ERROR_MAJOR); + break; + case MRC_TURN_AROUND_ERROR : + case MRC_SAVE_MC_VALUES_ERROR : + case MRC_RMT_TOOL_ERROR : + case MRC_CPGC_MEMORY_TEST_ERROR : + case MRC_RESTORE_TRAINING_ERROR : + PEI_ERROR_CODE(PeiServices, PEI_MEMORY_MISMATCH, EFI_ERROR_MAJOR); + break; + case MRC_SELF_REFRESH_EXIT_ERROR : + case MRC_MRC_NORMAL_MODE_ERROR : + case MRC_ALIAS_CHECK_ERROR : + case MRC_POST_TRAINING_ERROR : + case MRC_MC_ACTIVATE_ERROR : + case MRC_DONE_WITH_ERROR : + case MRC_FILL_RMT_STRUCTURE_ERROR : + PEI_ERROR_CODE(PeiServices, PEI_MEMORY_NOT_INSTALLED, EFI_ERROR_MAJOR); + break; + default : //Default to " N/A " + break; + } + + return Status; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/NBSMI.C b/Chipset/NB/NBSMI.C new file mode 100644 index 0000000..478ec8b --- /dev/null +++ b/Chipset/NB/NBSMI.C @@ -0,0 +1,996 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB SMI/NBSMI.C 5 10/14/12 12:17a Jeffch $ +// +// $Revision: 5 $ +// +// $Date: 10/14/12 12:17a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB SMI/NBSMI.C $ +// +// 5 10/14/12 12:17a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Follow MahoBay Update. +// [Files] NBSMI.c, NBSMI.Dxe +// +// 3 6/14/12 4:36a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Fixed PEG PERR log lost issue. +// [Description] NBSMI.C +// +// 2 4/05/12 3:18a Yurenlai +// [TAG] EIP87103 +// [Category] Spec Update +// [Severity] Important +// [Description] Change for SystemAgent RefCode Revision: 0.5.5 . +// [Files] NBDxe.c, NBPEI.c, NBSMI.C, NBGeneric.cm NB.sd, NBSetup.c, +// GetSetupData.c, NbSetupData.h +// +// 1 2/08/12 4:34a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: NBSMI.c +// +// Description: This file contains code for all North Bridge SMI events +// +//<AMI_FHDR_END> +//************************************************************************* + +//---------------------------------------------------------------------------- +// Include(s) +//---------------------------------------------------------------------------- + +#include <Token.h> +#include <AmiDxeLib.h> +#include <Protocol\SmmBase.h> +#include <Protocol\SmmSwDispatch.h> +#include <Protocol\SmmSxDispatch.h> +#include <Protocol\NBPlatformData.h> +#include <AmiCspLib.h> +#include <Setup.h> +#if NB_ERROR_LOG_SUPPORT +#include <Edk\Foundation\Framework\Protocol\SmmIchnDispatch\SmmIchnDispatch.h> +#include <Protocol\SmbiosElogSupport.h> +#include <NBSMI.h> +#endif +//---------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//---------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//---------------------------------------------------------------------------- +// Variable and External Declaration(s) +//---------------------------------------------------------------------------- +// Variable Declaration(s) +static BOOLEAN gEccErrHandleEnable = FALSE; +static BOOLEAN gPegErrHandleEnable = FALSE; +NB_ASL_BUFFER *gNbAslBufPtr = NULL; +NB_SETUP_DATA *gNbSetupData = NULL; +// GUID Definition(s) +#if NB_ERROR_LOG_SUPPORT +EFI_GUID gNbErrorLogDispatchProtocolGuid = EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL_GUID; +EFI_GUID gIchnDispatchProtocolGuid = EFI_SMM_ICHN_DISPATCH_PROTOCOL_GUID; +#endif +// Protocol Definition(s) + +// External Declaration(s) + +// Function Definition(s) +//---------------------------------------------------------------------------- +// Variable and External Declaration(s) +//---------------------------------------------------------------------------- +// Variable Declaration(s) +#if NB_ERROR_LOG_SUPPORT +NB_ERROR_LOG_DISPATCH_LINK *gNbErrorLogDispatchHead = 0, *gNbErrorLogDispatchTail = 0; + +UINT32 NBPcieBridge[] = +{ + {(UINT32)NB_PCIE_CFG_ADDRESS(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, PCI_VID)}, + {(UINT32)NB_PCIE_CFG_ADDRESS(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN1, PCI_VID)}, + {(UINT32)NB_PCIE_CFG_ADDRESS(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN2, PCI_VID)}, + {0xFFFFFFFF} +}; + +EFI_STATUS NbErrorLogRegister ( + IN EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL *This, + IN EFI_NB_ERROR_LOG_DISPATCH Function, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS NbErrorLogUnregister ( + IN EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL gEfiNbErrorLogDispatchProtocol = \ + {NbErrorLogRegister, NbErrorLogUnregister}; + +NB_ERROR_INFO NbErrorInfo; +UINT32 DevBaseAddr = 0; + +#if NB_ECC_ERROR_LOG_SUPPORT +EFI_STATUS NBEccErrLogHandle(VOID); +#endif + +#endif + +#if NB_ERROR_LOG_SUPPORT +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: AddLink +// +// Description: Create and add link to specified list. +// +// Parameters: Size - +// Head - +// Tail - +// +// Returns: VOID Pointer +// +// Modified: +// +// Referrals: SmmAllocatePool +// +// Notes: Here is the control flow of this function: +// 1. Allocate Link in Smm Pool. +// 2. Add Link to end. +// 3. Return Link address. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID * AddLink ( + IN UINT32 Size, + IN VOID **Head, + IN VOID **Tail ) +{ + VOID *Link; + + if (pSmst->SmmAllocatePool(0, Size, &Link) != EFI_SUCCESS) return 0; + + ((GENERIC_LINK*)Link)->Link = 0; + if (!*Head) { + *Head = *Tail = Link; + } else { + ((GENERIC_LINK*)*Tail)->Link = Link; + *Tail = Link; + } + + return Link; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RemoveLink +// +// Description: Remove link from specified list. +// +// Parameters: Handle - EFI Handle +// Head - +// Tail - +// +// Returns: BOOLEAN +// TRUE if link was removed. FALSE if link not in the list. +// +// Modified: +// +// Referrals: SmmFreePool +// +// Notes: Here is the control flow of this function: +// 1. Search link list for Link. +// 2. Remove link from list. +// 3. Free link. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN RemoveLink ( + IN EFI_HANDLE Handle, + IN VOID **Head, + IN VOID **Tail ) +{ + GENERIC_LINK *PrevLink,*Link; + + PrevLink = *Head; + + // Is link first. Link address is the same as the Handle. + if (((GENERIC_LINK*)*Head) == Handle) { + if (PrevLink == *Tail) *Tail = 0; // If Tail = Head, then 0. + *Head = PrevLink->Link; + pSmst->SmmFreePool(PrevLink); + return TRUE; + } + + // Find Link. + for (Link=PrevLink->Link; Link; PrevLink=Link, Link=Link->Link) { + if (Link == Handle) { // Link address is the same as the Handle. + if (Link == *Tail) *Tail = PrevLink; + PrevLink->Link = Link->Link; + pSmst->SmmFreePool(Link); + return TRUE; + } + } + + return FALSE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiNbErrorLogEnRegister +// +// Description: Register a Link on NbErrorLog enable SMI. +// +// Parameters: This - +// Function - +// Context - +// +// +// Returns: Handle - +// EFI_STATUS +// +// Modified: gNbErrorLogDispatchHead, gNbErrorLogDispatchTail +// +// Referrals: AddLink +// +// Notes: Here is the control flow of this function: +// 1. Verify if Context if valid. If invalid, +// return EFI_INVALID_PARAMETER. +// 2. Allocate structure and add to link list. +// 3. Fill link. +// 4. Enable Smi Source. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NbErrorLogRegister ( + IN EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL *This, + IN EFI_NB_ERROR_LOG_DISPATCH Function, + OUT EFI_HANDLE *Handle ) +{ + NB_ERROR_LOG_DISPATCH_LINK *NewLink; + + NewLink = AddLink( sizeof(NB_ERROR_LOG_DISPATCH_LINK), \ + &gNbErrorLogDispatchHead, \ + &gNbErrorLogDispatchTail ); + if (!NewLink) return EFI_OUT_OF_RESOURCES; + + NewLink->Function = Function; + *Handle = NewLink; + +#if NB_ECC_ERROR_LOG_SUPPORT + if(((READ_PCI16_NB(0xC8) & (BIT00 | BIT01)) != 0) && gEccErrHandleEnable) + { + NBEccErrLogHandle(); + } +#endif + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbErrorLogUnregister +// +// Description: Unregister a Link on NbErrorLog enable SMI. +// +// Parameters: This - +// Handle - +// +// Returns: EFI_STATUS +// +// Modified: gNbErrorLogDispatchHead, gNbErrorLogDispatchTail +// +// Referrals: RemoveLink +// +// Notes: Here is the control flow of this function: +// 1. Remove link. If no link, return EFI_INVALID_PARAMETER. +// 2. Disable SMI Source if no other handlers using source. +// 3. Return EFI_SUCCESS. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NbErrorLogUnregister ( + IN EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ + if (!RemoveLink(Handle, &gNbErrorLogDispatchHead, &gNbErrorLogDispatchTail)) + return EFI_INVALID_PARAMETER; + return EFI_SUCCESS; +} +#endif +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetNbSmiContext +// +// Description: This is a template NB SMI GetContext for Porting. +// +// Input: None +// +// Output: BOOLEAN +// +// Notes: Here is the control flow of this function: +// 1. Check if NB Smi source. +// 2. If yes, return TRUE. +// 3. If not, return FALSE. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN GetNbSmiContext (VOID) +{ + return FALSE; +} + +#if NB_ERROR_LOG_SUPPORT +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBPcieErrLogHandle +// +// Description: Init NB PCIE Error devices log. +// +// Input: VOID +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID NBPcieErrLogHandle (VOID) +{ + EFI_STATUS Status = EFI_SUCCESS; + NB_ERROR_LOG_DISPATCH_LINK *Link; + UINT8 CapPtr; + UINT16 PciStatus; + UINT16 PcieStatus; + UINT16 DeviceStatus; + +// if (READ_IO8(NMI_SC_PORT) & BIT7) // SERR#_NMI_STS? +// { + + MemSet((VOID*)&NbErrorInfo, sizeof(NB_ERROR_INFO), 0); + + PciStatus = READ_MEM16(DevBaseAddr + 0x06); + PcieStatus = READ_MEM16(DevBaseAddr + 0x1E); + + CapPtr = NbFindCapPtr(DevBaseAddr, 0x10); + if (CapPtr != 0) + DeviceStatus = READ_MEM16(DevBaseAddr + CapPtr + 0x0A); + + if ((PciStatus & (BIT8 | BIT15)) || (PcieStatus & (BIT8 | BIT15))) + NbErrorInfo.PcieErrorInfo.ParityError = TRUE; + else + NbErrorInfo.PcieErrorInfo.ParityError = FALSE; + + if (READ_IO8(NMI_SC_PORT) & BIT7) // SERR#_NMI_STS? + { + if ((PciStatus & BIT14) || (PcieStatus & BIT14) || ((CapPtr != 0) && (DeviceStatus & 0x7))) + NbErrorInfo.PcieErrorInfo.SystemError = TRUE; + else + NbErrorInfo.PcieErrorInfo.SystemError = FALSE; + } + + if ((NbErrorInfo.PcieErrorInfo.ParityError) || (NbErrorInfo.PcieErrorInfo.SystemError)) + { + NbErrorInfo.PcieErrorInfo.Bus = (DevBaseAddr >> 20) & ((UINT8)((PCIEX_LENGTH >> 20) - 1)); + NbErrorInfo.PcieErrorInfo.Dev = (DevBaseAddr >> 15) & 0x1F; + NbErrorInfo.PcieErrorInfo.Fun = (DevBaseAddr >> 12) & 0x07; + NbErrorInfo.PcieErrorInfo.VendorId = READ_MEM16(DevBaseAddr + 0x00); + NbErrorInfo.PcieErrorInfo.DeviceId = READ_MEM16(DevBaseAddr + 0x02); + NbErrorInfo.PcieErrorInfo.PciCommand = READ_MEM16(DevBaseAddr + 0x04); + NbErrorInfo.PcieErrorInfo.PciCCode = READ_MEM16(DevBaseAddr + 0x0A); + NbErrorInfo.PcieErrorInfo.BridgeControl = READ_MEM16(DevBaseAddr + 0x3E); + NbErrorInfo.PcieErrorInfo.Version = READ_MEM8(DevBaseAddr + CapPtr + 0x02) & 0x0F; + NbErrorInfo.PcieErrorInfo.PortType = (UINT32)((READ_MEM8(DevBaseAddr + CapPtr + 0x02) & 0xF0) >> 4); + + if (CapPtr != 0) { + NbErrorInfo.PcieErrorInfo.Correctable = (DeviceStatus & BIT0)? TRUE : FALSE; + NbErrorInfo.PcieErrorInfo.NonFatal = (DeviceStatus & BIT1)? TRUE : FALSE; + NbErrorInfo.PcieErrorInfo.Fatal = (DeviceStatus & BIT2)? TRUE : FALSE; + } + + NbErrorInfo.ErrorType = NbPcieError; // PCIE Error + + // Clear Error status + WRITE_MEM16(DevBaseAddr + 0x06, PciStatus); + WRITE_MEM16(DevBaseAddr + 0x1E, PcieStatus); + + if (CapPtr != 0) + // Clear Error Status + WRITE_MEM16(DevBaseAddr + CapPtr + 0x0A, DeviceStatus); + + // Clear DMISERR + SET_IO16((TCO_BASE_ADDRESS + 0x04), BIT12); + + // Clear SERR#_NMI_STS & NMI2SMI_STS by set Port 61h[2] = 1 then set it to 0. + if(NbErrorInfo.PcieErrorInfo.SystemError) + { + SET_IO8(NMI_SC_PORT, BIT02); + RESET_IO8(NMI_SC_PORT, BIT02); + } + + for(Link = gNbErrorLogDispatchHead; Link; Link = Link->Link) { + Link->Function(Link, NbErrorInfo); + } + } +// }// SERR#_NMI_STS? +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetNbPcieContext +// +// Description: The function will check PCIE error event. +// +// Input: N/A +// +// Output: EFI_SUCCESS - ECC error event generated. +// Other - No ECC error event +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN GetNbPcieContext( +) +{ + UINT8 i; + + if(!gPegErrHandleEnable) return FALSE; + + for (i = 0; NBPcieBridge[i] != 0xFFFFFFFF; i++) + { + DevBaseAddr = NBPcieBridge[i]; + if (READ_MEM32(DevBaseAddr) == 0xFFFFFFFF) + continue; + + if(((READ_MEM16(DevBaseAddr + PCI_CMD) & (BIT6 | BIT8)) == (BIT6 | BIT8)) && + (((READ_MEM16(DevBaseAddr + 0x06) & (BIT08 | BIT14 | BIT15)) != 0) || + ((READ_MEM16(DevBaseAddr + 0x1E) & (BIT08 | BIT14 | BIT15)) != 0))) + { + return TRUE; + } + } + return FALSE; +} +#endif + +#if NB_ECC_ERROR_LOG_SUPPORT +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EccEnableFunction +// +// Description: The function will check what ECC feature is enable or disable. +// +// Input: N/A +// +// Output: EFI_SUCCESS - ECC feature is support. +// EFI_UNSUPPORTED - ECC feature is not support +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS EccEnableFunction(VOID) +{ + if (((READ_MEM32_MCH(0x5004) & (BIT24 | BIT25)) != 0) || \ + ((READ_MEM32_MCH(0x5008) & (BIT24 | BIT25)) != 0)) + { + RW_MEM32_MCH(0x40B8, 0, (BIT14 | BIT16 | BIT17)); + RW_MEM32_MCH(0x44B8, 0, (BIT14 | BIT16 | BIT17)); + + // Disable Error and SCI Commands + RW_PCI16_NB(0xCA, 0, (BIT00 | BIT01)); + RW_PCI16_NB(0xCE, 0, (BIT00 | BIT01)); + + // Enable SMI Command +// RW_PCI16_NB(0xC8, (BIT00 | BIT01), 0); + RW_PCI16_NB(0xCC, (BIT00 | BIT01), 0); + + return EFI_SUCCESS; + } + + return EFI_UNSUPPORTED; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetNbEccContext +// +// Description: The function will check ECC error event. +// +// Input: N/A +// +// Output: EFI_SUCCESS - ECC error event generated. +// Other - No ECC error event +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN GetNbEccContext(VOID) +{ + if (gEccErrHandleEnable) + { + if (((READ_PCI16_NB(0xCC) & (BIT00 | BIT01)) != 0) && + ((READ_PCI16_NB(0xC8) & (BIT00 | BIT01)) != 0)) + { + return TRUE; + } + } + + return FALSE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBEccErrLogHandle +// +// Description: This function handles ECC error. +// +// Input: *This - NB SMI Context pointer +// +// Output: EFI_SUCCESS - ECC error is handled. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS NBEccErrLogHandle(VOID) +{ + + NB_ERROR_INFO NbErrorInfo; + NB_ERROR_LOG_DISPATCH_LINK *Link; + + MemSet((VOID*)&NbErrorInfo, sizeof(NB_ERROR_INFO), 0); + + if ((READ_MEM32_MCH(0x4CC8) & (BIT00 | BIT01)) != 0) + { + NbErrorInfo.EccErrorInfo.EccErrLog0 = READ_MEM32_MCH(0x4CC8); + NbErrorInfo.EccErrorInfo.EccErrLog1 = READ_MEM32_MCH(0x4CCC); + } + + // Channel 0 + if ((READ_MEM32_MCH(0x40C8) & (BIT00 | BIT01)) != 0) + { + NbErrorInfo.EccErrorInfo.Ch0_EccErrLog0 = READ_MEM32_MCH(0x40C8); + NbErrorInfo.EccErrorInfo.Ch0_EccErrLog1 = READ_MEM32_MCH(0x40CC); + // [28:27] 00 or 01 = DimmNum 0, 10 or 11 = DimmNum 1 + NbErrorInfo.EccErrorInfo.EccErrDimmNum = (READ_MEM32_MCH(0x40C8) & BIT28) ? 1 : 0; + } + + // Channel 1 + if ((READ_MEM32_MCH(0x44C8) & (BIT00 | BIT01)) != 0) + { + NbErrorInfo.EccErrorInfo.Ch1_EccErrLog0 = READ_MEM32_MCH(0x44C8); + NbErrorInfo.EccErrorInfo.Ch1_EccErrLog1 = READ_MEM32_MCH(0x44CC); + // [28:27] 00 or 01 = DimmNum 0, 10 or 11 = DimmNum 1 + NbErrorInfo.EccErrorInfo.EccErrDimmNum = (READ_MEM32_MCH(0x44C8) & BIT28) ? 3 : 2; + } + + if ((READ_PCI16_NB(0xC8) & BIT00) != 0) + NbErrorInfo.EccErrorInfo.Correctable = 1; + + if ((READ_PCI16_NB(0xC8) & BIT01) != 0) + NbErrorInfo.EccErrorInfo.UnCorrectable = 1; + + NbErrorInfo.ErrorType = NbEccError; // Ecc Error + + for(Link = gNbErrorLogDispatchHead; Link; Link = Link->Link) { + Link->Function(Link, NbErrorInfo); + } + + RW_PCI16_NB(0xC8, (BIT00 | BIT01), 0); + +#if ECC_MULTI_BIT_TYPE_HANG == 1 + if (NbErrorInfo.EccErrorInfo.UnCorrectable == 1){ + EFI_DEADLOOP() + } +#endif + + return EFI_SUCCESS; +} +#endif + +#if NB_ERROR_LOG_SUPPORT +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBErrLogHandler +// +// Description: North Bridge error logging handler. +// +// Input: DispatchHandle - Handle of dispatch function, for when interfacing +// with the parent SMM driver, will be the address of linked +// list link in the call back record. +// DispatchContext - Pointer to the dispatch function's context. +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID NBErrLogHandler ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_ICHN_DISPATCH_CONTEXT *DispatchContext +) +{ +//#if NB_PCIE_ERROR_LOG_SUPPORT +// if (GetNbPcieContext()) NBPcieErrLogHandle(); +//#endif +} + +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbSmiHandler +// +// Description: This is a template NB SMI Handler for Porting. +// +// Input: None +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbSmiHandler (VOID) +{ + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbSwSmiIgfxGetSetupHandler +// +// Description: This is a NB software SMI Handler for IGFX int15 get setup data. +// +// Input: DispatchHandle - EFI Handle +// DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbSwSmiIgfxGetSetupHandler ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext ) +{ + EFI_SMM_CPU_SAVE_STATE *pCpuSaveState = pSmst->CpuSaveState; + UINTN Cpu = pSmst->CurrentlyExecutingCpu - 1; + UINT8 RegBL; + + // Nb int 15 go to here + RegBL = (UINT8)pCpuSaveState[Cpu].Ia32SaveState.EBX; + + switch (RegBL) { + case IGFX_LCD_PANEL_TYPE: // 0x80 + pCpuSaveState[Cpu].Ia32SaveState.EBX = (UINT8)gNbSetupData->LcdPanelType; + break; + case IGFX_LCD_PANEL_SCALING: // 0x81 + pCpuSaveState[Cpu].Ia32SaveState.EBX = (UINT8)gNbSetupData->LcdPanelScaling; + break; + case IGFX_BOOT_TYPE: // 0x82 + pCpuSaveState[Cpu].Ia32SaveState.EBX = (UINT8)gNbSetupData->IgdBootType; + break; + case IGFX_BACKLIGHT_TYPE: // 0x83 + pCpuSaveState[Cpu].Ia32SaveState.EBX = (UINT8)gNbSetupData->IgdLcdBlc; + break; + case IGFX_LFP_PANEL_COLOR_DEPTH_TYPE: // 0x84 + pCpuSaveState[Cpu].Ia32SaveState.EBX = (UINT8)gNbSetupData->LfpColorDepth; + break; + case IGFX_EDP_ACTIVE_LFP_CONFIG_TYPE: // 0x85 + pCpuSaveState[Cpu].Ia32SaveState.EBX = (UINT8)gNbSetupData->ActiveLFP; + break; + case IGFX_PRIMARY_DISPLAY_TYPE: // 0x86 + pCpuSaveState[Cpu].Ia32SaveState.EBX = (UINT8)gNbSetupData->PrimaryDisplay; + break; + case IGFX_DISPLAY_PIPE_B_TYPE: // 0x87 + pCpuSaveState[Cpu].Ia32SaveState.EBX = (UINT8)gNbSetupData->DisplayPipeB; + break; + case IGFX_SDVO_PANEL_TYPE: // 0x88 + pCpuSaveState[Cpu].Ia32SaveState.EBX = (UINT8)gNbSetupData->SdvoPanelType; + break; + default: + break; + } // switch + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbSxSmiHandler +// +// Description: This is a template NB Sx SMI Handler for Porting. +// +// Input: DispatchHandle - EFI Handle +// DispatchContext - Pointer to the EFI_SMM_SX_DISPATCH_CONTEXT +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbSxSmiHandler ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_SX_DISPATCH_CONTEXT *DispatchContext ) +{ +/* + // SMBAVUMA Workaround + WRITE_IO8(0x3c4, 0x01); + SET_IO8(0x3c5, 0x20); +*/ +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbChildDispatcher +// +// Description: North Bridge SMM Child Dispatcher Handler. +// +// Input: SmmImageHandle - +// *CommunicationBuffer - OPTIONAL +// *SourceSize - OPTIONAL +// +// Output: EFI_STATUS +// +// Modified: +// +// Referrals: EfiSmmSwDispatch EfiSmmSxDispatch +// +// Notes: Here is the control flow of this function: +// 1. Read SMI source status registers. +// 2. If source, call handler. +// 3. Repeat #2 for all sources registered. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NbChildDispatcher ( + IN EFI_HANDLE SmmImageHandle, + IN OUT VOID *CommunicationBuffer OPTIONAL, + IN OUT UINTN *SourceSize OPTIONAL ) +{ + if (GetNbSmiContext()) NbSmiHandler(); +#if NB_ECC_ERROR_LOG_SUPPORT + if (GetNbEccContext()) NBEccErrLogHandle(); +#endif +#if NB_PCIE_ERROR_LOG_SUPPORT + if (GetNbPcieContext()) NBPcieErrLogHandle(); +#endif + return EFI_HANDLER_SUCCESS; +} + +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InSmmFunction +// +// Description: Installs North Bridge SMM Child Dispatcher Handler. +// +// Input: ImageHandle - Image handle +// *SystemTable - Pointer to the system table +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS InSmmFunction ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status; + EFI_STATUS IchnDispatchStatus = EFI_SUCCESS; + EFI_SMM_SW_DISPATCH_PROTOCOL *pSwDispatch; + EFI_SMM_SX_DISPATCH_PROTOCOL *pSxDispatch; + EFI_SMM_SW_DISPATCH_CONTEXT SwContext = {NB_SWSMI_IGFX_GET_SETUP}; + EFI_SMM_SX_DISPATCH_CONTEXT SxContext = {SxS3, SxEntry}; + EFI_HANDLE DummyHandle = NULL; + EFI_HANDLE Handle; + EFI_SMM_BASE_PROTOCOL *SmmBaseProtocol; + EFI_GUID NbAslBufPtrGuid = NB_ASL_BUFFER_PTR_GUID; + CHAR16 NbAslBufPtrVar[] = \ + NB_ASL_BUFFER_PTR_VARIABLE; + UINTN VarSize = sizeof(UINT32); + UINT32 NbAslBufPtr; + UINTN VariableSize = sizeof(NB_SETUP_DATA); +#if NB_ERROR_LOG_SUPPORT + EFI_SMM_ICHN_DISPATCH_PROTOCOL *IchnDispatch; + EFI_SMM_ICHN_DISPATCH_CONTEXT IchnContext; +#endif + + // + // Get SETUP variables and change defaults for some boards. + // + + Status = pRS->GetVariable( NbAslBufPtrVar, \ + &NbAslBufPtrGuid, \ + NULL, \ + &VarSize, \ + &NbAslBufPtr ); + if (!EFI_ERROR(Status)) gNbAslBufPtr = (NB_ASL_BUFFER *)NbAslBufPtr; + + Status = pBS->LocateProtocol( &gEfiSmmBaseProtocolGuid, \ + NULL, \ + &SmmBaseProtocol ); + if (EFI_ERROR(Status)) return Status; + + Status = SmmBaseProtocol->SmmAllocatePool( \ + SmmBaseProtocol, \ + EfiRuntimeServicesData, \ + VariableSize, \ + &gNbSetupData ); + if (!EFI_ERROR (Status)){ + GetNbSetupData( pRS, gNbSetupData, FALSE ); + } else { + gNbSetupData->EccSupport = 0; + gNbSetupData->LcdPanelType = 0; + gNbSetupData->SdvoPanelType = 0; + gNbSetupData->LcdPanelScaling = 0; + gNbSetupData->IgdBootType = 0; + gNbSetupData->DisplayPipeB = 0; + gNbSetupData->IgdLcdBlc = 0; + gNbSetupData->ActiveLFP = 1; + gNbSetupData->LfpColorDepth = 0; + gNbSetupData->PrimaryDisplay = 3; + } + + Status = pBS->LocateProtocol( &gEfiSmmSwDispatchProtocolGuid, \ + NULL, \ + &pSwDispatch ); + if (!EFI_ERROR(Status)) { + + if (READ_PCI32_IGD (R_SA_IGD_VID) != 0xFFFFFFFF) { + + Status = pSwDispatch->Register( pSwDispatch, \ + NbSwSmiIgfxGetSetupHandler, \ + &SwContext, \ + &Handle ); + + } + } + + Status = pBS->LocateProtocol( &gEfiSmmSxDispatchProtocolGuid, \ + NULL, \ + &pSxDispatch ); + if (!EFI_ERROR(Status)) { + Status = pSxDispatch->Register( pSxDispatch, \ + NbSxSmiHandler, \ + &SxContext, \ + &Handle ); + } + +#if NB_ERROR_LOG_SUPPORT + + if (gNbSetupData->SmbiosLogging == 1) + { + + Status = pBS->LocateProtocol ( &gIchnDispatchProtocolGuid, \ + NULL, \ + &IchnDispatch ); + +#if NB_ECC_ERROR_LOG_SUPPORT + + if(gNbSetupData->EccSupport) + { + if (!EFI_ERROR(Status)) + { + IchnContext.Type = IchnMch; //TCO DMI SMI + IchnDispatchStatus = IchnDispatch->Register( IchnDispatch, \ + NBErrLogHandler, \ + &IchnContext, \ + &Handle ); + ASSERT_EFI_ERROR (IchnDispatchStatus); + + if (!EFI_ERROR(IchnDispatchStatus)) gEccErrHandleEnable = TRUE; + // Enable ECC error log function + //EccEnableFunction(); + } + } + +#endif + +#if NB_PCIE_ERROR_LOG_SUPPORT + + if (!EFI_ERROR(Status)) + { + IchnContext.Type = IchnNmi; //TCO NMI2 SMI + IchnDispatchStatus = IchnDispatch->Register( IchnDispatch, \ + NBErrLogHandler, \ + &IchnContext, \ + &Handle ); + ASSERT_EFI_ERROR (IchnDispatchStatus); + + if (!EFI_ERROR(IchnDispatchStatus)) gPegErrHandleEnable = TRUE; + + } + +#endif + + + +// pBS->FreePool( NBSetupData ); + + Status = pBS->InstallProtocolInterface( &DummyHandle, \ + &gNbErrorLogDispatchProtocolGuid, \ + EFI_NATIVE_INTERFACE, \ + &gEfiNbErrorLogDispatchProtocol ); + } +#endif + + // Register Callbacks + SmmBaseProtocol->RegisterCallback( SmmBaseProtocol, \ + ImageHandle, \ + NbChildDispatcher, \ + FALSE, \ + FALSE ); + + return EFI_SUCCESS; + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitializeNBSmm +// +// Description: Installs North Bridge SMM Child Dispatcher Handler. +// +// Input: ImageHandle - Image handle +// *SystemTable - Pointer to the system table +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS InitializeNBSmm ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + InitAmiLib(ImageHandle, SystemTable); + return InitSmmHandler(ImageHandle, SystemTable, InSmmFunction, NULL); +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/NBSMI.CIF b/Chipset/NB/NBSMI.CIF new file mode 100644 index 0000000..099a66e --- /dev/null +++ b/Chipset/NB/NBSMI.CIF @@ -0,0 +1,12 @@ +<component> + name = "NB SMI" + category = ModulePart + LocalRoot = "Chipset\NB" + RefName = "NBSMI" +[files] +"\NBSMI.C" +"\NBSMI.H" +"\NBSMI.MAK" +"\NBSMI.DXS" +"\NBSMI.SDL" +<endComponent> diff --git a/Chipset/NB/NBSMI.DXS b/Chipset/NB/NBSMI.DXS new file mode 100644 index 0000000..7f41c0a --- /dev/null +++ b/Chipset/NB/NBSMI.DXS @@ -0,0 +1,76 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB SMI/NBSMI.DXS 2 10/14/12 12:16a Jeffch $ +// +// $Revision: 2 $ +// +// $Date: 10/14/12 12:16a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB SMI/NBSMI.DXS $ +// +// 2 10/14/12 12:16a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Follow MahoBay Update. +// [Files] NBSMI.c, NBSMI.Dxe +// +// 1 2/08/12 4:35a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: NbSmi.dxs +// +// Description: This file is the dependency file for the North Bridge SMI +// handler. +// +//<AMI_FHDR_END> +//************************************************************************* +#include <token.h> +#if defined(PI_SPECIFICATION_VERSION) && (PI_SPECIFICATION_VERSION >= 0x0001000A) +#include <Protocol\SmmSwDispatch2.h> +#include <Protocol\SmmSxDispatch2.h> +#else +#include <Protocol\SmmSwDispatch.h> +#include <Protocol\SmmSxDispatch.h> +#endif + +DEPENDENCY_START +#if defined(PI_SPECIFICATION_VERSION) && (PI_SPECIFICATION_VERSION >= 0x0001000A) + EFI_SMM_SW_DISPATCH2_PROTOCOL_GUID AND + EFI_SMM_SX_DISPATCH2_PROTOCOL_GUID +#else + EFI_SMM_SW_DISPATCH_PROTOCOL_GUID AND + EFI_SMM_SX_DISPATCH_PROTOCOL_GUID +#endif +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/NBSMI.H b/Chipset/NB/NBSMI.H new file mode 100644 index 0000000..4bdc232 --- /dev/null +++ b/Chipset/NB/NBSMI.H @@ -0,0 +1,153 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB SMI/NBSMI.H 1 2/08/12 4:34a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 4:34a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB SMI/NBSMI.H $ +// +// 1 2/08/12 4:34a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +//************************************************************************* +// +// Name: NBSMI.h +// +// Description: This file contains all definitions for South Bridge SMI +// driver +// +//************************************************************************* +//<AMI_FHDR_END> + +#ifndef _NBSMI_H__ +#define _NBSMI_H__ + +// {FF2D54D4-5C55-4c06-8549-C3627CB8B995} +#define EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL_GUID \ + {0xff2d54d4, 0x5c55, 0x4c06, 0x85, 0x49, 0xc3, 0x62, 0x7c, 0xb8, 0xb9, 0x95} + +typedef enum { + NbErrorNone, + NbEccError, + NbPcieError, + NbErrorMax, +} AMI_NB_ERROR_LOG_TYPE; + +// Prototypes +typedef struct _NB_ECC_INFO +{ + UINT32 Correctable:1; + UINT32 UnCorrectable:1; + UINT32 EccErrDimmNum:2; // DIMM 0/1/2/3 + UINT32 Reserved:28; + UINT32 EccErrLog0; + UINT32 EccErrLog1; + UINT32 Ch0_EccErrLog0; + UINT32 Ch0_EccErrLog1; + UINT32 Ch1_EccErrLog0; + UINT32 Ch1_EccErrLog1; +} NB_ECC_INFO; + +typedef struct _NB_PCIE_INFO +{ + UINT8 Bus; + UINT8 Dev; + UINT8 Fun; + UINT16 VendorId; + UINT16 DeviceId; + UINT16 PciCommand; + UINT16 PciStatus; + UINT16 PciCCode; + UINT16 PcieStatus; + UINT32 PortType; + UINT8 Version; + UINT16 SecondaryStatus; + UINT16 BridgeControl; + BOOLEAN Correctable; + BOOLEAN NonFatal; + BOOLEAN Fatal; + BOOLEAN ParityError; + BOOLEAN SystemError; +} NB_PCIE_INFO; + +typedef struct _NB_ERROR_INFO +{ + UINT8 ErrorType; + NB_ECC_INFO EccErrorInfo; + NB_PCIE_INFO PcieErrorInfo; +} NB_ERROR_INFO; + +typedef struct _EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL; + +#ifndef __SMM_CHILD_DISPATCH__H__ +#ifndef _SB_SMI_PROTOCOL_H +typedef struct _GENERIC_LINK GENERIC_LINK; +typedef struct _GENERIC_LINK { + void *Link; +}; +#endif +#endif + +typedef VOID (EFIAPI *EFI_NB_ERROR_LOG_DISPATCH) ( + IN EFI_HANDLE DispatchHandle, + IN NB_ERROR_INFO NbErrorInfo +); + +typedef struct _NB_ERROR_LOG_DISPATCH_LINK NB_ERROR_LOG_DISPATCH_LINK; +struct _NB_ERROR_LOG_DISPATCH_LINK { + IN NB_ERROR_LOG_DISPATCH_LINK *Link; + IN EFI_NB_ERROR_LOG_DISPATCH Function; +}; + +typedef EFI_STATUS (EFIAPI *EFI_NB_ERROR_LOG_REGISTER) ( + IN EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL *This, + IN EFI_NB_ERROR_LOG_DISPATCH DispatchFunction, + OUT EFI_HANDLE *DispatchHandle +); + +typedef EFI_STATUS (EFIAPI *EFI_NB_ERROR_LOG_UNREGISTER) ( + IN EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle +); + +struct _EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL { + EFI_NB_ERROR_LOG_REGISTER Register; + EFI_NB_ERROR_LOG_UNREGISTER UnRegister; +}; + +#define NMI_SC_PORT 0x61 + +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/NBSMI.MAK b/Chipset/NB/NBSMI.MAK new file mode 100644 index 0000000..2553524 --- /dev/null +++ b/Chipset/NB/NBSMI.MAK @@ -0,0 +1,72 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB SMI/NBSMI.MAK 1 2/08/12 4:35a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 4:35a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB SMI/NBSMI.MAK $ +# +# 1 2/08/12 4:35a Yurenlai +# Intel Haswell/NB eChipset initially releases. +# +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: NBSMI.MAK +# +# Description: Make file for the NB SMI handler code +# +#<AMI_FHDR_END> +#************************************************************************* + +all : NBSMI + +NBSMI: $(BUILD_DIR)\NBSMI.mak NBSMIBin + +$(BUILD_DIR)\NBSMI.mak : $(NB_SMI_PATH)\NBSMI.cif $(NB_SMI_PATH)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(NB_SMI_PATH)\NBSMI.cif $(CIF2MAK_DEFAULTS) + +NB_SMI_OBJECTS = $(BUILD_NB_CHIPSET_DIR)\NBSMI.obj \ +$(BUILD_NB_BOARD_DIR)\GetSetupData.obj + +NBSMIBin : $(AMIDXELIB) $(AMICSPLib) + @set INCLUDE=%%INCLUDE%% + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\NBSMI.mak all\ + "CFLAGS=$(CFLAGS) /I$(NB_BOARD_DIR) /I$(SB_BOARD_DIR) /I$(SB_CHIPSET_DIR)"\ + OBJECTS="$(NB_SMI_OBJECTS)" \ + GUID=D933DEDE-0260-4e76-A7D9-2F9F2440E5A5\ + ENTRY_POINT=InitializeNBSmm\ + TYPE=BS_DRIVER \ + COMPRESS=1 + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/NB/NBSMI.SDL b/Chipset/NB/NBSMI.SDL new file mode 100644 index 0000000..81e5e69 --- /dev/null +++ b/Chipset/NB/NBSMI.SDL @@ -0,0 +1,114 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB SMI/NBSMI.SDL 1 2/08/12 4:35a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 4:35a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB SMI/NBSMI.SDL $ +# +# 1 2/08/12 4:35a Yurenlai +# Intel Haswell/NB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "NBSMI_SUPPORT" + Value = "1" + Help = "Main switch to enable NB SMI support in Project" + TokenType = Boolean + TargetMAK = Yes + Master = Yes +End + +TOKEN + Name = "NB_ERROR_LOG_SUPPORT" + Value = "1" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Token = "ErrorLogging_SUPPORT" "=" "1" + Token = "IpmiLib_SUPPORT" "=" "1" + Token = "SmmRuntime_SUPPORT" "=" "1" +End + +TOKEN + Name = "NB_PCIE_ERROR_LOG_SUPPORT" + Value = "1" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Token = "NB_ERROR_LOG_SUPPORT" "=" "1" +End + +TOKEN + Name = "NB_ECC_ERROR_LOG_SUPPORT" + Value = "1" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Token = "NB_ERROR_LOG_SUPPORT" "=" "1" +End + +TOKEN + Name = "ECC_MULTI_BIT_TYPE_HANG" + Value = "0" + TokenType = Boolean + TargetH = Yes + Token = "NB_ECC_ERROR_LOG_SUPPORT" "=" "1" +End + +TOKEN + Name = "NB_SWSMI_IGFX_GET_SETUP" + Value = "0xb0" + Help = "Value to write into SMI command register to generate software SMI for NB" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Range = "0xB0 - 0xB6" +End + +PATH + Name = "NB_SMI_PATH" + Path = "Chipset\NB" +End + +MODULE + Help = "Includes NBSMI.mak to Project" + File = "NBSMI.mak" +End + +ELINK + Name = "$(BUILD_DIR)\NBSMI.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Chipset/NB/NBSmm.c b/Chipset/NB/NBSmm.c new file mode 100644 index 0000000..64499c9 --- /dev/null +++ b/Chipset/NB/NBSmm.c @@ -0,0 +1,625 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBSmm.c 1 2/08/12 4:34a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 4:34a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBSmm.c $ +// +// 1 2/08/12 4:34a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: NBSMM.C +// +// Description: This file contains code for SMM access and control (both the +// protocol defined by Framework +// +//<AMI_FHDR_END> +//************************************************************************* + +//---------------------------------------------------------------------------- +// Include(s) +//---------------------------------------------------------------------------- + +#include <Efi.h> +#include <token.h> +#include <HOB.h> +#include <DXE.h> +#include <AmiLib.h> +#include <AmiDxeLib.h> +#include <AmiCspLib.h> + +// Used Protocols +#include <Protocol\PciRootBridgeIo.h> +// Produced Protocols +#include <Protocol\SmmAccess.h> +#if PI_SPECIFICATION_VERSION >= 0x0001000A +#include <Protocol\SmmAccess2.h> +#endif + +//---------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//---------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//---------------------------------------------------------------------------- +// Variable and External Declaration(s) +//---------------------------------------------------------------------------- +// Variable Declaration(s) + +EFI_HOB_HANDOFF_INFO_TABLE *pHIT; + +static EFI_SMRAM_DESCRIPTOR gSmramMap[] = { + { + 0xA0000, // PhysicalStart + 0xA0000, // CpuStart + 128*1024, // PhysicalSize + EFI_ALLOCATED | EFI_SMRAM_CLOSED // RegionState + }, + { + 0, // PhysicalStart + 0, // CputStart + TSEG_SIZE, // PhysicalSize + EFI_ALLOCATED | EFI_SMRAM_CLOSED // RegionState + } +}; + +#define SMRAM_MAP_NUM_DESCRIPTORS (sizeof(gSmramMap)/sizeof(EFI_SMRAM_DESCRIPTOR)) +static UINTN SmramMapNumDescriptors = SMRAM_MAP_NUM_DESCRIPTORS; + +// GUID Definition(s) + +EFI_GUID gGuidHobList = HOB_LIST_GUID; +EFI_GUID gEfiSmmAccessProtocolGuid = EFI_SMM_ACCESS_PROTOCOL_GUID; + +// Protocol Definition(s) + +// External Declaration(s) + +//#### extern EFI_GUID gEfiBootScriptSaveGuid; +//#### extern EFI_GUID gEfiPciRootBridgeIoProtocolGuid; +//#### extern EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *gPciRootBridgeIo; +//#### extern EFI_BOOT_SCRIPT_SAVE_PROTOCOL *gBootScriptSave; + +// Function Definition(s) + +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBSMM_EnableSMMAddress +// +// Description: This function programs the NB chipset registers to enable +// appropriate SMRAM area. +// +// Input: None +// +// Output: EFI_SUCCESS Always +// +// Notes: CHIPSET AND/OR BOARD PORTING NEEDED +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBSMM_EnableSMMAddress (VOID) +{ + UINT64 qTsegAddress; + + // Currently TSEG address is assumed to be TOM - TSEG_SIZE + // THIS CODE SHOULD BE CHANGED TO GET THE TSEG LOCATION FROM CPU INFO HOB + qTsegAddress = pHIT->EfiMemoryTop; +#if NB_DEBUG_MESSAGE + TRACE((TRACE_ALWAYS, "TSEG Address %x.\n", qTsegAddress)); +#endif + gSmramMap[1].PhysicalStart = gSmramMap[1].CpuStart = qTsegAddress; + gSmramMap[1].PhysicalSize = TSEG_SIZE; + +// Porting Required - Enable SMM area in Chipset (both TSEG & 0xA0000) +// TSEG & 0xA0000 had been enabled at PEI phase. +// Porting ENDS + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBSMM_OpenSmram +// +// Description: This function programs the NB chipset registers to open +// the SMRAM area. +// +// Input: *This - Pointer to the SMM access protocol +// DescriptorIndex - Index of SMM Descriptor +// +// Output: EFI_STATUS +// EFI_SUCCESS Opened the SMM area. +// EFI_INVALID_PARAMETER Descriptor doesn't exist. +// EFI_ACCESS_DENIED SMM area locked +// +// Modified: gSmramMap[DescriptorIndex].RegionState to EFI_SMRAM_OPEN. +// +// Notes: CHIPSET AND/OR BOARD PORTING NEEDED +// Here is the control flow of this function: +// 1. If invalid Descriptor return EFI_INVALID_PARAMETER. +// 2. Read NB SMM register. +// 3. If locked, return EFI_ACCESS_DENIED +// 4. Set Value for register to Open SMM area (0a0000-bffff) +// 5. Write Register. +// 6. Set OpenState to TRUE. +// 7. Set the RegionState to EFI_SMRAM_OPEN. +// 8. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBSMM_OpenSmram ( + IN EFI_SMM_ACCESS_PROTOCOL *This, + IN UINTN DescriptorIndex ) +{ + //-UINT8 SmramControl; + + if (DescriptorIndex >= SmramMapNumDescriptors) + return EFI_INVALID_PARAMETER; + +// Porting Required - Open SMM area in Chipset (both TSEG & 0xA0000) + if (gSmramMap[0].RegionState == EFI_SMRAM_LOCKED ) + /* Write code to check SMM lock */ + return EFI_ACCESS_DENIED; //If device is locked, return error. + +/* + SmramControl = MmPci8(MC_BUS, MC_DEV, MC_FUN, SMRAMC); + + if ((SmramControl & SMRAMC_D_LCK_MASK) != 0) + { + gSmramMap[0].RegionState = EFI_SMRAM_LOCKED; + gSmramMap[1].RegionState = EFI_SMRAM_LOCKED; + return EFI_DEVICE_ERROR; + } + + SmramControl |= SMRAMC_D_OPEN_MASK; + SmramControl &= ~(SMRAMC_D_CLS_MASK); + + MmPci8(MC_BUS, MC_DEV, MC_FUN, SMRAMC) = SmramControl; +*/ +// Porting ENDS + + // Update appropriate flags + This->OpenState = TRUE; + gSmramMap[0].RegionState = EFI_SMRAM_OPEN; + gSmramMap[1].RegionState = EFI_SMRAM_OPEN; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBSMM_CloseSmram +// +// Description: This function programs the NB chipset registers to close +// the SMRAM area. +// +// Input: *This Pointer to the SMM access protocol +// DescriptorIndex Index of SMM Descriptor +// +// Output: EFI_STATUS +// EFI_SUCCESS Closed the SMM area. +// EFI_INVALID_PARAMETER Descriptor doesn't exist. +// EFI_ACCESS_DENIED SMM area locked +// +// Modified: gSmramMap[DescriptorIndex].RegionState to EFI_SMRAM_CLOSED & +// EFI_ALLOCATED +// +// Notes: CHIPSET AND/OR BOARD PORTING NEEDED +// Here is the control flow of this function: +// 1. If invalid Descriptor return EFI_INVALID_PARAMETER. +// 2. Read NB SMM register. +// 3. If locked, return EFI_ACCESS_DENIED +// 4. Set Value for register to close SMM area (0a0000-bffff) +// 5. Write Register. +// 6. Set OpenState to FALSE. +// 7. Set the RegionState to EFI_SMRAM_CLOSED & EFI_ALLOCATED +// 8. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBSMM_CloseSmram ( + IN EFI_SMM_ACCESS_PROTOCOL *This, + IN UINTN DescriptorIndex ) +{ + //-UINT8 SmramControl; + + if (DescriptorIndex >= SmramMapNumDescriptors) + return EFI_INVALID_PARAMETER; + +// Porting Required - Close SMM area in Chipset (both TSEG & 0xA0000) + if (gSmramMap[0].RegionState == EFI_SMRAM_LOCKED ) + /* Write code to check SMM lock */ + return EFI_ACCESS_DENIED; //If device is locked, return error. + +/* + SmramControl = MmPci8(MC_BUS, MC_DEV, MC_FUN, SMRAMC); + + if ((SmramControl & SMRAMC_D_LCK_MASK) != 0) + { + gSmramMap[0].RegionState = EFI_SMRAM_LOCKED; + gSmramMap[1].RegionState = EFI_SMRAM_LOCKED; + return EFI_DEVICE_ERROR; + } + + SmramControl &= ~(SMRAMC_D_OPEN_MASK); + + MmPci8(MC_BUS, MC_DEV, MC_FUN, SMRAMC) = SmramControl; +*/ +// Porting ENDS + + // Update appropriate flags + This->OpenState = FALSE; + gSmramMap[0].RegionState = EFI_SMRAM_CLOSED | EFI_ALLOCATED; + gSmramMap[1].RegionState = EFI_SMRAM_CLOSED | EFI_ALLOCATED; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBSMM_LockSmram +// +// Description: This function programs the NB chipset registers to lock +// the SMRAM area from opening/closing. Only system level reset +// can unlock the SMRAM lock. +// +// Input: *This Pointer to the SMM access protocol +// DescriptorIndex Index of SMM Descriptor +// +// Output: EFI_STATUS +// EFI_SUCCESS Locked the SMM area. +// EFI_INVALID_PARAMETER Descriptor doesn't exist. +// EFI_DEVICE_ERROR SMM area is opened, need to be +// closed first before locking +// +// Modified: gSmramMap[DescriptorIndex].RegionState to EFI_SMRAM_LOCKED. +// +// Notes: CHIPSET AND/OR BOARD PORTING NEEDED +// Here is the control flow of this function: +// 1. If invalid Descriptor return EFI_INVALID_PARAMETER. +// 2. Read NB SMM register. +// 3. If opened, return EFI_ACCESS_DENIED +// 4. Set Value for register to lock SMM area (0a0000-bffff) +// 5. Write Register. +// 6. Set the RegionState to EFI_SMRAM_CLOSED & EFI_ALLOCATED +// 7. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBSMM_LockSmram ( + IN EFI_SMM_ACCESS_PROTOCOL *This, + IN UINTN DescriptorIndex ) +{ + //-UINT8 SmramControl; + + //Both regions must open and close at the same time. + if (DescriptorIndex >= SmramMapNumDescriptors) + return EFI_INVALID_PARAMETER; + +// Porting Required - Lock SMM area in Chipset (both TSEG & 0xA0000) + if (gSmramMap[0].RegionState == EFI_SMRAM_OPEN) + { + /* Write code to check SMM lock */ + return EFI_ACCESS_DENIED; //If SMM is opened, return error. + } + +/* + SmramControl = MmPci8(MC_BUS, MC_DEV, MC_FUN, SMRAMC); + + SmramControl &= ~(SMRAMC_D_OPEN_MASK); + SmramControl |= (SMRAMC_D_LCK_MASK); + + MmPci8(MC_BUS, MC_DEV, MC_FUN, SMRAMC) = SmramControl; +*/ +// Porting ENDS + + // Update appropriate flags + This->LockState = TRUE; + gSmramMap[0].RegionState = EFI_SMRAM_LOCKED; + gSmramMap[1].RegionState = EFI_SMRAM_LOCKED; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBSMM_GetCapabilities +// +// Description: This function returns the current SMRAM area map information +// such as number of regions and its start address and size +// +// Input: *This Pointer to the SMM access protocol +// *SmramMapSize Size of the SMRAM map buffer provided +// *SmramMap Buffer to copy the SMRAM map information +// +// Output: EFI_STATUS +// EFI_SUCCESS Smram Map copied into buffer +// EFI_BUFFER_TOO_SMALL Indicates that provided buffer is +// not enough +// *SmramMapSize Filled with required/updated size +// +// Notes: CHIPSET AND/OR BOARD PORTING NEEDED +// Here is the control flow of this function: +// 1.If Smram Map Size less than the actual map size, set +// the map size and return EFI_BUFFER_TOO_SMALL. +// 2.Copy the Smram Map descriptors into the supplied buffer. +// 3.Set the map size in *SmramMapSize, just in case is +// larger than the actual buffer. +// 4.Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBSMM_GetCapabilities ( + IN EFI_SMM_ACCESS_PROTOCOL *This, + IN OUT UINTN *SmramMapSize, + OUT EFI_SMRAM_DESCRIPTOR *SmramMap ) +{ + UINTN i; + + if (*SmramMapSize < sizeof(gSmramMap)) + { + // If input map size to small, + // report the correct map size and return error. + *SmramMapSize = sizeof(gSmramMap); + return EFI_BUFFER_TOO_SMALL; + } + + for(i=0; i < SmramMapNumDescriptors; ++i) + SmramMap[i] = gSmramMap[i]; + + *SmramMapSize = sizeof(gSmramMap); // Set the correct map size + + return EFI_SUCCESS; +} + +EFI_SMM_ACCESS_PROTOCOL mSmmAccess = { + NBSMM_OpenSmram, + NBSMM_CloseSmram, + NBSMM_LockSmram, + NBSMM_GetCapabilities, + FALSE, + FALSE +}; + +EFI_SMM_ACCESS_PROTOCOL *gSmmAccess = NULL; + +#if PI_SPECIFICATION_VERSION >= 0x0001000A +EFI_STATUS OpenSmram2(IN EFI_SMM_ACCESS2_PROTOCOL *This) +{ + EFI_STATUS Status; + UINTN i; + + if ((This->LockState != gSmmAccess->LockState) || + (This->OpenState != gSmmAccess->OpenState)) + { + This->LockState = gSmmAccess->LockState; + This->OpenState = gSmmAccess->OpenState; + } + +// Porting Required - Open SMM area in Chipset (both TSEG & 0xA0000) + if (gSmramMap[0].RegionState == EFI_SMRAM_LOCKED) + { + /* Write code to check SMM lock */ + + //If device is locked, return error. + return EFI_ACCESS_DENIED; + } + + for(i=0; i < SmramMapNumDescriptors; ++i) + { + Status = gSmmAccess->Open(gSmmAccess, i); + if (Status != EFI_SUCCESS) + return Status; + } +// Porting ENDS + + // Update appropriate flags + This->OpenState = TRUE; + + return EFI_SUCCESS; +} + +EFI_STATUS CloseSmram2(IN EFI_SMM_ACCESS2_PROTOCOL *This) +{ + EFI_STATUS Status; + UINTN i; + + if ((This->LockState != gSmmAccess->LockState) || + (This->OpenState != gSmmAccess->OpenState)) + { + This->LockState = gSmmAccess->LockState; + This->OpenState = gSmmAccess->OpenState; + } + +// Porting Required - Close SMM area in Chipset (both TSEG & 0xA0000) + if (gSmramMap[0].RegionState == EFI_SMRAM_LOCKED) + { + /* Write code to check SMM lock */ + + //If device is locked, return error. + return EFI_ACCESS_DENIED; + } + + for(i=0; i < SmramMapNumDescriptors; ++i) + { + Status = gSmmAccess->Close(gSmmAccess, i); + if (Status != EFI_SUCCESS) + return Status; + } +// Porting ENDS + + // Update appropriate flags + This->OpenState = FALSE; + + return EFI_SUCCESS; +} + +EFI_STATUS LockSmram2(IN EFI_SMM_ACCESS2_PROTOCOL *This) +{ + EFI_STATUS Status; + UINTN i; + + if ((This->LockState != gSmmAccess->LockState) || + (This->OpenState != gSmmAccess->OpenState)) + { + This->LockState = gSmmAccess->LockState; + This->OpenState = gSmmAccess->OpenState; + } + +// Porting Required - Lock SMM area in Chipset (both TSEG & 0xA0000) + if (gSmramMap[0].RegionState == EFI_SMRAM_OPEN) + { + /* Write code to check SMM lock */ + return EFI_ACCESS_DENIED; //If SMM is opened, return error. + } + + for(i=0; i < SmramMapNumDescriptors; ++i) + { + Status = gSmmAccess->Lock(gSmmAccess, i); + if (Status != EFI_SUCCESS) + return Status; + } +// Porting ENDS + + // Update appropriate flags + This->LockState = TRUE; + + return EFI_SUCCESS; +} + +EFI_STATUS GetCapabilities2( + IN CONST EFI_SMM_ACCESS2_PROTOCOL *This, + IN OUT UINTN *SmramMapSize, + IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap +) +{ + EFI_STATUS Status; + + Status = gSmmAccess->GetCapabilities(gSmmAccess, SmramMapSize, SmramMap); + + return Status; +} + +EFI_SMM_ACCESS2_PROTOCOL gSmmAccess2 = { + OpenSmram2, + CloseSmram2, + LockSmram2, + GetCapabilities2, + FALSE, + FALSE +}; +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBSMM_Init +// +// Description: This function is invoked from NB DXE to initialize SMM +// related stuff in NorthBridge and install appropriate +// SMM protocols such as SMM Access & SMM Control +// +// Input: ImageHandle Image handle +// SystemTable Pointer to the system table +// +// Output: Return Status based on errors that occurred while waiting for +// time to expire. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NbSmmInit ( + IN EFI_EVENT Event, + IN VOID *Context) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINTN SmramMapSize = sizeof(gSmramMap); + + PROGRESS_CODE (DXE_NB_SMM_INIT); + + Status = pBS->LocateProtocol(&gEfiSmmAccessProtocolGuid, NULL, &gSmmAccess); + if (EFI_ERROR(Status)) + { + pHIT = GetEfiConfigurationTable(pST, &gGuidHobList); + + // Enable SMM address range by programming appropriate chipset registers + NBSMM_EnableSMMAddress (); + + Status = pBS->InstallMultipleProtocolInterfaces(&TheImageHandle, + &gEfiSmmAccessProtocolGuid, + &mSmmAccess, +#if PI_SPECIFICATION_VERSION >= 0x0001000A + &gEfiSmmAccess2ProtocolGuid, + &gSmmAccess2, +#endif + NULL, + NULL ); + ASSERT_EFI_ERROR(Status); + } + else + { + Status = gSmmAccess->GetCapabilities(gSmmAccess, &SmramMapSize, gSmramMap); + ASSERT_EFI_ERROR(Status); + + SmramMapNumDescriptors = SmramMapSize / sizeof(EFI_SMRAM_DESCRIPTOR); + +#if PI_SPECIFICATION_VERSION >= 0x0001000A + Status = pBS->InstallMultipleProtocolInterfaces(&TheImageHandle, + &gEfiSmmAccess2ProtocolGuid, + &gSmmAccess2, + NULL, + NULL ); + ASSERT_EFI_ERROR(Status); +#endif + } + + return Status; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/NbPciCSP.c b/Chipset/NB/NbPciCSP.c new file mode 100644 index 0000000..396e0df --- /dev/null +++ b/Chipset/NB/NbPciCSP.c @@ -0,0 +1,1165 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NbPciCSP.c 2 5/13/14 10:41p Dennisliu $ +// +// $Revision: 2 $ +// +// $Date: 5/13/14 10:41p $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NbPciCSP.c $ +// +// 2 5/13/14 10:41p Dennisliu +// [TAG] EIP167027 +// [Category] Improvement +// [Description] [SharkBay Aptio4]Variable's attribute needs to be +// reviewed by SA component driver +// [Files] NBDXEBoard.c; IntelSaGopSetup.c; IntelSaGopPolicy.c; +// NBDxe.c; NbPciCSP.c; PciHostBridge.c; +// +// 1 2/08/12 4:34a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: NbPciCSP.c +// +// Description: Chipset Porting Hooks for PCI Host Bridge Driver. +// +//<AMI_FHDR_END> +//************************************************************************* + +#include <Token.h> +#if AMI_ROOT_BRIDGE_SUPPORT == 1 +/****** DO NOT WRITE ABOVE THIS LINE *******/ + +//---------------------------------------------------------------------------- +// Include(s) +//---------------------------------------------------------------------------- + +#include "PciHostBridge.h" +#include <Acpi11.h> +#include <Acpi20.h> +#include <Protocol\AcpiTable.h> +#include <AmiCspLib.h> + +//---------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//---------------------------------------------------------------------------- +// Constant Definition(s) + +#if ACPI_SUPPORT + #if defined(PI_SPECIFICATION_VERSION) && (PI_SPECIFICATION_VERSION >= 0x00010014) + #include <Protocol\AcpiSystemDescriptionTable.h> + #else + #include <Protocol\AcpiSupport.h> + #endif +#endif + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//---------------------------------------------------------------------------- +// Variable and External Declaration(s) +//---------------------------------------------------------------------------- +// GUID Definition(s) + +EFI_GUID gEfiGlobalVariableGuid = EFI_GLOBAL_VARIABLE; + +// Variable Declaration(s) + +EFI_EVENT mAcpiEvent; +VOID *mAcpiReg; +UINTN mMcfgTblHandle = 0; +CHAR16 gMemoryCeilingVariable[] = L"MemCeil."; + +#if (CORE_VERSION <= 4635) +//---------------------------------------------------------------------------- +// For HOST AND ROOT BRIDGE Architectural information +// see chapter 12.1.1 PCI Root Bridge I/O Overview of EFI 1.1 spec +//---------------------------------------------------------------------------- +//This table will provide information on how many Root Bridges +//particular Host Bridge will produce. +//The table has NB_NUMBER_OF_HOST_BRG entries. +//(Token NB_NUMBER_OF_HOST_BRG is defined in NB.sdl) +// +//For desktop chipset it will be ONE ROOT UNDER ONE HOST. +// +//If system has more than ONE Host Add more Lines +//----------------------------------------------------------------------------------------------- + +UINTN gRbCountTbl[NB_NUMBER_OF_HOST_BRG]={ + 1, //Number of root bridges produced by Host #0 + //Number of root bridges produced by Host #1 + //Number of root bridges produced by Host #2 + //Number of root bridges produced by Host #3 +}; + +//----------------------------------------------------------------------------------------------- +// This is the table to provide each host allocation attributes +// The table has NB_NUMBER_OF_HOST_BRG entries. +// (Token NB_NUMBER_OF_HOST_BRG is defined in NB.sdl) +// Accepted values are: +// EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM +// EFI_PCI_HOST_BRIDGE_MEM64_DECODE +// These values can be ORed. +// The values are defined and explained in +// PCI Host Bridge Resource Allocation Protocol Specification V 0.9 +//----------------------------------------------------------------------------------------------- + +UINT64 gHbAllocAttribTbl[NB_NUMBER_OF_HOST_BRG]={ + 0, //Allocation Attributes of Host #0 + //Allocation Attributes of Host #1 + //Allocation Attributes of Host #2 + //Allocation Attributes of Host #3 + // And so on +}; + +//----------------------------------------------------------------------------------------------- +// This table will provide PCI Buses Decoding Information +// in form of ACPI QWORD resource descriptor. +// The only valid fields are: +// ResourceType, _MIN, _LEN. +// Maximum Bus may be calculated as: _MAX=_MIN+_LEN -1 +// +// If system has more then one root bridge, add more lines +// +// Desktop chipset is simple chipset with only one root bridge +// which decodes all bus ranges from 0 to 0xFF +// +// See definition of QWORD ACPI Resource Descriptor in ACPI 2.0 Spec +// and "Address Space Resource Descriptor Internal definitions" in AcpiRes.h +// Number of table entries depends on values ported in gRbCountTbl +//----------------------------------------------------------------------------------------------- + +// Name, Len, Resource Type, Flags ,_GRA, _MIN, _MAX, _TRA, _LEN +ASLR_QWORD_ASD gRbBusesTbl[] = { +// for Root 0 at Host 0 + {0x8a, 0x2b,ASLRV_SPC_TYPE_BUS, 0, 0, 0x1, 0x00, 0xff, 0, 0x100} +// for Root 1 at Host 0 if any + +// for Root 0 at Host 1 if any +}; + +//----------------------------------------------------------------------------------------------- +// This is the table for the Capabilities Supported by ROOT BRIDGE +// See EFI 1.1 spec for meaning of the Capabilities bits +// +// if system has more than one root bridge add more lines +// Number of table entries depends on values ported in gRbCountTbl +//----------------------------------------------------------------------------------------------- + +UINT64 gRbSupportsTbl[] = { +//for Root 0 at Host 0 + (EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO| \ + EFI_PCI_ATTRIBUTE_ISA_IO | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | \ + EFI_PCI_ATTRIBUTE_VGA_MEMORY | EFI_PCI_ATTRIBUTE_VGA_IO | \ + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO), +//for Root 1 at Host 0 if any + +//for Root 0 at Host 1 if any + +// and so on... +}; +#endif + +// Protocol Definition(s) + +// External Declaration(s) + +// Function Definition(s) + +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbCspGetPciSegment +// +// Description: This procedure returns PCI segment number for chipsets which +// capable of decoding multiple PCI segments. +// +// Input: HostBridgeNumber - Host Bridge Number (0 Based) +// RootBridgeNumber - Root Bridge Number (0 Based) +// +// Output: UINTN - PCI Segment Number (0 Based) +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINTN HbCspGetPciSegment ( + IN UINTN HostBridgeNumber, + IN UINTN RootBridgeNumber ) +{ + + // Usually even server chipsets decodes only one PCI segment + // but if chipsets has more than one SEGMENT we have to specify + // which HOST/ROOT(s) pare will have SEG=0; SEG=1 and so on... + + return 0; // this is for Single Host chipset + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbNotifyCspBeforeEnumeration +// +// Description: This procedure will be invoked in PCI Host Bridge Protocol +// when NotifyPhase function is called with phase +// EfiPciHostBridgeBeginEnumeration. +// +// Input: ResAllocProtocol - Pointer to Host Bridge Resource +// Allocation Protocol. +// RbIoProtocolBuffer - Pointer to Root Bridge I/O Protocol. +// RbCount - Root Bridge counter. +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbNotifyCspBeforeEnumeration ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + IN UINTN RbCount ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbNotifyCspBeginBusAllocation +// +// Description: This procedure will be invoked in PCI Host Bridge Protocol +// when NotifyPhase function is called with phase +// EfiPciHostBridgeBeginBusAllocation. +// +// Input: ResAllocProtocol - Pointer to Host Bridge Resource +// Allocation Protocol. +// RbIoProtocolBuffer - Pointer to Root Bridge I/O Protocol. +// RbCount - Root Bridge counter. +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbNotifyCspBeginBusAllocation ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + IN UINTN RbCount ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbNotifyCspEndBusAllocation +// +// Description: This procedure will be invoked in PCI Host Bridge Protocol +// when NotifyPhase function is called with phase +// EfiPciHostBridgeEndBusAllocation +// +// Input: ResAllocProtocol - Pointer to Host Bridge Resource +// Allocation Protocol. +// RbIoProtocolBuffer - Pointer to Root Bridge I/O Protocol. +// RbCount - Root Bridge counter. +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbNotifyCspEndBusAllocation ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + IN UINTN RbCount ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbNotifyCspBeginResourceAllocation +// +// Description: This procedure will be invoked in PCI Host Bridge Protocol +// when NotifyPhase function is called with phase +// EfiPciHostBridgeBeginResourceAllocation. +// +// Input: ResAllocProtocol - Pointer to Host Bridge Resource +// Allocation Protocol. +// RbIoProtocolBuffer - Pointer to Root Bridge I/O Protocol. +// RbCount - Root Bridge counter. +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbNotifyCspBeginResourceAllocation ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + IN UINTN RbCount ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbNotifyCspAllocateResources +// +// Description: This procedure will be invoked in PCI Host Bridge Protocol +// when NotifyPhase function is called with phase +// EfiPciHostBridgeAllocateResources. +// +// Input: ResAllocProtocol - Pointer to Host Bridge Resource +// Allocation Protocol. +// RbIoProtocolBuffer - Pointer to Root Bridge I/O Protocol. +// RbCount - Root Bridge counter. +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbNotifyCspAllocateResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + IN UINTN RbCount ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbNotifyCspSetResources +// +// Description: This procedure will be invoked in PCI Host Bridge Protocol +// when NotifyPhase function is called with phase +// EfiPciHostBridgeSetResources. +// +// Input: ResAllocProtocol - Pointer to Host Bridge Resource +// Allocation Protocol. +// RbIoProtocolBuffer - Pointer to Root Bridge I/O Protocol. +// RbCount - Root Bridge counter. +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbNotifyCspSetResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + IN UINTN RbCount ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbNotifyCspEndResourceAllocation +// +// Description: This procedure will be invoked in PCI Host Bridge Protocol +// when NotifyPhase function is called with phase +// EfiPciHostBridgeEndResourceAllocation +// +// Input: ResAllocProtocol - Pointer to Host Bridge Resource +// Allocation Protocol. +// RbIoProtocolBuffer - Pointer to Root Bridge I/O Protocol. +// RbCount - Root Bridge counter. +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbNotifyCspEndResourceAllocation ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + IN UINTN RbCount ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbCspStartBusEnumeration +// +// Description: This procedure will be invoked in PCI Host Bridge Protocol +// StartBusEnumeration function, it must prepare initial Bus +// ACPI Resource +// +// Input: HostBrgData - Pointer to Host Bridge private structure data. +// RootBrgData - Pointer to Root Bridge private structure data. +// RootBrgIndex - Root Bridge index (0 Based). +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbCspStartBusEnumeration ( + IN PCI_HOST_BRG_DATA *HostBrgData, + IN PCI_ROOT_BRG_DATA *RootBrgData, + IN UINTN RootBrgIndex ) +{ + EFI_STATUS Status = EFI_SUCCESS; +#if (CORE_COMBINED_VERSION <= 0x4027B) // 4.6.3.5 + + ASLR_QWORD_ASD *br; // Bus Resource Descriptor + + br = Malloc(sizeof(ASLR_QWORD_ASD)); + ASSERT(br); + if(!br) return EFI_OUT_OF_RESOURCES; + + // Fill out Bus Resource Requirements + MemCpy(br, &gRbBusesTbl[RootBrgIndex], sizeof(ASLR_QWORD_ASD)); + Status = AppendItemLst((T_ITEM_LIST*)&RootBrgData->ResInitCnt, br); + ASSERT_EFI_ERROR(Status); +#endif + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbCspSetBusNnumbers +// +// Description: This procedure will be invoked in PCI Host Bridge Protocol +// SubmitBusNumbers function. +// +// Input: HostBrgData - Pointer to Host Bridge private structure data. +// RootBrgData - Pointer to Root Bridge private structure data. +// RootBrgIndex - Root Bridge index (0 Based). +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbCspSetBusNnumbers ( + IN PCI_HOST_BRG_DATA *HostBrgData, + IN PCI_ROOT_BRG_DATA *RootBrgData, + IN UINTN RootBrgIndex ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbCspSubmitResources +// +// Description: This procedure will be invoked in PCI Host Bridge Protocol +// SubmitResources function. +// +// Input: HostBrgData - Pointer to Host Bridge private structure data. +// RootBrgData - Pointer to Root Bridge private structure data. +// RootBrgIndex - Root Bridge index (0 Based). +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbCspSubmitResources ( + IN PCI_HOST_BRG_DATA *HostBrgData, + IN PCI_ROOT_BRG_DATA *RootBrgData, + IN UINTN RootBrgIndex ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbCspAdjustMemoryMmioOverlap +// +// Description: This procedure will be invoked during PCI bus enumeration, +// it determines the PCI memory base address below 4GB whether +// it is overlapping the main memory, if it is overlapped, then +// updates MemoryCeiling variable and reboot. +// +// Input: HostBrgData - Pointer to Host Bridge private structure data. +// RootBrgData - Pointer to Root Bridge private structure data. +// RootBrgIndex - Root Bridge index (0 Based). +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbCspAdjustMemoryMmioOverlap ( + IN PCI_HOST_BRG_DATA *HostBrgData, + IN PCI_ROOT_BRG_DATA *RootBrgData, + IN UINTN RootBrgIndex ) +{ + EFI_STATUS Status; + + EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap; + UINTN NumberOfDescriptors; + ASLR_QWORD_ASD *Res; + UINTN i; + EFI_PHYSICAL_ADDRESS Highest4GMem = 0; + EFI_PHYSICAL_ADDRESS LowestMMIO = 0xffffffff; + EFI_PHYSICAL_ADDRESS LowestAllocMMIO = 0xffffffff; + UINTN MemoryCeiling = 0; // Init to 0 + UINTN NewMemoryCeiling = 0xffffffff; + UINTN DataSize = sizeof(UINT32); + UINT32 Attributes; // [ EIP167027 ] +#if (CORE_VERSION >= 4600) + DXE_SERVICES *DxeSvc; + +//------------------------------------ + Status = LibGetDxeSvcTbl( &DxeSvc ); + ASSERT_EFI_ERROR(Status) + if(EFI_ERROR(Status)) return Status; +#else + ASSERT(gDxeSvcTbl); +#endif + return EFI_SUCCESS; + //pRS->GetVariable ( gMemoryCeilingVariable, \ // [ EIP167027 ] + // &gEfiGlobalVariableGuid, \ + // NULL, \ + // &DataSize, \ + // &MemoryCeiling ); + pRS->GetVariable ( gMemoryCeilingVariable, \ + &gEfiGlobalVariableGuid, \ + &Attributes, \ + &DataSize, \ + &MemoryCeiling ); + if (EFI_ERROR(Status)) + Attributes = EFI_VARIABLE_NON_VOLATILE + EFI_VARIABLE_BOOTSERVICE_ACCESS; + + // Memory sizing uses memory ceiling to set top of memory. + + +#if (CORE_VERSION >= 4600) + Status = DxeSvc->GetMemorySpaceMap( &NumberOfDescriptors, \ + &MemorySpaceMap ); +#else + Status = gDxeSvcTbl->GetMemorySpaceMap( &NumberOfDescriptors, \ + &MemorySpaceMap ); +#endif + ASSERT_EFI_ERROR(Status) + + // Find the lowest MMIO and lowest allocated MMIO in GCD. + for (i = 0; i < NumberOfDescriptors; ++i) { + EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descr = &MemorySpaceMap[i]; + EFI_PHYSICAL_ADDRESS Base = Descr->BaseAddress; + + // Find highest system below 4GB memory. + // Treat any non MMIO as system memory. Not all system memory is + // reported as system memory, such as SMM. + + if (Descr->GcdMemoryType != EfiGcdMemoryTypeMemoryMappedIo && \ + Base < LowestMMIO) { + EFI_PHYSICAL_ADDRESS EndMem = Base + Descr->Length - 1; + if (EndMem > Highest4GMem && EndMem <= 0xffffffff) + Highest4GMem = EndMem; + + // Find Lowest mmio above system memory. + } else if (Descr->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) { + if (Base >= 0x100000) { + if (Base < LowestMMIO) LowestMMIO = Base; + + // If ImageHandle, then MMIO is allocated. + if ((Base < LowestAllocMMIO) && Descr->ImageHandle) + LowestAllocMMIO = Base; + } + } + } + + pBS->FreePool(MemorySpaceMap); + + if (Highest4GMem + 1 != LowestMMIO) { + TRACE( (-1, "PciHostCSHooks: ") ); + TRACE( (-1, "System Memory and MMIO are not consequitive.\n") ); + TRACE( (-1, "Top of Below 4G Memory: %lX", Highest4GMem) ); + TRACE( (-1, "Bottom of MMIO: %X\n", LowestMMIO) ); + } + + + // Find any MMIO that could not be allocated due to small of MMIO region. + for (i = 0; i < RootBrgData->ResCount; ++i) { + EFI_PHYSICAL_ADDRESS NeededBottomMmio; + + Res = RootBrgData->RbRes[i]; + + // Any unallocated MMIO will have Res->_MIN set to zero for the MMIO + // type. + if (Res->Type != ASLRV_SPC_TYPE_MEM || Res->_GRA != 32 || Res->_MIN) + continue; + + // Determine new memory ceiling variable needed to allocate this + // memory. + NeededBottomMmio = LowestAllocMMIO - Res->_LEN; + + // Round down. If resource is not allocated, _MAX contains + // granularity. + NeededBottomMmio &= ~Res->_MAX; + if (NeededBottomMmio < NewMemoryCeiling) + NewMemoryCeiling = (UINTN) NeededBottomMmio; + } + + // Check if a NewMemory Ceiling is needed. + if (NewMemoryCeiling < 0xffffffff) { + if (!MemoryCeiling || MemoryCeiling != NewMemoryCeiling ) { + + // Set memory ceiling variable. + //pRS->SetVariable( gMemoryCeilingVariable, \ // [ EIP167027 ] + // &gEfiGlobalVariableGuid, \ + // EFI_VARIABLE_NON_VOLATILE + \ + // EFI_VARIABLE_BOOTSERVICE_ACCESS + \ + // EFI_VARIABLE_RUNTIME_ACCESS, + // sizeof (UINT32), \ + // &NewMemoryCeiling ); + pRS->SetVariable( gMemoryCeilingVariable, \ + &gEfiGlobalVariableGuid, \ + Attributes, + sizeof (UINT32), \ + &NewMemoryCeiling ); + + TRACE((-1, "Adjusting maximum top of RAM.\n Resetting System.\n")); + + // Reset only needed of type of physical memory overlaps with MMIO. + +#if (NV_SIMULATION != 1) + // Don't reset system in case of NVRAM simulation + pRS->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL); +#endif + // Control should not come here if NV_SIMULATION = 0. + } + return EFI_SUCCESS; + } + + // Check to see if Ceiling needs to be increased. If too low, + // then part of the memory be not be usuable. + if (MemoryCeiling != LowestAllocMMIO) { + + // Set memory ceiling variable. + //pRS->SetVariable( gMemoryCeilingVariable, \ // [ EIP167027 ] + // &gEfiGlobalVariableGuid, \ + // EFI_VARIABLE_NON_VOLATILE + \ + // EFI_VARIABLE_BOOTSERVICE_ACCESS + \ + // EFI_VARIABLE_RUNTIME_ACCESS, + // sizeof (UINT32), \ + // &LowestAllocMMIO ); + pRS->SetVariable( gMemoryCeilingVariable, \ + &gEfiGlobalVariableGuid, \ + Attributes, + sizeof (UINT32), \ + &LowestAllocMMIO ); + + TRACE((-1, "Adjusting maximum top of RAM.\n Resetting System.\n")); + +#if (NV_SIMULATION != 1) + // Don't reset system in case of NVRAM simulation + pRS->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL); +#endif + // Control should not come here if NV_SIMULATION = 0. + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbCspPreprocessController +// +// Description: This function is called for all the PCI controllers that +// the PCI bus driver finds. +// It can be used to Preprogram the controller. +// +// Input: HostBrgData - Pointer to Host Bridge private structure data. +// RootBrgData - Pointer to Root Bridge private structure data. +// RootBrgNumber - Root Bridge number (0 Based). +// PciAddress - Address of the controller on the PCI bus. +// Phase - The phase during enumeration +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbCspPreprocessController ( + IN PCI_HOST_BRG_DATA *HostBrgData, + IN PCI_ROOT_BRG_DATA *RootBrgData, + IN UINTN RootBrgNumber, + IN EFI_PCI_CONFIGURATION_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbCspMapRootBrgToHost +// +// Description: Chipset specific function that returns Host Bridge Number for +// the corresponded Root Bridge. +// +// Input: RootBrgXlatHdr - Pointer to Root Bridge XLAT table entry. +// AllocationAttr - Pointer to allocation attribute. +// RbSuportedAttr - Pointer to Root Bridge supported attribute. +// +// Output: UINTN - Number of the Host Bridge that root bridge +// identified by RootBrgXlatHdr belongs to. +// +// Note: THIS FUNCTION MUST BE PORTED FOR MULTI-HOST SYSTEMS +// HOST bridge handle supports: +// - ResourceAllocation Protocol (REQUIRED); +// - RootHotplugControllerInitialization +// Protocol (OPTIONAL); +// - PciPlatform Protocol (OPTIONAL). +// ROOT bridge handle supports: +// - PciRootBridgeIo Protocol (REQUIRED). +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINTN HbCspMapRootBrgToHost ( +#if (PCIBUS_VERSION > 020102) + IN PCI_BUS_XLAT_HDR *RootBrgXlatHdr, + IN UINT64 *AllocationAttr, + IN UINT64 *RbSuportedAttr ) +#else + IN PCI_BUS_XLAT_HDR *RootBrgXlatHdr ) +#endif +{ + // Usually even server chipsets use only one PCI HOST abstraction + // but if chipset has more than one HOST we have to specify + // which ROOT from PciBusXlat table belongs to which HOST. + + // Check if we need to update/change Allocation Attributes Passed to + // this function. + // Here we have ability to override Automaticaly generated Attributes + // based on SDL tokens COMBINE_MEM_PMEM and ABOVE_4G_PCI_DECODE + // bits currently defined for Allocation Attributes is: + // EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM + // EFI_PCI_HOST_BRIDGE_MEM64_DECODE + // Usually nothing needs to be done sor SINGLE HOST-SINGLE-ROOT systems + // NOTE: this function could be called more than one time for each HOST + // if you updating AllocationAttr only last data will be valid. + // PCI HostBridge Driver sets DEFAULT allocation attributes. + // Add code only if you need to overwrite it. + + // if i.e. second root does not support PF_MMIO + // if(RootBrgXlatHdr->BusBuild == 0x80 ) \ + // *AllocationAttr &= ~(EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM); + // else *RbSuportedAttr = ....; + + // Check that in VeB PCI Wizard this Root creates bus 0 + // This is usualy a compatibility bus + // Set the Compatibility bus Attributes it must decode Legacy resources + + // PCI HostBridge Driver sets DEFAULT Supported ROOT BRIDGE Attributes. + // Add code only if you need to overwrite it. + + // if (RootBrgXlatHdr->BusBuild == 0) *RbSuportedAttr= \ + // (EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | \ + // EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \ + // EFI_PCI_ATTRIBUTE_ISA_IO | \ + // EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | \ + // EFI_PCI_ATTRIBUTE_VGA_MEMORY | \ + // EFI_PCI_ATTRIBUTE_VGA_IO | \ + // EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO); + // else *RbSuportedAttr = 0; + + // Returning Host Number for Root Bridge corresponded to the Root + // ported as RootBrgXlatHdr->BusBuild from BusXLat Table + // for single SINGLEHOST-SINGLE-ROOT system this value always 0 + + // If your system MULTY-HOST/MULTY-ROOTs system + // you need to add code here to correctly map each ROOT referenced in + // VeB wizard to it's corresponded host + + return 0; +} + +#if (PCIBUS_VERSION > 020102) + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbCspAllocateResources +// +// Description: This function is invoked in PCI Host Bridge Driver when time +// to ask GCD for resources. You can overwrite a default +// algorithm used to allocate resources for the Root Bridge. +// +// Input: HostBrgData - Pointer to Host Bridge private structure data. +// RootBrgData - Pointer to Root Bridge private structure data. +// RootBrgIndex - Root Bridge index (0 Based). +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbCspAllocateResources ( + IN PCI_HOST_BRG_DATA *HostBrgData, + IN PCI_ROOT_BRG_DATA *RootBrgData, + IN UINTN RootBrgIndex ) +{ + EFI_STATUS Status = EFI_UNSUPPORTED; + + return Status; +} +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbCspBasicChipsetInit +// +// Description: This function will be invoked after Initialization of generic +// part of the Host and Root Bridges. +// All Handles for PCIHostBrg and PciRootBrg has been created +// and Protocol Intergaces installed. +// +// Input: HostBrgData - Pointer to Host Bridge private structure data. +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbCspBasicChipsetInit ( + IN PCI_HOST_BRG_DATA *HostBrg0 ) +{ + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RbCspIoPciMap +// +// Description: Chipset Specific function to Map Internal Device address +// residing ABOVE 4G to the BELOW 4G address space for DMA. +// MUST BE IMPLEMENTED if CHIPSET supports address space +// decoding ABOVE 4G. +// +// Input: *RbData - Root Bridge private structure data +// Operation - Operation to provide Mapping for +// HostAddress - HostAddress of the Device +// *NumberOfBytes - Number of Byte in Mapped Buffer. +// *DeviceAddress - Mapped Device Address. +// **Mapping - Mapping Info Structure this function must +// allocate and fill. +// +// Output: EFI_STATUS +// EFI_SUCCESS - Successful. +// EFI_UNSUPPORTED - The Map function is not supported. +// EFI_INVALID_PARAMETER - One of the parameters has an +// invalid value. +// +// Notes: Porting is required for chipsets that supports Decoding +// of the PCI Address Space ABOVE 4G. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS RbCspIoPciMap ( + IN PCI_ROOT_BRG_DATA *RbData, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, + IN EFI_PHYSICAL_ADDRESS HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping ) +{ + + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + *Mapping = NULL; + Status = EFI_UNSUPPORTED; + + // For Chipsets which DOES support decoding of the PCI resources ABOVE 4G. + // here must be something like that. + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RbCspIoPciUnmap +// +// Description: Chipset Specific function to Unmap previousely Mapped +// buffer for DMA. +// MUST BE IMPLEMENTED if CHIPSET supports address space +// decoding ABOVE 4G. +// +// Input: *RbData - Root Bridge private structure data +// *Mapping - Mapping Info Structure this function must free. +// +// Output: EFI_STATUS +// EFI_SUCCESS - Successful. +// EFI_UNSUPPORTED - The Unmap function is not supported. +// EFI_INVALID_PARAMETER - One of the parameters has an +// invalid value. +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS RbCspIoPciUnmap ( + IN PCI_ROOT_BRG_DATA *RbData, + OUT PCI_ROOT_BRIDGE_MAPPING *Mapping ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + + if (Mapping != NULL) return EFI_INVALID_PARAMETER; + // for all other conditions we would return EFI_UNSUPPORTED. + Status = EFI_UNSUPPORTED; + + // for Chipsets which DOES support decoding of the PCI resources ABOVE 4G. + // And provides corresponded mapping for the host address + // here must be something like that. + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RbCspIoPciAttributes +// +// Description: Chipset Specific function to do PCI RB Attributes releated +// programming. +// +// Input: RbData - Pointer to Root Bridge private structure. +// Attributes - The Root Bridge attributes to be programming. +// ResourceBase - Pointer to the resource base. (OPTIONAL) +// ResourceLength - Pointer to the resource Length. (OPTIONAL) +// +// Output: EFI_STATUS +// EFI_SUCCESS - Successful. +// EFI_INVALID_PARAMETER - One of the parameters has an +// invalid value. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS RbCspIoPciAttributes ( + IN PCI_ROOT_BRG_DATA *RbData, + IN UINT64 Attributes, + IN OUT UINT64 *ResourceBase OPTIONAL, + IN OUT UINT64 *ResourceLength OPTIONAL ) +{ + + + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RootBridgeIoPciRW +// +// Description: Read Pci Registers into buffer. +// Csp Function which actualy access PCI Config Space. +// Chipsets that capable of having PCI EXPRESS Ext Cfg Space +// transactions. +// Must Implement this access routine here. +// +// Input: *RbData - Root Bridge private structure. +// Width - PCI Width. +// Address - PCI Address. +// Count - Number of width reads/writes. +// *Buffer - Buffer where read/written. +// Write - Set if write. +// +// Output: EFI_STATUS +// EFI_SUCCESS - Successful read. +// EFI_INVALID_PARAMETER - One of the parameters has an +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS RootBridgeIoPciRW ( + IN PCI_ROOT_BRG_DATA *RbData, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer, + IN BOOLEAN Write ) +{ + BOOLEAN ValidCfg = TRUE; + UINT8 IncrementValue = 1 << (Width & 3); // 1st 2 bits currently define + // width. + // Other bits define type. + + UINTN PciAddress = PCIEX_BASE_ADDRESS + \ + (((EFI_PCI_CONFIGURATION_ADDRESS*) &Address)->Bus << 20 ) + \ + (((EFI_PCI_CONFIGURATION_ADDRESS*) &Address)->Device << 15 ) + \ + (((EFI_PCI_CONFIGURATION_ADDRESS*) &Address)->Function << 12 ); + + PciAddress += \ + ((EFI_PCI_CONFIGURATION_ADDRESS*) &Address)->ExtendedRegister ? \ + ((EFI_PCI_CONFIGURATION_ADDRESS*) &Address)->ExtendedRegister : \ + ((EFI_PCI_CONFIGURATION_ADDRESS*) &Address)->Register; + + // To read 64bit values, reduce Increment Value (by half) and + // double the count value (by twice) + if (IncrementValue > 4) { + IncrementValue >>= 1; + Count <<= 1; + } + + if (Width >= EfiPciWidthMaximum || IncrementValue > 4) + return EFI_INVALID_PARAMETER; + + while (Count--) { + if (PciAddress >= (PCIEX_BASE_ADDRESS + PCIEX_LENGTH)) \ + ValidCfg = FALSE; + if (Write) { + switch(IncrementValue) { + case 1: + if (ValidCfg) *(UINT8*)PciAddress = *(UINT8*)Buffer; + break; + case 2: + if (ValidCfg) *(UINT16*)PciAddress = *(UINT16*)Buffer; + break; + default: + if (ValidCfg) *(UINT32*)PciAddress = *(UINT32*)Buffer; + break; + } + } else { + switch(IncrementValue) { + case 1: + *(UINT8*)Buffer = (ValidCfg) ? *(UINT8*)PciAddress : -1; + break; + case 2: + *(UINT16*)Buffer = (ValidCfg) ? *(UINT16*)PciAddress : -1; + break; + default: + *(UINT32*)Buffer = (ValidCfg) ? *(UINT32*)PciAddress : -1; + break; + } + } + + if (Width <= EfiPciWidthFifoUint64) { + Buffer = ((UINT8 *)Buffer + IncrementValue); + // Buffer is increased for only EfiPciWidthUintxx and + // EfiPciWidthFifoUintxx + } + + // Only increment the PCI address if Width is not a FIFO. + if ((Width & 4) == 0) { + PciAddress += IncrementValue; + } + } + + return EFI_SUCCESS; +} + +/****** DO NOT WRITE BELOW THIS LINE *******/ +#endif //#if AMI_ROOT_BRIDGE_SUPPORT == 1 + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/ReleaseNotes.chm b/Chipset/NB/ReleaseNotes.chm Binary files differnew file mode 100644 index 0000000..b652c4c --- /dev/null +++ b/Chipset/NB/ReleaseNotes.chm diff --git a/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.c b/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.c new file mode 100644 index 0000000..3a5a8b4 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.c @@ -0,0 +1,263 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/LegacyRegion2/LegacyRegion2.c 1 4/05/12 3:08a Yurenlai $ +// +// $Date: 4/05/12 3:08a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: LegacyRegion2.c +// +// Description: Legacy Region 2 functions implementation +// +//<AMI_FHDR_END> +//************************************************************************* + +#include <efi.h> +#include <AmiDxeLib.h> +#include <AmiCspLib.h> +#include <Protocol\LegacyRegion.h> +#include <Protocol\LegacyRegion2.h> + +EFI_LEGACY_REGION_PROTOCOL *gLegacyRegionProtocol = NULL; + +//************************************************************************* +//<AMI_PHDR_START> +// +// Procedure: LegacyRegionDecode +// +// Description: Program chipset to allow decoding of 0xc0000 - 0xfffff. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This, +// IN UINT32 Start, +// IN UINT32 Length, +// OUT UINT32 *Granularity, +// IN BOOLEAN *On +// +// Output: +// Status of the operation +// +//<AMI_PHDR_END> +//************************************************************************* +EFI_STATUS LegacyRegionDecode( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity, + IN BOOLEAN *On +) +{ + return gLegacyRegionProtocol->Decode( gLegacyRegionProtocol, Start, Length, On); +} + +//************************************************************************* +//<AMI_PHDR_START> +// +// Procedure: LegacyRegionLock +// +// Description: To disallow writes to memory 0xc0000 - 0xfffff. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This, +// IN UINT32 Start, +// IN UINT32 Length, +// OUT UINT32 *Granularity OPTIONAL +// +// Output: +// Status of the operation +// +//<AMI_PHDR_END> +//************************************************************************* +EFI_STATUS LegacyRegionLock( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity OPTIONAL +) +{ + return gLegacyRegionProtocol->Lock( gLegacyRegionProtocol, Start, Length, Granularity); +} + +//************************************************************************* +//<AMI_PHDR_START> +// +// Procedure: LegacyRegionBootLock +// +// Description: To permanently disallow writes to memory 0xc0000 - 0xffff. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This, +// IN UINT32 Start, +// IN UINT32 Length, +// OUT UINT32 *Granularity OPTIONAL +// +// Output: +// Status of the operation +// +//<AMI_PHDR_END> +//************************************************************************* +EFI_STATUS LegacyRegionBootLock( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity OPTIONAL +) +{ + return gLegacyRegionProtocol->BootLock( gLegacyRegionProtocol, Start, Length, Granularity); +} + +//************************************************************************* +//<AMI_PHDR_START> +// +// Procedure: LegacyRegionUnlock +// +// Description: To allow read/write of memory 0xc0000-0xfffff. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This, +// IN UINT32 Start, +// IN UINT32 Length, +// OUT UINT32 *Granularity OPTIONAL +// +// Output: +// Status of the operation +// +//<AMI_PHDR_END> +//************************************************************************* +EFI_STATUS LegacyRegionUnlock( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity OPTIONAL +) +{ + return gLegacyRegionProtocol->UnLock(gLegacyRegionProtocol, Start, Length, Granularity); +} + +//************************************************************************* +//<AMI_PHDR_START> +// +// Procedure: GetLegacyRegionInfo +// +// Description: +// This function is used to discover the granularity of the attributes +// for the memory in the legacy region. Each attribute may have a different +// granularity and the granularity may not be the same for all memory ranges +// in the legacy region. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This +// -- Indicates the EFI_LEGACY_REGION_PROTOCOL instance. +// +// Output: +// EFI_UNSUPPORTED - This function is not supported +// EFI_SUCCESS - The following information structure is returned: +// OUT UINT32 *DescriptorCount +// -- The number of region descriptor entries returned in the Descriptor +// buffer. See EFI_LEGACY_REGION_DESCRIPTOR definition for reference. +// OUT EFI_LEGACY_REGION_DESCRIPTOR **Descriptor +// -- A pointer to a pointer used to return a buffer where the legacy +// region information is deposited. This buffer will contain a list +// of DescriptorCount number of region descriptors. This function will +// provide the memory for the buffer. +// +//<AMI_PHDR_END> +//************************************************************************* +EFI_STATUS GetLegacyRegionInfo( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + OUT UINT32 *DescriptorCount, + OUT EFI_LEGACY_REGION_DESCRIPTOR **Descriptor +) +{ + return EFI_UNSUPPORTED; // Note: to support this function there is a need + // to update NB template. +} + +EFI_LEGACY_REGION2_PROTOCOL gLegacyRegion2Protocol = +{ + LegacyRegionDecode, LegacyRegionLock, + LegacyRegionBootLock, LegacyRegionUnlock, + GetLegacyRegionInfo +}; + +//************************************************************************* +//<AMI_PHDR_START> +// +// Procedure: InitializeLegacyRegion2 +// +// Description: Install the legacy region 2 protocol. +// +// Input: +// IN EFI_HANDLE ImageHandle, +// IN EFI_SYSTEM_TABLE *SystemTable +// +// Output: +// Status of the operation +// +// Notes: +// Here is the control flow of this function: +// 1. Get root bridge io protocol. +// 2. Install legacy region protocol. +// +//<AMI_PHDR_END> +//************************************************************************* +EFI_STATUS InitializeLegacyRegion2( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + InitAmiLib(ImageHandle, SystemTable); + + Status = pBS->LocateProtocol( + &gEfiLegacyRegionProtocolGuid, + NULL, + &gLegacyRegionProtocol); + + if(!EFI_ERROR(Status)) { + + Status = pBS->InstallProtocolInterface ( + &ImageHandle, + &gEfiLegacyRegion2ProtocolGuid, + EFI_NATIVE_INTERFACE, + &gLegacyRegion2Protocol + ); + } + + return Status; + +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.cif b/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.cif new file mode 100644 index 0000000..429cfe6 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.cif @@ -0,0 +1,11 @@ +<component> + name = "LegacyRegion2" + category = ModulePart + LocalRoot = "Chipset\NB\SystemAgentWrap\LegacyRegion2\" + RefName = "LegacyRegion2" +[files] +"LegacyRegion2.sdl" +"LegacyRegion2.mak" +"LegacyRegion2.dxs" +"LegacyRegion2.c" +<endComponent> diff --git a/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.dxs b/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.dxs new file mode 100644 index 0000000..1e5b3e0 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.dxs @@ -0,0 +1,51 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/LegacyRegion2/LegacyRegion2.dxs 1 4/05/12 3:08a Yurenlai $ +// +// $Date: 4/05/12 3:08a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: LegacyRegion2.dxs +// +// Description: Legacy Region 2 dependency file +// +//<AMI_FHDR_END> +//************************************************************************* +#include <protocol\LegacyRegion.h> + +DEPENDENCY_START + EFI_LEGACY_REGION_PROTOCOL_GUID +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.mak b/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.mak new file mode 100644 index 0000000..da09a37 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.mak @@ -0,0 +1,44 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +all : LegacyRegion2 + +LegacyRegion2 : $(BUILD_DIR)\LegacyRegion2.mak LegacyRegion2Bin + +$(BUILD_DIR)\LegacyRegion2.mak : $(LEGACY_REGION2_DIR)\$(@B).cif $(LEGACY_REGION2_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(LEGACY_REGION2_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +LegacyRegion2Bin : $(AMIDXELIB) $(AMICSPLib) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\LegacyRegion2.mak all\ + GUID=FE6F8ACD-55A6-4c6b-B448-64E659DE94B3 \ + ENTRY_POINT=InitializeLegacyRegion2 \ + DEPEX1=$(LEGACY_REGION2_DIR)\LegacyRegion2.dxs\ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + TYPE=BS_DRIVER \ + COMPRESS=1\ + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2012, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.sdl b/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.sdl new file mode 100644 index 0000000..2f6de11 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.sdl @@ -0,0 +1,26 @@ +TOKEN + Name = "LegacyRegion2_SUPPORT" + Value = "1" + Help = "Main switch to enable LegacyRegion2 support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Token = "CSM_SUPPORT" "=" "1" +End + +PATH + Name = "LEGACY_REGION2_DIR" +End + +MODULE + Help = "Includes LegacyRegion.mak to Project" + File = "LegacyRegion2.mak" +End + +ELINK + Name = "$(BUILD_DIR)\LegacyRegion2.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + diff --git a/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.c b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.c new file mode 100644 index 0000000..275b297 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.c @@ -0,0 +1,80 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/MiscSubclass/MiscSubclass.c 1 2/08/12 4:36a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 4:36a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/MiscSubclass/MiscSubclass.c $ +// +// 1 2/08/12 4:36a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: MiscSubclass.c +// +// Description: This file for BIOS id Build in to Hii data base. +// +//<AMI_FHDR_END> +//********************************************************************** + +#include <AmiLib.h> +#include <AmiDxeLib.h> +#include <Setup.h> +#include <SetupStrTokens.h> + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitiMiscStrings +// +// Description: Create BIOS id string. +// +// Input: HiiHandle - Handle to HII database +// Class - Indicates the setup class +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +InitiMiscStrings ( + IN EFI_HII_HANDLE HiiHandle, + IN UINT16 Class +) +{ + STRING_REF Dummy [] = { STRING_TOKEN (STR_BIOS_ID)} + return; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//*************************************************************************
\ No newline at end of file diff --git a/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.cif b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.cif new file mode 100644 index 0000000..e105399 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.cif @@ -0,0 +1,13 @@ +<component> + name = "MiscSubclass" + category = ModulePart + LocalRoot = "Chipset\NB\SystemAgentWrap\MiscSubclass" + RefName = "MiscSubclass" +[files] +"MiscSubclass.sdl" +"MiscSubclass.mak" +"MiscSubclassStrings.uni" +"MiscSubclass.c" +"MiscSubclassDxe.c" +"MiscSubclassDxe.dxs" +<endComponent> diff --git a/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.mak b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.mak new file mode 100644 index 0000000..66c165d --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.mak @@ -0,0 +1,106 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/MiscSubclass/MiscSubclass.mak 1 2/08/12 4:36a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 4:36a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/MiscSubclass/MiscSubclass.mak $ +# +# 1 2/08/12 4:36a Yurenlai +# Intel Haswell/NB eChipset initially releases. +# +#************************************************************************* + +#--------------------------------------------------------------------------- +# Create SmBiosMemory DXE driver +#--------------------------------------------------------------------------- +all: MiscSubclass MiscSubclassSDB MiscSubclassDxe + +#MiscSubclass: $(BUILD_DIR)\MiscSubclass.mak MiscSubclassBin +MiscSubclass: $(BUILD_DIR)\MiscSubclass.mak + +$(BUILD_DIR)\MiscSubclass.mak : $(MiscSubclass_DIR)\$(@B).cif $(MiscSubclass_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(MiscSubclass_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +MiscSubclass_OBJECTS = \ +$(BUILD_DIR)\$(MiscSubclass_DIR)\MiscSubclass.obj \ +$(BUILD_DIR)\MiscSubclassStrings.obj \ + +#MiscSubclassBin : $(PRINTLIB) $(EFIDRIVERLIB) $(EDKGUIDLIB) $(EFIPROTOCOLLIB) $(EFIIFRSUPPORTLIB) +# $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ +# /f $(BUILD_DIR)\MiscSubclass.mak all\ +# GUID=EDA39402-F375-4496-92D3-83B43CB8A76A\ +# "MY_INCLUDES=$(SmBiosMemory_INCLUDES)" \ +# ENTRY_POINT=MiscSubclass\ +# TYPE=BS_DRIVER\ +# "OBJECTS=$(MiscSubclass_OBJECTS)"\ +# DEPEX1=$(SmBiosMemory_DIR)\SmBiosMemory.dxs\ +# DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\ +# COMPRESS=1 + +#--------------------------------------------------------------------------- +# Create MiscSubclass Setup Screens +#--------------------------------------------------------------------------- +MiscSubclassSDB : $(BUILD_DIR)\MiscSubclass.mak + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\MiscSubclass.mak all\ + TYPE=SDB NAME=MiscSubclass + $(STRGATHER) -dump -lang $(SUPPORTED_LANGUAGES: = -lang )\ + -db $(BUILD_DIR)\MiscSubclass.sdb\ + -bn MiscSubclass\ + -oh $(BUILD_DIR)\MiscSubclassStrings.h\ + -oc $(BUILD_DIR)\MiscSubclassStrings.c + $(CC) $(CFLAGS) /Fo$(BUILD_DIR)\ $(BUILD_DIR)\MiscSubclassStrings.c + +#---------------------------------------------------------------------------- +# Create MiscSubclass DXE Component +#---------------------------------------------------------------------------- +MiscSubclassDxe : $(BUILD_DIR)\MiscSubclass.mak MiscSubclassDxeBin + +MiscSubclass_DXE_OBJECTS = $(BUILD_DIR)\$(MiscSubclass_DIR)\MiscSubclassDxe.obj \ +$(BUILD_DIR)\MiscSubclassStrings.obj \ + +MiscSubclassDxeBin : $(AMICSPLib) $(AMIDXELIB) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\MiscSubclass.mak all\ + NAME=MiscSubclassDxe\ + MAKEFILE=$(BUILD_DIR)\MiscSubclass.mak \ + OBJECTS="$(MiscSubclass_DXE_OBJECTS)" \ + GUID=16271FCA-55D9-4a33-93FC-5A3EB128DE21 \ + ENTRY_POINT=MiscSubclassDxe_Init \ + "CFLAGS=$(CFLAGS) /I$(NB_CHIPSET_DIR) /I$(NB_BOARD_DIR) /I$(SB_CHIPSET_DIR) /I$(SB_BOARD_DIR)"\ + "EXT_HEADERS=$(BUILD_DIR)\token.h"\ + TYPE=BS_DRIVER \ + DEPEX1=$(MiscSubclass_DIR)\MiscSubclassDxe.dxs DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + COMPRESS=1 + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.sdl b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.sdl new file mode 100644 index 0000000..df10827 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.sdl @@ -0,0 +1,69 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/MiscSubclass/MiscSubclass.sdl 1 2/08/12 4:36a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 4:36a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/MiscSubclass/MiscSubclass.sdl $ +# +# 1 2/08/12 4:36a Yurenlai +# Intel Haswell/NB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "MISC_SUBCLASS_SUPPORT" + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Master = Yes + Help = "Main switch to enable MiscSubclass support in Project" +End + +MODULE + Help = "Includes MiscSubclass.mak to Project" + File = "MiscSubclass.mak" +End + +PATH + Name = "MiscSubclass_DIR" +End + +ELINK + Name = "$(BUILD_DIR)\MiscSubclassDxe.ffs" + Parent = "FV_MAIN" + Help = "Add Intel MiscSubclass Dxe driver" + InvokeOrder = AfterParent +End + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclassDxe.c b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclassDxe.c new file mode 100644 index 0000000..8f87be9 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclassDxe.c @@ -0,0 +1,483 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/MiscSubclass/MiscSubclassDxe.c 1 2/08/12 4:36a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 4:36a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/MiscSubclass/MiscSubclassDxe.c $ +// +// 1 2/08/12 4:36a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: MiscSubclassDxe.c +// +// Description: This file for init Hii data base in BIOS id. +// +//<AMI_FHDR_END> +//************************************************************************* + +//--------------------------------------------------------------------------- +// Include(s) +//--------------------------------------------------------------------------- + +#include <Efi.h> +#include <token.h> +#include <AmiLib.h> +#include <AmiDxeLib.h> +#include <Setup.h> +#include <Dxe.h> +#include <PCI.h> +#include <AmiHobs.h> +#include <AmiCspLib.h> + +// Produced Protocols + +// Consumed Protocols + +#include <Protocol\DataHub.h> +#include <Include\DataHubSubClass.h> + +#if EFI_SPECIFICATION_VERSION >= 0x2000A +#include "Include\UefiHii.h" +#include "Protocol\HiiDatabase.h" +#include "Protocol\HiiString.h" +#else +#include <Protocol/Hii.h> +#endif + +//--------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//--------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) +#define EFI_MISC_SUBCLASS_GUID \ +{ 0x772484B2, 0x7482, 0x4b91, 0x9F, 0x9A, 0xAD, 0x43, 0xF8, 0x1C, 0x58, 0x81 } + +#define EFI_MISC_SUBCLASS_DRIVER_GUID \ + { 0xF50E702C, 0x8653, 0x4CDE, 0xBB, 0xCE, 0x43, 0xB4, 0xD5, 0x5B, 0x34, 0xB8 } + +// Type Definition(s) + +#define EFI_MISC_SUBCLASS_VERSION 0x0100 +#define EFI_DATA_RECORD_CLASS_DATA 0x0000000000000004 +#define EFI_MISC_BIOS_VENDOR_RECORD_NUMBER 0x00000002 + +#define EFI_SUBCLASS_INSTANCE_NON_APPLICABLE 0xFFFF //16 bit +// Function Prototype(s) + +//--------------------------------------------------------------------------- +// Variable and External Declaration(s) +//--------------------------------------------------------------------------- +// Variable Declaration(s) + +// GUID Definition(s) +EFI_GUID gEfiMiscSubClassGuid = EFI_MISC_SUBCLASS_GUID; +EFI_GUID gEfiMiscSubClassDriverGuid = EFI_MISC_SUBCLASS_DRIVER_GUID; +EFI_GUID gEfiDataHubProtocolGuid = EFI_DATA_HUB_PROTOCOL_GUID; + +// Protocol Definition(s) + +// External Declaration(s) + +// Function Definition(s) +EFI_STATUS InstallMiscSubClassData ( + IN EFI_HANDLE ImageHandle +); + + +typedef struct { + UINT8 LastPciBus; +} EFI_MISC_LAST_PCI_BUS; + +typedef struct { + UINT32 Reserved1 :2; + UINT32 Unknown :1; + UINT32 BiosCharacteristicsNotSupported :1; + UINT32 IsaIsSupported :1; + UINT32 McaIsSupported :1; + UINT32 EisaIsSupported :1; + UINT32 PciIsSupported :1; + UINT32 PcmciaIsSupported :1; + UINT32 PlugAndPlayIsSupported :1; + UINT32 ApmIsSupported :1; + UINT32 BiosIsUpgradable :1; + UINT32 BiosShadowingAllowed :1; + UINT32 VlVesaIsSupported :1; + UINT32 EscdSupportIsAvailable :1; + UINT32 BootFromCdIsSupported :1; + UINT32 SelectableBootIsSupported :1; + UINT32 RomBiosIsSocketed :1; + UINT32 BootFromPcmciaIsSupported :1; + UINT32 EDDSpecificationIsSupported :1; + UINT32 JapaneseNecFloppyIsSupported :1; + UINT32 JapaneseToshibaFloppyIsSupported :1; + UINT32 Floppy525_360IsSupported :1; + UINT32 Floppy525_12IsSupported :1; + UINT32 Floppy35_720IsSupported :1; + UINT32 Floppy35_288IsSupported :1; + UINT32 PrintScreenIsSupported :1; + UINT32 Keyboard8042IsSupported :1; + UINT32 SerialIsSupported :1; + UINT32 PrinterIsSupported :1; + UINT32 CgaMonoIsSupported :1; + UINT32 NecPc98 :1; + UINT32 AcpiIsSupported :1; + UINT32 UsbLegacyIsSupported :1; + UINT32 AgpIsSupported :1; + UINT32 I20BootIsSupported :1; + UINT32 Ls120BootIsSupported :1; + UINT32 AtapiZipDriveBootIsSupported :1; + UINT32 Boot1394IsSupported :1; + UINT32 SmartBatteryIsSupported :1; + UINT32 BiosBootSpecIsSupported :1; + UINT32 FunctionKeyNetworkBootIsSupported :1; + UINT32 TargetContentDistributionEnabled :1; + UINT32 Reserved :21; +} EFI_MISC_BIOS_CHARACTERISTICS; + +typedef struct { + UINT32 BiosReserved :16; + UINT32 SystemReserved :16; + UINT32 Reserved :32; +} EFI_MISC_BIOS_CHARACTERISTICS_EXTENSION; + +typedef struct { + STRING_REF BiosVendor; + STRING_REF BiosVersion; + STRING_REF BiosReleaseDate; + EFI_PHYSICAL_ADDRESS BiosStartingAddress; + EFI_EXP_BASE2_DATA BiosPhysicalDeviceSize; + EFI_MISC_BIOS_CHARACTERISTICS BiosCharacteristics1; + EFI_MISC_BIOS_CHARACTERISTICS_EXTENSION BiosCharacteristics2; + UINT8 BiosMajorRelease; + UINT8 BiosMinorRelease; + UINT8 BiosEmbeddedFirmwareMajorRelease; + UINT8 BiosEmbeddedFirmwareMinorRelease; +} EFI_MISC_BIOS_VENDOR; + +typedef union { + EFI_MISC_LAST_PCI_BUS LastPciBus; + EFI_MISC_BIOS_VENDOR MiscBiosVendor; +} EFI_MISC_SUBCLASS_RECORDS; + +typedef struct { + EFI_SUBCLASS_TYPE1_HEADER Header; + EFI_MISC_SUBCLASS_RECORDS Record; +} EFI_MISC_SUBCLASS_DRIVER_DATA; + +extern UINT8 MiscSubclass[]; + +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: MiscSubclassDxe_Init +// +// Description: This function is the entry point for MiscSubclass DXE driver. +// This function initializes the MiscSubclass in DXE phase. +// +// Input: ImageHandle - Image handle +// SystemTable - Pointer to the system table +// +// Output: EFI_SUCCESS +// +// Notes: +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS MiscSubclassDxe_Init ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + InitAmiLib(ImageHandle, SystemTable); + + Status = InstallMiscSubClassData (ImageHandle); + ASSERT_EFI_ERROR(Status); + + return EFI_SUCCESS; +} + + +#if EFI_SPECIFICATION_VERSION >= 0x2000A +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: PreparePackageList +// +// Description: +// Assemble EFI_HII_PACKAGE_LIST according to the passed in packages. +// +// Input: NumberOfPackages - Number of packages. +// GuidId - Package GUID. +// +// +// Output: Pointer of EFI_HII_PACKAGE_LIST_HEADER. +// +// Notes: +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_HII_PACKAGE_LIST_HEADER * +PreparePackageList ( + IN UINTN NumberOfPackages, + IN EFI_GUID *GuidId, + IN ... +) +{ + va_list Marker; + EFI_HII_PACKAGE_LIST_HEADER *PackageListHeader = NULL; + UINT8 *PackageListData; + UINT32 PackageListLength; + UINT32 PackageLength; + EFI_HII_PACKAGE_HEADER PackageHeader; + UINT8 *PackageArray; + UINTN Index; + + PackageListLength = sizeof (EFI_HII_PACKAGE_LIST_HEADER); + + va_start (Marker, GuidId); + for (Index = 0; Index < NumberOfPackages; Index++) { + pBS->CopyMem (&PackageLength, va_arg (Marker, VOID *), sizeof (UINT32)); + PackageListLength += (PackageLength - sizeof (UINT32)); + } + va_end (Marker); + + // + // Include the lenght of EFI_HII_PACKAGE_END + // + PackageListLength += sizeof (EFI_HII_PACKAGE_HEADER); + //PackageListHeader = EfiLibAllocateZeroPool (PackageListLength); + + // PackageListHeader = EfiLibAllocatePool (PackageListLength); + pBS->AllocatePool (EfiBootServicesData, PackageListLength, &PackageListHeader); + + if (PackageListHeader != NULL) { + pBS->SetMem (PackageListHeader, PackageListLength, 0); + } + + ASSERT (PackageListHeader != NULL); + pBS->CopyMem (&PackageListHeader->PackageListGuid, GuidId, sizeof (EFI_GUID)); + PackageListHeader->PackageLength = PackageListLength; + + PackageListData = ((UINT8 *) PackageListHeader) + sizeof (EFI_HII_PACKAGE_LIST_HEADER); + + va_start (Marker, GuidId); + for (Index = 0; Index < NumberOfPackages; Index++) { + PackageArray = (UINT8 *) va_arg (Marker, VOID *); + pBS->CopyMem (&PackageLength, PackageArray, sizeof (UINT32)); + PackageLength -= sizeof (UINT32); + PackageArray += sizeof (UINT32); + pBS->CopyMem (PackageListData, PackageArray, PackageLength); + PackageListData += PackageLength; + } + va_end (Marker); + + // + // Append EFI_HII_PACKAGE_END + // + PackageHeader.Type = EFI_HII_PACKAGE_END; + PackageHeader.Length = sizeof (EFI_HII_PACKAGE_HEADER); + pBS->CopyMem (PackageListData, &PackageHeader, PackageHeader.Length); + + return PackageListHeader; +} + +#else +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: PreparePackages +// +// Description: +// Assemble EFI_HII_PACKAGE_LIST according to the passed in packages. +// +// Input: NumberOfPackages - Number of packages. +// GuidId - Package GUID. +// +// +// Output: Pointer of EFI_HII_PACKAGE_LIST_HEADER. +// +// Notes: +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_HII_PACKAGES * +PreparePackages ( + IN UINTN NumberOfPackages, + IN EFI_GUID *GuidId, + IN ... +) +{ + va_list args; + EFI_HII_PACKAGES *HiiPackages; + VOID **Package; + UINTN Index; + EFI_STATUS Status; + ASSERT (NumberOfPackages > 0); + + Status = pBS->AllocatePool(EfiBootServicesData, (sizeof (EFI_HII_PACKAGES)) + NumberOfPackages * sizeof (VOID *), &HiiPackages); + HiiPackages->GuidId = GuidId; + HiiPackages->NumberOfPackages = NumberOfPackages; + Package = (VOID **) (((UINT8 *) HiiPackages) + sizeof (EFI_HII_PACKAGES)); + + va_start (args, GuidId); + + for (Index = 0; Index < NumberOfPackages; Index++) { + *Package = va_arg (args, VOID *); + Package++; + } + + va_end (args); + + return HiiPackages; +} + +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InstallMiscSubClassData +// +// Description: +// Install MiscSubClassData for IgdOpRegion. +// +// Input: ImageHandle +// +// +// Output: Status. +// +// Notes: +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS InstallMiscSubClassData ( + IN EFI_HANDLE ImageHandle +) +{ + EFI_STATUS Status; + EFI_DATA_HUB_PROTOCOL *DataHub; + EFI_MISC_SUBCLASS_DRIVER_DATA MiscSubClassData; + EFI_STRING StringBuffer; + EFI_HII_HANDLE HiiHandle; +#if EFI_SPECIFICATION_VERSION >= 0x2000A + CHAR8 Language[]="en-US"; + EFI_HII_DATABASE_PROTOCOL *HiiDatabase; + EFI_HII_STRING_PROTOCOL *HiiString; + EFI_HII_PACKAGE_LIST_HEADER *PackageList; +#else + EFI_HII_PROTOCOL *Hii; + EFI_HII_PACKAGES *PackageList; +#endif + + Status = pBS->LocateProtocol (&gEfiDataHubProtocolGuid, NULL, &DataHub); + ASSERT_EFI_ERROR (Status); + +#if EFI_SPECIFICATION_VERSION >= 0x2000A + // There should only be one HII Database protocol + Status = pBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL, &HiiDatabase); + ASSERT_EFI_ERROR (Status); + + Status = pBS->LocateProtocol (&gEfiHiiStringProtocolGuid, NULL, &HiiString); + ASSERT_EFI_ERROR (Status); + +#else + // There should only be one HII protocol + Status = pBS->LocateProtocol (&gEfiHiiProtocolGuid, NULL, &Hii); + ASSERT_EFI_ERROR (Status); +#endif + + MiscSubClassData.Header.Version = EFI_MISC_SUBCLASS_VERSION; + MiscSubClassData.Header.HeaderSize = sizeof (EFI_SUBCLASS_TYPE1_HEADER); + MiscSubClassData.Header.Instance = 1; + MiscSubClassData.Header.SubInstance = EFI_SUBCLASS_INSTANCE_NON_APPLICABLE; + MiscSubClassData.Header.RecordType = EFI_MISC_BIOS_VENDOR_RECORD_NUMBER; + + Status = pBS->AllocatePool(EfiBootServicesData, (sizeof (CHAR16)) * 100, &StringBuffer); + pBS->SetMem(StringBuffer, (sizeof(CHAR16)) * 100, 0); + + Strcpy ((char*)StringBuffer, CONVERT_TO_STRING(BIOSID)); + +#if EFI_SPECIFICATION_VERSION >= 0x2000A + + PackageList = PreparePackageList (1, &gEfiMiscSubClassDriverGuid, MiscSubclass); + + Status = HiiDatabase->NewPackageList ( + HiiDatabase, + PackageList, + ImageHandle, + &HiiHandle + ); + +#else + PackageList = PreparePackages (1, &gEfiMiscSubClassDriverGuid, MiscSubclass); + Status = Hii->NewPack (Hii, PackageList, &HiiHandle); +#endif + ASSERT_EFI_ERROR (Status); + pBS->FreePool (PackageList); + + MiscSubClassData.Record.MiscBiosVendor.BiosVersion = (STRING_REF)0; +#if EFI_SPECIFICATION_VERSION >= 0x2000A + Status = HiiString->NewString (HiiString, HiiHandle, &MiscSubClassData.Record.MiscBiosVendor.BiosVersion, Language, NULL, StringBuffer, NULL); + +// Status = HiiLibSetString(HiiHandle, MiscSubClassData.Record.MiscBiosVendor.BiosVersion, StringBuffer); + if (EFI_ERROR(Status)) return Status; +#else + Hii->NewString ( + Hii, + NULL, + HiiHandle, + &MiscSubClassData.Record.MiscBiosVendor.BiosVersion, + StringBuffer + ); +#endif + + + Status = DataHub->LogData ( + DataHub, + &gEfiMiscSubClassGuid, + &gEfiMiscSubClassDriverGuid, + EFI_DATA_RECORD_CLASS_DATA, + &MiscSubClassData, + sizeof (EFI_SUBCLASS_TYPE1_HEADER) + sizeof (EFI_MISC_BIOS_VENDOR) + ); + + pBS->FreePool(StringBuffer); + + return Status; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclassDxe.dxs b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclassDxe.dxs new file mode 100644 index 0000000..aa12ec3 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclassDxe.dxs @@ -0,0 +1,70 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/MiscSubclass/MiscSubclassDxe.dxs 1 2/08/12 4:37a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 4:37a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/MiscSubclass/MiscSubclassDxe.dxs $ +// +// 1 2/08/12 4:37a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: MiscSubclassDxe.DXS +// +// Description: This file is the dependency file for the MiscSubclass DXE driver. +// +//<AMI_FHDR_END> +//************************************************************************* +#include <Protocol\DataHub.h> + +#if EFI_SPECIFICATION_VERSION >= 0x2000A +#include "Include\UefiHii.h" +#include "Protocol\HiiDatabase.h" +#include "Protocol\HiiString.h" +#else +#include <Protocol/Hii.h> +#endif + +DEPENDENCY_START + EFI_DATA_HUB_PROTOCOL_GUID AND +#if EFI_SPECIFICATION_VERSION >= 0x2000A + EFI_HII_DATABASE_PROTOCOL_GUID AND + EFI_HII_STRING_PROTOCOL_GUID +#else + EFI_HII_PROTOCOL_GUID +#endif +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclassStrings.uni b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclassStrings.uni Binary files differnew file mode 100644 index 0000000..508d5e6 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclassStrings.uni diff --git a/Chipset/NB/SystemAgentWrap/SystemAgentWrap.cif b/Chipset/NB/SystemAgentWrap/SystemAgentWrap.cif new file mode 100644 index 0000000..bd07ece --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/SystemAgentWrap.cif @@ -0,0 +1,12 @@ +<component> + name = "SystemAgentWrap" + category = ModulePart + LocalRoot = "Chipset\NB\SystemAgentWrap\" + RefName = "SystemAgentWrap" +[files] +"SystemAgentWrap.sdl" +[parts] +"MiscSubclass" +"UpdateMemoryRecord" +"LegacyRegion2" +<endComponent> diff --git a/Chipset/NB/SystemAgentWrap/SystemAgentWrap.sdl b/Chipset/NB/SystemAgentWrap/SystemAgentWrap.sdl new file mode 100644 index 0000000..badcac8 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/SystemAgentWrap.sdl @@ -0,0 +1,77 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/SystemAgentWrap.sdl 3 7/31/13 3:28a Ireneyang $ +# +# $Revision: 3 $ +# +# $Date: 7/31/13 3:28a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/SystemAgentWrap.sdl $ +# +# 3 7/31/13 3:28a Ireneyang +# [TAG] None +# [Category] Improvement +# [Description] Change token name REFERENCE_DDR_IO_BUS to DCLK_FREQUENCY. +# When it's 0, it would show DDR Frequency in SMBIOS +# (DCLK Frequency). +# When it's 1, it would show DDR IO Bus Clock in SMBIOS +# (QCLK Frequency). +# [Files] SystemAgentWrap.sdl; +# +# 2 6/26/13 5:29a Ireneyang +# [TAG] None +# [Category] Improvement +# [Description] According to SMBIOS spec, Set REFERENCE_DDR_IO_BUS token +# for choosing how to show DDR speed. +# [Files] SystemAgentWrap.sdl; UpdateMemoryRecord.c; +# +# 1 2/08/12 4:36a Yurenlai +# Intel Haswell/NB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "SystemAgentWrap_SUPPORT" + Value = "1" + Help = "Main switch to enable SystemAgentWrap support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes +End + +TOKEN + Name = "DCLK_FREQUENCY" + Value = "0" + Help = "Default: 0, 0 : DDR Frequency (DCLK Frequency) 1: DDR IO Bus Clock (QCLK Frequency)" + TokenType = Integer + TargetH = Yes +End + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.c b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.c new file mode 100644 index 0000000..cd4a8f6 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.c @@ -0,0 +1,1701 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.c 1 4/19/16 7:41a Chienhsieh $ +// +// $Revision: 1 $ +// +// $Date: 4/19/16 7:41a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.c $ +// +// 1 4/19/16 7:41a Chienhsieh +// Update rev10. +// +// 10 12/21/15 5:58a Chienhsieh +// [TAG] EIP249553 +// [Category] Improvement +// [Description] SMBIOS Type17 memory speed report issue with Hawell +// (Sharkbay) platform +// [Files] UpdateMemoryRecord.c +// +// 9 8/23/13 2:59a Ireneyang +// [TAG] EIP126356 +// [Category] Improvement +// [Description] Change calucating method for Dimm Frequency. +// [Files] UpdateMemoryRecord.c; +// +// 8 7/31/13 3:38a Ireneyang +// [TAG] None +// [Category] Improvement +// [Description] Change token name REFERENCE_DDR_IO_BUS to DCLK_FREQUENCY. +// When it's 0, it would show DDR Frequency in SMBIOS +// (DCLK Frequency). +// When it's 1, it would show DDR IO Bus Clock in SMBIOS +// (QCLK Frequency). +// [Files] SystemAgentWrap.sdl; UpdateMemoryRecord.c; +// +// 7 6/26/13 10:00a Ireneyang +// [TAG] None +// [Category] Improvement +// [Description] According to SMBIOS spec, Set REFERENCE_DDR_IO_BUS token +// for choosing how to show DDR speed. +// [Files] SystemAgentWrap.sdl; UpdateMemoryRecord.c; +// +// 5 6/26/13 4:27a Ireneyang +// [TAG] None +// [Category] Improvement +// [Description] Rename NbSmbiosType17Voltage() to +// NbSmbiosType17VoltageAndSpeed(). +// [Files] UpdateMemoryRecord.c; +// +// 4 6/13/13 7:14a Ireneyang +// [TAG] EIP125449 +// [Category] Improvement +// [Description] Update XmpId for SMBIOS Spec 2.8.0. +// +// 3 6/07/13 8:13a Ireneyang +// [TAG] EIP125449 +// [Category] Improvement +// [Description] Update SMBIOS Spec 2.8.0. +// +// 2 1/28/13 2:58a Jeffch +// [TAG] None +// [Category] Improvement +// [Description] Update SMBIOS Spec 2.7.1. +// +// +// 1 2/08/12 4:37a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: UpdateMemoryRecord.c +// +// Description: This file for update SMBIOS Type 16 ~19. +// +//<AMI_FHDR_END> +//********************************************************************** + +#include "UpdateMemoryRecord.h" + +#include <MemInfo\MemInfo.h> +#define __EFI__H__ +#ifndef GUID_VARIABLE_DEFINITION +#define GUID_VARIABLE_DECLARATION(Variable, Guid) extern EFI_GUID Variable +#else +#define GUID_VARIABLE_DECLARATION(Variable, Guid) GLOBAL_REMOVE_IF_UNREFERENCED EFI_GUID Variable=Guid +#endif +#include <Protocol\SmBus.h> + +#include <Protocol\SaPlatformPolicy\SaPlatformPolicy.h> + + +#define EFI_SMBIOS_BOARD_PROTOCOL_GUID \ + {0x903dd14, 0x2ca0, 0x458a, 0xb5, 0xeb, 0xc, 0xc, 0xa3, 0xd, 0x78, 0x5c} + +#define EFI_MEMORY_SUBCLASS_DRIVER_GUID \ + { 0x1767CEED, 0xDB82, 0x47cd, 0xBF, 0x2B, 0x68, 0x45, 0x8A, 0x8C, 0xCF, 0xFF } + + +EFI_GUID gEfiMemorySubClassDriverGuid = EFI_MEMORY_SUBCLASS_DRIVER_GUID; +EFI_GUID gEfiSmbiosBoardProtocolGuid = EFI_SMBIOS_BOARD_PROTOCOL_GUID; +EFI_GUID gEfiSmbiosUpdateDataProtocolGuid = EFI_SMBIOS_UPDATE_DATA_PROTOCOL_GUID; +EFI_GUID gDxePlatformSaPolicyGuid = DXE_PLATFORM_SA_POLICY_GUID; +EFI_GUID gMemInfoHobProtocolGuid = MEM_INFO_PROTOCOL_GUID; +EFI_GUID gEfiSmbusProtocolGuid = EFI_SMBUS_HC_PROTOCOL_GUID; + + +EFI_SMBIOS_UPDATE_DATA_PROTOCOL *gSBUpdate; +EFI_SMBIOS_PROTOCOL *gSmbiosProtocol; +MEM_INFO_PROTOCOL *gMemInfoHobProtocol = NULL; +EFI_SMBUS_HC_PROTOCOL *gSmbusProtocol = NULL; +DXE_PLATFORM_SA_POLICY_PROTOCOL *gDxePlatformSaPolicy = NULL; +static UINT8 DimmNumber = 0; +static UINT8 DimmSlot[4] = { DIMM1_SMBUS_ADDRESS, + DIMM2_SMBUS_ADDRESS, + DIMM3_SMBUS_ADDRESS, + DIMM4_SMBUS_ADDRESS + }; + +#define MRC_REF_CLOCK_133 (0) +#define MRC_REF_CLOCK_100 (1) +#define fNoInit (0) +#define f800 (800) +#define f1000 (1000) +#define f1067 (1067) +#define f1200 (1200) +#define f1333 (1333) +#define f1400 (1400) +#define f1600 (1600) +#define f1800 (1800) +#define f1867 (1867) +#define f2000 (2000) +#define f2133 (2133) +#define f2200 (2200) +#define f2400 (2400) +#define f2600 (2600) +#define f2667 (2667) +#define fUnSupport (0x7FFFFFFF) + +#define MRC_FREQUENCY_MTB_OFFSET 1000000 +#define MRC_FREQUENCY_FTB_OFFSET 1000 +#define MRC_DDR3_800_TCK_MIN 2500000 /// 1/(800/2) femtoseconds +#define MRC_DDR3_1000_TCK_MIN 2000000 /// 1/(1000/2) femtoseconds +#define MRC_DDR3_1067_TCK_MIN 1875000 /// 1/(1067/2) femtoseconds +#define MRC_DDR3_1200_TCK_MIN 1666666 /// 1/(1200/2) femtoseconds +#define MRC_DDR3_1333_TCK_MIN 1500000 /// 1/(1333/2) femtoseconds +#define MRC_DDR3_1400_TCK_MIN 1428571 /// 1/(1400/2) femtoseconds +#define MRC_DDR3_1600_TCK_MIN 1250000 /// 1/(1600/2) femtoseconds +#define MRC_DDR3_1800_TCK_MIN 1111111 /// 1/(1800/2) femtoseconds +#define MRC_DDR3_1867_TCK_MIN 1071428 /// 1/(1867/2) femtoseconds +#define MRC_DDR3_2000_TCK_MIN 1000000 /// 1/(2000/2) femtoseconds +#define MRC_DDR3_2133_TCK_MIN 937500 /// 1/(2133/2) femtoseconds +#define MRC_DDR3_2200_TCK_MIN 909090 /// 1/(2200/2) femtoseconds +#define MRC_DDR3_2400_TCK_MIN 833333 /// 1/(2400/2) femtoseconds +#define MRC_DDR3_2600_TCK_MIN 769230 /// 1/(2600/2) femtoseconds +#define MRC_DDR3_2667_TCK_MIN 750000 /// 1/(2667/2) femtoseconds +#define MRC_DDR3_2800_TCK_MIN 714285 /// 1/(2800/2) femtoseconds +#define TREFIMULTIPLIER 1000 /// tREFI value defined in XMP 1.3 spec is actually in thousands of MTB units. +#define MAX(a,b) (((a) > (b)) ? (a) : (b)) +#define MIN(a,b) (((a) < (b)) ? (a) : (b)) + +typedef struct { + UINT32 tCK; + UINT32 DDRFreq; + UINT8 RefClkFlag; // 0 = invalid freq. 1 = valid only at 133 RefClk, 2 = valid only at 100 RefClk, 3 = valid at both. +} NbTRangeTable; + +// Timing Range table +const NbTRangeTable NbRange[] = { + { 0xFFFFFFFF, fUnSupport, (0 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_800_TCK_MIN, f800, (1 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1000_TCK_MIN, f1000, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1067_TCK_MIN, f1067, (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1200_TCK_MIN, f1200, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1333_TCK_MIN, f1333, (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1400_TCK_MIN, f1400, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1600_TCK_MIN, f1600, (1 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1800_TCK_MIN, f1800, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1867_TCK_MIN, f1867, (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2000_TCK_MIN, f2000, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2133_TCK_MIN, f2133, (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2200_TCK_MIN, f2200, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2400_TCK_MIN, f2400, (1 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2600_TCK_MIN, f2600, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2667_TCK_MIN, f2667, (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { 0, fNoInit, (0 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) } +}; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ReadSpdData +// +// Description: Returns the length of the Dimm Spd +// +// Input: UINT8 SpdSalveAddr, +// UINT8 Offset, +// UINTN Count, +// Output: UINT8 *Buffer +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS ReadSpdData ( + IN UINT8 SpdSalveAddr, + IN UINT8 Offset, + IN UINTN Count, + OUT UINT8 *Buffer + ) +{ + EFI_STATUS Status; + UINTN Index; + UINTN Length; + EFI_SMBUS_OPERATION Operation; + EFI_SMBUS_DEVICE_COMMAND Command; + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + + if(gSmbusProtocol == NULL) return EFI_UNSUPPORTED; + + SlaveAddress.SmbusDeviceAddress = SpdSalveAddr >> 1; + + for (Index = 0; Index < Count; Index++) + { + Command = Offset + Index; + + Length = 1; + Operation = EfiSmbusReadByte; + Status = gSmbusProtocol->Execute (gSmbusProtocol, + SlaveAddress, + Command, + Operation, + FALSE, + &Length, + &Buffer[Index] ); + if (EFI_ERROR(Status)) return Status; + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: NbGetDimmTCK +// +// Description: Returns the Dimm tCK Timing +// +// +// Input: UINT32 tCK +// +// Output: TRUE - Have tCK Timing +// FALSE - Not have tCK Timing +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +static BOOLEAN +NbGetDimmTCK ( + UINT8 SpdFtbDividend, + UINT8 SpdFtbDivisor, + UINT8 SpdMtbDividend, + UINT8 SpdMtbDivisor, + UINT8 tCKminMtb, +// UINT8 tCKminFine, // EIP249553 + INT8 tCKminFine, + OUT UINT32 *tCK + ) +{ + INT32 MediumTimebase = 0; + INT32 FineTimebase = 0; + + FineTimebase = (SpdFtbDivisor == 0) ? 0 : (SpdFtbDividend * MRC_FREQUENCY_FTB_OFFSET) / SpdFtbDivisor; + MediumTimebase = (SpdMtbDivisor == 0) ? 0 : (SpdMtbDividend * MRC_FREQUENCY_MTB_OFFSET) / SpdMtbDivisor; + *tCK = (MediumTimebase * tCKminMtb) + (FineTimebase * tCKminFine); + + return (MediumTimebase == 0) ? FALSE : TRUE; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: NbGetDimmFrequency +// +// Description: Returns Dimm Frequency +// +// +// Input: UINT32 tCK +// +// Output: UINT32 XmpFrequency +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +static +UINT32 +NbGetDimmFrequency ( + IN UINT32 tCK + ) +{ + UINT32 Index; + UINT32 XmpFrequency = fNoInit; + UINT32 NbRangeSize = (sizeof (NbRange) / sizeof (NbTRangeTable)) - 1; + + if(tCK == 0 || tCK == 0xffffffff) return fNoInit; + + for (Index = 0; Index < NbRangeSize; Index++) { + if ((tCK <= NbRange[Index].tCK) && (tCK > NbRange[Index + 1].tCK)) { + XmpFrequency = NbRange[Index].DDRFreq; + break; + } + } + + while (Index) { + if ((NbRange[Index].RefClkFlag & (1 << gMemInfoHobProtocol->MemInfoData.RefClk)) == MRC_REF_CLOCK_133) { + XmpFrequency = NbRange[--Index].DDRFreq; + } else break; + } + + return XmpFrequency; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: NbSmbiosType17Voltage +// +// Description: To update MinimumVoltage, MaximumVoltage, ConfiguredVoltage +// and Dimm Frequency +// +// +// Input: SMBIOS_MEMORY_DEVICE_INFO *TypeBuffer +// +// Output: SMBIOS_MEMORY_DEVICE_INFO *TypeBuffer +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS NbSmbiosType17VoltageAndSpeed ( + IN OUT SMBIOS_MEMORY_DEVICE_INFO *TypeBuffer + ) +{ + UINT8 VoltageCap = 0; + UINT16 XmpId = 0; + UINT8 XmpProfileCap = 0; + UINT8 SpdFtbDividend = 0; + UINT8 SpdFtbDivisor = 0; + UINT8 SpdMtbDividend = 0; + UINT8 SpdMtbDivisor = 0; + UINT8 tCKminMtb = 0; +// UINT8 tCKminFine = 0; // EIP249553 + INT8 tCKminFine; + UINT32 tCK = 0; + UINT32 XmpProfile1Speed = 0; + UINT32 XmpProfile2Speed = 0; + UINT8 SpdData[18] = {6, 9, 10, 11, 12, 34, 176, 177, 178, 180, 181, 182, 183, 184, 186, 211, 221, 246}; + EFI_STATUS Status; + UINT8 i; + + // find DimmNumber + for ( ; DimmNumber < 4; DimmNumber++) { + if (DimmSlot[DimmNumber] != 0) break; + } + + if(gMemInfoHobProtocol != NULL) { + if (gMemInfoHobProtocol->MemInfoData.DimmExist[DimmNumber]) { // DIMM_PRESENT + for (i = 0; i < sizeof(SpdData) ; i++) { + // Get Spd data + Status = ReadSpdData(DimmSlot[DimmNumber], SpdData[i], 1, &SpdData[i]); + if (EFI_ERROR (Status)) { + // if memory down mode, use MemInfoHob + SpdData[i] = *(UINT8 *)(gMemInfoHobProtocol->MemInfoData.DimmsSpdData[DimmNumber] + SpdData[i]); + } + } + + XmpId = *(UINT16 *)&SpdData[6]; + + VoltageCap = SpdData[0]; + XmpProfileCap = SpdData[8]; + +#if defined AMI_SMBIOS_MODULE_VERSION && AMI_SMBIOS_MODULE_VERSION >= 105 + if (VoltageCap & 0x04) { // 1.25 v + TypeBuffer->MinimumVoltage = 1250; + } else if (VoltageCap & 0x02) { // 1.35 v + TypeBuffer->MinimumVoltage = 1350; + } else if (!(VoltageCap & 0x01)) { // 1.5 v bit0 = 0 + TypeBuffer->MinimumVoltage = 1500; + } + + if (!(VoltageCap & 0x01)) { // 1.5 v bit0 = 0 + TypeBuffer->MaximumVoltage = 1500; + } else if (VoltageCap & 0x02) { // 1.35 v + TypeBuffer->MaximumVoltage = 1350; + } else if (VoltageCap & 0x04) { // 1.25 v + TypeBuffer->MaximumVoltage = 1250; + } + + TypeBuffer->ConfiguredVoltage = gMemInfoHobProtocol->MemInfoData.VddVoltage[0]; +#endif + // Calculate Dimm STD Profile + SpdFtbDivisor = SpdData[1]; + SpdFtbDividend = (UINT8)(SpdFtbDivisor >> 4); + SpdFtbDivisor &= 0x0f; + SpdMtbDividend = SpdData[2]; + SpdMtbDivisor = SpdData[3]; + tCKminMtb = SpdData[4]; + tCKminFine = SpdData[5]; + // Get tCK Timing + if(NbGetDimmTCK(SpdFtbDividend, SpdFtbDivisor, SpdMtbDividend, SpdMtbDivisor, tCKminMtb, tCKminFine, &tCK)){ + // Get Dimm Frequency + TypeBuffer->Speed = NbGetDimmFrequency(tCK); + +#if defined DCLK_FREQUENCY && DCLK_FREQUENCY == 1 + // Get Dimm Frequency + if((NbGetDimmFrequency(tCK)%5) == 3) { + TypeBuffer->Speed = (NbGetDimmFrequency(tCK)/2)+1; + } else { + TypeBuffer->Speed = (NbGetDimmFrequency(tCK)/2); + } +#endif + } + + if(XmpId == 0x4A0C) { // is XMP + + // Calculate Dimm XMP Profile 1 + if (XmpProfileCap & 0x01) { + SpdFtbDivisor = SpdData[13]; + SpdFtbDividend = (UINT8)(SpdFtbDivisor >> 4); + SpdFtbDivisor &= 0x0f; + SpdMtbDividend = SpdData[9]; + SpdMtbDivisor = SpdData[10]; + tCKminMtb = SpdData[14]; + tCKminFine = SpdData[15]; + // Get tCK Timing + if(NbGetDimmTCK(SpdFtbDividend, SpdFtbDivisor, SpdMtbDividend, SpdMtbDivisor, tCKminMtb, tCKminFine, &tCK)){ + // Get Dimm Frequency + XmpProfile1Speed = NbGetDimmFrequency(tCK); + // Speed must MAX Speed. + TypeBuffer->Speed = MAX(TypeBuffer->Speed, XmpProfile1Speed); + +#if defined DCLK_FREQUENCY && DCLK_FREQUENCY == 1 + // Speed must MAX Speed. + TypeBuffer->Speed = MAX(TypeBuffer->Speed, ((XmpProfile1Speed/2)+1)); +#endif + } + } + + // Calculate Dimm XMP Profile 2 + if (XmpProfileCap & 0x02) { + SpdFtbDivisor = SpdData[13]; + SpdFtbDividend = (UINT8)(SpdFtbDivisor >> 4); + SpdFtbDivisor &= 0x0f; + SpdMtbDividend = SpdData[11]; + SpdMtbDivisor = SpdData[12]; + tCKminMtb = SpdData[16]; + tCKminFine = SpdData[17]; + // Get tCK Timing + if(NbGetDimmTCK(SpdFtbDividend, SpdFtbDivisor, SpdMtbDividend, SpdMtbDivisor, tCKminMtb, tCKminFine, &tCK)){ + // Get Dimm Frequency + XmpProfile2Speed = NbGetDimmFrequency(tCK); + // Speed must MAX Speed. + TypeBuffer->Speed = MAX(TypeBuffer->Speed, XmpProfile2Speed); + +#if defined DCLK_FREQUENCY && DCLK_FREQUENCY == 1 + // Speed must MAX Speed. + TypeBuffer->Speed = MAX(TypeBuffer->Speed, ((XmpProfile2Speed/2)+1)); +#endif + } + } + + } // if(XmpId == 0x4A0C) + } // if (gMemInfoHobProtocol.MemInfoData.DimmExist != DIMM_PRESENT) + } // if(gMemInfoHobProtocol != NULL) + + return EFI_SUCCESS; +}; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: GetStructureLength +// +// Description: Returns the length of the structure pointed by BufferStart +// in bytes +// +// Input: UINT8 *BufferStart +// +// Output: Structure Size +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT16 +GetStructureLength( + IN UINT8 *BufferStart +) +{ + UINT8 *BufferEnd = BufferStart; + + BufferEnd += ((SMBIOS_STRUCTURE_HEADER*)BufferStart)->Length; + while (*(UINT16*)BufferEnd != 0) + { + BufferEnd++; + } + + return (UINT16)(BufferEnd + 2 - BufferStart); // +2 for double zero terminator +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: FindStructureType +// +// Description: Find structure type starting from memory location pointed by +// Buffer +// +// Input: UINT8 **Buffer +// UINT8 **StructureFoundPtr +// UINT8 SearchType +// UINT8 Instance +// +// Output: If SearchType is found: +// UINT8 **Buffer - Points to the next structure +// UINT8 **StructureFoundPtr - Points to the structure +// that was found +// If SearchType is not found: +// UINT8 **Buffer - No change +// UINT8 **StructureFoundPtr = NULL +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +BOOLEAN +FindStructureType( + IN OUT UINT8 **Buffer, + IN OUT UINT8 **StructureFoundPtr, + IN UINT8 SearchType, + IN UINT8 Instance // 1-based +) +{ + UINT8 *BufferPtr = *Buffer; + BOOLEAN FindStatus = FALSE; + + *StructureFoundPtr = NULL; + while (((SMBIOS_STRUCTURE_HEADER*)BufferPtr)->Type != 127) + { + if (((SMBIOS_STRUCTURE_HEADER*)BufferPtr)->Type == SearchType) + { + // If this instance, set the find status flag and update the Buffer pointer + if (--Instance == 0) + { + FindStatus = TRUE; + *StructureFoundPtr = BufferPtr; + *Buffer = BufferPtr + GetStructureLength(BufferPtr); + break; + } + } + BufferPtr += GetStructureLength(BufferPtr); + } + + if ((FindStatus == FALSE) & (SearchType == 127)) + { + FindStatus = TRUE; + *StructureFoundPtr = BufferPtr; + *Buffer = BufferPtr + GetStructureLength(BufferPtr); + } + + return FindStatus; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: BuildType16 +// +// Description: Build SMBIOS Type 16 +// +// Input: SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, +// EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData +// +// Output: +// None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +BuildType16( + IN SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, + IN EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData +) +{ + SMBIOS_PHYSICAL_MEM_ARRAY_INFO *TypeBuffer; + UINT16 bsize; + + // Allocate temporary buffer + TypeBuffer = EfiLibAllocateZeroPool(sizeof(SMBIOS_PHYSICAL_MEM_ARRAY_INFO)+0x100); + + // Build header of structure + TypeBuffer->StructureType.Type = 16; // Type 16 + TypeBuffer->StructureType.Length = sizeof(SMBIOS_PHYSICAL_MEM_ARRAY_INFO); + TypeBuffer->StructureType.Handle = gSBUpdate->SMBIOS_GetFreeHandle(SmbiosBuffer); + + // Build Content of structure + TypeBuffer->Location = MemorySubClassData->ArrayLocationData.MemoryArrayLocation; + TypeBuffer->Use = MemorySubClassData->ArrayLocationData.MemoryArrayUse; + TypeBuffer->MemErrorCorrection = MemorySubClassData->ArrayLocationData.MemoryErrorCorrection; + TypeBuffer->MaxCapacity = MemorySubClassData->ArrayLocationData.MaximumMemoryCapacity; + if (TypeBuffer->MaxCapacity >= 0x80000000) + { + TypeBuffer->ExtMaxCapacity = TypeBuffer->MaxCapacity; + TypeBuffer->MaxCapacity = 0x80000000; + } + else + { + TypeBuffer->ExtMaxCapacity = 0; + } + + // + // Maximum memory supported by the memory controller + // 2 GB in terms of KB + // +#if MEMORY_ERROR_INFO + TypeBuffer->MemErrInfoHandle = SMBIOS_UNKNOW; +#else + TypeBuffer->MemErrInfoHandle = SMBIOS_NOT_PROVIDE; +#endif + TypeBuffer->NumberOfMemDev = MemorySubClassData->ArrayLocationData.NumberMemoryDevices; + + // Write structure To SMBIOS Buffer + bsize = SMBIOS_GetStructureTotalSize((UINT8 *)TypeBuffer); + gSBUpdate->SMBIOS_InsertStructure(SmbiosBuffer, (UINT8 *)TypeBuffer, bsize); + + // Fix handle link + SMBIOS_FixHandleLink(SmbiosBuffer); + + // Free temporary buffer + gBS->FreePool(TypeBuffer); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: BuildType17 +// +// Description: Build SMBIOS Type 17 +// +// Input: SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, +// EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +BuildType17( + IN SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, + IN EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData +) +{ + SMBIOS_MEMORY_DEVICE_INFO *TypeBuffer; + UINT16 bsize; + + // Allocate temporary buffer + TypeBuffer = EfiLibAllocateZeroPool(sizeof(SMBIOS_MEMORY_DEVICE_INFO)+0x100); + + // Build header of structure + TypeBuffer->StructureType.Type = 17; // Type 17 + TypeBuffer->StructureType.Length = sizeof(SMBIOS_MEMORY_DEVICE_INFO); + TypeBuffer->StructureType.Handle = gSBUpdate->SMBIOS_GetFreeHandle(SmbiosBuffer); + + // Build Content of structure + TypeBuffer->PhysicalMemArrayHandle = (UINT16)gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 16, 1); +#if MEMORY_ERROR_INFO + TypeBuffer->MemErrorInfoHandle = SMBIOS_UNKNOW; +#else + TypeBuffer->MemErrorInfoHandle = SMBIOS_NOT_PROVIDE; +#endif + TypeBuffer->TotalWidth = MemorySubClassData->ArrayLink.MemoryTotalWidth; + TypeBuffer->DataWidth = MemorySubClassData->ArrayLink.MemoryDataWidth; + TypeBuffer->Size = (UINT16) (RShiftU64 (MemorySubClassData->ArrayLink.MemoryDeviceSize, 20)); + TypeBuffer->FormFactor = MemorySubClassData->ArrayLink.MemoryFormFactor; + TypeBuffer->DeviceSet = MemorySubClassData->ArrayLink.MemoryDeviceSet; + TypeBuffer->DeviceLocator = TransferHiiStringToSmbios((UINT8 *)TypeBuffer, MemorySubClassData->ArrayLink.MemoryDeviceLocator); + TypeBuffer->BankLocator = TransferHiiStringToSmbios((UINT8 *)TypeBuffer, MemorySubClassData->ArrayLink.MemoryBankLocator); + TypeBuffer->MemoryType = MemorySubClassData->ArrayLink.MemoryType; + TypeBuffer->TypeDetail = *((UINT16*)(&(MemorySubClassData->ArrayLink.MemoryTypeDetail))); + TypeBuffer->Speed = 0; + TypeBuffer->Manufacturer = TransferHiiStringToSmbios((UINT8 *)TypeBuffer, MemorySubClassData->ArrayLink.MemoryManufacturer); + TypeBuffer->SerialNumber = TransferHiiStringToSmbios((UINT8 *)TypeBuffer, MemorySubClassData->ArrayLink.MemorySerialNumber); + TypeBuffer->AssetTag = TransferHiiStringToSmbios((UINT8 *)TypeBuffer, MemorySubClassData->ArrayLink.MemoryAssetTag); + TypeBuffer->PartNumber = TransferHiiStringToSmbios((UINT8 *)TypeBuffer, MemorySubClassData->ArrayLink.MemoryPartNumber); + TypeBuffer->Attributes = MemorySubClassData->ArrayLink.MemoryAttributes; + TypeBuffer->ConfMemClkSpeed = MemorySubClassData->ArrayLink.MemorySpeed; +#if defined DCLK_FREQUENCY && DCLK_FREQUENCY == 1 + TypeBuffer->ConfMemClkSpeed = ((MemorySubClassData->ArrayLink.MemorySpeed)/2)+1; +#endif + TypeBuffer->ExtendedSize = 0; +#if defined AMI_SMBIOS_MODULE_VERSION && AMI_SMBIOS_MODULE_VERSION >= 105 + TypeBuffer->MinimumVoltage = 0; // unknown SmBios 2.8.0+ + TypeBuffer->MaximumVoltage = 0; // unknown SmBios 2.8.0+ + TypeBuffer->ConfiguredVoltage = 0; // unknown SmBios 2.8.0+ +#endif + + if (TypeBuffer->Size >= 0x8000 ) // 32G + { + TypeBuffer->ExtendedSize = TypeBuffer->Size; + + // ExtendedSize Bit 31 is reserved for future use and must be set to 0. + if (TypeBuffer->ExtendedSize >= BIT31) { + TypeBuffer->ExtendedSize = BIT31 - 1; + } + TypeBuffer->Size = 0x7FFF; + } + + // SmBios 2.8.0+ + // To update MinimumVoltage, MaximumVoltage, ConfiguredVoltage and Dimm Frequency + NbSmbiosType17VoltageAndSpeed (TypeBuffer); + + // Write structure To SMBIOS Buffer + bsize = SMBIOS_GetStructureTotalSize((UINT8 *)TypeBuffer); + gSBUpdate->SMBIOS_InsertStructure(SmbiosBuffer, (UINT8 *)TypeBuffer, bsize); + + // Fix handle link + SMBIOS_FixHandleLink(SmbiosBuffer); + + // Free temporary buffer + gBS->FreePool(TypeBuffer); +} + +#if MEMORY_ERROR_INFO +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: BuildType18 +// +// Description: Build SMBIOS Type 18 +// +// Input: SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, +// EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +BuildType18( + IN SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, + IN EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData +) +{ + SMBIOS_MEMORY_ERROR_INFO *TypeBuffer; + UINT16 bsize; + + // Allocate temporary buffer + TypeBuffer = EfiLibAllocateZeroPool(sizeof(SMBIOS_MEMORY_ERROR_INFO)+0x100); + + // Build header of structure + TypeBuffer->StructureType.Type = 18; // Type 18 + TypeBuffer->StructureType.Length = sizeof(SMBIOS_MEMORY_ERROR_INFO); + TypeBuffer->StructureType.Handle = gSBUpdate->SMBIOS_GetFreeHandle(SmbiosBuffer); + + //Memory.PhysicalMemArray[PMAIdx].ArrayMemoryError.ErrorType = 3; + TypeBuffer->ErrorType = 3; + //Memory.PhysicalMemArray[PMAIdx].ArrayMemoryError.ErrorGranularity = 2; + TypeBuffer->ErrorGranularity = 2; + //Memory.PhysicalMemArray[PMAIdx].ArrayMemoryError.ErrorOperation = 2; + TypeBuffer->ErrorOperation = 2; + //Memory.PhysicalMemArray[PMAIdx].ArrayMemoryError.MemArrayErrorAddress = 0x80000000; + TypeBuffer->MemArrayErrorAddress = 0x80000000; + //Memory.PhysicalMemArray[PMAIdx].ArrayMemoryError.DeviceErrorAddress = 0x80000000; + TypeBuffer->DeviceErrorAddress = 0x80000000; + //Memory.PhysicalMemArray[PMAIdx].ArrayMemoryError.ErrorResolution = 0x80000000; + TypeBuffer->ErrorResolution = 0x80000000; + + // Write structure To SMBIOS Buffer + bsize = SMBIOS_GetStructureTotalSize((UINT8 *)TypeBuffer); + gSBUpdate->SMBIOS_InsertStructure(SmbiosBuffer, (UINT8 *)TypeBuffer, bsize); + + // Fix handle link + SMBIOS_FixHandleLink(SmbiosBuffer); + + // Free temporary buffer + gBS->FreePool(TypeBuffer); + +} +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: BuildType19 +// +// Description: Build SMBIOS Type 19 +// +// +// +// Input: SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, +// EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +BuildType19( + IN SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, + IN EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData +) +{ + SMBIOS_MEM_ARRAY_MAP_ADDR_INFO *TypeBuffer; + UINT16 bsize; + + // Allocate temporary buffer + TypeBuffer = EfiLibAllocateZeroPool(sizeof(SMBIOS_MEM_ARRAY_MAP_ADDR_INFO)+0x100); + + // Build header of structure + TypeBuffer->StructureType.Type = 19; // Type 19 + TypeBuffer->StructureType.Length = sizeof(SMBIOS_MEM_ARRAY_MAP_ADDR_INFO); + TypeBuffer->StructureType.Handle = gSBUpdate->SMBIOS_GetFreeHandle(SmbiosBuffer); + + // Build Content of structure + TypeBuffer->StartingAddress = (UINT32)(MemorySubClassData->ArrayStartAddress.MemoryArrayStartAddress / 1024); + TypeBuffer->EndingAddress = (UINT32)(MemorySubClassData->ArrayStartAddress.MemoryArrayEndAddress / 1024); + TypeBuffer->MemoryArrayHandle = (UINT16)gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 16, 0); + TypeBuffer->PartitionWidth = (UINT8) MemorySubClassData->ArrayStartAddress.MemoryArrayPartitionWidth; + TypeBuffer->ExtendedStartAddr = (MemorySubClassData->ArrayStartAddress.MemoryArrayStartAddress / 1024); + if ((MemorySubClassData->ArrayStartAddress.MemoryArrayEndAddress / 1024) >= 0xFFFFFFFF) + { + TypeBuffer->ExtendedEndAddr = (MemorySubClassData->ArrayStartAddress.MemoryArrayEndAddress / 1024); + TypeBuffer->EndingAddress = 0xFFFFFFFF; + } + else + { + TypeBuffer->ExtendedEndAddr = 0; + } + + // Write structure To SMBIOS Buffer + bsize = SMBIOS_GetStructureTotalSize((UINT8 *)TypeBuffer); + gSBUpdate->SMBIOS_InsertStructure(SmbiosBuffer, (UINT8 *)TypeBuffer, bsize); + + // Fix handle link + SMBIOS_FixHandleLink(SmbiosBuffer); + + // Free temporary buffer + gBS->FreePool(TypeBuffer); + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: BuildType20 +// +// Description: Build SMBIOS Type 20 +// +// Input: SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, +// EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +BuildType20( + IN SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, + IN EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData +) +{ + SMBIOS_MEM_DEV_MAP_ADDR_INFO *TypeBuffer; + UINT16 bsize; + + // Allocate temporary buffer + TypeBuffer = EfiLibAllocateZeroPool(sizeof(SMBIOS_MEM_DEV_MAP_ADDR_INFO)+0x100); + + // Build header of structure + TypeBuffer->StructureType.Type = 20; // Type 20 + TypeBuffer->StructureType.Length = sizeof(SMBIOS_MEM_DEV_MAP_ADDR_INFO); + TypeBuffer->StructureType.Handle = gSBUpdate->SMBIOS_GetFreeHandle(SmbiosBuffer); + + // Build Content of structure + TypeBuffer->StartingAddress = (UINT32)(MemorySubClassData->DeviceStartAddress.MemoryDeviceStartAddress / 1024); + TypeBuffer->EndingAddress = (UINT32)(MemorySubClassData->DeviceStartAddress.MemoryDeviceEndAddress / 1024); + + TypeBuffer->MemoryDeviceHandle = SMBIOS_UNKNOW; + TypeBuffer->MemoryArrayMapAddrHandle = (UINT16)gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 19, 1); + + TypeBuffer->PartitionRowPosition = 0xFF;// unknow type. + //MemorySubClassData->DeviceStartAddress.MemoryDevicePartitionRowPosition; + TypeBuffer->InterleavePosition = 0xFF;// unknow type. + //MemorySubClassData->DeviceStartAddress.MemoryDeviceInterleavePosition; + TypeBuffer->InterleaveDataDepth = 0xFF;// unknow type. + //MemorySubClassData->DeviceStartAddress.MemoryDeviceInterleaveDataDepth; + if ((MemorySubClassData->DeviceStartAddress.MemoryDeviceEndAddress / 1024) >= 0xFFFFFFFF) + { + TypeBuffer->ExtendedEndAddr = (MemorySubClassData->DeviceStartAddress.MemoryDeviceEndAddress / 1024); + TypeBuffer->EndingAddress = 0xFFFFFFFF; + } + else + { + TypeBuffer->ExtendedEndAddr = 0; + } + + // Write structure To SMBIOS Buffer + bsize = SMBIOS_GetStructureTotalSize((UINT8 *)TypeBuffer); + gSBUpdate->SMBIOS_InsertStructure(SmbiosBuffer, (UINT8 *)TypeBuffer, bsize); + + // Fix handle link + SMBIOS_FixHandleLink(SmbiosBuffer); + + // Free temporary buffer + gBS->FreePool(TypeBuffer); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmbiosProcessMemoryDataRecord +// +// Description: +// This function parses the data record and stores it into the Smbios format +// +// Input: EFI_DATA_RECORD_HEADER *Record, +// SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +SmbiosProcessMemoryDataRecord( + IN EFI_DATA_RECORD_HEADER *Record, + IN SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer +) +{ + UINT8 *SrcData; + EFI_SUBCLASS_TYPE1_HEADER *DataHeader; + EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData; + + if (EfiCompareGuid (&Record->DataRecordGuid, &gEfiMemorySubClassGuid)) + { + DEBUG((EFI_D_ERROR, "SMBIOS Memory Record Address:0x%X\n", Record)); + + DataHeader = (EFI_SUBCLASS_TYPE1_HEADER *) (Record + 1); + SrcData = (UINT8 *) (DataHeader + 1); + MemorySubClassData = (EFI_MEMORY_SUBCLASS_RECORDS *) SrcData; + + switch (DataHeader->RecordType) + { + case EFI_MEMORY_ARRAY_LOCATION_RECORD_NUMBER: // 16 + BuildType16(SmbiosBuffer, MemorySubClassData); + break; + case EFI_MEMORY_ARRAY_LINK_RECORD_NUMBER: // 17 + BuildType17(SmbiosBuffer, MemorySubClassData); +#if MEMORY_ERROR_INFO + BuildType18(SmbiosBuffer, MemorySubClassData); // 18 +#endif + // next dimm + DimmNumber ++; + break; + case EFI_MEMORY_ARRAY_START_ADDRESS_RECORD_NUMBER: // 19 + BuildType19(SmbiosBuffer, MemorySubClassData); + break; + case EFI_MEMORY_DEVICE_START_ADDRESS_RECORD_NUMBER: // 20 + BuildType20(SmbiosBuffer, MemorySubClassData); + break; + } + } + + return; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: DynamicUpdateMemoryRecord +// +// Description: Updates Memory related structures (Type 16-20) in +// input Buffer with dynamically detected Record for Intel Tiano +// SmBiosMemory Driver. +// +// Input: UINT8 *Buffer +// +// Output: EFI_STATUS - EFI_SUCCESS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS DynamicUpdateMemoryRecord( + IN SMBIOS_TABLE_ENTRY_POINT *Buffer +) +{ + EFI_STATUS Status; + EFI_HANDLE DataHubHandle; + UINTN HandleSize; + UINT64 MonotonicCount; + EFI_DATA_HUB_PROTOCOL *DataHub; + EFI_DATA_RECORD_HEADER *Record; + EFI_GUID gEfiDataHubProtocolGuid = EFI_DATA_HUB_PROTOCOL_GUID; + UINT8 BitIndex; + + Status = EFI_SUCCESS; + DataHub = NULL; + + // + // Get the SmbusProtocol. + // + Status = gBS->LocateProtocol( &gEfiSmbusProtocolGuid, \ + NULL, \ + &gSmbusProtocol ); + // + // Get the MemInfoHobProtocol. + // + Status = gBS->LocateProtocol (&gMemInfoHobProtocolGuid, \ + NULL, \ + &gMemInfoHobProtocol); + + // + // Get the DxePlatformSaPolicyProtocol. + // + Status = gBS->LocateProtocol (&gDxePlatformSaPolicyGuid, \ + NULL, \ + &gDxePlatformSaPolicy); + if (EFI_ERROR (Status)) return Status; + + // Check User Dimm Map + for (BitIndex = 0; BitIndex < 2; BitIndex++) { + if (!((gDxePlatformSaPolicy->MemoryConfig->ChannelASlotMap >> BitIndex) & BIT0)) { + DimmSlot[BitIndex] = 0; //if not, Clear Spd sddress; + } + if (!((gDxePlatformSaPolicy->MemoryConfig->ChannelBSlotMap >> BitIndex) & BIT0)) { + DimmSlot[BitIndex + 2] = 0; //if not, Clear Spd sddress; + } + } + + // + // Get the Data Hub Protocol. Assume only one instance + // of Data Hub Protocol is availabe in the system. + // + HandleSize = sizeof (EFI_HANDLE); + + Status = gBS->LocateHandle ( + ByProtocol, + &gEfiDataHubProtocolGuid, + NULL, + &HandleSize, + &DataHubHandle + ); + + if (EFI_ERROR (Status)) + { + return EFI_SUCCESS; + } + Status = gBS->HandleProtocol ( + DataHubHandle, + &gEfiDataHubProtocolGuid, + &DataHub + ); + + if (EFI_ERROR (Status)) + { + return EFI_SUCCESS; + } +#if defined (MEMORY_DEVICE_INFO) && MEMORY_DEVICE_INFO == 1 + // Clean strcutures which need rebuild + SMBIOS_DeleteStructureByType(Buffer, 16, SMBIOS_FOR_ALL); + SMBIOS_DeleteStructureByType(Buffer, 17, SMBIOS_FOR_ALL); +#if defined (MEMORY_ERROR_INFO) && MEMORY_ERROR_INFO == 1 + SMBIOS_DeleteStructureByType(Buffer, 18, SMBIOS_FOR_ALL); +#endif + SMBIOS_DeleteStructureByType(Buffer, 19, SMBIOS_FOR_ALL); + SMBIOS_DeleteStructureByType(Buffer, 20, SMBIOS_FOR_ALL); +#endif + // + // Get all available data records from data hub + // + MonotonicCount = 0; + Record = NULL; + + do { + Status = DataHub->GetNextRecord ( + DataHub, + &MonotonicCount, + NULL, + &Record + ); + + if (!EFI_ERROR (Status)) + { + if (Record->DataRecordClass == EFI_DATA_RECORD_CLASS_DATA) + { + SmbiosProcessMemoryDataRecord (Record, Buffer); + } + } + } while (!EFI_ERROR (Status) && (MonotonicCount != 0)); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SMIBiosUpdateMemoryRecordDriverEntryPoint +// +// Description: Update memory record DXE driver for Intel Tiano SmBiosMemory Driver. +// +// Input: ImageHandle - Image handle. +// SystemTable - Pointer to the system table. +// +// Output: EFI_STATUS - EFI_SUCCESS. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS SMIBiosUpdateMemoryRecordDriverEntryPoint( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status; + EFI_GUID gEfiSmbiosProtocolGuid = EFI_SMBIOS_PROTOCOL_GUID; + SMBIOS_TABLE_ENTRY_POINT *SmbiosTableEntryPoint; + + DxeInitializeDriverLib (ImageHandle, SystemTable); + Status = gBS->LocateProtocol(&gEfiSmbiosUpdateDataProtocolGuid, NULL, &gSBUpdate); + ASSERT_EFI_ERROR(Status); + + Status = gBS->LocateProtocol(&gEfiSmbiosProtocolGuid, NULL, &gSmbiosProtocol); + ASSERT_EFI_ERROR(Status); + SmbiosTableEntryPoint = gSmbiosProtocol->SmbiosGetTableEntryPoint(); + + Status = DynamicUpdateMemoryRecord(SmbiosTableEntryPoint); + ASSERT_EFI_ERROR(Status); + + return EFI_SUCCESS; +} + +//----------------------------------------------------------------------------- +// SMBIOS Dynamic Maintain Functions +//----------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SMBIOS_DeleteStructureByType +// +// Description: SMBIOS Delete Structure Type +// +// Input: SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, +// UINT8 Type, +// UINT8 Index +// +// Output: UINTN count +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINTN +SMBIOS_DeleteStructureByType( + IN SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, + IN UINT8 Type, + IN UINT8 Index +) +{ + UINT8 i; + UINT16 handle; + UINTN count; + + count = 0; + if (Index != SMBIOS_FOR_ALL) + { // for Single + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, Type, Index); + if (handle != SMBIOS_NOT_FOUND) + { + gSBUpdate->SMBIOS_DeleteStructure(SmbiosBuffer, handle); + } + } else { // -1 for ALL + for(i = 0; i < MAX_HANDLES; i++) + { + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, Type, 1); + if (handle != SMBIOS_NOT_FOUND) + { + gSBUpdate->SMBIOS_DeleteStructure(SmbiosBuffer, handle); + count++; + } + } + } + + return count; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SMBIOS_GetStructureTotalSize +// +// Description: SMBIOS get structure total size +// +// Input: UINT8 *BufferStart +// +// Output: UINT16 Total Size. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT16 +SMBIOS_GetStructureTotalSize( + IN UINT8 *BufferStart +) +{ + UINT8 *BufferEnd; + + BufferEnd = BufferStart; + BufferEnd += ((SMBIOS_STRUCTURE_HEADER*)BufferStart)->Length; + while (*(UINT16*)BufferEnd != 0) + { + BufferEnd++; + } + + return (UINT16)(BufferEnd + 2 - BufferStart); // +2 for double zero terminator +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SMBIOS_GetStringBase +// +// Description: SMBIOS get String Base +// +// Input: UINT8 *Buffer +// +// Output: UINT8 Buffer +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8* SMBIOS_GetStringBase( + IN UINT8 *Buffer +) +{ + SMBIOS_STRUCTURE_HEADER *p; + + p = (SMBIOS_STRUCTURE_HEADER *)Buffer; + Buffer += p->Length; + + return Buffer; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SMBIOS_NextString +// +// Description: SMBIOS next String +// +// Input: UINT8 *String +// +// Output: String point. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8* SMBIOS_NextString( + IN UINT8 *String +) +{ + return String+(EfiAsciiStrLen(String)+1); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SMBIOS_FindString +// +// Description: SMBIOS find String +// +// Input: CHAR8 *Buffer +// CHAR8 *String +// +// Output: String point. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8 +SMBIOS_FindString( + IN CHAR8 *Buffer, + IN CHAR8 *String +) +{ + CHAR8 *sp; + UINT8 i; + UINTN quit; + UINTN l; + + quit = 0; + i = 1; + sp = SMBIOS_GetStringBase(Buffer); + while (quit == 0) + { + l = EfiAsciiStrLen(sp); + if (l == 0) + { + i = 0xFF; + quit = 1; + } else if (EfiAsciiStrCmp(String, sp) == 0) + { + quit = 1; + } else { + sp = SMBIOS_NextString(sp); + i++; + } + } + + return i; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SMBIOS_AddString +// +// Description: SMBIOS add String +// +// Input: CHAR8 *Buffer +// CHAR8 *String +// +// Output: UINT8 +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8 +SMBIOS_AddString( + IN CHAR8 *Buffer, + IN CHAR8 *String +) +{ + CHAR8 *sp; + UINT8 i; + UINTN l; + + if (EfiAsciiStrLen(String) == 0) + { + EfiAsciiStrCpy(String, "[Empty]"); + } + + i = 1; + sp = SMBIOS_GetStringBase(Buffer); + while ((l = EfiAsciiStrLen(sp)) != 0) + { + sp = sp + (l+1); + i++; + } + + EfiAsciiStrCpy(sp, String); + sp = SMBIOS_NextString(sp); + *sp = 0; + + return i; + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SMBIOS_FixHandleLink +// +// Description: SMBIOS fix handle link +// +// Input: SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer +// +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +SMBIOS_FixHandleLink( + IN SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer +) +{ + UINT16 handle; + SMBIOS_PHYSICAL_MEM_ARRAY_INFO *T16_p; + SMBIOS_MEMORY_DEVICE_INFO *T17_p; + SMBIOS_MEM_ARRAY_MAP_ADDR_INFO *T19_p; + SMBIOS_MEM_DEV_MAP_ADDR_INFO *T20_p; + UINT16 T19_Handle; + UINT16 T17_Size_KB; + UINT16 T20_Size_KB; + UINTN Q_flag; + UINT8 i, j; +#if MEMORY_ERROR_INFO + SMBIOS_MEMORY_ERROR_INFO *T18_p = NULL; +#endif + + T16_p = NULL; + T17_p = NULL; + T19_p = NULL; + T20_p = NULL; + T19_Handle = SMBIOS_UNKNOW; + Q_flag = 0; + T17_Size_KB = 0; + + // Looking for Type 19 to set MemoryArrayHandle + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 19, 1); + if (handle != SMBIOS_NOT_FOUND) + { + T19_p = (SMBIOS_MEM_ARRAY_MAP_ADDR_INFO *)gSBUpdate->SMBIOS_GetStructureBase(SmbiosBuffer, handle); + T19_Handle = T19_p->StructureType.Handle; + if (T19_p->MemoryArrayHandle == SMBIOS_UNKNOW) + { + // Looking for Type 16 + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 16, 1); + if (handle != SMBIOS_NOT_FOUND) + { + T16_p = (SMBIOS_PHYSICAL_MEM_ARRAY_INFO *)gSBUpdate->SMBIOS_GetStructureBase(SmbiosBuffer, handle); + T19_p->MemoryArrayHandle = T16_p->StructureType.Handle; + } + } + } + +#if MEMORY_ERROR_INFO + // Looking for Type 16 + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 16, 1); + if (handle != SMBIOS_NOT_FOUND) + { + T16_p = (SMBIOS_PHYSICAL_MEM_ARRAY_INFO *)gSBUpdate->SMBIOS_GetStructureBase(SmbiosBuffer, handle); + if (T16_p->MemErrInfoHandle == SMBIOS_UNKNOW) + { + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 18, 1); + if (handle != SMBIOS_NOT_FOUND) + { + T18_p = (SMBIOS_MEMORY_ERROR_INFO *)gSBUpdate->SMBIOS_GetStructureBase(SmbiosBuffer, handle); + T16_p->MemErrInfoHandle = T18_p->StructureType.Handle; + } + } + } + + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 17, 1); + if (handle != SMBIOS_NOT_FOUND) + { + T17_p = (SMBIOS_MEMORY_DEVICE_INFO *)gSBUpdate->SMBIOS_GetStructureBase(SmbiosBuffer, handle); + if (T17_p->MemErrorInfoHandle == SMBIOS_UNKNOW) + { + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 18, 2); + if (handle != SMBIOS_NOT_FOUND) + { + T18_p = (SMBIOS_MEMORY_ERROR_INFO *)gSBUpdate->SMBIOS_GetStructureBase(SmbiosBuffer, handle); + T17_p->MemErrorInfoHandle = T18_p->StructureType.Handle; + } + } + } + + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 17, 3); + if (handle != SMBIOS_NOT_FOUND) + { + T17_p = (SMBIOS_MEMORY_DEVICE_INFO *)gSBUpdate->SMBIOS_GetStructureBase(SmbiosBuffer, handle); + if (T17_p->MemErrorInfoHandle == SMBIOS_UNKNOW) + { + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 18, 3); + if (handle != SMBIOS_NOT_FOUND) + { + T18_p = (SMBIOS_MEMORY_ERROR_INFO *)gSBUpdate->SMBIOS_GetStructureBase(SmbiosBuffer, handle); + T17_p->MemErrorInfoHandle = T18_p->StructureType.Handle; + } + } + } +#endif + + Q_flag = 0; + // Looking for Type 20 to set MemoryArrayMapAddrHandle and MemoryDeviceHandle + for(i = 1; i < MAX_HANDLES; i++) + { + T20_Size_KB = 0; + + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 20, i); + if (handle != SMBIOS_NOT_FOUND) + { + T20_p = (SMBIOS_MEM_DEV_MAP_ADDR_INFO *)gSBUpdate->SMBIOS_GetStructureBase(SmbiosBuffer, handle); + T20_p->MemoryArrayMapAddrHandle = T19_Handle; + if (T20_p->MemoryDeviceHandle == SMBIOS_UNKNOW) + { + T20_Size_KB =(UINT16) T20_p->EndingAddress + 1; + + // Looking for Type 17 + for(j = i; j < MAX_HANDLES; j++) + { + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 17, j); + if (handle != SMBIOS_NOT_FOUND) + { + T17_p = (SMBIOS_MEMORY_DEVICE_INFO *)gSBUpdate->SMBIOS_GetStructureBase(SmbiosBuffer, handle); + + T17_Size_KB = (T17_p->Size & 0x7FFF) * ((T17_p->Size & 0x8000) ? 1 : 1024); + if (T17_Size_KB == T20_Size_KB) + { + T20_p->MemoryDeviceHandle = T17_p->StructureType.Handle; + } + } + } + } + Q_flag++; + } + + if (Q_flag == 0) + break; + } +} + +#if (EFI_SPECIFICATION_VERSION < 0x0002000A) +//----------------------------------------------------------------------------- +// HII Functions +//----------------------------------------------------------------------------- +EFI_HII_HANDLE HiiHandle; +EFI_HII_PROTOCOL *Hii = NULL; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: InitHiiString +// +// Description: Init Hii string +// +// Input: VOID +// +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +InitHiiString(VOID) +{ + EFI_STATUS Status; + UINT16 HandleBufferLength; + EFI_HII_HANDLE *HiiHandleBuffer; + UINTN NumberOfHiiHandles; + UINTN Index; + UINT16 Length; + EFI_GUID HiiGuid; + + if (Hii == NULL) + { + HandleBufferLength = 0x1000; + HiiHandleBuffer = NULL; + HiiHandle = 0; + + // + // Locate HII protocol + // + Status = gBS->LocateProtocol (&gEfiHiiProtocolGuid, NULL, &Hii); + ASSERT_EFI_ERROR (Status); + + HiiHandleBuffer = EfiLibAllocateZeroPool (HandleBufferLength); + + Status = Hii->FindHandles (Hii, &HandleBufferLength, HiiHandleBuffer); + ASSERT_EFI_ERROR (Status); + + // + // Get the Hii Handle that matches the StructureNode->ProducerName + // + NumberOfHiiHandles = HandleBufferLength / sizeof (EFI_HII_HANDLE); + for (Index = 0; Index < NumberOfHiiHandles; Index++) + { + Length = 0; + Status = ExtractDataFromHiiHandle ( + HiiHandleBuffer[Index], + &Length, + NULL, + &HiiGuid + ); + if (EfiCompareGuid (&gEfiMemorySubClassDriverGuid, &HiiGuid)) + { + HiiHandle = HiiHandleBuffer[Index]; + break; + } + } + gBS->FreePool (HiiHandleBuffer); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: HiiGetString +// +// Description: Init get string +// +// Input: STRING_REF Token +// +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +CHAR16 * +HiiGetString( + IN STRING_REF Token +) +{ + UINTN StringBufferLength; + CHAR16 *StringBuffer; + EFI_STATUS Status; + + InitHiiString(); + + Status = EFI_SUCCESS; + StringBufferLength = 0x100; + StringBuffer = EfiLibAllocateZeroPool(StringBufferLength); + ASSERT(StringBuffer); + + // + // Find the string based on the current language + // + Status = Hii->GetString ( + Hii, + HiiHandle, + Token, + FALSE, + NULL, + &StringBufferLength, + StringBuffer + ); + + if (EFI_ERROR (Status)) + { + gBS->FreePool(StringBuffer); + StringBuffer = NULL; + } + + return StringBuffer; +} +#endif //EFI_SPECIFICATION_VERSION < 0x0002000A + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ConvertChar16ToChar8 +// +// Description: Convert char 16 to char 8 +// +// Input: CHAR8 *Dest +// CHAR16 *Src +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +ConvertChar16ToChar8 ( + IN CHAR8 *Dest, + IN CHAR16 *Src +) +{ + while (*Src) + { + *Dest++ = (UINT8) (*Src++); + } + + *Dest = 0; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: TransferHiiStringToSmbios +// +// Description: Transfer Hii string to Smbios +// +// Input: CHAR8 *Structure +// STRING_REF Token +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8 +TransferHiiStringToSmbios ( + IN UINT8 *Structure, + IN STRING_REF Token +) +{ + CHAR8 *Buffer; + UINTN BufferSize; + UINT8 i; + CHAR16 *String; + +#if (EFI_SPECIFICATION_VERSION >= 0x0002000A) + EFI_STATUS Status; +#endif + + BufferSize = 0x100; + Buffer = EfiLibAllocateZeroPool(BufferSize); + ASSERT(Buffer); + i = (UINT8) -1; + +#if (EFI_SPECIFICATION_VERSION < 0x0002000A) + String = HiiGetString(Token); +#else + + Status = GetStringFromToken (&gEfiMemorySubClassDriverGuid, Token, (EFI_STRING *)&String); + ASSERT_EFI_ERROR(Status); + +#endif + + ConvertChar16ToChar8(Buffer, String); + + i = SMBIOS_AddString(Structure, Buffer); + gBS->FreePool(String); + gBS->FreePool(Buffer); + return i; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.cif b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.cif new file mode 100644 index 0000000..e0e556e --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.cif @@ -0,0 +1,12 @@ +<component> + name = "UpdateMemoryRecord" + category = ModulePart + LocalRoot = "Chipset\NB\SystemAgentWrap\UpdateMemoryRecord" + RefName = "UpdateMemoryRecord" +[files] +"UpdateMemoryRecord.sdl" +"UpdateMemoryRecord.mak" +"UpdateMemoryRecord.dxs" +"UpdateMemoryRecord.c" +"UpdateMemoryRecord.h" +<endComponent> diff --git a/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.dxs b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.dxs new file mode 100644 index 0000000..fe4a9cb --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.dxs @@ -0,0 +1,86 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.dxs 2 8/31/12 2:38a Yurenlai $ +// +// $Revision: 2 $ +// +// $Date: 8/31/12 2:38a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.dxs $ +// +// 2 8/31/12 2:38a Yurenlai +// [TAG] EIP99526 +// [Category] Improvement +// [Severity] Important +// [Description] Fixed system hang at CKP 0x6A if +// PI_SPECIFICATION_VERSION = 0x10000. +// [Files] UpdateMemoryRecord.dxs +// +// 1 2/08/12 4:37a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* + +#if (PI_SPECIFICATION_VERSION < 0x10014) +#include <Token.h> +#include <protocol\SmbiosGetFlashDataProtocol.h> +#define __AMIHOBS_H__ +#include <protocol\SmbiosDynamicData.h> +#include <Protocol\Datahub.h> +#if (EFI_SPECIFICATION_VERSION >= 0x0002000A) +#include <Protocol/HiiDatabase.h> +#else +#include <Protocol/HII.h> +#endif +#define __EFI__H__ +#include <Protocol\Smbus.h> +#include <SmbiosUpdateDataProtocol.h> +#include <SaInfo\SaInfo.h> + +DEPENDENCY_START + EFI_SMBIOS_BOARD_PROTOCOL_GUID AND + EFI_DATA_HUB_PROTOCOL_GUID AND +#if (EFI_SPECIFICATION_VERSION >= 0x0002000A) + EFI_HII_DATABASE_PROTOCOL_GUID AND +#else + EFI_HII_PROTOCOL_GUID AND +#endif + EFI_SA_INFO_PROTOCOL_GUID AND + EFI_SMBUS_HC_PROTOCOL_GUID AND + EFI_SMBIOS_PROTOCOL_GUID AND + EFI_SMBIOS_UPDATE_DATA_PROTOCOL_GUID +DEPENDENCY_END +#else +DEPENDENCY_START + AFTER {0xEDA39402, 0xF375, 0x4496, 0x92, 0xD3, 0x83, 0xB4, 0x3C, 0xB8, 0xA7, 0x6A} +DEPENDENCY_END +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//*************************************************************************
\ No newline at end of file diff --git a/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.h b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.h new file mode 100644 index 0000000..254f132 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.h @@ -0,0 +1,108 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.h 1 2/08/12 4:37a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 4:37a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.h $ +// +// 1 2/08/12 4:37a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: UpdateMemoryRecord.h +// +// Description: +// +//<AMI_FHDR_END> +//********************************************************************** +#ifndef __UPDATE_MEMORY_RECORD_H__ +#define __UPDATE_MEMORY_RECORD_H__ + +#include <Tiano.h> +#include <Protocol\SMBios.h> +#include <Protocol\SmbiosGetFlashDataProtocol.h> +#include "EfiDriverLib.h" +#include "Guid\DataHubRecords\DataHubSubClassMemory.h" +#include "SmbiosUpdateDataProtocol.h" + +#if (EFI_SPECIFICATION_VERSION >= 0x0002000A) +#include "UefiIfrLibrary.h" +#include EFI_PROTOCOL_DEPENDENCY (HiiDatabase) +#include EFI_PROTOCOL_DEPENDENCY (HiiString) +#else +#include "Library\Dxe\EfiIfrSupportLib\IfrLibrary.h" +#include EFI_PROTOCOL_DEPENDENCY (Hii) +#endif + +#define SMBIOS_NOT_FOUND 0xFFFF +#define SMBIOS_UNKNOW 0xFFFF +#define SMBIOS_NOT_PROVIDE 0xFFFE +#define MAX_HANDLES 0x10 +#define SMBIOS_FOR_ALL 0xFF + +VOID +SMBIOS_FixHandleLink( + IN SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer +); + +EFI_STATUS +ExtractDataFromHiiHandle ( + IN EFI_HII_HANDLE HiiHandle, + IN OUT UINT16 *ImageLength, + OUT UINT8 *DefaultImage, + OUT EFI_GUID *Guid +); + + +UINT8 +TransferHiiStringToSmbios ( + IN UINT8 *Structure, + IN STRING_REF Token +); + +UINT16 +SMBIOS_GetStructureTotalSize( + IN UINT8 *BufferStart +); + +UINTN +SMBIOS_DeleteStructureByType ( + SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, + UINT8 Type, + UINT8 Index +); + +#endif +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//*************************************************************************
\ No newline at end of file diff --git a/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.mak b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.mak new file mode 100644 index 0000000..df6ad4a --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.mak @@ -0,0 +1,44 @@ +# /*++ +# Copyright (c) 2011 Intel Corporation. All rights reserved. +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# --*/ +all : UpdateMemoryRecord + +UpdateMemoryRecord : $(BUILD_DIR)\UpdateMemoryRecord.mak UpdateMemoryRecordBin + +$(BUILD_DIR)\UpdateMemoryRecord.mak : $(UpdateMemroyRecord_DIR)\UpdateMemoryRecord.CIF $(UpdateMemroyRecord_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(UpdateMemroyRecord_DIR)\UpdateMemoryRecord.CIF $(CIF2MAK_DEFAULTS) + +MemoryRecord_INCLUDES = \ + $(EDK_INCLUDES)\ + $(INTEL_MCH_INCLUDES) \ + /I$(SMBIOSUpdateData_DIR)\ + /I$(UefiEfiIfrSupportLib_DIR)\ + /I$(PROJECT_DIR)\ + /IInclude\ + +MemoryRecord_LIB_LINKS =\ + $(EFIDRIVERLIB)\ +!IF $(EFI_SPECIFICATION_VERSION) >= 0x2000A + $(UEFIEFIIFRSUPPORTLIB) +!ELSE + $(EFIIFRSUPPORTLIB)\ +!ENDIF + +UpdateMemoryRecordBin : $(MemoryRecord_LIB_LINKS) + $(MAKE) /$(MAKEFLAGS) $(EDK_DEFAULTS)\ + /f $(BUILD_DIR)\UpdateMemoryRecord.mak all\ + NAME=UpdateMemoryRecord\ + "MY_INCLUDES=$(MemoryRecord_INCLUDES)"\ + GUID=24CCD374-3DF6-4181-86F6-E3C66920A145\ + ENTRY_POINT=SMIBiosUpdateMemoryRecordDriverEntryPoint\ + DEPEX1=$(UpdateMemroyRecord_DIR)\UpdateMemoryRecord.dxs \ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + TYPE=BS_DRIVER\ + COMPRESS=1\ diff --git a/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.sdl b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.sdl new file mode 100644 index 0000000..8accc20 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.sdl @@ -0,0 +1,69 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.sdl 1 2/08/12 4:37a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 4:37a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.sdl $ +# +# 1 2/08/12 4:37a Yurenlai +# Intel Haswell/NB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "UpdateMemoryRecord_SUPPORT" + Value = "1" + Help = "Main switch to enable UpdateMemoryRecord support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Token = "SMBIOS_MEMORY_SUPPORT" "=" "1" + Token = "SMBIOS_SUPPORT" "=" "1" +End + +PATH + Name = "UpdateMemroyRecord_DIR" +End + +MODULE + Help = "Includes UpdateMemoryRecord.mak to Project" + File = "UpdateMemoryRecord.mak" +End + +ELINK + Name = "$(BUILD_DIR)\UpdateMemoryRecord.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Chipset/NB/hsw_VBios.dat b/Chipset/NB/hsw_VBios.dat Binary files differnew file mode 100644 index 0000000..1e23bf1 --- /dev/null +++ b/Chipset/NB/hsw_VBios.dat diff --git a/Chipset/SB/AcpiModeEnable.c b/Chipset/SB/AcpiModeEnable.c new file mode 100644 index 0000000..618f9c8 --- /dev/null +++ b/Chipset/SB/AcpiModeEnable.c @@ -0,0 +1,959 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/AcpiModeEnable/AcpiModeEnable.c 17 5/23/13 1:57a Scottyang $ +// +// $Revision: 17 $ +// +// $Date: 5/23/13 1:57a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/AcpiModeEnable/AcpiModeEnable.c $ +// +// 17 5/23/13 1:57a Scottyang +// [TAG] EIP120623 +// [Category] Improvement +// [Description] LCD turn on automatically when resume from S3. +// [Files] SBPEI.c, SBDxe.c, AcpiModeEnable.c +// +// 16 5/09/13 6:32a Scottyang +// [TAG] None +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] S3 resume Verb table will error when enable token +// "AMI_INIT_VERB_TABLE_IN_S3". +// [RootCause] The FrontPanel is wrong. +// [Solution] Change FrontPanel to frontSideNo. +// [Files] AcpiModeEnable.c +// +// 15 4/23/13 4:20a Wesleychen +// [TAG] None +// [Category] Improvement +// [Description] Add token "ONLY_CLEAR_RTC_EN_IN_PEI" for improve +// "EIP120623". +// [Files] AcpiModeEnable.c; SB.SDL; SBPEI.c +// +// 14 4/18/13 12:17a Wesleychen +// [TAG] EIP120623 +// [Category] Bug Fix +// [Severity] Important +// [Symptom] LCD doesn't turn on automatically when resume from S3. +// [RootCause] PM1_STS (PMBASE+00h) are cleared in EnableAcpiMode(). +// [Solution] Avoid PM1_STS clearing behavior is occurring in S3 +// resuming. +// *AcpiModeEnable.c Rev#8~11(EIP101628 & EIP118531) are are +// no need be existence. +// [Files] SBPEI.c; AcpiModeEnable.c +// +// 12 4/08/13 2:27a Wesleychen +// Revise the content of history. +// +// 7 10/12/12 2:08a Scottyang +// [TAG] EIP76432 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] It will BSOD ,while system boot to OS at "starting windows" +// press the KB in succession. +// [RootCause] System BSOD is caused by a large number of SMI generated. +// [Solution] Disable legacy USB SMI in ACPI enable stage. +// [Files] AcpiModeEnable.c; SBDXE.c +// +// 6 10/01/12 5:51a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update EIP#102349 "GPE0 setting and SCI routing for ULT +// platfoem". +// [Files] AcpiModeEnable.c, AcpiModeEnable.sdl +// +// 5 9/26/12 3:57a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Fixed RTC on iFFS failed. +// [Files] AcpiModeEnable.c +// +// 4 9/12/12 5:16a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Modify for ULT GPIO changed by PCH LPT-LP EDS 1.0. +// [Files] SB.H, SB.sdl, AcpiModeEnable.c, AcpiModeEnable.sdl, +// SBPEI.c +// +// 3 7/27/12 6:16a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update to support ULT Platform. +// [Files] SB.H, SB.mak, SB.sdl, SB.sd, SBSetup.c, +// AcpiModeEnable.c, SBDxe.c, SBPEI.c, SBSMI.c, SleepSmi.c, +// SmiHandlerPorting.c, SmiHandlerPorting2.c, SBPPI.h, Pch.sdl +// +// 2 4/25/12 9:25a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Apply AcpiModeEnable support PI 1.2. +// [Files] AcpiModeEnable.c +// +// 1 2/08/12 8:30a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: AcpiModeEnable.C +// +// Description: Provide functions to enable and disable ACPI mode +// +//<AMI_FHDR_END> +//************************************************************************* + +//--------------------------------------------------------------------------- +// Include(s) +//--------------------------------------------------------------------------- +#include <Token.h> +#include <AmiDxeLib.h> + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION>=0x4028B) +#include <Protocol\SmmBase2.h> +#include <Protocol\SmmSwDispatch2.h> +#else +#include <Protocol\SmmBase.h> +#include <Protocol\SmmSwDispatch.h> +#endif + +#include <Protocol\DevicePath.h> +#include <Token.h> +#include <AmiCspLib.h> +#include <PchAccess.h> +#include "RTC.h" +#include "HDAVBTBL.h" +#include "AcpiModeEnable.h" + +#if defined(PchDxePlatformPolicy_SUPPORT) && PchDxePlatformPolicy_SUPPORT +#include <PchDxePlatformPolicy.h> +#endif // PchDxePlatformPolicy_SUPPORT end + +//--------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//--------------------------------------------------------------------------- +// Constant Definition(s) + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) +#define AMI_SMM_SW_DISPATCH_PROTOCOL EFI_SMM_SW_DISPATCH2_PROTOCOL +#define AMI_SMM_SW_DISPATCH_CONTEXT EFI_SMM_SW_REGISTER_CONTEXT +#define SMM_CHILD_DISPATCH_SUCCESS EFI_SUCCESS +#else +#define AMI_SMM_SW_DISPATCH_PROTOCOL EFI_SMM_SW_DISPATCH_PROTOCOL +#define AMI_SMM_SW_DISPATCH_CONTEXT EFI_SMM_SW_DISPATCH_CONTEXT +#define SMM_CHILD_DISPATCH_SUCCESS +#endif + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) +VOID InitParts ( + IN VOID* DispatchHandle, + IN CONST VOID *DispatchContext +); + +VOID InitParts2 ( + IN VOID* DispatchHandle, + IN CONST VOID *DispatchContext +); + +//--------------------------------------------------------------------------- +// Variable and External Declaration(s) +//--------------------------------------------------------------------------- +// Variable Declaration(s) + +ACPI_DISPATCH_LINK *gAcpiEnDispatchHead = 0, *gAcpiEnDispatchTail = 0; +ACPI_DISPATCH_LINK *gAcpiDisDispatchHead = 0, *gAcpiDisDispatchTail = 0; + +UINT8 gFirstInFlag = 0; +UINT16 wPM1_SaveState; +UINT32 dGPE_SaveState; +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) +EFI_SMM_BASE2_PROTOCOL *gSmmBase2; +#endif + +// GUID Definition(s) + +EFI_GUID gEfiAcpiEnDispatchProtocolGuid = EFI_ACPI_EN_DISPATCH_PROTOCOL_GUID; +EFI_GUID gEfiAcpiDisDispatchProtocolGuid = EFI_ACPI_DIS_DISPATCH_PROTOCOL_GUID; + +// Protocol Definition(s) + +// External Declaration(s) + +// Function Definition(s) +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbGpioSciInit +// +// Description: Programming the corresponding GPIO pin to generate SCI#. +// +// Input: None +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID SbGpioSciInit (VOID) +{ + UINT32 GpioRoute; + UINT8 GpioIndex; + UINT32 GpioSmiEnable; + UINT32 GpioNmiEnable; + + if (GetPchSeries() == PchLp) { + GpioRoute = READ_IO32(GPIO_BASE_ADDRESS+GP_IOREG_GPI_ROUT2); + GpioSmiEnable = READ_IO32(GPIO_BASE_ADDRESS+GP_IOREG_ALTGP_SMI_EN); + GpioNmiEnable = READ_IO32(GPIO_BASE_ADDRESS+GP_IOREG_PCHLP_GPI_NMI_EN); + + GpioRoute &= ~GPIO_SCI_BITMAP; + GpioSmiEnable &= ~GPIO_SCI_BITMAP; + GpioNmiEnable &= ~GPIO_SCI_BITMAP; + + WRITE_IO16(GPIO_BASE_ADDRESS+GP_IOREG_GPI_ROUT2, GpioRoute); + WRITE_IO16(GPIO_BASE_ADDRESS+GP_IOREG_ALTGP_SMI_EN, GpioSmiEnable); + WRITE_IO16(GPIO_BASE_ADDRESS+GP_IOREG_PCHLP_GPI_NMI_EN, GpioNmiEnable); + } else { + GpioRoute = READ_PCI32_SB(R_PCH_LPC_GPI_ROUT); + for (GpioIndex = 0; GpioIndex < 16; GpioIndex++) { + if (GPIO_SCI_BITMAP & (UINT16)(1 << GpioIndex)) { + GpioRoute &= ~(3 << (GpioIndex * 2)); + GpioRoute |= (2 << (GpioIndex * 2)); + } + } + WRITE_PCI32_SB(R_PCH_LPC_GPI_ROUT, GpioRoute); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EnableAcpiMode +// +// Description: This function enable ACPI mode by clearing all SMI and +// enabling SCI generation +// This routine is also called on a S3 resume for special ACPI +// programming. +// Status should not be cleared on S3 resume. Enables are +// already taken care of. +// +// Input: PI 0.91, 1.0 +// DispatchHandle - SMI dispatcher handle +// *DispatchContext - Pointer to the dispatch context +// PI 1.1, 1.2 +// DispatchHandle - SMI dispatcher handle +// *DispatchContext- Points to an optional S/W SMI context +// CommBuffer - Points to the optional communication +// buffer +// CommBufferSize - Points to the size of the optional +// communication buffer +// +// Output: EFI_STATUS if the new SMM PI is applied. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) +EFI_STATUS EnableAcpiMode ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *DispatchContext OPTIONAL, + IN OUT VOID *CommBuffer OPTIONAL, + IN OUT UINTN *CommBufferSize OPTIONAL ) +#else +VOID EnableAcpiMode ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext ) +#endif +{ + + ACPI_DISPATCH_LINK *Link; + UINT16 wordValue; + UINT32 dwordValue; + PCH_SERIES PchSeries = GetPchSeries(); + +#if defined EMUL6064_SUPPORT && EMUL6064_SUPPORT == 1 + if (READ_PCI8_SB(R_PCH_LPC_ULKMC)) // 0x94 + WRITE_PCI8_SB(R_PCH_LPC_ULKMC, 0); // 0x94 +#endif + + if ( gFirstInFlag == 0 ) { + gFirstInFlag = 1; + + // Check if WAK bit is set, if yes skip clearing status + wordValue = READ_IO16_PM(ACPI_IOREG_PM1_STS); // 0x00 + if (wordValue & B_PCH_ACPI_PM1_STS_WAK) { + // NAPA-CHANGES Disable and Clear GPE0 Sources + if (PchSeries == PchLp) { + WRITE_IO32_PM(ACPI_PCHLP_IOREG_GPE0_EN+0x0c, 0x0000); //GPE0_EN 0x9C + WRITE_IO32_PM(ACPI_PCHLP_IOREG_GPE0_STS+0x0c, 0xffffffff); //GPE0_STS 0x8C + } else { + WRITE_IO32_PM(ACPI_IOREG_GPE0_EN, 0x0000); //GPE0_EN 0x28 + WRITE_IO32_PM(ACPI_IOREG_GPE0_STS, 0xffffffff); //GPE0_STS 0x20 + } + } else { + //Disable SMI Sources + dwordValue = READ_IO32_PM(ACPI_IOREG_SMI_EN); //SMI_EN (SMI Control and Enable register.) + + dwordValue &= ~(B_PCH_SMI_EN_ON_SLP_EN | B_PCH_SMI_EN_SWSMI_TMR); // Clear SLP_SMI_EN and SWSMI_TMR bit. + + // [EIP76432]>> +#if defined EMUL6064_SUPPORT && EMUL6064_SUPPORT == 1 + dwordValue &= ~(B_PCH_SMI_EN_LEGACY_USB); +#endif + // <<[EIP76432] + + WRITE_IO32_PM(ACPI_IOREG_SMI_EN, dwordValue); + + //Disable and Clear PM1 Sources except power button + wPM1_SaveState = READ_IO16_PM(ACPI_IOREG_PM1_EN); //PM1_EN + WRITE_IO16_PM(ACPI_IOREG_PM1_EN, (UINT16)B_PCH_ACPI_PM1_EN_PWRBTN); //PM1_EN Bit 8: PWRBTN_EN + WRITE_IO16_PM(ACPI_IOREG_PM1_STS, 0xffff); //PM1_STS 0x00 + + //Disable and Clear GPE0 Sources + if (PchSeries == PchLp) { + dGPE_SaveState = READ_IO16_PM(ACPI_PCHLP_IOREG_GPE0_EN+0x0c);//GPE0_EN 0x9C + WRITE_IO32_PM(ACPI_PCHLP_IOREG_GPE0_EN+0x0c, 0x00000000); //GPE0_EN 0x9C + WRITE_IO32_PM(ACPI_PCHLP_IOREG_GPE0_STS+0x0c, 0xffffffff); //GPE0_STS 0x8C + } else { + dGPE_SaveState = READ_IO16_PM(ACPI_IOREG_GPE0_EN);//GPE0_EN 0x28 + WRITE_IO32_PM(ACPI_IOREG_GPE0_EN, 0x00000000); //GPE0_EN 0x28 + WRITE_IO32_PM(ACPI_IOREG_GPE0_STS, 0xffffffff); //GPE0_STS + } + + //Set day of month alarm invalid - ACPI 1.0 section 4.7.2.4 + IoWrite8(CMOS_ADDR_PORT, 0xd | 0x80); //RTC_REGD + IoWrite8(CMOS_DATA_PORT, 0); + } + } + + //SCI_EN = 1 + SET_IO8_PM(ACPI_IOREG_PM1_CNTL, B_PCH_ACPI_PM1_CNT_SCI_EN); //PM1_CNT + + SbGpioSciInit(); + + InitParts(DispatchHandle, DispatchContext); + + for (Link = gAcpiEnDispatchHead; Link; Link = Link->Link) + { + Link->Function(Link); + } + + WRITE_IO8 (PCI_DEBUG_PORT, SW_SMI_ACPI_ENABLE); + + return SMM_CHILD_DISPATCH_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: DisableAcpiMode +// +// Description: This function disables ACPI mode by enabling SMI generation +// +// Input: PI 0.91, 1.0 +// DispatchHandle - SMI dispatcher handle +// *DispatchContext - Pointer to the dispatch context +// PI 1.1, 1.2 +// DispatchHandle - SMI dispatcher handle +// *DispatchContext- Points to an optional S/W SMI context +// CommBuffer - Points to the optional communication +// buffer +// CommBufferSize - Points to the size of the optional +// communication buffer +// +// Output: EFI_STATUS if the new SMM PI is applied. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) +EFI_STATUS DisableAcpiMode ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *DispatchContext OPTIONAL, + IN OUT VOID *CommBuffer OPTIONAL, + IN OUT UINTN *CommBufferSize OPTIONAL ) +#else +VOID DisableAcpiMode ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext ) +#endif +{ + ACPI_DISPATCH_LINK *Link; + + //Clear PM Sources and set Enables + WRITE_IO16_PM(ACPI_IOREG_PM1_STS, 0xffff); // 0x00 + WRITE_IO16_PM(ACPI_IOREG_PM1_EN, wPM1_SaveState); // 0x02 + + //Clear GPE0 Sources and set Enables + if (GetPchSeries() == PchLp) { + WRITE_IO32_PM(ACPI_PCHLP_IOREG_GPE0_STS + 0x0c, 0xffffffff); //GPE0_STS 0x8C + WRITE_IO32_PM(ACPI_PCHLP_IOREG_GPE0_EN + 0x0c, dGPE_SaveState); //GPE0_EN 0x9C + } else { + WRITE_IO32_PM(ACPI_IOREG_GPE0_STS + 0, 0xffffffff); //GPE0_STS 0x20 + WRITE_IO32_PM(ACPI_IOREG_GPE0_STS + 4, 0xffffffff); //GPE0_STS 0x24 + WRITE_IO32_PM(ACPI_IOREG_GPE0_EN, dGPE_SaveState); //GPE0_EN 0x28 + } + + //Disable SCI + RESET_IO8_PM(ACPI_IOREG_PM1_CNTL, BIT00); // 0x04 + InitParts2(DispatchHandle, DispatchContext); + for (Link = gAcpiDisDispatchHead; Link; Link = Link->Link) + { + Link->Function(Link); + } + + + WRITE_IO8 (PCI_DEBUG_PORT, SW_SMI_ACPI_DISABLE); + + return SMM_CHILD_DISPATCH_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: AddLink +// +// Description: Create and add link to specified list. +// +// Input: Size - +// Head - +// Tail - +// +// Output: VOID Pointer +// +// Modified: +// +// Referrals: SmmAllocatePool +// +// Notes: Here is the control flow of this function: +// 1. Allocate Link in Smm Pool. +// 2. Add Link to end. +// 3. Return Link address. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID * AddLink( + IN UINT32 Size, + IN VOID **Head, + IN VOID **Tail) +{ + VOID *Link; + + if (pSmst->SmmAllocatePool(0, Size, &Link) != EFI_SUCCESS) return 0; + + ((GENERIC_LINK*)Link)->Link = 0; + if (!*Head) + { + *Head = *Tail = Link; + } + else + { + ((GENERIC_LINK*)*Tail)->Link = Link; + *Tail = Link; + } + + return Link; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RemoveLink +// +// Description: Remove link from specified list. +// +// Input: Handle - EFI Handle +// Head - +// Tail - +// +// Output: BOOLEAN +// TRUE if link was removed. FALSE if link not in the list. +// +// Modified: +// +// Referrals: SmmFreePool +// +// Notes: Here is the control flow of this function: +// 1. Search link list for Link. +// 2. Remove link from list. +// 3. Free link. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN RemoveLink( + IN EFI_HANDLE Handle, + IN VOID **Head, + IN VOID **Tail) +{ + GENERIC_LINK *PrevLink, *Link; + + PrevLink = *Head; + + // Is link first. Link address is the same as the Handle. + if (((GENERIC_LINK*)*Head) == Handle) + { + if (PrevLink == *Tail) *Tail = 0; // If Tail = Head, then 0. + *Head = PrevLink->Link; + pSmst->SmmFreePool(PrevLink); + return TRUE; + } + + // Find Link. + for (Link = PrevLink->Link; Link; PrevLink = Link, Link = Link->Link) + { + if (Link == Handle) // Link address is the same as the Handle. + { + if (Link == *Tail) *Tail = PrevLink; + PrevLink->Link = Link->Link; + pSmst->SmmFreePool(Link); + return TRUE; + } + } + + return FALSE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiAcpiEnRegister +// +// Description: Register a Link on ACPI enable SMI. +// +// Input: This - +// Function - +// Context - +// +// +// Output: Handle - +// EFI_STATUS +// +// Modified: gAcpiEnDispatchHead, gAcpiEnDispatchTail +// +// Referrals: AddLink +// +// Notes: Here is the control flow of this function: +// 1. Verify if Context if valid. If invalid, +// return EFI_INVALID_PARAMETER. +// 2. Allocate structure and add to link list. +// 3. Fill link. +// 4. Enable Smi Source. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiAcpiEnRegister( + IN EFI_ACPI_DISPATCH_PROTOCOL *This, + IN EFI_ACPI_DISPATCH Function, + OUT EFI_HANDLE *Handle) +{ + ACPI_DISPATCH_LINK *NewLink; + + NewLink = AddLink(sizeof(ACPI_DISPATCH_LINK), \ + &gAcpiEnDispatchHead, \ + &gAcpiEnDispatchTail); + if (!NewLink) return EFI_OUT_OF_RESOURCES; + + NewLink->Function = Function; + *Handle = NewLink; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiAcpiEnUnregister +// +// Description: Unregister a Link on ACPI enable SMI. +// +// Input: This - +// Handle - +// +// Output: EFI_STATUS +// +// Modified: gAcpiEnDispatchHead, gAcpiEnDispatchTail +// +// Referrals: RemoveLink +// +// Notes: Here is the control flow of this function: +// 1. Remove link. If no link, return EFI_INVALID_PARAMETER. +// 2. Disable SMI Source if no other handlers using source. +// 3. Return EFI_SUCCESS. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiAcpiEnUnregister( + IN EFI_ACPI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle) +{ + if (!RemoveLink(Handle, &gAcpiEnDispatchHead, &gAcpiEnDispatchTail)) + return EFI_INVALID_PARAMETER; + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiAcpiDisRegister +// +// Description: Register a Link on ACPI disable SMI. +// +// Input: This - +// Function - +// *Context - +// +// +// Output: Handle - EFI Handle +// EFI_STATUS +// +// Modified: gAcpiDisDispatchHead, gAcpiDisDispatchTail +// +// Referrals: AddLink +// +// Notes: Here is the control flow of this function: +// 1. Verify if Context if valid. If invalid, +// return EFI_INVALID_PARAMETER. +// 2. Allocate structure and add to link list. +// 3. Fill link. +// 4. Enable Smi Source. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiAcpiDisRegister( + IN EFI_ACPI_DISPATCH_PROTOCOL *This, + IN EFI_ACPI_DISPATCH Function, + OUT EFI_HANDLE *Handle) +{ + ACPI_DISPATCH_LINK *NewLink; + + NewLink = AddLink(sizeof(ACPI_DISPATCH_LINK), \ + &gAcpiDisDispatchHead, \ + &gAcpiDisDispatchTail); + if (!NewLink) return EFI_OUT_OF_RESOURCES; + + NewLink->Function = Function; + *Handle = NewLink; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiAcpiDisUnregister +// +// Description: Unregister a Link on ACPI Disable SMI. +// +// Input: This - +// Handle - EFI Handle +// +// Output: EFI_STATUS +// +// Modified: gAcpiDisDispatchHead, gAcpiDisDispatchTail +// +// Referrals: RemoveLink +// +// Notes: Here is the control flow of this function: +// 1. Remove link. If no link, return EFI_INVALID_PARAMETER. +// 2. Disable SMI Source if no other handlers using source. +// 3. Return EFI_SUCCESS. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiAcpiDisUnregister( + IN EFI_ACPI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle) +{ + if (!RemoveLink(Handle, &gAcpiDisDispatchHead, &gAcpiDisDispatchTail)) + return EFI_INVALID_PARAMETER; + return EFI_SUCCESS; +} + +EFI_ACPI_DISPATCH_PROTOCOL gEfiAcpiEnDispatchProtocol = \ + {EfiAcpiEnRegister, EfiAcpiEnUnregister}; + +EFI_ACPI_DISPATCH_PROTOCOL gEfiAcpiDisDispatchProtocol = \ + {EfiAcpiDisRegister, EfiAcpiDisUnregister}; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbAcpiS3PatchedFunction +// +// Description: This function will be called when ACPI S3 resuming. +// +// Input: PI 0.91, 1.0 +// DispatchHandle - SMI dispatcher handle +// *DispatchContext - Pointer to the dispatch context +// PI 1.1, 1.2 +// DispatchHandle - SMI dispatcher handle +// *DispatchContext- Points to an optional S/W SMI context +// CommBuffer - Points to the optional communication +// buffer +// CommBufferSize - Points to the size of the optional +// communication buffer +// +// Output: EFI_STATUS if the new SMM PI is applied. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) +EFI_STATUS SbAcpiS3PatchedFunction ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *Context OPTIONAL, + IN OUT VOID *CommBuffer OPTIONAL, + IN OUT UINTN *CommBufferSize OPTIONAL ) +#else +VOID SbAcpiS3PatchedFunction ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext ) +#endif +{ +#if AMI_INIT_VERB_TABLE_IN_S3 + UINT8 CodecIdx; + UINT8 j; + UINT8 i; + UINT16 Cmd16; + UINT16 TimeOut; + UINT16 SDIPin; + UINT32 Buffer32; + UINT32 CodecId; + UINT32 Base32; + UINT8 VerbTblSize = sizeof(HdaVerbTbl) / \ + sizeof(HDA_VERB_TABLE); + volatile UINT32 *pHdaVerbTbl; + + if ((READ_MEM8_RCRB(RCRB_MMIO_FD) & 0x10) == 0) { // 0x3418 + Base32 = READ_PCI32_HDA(R_PCH_HDA_HDBARL) & B_PCH_HDA_HDBARL_LBA; // 0x10 + Cmd16 = READ_PCI16_HDA(R_PCH_HDA_COMMAND); + WRITE_PCI16_HDA(R_PCH_HDA_COMMAND, Cmd16 | B_PCH_HDA_COMMAND_MSE); + + // Deassert the CRST bit in Azalia to cause the link to start up + SET_MEM8(Base32 | R_HDA_GCTL, B_HDA_GCTL_CRST); + + // Turn off the link by writing a 0 to the Controller Reset bit in + // HD Audio, poll Controller Reset bit until it reads back as 0. + RESET_MEM8(Base32 | R_HDA_GCTL, B_HDA_GCTL_CRST); + + for (TimeOut = 0; TimeOut < 0x8000; TimeOut++) + if ((READ_MEM8(Base32 | R_HDA_GCTL) & B_HDA_GCTL_CRST) == 0) break; + + // Turn on the link again by writing a 1 to Controller Reset bit + // This causes a codec link re-enumeration. Delay for 1ms, + // then poll Controller Reset bit until it reads back 1. + SET_MEM8(Base32 | R_HDA_GCTL, B_HDA_GCTL_CRST); + CountTime(1000, PM_BASE_ADDRESS); // 1ms + + for (TimeOut = 0; TimeOut < 0x8000; TimeOut++) + if (READ_MEM8(Base32 | R_HDA_GCTL) & B_HDA_GCTL_CRST) break; + + // Set the map of SDI pins + SDIPin = READ_MEM8(Base32 | R_HDA_STATESTS); + for (CodecIdx = MAX_NUM_HD_CODECS; CodecIdx; CodecIdx--) { + if (SDIPin & (1 << (CodecIdx - 1))) { + SDIPin &= ~(1 << (CodecIdx - 1)); + for (TimeOut = 0; TimeOut < 0x8000; TimeOut++) { + if ((READ_MEM16(Base32 | R_HDA_IRS) & B_HDA_IRS_ICB) == 0) break; + } + + if (TimeOut == 0x8000) { + RESET_MEM8(Base32 | R_HDA_GCTL, B_HDA_GCTL_CRST); + SET_MEM8(Base32 | R_HDA_GCTL, B_HDA_GCTL_CRST); + } + + Buffer32 = ((CodecIdx - 1) << 28) | 0xf0000; + WRITE_MEM32(Base32|R_HDA_IC, Buffer32); + + SET_MEM16(Base32 | R_HDA_IRS, B_HDA_IRS_ICB | B_HDA_IRS_IRV); + + while ((READ_MEM16(Base32 | R_HDA_IRS) & (B_HDA_IRS_ICB | B_HDA_IRS_IRV)) != B_HDA_IRS_IRV); + + CodecId = READ_MEM32(Base32 | R_HDA_IR); + + // CheckforValidCodec + + if (VerbTblSize == 0) break; + + for (j = 0; j < VerbTblSize; j++) { + if (HdaVerbTbl[j].CodecId32 == CodecId) { + pHdaVerbTbl = HdaVerbTbl[j].VerbPtr; + Buffer32 = *pHdaVerbTbl; + if ((UINT8)(Buffer32 >> 28) == (CodecIdx - 1)) + break; + } + } + + // Program Pin Widget Configuration + if (j != VerbTblSize) { + pHdaVerbTbl = HdaVerbTbl[j].VerbPtr; + for(i = 0; i < (HdaVerbTbl[j].frontSideNo + HdaVerbTbl[j].RearSideNo) * 4; i++) { + // Poll the ICB bit of the ICS register at HDABAR + 68h[0] until it return 0. + for (TimeOut = 0; TimeOut < 0x8000; TimeOut++) { + if ((READ_MEM16(Base32 | R_HDA_IRS) & B_HDA_IRS_ICB) == 0) + break; + } + // Write the current verb(DWORD) to the IC register at HDABAR + 60h + WRITE_MEM32(Base32 | R_HDA_IC, *pHdaVerbTbl++); + // Send verb to Codec + SET_MEM16(Base32 | R_HDA_IRS, (B_HDA_IRS_ICB | B_HDA_IRS_IRV)); + } + } + } + } + } + + // Restore Command Register + WRITE_PCI16_HDA(R_PCH_HDA_COMMAND, Cmd16); +#endif + + return SMM_CHILD_DISPATCH_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InSmmFunction +// +// Description: Install ACPI Software SMI Handlers. +// +// Input: ImageHandle - Image handle +// *SystemTable - Pointer to the system table +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS InSmmFunction ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle = NULL; + EFI_HANDLE DummyHandle = NULL; + AMI_SMM_SW_DISPATCH_PROTOCOL *SwDispatch = NULL; + AMI_SMM_SW_DISPATCH_CONTEXT AcpiEnableContext = {SW_SMI_ACPI_ENABLE}; + AMI_SMM_SW_DISPATCH_CONTEXT AcpiDisableContext = {SW_SMI_ACPI_DISABLE}; + AMI_SMM_SW_DISPATCH_CONTEXT AcpiS3PatchContext = {SW_SMI_SB_ACPI_S3}; +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) + EFI_SMM_SYSTEM_TABLE2 *pSmst2; +#endif + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) + Status = InitAmiSmmLib( ImageHandle, SystemTable ); + if (EFI_ERROR(Status)) return Status; + + // We are in SMM, retrieve the pointer to SMM System Table + Status = gSmmBase2->GetSmstLocation( gSmmBase2, &pSmst2); + if (EFI_ERROR(Status)) return EFI_UNSUPPORTED; + + Status = pSmst2->SmmLocateProtocol( &gEfiSmmSwDispatch2ProtocolGuid , \ + NULL, \ + &SwDispatch ); + TRACE((TRACE_ALWAYS, "Smm Locate Protocol gEfiSmmSwDispatch2ProtocolGuid, Status = %r\n",Status)); +#else + Status = pBS->LocateProtocol( &gEfiSmmSwDispatchProtocolGuid , \ + NULL, \ + &SwDispatch ); +#endif + if (EFI_ERROR(Status)) return Status; + + Status = SwDispatch->Register( SwDispatch, \ + SbAcpiS3PatchedFunction, \ + &AcpiS3PatchContext, \ + &Handle ); + if (EFI_ERROR(Status)) return Status; + + Status = SwDispatch->Register( SwDispatch, \ + EnableAcpiMode, \ + &AcpiEnableContext, \ + &Handle ); + if (EFI_ERROR(Status)) return Status; + + Status = SwDispatch->Register( SwDispatch, \ + DisableAcpiMode, \ + &AcpiDisableContext,\ + &Handle ); + if (EFI_ERROR(Status)) return Status; + + Status = pBS->InstallMultipleProtocolInterfaces( + &DummyHandle, + &gEfiAcpiEnDispatchProtocolGuid, + &gEfiAcpiEnDispatchProtocol, + &gEfiAcpiDisDispatchProtocolGuid, + &gEfiAcpiDisDispatchProtocol, + NULL); + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: AcpiModeEnableInit +// +// Description: installs appropriate ACPI enable/disable Dispatch Protocol. +// +// Input: ImageHandle - Image handle +// *SystemTable - Pointer to the system table +// +// Output: EFI_STATUS +// +// Referrals: InitAmiLib, InitSmmHandler +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS AcpiModeEnableInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + InitAmiLib( ImageHandle, SystemTable ); + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) + Status = SystemTable->BootServices->LocateProtocol( \ + &gEfiSmmBase2ProtocolGuid, \ + NULL, \ + &gSmmBase2 ); + ASSERT_EFI_ERROR(Status); +#endif + + return InitSmmHandler( ImageHandle, SystemTable, InSmmFunction, NULL ); +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/AcpiModeEnable.cif b/Chipset/SB/AcpiModeEnable.cif new file mode 100644 index 0000000..371a6da --- /dev/null +++ b/Chipset/SB/AcpiModeEnable.cif @@ -0,0 +1,12 @@ +<component> + name = "AcpiModeEnable" + category = ModulePart + LocalRoot = "Chipset\SB" + RefName = "AcpiModeEnable" +[files] +"AcpiModeEnable.sdl" +"AcpiModeEnable.mak" +"AcpiModeEnable.c" +"AcpiModeEnable.dxs" +"AcpiModeEnable.h" +<endComponent> diff --git a/Chipset/SB/AcpiModeEnable.dxs b/Chipset/SB/AcpiModeEnable.dxs new file mode 100644 index 0000000..ec4f181 --- /dev/null +++ b/Chipset/SB/AcpiModeEnable.dxs @@ -0,0 +1,64 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/AcpiModeEnable/AcpiModeEnable.dxs 2 4/25/12 9:26a Victortu $ +// +// $Revision: 2 $ +// +// $Date: 4/25/12 9:26a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/AcpiModeEnable/AcpiModeEnable.dxs $ +// +// 2 4/25/12 9:26a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Remove unnecessary dependence. +// [Files] AcpiModeEnable.dxs; SBSMI.dxs; SleepSmi.dxs +// +// 1 2/08/12 8:30a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +//--------------------------------------------------------------------------- +// +// Name: AcpiModeEnable.DXS +// +// Description: Dependency file for the ACPI mode enable/disable driver +// +//--------------------------------------------------------------------------- +//<AMI_FHDR_END> + +#include <Protocol\SmmSwDispatch.h> + +DEPENDENCY_START + EFI_SMM_SW_DISPATCH_PROTOCOL_GUID +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/AcpiModeEnable.h b/Chipset/SB/AcpiModeEnable.h new file mode 100644 index 0000000..91943a8 --- /dev/null +++ b/Chipset/SB/AcpiModeEnable.h @@ -0,0 +1,123 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/AcpiModeEnable/AcpiModeEnable.h 1 2/08/12 8:30a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:30a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/AcpiModeEnable/AcpiModeEnable.h $ +// +// 1 2/08/12 8:30a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* + +//<AMI_FHDR_START> +//---------------------------------------------------------------------------- +// +// Name: AcpiModeEnable.h +// +// Description: +// +//---------------------------------------------------------------------------- +//<AMI_FHDR_END> + +#ifndef __SMM_ACPI_EN_PROTOCOL_H__ +#define __SMM_ACPI_EN_PROTOCOL_H__ +#ifdef __cplusplus +extern "C" { +#endif +#include <EFI.h> + +#define EFI_ACPI_EN_DISPATCH_PROTOCOL_GUID \ + { 0xbd88ec68, 0xebe4, 0x4f7b, 0x93, 0x5a, 0x4f,\ + 0x66, 0x66, 0x42, 0xe7, 0x5f } + +#define EFI_ACPI_DIS_DISPATCH_PROTOCOL_GUID \ + { 0x9c939ba6, 0x1fcc, 0x46f6, 0xb4, 0xe1, 0x10, \ + 0x2d, 0xbe, 0x18, 0x65, 0x67 } + +#define PM1_CNT 0x04 +#define BIT_WAK_STS 0x8000 +#define BIT_SLP_TYP_MASK 0x1C00 +#define S3_SLP_TYP 0x05 + +typedef struct _EFI_ACPI_DISPATCH_PROTOCOL EFI_ACPI_DISPATCH_PROTOCOL; + +//---------------------------------------------------------------------------- +// EFI_ACPI_DISPATCH +//---------------------------------------------------------------------------- + +#ifndef __SMM_CHILD_DISPATCH__H__ +typedef struct _GENERIC_LINK GENERIC_LINK; +typedef struct _GENERIC_LINK { + void *Link; +}; +#endif + +typedef VOID (EFIAPI *EFI_ACPI_DISPATCH) ( + IN EFI_HANDLE DispatchHandle +); + +typedef struct _ACPI_DISPATCH_LINK ACPI_DISPATCH_LINK; +struct _ACPI_DISPATCH_LINK { + IN ACPI_DISPATCH_LINK *Link; + IN EFI_ACPI_DISPATCH Function; +}; + +typedef EFI_STATUS (EFIAPI *EFI_ACPI_REGISTER) ( + IN EFI_ACPI_DISPATCH_PROTOCOL *This, + IN EFI_ACPI_DISPATCH DispatchFunction, + OUT EFI_HANDLE *DispatchHandle +); + +typedef EFI_STATUS (EFIAPI *EFI_ACPI_UNREGISTER) ( + IN EFI_ACPI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle +); + + +struct _EFI_ACPI_DISPATCH_PROTOCOL { + EFI_ACPI_REGISTER Register; + EFI_ACPI_UNREGISTER UnRegister; +}; + + +typedef EFI_STATUS (*EFI_TASK_FUNCTION) (VOID); + + +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/AcpiModeEnable.mak b/Chipset/SB/AcpiModeEnable.mak new file mode 100644 index 0000000..260c96e --- /dev/null +++ b/Chipset/SB/AcpiModeEnable.mak @@ -0,0 +1,94 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/AcpiModeEnable/AcpiModeEnable.mak 2 7/02/12 10:16a Victortu $ +# +# $Revision: 2 $ +# +# $Date: 7/02/12 10:16a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/AcpiModeEnable/AcpiModeEnable.mak $ +# +# 2 7/02/12 10:16a Victortu +# [TAG] None +# [Category] Bug Fix +# [Severity] Normal +# [Symptom] System may hang at 0xB1 when boot to UEFI Windows 8. +# [Solution] Set Driver type to SMM_DRIVER. +# [Files] AcpiModeEnable.mak +# +# 1 2/08/12 8:29a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: AcpiModeEnable.MAK +# +# Description: Make file to enable/disable ACPI mode +# +#<AMI_FHDR_END> +#************************************************************************* +!IFNDEF PI_SPECIFICATION_VERSION +PI_SPECIFICATION_VERSION = 0 +!ENDIF + +all : AcpiModeEnable + +AcpiModeEnable : $(BUILD_DIR)\AcpiModeEnable.mak AcpiModeEnableBin + +$(BUILD_DIR)\AcpiModeEnable.mak : $(ACPI_MODE_ENABLE_DIR)\AcpiModeEnable.cif $(ACPI_MODE_ENABLE_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(ACPI_MODE_ENABLE_DIR)\AcpiModeEnable.cif $(CIF2MAK_DEFAULTS) + +AcpiModeEnable_INCLUDES=\ + /I$(Foundation_DIR)\ + /I$(PROJECT_DIR)\ + $(INTEL_PCH_INCLUDES)\ + +AcpiModeEnableBin : $(AMIDXELIB) $(AMICSPLib) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\AcpiModeEnable.mak all\ + "CFLAGS=$(CFLAGS) /I$(SB_BOARD_DIR) /D\"OEM_HDA_VERB_TABLE=$(OEM_HDA_VERB_TABLE)\" /D\"OEM_HDA_VERB_TABLE_CONTENT=$(OEM_HDA_VERB_TABLE_CONTENT)\""\ + GUID=750890A6-7ACF-4f4f-81BD-B400C2BEA95A\ + ENTRY_POINT=AcpiModeEnableInit\ + "MY_INCLUDES=$(AcpiModeEnable_INCLUDES)"\ +!IF $(PI_SPECIFICATION_VERSION) >= 0x1000A && $(CORE_COMBINED_VERSION) >= 0x4028B + TYPE=SMM_DRIVER \ + DEPEX1=$(ACPI_MODE_ENABLE_DIR)\AcpiModeEnable.DXS \ +!ELSE + TYPE=BS_DRIVER \ + DEPEX1=$(ACPI_MODE_ENABLE_DIR)\AcpiModeEnable.DXS DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ +!ENDIF + COMPRESS=1\ + "INIT_LIST=$(AcpiEnableCallbackList)"\ + "INIT_LIST2=$(AcpiDisableCallbackList)" + +AcpiModeEnableBin : $(CSP_ACPI_OBJ_FILES) + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/SB/AcpiModeEnable.sdl b/Chipset/SB/AcpiModeEnable.sdl new file mode 100644 index 0000000..4778722 --- /dev/null +++ b/Chipset/SB/AcpiModeEnable.sdl @@ -0,0 +1,125 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/AcpiModeEnable/AcpiModeEnable.sdl 4 10/01/12 5:51a Victortu $ +# +# $Revision: 4 $ +# +# $Date: 10/01/12 5:51a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/AcpiModeEnable/AcpiModeEnable.sdl $ +# +# 4 10/01/12 5:51a Victortu +# +# 3 9/26/12 3:57a Victortu +# [TAG] None +# [Category] Improvement +# [Description] Update for PCH LP GPIO compatible. +# [Files] SB.sdl, SB.H, AcpiModeEnable.c, AcpiModeEnable.sdl, +# SBDxe.c, SBGeneric.c, SBPEI.c, SBSMI.c, SleepSmi.c, +# SmiHandlerPorting.c, SmiHandlerPorting2.c +# +# 2 9/12/12 5:16a Victortu +# [TAG] None +# [Category] Improvement +# [Description] Modify for ULT GPIO changed by PCH LPT-LP EDS 1.0. +# [Files] SB.H, SB.sdl, AcpiModeEnable.c, AcpiModeEnable.sdl, +# SBPEI.c +# +# 1 2/08/12 8:29a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "AcpiModeEnable_SUPPORT" + Value = "1" + Help = "Main switch to enable AcpiModeEnable support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes +End + +TOKEN + Name = "SW_SMI_ACPI_ENABLE" + Value = "0xA0" + Help = "Value to be written into SMI command register \to enable SCI generation and switch to ACPI mode" + TokenType = Integer + TargetH = Yes + Range = "0-0xff" +End + +TOKEN + Name = "SW_SMI_ACPI_DISABLE" + Value = "0xA1" + Help = "Value to write into SMI command register to disable \SCI generation and switch to non ACPI mode" + TokenType = Integer + TargetH = Yes + Range = "0 - 0xff" +End + +TOKEN + Name = "GPIO_SCI_BITMAP" + Value = "0x0000" + Help = "Programming the corresponding GPIO pin to generate SCI#.\BIT00: GPIO0\BIT01: GPIO1\BIT02: GPIO2\.\.\.\BIT15: GPIO15" + TokenType = Integer + TargetH = Yes + Range = "0 - 0xffff" +End + +PATH + Name = "ACPI_MODE_ENABLE_DIR" +End + +MODULE + Help = "Includes AcpiModeEnable.mak to Project" + File = "AcpiModeEnable.mak" +End + +ELINK + Name = "$(BUILD_DIR)\AcpiModeEnable.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + +ELINK + Name = "CSP_ACPI_OBJ_FILES" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "AcpiEnableCallbackList" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "AcpiDisableCallbackList" + InvokeOrder = ReplaceParent +End +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Chipset/SB/CSM/LegacyInterrupt/LegacyInterrupt.c b/Chipset/SB/CSM/LegacyInterrupt/LegacyInterrupt.c new file mode 100644 index 0000000..6177f8a --- /dev/null +++ b/Chipset/SB/CSM/LegacyInterrupt/LegacyInterrupt.c @@ -0,0 +1,310 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2010, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/CSM/Generic/Chipset/SouthBridge/LegacyInterrupt.c 14 7/28/10 2:46p Olegi $ +// +// $Revision: 14 $ +// +// $Date: 7/28/10 2:46p $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/CSM/Generic/Chipset/SouthBridge/LegacyInterrupt.c $ +// +// 14 7/28/10 2:46p Olegi +// +// 13 1/12/10 11:51a Olegi +// Copyright message updated. +// +// 12 10/14/09 12:26p Krishnakumarg +// CloseEvent funtion used instead of a static variable in callback +// routines - EIP 27065 +// +// 11 4/27/07 5:43p Olegi +// +// 10 4/27/07 5:39p Olegi +// +// 9 4/27/07 5:21p Olegi +// CSM.CHM preparations. +// +// 8 10/13/06 12:32a Felixp +// UEFI2.0 compliance: use CreateReadyToBootEvent instead of +// CreateEvent(READY_TO_BOOT) +// +// 7 5/27/05 4:24p Markw +// Added Boot Script. +// +// 6 4/04/05 4:19p Sivagarn +// Updated to latest template format +// +// 2 2/22/05 10:00a Sivagarn +// - Updated to latest labeled CSM & Core +// +// 5 1/18/05 3:22p Felixp +// PrintDebugMessage renamed to Trace +// +// 4 12/09/04 10:59a Olegi +// +// 3 12/06/04 9:37a Olegi +// Added interrupt router registers' buffering. +// +// 2 12/03/04 9:55a Olegi +// +// 1 10/26/04 9:48a Olegi +// +// 3 8/31/04 5:46p Markw +// Fixed bug. Using wrong value to index PirqReg. +// +// 2 8/25/04 4:58p Markw +// Added comments. +// +// 1 8/25/04 3:01p Markw +// +// 1 8/13/04 2:39p Markw +// +//********************************************************************** +//<AMI_FHDR_START> +// +// Name: 8259InterruptController.c +// +// Description: Initialize and provide a protocol to set PIRQ values +// +//<AMI_FHDR_END> +//********************************************************************** + +#include <AmiDxeLib.h> +#include <Protocol\PciRootBridgeIo.h> +#include <Protocol\LegacyInterrupt.h> +#include <Protocol\BootScriptSave.h> + +extern UINT8 bMaxPIRQ; +extern UINT8 bRouterBus; +extern UINT8 bRouterDevice; +extern UINT8 bRouterFunction; + +EFI_GUID gEfiLegacyInterruptProtocolGuid = EFI_LEGACY_INTERRUPT_PROTOCOL_GUID; +EFI_GUID gEfiPciRootBridgeIoProtocolGuid = EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID; +EFI_GUID gEfiBootScriptSaveGuid = EFI_BOOT_SCRIPT_SAVE_GUID; + +EFI_EVENT gEvtBootScript; + +extern +EFI_STATUS +SBGen_InitializeRouterRegisters ( + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *gPciRootBridgeIo); + +extern +EFI_STATUS +SBGen_ReadPirq ( + IN EFI_LEGACY_INTERRUPT_PROTOCOL *This, + IN UINT8 PirqNumber, + OUT UINT8 *PirqData); + +EFI_STATUS +SBGen_WritePirq( + IN EFI_LEGACY_INTERRUPT_PROTOCOL *This, + IN UINT8 PirqNumber, + IN UINT8 PirqData); + +EFI_STATUS SBGen_WriteBootScript( + IN EFI_BOOT_SCRIPT_SAVE_PROTOCOL *BootScriptSave +); + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure: GetNumberPirqs +// +// Description: Return number of supported Pirqs. +// +// Input: +// IN EFI_LEGACY_INTERRUPT_PROTOCOL *This +// OUT UINT8 *NumberPirqs +// +// Output: +// Status of the operation +// +// Notes: +// Here is the control flow of this function: +// 1. Set NumberPirqs to number of supported Pirqs. +// 2. Return EFI_SUCCESS; +// +//<AMI_PHDR_END> +//********************************************************************** +EFI_STATUS GetNumberPirqs( + IN EFI_LEGACY_INTERRUPT_PROTOCOL *This, + OUT UINT8 *NumberPirqs + ) +{ + *NumberPirqs = bMaxPIRQ; + return EFI_SUCCESS; +} + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure: GetLocation +// +// Description: Return location of device controlling the Pirqs. +// +// Input: +// IN EFI_LEGACY_INTERRUPT_PROTOCOL *This +// OUT UINT8 *Bus +// OUT UINT8 *Device +// OUT UINT8 *Function +// +// Output: +// Status of the operation +// +// Notes: +// Here is the control flow of this function: +// 1. Set Bus, Device, and Function. +// 2. Return EFI_SUCCESS. +// +//<AMI_PHDR_END> +//********************************************************************** +EFI_STATUS GetLocation( + IN EFI_LEGACY_INTERRUPT_PROTOCOL *This, + OUT UINT8 *Bus, + OUT UINT8 *Device, + OUT UINT8 *Function + ) +{ + *Bus = bRouterBus; + *Device = bRouterDevice; + *Function = bRouterFunction; + return EFI_SUCCESS; +} + + + +EFI_LEGACY_INTERRUPT_PROTOCOL gEfiLegacyInterruptProtocol = +{ + GetNumberPirqs, GetLocation, + SBGen_ReadPirq, SBGen_WritePirq +}; + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure: CallbackBootScript +// +// Description: Saves the PIRQ registers to Boot Script +// +// Input: +// IN EFI_EVENT Event +// IN VOID *Context +// Output: +// None +// +//<AMI_PHDR_END> +//********************************************************************** +VOID CallbackBootScript(IN EFI_EVENT Event, IN VOID *Context) +{ + EFI_BOOT_SCRIPT_SAVE_PROTOCOL *BootScriptSave; + EFI_STATUS Status; + + + Status = pBS->LocateProtocol( + &gEfiBootScriptSaveGuid, + NULL, + &BootScriptSave + ); + if (EFI_ERROR(Status)) return; + + SBGen_WriteBootScript(BootScriptSave); + + // + //Kill the Event + // + pBS->CloseEvent(Event); + +} + + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure: InitializeLegacyInterrupt +// +// Description: Install Legacy Interrupt Protocol. +// +// Input: +// IN EFI_HANDLE ImageHandle +// IN EFI_SYSTEM_TABLE *SystemTable +// +// Output: +// EFI_STATUS +// +// Notes: +// Here is the control flow of this function: +// 1. Intialize Library. +// 2. Locate PciRootBridgeIo. If error, return error. +// 3. Install Legacy Interrupt protocol. +// 4. Return its Status. +//<AMI_PHDR_END> +//********************************************************************** +EFI_STATUS InitializeLegacyInterrupt( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *gPciRootBridgeIo; + + InitAmiLib(ImageHandle, SystemTable); + + Status = pBS->LocateProtocol( + &gEfiPciRootBridgeIoProtocolGuid, + NULL, + &gPciRootBridgeIo + ); + if (EFI_ERROR(Status)) return Status; + + //Create event for boot script + Status = CreateReadyToBootEvent( + TPL_NOTIFY, + CallbackBootScript, + NULL, + &gEvtBootScript + ); + ASSERT_EFI_ERROR(Status); + + // + // Initialize router registers buffer + // + Status = SBGen_InitializeRouterRegisters (gPciRootBridgeIo); + if (EFI_ERROR(Status)) return Status; + + return pBS->InstallMultipleProtocolInterfaces( + &ImageHandle, + &gEfiLegacyInterruptProtocolGuid, &gEfiLegacyInterruptProtocol, + NULL + ); +} + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2010, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Chipset/SB/CSM/LegacyInterrupt/LegacyInterrupt.cif b/Chipset/SB/CSM/LegacyInterrupt/LegacyInterrupt.cif new file mode 100644 index 0000000..381450d --- /dev/null +++ b/Chipset/SB/CSM/LegacyInterrupt/LegacyInterrupt.cif @@ -0,0 +1,11 @@ +<component> + name = "LegacyInterrupt" + category = ModulePart + LocalRoot = "Chipset\SB\CSM\LegacyInterrupt\" + RefName = "LegacyInterrupt" +[files] +"\LegacyInterrupt.sdl" +"\LegacyInterrupt.mak" +"\LegacyInterrupt.c" +"\LegacyInterrupt.dxs" +<endComponent> diff --git a/Chipset/SB/CSM/LegacyInterrupt/LegacyInterrupt.dxs b/Chipset/SB/CSM/LegacyInterrupt/LegacyInterrupt.dxs new file mode 100644 index 0000000..7aca534 --- /dev/null +++ b/Chipset/SB/CSM/LegacyInterrupt/LegacyInterrupt.dxs @@ -0,0 +1,65 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2010, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/CSM/Generic/Chipset/SouthBridge/LegacyInterrupt.dxs 5 1/12/10 11:51a Olegi $ +// +// $Revision: 5 $ +// +// $Date: 1/12/10 11:51a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/CSM/Generic/Chipset/SouthBridge/LegacyInterrupt.dxs $ +// +// 5 1/12/10 11:51a Olegi +// Copyright message updated. +// +// 4 4/27/07 5:21p Olegi +// CSM.CHM preparations. +// +// 3 8/23/05 11:51a Girim +// Updated Copyright Year +// +//********************************************************************** +//<AMI_FHDR_START> +// +// Name: LegacyInterrupt.dxs +// +// Description: Legacy Interrupt dependency file +// +//<AMI_FHDR_END> +//********************************************************************** + +#include <Protocol\PciRootBridgeIo.h> +#include <Protocol\BootScriptSave.h> + +DEPENDENCY_START + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID AND + EFI_BOOT_SCRIPT_SAVE_GUID +DEPENDENCY_END + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2010, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Chipset/SB/CSM/LegacyInterrupt/LegacyInterrupt.mak b/Chipset/SB/CSM/LegacyInterrupt/LegacyInterrupt.mak new file mode 100644 index 0000000..6d23259 --- /dev/null +++ b/Chipset/SB/CSM/LegacyInterrupt/LegacyInterrupt.mak @@ -0,0 +1,90 @@ +#********************************************************************** +#********************************************************************** +#** ** +#** (C)Copyright 1985-2010, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#********************************************************************** +#********************************************************************** + +#********************************************************************** +# $Header: /Alaska/SOURCE/Modules/CSM/Generic/Chipset/SouthBridge/LegacyInterrupt.mak 8 1/12/10 11:51a Olegi $ +# +# $Revision: 8 $ +# +# $Date: 1/12/10 11:51a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/CSM/Generic/Chipset/SouthBridge/LegacyInterrupt.mak $ +# +# 8 1/12/10 11:51a Olegi +# Copyright message updated. +# +# 7 4/27/07 5:21p Olegi +# CSM.CHM preparations. +# +# 6 12/02/05 11:44a Felixp +# +# 5 4/04/05 4:19p Sivagarn +# Included CSP Library into the build process +# +# 2 2/22/05 10:00a Sivagarn +# - Updated to latest labeled CSM & Core +# +# 4 1/18/05 3:22p Felixp +# PrintDebugMessage renamed to Trace +# +# 3 12/24/04 3:42p Felixp +# +# 2 11/30/04 4:22p Felixp +# Updated in accordance with the latest build process +# +# 1 10/26/04 9:48a Olegi +# +# 1 8/25/04 3:01p Markw +# +# 1 8/13/04 2:39p Markw +# +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: LegacyInterrupt +# +# Description: Legacy Interrupt make file +# +#<AMI_FHDR_END> +#********************************************************************** +all : LegacyInterrupt + +LegacyInterrupt : $(BUILD_DIR)\LegacyInterrupt.mak LegacyInterruptBin + +$(BUILD_DIR)\LegacyInterrupt.mak : $(LEGACY_INTERRUPT_DIR)\$(@B).cif $(LEGACY_INTERRUPT_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(LEGACY_INTERRUPT_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +LegacyInterruptBin : $(AMIDXELIB) $(AMICSPLib) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\LegacyInterrupt.mak all\ + GUID=71ED12D1-250B-42fb-8C17-10DCFA771701\ + ENTRY_POINT=InitializeLegacyInterrupt\ + TYPE=BS_DRIVER\ + COMPRESS=1 + +#********************************************************************** +#********************************************************************** +#** ** +#** (C)Copyright 1985-2010, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#********************************************************************** +#********************************************************************** diff --git a/Chipset/SB/CSM/LegacyInterrupt/LegacyInterrupt.sdl b/Chipset/SB/CSM/LegacyInterrupt/LegacyInterrupt.sdl new file mode 100644 index 0000000..d6a7457 --- /dev/null +++ b/Chipset/SB/CSM/LegacyInterrupt/LegacyInterrupt.sdl @@ -0,0 +1,25 @@ +TOKEN + Name = "LegacyInterrupt_SUPPORT" + Value = "1" + Help = "Main switch to enable LegacyInterrupt support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes +End + +PATH + Name = "LEGACY_INTERRUPT_DIR" +End + +MODULE + Help = "Includes LegacyInterrupt.mak to Project" + File = "LegacyInterrupt.mak" +End + +ELINK + Name = "$(BUILD_DIR)\LegacyInterrupt.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + diff --git a/Chipset/SB/CSM/csmsb.cif b/Chipset/SB/CSM/csmsb.cif new file mode 100644 index 0000000..5a8509b --- /dev/null +++ b/Chipset/SB/CSM/csmsb.cif @@ -0,0 +1,8 @@ +<component> + name = "CSM SB-Generic" + category = ModulePart + LocalRoot = "Chipset\SB\CSM\" + RefName = "CSMSB" +[parts] +"LegacyInterrupt" +<endComponent> diff --git a/Chipset/SB/GbE_OR.BIN b/Chipset/SB/GbE_OR.BIN Binary files differnew file mode 100644 index 0000000..6668f11 --- /dev/null +++ b/Chipset/SB/GbE_OR.BIN diff --git a/Chipset/SB/IDE.ASL b/Chipset/SB/IDE.ASL new file mode 100644 index 0000000..b7a188e --- /dev/null +++ b/Chipset/SB/IDE.ASL @@ -0,0 +1,380 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/IDE.ASL 2 10/12/12 1:28a Scottyang $ +// +// $Revision: 2 $ +// +// $Date: 10/12/12 1:28a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/IDE.ASL $ +// +// 2 10/12/12 1:28a Scottyang +// [TAG] EIP83353 +// [Category] Improvement +// [Description] Correct IDE Mode SATA2 Ch1 Master timing. +// [Files] IDE.asl +// +// 1 2/08/12 8:25a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* + +DefinitionBlock ( + "Ide.aml", + "SSDT", + 1, + "IdeRef", + "IdeTable", + 0x1000 + ) +{ + +External(DSSP, IntObj) +External(FHPP, IntObj) +External(\_SB.PCI0.SAT0, DeviceObj) +External(\_SB.PCI0.SAT1, DeviceObj) + +Scope(\) +{ + // SATA Command Set + //---------------------------------------------------------------// + // Reg1 Reg2 Reg3 Reg4 Reg5 Reg6 Reg7 + //---------------------------------------------------------------// + Name(STFE, Buffer(){0x10, 0x06, 0x00, 0x00, 0x00, 0x00, 0xEF,}) // Set Features - Enable USE of SATA Feature + Name(STFD, Buffer(){0x90, 0x06, 0x00, 0x00, 0x00, 0x00, 0xEF,}) // Set Features - Disable USE of SATA Feature + Name(FZTF, Buffer(){0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 }) // Freeze Lock Command + Name(DCFL, Buffer(){0xC1, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB1 }) // Device Configuration Freeze Lock Command + + Name(SCBF, Buffer(21){}) // SATA Command Buffer to be returned + + // The number of SATA command + Name (CMDC, 0) // SATA Commands counter + + // Build the return buffer for GTF() control method + Method (GTFB, 2, Serialized) + // Arg0 - Command to write + // Arg1 - Subcommand value for "Set Feature command" + { + Multiply(CMDC, 56, Local0) + CreateField(SCBF, Local0, 56, CMDx) // Command field + Multiply(CMDC, 7, Local0) + CreateByteField(SCBF, Add(Local0, 1), A001) // Subcommand of "Set Feature" command + Store(Arg0, CMDx) // Store command into return buffer + Store(Arg1, A001) // Set Subcommand code + Increment(CMDC) + } +} + +Scope(\_SB.PCI0.SAT0) +{ + Name(REGF, 1) // PCI Bus access Flag + + Method(_REG, 2) // is PCI Config space accessible as OpRegion? + // _REG to update REGF status + { + If(LEqual(Arg0, 0x2)) + { + Store(Arg1, REGF) + } + } + // Buffer to be returned by _GTM + Name(TMD0, Buffer(20){}) // 5 DWORD length + CreateDWordField(TMD0, 00, PIO0) + CreateDWordField(TMD0, 04, DMA0) + CreateDWordField(TMD0, 8, PIO1) // do not use "08" + CreateDWordField(TMD0, 12, DMA1) + CreateDWordField(TMD0, 16, CHNF) + Device(CHN0) + { + Name(_ADR,0x00) + // Get Timing PIO/DMA Mode + Method(_GTM,0 ) { // Return Buffer + // PIO 0 Speed DWORD + // DMA 0 Speed DWORD + // PIO 1 Speed DWORD + // DMA 1 Speed DWORD + // Flags DWORD + + Store(120, PIO0) // Forced to PIO Mode 4 + Store(20, DMA0) // Forced to UDMA Mode 5 + Store(120, PIO1) // Forced to PIO Mode 4 + Store(20, DMA1) // Forced to UDMA Mode 5 + Store(0x05, CHNF) + Return (TMD0) + } // end Method _GTM +//////////////////////////////////////////////////////////////////////////////// + // Set Timing PIO/DMA Mode + Method(_STM, 3) // Arg 0 = Channel Timing Info (Package) + // Arg 1 = ATA Command set Master(Buffer) + // Arg 2 = ATA Command set Slave (Buffer) + { } // end Method _STM +//////////////////////////////////////////////////////////////////////////////// + + Device(DRV0) + { + Name(_ADR,0x00) + + // GET TASK FILE METHOD + Method(_GTF, 0, NotSerialized) { + Store(0, CMDC) // SATA Commands counter + If(LOr(DSSP, FHPP)) { // Check DISABLE_SOFT_SET_PREV SDL Token Enabled + // or FORCE_HDD_PASSWORD_PROMPT SDL Token Enabled + GTFB(STFD, 0x06) // Disable SW Preservation Settings + } else { + GTFB(STFE, 0x06) // Enable SW Preservation Settings + } + + GTFB(DCFL, 0x00) // Issue Device Configuration Freeze Lock Command + GTFB(FZTF, 0x00) // Issue Freeze Lock Command + Return(SCBF) + } + } + + Device(DRV1) + { + Name(_ADR,0x01) + + // GET TASK FILE METHOD + Method(_GTF, 0, NotSerialized) { + Store(0, CMDC) // SATA Commands counter + + If(LOr(DSSP, FHPP)) { // Check DISABLE_SOFT_SET_PREV SDL Token Enabled + // or FORCE_HDD_PASSWORD_PROMPT SDL Token Enabled + GTFB(STFD, 0x06) // Disable SW Preservation Settings + } else { + GTFB(STFE, 0x06) // Enable SW Preservation Settings + } + + GTFB(DCFL, 0x00) // Issue Device Configuration Freeze Lock Command + GTFB(FZTF, 0x00) // Issue Freeze Lock Command + Return(SCBF) + } + } + } + + Device(CHN1) + { + Name(_ADR,0x01) + +//////////////////////////////////////////////////////////////////////////////// + // Get Timing PIO/DMA Mode + Method(_GTM,0 ) { // Return Buffer + // PIO 0 Speed DWORD + // DMA 0 Speed DWORD + // PIO 1 Speed DWORD + // DMA 1 Speed DWORD + // Flags DWORD + + Store(120, PIO0) // Forced to PIO Mode 4 + Store(20, DMA0) // Forced to UDMA Mode 5 + Store(120, PIO1) // Forced to PIO Mode 4 + Store(20, DMA1) // Forced to UDMA Mode 5 + Store(0x05, CHNF) + + Return (TMD0) + } // end Method _GTM +//////////////////////////////////////////////////////////////////////////////// + // Set Timing PIO/DMA Mode + Method(_STM, 3) // Arg 0 = Channel Timing Info (Package) + // Arg 1 = ATA Command set Master(Buffer) + // Arg 2 = ATA Command set Slave (Buffer) + { } // end Method _STM +//////////////////////////////////////////////////////////////////////////////// + + Device(DRV0) + { + Name(_ADR,0x00) + + // GET TASK FILE METHOD + Method(_GTF, 0, NotSerialized) { + Store(0, CMDC) // SATA Commands counter + + If(LOr(DSSP, FHPP)) { // Check DISABLE_SOFT_SET_PREV SDL Token Enabled + // or FORCE_HDD_PASSWORD_PROMPT SDL Token Enabled + GTFB(STFD, 0x06) // Disable SW Preservation Settings + } else { + GTFB(STFE, 0x06) // Enable SW Preservation Settings + } + + GTFB(DCFL, 0x00) // Issue Device Configuration Freeze Lock Command + GTFB(FZTF, 0x00) // Issue Freeze Lock Command + Return(SCBF) + } + } + + Device(DRV1) + { + Name(_ADR,0x01) + + // GET TASK FILE METHOD + Method(_GTF, 0, NotSerialized) { + Store(0, CMDC) // SATA Commands counter + + If(LOr(DSSP, FHPP)) { // Check DISABLE_SOFT_SET_PREV SDL Token Enabled + // or FORCE_HDD_PASSWORD_PROMPT SDL Token Enabled + GTFB(STFD, 0x06) // Disable SW Preservation Settings + } else { + GTFB(STFE, 0x06) // Enable SW Preservation Settings + } + + GTFB(DCFL, 0x00) // Issue Device Configuration Freeze Lock Command + GTFB(FZTF, 0x00) // Issue Freeze Lock Command + Return(SCBF) + } + } + } +} + +Scope(\_SB.PCI0.SAT1) +{ + Name(REGF, 1) // PCI Bus access Flag + + Method(_REG, 2) // is PCI Config space accessible as OpRegion? + // _REG to update REGF status + { + If(LEqual(Arg0, 0x2)) + { + Store(Arg1, REGF) + } + } + + // Buffer to be returned by _GTM + Name(TMD0, Buffer(20){}) // 5 DWORD length + CreateDWordField(TMD0, 00, PIO0) + CreateDWordField(TMD0, 04, DMA0) + CreateDWordField(TMD0, 8, PIO1) // do not use "08" + CreateDWordField(TMD0, 12, DMA1) + CreateDWordField(TMD0, 16, CHNF) + + Device(CHN0) + { + Name(_ADR,0x00) + +//////////////////////////////////////////////////////////////////////////////// + // Get Timing PIO/DMA Mode + Method(_GTM,0 ) { // Return Buffer + // PIO 0 Speed DWORD + // DMA 0 Speed DWORD + // PIO 1 Speed DWORD + // DMA 1 Speed DWORD + // Flags DWORD + + Store(120, PIO0) // Forced to PIO Mode 4 + Store(20, DMA0) // Forced to UDMA Mode 5 + Store(120, PIO1) // Forced to PIO Mode 4 + Store(20, DMA1) // Forced to UDMA Mode 5 + Store(0x01, CHNF) + + Return (TMD0) + } // end Method _GTM +//////////////////////////////////////////////////////////////////////////////// + // Set Timing PIO/DMA Mode + Method(_STM, 3) // Arg 0 = Channel Timing Info (Package) + // Arg 1 = ATA Command set Master(Buffer) + // Arg 2 = ATA Command set Slave (Buffer) + { } // end Method _STM +//////////////////////////////////////////////////////////////////////////////// + + Device(DRV0) + { + Name(_ADR,0x00) + + // GET TASK FILE METHOD + Method(_GTF, 0, NotSerialized) { + Store(0, CMDC) // SATA Commands counter + + If(LOr(DSSP, FHPP)) { // Check DISABLE_SOFT_SET_PREV SDL Token Enabled + // or FORCE_HDD_PASSWORD_PROMPT SDL Token Enabled + GTFB(STFD, 0x06) // Disable SW Preservation Settings + } else { + GTFB(STFE, 0x06) // Enable SW Preservation Settings + } + + GTFB(DCFL, 0x00) // Issue Device Configuration Freeze Lock Command + GTFB(FZTF, 0x00) // Issue Freeze Lock Command + Return(SCBF) + } + } + } + + Device(CHN1) + { + Name(_ADR,0x01) + +//////////////////////////////////////////////////////////////////////////////// + // Get Timing PIO/DMA Mode + Method(_GTM,0 ) { // Return Buffer + // PIO 0 Speed DWORD + // DMA 0 Speed DWORD + // PIO 1 Speed DWORD + // DMA 1 Speed DWORD + // Flags DWORD + + Store(120, PIO0) // Forced to PIO Mode 4 + Store(20, DMA0) // Forced to UDMA Mode 5 + Store(120, PIO1) // Forced to PIO Mode 4 + Store(20, DMA1) // Forced to UDMA Mode 5 + Store(0x01, CHNF) + + Return (TMD0) + } // end Method _GTM +//////////////////////////////////////////////////////////////////////////////// + // Set Timing PIO/DMA Mode + Method(_STM, 3) // Arg 0 = Channel Timing Info (Package) + // Arg 1 = ATA Command set Master(Buffer) + // Arg 2 = ATA Command set Slave (Buffer) + { } // end Method _STM +//////////////////////////////////////////////////////////////////////////////// + + Device(DRV0) + { + Name(_ADR,0x01) + + // GET TASK FILE METHOD + Method(_GTF, 0, NotSerialized) { + Store(0, CMDC) // SATA Commands counter + + If(LOr(DSSP, FHPP)) { // Check DISABLE_SOFT_SET_PREV SDL Token Enabled + // or FORCE_HDD_PASSWORD_PROMPT SDL Token Enabled + GTFB(STFD, 0x06) // Disable SW Preservation Settings + } else { + GTFB(STFE, 0x06) // Enable SW Preservation Settings + } + + GTFB(DCFL, 0x00) // Issue Device Configuration Freeze Lock Command + GTFB(FZTF, 0x00) // Issue Freeze Lock Command + Return(SCBF) + } + } + } +} +}//end of SSDT + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//*************************************************************************
\ No newline at end of file diff --git a/Chipset/SB/PchWrap/PchSpiWrap/PchSpiWrap.c b/Chipset/SB/PchWrap/PchSpiWrap/PchSpiWrap.c new file mode 100644 index 0000000..237366a --- /dev/null +++ b/Chipset/SB/PchWrap/PchSpiWrap/PchSpiWrap.c @@ -0,0 +1,174 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/PchSpiWrap/PchSpiWrap.c 2 11/17/14 7:31a Mirayang $ +// +// $Revision: 2 $ +// +// $Date: 11/17/14 7:31a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/PchSpiWrap/PchSpiWrap.c $ +// +// 2 11/17/14 7:31a Mirayang +// [TAG] EIP191661 +// [Category] Improvement +// [Description] SUT can't generate UEFI SCT2.3.1 report completely. +// +// 1 2/08/12 8:33a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//---------------------------------------------------------------------- +// Includes +#include <AmiDxeLib.h> +#include <Protocol\LoadPe32Image.h> +#include "token.h" + + +static EFI_GUID gDxeSvcTblGuid = DXE_SERVICES_TABLE_GUID; +EFI_GUID gPchSpiRuntimeFFsGuid = \ + {0xC194C6EA,0xB68C,0x4981,0xB6,0x4B,0x9B,0xD2,0x71,0x47,0x4B,0x20}; + +EFI_STATUS +FFsLoaderToRuntime( + IN EFI_HANDLE ImageHandle +); + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: PchSpiWrapEntry +// +// Description: This function load PchSpi and execute it. +// +// Input: ImageHandle Image handle of this driver. +// SystemTable Global system service table. +// +// Output: EFI_SUCCESS Load and execute complete. +// EFI_UNSUPPORTED Image type is unsupported by this driver. +// EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +PchSpiWrapEntry( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + InitAmiLib(ImageHandle, SystemTable); + + Status = FFsLoaderToRuntime( ImageHandle); + ASSERT_EFI_ERROR (Status); + + return Status; +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: FFsLoaderToRuntime +// +// Description: Load FFs to Runtime. +// +// Input: ImageHandle Image handle of this driver. +// +// Output: EFI_SUCCESS FFs Load to Runtime complete. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +FFsLoaderToRuntime( + IN EFI_HANDLE ImageHandle +){ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS Dst; + EFI_PHYSICAL_ADDRESS EntryPoint; + EFI_PE32_IMAGE_PROTOCOL *LoadPeImageEx; + VOID *Buffer; + UINTN BufferSize; + UINT32 AuthenticationStatus; + UINTN Pages; + EFI_HANDLE FFsImageHandle; + EFI_DEVICE_PATH_PROTOCOL EndOfDp = { 0x7F, 0xFF, 0x4 , 0x0 }; + + Buffer = 0; + + Status = FvReadPe32Image ( + &gPchSpiRuntimeFFsGuid, + &Buffer, + &BufferSize, + &AuthenticationStatus + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + Pages = EFI_SIZE_TO_PAGES (BufferSize) + 2; + Status = pBS->AllocatePages ( + AllocateAnyPages, + EfiRuntimeServicesCode, + Pages, + &Dst + ); + + Status = pBS->LocateProtocol (&gEfiLoadPeImageGuid, NULL, &LoadPeImageEx); + if (EFI_ERROR (Status)) { + pBS->FreePool (&Dst); + return Status; + } + + Status = LoadPeImageEx->LoadPeImage( + LoadPeImageEx, + ImageHandle, +// NULL, + &EndOfDp, + Buffer, + BufferSize, + Dst, + &Pages, + &FFsImageHandle, + &EntryPoint, + EFI_LOAD_PE_IMAGE_ATTRIBUTE_NONE + ); + if (EFI_ERROR (Status)) { + pBS->FreePool (&Dst); + return Status; + } + + Status = pBS->StartImage(FFsImageHandle, NULL, NULL); + pBS->FreePool(Buffer); + + return Status; +} +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/PchWrap/PchSpiWrap/PchSpiWrap.cif b/Chipset/SB/PchWrap/PchSpiWrap/PchSpiWrap.cif new file mode 100644 index 0000000..7d6847b --- /dev/null +++ b/Chipset/SB/PchWrap/PchSpiWrap/PchSpiWrap.cif @@ -0,0 +1,11 @@ +<component> + name = "PchSpiWrap" + category = ModulePart + LocalRoot = "Chipset\SB\PchWrap\PchSpiWrap\" + RefName = "PchSpiWrap" +[files] +"PchSpiWrap.sdl" +"PchSpiWrap.mak" +"PchSpiWrap.c" +"PchSpiWrap.dxs" +<endComponent> diff --git a/Chipset/SB/PchWrap/PchSpiWrap/PchSpiWrap.dxs b/Chipset/SB/PchWrap/PchSpiWrap/PchSpiWrap.dxs new file mode 100644 index 0000000..432fc02 --- /dev/null +++ b/Chipset/SB/PchWrap/PchSpiWrap/PchSpiWrap.dxs @@ -0,0 +1,59 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/PchSpiWrap/PchSpiWrap.dxs 1 2/08/12 8:33a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:33a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/PchSpiWrap/PchSpiWrap.dxs $ +// +// 1 2/08/12 8:33a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: PchSpiWrap.dxs +// +// Description: This file is the dependency file for the Pch Spi Wrap driver. +// +//<AMI_FHDR_END> +//************************************************************************* + +#include <Protocol\Runtime.h> +#include <Protocol\PchPlatformPolicy\PchPlatformPolicy.h> + +DEPENDENCY_START + EFI_RUNTIME_ARCH_PROTOCOL_GUID AND + DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/PchWrap/PchSpiWrap/PchSpiWrap.mak b/Chipset/SB/PchWrap/PchSpiWrap/PchSpiWrap.mak new file mode 100644 index 0000000..c22d22d --- /dev/null +++ b/Chipset/SB/PchWrap/PchSpiWrap/PchSpiWrap.mak @@ -0,0 +1,58 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/PchSpiWrap/PchSpiWrap.mak 1 2/08/12 8:33a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 8:33a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/PchSpiWrap/PchSpiWrap.mak $ +# +# 1 2/08/12 8:33a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +all : PchSpiWrap + +PchSpiWrap : $(BUILD_DIR)\PchSpiWrap.mak PchSpiWrapBin + +$(BUILD_DIR)\PchSpiWrap.mak : $(PchSpiWrap_DIR)\$(@B).cif $(PchSpiWrap_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(PchSpiWrap_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +PchSpiWrapBin : $(AMICSPLib) $(AMIDXELIB) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\PchSpiWrap.mak all\ + GUID=B716A6F8-F3A1-4b8e-8582-5A303F1CDD64\ + "MY_INCLUDES=$(INTEL_PCH_INCLUDES)"\ + ENTRY_POINT=PchSpiWrapEntry\ + TYPE=RT_DRIVER \ + DEPEX1=$(PchSpiWrap_DIR)\PchSpiWrap.DXS DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + COMPRESS=1 +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/SB/PchWrap/PchSpiWrap/PchSpiWrap.sdl b/Chipset/SB/PchWrap/PchSpiWrap/PchSpiWrap.sdl new file mode 100644 index 0000000..950af3e --- /dev/null +++ b/Chipset/SB/PchWrap/PchSpiWrap/PchSpiWrap.sdl @@ -0,0 +1,75 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/PchSpiWrap/PchSpiWrap.sdl 1 2/08/12 8:32a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 8:32a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/PchSpiWrap/PchSpiWrap.sdl $ +# +# 1 2/08/12 8:32a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = PchSpiWrap_SUPPORT + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable PchSpiWrap support in Project" +End + +MODULE + Help = "Includes PchSpiWrap.mak to Project" + File = "PchSpiWrap.mak" +End + +PATH + Name = "PchSpiWrap_DIR" +End + +TOKEN + Name = "PchSpiRuntime_GUID" + Value = "C194C6EA-B68C-4981-B64B-9BD271474B20" + Help = "GUID of AP initialization file." + TokenType = Expression + TargetMAK = Yes + TargetH = Yes +End + +ELINK + Name = "$(BUILD_DIR)\PchSpiWrap.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Chipset/SB/PchWrap/PchWrap.cif b/Chipset/SB/PchWrap/PchWrap.cif new file mode 100644 index 0000000..18da186 --- /dev/null +++ b/Chipset/SB/PchWrap/PchWrap.cif @@ -0,0 +1,13 @@ +<component> + name = "PchWrap" + category = ModulePart + LocalRoot = "Chipset\SB\PchWrap\" + RefName = "PchWrap" +[files] +"PchWrap.sdl" +[parts] +"PchSpiWrap" +"WdtApp" +"PciHotPlug" +"SmBusMemoryDown" +<endComponent> diff --git a/Chipset/SB/PchWrap/PchWrap.sdl b/Chipset/SB/PchWrap/PchWrap.sdl new file mode 100644 index 0000000..ab9167e --- /dev/null +++ b/Chipset/SB/PchWrap/PchWrap.sdl @@ -0,0 +1,52 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/PchWrap.sdl 1 2/08/12 8:32a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 8:32a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/PchWrap.sdl $ +# +# 1 2/08/12 8:32a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "PchWrap_SUPPORT" + Value = "1" + Help = "Main switch to enable PchWrap support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes +End + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/SB/PchWrap/PciHotPlug/PciHotPlug.c b/Chipset/SB/PchWrap/PciHotPlug/PciHotPlug.c new file mode 100644 index 0000000..34540d7 --- /dev/null +++ b/Chipset/SB/PchWrap/PciHotPlug/PciHotPlug.c @@ -0,0 +1,544 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/PciHotPlug/PciHotPlug.c 6 5/16/14 5:56p Barretlin $ +// +// $Revision: 6 $ +// +// $Date: 5/16/14 5:56p $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/PciHotPlug/PciHotPlug.c $ +// +// 6 5/16/14 5:56p Barretlin +// [TAG] EIP165410 +// [Category] Improvement +// [Description] Support Thunderbolt AIC at NB PCIE slot +// [Files] PciHotplug.c +// +// 5 5/14/14 1:15p Barretlin +// [TAG] EIP165410 +// [Category] New Feature +// [Description] Support Thunderbolt AIC at NB PCIE slot +// [Files] PciHotPlug.c +// +// 4 4/24/13 5:02a Scottyang +// +// 3 9/12/12 5:15a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Modify for Thunderbolt support. +// [Files] GetSetupData.c, SB.sdl, SB.sd, SB.uni, SbSetupData.h, +// PciHotPlug.c +// +// 2 5/03/12 6:30a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Modify to support Thunderbolt. +// [Files] SB.sd; SB.uni; SB.sdl; SbSetupData.h; PciHotPlug.c +// +// 1 2/08/12 8:37a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* + +// +// Statements that include other files +// +#include "PciHotPlug.h" +#include <token.h> + +#define PCIE_NUM (11) + +// +// Instantiation of Driver private data. +// +PCIE_HOT_PLUG_DEVICE_PATH mPcieList[PCIE_NUM] = { + { + ACPI, + PCI(0x1C, 0), + END + }, // PCI Express 0 + { + ACPI, + PCI(0x1C, 1), + END + }, // PCI Express 1 + { + ACPI, + PCI(0x1C, 2), + END + }, // PCI Express 2 + { + ACPI, + PCI(0x1C, 3), + END + }, // PCI Express 3 + { + ACPI, + PCI(0x1C, 4), + END + }, // PCI Express 4 + { + ACPI, + PCI(0x1C, 5), + END + }, // PCI Express 5 + { + ACPI, + PCI(0x1C, 6), + END + }, // PCI Express 6 + { + ACPI, + PCI(0x1C, 7), + END + }, // PCI Express 7 + { + ACPI, + PCI(0x01, 0), + END + }, // NB PCI Express 0 + { + ACPI, + PCI(0x01, 1), + END + }, // NB PCI Express 1 + { + ACPI, + PCI(0x01, 2), + END + }, // NB PCI Express 2 +}; + +EFI_HPC_LOCATION mPcieLocation[PCIE_NUM] = { + { + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[0], + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[0] + }, + { + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[1], + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[1] + }, + { + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[2], + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[2] + }, + { + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[3], + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[3] + }, + { + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[4], + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[4] + }, + { + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[5], + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[5] + }, + { + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[6], + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[6] + }, + { + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[7], + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[7] + }, + { + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[8], + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[8] + }, + { + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[9], + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[9] + }, + { + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[10], + (EFI_DEVICE_PATH_PROTOCOL *) &mPcieList[10] + }, +}; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: PciHotPlug +// +// Description: This routine reads the PlatformType GPI on FWH and produces a protocol +// to be consumed by the chipset driver to effect those settings. +// +// Input: ImageHandle An image handle. +// SystemTable A pointer to the system table. +// +// Output: EFI_SUCCESS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +PciHotPlug ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + PCI_HOT_PLUG_INSTANCE *PciHotPlug; + + + PciHotPlug = AllocatePool (sizeof (PCI_HOT_PLUG_INSTANCE)); + ASSERT (PciHotPlug != NULL); + + // + // Initialize driver private data. + // + ZeroMem (PciHotPlug, sizeof (PCI_HOT_PLUG_INSTANCE)); + + PciHotPlug->Signature = PCI_HOT_PLUG_DRIVER_PRIVATE_SIGNATURE; + PciHotPlug->HotPlugInitProtocol.GetRootHpcList = GetRootHpcList; + PciHotPlug->HotPlugInitProtocol.InitializeRootHpc = InitializeRootHpc; + PciHotPlug->HotPlugInitProtocol.GetResourcePadding = GetResourcePadding; + + Status = gBS->InstallProtocolInterface ( + &PciHotPlug->Handle, + &gEfiPciHotPlugInitProtocolGuid, + EFI_NATIVE_INTERFACE, + &PciHotPlug->HotPlugInitProtocol + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetRootHpcList +// +// Description: This procedure returns a list of Root Hot Plug controllers +// that require initialization during boot process +// +// Input: This The pointer to the instance of the +// EFI_PCI_HOT_PLUG_INIT protocol. +// HpcCount The number of Root HPCs returned. +// HpcList The list of Root HPCs. HpcCount defines the +// number of elements in this list. +// +// Output: EFI_SUCCESS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +GetRootHpcList ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + OUT UINTN *HpcCount, + OUT EFI_HPC_LOCATION **HpcList + ) +{ + + *HpcCount = PCIE_NUM; + *HpcList = mPcieLocation; + + return EFI_SUCCESS; +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitializeRootHpc +// +// Description: This procedure Initializes one Root Hot Plug Controller +// This process may casue initialization of its subordinate buses +// +// Input: This The pointer to the instance of the +// EFI_PCI_HOT_PLUG_INIT protocol. +// HpcDevicePath The Device Path to the HPC that is being initialized. +// HpcPciAddress The address of the Hot Plug Controller function +// on the PCI bus. +// Event The event that should be signaled when the Hot +// Plug Controller initialization is complete. +// Set to NULL if the caller wants to wait until +// the entire initialization process is complete. +// The event must be of the type EFI_EVT_SIGNAL. +// HpcState The state of the Hot Plug Controller hardware. +// The type EFI_Hpc_STATE is defined in section 3.1. +// +// Output: EFI_SUCCESS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +InitializeRootHpc ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath, + IN UINT64 HpcPciAddress, + IN EFI_EVENT Event, OPTIONAL + OUT EFI_HPC_STATE *HpcState + ) +{ + if (Event) { + gBS->SignalEvent (Event); + } + + *HpcState = EFI_HPC_STATE_INITIALIZED; + + return EFI_SUCCESS; +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetResourcePadding +// +// Description: Returns the resource padding required by the PCI bus that is +// controlled by the specified Hot Plug Controller. +// +// Input: This The pointer to the instance of the +// EFI_PCI_HOT_PLUG_INIT protocol. +// HpcDevicePath The Device Path to the HPC that is being initialized. +// HpcPciAddress The address of the Hot Plug Controller function +// on the PCI bus. +// HpcState The state of the Hot Plug Controller hardware. +// The type EFI_Hpc_STATE is defined in section 3.1. +// Padding This is the amount of resource padding required +// by the PCI bus under the control of the specified Hpc. +// Since the caller does not know the size of this buffer, +// this buffer is allocated by the callee and freed by the +// caller. +// Attribute Describes how padding is accounted for. +// +// Output: EFI_SUCCESS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +GetResourcePadding ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath, + IN UINT64 HpcPciAddress, + OUT EFI_HPC_STATE *HpcState, + OUT VOID **Padding, + OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *PaddingResource; + EFI_STATUS Status; + UINT8 FindRP; + UINT8 RsvdExtraBusNum = 0; + // (SB082311A)> + UINT16 RsvdPcieMegaMem = 0; + UINT8 RsvdPcieKiloIo = 0; + UINT16 RsvdPcieMegaPFMem = 0; + UINT8 RsvdPcieMegaMemalig = 0; + UINT8 RsvdPcieMegaPFMemalig = 0; + // <(SB082311A) + UINTN VariableSize; + SETUP_DATA SetupData; + EFI_GUID SetupGuid = SETUP_GUID; + UINT32 RPFN; //Root Port Function Number + UINT8 SwRPFN; + + PaddingResource = AllocatePool (PCIE_NUM * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); + ASSERT (PaddingResource != NULL); + + *Padding = (VOID *) PaddingResource; + + RPFN = MmioRead32(SB_RCRB_BASE_ADDRESS + R_PCH_RCRB_RPFN); + DEBUG((EFI_D_INFO, "\nRCBA RPFN = %x\n", RPFN)); + // + // Check if PCIe Root Hob Controller need to reserve bus for docking downstream P2P hotplug + // + + VariableSize = sizeof(SETUP_DATA); + Status = gRT->GetVariable(L"Setup", + &SetupGuid, + NULL, + &VariableSize, + &SetupData); + + for (FindRP = 0; FindRP < PCIE_NUM; FindRP ++) { + if (HpcPciAddress == EFI_PCI_ADDRESS(0, 0x1C, FindRP, 0)) { + if (!EFI_ERROR(Status)) { + switch (FindRP){ + case 0: + SwRPFN = (UINT8)(RPFN & B_PCH_RCRB_RPFN_RP1FN); + break; + case 1: + SwRPFN = (UINT8)((RPFN & B_PCH_RCRB_RPFN_RP2FN) >> 4); + break; + case 2: + SwRPFN = (UINT8)((RPFN & B_PCH_RCRB_RPFN_RP3FN) >> 8); + break; + case 3: + SwRPFN = (UINT8)((RPFN & B_PCH_RCRB_RPFN_RP4FN) >> 12); + break; + case 4: + SwRPFN = (UINT8)((RPFN & B_PCH_RCRB_RPFN_RP5FN) >> 16); + break; + case 5: + SwRPFN = (UINT8)((RPFN & B_PCH_RCRB_RPFN_RP6FN) >> 20); + break; + case 6: + SwRPFN = (UINT8)((RPFN & B_PCH_RCRB_RPFN_RP7FN) >> 24); + break; + case 7: + SwRPFN = (UINT8)((RPFN & B_PCH_RCRB_RPFN_RP8FN) >> 28); + break; + default: + ASSERT_EFI_ERROR(EFI_DEVICE_ERROR); + } + DEBUG((EFI_D_INFO, "FindRP = %x\nSwRPFN = %x\n", FindRP, SwRPFN)); +#if (defined SB_SETUP_SUPPORT && SB_SETUP_SUPPORT) || \ + (defined OEM_SB_SETUP_SUPPORT && OEM_SB_SETUP_SUPPORT) + if (SwRPFN == FindRP) { + DEBUG((EFI_D_INFO, "PCIE Root Port#%x does not swap...\n", FindRP)); + if (SetupData.PcieRootPortHPE[FindRP]){ + RsvdExtraBusNum = SetupData.ExtraBusRsvd[FindRP]; + RsvdPcieMegaMem = SetupData.PcieMemRsvd[FindRP]; + RsvdPcieMegaPFMem = SetupData.PciePFMemRsvd[FindRP]; + RsvdPcieKiloIo = SetupData.PcieIoRsvd[FindRP]; + RsvdPcieMegaMemalig = SetupData.PcieMemRsvdalig[FindRP]; + RsvdPcieMegaPFMemalig = SetupData.PciePFMemRsvdalig[FindRP]; + } + } + else{ + DEBUG((EFI_D_INFO, "PCIE Root Port#%x is mapping to PCIE slot#%x...\n", FindRP, SwRPFN)); + if (SetupData.PcieRootPortHPE[SwRPFN]){ + RsvdExtraBusNum = SetupData.ExtraBusRsvd[SwRPFN]; + RsvdPcieMegaMem = SetupData.PcieMemRsvd[SwRPFN]; + RsvdPcieMegaPFMem = SetupData.PciePFMemRsvd[SwRPFN]; + RsvdPcieKiloIo = SetupData.PcieIoRsvd[SwRPFN]; + RsvdPcieMegaMemalig = SetupData.PcieMemRsvdalig[SwRPFN]; + RsvdPcieMegaPFMemalig = SetupData.PciePFMemRsvdalig[SwRPFN]; + } + } +#endif + } + break; + } // SB PCIE root port +#if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 + if (HpcPciAddress == EFI_PCI_ADDRESS(0, 0x01, (FindRP - 8), 0)) { + if (!EFI_ERROR(Status)) { + DEBUG((EFI_D_INFO, "Hotplug root port is NB PCIE root port\n")); + if ((SetupData.TbtEnable != 0) && (SetupData.TbtHostLocation >= 0x20) && (SetupData.TbtHostLocation < 0x23)){ + DEBUG((EFI_D_INFO, "Update resource for NB PCIE root port\n")); + RsvdExtraBusNum = TBT_DEFAULT_EXTRA_BUS_RESERVED; + RsvdPcieMegaMem = TBT_DEFAULT_PCIE_MEM_RESERVED; + RsvdPcieMegaPFMem = TBT_DEFAULT_PCIE_PF_MEM_RESERVED; + RsvdPcieKiloIo = TBT_DEFAULT_PCIE_IO_RESERVED; + RsvdPcieMegaMemalig = 26; + RsvdPcieMegaPFMemalig = 28; + } + } + } // NB PCIE root port +#endif + } // for loop + + // + // Padding for bus + // + ZeroMem (PaddingResource, PCIE_NUM * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); + *Attributes = EfiPaddingPciBus; + + PaddingResource->Desc = 0x8A; + PaddingResource->Len = 0x2B; + PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS; + PaddingResource->GenFlag = 0x0; + PaddingResource->SpecificFlag = 0; + PaddingResource->AddrRangeMin = 0; + PaddingResource->AddrRangeMax = 0; + PaddingResource->AddrLen = RsvdExtraBusNum; + + // + // Padding for non-prefetchable memory + // + PaddingResource++; + PaddingResource->Desc = 0x8A; + PaddingResource->Len = 0x2B; + PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; + PaddingResource->GenFlag = 0x0; + PaddingResource->AddrSpaceGranularity = 32; + PaddingResource->SpecificFlag = 0; + // + // Pad non-prefetchable + // + PaddingResource->AddrRangeMin = 0; + PaddingResource->AddrLen = RsvdPcieMegaMem * 0x100000; + PaddingResource->AddrRangeMax = (1 << RsvdPcieMegaMemalig) - 1; // 0x3FFFFFF + + // + // Padding for prefetchable memory + // + PaddingResource++; + PaddingResource->Desc = 0x8A; + PaddingResource->Len = 0x2B; + PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM; + PaddingResource->GenFlag = 0x0; + PaddingResource->AddrSpaceGranularity = 32; + PaddingResource->SpecificFlag = 06; + // + // Padding for prefetchable memory + // + PaddingResource->AddrRangeMin = 0; + PaddingResource->AddrLen = RsvdPcieMegaPFMem * 0x100000; + // + // Pad 16 MB of MEM + // + PaddingResource->AddrRangeMax = (1 << RsvdPcieMegaPFMemalig) - 1; // 0xfffffff + // + // Alignment + // + // Padding for I/O + // + PaddingResource++; + PaddingResource->Desc = 0x8A; + PaddingResource->Len = 0x2B; + PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_IO; + PaddingResource->GenFlag = 0x0; + PaddingResource->SpecificFlag = 0; + PaddingResource->AddrRangeMin = 0; + PaddingResource->AddrLen = RsvdPcieKiloIo * 0x400; + // + // Pad 4K of IO + // + PaddingResource->AddrRangeMax = 1; + // + // Alignment + // + // Terminate the entries. + // + PaddingResource++; + ((EFI_ACPI_END_TAG_DESCRIPTOR *) PaddingResource)->Desc = ACPI_END_TAG_DESCRIPTOR; + ((EFI_ACPI_END_TAG_DESCRIPTOR *) PaddingResource)->Checksum = 0x0; + + *HpcState = EFI_HPC_STATE_INITIALIZED | EFI_HPC_STATE_ENABLED; + + return EFI_SUCCESS; +} +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + diff --git a/Chipset/SB/PchWrap/PciHotPlug/PciHotPlug.cif b/Chipset/SB/PchWrap/PciHotPlug/PciHotPlug.cif new file mode 100644 index 0000000..5a46b95 --- /dev/null +++ b/Chipset/SB/PchWrap/PciHotPlug/PciHotPlug.cif @@ -0,0 +1,12 @@ +<component> + name = "PciHotPlug" + category = ModulePart + LocalRoot = "Chipset\SB\PchWrap\PciHotPlug" + RefName = "PciHotPlug" +[files] +"PciHotPlug.sdl" +"PciHotPlug.mak" +"PciHotPlug.c" +"PciHotPlug.h" +"PciHotPlug.dxs" +<endComponent> diff --git a/Chipset/SB/PchWrap/PciHotPlug/PciHotPlug.dxs b/Chipset/SB/PchWrap/PciHotPlug/PciHotPlug.dxs new file mode 100644 index 0000000..d6a5059 --- /dev/null +++ b/Chipset/SB/PchWrap/PciHotPlug/PciHotPlug.dxs @@ -0,0 +1,61 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/PciHotPlug/PciHotPlug.dxs 1 2/08/12 8:37a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:37a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/PciHotPlug/PciHotPlug.dxs $ +// +// 1 2/08/12 8:37a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* + +// +// Common for R8 and R9 codebase +// +#include "AutoGen.h" +#include "DxeDepex.h" + +// +// BUILD_WITH_GLUELIB is turned "on" in R8 codebase; +// BUILD_WITH_GLUELIB is turned "off" in R9 codebase. +// +#ifdef BUILD_WITH_GLUELIB +#include "EfiDepex.h" +#endif + +DEPENDENCY_START + TRUE +DEPENDENCY_END +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + diff --git a/Chipset/SB/PchWrap/PciHotPlug/PciHotPlug.h b/Chipset/SB/PchWrap/PciHotPlug/PciHotPlug.h new file mode 100644 index 0000000..295e721 --- /dev/null +++ b/Chipset/SB/PchWrap/PciHotPlug/PciHotPlug.h @@ -0,0 +1,198 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/PciHotPlug/PciHotPlug.h 2 4/24/13 5:02a Scottyang $ +// +// $Revision: 2 $ +// +// $Date: 4/24/13 5:02a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/PciHotPlug/PciHotPlug.h $ +// +// 2 4/24/13 5:02a Scottyang +// +// 1 2/08/12 8:37a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* + +#ifndef _PCI_HOT_PLUG_H_ +#define _PCI_HOT_PLUG_H_ + +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined (EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) + +#include "EdkIIGlueDxe.h" + +#include "PchRegs.h" +#include "PchRegsRcrb.h" + +#include EFI_PROTOCOL_DEFINITION (PciHotPlugInit) +#include EFI_PROTOCOL_DEFINITION (PciRootBridgeIo) +#include "Acpi.h" + +// without these include guards, setup.h would include AMI EFI definitions conflicting with those from EDK +#define __UEFI_HII__H__ +#if EFI_SPECIFICATION_VERSION >= 0x2000A +#define __HII_CONFIG_ACCESS__H__ +#else +#define __HII_PROTOCOL_H__ +#define _HII_H_ +#define __FORM_CALLBACK_PROTOCOL_H__ +#endif +#include <Setup.h> +#endif + +#define PCI_HOT_PLUG_DRIVER_PRIVATE_SIGNATURE EFI_SIGNATURE_32 ('G', 'U', 'L', 'P') + +#define ACPI \ + { \ + ACPI_DEVICE_PATH, ACPI_DP, (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), (UINT8) \ + ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8), EISA_PNP_ID (0x0A03), 0 \ + } + +#define PCI(device, function) \ + { \ + HARDWARE_DEVICE_PATH, HW_PCI_DP, (UINT8) (sizeof (PCI_DEVICE_PATH)), (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8), \ + (UINTN) function, (UINTN) device \ + } + +#define END \ + { \ + END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, END_DEVICE_PATH_LENGTH, 0 \ + } + +#define LPC(eisaid, function) \ + { \ + ACPI_DEVICE_PATH, ACPI_DP, (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), (UINT8) \ + ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8), EISA_PNP_ID (eisaid), function \ + } + +typedef struct PCIE_HOT_PLUG_DEVICE_PATH { + ACPI_HID_DEVICE_PATH PciRootBridgeNode; + PCI_DEVICE_PATH PciRootPortNode; + EFI_DEVICE_PATH_PROTOCOL EndDeviceNode; +} PCIE_HOT_PLUG_DEVICE_PATH; + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; // Handle for protocol this driver installs on + EFI_PCI_HOT_PLUG_INIT_PROTOCOL HotPlugInitProtocol; +} PCI_HOT_PLUG_INSTANCE; + +EFI_STATUS +GetRootHpcList ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + OUT UINTN *PhpcCount, + OUT EFI_HPC_LOCATION **PhpcList + ) +/*++ + +Routine Description: + + This procedure returns a list of Root Hot Plug controllers that require + initialization during boot process + +Arguments: + + This - The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol. + PhpcCount - The number of Root HPCs returned. + PhpcList - The list of Root HPCs. HpcCount defines the number of elements in this list. +Returns: + + EFI_SUCCESS. + +--*/ +; + +EFI_STATUS +InitializeRootHpc ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *PhpcDevicePath, + IN UINT64 PhpcPciAddress, + IN EFI_EVENT Event, OPTIONAL + OUT EFI_HPC_STATE *PhpcState + ) +/*++ + +Routine Description: + + This procedure Initializes one Root Hot Plug Controller + This process may casue initialization of its subordinate buses + +Arguments: + + This - The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol. + PhpcDevicePath - The Device Path to the HPC that is being initialized. + PhpcPciAddress - The address of the Hot Plug Controller function on the PCI bus. + Event - The event that should be signaled when the Hot Plug Controller initialization is complete. Set to NULL if the caller wants to wait until the entire initialization process is complete. The event must be of the type EFI_EVT_SIGNAL. + PhpcState - The state of the Hot Plug Controller hardware. The type EFI_Hpc_STATE is defined in section 3.1. + +Returns: + + EFI_SUCCESS. +--*/ +; + +EFI_STATUS +GetResourcePadding ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *PhpcDevicePath, + IN UINT64 PhpcPciAddress, + OUT EFI_HPC_STATE *PhpcState, + OUT VOID **Padding, + OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes + ) +/*++ + +Routine Description: + + Returns the resource padding required by the PCI bus that is controlled by the specified Hot Plug Controller. + +Arguments: + + This - The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol. initialized. + PhpcDevicePath - The Device Path to the Hot Plug Controller. + PhpcPciAddress - The address of the Hot Plug Controller function on the PCI bus. + PhpcState - The state of the Hot Plug Controller hardware. The type EFI_HPC_STATE is defined in section 3.1. + Padding - This is the amount of resource padding required by the PCI bus under the control of the specified Hpc. Since the caller does not know the size of this buffer, this buffer is allocated by the callee and freed by the caller. + Attributes - Describes how padding is accounted for. + +Returns: + + EFI_SUCCESS. +--*/ +; + +#endif +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + diff --git a/Chipset/SB/PchWrap/PciHotPlug/PciHotPlug.mak b/Chipset/SB/PchWrap/PciHotPlug/PciHotPlug.mak new file mode 100644 index 0000000..62c3a01 --- /dev/null +++ b/Chipset/SB/PchWrap/PciHotPlug/PciHotPlug.mak @@ -0,0 +1,98 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/PciHotPlug/PciHotPlug.mak 2 2/24/12 2:00a Victortu $ +# +# $Revision: 2 $ +# +# $Date: 2/24/12 2:00a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/PciHotPlug/PciHotPlug.mak $ +# +# 2 2/24/12 2:00a Victortu +# Updated to support 4.6.5.3_IntelEDK_1117_Patch7_00. +# +# 1 2/08/12 8:37a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +#--------------------------------------------------------------------------- +# Create PciHotPlug Driver +#--------------------------------------------------------------------------- +EDK : PciHotPlug + +PciHotPlug : $(BUILD_DIR)\PciHotPlug.mak PciHotPlugBin + +$(BUILD_DIR)\PciHotPlug.mak : $(PciHotPlug_DIR)\$(@B).cif $(PciHotPlug_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(PciHotPlug_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +PciHotPlug_INCLUDES=\ + $(INTEL_PCH_INCLUDES)\ + $(EdkIIGlueLib_INCLUDES)\ + $(NB_INCLUDES)\ + $(SB_INCLUDES)\ + /I$(PROJECT_DIR)\ + /IInclude\ + +PciHotPlug_DEFINES = $(MY_DEFINES)\ + /D"__EDKII_GLUE_MODULE_ENTRY_POINT__=PciHotPlug"\ + /D __EDKII_GLUE_BASE_MEMORY_LIB__ \ + /D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \ + /D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \ + /D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \ + /D __EDKII_GLUE_DXE_MEMORY_ALLOCATION_LIB__ \ + +PciHotPlug_LIB_LINKS =\ + $(EDKPROTOCOLLIB) \ + $(EdkIIGlueBaseLib_LIB)\ +!IF "$(x64_BUILD)"=="1" + $(EdkIIGlueBaseLibX64_LIB)\ +!ELSE + $(EdkIIGlueBaseLibIA32_LIB)\ +!ENDIF + $(EdkIIGlueBaseMemoryLib_LIB)\ + $(EdkIIGlueDxeReportStatusCodeLib_LIB)\ + $(EdkIIGlueDxeDebugLibReportStatusCode_LIB)\ + $(EdkIIGlueUefiBootServicesTableLib_LIB)\ + $(EdkIIGlueDxeMemoryAllocationLib_LIB)\ + $(EDKFRAMEWORKPROTOCOLLIB) + +PciHotPlugBin: $(PciHotPlug_LIB_LINKS) + $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\ + /f $(BUILD_DIR)\PciHotPlug.mak all \ + "MY_INCLUDES=$(PciHotPlug_INCLUDES)"\ + "MY_DEFINES=$(PciHotPlug_DEFINES)"\ + GUID=3022E512-B94A-4f12-806D-7EF1177899D8\ + ENTRY_POINT=_ModuleEntryPoint \ + TYPE=BS_DRIVER\ + EDKIIModule=DXEDRIVER\ + DEPEX1=$(PciHotPlug_DIR)\PciHotPlug.dxs\ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\ + COMPRESS=1 +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/SB/PchWrap/PciHotPlug/PciHotPlug.sdl b/Chipset/SB/PchWrap/PciHotPlug/PciHotPlug.sdl new file mode 100644 index 0000000..4a3cbf9 --- /dev/null +++ b/Chipset/SB/PchWrap/PciHotPlug/PciHotPlug.sdl @@ -0,0 +1,75 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/PciHotPlug/PciHotPlug.sdl 1 2/08/12 8:37a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 8:37a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/PciHotPlug/PciHotPlug.sdl $ +# +# 1 2/08/12 8:37a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "PciHotPlug_SUPPORT" + Value = "1" + Help = "Main switch to enable PciHotPlug support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Token = "AMI_ROOT_BRIDGE_SUPPORT" "=" "0" + Token = "HOTPLUG_SUPPORT" "=" "1" +End + +MODULE + Help = "Includes PciHotPlug to Project" + File = "PciHotPlug.mak" +End + + +ELINK + Name = "PciHotPlug" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "$(BUILD_DIR)\PciHotPlug.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + +PATH + Name = "PciHotPlug_DIR" +End + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/SB/PchWrap/SmBusMemoryDown/SmBusMemoryDown.c b/Chipset/SB/PchWrap/SmBusMemoryDown/SmBusMemoryDown.c new file mode 100644 index 0000000..8e081d1 --- /dev/null +++ b/Chipset/SB/PchWrap/SmBusMemoryDown/SmBusMemoryDown.c @@ -0,0 +1,252 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/SmBusMemoryDown.c 1 12/11/12 1:09a Scottyang $ +// +// $Date: 12/11/12 1:09a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SmBusMemoryDown.c +// +// Description: SmBus support MemoryDown functions implementation +// +//<AMI_FHDR_END> +//************************************************************************* + +#include <efi.h> +#include <AmiDxeLib.h> +#include <AmiCspLib.h> +#include <Protocol\SmBus.h> + +EFI_SMBUS_HC_PROTOCOL *SmBusProtocol = NULL; +static EFI_SMBUS_HC_EXECUTE_OPERATION PchSmBusExecute = NULL; +EFI_EVENT gSmBusMemoryDownEvent; +VOID *gSmBusMemoryDownEventReg; +UINT8 IsRunMemoryDown = 0; +EFI_GUID gEfiSMBusProtocolGuid = EFI_SMBUS_HC_PROTOCOL_GUID; + +#ifndef AMI_OVERRIDE_FOR_MEMORY_DOWN +#if defined(NB_OEM_DIMM1_STATUS) && (NB_OEM_DIMM1_STATUS == 0x02) +static UINT8 Dimm1SpdTbl[] = NB_OEM_DIMM1_SPD_DATA; +#endif +#if defined(NB_OEM_DIMM2_STATUS) && (NB_OEM_DIMM2_STATUS == 0x02) +static UINT8 Dimm2SpdTbl[] = NB_OEM_DIMM2_SPD_DATA; +#endif +#if defined(NB_OEM_DIMM3_STATUS) && (NB_OEM_DIMM3_STATUS == 0x02) +static UINT8 Dimm3SpdTbl[] = NB_OEM_DIMM3_SPD_DATA; +#endif +#if defined(NB_OEM_DIMM4_STATUS) && (NB_OEM_DIMM4_STATUS == 0x02) +static UINT8 Dimm4SpdTbl[] = NB_OEM_DIMM4_SPD_DATA; +#endif +#endif // AMI_OVERRIDE_FOR_MEMORY_DOWN + +VOID OverrideSmBusNotify ( + IN EFI_EVENT Event, + IN VOID *Context +); + + +//************************************************************************* +//<AMI_PHDR_START> +// +// Procedure: OverrideSmBusExecute +// +// Description: Init SmBus MemoryDown Protocol Execute.. +// +// Input: +// +// Output: +// +//<AMI_PHDR_END> +//************************************************************************* +EFI_STATUS +EFIAPI +OverrideSmBusExecute ( + IN EFI_SMBUS_HC_PROTOCOL *This, + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN EFI_SMBUS_DEVICE_COMMAND Command, + IN EFI_SMBUS_OPERATION Operation, + IN BOOLEAN PecCheck, + IN OUT UINTN *Length, + IN OUT VOID *Buffer + ) +{ + UINT8 *DimmSpd = NULL; + UINT8 *BufferPoint = Buffer; + UINT16 i = 0; + + if (IsRunMemoryDown) { +#ifdef NB_OEM_DIMM1_SPD_DATA + if(SlaveAddress.SmbusDeviceAddress == DIMM1_SMBUS_ADDRESS >> 1) { + DimmSpd = Dimm1SpdTbl; + } +#endif +#ifdef NB_OEM_DIMM2_SPD_DATA + if(SlaveAddress.SmbusDeviceAddress == DIMM2_SMBUS_ADDRESS >> 1) { + DimmSpd = Dimm2SpdTbl; + } +#endif +#ifdef NB_OEM_DIMM3_SPD_DATA + if(SlaveAddress.SmbusDeviceAddress == DIMM3_SMBUS_ADDRESS >> 1) { + DimmSpd = Dimm3SpdTbl; + } +#endif +#ifdef NB_OEM_DIMM4_SPD_DATA + if(SlaveAddress.SmbusDeviceAddress == DIMM4_SMBUS_ADDRESS >> 1) { + DimmSpd = Dimm4SpdTbl; + } +#endif + if (DimmSpd != NULL) { + for (i=0; i <= *Length; i++) { + *BufferPoint = DimmSpd[Command + i]; + BufferPoint++; + } + return EFI_SUCCESS; + } + } + + return PchSmBusExecute ( + This, + SlaveAddress, + Command, + Operation, + PecCheck, + Length, + Buffer + ); + +} +//************************************************************************* +//<AMI_PHDR_START> +// +// Procedure: OverrideSmBusNotify +// +// Description: Override SmBus Protocol Execute. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This, +// IN UINT32 Start, +// IN UINT32 Length, +// OUT UINT32 *Granularity, +// IN BOOLEAN *On +// +// Output: +// Status of the operation +// +//<AMI_PHDR_END> +//************************************************************************* +VOID OverrideSmBusNotify ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + EFI_STATUS Status; + + Status = pBS->LocateProtocol (&gEfiSmbusProtocolGuid, NULL, (VOID**) &SmBusProtocol); + if (!EFI_ERROR (Status)) { + + PchSmBusExecute = SmBusProtocol->Execute; + SmBusProtocol->Execute = OverrideSmBusExecute; + } + // Kill event + pBS->CloseEvent(Event); +} +//************************************************************************* +//<AMI_PHDR_START> +// +// Procedure: InitSmBusMemoryDown +// +// Description: Override the SmBus protocol. +// +// Input: +// IN EFI_HANDLE ImageHandle, +// IN EFI_SYSTEM_TABLE *SystemTable +// +// Output: +// Status of the operation +// +// Notes: +// Here is the control flow of this function: +// 1. Get SmBus protocol. +// 2. Override the SmBus protocol. +// +//<AMI_PHDR_END> +//************************************************************************* +EFI_STATUS InitSmBusMemoryDown( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + NB_SETUP_DATA *NBSetupData = NULL; + UINTN VariableSize = sizeof(NB_SETUP_DATA); + + + InitAmiLib(ImageHandle, SystemTable); + + Status = pBS->AllocatePool( EfiBootServicesData, \ + VariableSize, \ + &NBSetupData ); + ASSERT_EFI_ERROR(Status); + + GetNbSetupData( pRS, NBSetupData, FALSE ); + + if (NBSetupData->IsRunMemoryDown) { + IsRunMemoryDown = NBSetupData->IsRunMemoryDown; + + + //NbSetupdata Pass to SaGlobalNvsArea. + Status = pBS->CreateEvent ( + EFI_EVENT_NOTIFY_SIGNAL, + TPL_CALLBACK, + OverrideSmBusNotify, + NULL, + &gSmBusMemoryDownEvent + ); + + if (!EFI_ERROR (Status)) { + Status = pBS->RegisterProtocolNotify ( + &gEfiSMBusProtocolGuid, + gSmBusMemoryDownEvent, + &gSmBusMemoryDownEventReg + ); + } + + } + // Free memory used for setup data + pBS->FreePool( NBSetupData ); + + return Status; + +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/PchWrap/SmBusMemoryDown/SmBusMemoryDown.cif b/Chipset/SB/PchWrap/SmBusMemoryDown/SmBusMemoryDown.cif new file mode 100644 index 0000000..d187e08 --- /dev/null +++ b/Chipset/SB/PchWrap/SmBusMemoryDown/SmBusMemoryDown.cif @@ -0,0 +1,11 @@ +<component> + name = "SmBusMemoryDown" + category = ModulePart + LocalRoot = "Chipset\SB\PchWrap\SmBusMemoryDown\" + RefName = "SmBusMemoryDown" +[files] +"SmBusMemoryDown.sdl" +"SmBusMemoryDown.mak" +"SmBusMemoryDown.dxs" +"SmBusMemoryDown.c" +<endComponent> diff --git a/Chipset/SB/PchWrap/SmBusMemoryDown/SmBusMemoryDown.dxs b/Chipset/SB/PchWrap/SmBusMemoryDown/SmBusMemoryDown.dxs new file mode 100644 index 0000000..6b1acfb --- /dev/null +++ b/Chipset/SB/PchWrap/SmBusMemoryDown/SmBusMemoryDown.dxs @@ -0,0 +1,50 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/SmBusMemoryDown.dxs 1 12/11/12 1:09a Scottyang $ +// +// $Date: 12/11/12 1:09a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SmBusMemoryDown.dxs +// +// Description: SmBusMemoryDown dependency file +// +//<AMI_FHDR_END> +//************************************************************************* + +DEPENDENCY_START + TRUE +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/PchWrap/SmBusMemoryDown/SmBusMemoryDown.mak b/Chipset/SB/PchWrap/SmBusMemoryDown/SmBusMemoryDown.mak new file mode 100644 index 0000000..c99931f --- /dev/null +++ b/Chipset/SB/PchWrap/SmBusMemoryDown/SmBusMemoryDown.mak @@ -0,0 +1,44 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +all : SmBusMemoryDown + +SmBusMemoryDown : $(BUILD_DIR)\SmBusMemoryDown.mak SmBusMemoryDownBin + +$(BUILD_DIR)\SmBusMemoryDown.mak : $(SMBUS_MEMORYDOWN_DIR)\$(@B).cif $(SMBUS_MEMORYDOWN_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(SMBUS_MEMORYDOWN_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +SmBusMemoryDownBin : $(AMIDXELIB) $(AMICSPLib) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\SmBusMemoryDown.mak all\ + GUID=F6A59595-BB9F-415b-A7F3-DC7C09387BE6 \ + ENTRY_POINT=InitSmBusMemoryDown \ + DEPEX1=$(SMBUS_MEMORYDOWN_DIR)\SmBusMemoryDown.dxs\ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + TYPE=BS_DRIVER \ + COMPRESS=1\ + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2012, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/SB/PchWrap/SmBusMemoryDown/SmBusMemoryDown.sdl b/Chipset/SB/PchWrap/SmBusMemoryDown/SmBusMemoryDown.sdl new file mode 100644 index 0000000..e5f0206 --- /dev/null +++ b/Chipset/SB/PchWrap/SmBusMemoryDown/SmBusMemoryDown.sdl @@ -0,0 +1,27 @@ +TOKEN + Name = "SmBusMemoryDown_SUPPORT" + Value = "1" + Help = "Main switch to enable SmBusMemoryDown support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Token = "PchSmbusDxe_SUPPORT" "=" "1" + Token = "MRC_MEMORY_DOWN_SUPPORT" "=" "1" +End + +PATH + Name = "SMBUS_MEMORYDOWN_DIR" +End + +MODULE + Help = "Includes SmBusMemoryDown.mak to Project" + File = "SmBusMemoryDown.mak" +End + +ELINK + Name = "$(BUILD_DIR)\SmBusMemoryDown.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + diff --git a/Chipset/SB/PchWrap/WdtApp/Dxe/WdtAppDxe.CIF b/Chipset/SB/PchWrap/WdtApp/Dxe/WdtAppDxe.CIF new file mode 100644 index 0000000..c79f8a0 --- /dev/null +++ b/Chipset/SB/PchWrap/WdtApp/Dxe/WdtAppDxe.CIF @@ -0,0 +1,11 @@ +<component> + name = "WdtAppDxe" + category = ModulePart + LocalRoot = "Chipset\SB\PchWrap\WdtApp\Dxe" + RefName = "WdtAppDxe" +[files] +"WdtAppDxe.sdl" +"WdtAppDxe.dxs" +"WdtAppDxe.mak" +"WdtAppDxe.c" +<endComponent>
\ No newline at end of file diff --git a/Chipset/SB/PchWrap/WdtApp/Dxe/WdtAppDxe.c b/Chipset/SB/PchWrap/WdtApp/Dxe/WdtAppDxe.c new file mode 100644 index 0000000..902b521 --- /dev/null +++ b/Chipset/SB/PchWrap/WdtApp/Dxe/WdtAppDxe.c @@ -0,0 +1,401 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppDxe/WdtAppDxe.c 2 5/14/14 1:10p Barretlin $ +// +// $Revision: 2 $ +// +// $Date: 5/14/14 1:10p $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppDxe/WdtAppDxe.c $ +// +// 2 5/14/14 1:10p Barretlin +// [TAG] EIP167028 +// [Category] Improvement +// [Description] Variable attribute improment +// [Files] SB.sd SBDxe.c WdtAppDxe.c +// +// 1 2/08/12 8:34a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +#include <Efi.h> +#include <token.h> +#include <AmiLib.h> +#include <AmiDxeLib.h> +#include <Dxe.h> +#include <PCI.h> +#include <AmiCspLib.h> +#include <WdtAppVariable.h> +#include <Protocol\Wdt\Wdt.h> +#include <Protocol\WdtApp\WdtApp.h> + +#ifdef EFI_DEBUG +#define WDT_TIMEOUT_VALUE 10 // s +#else +#define WDT_TIMEOUT_VALUE 5 // s +#endif + +#define WDT_RELOAD_TIMER 10000000 // in units of 100ns + +EFI_GUID guidLegacyBoot = EFI_EVENT_LEGACY_BOOT_GUID; +EFI_GUID gWdtProtocolGuid = WDT_PROTOCOL_GUID; + +EFI_STATUS +StopFeedingWatchdog ( + IN EFI_EVENT Event, + IN VOID *Context +); + +EFI_STATUS +FeedWatchdog ( + IN EFI_EVENT Event, + IN VOID *Context +); + +EFI_STATUS +InstallWdtSupport ( + VOID +); + +EFI_STATUS +EFIAPI +RequestWdtAfterReboot ( + VOID +); + +EFI_STATUS +EFIAPI +RequestWdtNow ( + VOID +); + +WDT_APP_PROTOCOL mWdtAppProtocol = { + RequestWdtAfterReboot, + RequestWdtNow +}; + +EFI_EVENT mFeedEvent; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WdtAppDxeEntryPoint +// +// Description: Turns on WDT during DXE phase according to requests made by +// OS overclocking application (through WDT status) and BIOS +// modules (through flash variable) +// +// Input: IN EFI_HANDLE ImageHandle, +// IN EFI_SYSTEM_TABLE *SystemTable +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +WdtAppDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + WDT_PROTOCOL *WdtProtocol; + UINTN VariableSize; + UINT32 Attributes; + EFI_GUID WdtPersistentDataGuid = WDT_PERSISTENT_DATA_GUID; + WDT_PERSISTENT_DATA WdtPersistentData; + + InitAmiLib(ImageHandle, SystemTable); + + TRACE ((-1, "(WdtApp) Entry Point to WdtAppDxe\n")); + + Status = pBS->LocateProtocol(&gWdtProtocolGuid, NULL, &WdtProtocol); + if ( EFI_ERROR(Status) ) { + TRACE ((-1, "(WdtApp) Failed to locate Wdt protocol, Status = %r\n",Status)); + return EFI_SUCCESS; + } + + VariableSize = sizeof (WDT_PERSISTENT_DATA); + + Status = pRS->GetVariable ( + L"WdtPersistentData", + &WdtPersistentDataGuid, + &Attributes, + &VariableSize, + &WdtPersistentData + ); + if (EFI_ERROR (Status)) { + WdtPersistentData.Enable = 0; + Attributes = EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS; + } + + if (WdtProtocol->IsWdtRequired() == TRUE || WdtPersistentData.Enable == 1) { + WdtProtocol->ReloadAndStart(WDT_TIMEOUT_VALUE); + InstallWdtSupport(); + } + + WdtPersistentData.Enable = 0; + pRS->SetVariable( + L"WdtPersistentData", + &WdtPersistentDataGuid, + Attributes, + sizeof (WDT_PERSISTENT_DATA), + &WdtPersistentData + ); + + Status = pBS->InstallProtocolInterface ( + &ImageHandle, + &gWdtAppProtocolGuid, + EFI_NATIVE_INTERFACE, + &mWdtAppProtocol + ); + + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RequestWdtNow +// +// Description: Allows protocol's clients to request that WDT be turned on and periodically kicked, +// starting from now. +// +// Input: None +// +// Output: EFI_SUCCESS if everything's OK +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +EFIAPI +RequestWdtNow ( + VOID + ) +{ + EFI_STATUS Status; + Status = InstallWdtSupport(); + return Status; +}; + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RequestWdtAfterReboot +// +// Description: Allows protocol's clients to request that WDT be turned on and periodically kicked +// during BIOS execution during next boot. +// +// Input: None +// +// Output: EFI_SUCCESS if everything's OK +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +EFIAPI +RequestWdtAfterReboot ( + VOID + ) +{ + EFI_STATUS Status; + EFI_GUID WdtPersistentDataGuid = WDT_PERSISTENT_DATA_GUID; + WDT_PERSISTENT_DATA WdtPersistentData; + UINT32 Attributes; + UINTN VariableSize; + + VariableSize = sizeof (WDT_PERSISTENT_DATA); + + Status = pRS->GetVariable ( + L"WdtPersistentData", + &WdtPersistentDataGuid, + &Attributes, + &VariableSize, + &WdtPersistentData + ); + if (EFI_ERROR(Status)) Attributes = EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS; + + WdtPersistentData.Enable = 1; + Status = pRS->SetVariable( + L"WdtPersistentData", + &WdtPersistentDataGuid, + Attributes, + sizeof (WDT_PERSISTENT_DATA), + &WdtPersistentData + ); + ASSERT_EFI_ERROR(Status); + + return Status; +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InstallWdtSupport +// +// Description: Creates events for FeedWatchdog and StopFeedingWatchdog functions. +// +// Input: None +// +// Output: EFI_SUCCESS if everything's OK +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +InstallWdtSupport ( + VOID + ) +{ + EFI_STATUS Status; + EFI_EVENT BootEvent; + WDT_PROTOCOL* WdtProtocol; + + TRACE ((-1, "(WdtApp) Wdt turned on\n")); + + Status = pBS->LocateProtocol(&gWdtProtocolGuid, NULL, &WdtProtocol); + ASSERT_EFI_ERROR(Status); + Status = WdtProtocol->ReloadAndStart(WDT_TIMEOUT_VALUE); + ASSERT_EFI_ERROR(Status); + + Status = pBS->CreateEvent ( + EFI_EVENT_TIMER | EFI_EVENT_NOTIFY_SIGNAL, + TPL_NOTIFY, + FeedWatchdog, + NULL, + &mFeedEvent + ); + ASSERT_EFI_ERROR (Status); + Status = pBS->SetTimer ( + mFeedEvent, + TimerPeriodic, + WDT_RELOAD_TIMER + ); + ASSERT_EFI_ERROR (Status); + + Status = pBS->CreateEvent ( + EVT_SIGNAL_EXIT_BOOT_SERVICES, + TPL_CALLBACK, + StopFeedingWatchdog, + NULL, + &BootEvent + ); + + ASSERT_EFI_ERROR (Status); + + Status = pBS->CreateEventEx( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + StopFeedingWatchdog, + NULL, + &guidLegacyBoot, + &BootEvent + ); + + ASSERT_EFI_ERROR (Status); + + return Status; +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: FeedWatchdog +// +// Description: Prevents WDT timeout by restarting it. +// +// Input: None +// +// Output: Nothing +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +FeedWatchdog ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + WDT_PROTOCOL* WdtProtocol; + + Status = pBS->LocateProtocol(&gWdtProtocolGuid, NULL, &WdtProtocol); + if ( EFI_ERROR(Status) ) { + TRACE ((-1, "(WdtApp) Failed to locate Wdt protocol, Status = %r\n",Status)); + Status = pBS->SetTimer (mFeedEvent, TimerCancel, 0); + ASSERT_EFI_ERROR(Status); + Status = pBS->CloseEvent (mFeedEvent); + ASSERT_EFI_ERROR(Status); + return Status; + } + Status = WdtProtocol->ReloadAndStart(WDT_TIMEOUT_VALUE); + return Status; +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: StopFeedingWatchdog +// +// Description: Stops timer and event that kept on feeding watchdog. +// +// Input: None +// +// Output: Nothing +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +StopFeedingWatchdog ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + WDT_PROTOCOL* WdtProtocol; + + TRACE ((-1, "(WdtApp) Stop feeding WDT\n")); + Status = pBS->SetTimer (mFeedEvent, TimerCancel, 0); + ASSERT_EFI_ERROR(Status); + Status = pBS->CloseEvent (mFeedEvent); + ASSERT_EFI_ERROR(Status); + Status = pBS->LocateProtocol(&gWdtProtocolGuid, NULL, &WdtProtocol); + if ( !EFI_ERROR(Status) ) { + WdtProtocol->Disable(); + } + return EFI_SUCCESS; +} +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/PchWrap/WdtApp/Dxe/WdtAppDxe.dxs b/Chipset/SB/PchWrap/WdtApp/Dxe/WdtAppDxe.dxs new file mode 100644 index 0000000..22e287c --- /dev/null +++ b/Chipset/SB/PchWrap/WdtApp/Dxe/WdtAppDxe.dxs @@ -0,0 +1,25 @@ +/*++ +Copyright (c) 2010 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + WdtAppDxe.dxs + +Abstract: + + Platform-specific ICC code + +--*/ + +#include <Protocol\Wdt\Wdt.h> + +DEPENDENCY_START + WDT_PROTOCOL_GUID +DEPENDENCY_END diff --git a/Chipset/SB/PchWrap/WdtApp/Dxe/WdtAppDxe.mak b/Chipset/SB/PchWrap/WdtApp/Dxe/WdtAppDxe.mak new file mode 100644 index 0000000..b8576a9 --- /dev/null +++ b/Chipset/SB/PchWrap/WdtApp/Dxe/WdtAppDxe.mak @@ -0,0 +1,65 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppDxe/WdtAppDxe.mak 1 2/08/12 8:34a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 8:34a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppDxe/WdtAppDxe.mak $ +# +# 1 2/08/12 8:34a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +all : WdtAppDxe + +$(BUILD_DIR)\WdtAppDxe.mak : $(WdtAppDxe_DIR)\$(@B).cif $(BUILD_RULES) + $(CIF2MAK) $(WdtAppDxe_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +WdtAppDxe : $(BUILD_DIR)\WdtAppDxe.mak WdtAppDxe_Bin + +WdtAppDxe_INCLUDES=\ + $(INTEL_PCH_INCLUDES)\ + $(PROJECT_INCLUDES)\ + $(WDT_APP_INCLUDES)\ + +WdtAppDxe_Bin : $(AMICSPLib) $(AMIDXELIB) $(WdtAppProtocol_LIB) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\WdtAppDxe.mak all\ + "MY_INCLUDES=$(WdtAppDxe_INCLUDES)"\ + GUID=CE366D33-B057-4c03-8561-CAF17738B66F\ + ENTRY_POINT=WdtAppDxeEntryPoint \ + TYPE=BS_DRIVER \ + DEPEX1=$(WdtAppDxe_DIR)\WdtAppDxe.dxs \ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + COMPRESS=1\ + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/SB/PchWrap/WdtApp/Dxe/WdtAppDxe.sdl b/Chipset/SB/PchWrap/WdtApp/Dxe/WdtAppDxe.sdl new file mode 100644 index 0000000..9a96355 --- /dev/null +++ b/Chipset/SB/PchWrap/WdtApp/Dxe/WdtAppDxe.sdl @@ -0,0 +1,68 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppDxe/WdtAppDxe.sdl 1 2/08/12 8:34a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 8:34a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppDxe/WdtAppDxe.sdl $ +# +# 1 2/08/12 8:34a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "WdtAppDxe_SUPPORT" + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Master = Yes + Help = "Main switch to enable WDT app support in Project in DXE Phase" +End + +MODULE + Help = "Includes WdtAppDxe.mak to Project" + File = "WdtAppDxe.mak" +End + +PATH + Name = "WdtAppDxe_DIR" + Help = "Wdt App dir" +End + +ELINK + Name = "$(BUILD_DIR)\WdtAppDxe.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/SB/PchWrap/WdtApp/Include/WdtAppInclude.CIF b/Chipset/SB/PchWrap/WdtApp/Include/WdtAppInclude.CIF new file mode 100644 index 0000000..4a73faa --- /dev/null +++ b/Chipset/SB/PchWrap/WdtApp/Include/WdtAppInclude.CIF @@ -0,0 +1,9 @@ +<component> + name = "WdtAppInclude" + category = ModulePart + LocalRoot = "Chipset\SB\PchWrap\WdtApp\Include" + RefName = "WdtAppInclude" +[files] +"WdtAppInclude.sdl" +"WdtAppVariable.h" +<endComponent> diff --git a/Chipset/SB/PchWrap/WdtApp/Include/WdtAppInclude.sdl b/Chipset/SB/PchWrap/WdtApp/Include/WdtAppInclude.sdl new file mode 100644 index 0000000..2791219 --- /dev/null +++ b/Chipset/SB/PchWrap/WdtApp/Include/WdtAppInclude.sdl @@ -0,0 +1,56 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppInclude/WdtAppInclude.sdl 1 2/08/12 8:35a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 8:35a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppInclude/WdtAppInclude.sdl $ +# +# 1 2/08/12 8:35a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "WdtAppInclude_SUPPORT" + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable WdtAppInclude support in Project" +End + +ELINK + Name = "WdtAppInclude" + InvokeOrder = ReplaceParent +End +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/SB/PchWrap/WdtApp/Include/WdtAppVariable.h b/Chipset/SB/PchWrap/WdtApp/Include/WdtAppVariable.h new file mode 100644 index 0000000..2b8d1c8 --- /dev/null +++ b/Chipset/SB/PchWrap/WdtApp/Include/WdtAppVariable.h @@ -0,0 +1,52 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppInclude/WdtAppVariable.h 1 2/08/12 8:35a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:35a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppInclude/WdtAppVariable.h $ +// +// 1 2/08/12 8:35a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* + +#define WDT_PERSISTENT_DATA_GUID \ +{0x78ce2354, 0xcfbc, 0x4643, 0xae, 0xba, 0x7, 0xa2, 0x7f, 0xa8, 0x92, 0xbf} + +#define WDT_PERSISTENT_DATA_C_NAME L"WdtPersistentData" + +typedef struct _WDT_PERSISTENT_DATA { + UINT8 Enable; +} WDT_PERSISTENT_DATA; +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + diff --git a/Chipset/SB/PchWrap/WdtApp/Pei/WdtAppPei.CIF b/Chipset/SB/PchWrap/WdtApp/Pei/WdtAppPei.CIF new file mode 100644 index 0000000..0fabb1c --- /dev/null +++ b/Chipset/SB/PchWrap/WdtApp/Pei/WdtAppPei.CIF @@ -0,0 +1,11 @@ +<component> + name = "WdtAppPei" + category = ModulePart + LocalRoot = "Chipset\SB\PchWrap\WdtApp\Pei\" + RefName = "WdtAppPei" +[files] +"WdtAppPei.sdl" +"WdtAppPei.mak" +"WdtAppPei.c" +"WdtAppPei.dxs" +<endComponent> diff --git a/Chipset/SB/PchWrap/WdtApp/Pei/WdtAppPei.c b/Chipset/SB/PchWrap/WdtApp/Pei/WdtAppPei.c new file mode 100644 index 0000000..7171b49 --- /dev/null +++ b/Chipset/SB/PchWrap/WdtApp/Pei/WdtAppPei.c @@ -0,0 +1,136 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppPei/WdtAppPei.c 1 2/08/12 8:34a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:34a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppPei/WdtAppPei.c $ +// +// 1 2/08/12 8:34a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* + +#include <Efi.h> +#include <Pei.h> +#include <Token.h> +#include <AmiPeiLib.h> +#include <AmiCspLib.h> + +#include "PchAccess.h" +#include "WdtAppVariable.h" +#include <Ppi\Wdt\Wdt.h> +#include <PPI\ReadOnlyVariable.h> + +#ifdef EFI_DEBUG +#define WDT_TIMEOUT_BETWEEN_PEI_DXE 30 +#else +#define WDT_TIMEOUT_BETWEEN_PEI_DXE 10 +#endif + +EFI_GUID gWdtPpiGuid = WDT_PPI_GUID; + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WdtAppPeiEntryPoint +// +// Description: Turns on WDT during PEI phase according to requests made by +// OS overclocking application (through WDT status) and BIOS +// modules (through flash variable) +// +// Input: *FfsHeader - Pointer to Firmware File System file header. +// *PeiServices - General purpose services available to every PEIM. +// +// Output: EFI_SUCCESS if everything's OK +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +WdtAppPeiEntryPoint ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + WDT_PPI *WdtPei; + EFI_GUID WdtPersistentData = WDT_PERSISTENT_DATA_GUID; + EFI_GUID gPeiReadOnlyVariablePpiGuid = EFI_PEI_READ_ONLY_VARIABLE_PPI_GUID; + WDT_PERSISTENT_DATA WdtStateData; + EFI_PEI_READ_ONLY_VARIABLE_PPI *ReadOnlyVariable; + UINTN VariableSize; + + PEI_TRACE((-1, PeiServices, "(WdtApp) WdtAppPei Entry Point\n")); + + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gPeiReadOnlyVariablePpiGuid, + 0, NULL, + &ReadOnlyVariable + ); + ASSERT_PEI_ERROR (PeiServices, Status); + + VariableSize = sizeof(WdtStateData); + + Status = ReadOnlyVariable->GetVariable ( + PeiServices, + WDT_PERSISTENT_DATA_C_NAME, + &WdtPersistentData, + NULL, + &VariableSize, + &WdtStateData + ); + + if (EFI_ERROR(Status)) { + WdtStateData.Enable = 0; + } + + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gWdtPpiGuid, + 0, + NULL, + &WdtPei + ); + + ASSERT_PEI_ERROR (PeiServices, Status); + + if (WdtPei->IsWdtRequired() == TRUE || WdtStateData.Enable == 1) { + WdtPei->ReloadAndStart(WDT_TIMEOUT_BETWEEN_PEI_DXE); + } + + return EFI_SUCCESS; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + diff --git a/Chipset/SB/PchWrap/WdtApp/Pei/WdtAppPei.dxs b/Chipset/SB/PchWrap/WdtApp/Pei/WdtAppPei.dxs new file mode 100644 index 0000000..e78218e --- /dev/null +++ b/Chipset/SB/PchWrap/WdtApp/Pei/WdtAppPei.dxs @@ -0,0 +1,47 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppPei/WdtAppPei.dxs 1 2/08/12 8:34a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:34a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppPei/WdtAppPei.dxs $ +// +// 1 2/08/12 8:34a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +#include <Ppi\Wdt\Wdt.h> + +DEPENDENCY_START +WDT_PPI_GUID +DEPENDENCY_END +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/PchWrap/WdtApp/Pei/WdtAppPei.mak b/Chipset/SB/PchWrap/WdtApp/Pei/WdtAppPei.mak new file mode 100644 index 0000000..c6f3127 --- /dev/null +++ b/Chipset/SB/PchWrap/WdtApp/Pei/WdtAppPei.mak @@ -0,0 +1,66 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppPei/WdtAppPei.mak 1 2/08/12 8:34a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 8:34a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppPei/WdtAppPei.mak $ +# +# 1 2/08/12 8:34a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +all : WdtAppPei + +$(BUILD_DIR)\WdtAppPei.mak : $(WdtAppPei_DIR)\$(@B).cif $(BUILD_RULES) + $(CIF2MAK) $(WdtAppPei_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +WdtAppPei : $(BUILD_DIR)\WdtAppPei.mak WdtAppPeiBin + +WdtAppPei_INCLUDES=\ + $(INTEL_PCH_INCLUDES)\ + $(WDT_APP_INCLUDES)\ + +WdtAppPeiBin : $(AMIPEILIB) $(AMICSPLib) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS) \ + /f $(BUILD_DIR)\WdtAppPei.mak all \ + "MY_INCLUDES = $(WdtAppPei_INCLUDES)" \ + NAME=WdtAppPei\ + MAKEFILE=$(BUILD_DIR)\WdtAppPei.mak \ + GUID=0F69F6D7-0E4B-43a6-BFC2-6871694369B0 \ + ENTRY_POINT=WdtAppPeiEntryPoint \ + TYPE=PEIM \ + DEPEX1=$(WdtAppPei_DIR)\WdtAppPei.dxs \ + DEPEX1_TYPE=EFI_SECTION_PEI_DEPEX \ + COMPRESS=0 + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/SB/PchWrap/WdtApp/Pei/WdtAppPei.sdl b/Chipset/SB/PchWrap/WdtApp/Pei/WdtAppPei.sdl new file mode 100644 index 0000000..8f0c3b9 --- /dev/null +++ b/Chipset/SB/PchWrap/WdtApp/Pei/WdtAppPei.sdl @@ -0,0 +1,68 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppPei/WdtAppPei.sdl 1 2/08/12 8:34a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 8:34a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppPei/WdtAppPei.sdl $ +# +# 1 2/08/12 8:34a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "WdtAppPei_SUPPORT" + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Master = Yes + Help = "Main switch to enable WDT APP support in Project in PEI Phase" +End + +MODULE + Help = "Includes WdtAppPei.mak to Project" + File = "WdtAppPei.mak" +End + +PATH + Name = "WdtAppPei_DIR" + Help = "WdtAppPei dir" +End + +ELINK + Name = "$(BUILD_DIR)\WdtAppPei.ffs" + Parent = "FV_BB" + InvokeOrder = AfterParent +End +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/SB/PchWrap/WdtApp/Protocol/WdtApp/WdtApp.c b/Chipset/SB/PchWrap/WdtApp/Protocol/WdtApp/WdtApp.c new file mode 100644 index 0000000..0c3a5f2 --- /dev/null +++ b/Chipset/SB/PchWrap/WdtApp/Protocol/WdtApp/WdtApp.c @@ -0,0 +1,55 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppProtocolLib/WdtApp/WdtApp.c 1 2/08/12 8:36a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:36a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppProtocolLib/WdtApp/WdtApp.c $ +// +// 1 2/08/12 8:36a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +#include "WdtApp.h" + +// +// Protocol GUID definition +// +EFI_GUID gWdtAppProtocolGuid = WDT_APP_PROTOCOL_GUID; + +// +// Protocol description +// +//EFI_GUID_STRING +// (&gWdtAppProtocolGuid, "WDT Application Protocol", "Watchdog Timer Application Protocol"); +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + diff --git a/Chipset/SB/PchWrap/WdtApp/Protocol/WdtApp/WdtApp.h b/Chipset/SB/PchWrap/WdtApp/Protocol/WdtApp/WdtApp.h new file mode 100644 index 0000000..f79ddc0 --- /dev/null +++ b/Chipset/SB/PchWrap/WdtApp/Protocol/WdtApp/WdtApp.h @@ -0,0 +1,78 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppProtocolLib/WdtApp/WdtApp.h 1 2/08/12 8:36a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:36a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppProtocolLib/WdtApp/WdtApp.h $ +// +// 1 2/08/12 8:36a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* + +#ifndef _WDT_APP_API_H_ +#define _WDT_APP_API_H_ + +#include <Efi.h> +#include <token.h> +#include <AmiLib.h> +#include <AmiDxeLib.h> +#include <Dxe.h> +#include <AmiCspLib.h> +// +// GUID for the WDT application Protocol +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define WDT_APP_PROTOCOL_GUID \ + {0x92c7d0bb, 0x679e, 0x479d, 0x87, 0x8d, 0xd4, 0xb8, 0x29, 0x68, 0x57, 0x8b} + +#else + +#define WDT_APP_PROTOCOL_GUID \ + {0x92c7d0bb, 0x679e, 0x479d, { 0x87, 0x8d, 0xd4, 0xb8, 0x29, 0x68, 0x57, 0x8b } } + +#endif +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gWdtAppProtocolGuid; + +typedef EFI_STATUS (EFIAPI *WDT_REQUEST) (VOID); + +typedef struct _WDT_APP_PROTOCOL { + WDT_REQUEST RequestWdtAfterReboot; + WDT_REQUEST RequestWdtNow; +} WDT_APP_PROTOCOL; + +#endif /* _WDT_APP_API_H_ */ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/PchWrap/WdtApp/Protocol/WdtAppProtocolLib.CIF b/Chipset/SB/PchWrap/WdtApp/Protocol/WdtAppProtocolLib.CIF new file mode 100644 index 0000000..6f76b03 --- /dev/null +++ b/Chipset/SB/PchWrap/WdtApp/Protocol/WdtAppProtocolLib.CIF @@ -0,0 +1,11 @@ +<component> + name = "WdtAppProtocolLib" + category = ModulePart + LocalRoot = "Chipset\SB\PchWrap\WdtApp\Protocol" + RefName = "WdtAppProtocolLib" +[files] +"WdtAppProtocolLib.sdl" +"WdtAppProtocolLib.mak" +"WdtApp\WdtApp.h" +"WdtApp\WdtApp.c" +<endComponent> diff --git a/Chipset/SB/PchWrap/WdtApp/Protocol/WdtAppProtocolLib.mak b/Chipset/SB/PchWrap/WdtApp/Protocol/WdtAppProtocolLib.mak new file mode 100644 index 0000000..2b938ab --- /dev/null +++ b/Chipset/SB/PchWrap/WdtApp/Protocol/WdtAppProtocolLib.mak @@ -0,0 +1,56 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppProtocolLib/WdtAppProtocolLib.mak 1 2/08/12 8:36a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 8:36a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppProtocolLib/WdtAppProtocolLib.mak $ +# +# 1 2/08/12 8:36a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* + +all : WdtAppProtocolLib + +$(WdtAppProtocol_LIB) : WdtAppProtocolLib + +WdtAppProtocolLib : $(BUILD_DIR)\WdtAppProtocolLib.mak WdtAppProtocolLibBin + +$(BUILD_DIR)\WdtAppProtocolLib.mak : $(WdtAppProtocol_DIR)\$(@B).cif $(WdtAppProtocol_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(WdtAppProtocol_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +WdtAppProtocolLibBin : + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\WdtAppProtocolLib.mak all\ + TYPE=LIBRARY \ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/SB/PchWrap/WdtApp/Protocol/WdtAppProtocolLib.sdl b/Chipset/SB/PchWrap/WdtApp/Protocol/WdtAppProtocolLib.sdl new file mode 100644 index 0000000..a2cf557 --- /dev/null +++ b/Chipset/SB/PchWrap/WdtApp/Protocol/WdtAppProtocolLib.sdl @@ -0,0 +1,71 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppProtocolLib/WdtAppProtocolLib.sdl 1 2/08/12 8:36a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 8:36a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtAppProtocolLib/WdtAppProtocolLib.sdl $ +# +# 1 2/08/12 8:36a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "WdtAppProtocolLib_SUPPORT" + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable WdtAppProtocolLib support in Project" +End + +PATH + Name = "WdtAppProtocol_DIR" +End + +MODULE + File = "WdtAppProtocolLib.mak" + Help = "Includes WdtAppProtocolLib.mak to Project" +End + +ELINK + Name = "WdtAppProtocol_LIB" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "$(BUILD_DIR)\WdtAppProtocolLib.lib" + Parent = "WdtAppProtocol_LIB" + InvokeOrder = AfterParent +End +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/SB/PchWrap/WdtApp/WdtApp.CIF b/Chipset/SB/PchWrap/WdtApp/WdtApp.CIF new file mode 100644 index 0000000..185f5f9 --- /dev/null +++ b/Chipset/SB/PchWrap/WdtApp/WdtApp.CIF @@ -0,0 +1,14 @@ +<component> + name = "WdtApp" + category = ModulePart + LocalRoot = "Chipset\SB\PchWrap\WdtApp" + RefName = "WdtApp" +[files] +"WdtApp.sdl" +[parts] +"WdtAppDxe" +"WdtAppPei" +"WdtAppInclude" +[parts] +"WdtAppProtocolLib" +<endComponent> diff --git a/Chipset/SB/PchWrap/WdtApp/WdtApp.sdl b/Chipset/SB/PchWrap/WdtApp/WdtApp.sdl new file mode 100644 index 0000000..05197b0 --- /dev/null +++ b/Chipset/SB/PchWrap/WdtApp/WdtApp.sdl @@ -0,0 +1,74 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtApp.sdl 1 2/08/12 8:33a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 8:33a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/PchWrap/WdtApp/WdtApp.sdl $ +# +# 1 2/08/12 8:33a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "WdtApp_SUPPORT" + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Master = Yes + Help = "Main switch to enable WDT app support in Project" +End + +PATH + Name = "WdtApp_DIR" + Help = "Wdt App dir" +End + +ELINK + Name = "WDT_APP_INCLUDES" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "/I$(WdtApp_DIR)" + Parent = "WDT_APP_INCLUDES" + InvokeOrder = AfterParent +End + +ELINK + Name = "/I$(WdtApp_DIR)\Include" + Parent = "WDT_APP_INCLUDES" + InvokeOrder = AfterParent +End +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/SB/PowerButton.c b/Chipset/SB/PowerButton.c new file mode 100644 index 0000000..d9256ff --- /dev/null +++ b/Chipset/SB/PowerButton.c @@ -0,0 +1,265 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SMM/PowerButton/PowerButton.c 9 9/20/11 3:12p Markw $ +// +// $Revision: 9 $ +// +// $Date: 9/20/11 3:12p $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SMM/PowerButton/PowerButton.c $ +// +// 9 9/20/11 3:12p Markw +// [TAG] EIP67890 +// [Category] Spec Update +// [Severity] Normal +// [Description] Support power button handler in PI 1.1 +// +// [Files] PowerButton.c, PowerButton.mak, PowerButton. dxs +// +// 8 7/08/09 7:56p Markw +// Update headers. +// +// 7 1/07/08 4:26p Robert +// Updated for coding standard +// +// 6 5/30/07 5:29p Markw +// Use library function to shutdown. +// +// 5 3/28/07 1:27p Markw +// Update headers. +// +// 4 2/26/07 11:44a Yakovlevs +// Added arming PwrButton Smi when registering SMI handler. +// In event handler added check for Sleep SMI enable and disabling it. +// +// 3 11/11/05 11:46a Markw +// Renamed IntallSmmHandler to InitSmmHandler because of build errors +// because another driver used InstallSmmHandler. +// +// 2 11/08/05 6:05p Markw +// Using InstallSmiHandler library function. +// +// 1 1/28/05 4:33p Sivagarn +// Power Button SMM Component - Initial check in +// +// +//********************************************************************** + +//<AMI_FHDR_START> +//--------------------------------------------------------------------------- +// +// Name: PowerButton.C +// +// Description: Provide functions to register and handle Powerbutton +// functionality. This code is generic and as long as PM +// base address SDL token is defined properly this should +// work fine. +// +//--------------------------------------------------------------------------- +//<AMI_FHDR_END> + + +#include <Token.h> +#include <AmiDxeLib.h> +#include <AMICSPLIBInc.h> +#if PI_SPECIFICATION_VERSION < 0x1000A +#include <Protocol\SmmPowerButtonDispatch.h> +#else +#include <Protocol\SmmPowerButtonDispatch2.h> +#endif + +EFI_GUID gThisFileGuid = + {0xe566b097,0x4378,0x485f,0x91,0xd0,0x1c,0x09,0x7c,0x19,0x0c,0xe2}; + //E566B097-4378-485f-91D0-1C097C190CE2 + +#if PI_SPECIFICATION_VERSION < 0x1000A +EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT DispatchContext = {PowerButtonEntry}; +#else +EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT DispatchContext = {EfiPowerButtonExit}; +EFI_SMM_BASE2_PROTOCOL *pSmmBase2; +EFI_SMM_SYSTEM_TABLE2 *pSmst2; +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: PowerButtonActivated +// +// Description: If the power button is pressed, then this function is called. +// +// Input: +// IN EFI_HANDLE DispatchHandle +// IN EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT *DispatchContext +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +#if PI_SPECIFICATION_VERSION < 0x1000A +VOID PowerButtonActivated( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT *DispatchContext + ) +#else +EFI_STATUS +EFIAPI +PowerButtonActivated( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *Context OPTIONAL, + IN OUT VOID *CommBuffer OPTIONAL, + IN OUT UINTN *CommBufferSize OPTIONAL) +#endif +{ + SBLib_Shutdown(); + +#if PI_SPECIFICATION_VERSION >= 0x1000A + return EFI_SUCCESS; +#endif +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InSmmFunction +// +// Description: This function is called from SMM during SMM registration. +// +// Input: +// IN EFI_HANDLE ImageHandle +// IN EFI_SYSTEM_TABLE *SystemTable +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS InSmmFunction(EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE *SystemTable) +{ +#if PI_SPECIFICATION_VERSION >= 0x1000A + EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL *PowerButton; +#else + EFI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL *PowerButton; +#endif + EFI_HANDLE hPowerButton; + EFI_STATUS Status; + +#if PI_SPECIFICATION_VERSION >= 0x1000A + Status = pSmmBase2->GetSmstLocation(pSmmBase2, &pSmst2); + if (EFI_ERROR(Status)) return Status; + + Status = pSmst2->SmmLocateProtocol( + &gEfiSmmPowerButtonDispatch2ProtocolGuid, + NULL, + &PowerButton + ); +#else + Status = pBS->LocateProtocol( + &gEfiSmmPowerButtonDispatchProtocolGuid, + NULL, + &PowerButton + ); +#endif + if (EFI_ERROR(Status)) return Status; + + Status = PowerButton->Register( + PowerButton, + PowerButtonActivated, + &DispatchContext, + &hPowerButton + ); + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NotInSmmFunction +// +// Description: This function is called from outside of SMM during SMM registration. +// +// Input: +// IN EFI_HANDLE ImageHandle +// IN EFI_SYSTEM_TABLE *SystemTable +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS NotInSmmFunction(EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE *SystemTable) +{ + UINT16 Value; + //Clear All PM Statuses + Value = IoRead16(PM_BASE_ADDRESS); + IoWrite16(PM_BASE_ADDRESS,Value); + + //Enable PowerButton and Global Enable + IoWrite16(PM_BASE_ADDRESS + 0x02, BIT05 + BIT08); + return EFI_SUCCESS; +} + + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitPowerButton +// +// Description: This is the entrypoint of the Power button driver. +// +// Input: +// IN EFI_HANDLE ImageHandle +// IN EFI_SYSTEM_TABLE *SystemTable +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS InitPowerButton( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ +#if PI_SPECIFICATION_VERSION >= 0x0001000a + EFI_STATUS Status; +#endif + + InitAmiLib(ImageHandle, SystemTable); + +#if PI_SPECIFICATION_VERSION >= 0x0001000a + Status = pBS->LocateProtocol(&gEfiSmmBase2ProtocolGuid, NULL, &pSmmBase2); + if (EFI_ERROR(Status)) return Status; + + return InitSmmHandler(ImageHandle, SystemTable, InSmmFunction, NULL); +#else + return InitSmmHandler(ImageHandle, SystemTable, InSmmFunction, NotInSmmFunction); +#endif +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/PowerButton.cif b/Chipset/SB/PowerButton.cif new file mode 100644 index 0000000..4dc4777 --- /dev/null +++ b/Chipset/SB/PowerButton.cif @@ -0,0 +1,11 @@ +<component> + name = "PowerButton" + category = ModulePart + LocalRoot = "Chipset\SB" + RefName = "PowerButton" +[files] +"\PowerButton.sdl" +"\PowerButton.mak" +"\PowerButton.c" +"\PowerButton.dxs" +<endComponent> diff --git a/Chipset/SB/PowerButton.dxs b/Chipset/SB/PowerButton.dxs new file mode 100644 index 0000000..198f3fd --- /dev/null +++ b/Chipset/SB/PowerButton.dxs @@ -0,0 +1,76 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SMM/PowerButton/PowerButton.dxs 3 9/20/11 3:13p Markw $ +// +// $Revision: 3 $ +// +// $Date: 9/20/11 3:13p $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SMM/PowerButton/PowerButton.dxs $ +// +// 3 9/20/11 3:13p Markw +// [TAG] EIP67890 +// [Category] Spec Update +// [Severity] Normal +// [Description] Support power button handler in PI 1.1 +// +// [Files] PowerButton.c, PowerButton.mak, PowerButton.dxs +// +// 2 7/08/09 7:56p Markw +// Update headers. +// +//********************************************************************** + +//<AMI_FHDR_START> +//--------------------------------------------------------------------------- +// +// Name: PowerButton.Dxs +// +// Description: Dependency file for the power button handler driver +// +//--------------------------------------------------------------------------- +//<AMI_FHDR_END> + + +#if PI_SPECIFICATION_VERSION >= 0x0001000a +#include <Protocol\SmmPowerButtonDispatch2.h> +#else +#include <Protocol\SmmPowerButtonDispatch.h> +#endif + +DEPENDENCY_START +#if PI_SPECIFICATION_VERSION >= 0x0001000a + EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL_GUID +#else + EFI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL_GUID +#endif +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/PowerButton.mak b/Chipset/SB/PowerButton.mak new file mode 100644 index 0000000..09a4ee8 --- /dev/null +++ b/Chipset/SB/PowerButton.mak @@ -0,0 +1,94 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#********************************************************************** +# $Header: /Alaska/SOURCE/Modules/SMM/PowerButton/PowerButton.mak 5 9/20/11 3:12p Markw $ +# +# $Revision: 5 $ +# +# $Date: 9/20/11 3:12p $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/SMM/PowerButton/PowerButton.mak $ +# +# 5 9/20/11 3:12p Markw +# [TAG] EIP67890 +# [Category] Spec Update +# [Severity] Normal +# [Description] Support power button handler in PI 1.1 +# +# [Files] PowerButton.c, PowerButton.mak, PowerButton. dxs +# +# 4 7/08/09 8:24p Markw +# Update header. +# +# 3 5/30/07 5:29p Markw +# Use library function to shutdown. +# +# 2 12/02/05 11:48a Felixp +# +# 1 1/28/05 4:33p Sivagarn +# Power Button SMM Component - Initial check in +# +# +#********************************************************************** + + + +#<AMI_FHDR_START> +#--------------------------------------------------------------------------- +# +# Name: PowerButton.MAK +# +# Description: Make file for the SMM power button handler code +# +#--------------------------------------------------------------------------- +#<AMI_FHDR_END> +!IFNDEF PI_SPECIFICATION_VERSION +PI_SPECIFICATION_VERSION=0 +!ENDIF + +all : PowerButton + +PowerButton : $(BUILD_DIR)\PowerButton.mak PowerButtonBin + +$(BUILD_DIR)\PowerButton.mak : $(POWER_BUTTON_DIR)\PowerButton.cif $(POWER_BUTTON_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(POWER_BUTTON_DIR)\PowerButton.cif $(CIF2MAK_DEFAULTS) + +PowerButtonBin : $(AMIDXELIB) $(AMICSPLib) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\PowerButton.mak all\ + GUID=E566B097-4378-485f-91D0-1C097C190CE2\ + ENTRY_POINT=InitPowerButton\ +!IF $(PI_SPECIFICATION_VERSION) < 0x1000A + TYPE=BS_DRIVER\ +!ELSE + TYPE=SMM_DRIVER\ +!ENDIF + COMPRESS=1 + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/SB/PowerButton.sdl b/Chipset/SB/PowerButton.sdl new file mode 100644 index 0000000..33cffcc --- /dev/null +++ b/Chipset/SB/PowerButton.sdl @@ -0,0 +1,25 @@ +TOKEN + Name = "PowerButton_SUPPORT" + Value = "1" + Help = "Main switch to enable PowerButton support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes +End + +PATH + Name = "POWER_BUTTON_DIR" +End + +MODULE + Help = "Includes PowerButton.mak to Project" + File = "PowerButton.mak" +End + +ELINK + Name = "$(BUILD_DIR)\PowerButton.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + diff --git a/Chipset/SB/RRIORDMA.asl b/Chipset/SB/RRIORDMA.asl new file mode 100644 index 0000000..a535886 --- /dev/null +++ b/Chipset/SB/RRIORDMA.asl @@ -0,0 +1,230 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/RRIORDMA.asl 1 2/08/12 8:24a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:24a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/RRIORDMA.asl $ +// +// 1 2/08/12 8:24a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: RRIORDMA.ASL +// +// Description: The ASL file for South Bridge LPC I/O Decoding & DMA +// assignment. +// +//<AMI_FHDR_END> +//************************************************************************* + + OperationRegion(\_SB.PCI0.LPCB.LPCR, PCI_Config, 0x80, 4) + Field(\_SB.PCI0.LPCB.LPCR, ByteAcc, NoLock, Preserve) { + CADR, 3, // COMA Decode Range + , 1, + CBDR, 3, // COMB Decode Range + , 1, + LTDR, 2, // LPT Decode Range + , 2, + FDDR, 1, // FDD Decode Range + , 3, + CALE, 1, // COM Port A Enable + CBLE, 1, // COM Port B Enable + LTLE, 1, // Parallel Port Enable + FDLE, 1, // Floppy Drive Enable + , 4, + GLLE, 1, // Low Game Port Enable + GHLE, 1, // High Game Port Enable + KCLE, 1, // Keyboard Enable + MCLE, 1, // Microcontroller Enable + C1LE, 1, // Super I/O Enable 1 + C2LE, 1, // Super I/O Enable 2 + , 2, + } + +/* +;<AMI_PHDR_START> +;------------------------------------------------------------------------ +; +; Procedure: UXDV +; +; Description: Convert UART port address to the decoded value in LPC bridge +; +; Input: Arg0 = Port to Route/Release +; +; Output: UART Port Decoded Value in the LPC bridge +; +;------------------------------------------------------------------------ +;<AMI_PHDR_END> +*/ + + Method(UXDV, 1) { + Store(0xff, Local0) // Unknown + Switch (Add(Arg0, 0)) { + Case (0x3F8) { Store(0, Local0) } + Case (0x2F8) { Store(1, Local0) } + Case (0x220) { Store(2, Local0) } + Case (0x228) { Store(3, Local0) } + Case (0x238) { Store(4, Local0) } + Case (0x2E8) { Store(5, Local0) } + Case (0x338) { Store(6, Local0) } + Case (0x3E8) { Store(7, Local0) } + } + return (Local0) + } + +/* +;<AMI_PHDR_START> +;------------------------------------------------------------------------ +; +; Procedure: RRIO +; +; Description: Route/Release I/O resources from/to EIO/LPC Bus +; +; Input: Arg0 = Device Category +; Arg1 = 0/1 Disable/Enable resource decoding +; Arg2 = Port to Route/Release +; Arg3 = Port SIZE to Route +; +; Output: Nothing +; +;------------------------------------------------------------------------ +;<AMI_PHDR_END> +*/ + Method(RRIO, 4) { + Switch (Add(Arg0, 0)) { + Case (0) { // UART 0 or 2 + Store(0, CALE) // Disable the decoding + Store (UXDV(Arg2), Local0) + If (LNotEqual(Local0, 0xff)) { Store(Local0, CADR)} + If (Arg1) { Store(1, CALE) } + } + Case (1) { // UART 1 or 3 + Store(0, CBLE) // Disable the decoding + Store (UXDV(Arg2), Local0) + If (LNotEqual(Local0, 0xff)) { Store(Local0, CBDR)} + If (Arg1) { Store(1, CBLE) } + } + Case (2) { // LPT + Store(0, LTLE) // Disable the decoding + If (LEqual(Arg2, 0x378)) { Store(0, LTDR) } + If (LEqual(Arg2, 0x278)) { Store(1, LTDR) } + If (LEqual(Arg2, 0x3BC)) { Store(2, LTDR) } + If (Arg1) { Store(1, LTLE) } + } + Case (3) { // FDD + Store(0, FDLE) // Disable the decoding + If (LEqual(Arg2, 0x3F0)) { Store(0, FDDR) } + If (LEqual(Arg2, 0x370)) { Store(1, FDDR) } + If (Arg1) { Store(1, FDLE) } + } + Case (8) { // Game 1 + If (LEqual(Arg2, 0x200)) { + If (Arg1) { Store(1, GLLE) } + Else { Store(0, GLLE) } + } + If (LEqual(Arg2, 0x208)) { + If (Arg1) { Store(1, GHLE) } + Else { Store(0, GHLE) } + } + } + Case (9) { // Game 2 + If (LEqual(Arg2, 0x200)) { + If (Arg1) { Store(1, GLLE) } + Else { Store(0, GLLE) } + } + If (LEqual(Arg2, 0x208)) { + If (Arg1) { Store(1, GHLE) } + Else { Store(0, GHLE) } + } + } + Case (10) { // Keyboard Controller + If (LOr(LEqual(Arg2, 0x60), LEqual(Arg2, 0x64))) { + If (Arg1) { Store(1, KCLE) } + Else { Store(0, KCLE) } + } + } + Case (11) { // MicroController + If (LOr(LEqual(Arg2, 0x62), LEqual(Arg2, 0x66))) { + If (Arg1) { Store(1, MCLE) } + Else { Store(0, MCLE) } + } + } + Case (12) { // Super I/O Enable 1 + If (LEqual(Arg2, 0x2E)) { + If (Arg1) { Store(1, C1LE) } + Else { Store(0, C1LE) } + } + If (LEqual(Arg2, 0x4E)) { + If (Arg1) { Store(1, C2LE) } + Else { Store(0, C2LE) } + } + } + Case (13) { // Super I/O Enable 2 + If (LEqual(Arg2, 0x2E)) { + If (Arg1) { Store(1, C1LE) } + Else { Store(0, C1LE) } + } + If (LEqual(Arg2, 0x4E)) { + If (Arg1) { Store(1, C2LE) } + Else { Store(0, C2LE) } + } + } + + } + + } + +/* +;<AMI_PHDR_START> +;------------------------------------------------------------------------ +; +; Procedure: rDMA +; +; Description: Route/Release DMA channel from/to being ISA/PCI mode +; +; Input: Arg0 = Device Category +; Arg1 = 0/1 Disable/Enable resource decoding +; Arg2 = DMA channel to Route/Release +; +; Output: Nothing +; +;------------------------------------------------------------------------ +;<AMI_PHDR_END> +*/ + Method(rDMA, 3) { + // Porting If needed. + } + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/RTC.h b/Chipset/SB/RTC.h new file mode 100644 index 0000000..3c88361 --- /dev/null +++ b/Chipset/SB/RTC.h @@ -0,0 +1,206 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/RTC.h 3 7/17/13 1:54a Scottyang $ +// +// $Revision: 3 $ +// +// $Date: 7/17/13 1:54a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/RTC.h $ +// +// 3 7/17/13 1:54a Scottyang +// [TAG] EIP128233 +// [Category] Improvement +// [Description] Improving UEFI PXE image downloading proformance. +// [Files] RTC.h +// SBRun.c +// +// 2 1/11/13 1:51a Scottyang +// [TAG] EIP88358 +// [Category] Improvement +// [Description] Add FORCE_USER_TO_SETUP_IF_CMOS_BAD token +// [Files] SBDex.c, SBPei.c, RTC.h, SB.sdl +// +// 1 2/08/12 8:24a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: RTC.h +// +// Description: Real Time Clock and CMOS Data bank registr definitions. +// +//<AMI_FHDR_END> +//************************************************************************* + +#ifndef __RTC__H__ +#define __RTC__H__ +#ifdef __cplusplus +extern "C" { +#endif + +#include <Efi.h> + +#define EFI_TIME_VARIABLE_GUID \ + {0x9d0da369, 0x540b, 0x46f8, 0x85, 0xa0, 0x2b, 0x5f, 0x2c, 0x30, 0x1e, 0x15} + // [EIP88358] >> +#define CMOS_BAD_HOB_GUID \ + {0x7e7369ce, 0x0188, 0x4183, 0x8c, 0x2d, 0xda, 0xf7, 0xb7, 0x30, 0xe4, 0x2b} + // [EIP88358] << +//--------------------------------------------------------------------------- +// Define Real Time Clock INDEX and DATA registers +//--------------------------------------------------------------------------- +#define RTC_INDEX_REG 0x70 +#define RTC_DATA_REG 0x71 + +//--------------------------------------------------------------------------- +// Define Internal Registers for Real Time Clock +//--------------------------------------------------------------------------- +#define RTC_SECONDS_REG 0x00 // R/W Range 0..59 +#define RTC_SECONDS_ALARM_REG 0x01 // R/W Range 0..59 +#define RTC_MINUTES_REG 0x02 // R/W Range 0..59 +#define RTC_MINUTES_ALARM_REG 0x03 // R/W Range 0..59 +#define RTC_HOURS_REG 0x04 // R/W Range 1..12 or 0..23 + // Bit 7 is AM/PM +#define RTC_HOURS_ALARM_REG 0x05 // R/W Range 1..12 or 0..23 + // Bit 7 is AM/PM +#define RTC_DAY_OF_WEEK_REG 0x06 // R/W Range 1..7 +#define RTC_DAY_OF_MONTH_REG 0x07 // R/W Range 1..31 +#define RTC_MONTH_REG 0x08 // R/W Range 1..12 +#define RTC_YEAR_REG 0x09 // R/W Range 0..99 +#define RTC_REG_A_INDEX 0x0a // R/W[0..6] R0[7] +#define RTC_REG_B_INDEX 0x0b // R/W +#define RTC_REG_C_INDEX 0x0c // RO +#define RTC_REG_D_INDEX 0x0d // RO + +#define RTC_NMI_MASK 0x80 + +#pragma pack(push,1) + +//--------------------------------------------------------------------------- +// Register A Bit definitions +//--------------------------------------------------------------------------- +typedef union { + UINT8 REG_A; + struct { + UINT8 RateSel : 4; + UINT8 Divisor : 3; + UINT8 UpdInProgr : 1; + }; +} RTC_REG_A; + +//--------------------------------------------------------------------------- +// Register B Bit definitions +//--------------------------------------------------------------------------- +typedef union { + UINT8 REG_B; + struct { + UINT8 DaylightSav : 1; // 0 - Daylight saving disabled + // 1 - Daylight savings enabled + UINT8 Mode : 1; // 0 - 12 hour mode + // 1 - 24 hour mode + UINT8 Format : 1; // 0 - BCD Format + // 1 - Binary Format + UINT8 SquareWave : 1; // 0 - Disable SQWE output + // 1 - Enable SQWE output + UINT8 UpdateInt : 1; // 0 - Update INT disabled + // 1 - Update INT enabled + UINT8 AlarmInt : 1; // 0 - Alarm INT disabled + // 1 - Alarm INT Enabled + UINT8 PeriodicInt : 1; // 0 - Periodic INT disabled + // 1 - Periodic INT Enabled + UINT8 Set : 1; // 0 - Normal operation + // 1 - Updates inhibited + }; +} RTC_REG_B; + +//--------------------------------------------------------------------------- +// Register C Bit definitions +//--------------------------------------------------------------------------- +typedef union { + UINT8 REG_C; + struct { + UINT8 Reserved : 4; // Read as zero. Can not be written. + UINT8 UpdEndFlag : 1; // Update End Interrupt Flag + UINT8 AlarmFlag : 1; // Alarm Interrupt Flag + UINT8 PeriodicFlag : 1; // Periodic Interrupt Flag + UINT8 IrqFlag : 1; // Iterrupt Request Flag = + // PF & PIE | AF & AIE | UF & UIE + }; +} RTC_REG_C; + +//--------------------------------------------------------------------------- +// Register D Bit definitions +//--------------------------------------------------------------------------- +typedef union { + UINT8 REG_D; + struct { + UINT8 Reserved : 7; + UINT8 DataValid : 1; // Valid RAM and Time + }; +} RTC_REG_D; + + +//--------------------------------------------------------------------------- +// Bit definitions for Day Alarm Register (Porting Required if needed) +//--------------------------------------------------------------------------- +typedef union { + UINT8 REG_DATE_ALARM; + struct { + UINT8 DateAlarm : 6; + UINT8 Reserved : 2; + }; +} RTC_DATE_ALARM_REG; + +//--------------------------------------------------------------------------- +// Bit definitions for Month Alarm Register (Porting Required if needed) +//--------------------------------------------------------------------------- +typedef union { + UINT8 REG_MONTH_ALARM; + struct { + UINT8 MonthAlarm : 6; + UINT8 Reserved : 2; + }; +} RTC_MONTH_ALARM_REG; + // [EIP88358] >> +typedef struct _CMOS_BAD_HOB { + EFI_HOB_GUID_TYPE Header; +} CMOS_BAD_HOB; + // [EIP88358] << +#pragma pack(pop) + +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/ReleaseNotes.chm b/Chipset/SB/ReleaseNotes.chm Binary files differnew file mode 100644 index 0000000..2752298 --- /dev/null +++ b/Chipset/SB/ReleaseNotes.chm diff --git a/Chipset/SB/SATA.ASL b/Chipset/SB/SATA.ASL new file mode 100644 index 0000000..2a3e318 --- /dev/null +++ b/Chipset/SB/SATA.ASL @@ -0,0 +1,297 @@ +// Set of generic ACPI Control Methods to configure SATA Controller and SATA Drives settings +// File is included under SATA controller PCI device scope +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Chipset/SB/SATA.ASL 1 6/17/16 4:05a Chienhsieh $ +// +// $Revision: 1 $ +// +// $Date: 6/17/16 4:05a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Chipset/SB/SATA.ASL $ +// +// 1 6/17/16 4:05a Chienhsieh +// [TAG] EIP255383 +// [Category] Improvement +// [Description] when the FORCE_HDD_PASSWORD_PROMPT sdl token enabled , +// even though use select s4 option, on resume system booted like S5. +// set HDD password and enter Win8 S4(Hibernate) sleep, behaviour of S4 +// resume would be like restart. +// [Files] SATA.ASL +// +// 2 10/23/12 3:19a Scottyang +// [TAG] EIP84560 +// [Category] Bug Fix +// [Symptom] Can't enter Win8 after Win8 AHCI driver version:11.5.0.1122 +// install. +// [Solution] fixed in EIP84560 +// [Files] sb.sdl, sb.mak, sata.asl +// +// 1 2/08/12 8:25a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* + +DefinitionBlock ( + "Sata.aml", + "SSDT", + 1, + "SataRef", + "SataTabl", + 0x1000 + ) +{ + +External(DSSP, IntObj) +External(\_SB.PCI0.SAT0, DeviceObj) + +Scope(\) +{ + // SATA Command Set + //---------------------------------------------------------------// + // Reg1 Reg2 Reg3 Reg4 Reg5 Reg6 Reg7 + //---------------------------------------------------------------// + Name(STFE, Buffer(){0x10, 0x06, 0x00, 0x00, 0x00, 0x00, 0xEF,}) // Set Features - Enable USE of SATA Feature + Name(STFD, Buffer(){0x90, 0x06, 0x00, 0x00, 0x00, 0x00, 0xEF,}) // Set Features - Disable USE of SATA Feature + Name(FZTF, Buffer(){0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 }) // Freeze Lock Command + Name(DCFL, Buffer(){0xC1, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB1 }) // Device Configuration Freeze Lock Command + + Name(SCBF, Buffer(21){}) // SATA Command Buffer to be returned + + // The number of SATA command + Name (CMDC, 0) // SATA Commands counter + + // Build the return buffer for GTF() control method + Method (GTFB, 2, Serialized) + // Arg0 - Command to write + // Arg1 - Subcommand value for "Set Feature command" + { + Multiply(CMDC, 56, Local0) + CreateField(SCBF, Local0, 56, CMDx) // Command field + Multiply(CMDC, 7, Local0) + CreateByteField(SCBF, Add(Local0, 1), A001) // Subcommand of "Set Feature" command + Store(Arg0, CMDx) // Store command into return buffer + Store(Arg1, A001) // Set Subcommand code + Increment(CMDC) + } +} + +Scope(\_SB.PCI0.SAT0) +{ + Name(REGF, 1) // PCI Bus access Flag + + Method(_REG, 2) // is PCI Config space accessible as OpRegion? + // _REG to update REGF status + { + If(LEqual(Arg0, 0x2)) + { + Store(Arg1, REGF) + } + } + // Buffer to be returned by _GTM + Name(TMD0, Buffer(20){}) // 5 DWORD length + CreateDWordField(TMD0, 00, PIO0) + CreateDWordField(TMD0, 04, DMA0) + CreateDWordField(TMD0, 8, PIO1) // do not use "08" + CreateDWordField(TMD0, 12, DMA1) + CreateDWordField(TMD0, 16, CHNF) + + // Get Timing PIO/DMA Mode + Method(_GTM,0 ) { // Return Buffer + // PIO 0 Speed DWORD + // DMA 0 Speed DWORD + // PIO 1 Speed DWORD + // DMA 1 Speed DWORD + // Flags DWORD + + Store(120, PIO0) // Forced to PIO Mode 4 + Store(20, DMA0) // Forced to UDMA Mode 5 + Store(120, PIO1) // Forced to PIO Mode 4 + Store(20, DMA1) // Forced to UDMA Mode 5 + + Or(CHNF, 0x05, CHNF) + + Return (TMD0) + } // end Method _GTM +//////////////////////////////////////////////////////////////////////////////// + // Set Timing PIO/DMA Mode + Method(_STM, 3) // Arg 0 = Channel Timing Info (Package) + // Arg 1 = ATA Command set Master(Buffer) + // Arg 2 = ATA Command set Slave (Buffer) + {} // end Method _STM +//////////////////////////////////////////////////////////////////////////////// +#if defined(ASL_ZPODD_SATA_PORT) && (ASL_ZPODD_SATA_PORT==0) +#else + // SATA PORT0 // + Device(SPT0) + { + Name(_ADR,0x0000FFFF) + + // GET TASK FILE METHOD + Method(_GTF, 0, NotSerialized) { + Store(0, CMDC) // SATA Commands counter + + If(LEqual(DSSP, 0x1)) { // Check DISABLE_SOFT_SET_PREV SDL Token Enabled + GTFB(STFD, 0x06) // Disable SW Preservation Settings + } else { + GTFB(STFE, 0x06) // Enable SW Preservation Settings + } + + GTFB(FZTF, 0x00) // Issue Freeze Lock Command + GTFB(DCFL, 0x00) // Issue Device Configuration Freeze Lock Command + Return(SCBF) + } + } + +#endif + // SATA PORT1 // +#if defined(ASL_ZPODD_SATA_PORT) && (ASL_ZPODD_SATA_PORT==1) +#else + Device(SPT1) + { + Name(_ADR,0x0001FFFF) + + // GET TASK FILE METHOD + Method(_GTF, 0, NotSerialized) { + Store(0, CMDC) // SATA Commands counter + + If(LEqual(DSSP, 0x1)) { // Check DISABLE_SOFT_SET_PREV SDL Token Enabled + GTFB(STFD, 0x06) // Disable SW Preservation Settings + } else { + GTFB(STFE, 0x06) // Enable SW Preservation Settings + } + + GTFB(FZTF, 0x00) // Issue Freeze Lock Command + GTFB(DCFL, 0x00) // Issue Device Configuration Freeze Lock Command + Return(SCBF) + } + } + +#endif + // SATA PORT2 // +#if defined(ASL_ZPODD_SATA_PORT) && (ASL_ZPODD_SATA_PORT==2) +#else + Device(SPT2) + { + Name(_ADR,0x0002FFFF) + + // GET TASK FILE METHOD + Method(_GTF, 0, NotSerialized) { + Store(0, CMDC) // SATA Commands counter + + If(LEqual(DSSP, 0x1)) { // Check DISABLE_SOFT_SET_PREV SDL Token Enabled + GTFB(STFD, 0x06) // Disable SW Preservation Settings + } else { + GTFB(STFE, 0x06) // Enable SW Preservation Settings + } + + GTFB(FZTF, 0x00) // Issue Freeze Lock Command + GTFB(DCFL, 0x00) // Issue Device Configuration Freeze Lock Command + Return(SCBF) + } + } + +#endif + // SATA PORT3 // +#if defined(ASL_ZPODD_SATA_PORT) && (ASL_ZPODD_SATA_PORT==3) +#else + Device(SPT3) + { + Name(_ADR,0x0003FFFF) + + // GET TASK FILE METHOD + Method(_GTF, 0, NotSerialized) { + Store(0, CMDC) // SATA Commands counter + + If(LEqual(DSSP, 0x1)) { // Check DISABLE_SOFT_SET_PREV SDL Token Enabled + GTFB(STFD, 0x06) // Disable SW Preservation Settings + } else { + GTFB(STFE, 0x06) // Enable SW Preservation Settings + } + + GTFB(FZTF, 0x00) // Issue Freeze Lock Command + GTFB(DCFL, 0x00) // Issue Device Configuration Freeze Lock Command + Return(SCBF) + } + } + +#endif + // SATA PORT4 // +#if defined(ASL_ZPODD_SATA_PORT) && (ASL_ZPODD_SATA_PORT==4) +#else + Device(SPT4) + { + Name(_ADR,0x0004FFFF) + + // GET TASK FILE METHOD + Method(_GTF, 0, NotSerialized) { + Store(0, CMDC) // SATA Commands counter + + If(LEqual(DSSP, 0x1)) { // Check DISABLE_SOFT_SET_PREV SDL Token Enabled + GTFB(STFD, 0x06) // Disable SW Preservation Settings + } else { + GTFB(STFE, 0x06) // Enable SW Preservation Settings + } + + GTFB(FZTF, 0x00) // Issue Freeze Lock Command + GTFB(DCFL, 0x00) // Issue Device Configuration Freeze Lock Command + Return(SCBF) + } + } + +#endif + // SATA PORT5 // +#if defined(ASL_ZPODD_SATA_PORT) && (ASL_ZPODD_SATA_PORT==5) +#else + Device(SPT5) + { + Name(_ADR,0x0005FFFF) + + // GET TASK FILE METHOD + Method(_GTF, 0, NotSerialized) { + Store(0, CMDC) // SATA Commands counter + + If(LEqual(DSSP, 0x1)) { // Check DISABLE_SOFT_SET_PREV SDL Token Enabled + GTFB(STFD, 0x06) // Disable SW Preservation Settings + } else { + GTFB(STFE, 0x06) // Enable SW Preservation Settings + } + + GTFB(FZTF, 0x00) // Issue Freeze Lock Command + GTFB(DCFL, 0x00) // Issue Device Configuration Freeze Lock Command + Return(SCBF) + } + } +#endif +} +}//end of SSDT + + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//*************************************************************************
\ No newline at end of file diff --git a/Chipset/SB/SB.ASL b/Chipset/SB/SB.ASL new file mode 100644 index 0000000..2a86c98 --- /dev/null +++ b/Chipset/SB/SB.ASL @@ -0,0 +1,341 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SB.ASL 7 7/15/13 3:19a Scottyang $ +// +// $Revision: 7 $ +// +// $Date: 7/15/13 3:19a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SB.ASL $ +// +// 7 7/15/13 3:19a Scottyang +// [TAG] EIP129089 +// [Category] Improvement +// [Description] Update PCH RC 1.6.1. +// [Files] SBDxe.c, SB.asl, ..\ReferenceCode\Chipset\LynxPoint\*.* +// +// 6 4/24/13 6:00a Scottyang +// [TAG] EIP121262 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] WOL BSOD +// [RootCause] When resume to OS hardware signal not ready. That made a +// dead loop in OS. +// [Solution] Remove while loop and add sychnorized the object in asl +// code. +// [Files] SB.asl, PchPcie.asl +// +// 5 4/08/13 2:51a Wesleychen +// [TAG] EIP118045 +// [Category] Improvement +// [Description] Creat tokens to support Power Button Notify +// for misc events. +// [Files] SB.SDL; SB.ASL +// +// 4 1/11/13 5:10a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Remove EIP105442 temp solution. +// [Files] SB.ASL, Pch.asl +// +// 3 11/26/12 12:39a Scottyang +// [TAG] EIP105442 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] After S3 resum cannot use FPT win64 +// [RootCause] The SPI HSFS register "Access Error Log" bit has been +// set. +// [Solution] Clear "Access Error Log" bit after resume. +// [Files] SB.ASL, Pch.asl +// +// 2 8/13/12 10:24a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update definition in ASL code for building when +// disabled PCI objects. +// [Files] SB.ASL +// +// 1 2/08/12 8:24a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SB.asl +// +// Description: The ASL file is for South Bridge specific function. +// +//<AMI_FHDR_END> +//************************************************************************* +Scope(\_SB.PCI0.LPCB) +{ + + OperationRegion(CPSB, SystemMemory, 0xC0000000, 16) // Relocatable + Field(CPSB, AnyAcc, NoLock, Preserve) //Field + { + RTCX, 1, + SBB0, 7, + SBB1, 8, + SBB2, 8, + SBB3, 8, + SBB4, 8, + SBB5, 8, + SBB6, 8, + SBB7, 8, + SBB8, 8, + SBB9, 8, + SBBA, 8, + SBBB, 8, + SBBC, 8, + SBBD, 8, + SBBE, 8, + SBBF, 8, + } + +/* +;<AMI_PHDR_START> +;------------------------------------------------------------------------ +; +; Procedure: SPTS +; Description: METHOD IS CALLED BY OS PRIOR TO ENTER ANY SLEEP STATE +; Input: Arg0 = Arg0 = Sleep state System about to enter +; Output: Nothing +; +;------------------------------------------------------------------------- +;<AMI_PHDR_END> +*/ + Method (SPTS, 1) { + Store(One, SLPX) // Clear SLP_SMI Status + Store(One, SLPE) // Enable SLP_SMI + +#if defined(ASL_RC_PORT_0) && (ASL_RC_PORT_0==1) + Store(Zero, \_SB.PCI0.RP01.RPAV) +#endif +#if defined(ASL_RC_PORT_1) && (ASL_RC_PORT_1==1) + Store(Zero, \_SB.PCI0.RP02.RPAV) +#endif +#if defined(ASL_RC_PORT_2) && (ASL_RC_PORT_2==1) + Store(Zero, \_SB.PCI0.RP03.RPAV) +#endif +#if defined(ASL_RC_PORT_3) && (ASL_RC_PORT_3==1) + Store(Zero, \_SB.PCI0.RP04.RPAV) +#endif +#if defined(ASL_RC_PORT_4) && (ASL_RC_PORT_4==1) + Store(Zero, \_SB.PCI0.RP05.RPAV) +#endif +#if defined(ASL_RC_PORT_5) && (ASL_RC_PORT_5==1) + Store(Zero, \_SB.PCI0.RP06.RPAV) +#endif +#if defined(ASL_RC_PORT_6) && (ASL_RC_PORT_6==1) + Store(Zero, \_SB.PCI0.RP07.RPAV) +#endif +#if defined(ASL_RC_PORT_7) && (ASL_RC_PORT_7==1) + Store(Zero, \_SB.PCI0.RP08.RPAV) +#endif + } + +/* +;<AMI_PHDR_START> +;------------------------------------------------------------------------ +; +; Procedure: SWAK +; Description: METHOD CALLED ON WAKE UP FROM ANY SLEEP STATE +; Input: Arg0 = Sleep state System is resuming from +; Output: Nothing +; +;------------------------------------------------------------------------ +;<AMI_PHDR_END> +*/ + Method (SWAK, 1) { + Store(Zero, SLPE) // Disable SLP_SMI +#if defined ASL_SX_NOTIFY_PWRB && ASL_SX_NOTIFY_PWRB == 1 + If (RTCS) {} + Else {Notify(\_SB.PWRB, 0x02)} +#endif + } + + OperationRegion (SMIE, SystemIO, PMBS, 4) + Field (SMIE, ByteAcc,NoLock,Preserve) { + ,10, + RTCS, 1, + , 3, + PEXS, 1, + WAKS, 1, + , 8, + PWBT, 1, + , 7, + } + + OperationRegion (SLPR, SystemIO, SMCR, 8) + Field (SLPR, ByteAcc,NoLock,Preserve) { + , 4, + SLPE,1, + ,31, + SLPX,1, + ,27, + } +}//Scope(\_SB.PCI0.LPCB) + +#if defined (ASL_RC_PORT_0) && (ASL_RC_PORT_0==1) +Scope(\_SB.PCI0.RP01) +{ + // + // Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR1, LTRE) + Store (PML1, LMSL) + Store (PNL1, LNSL) + Store (OBF1, OBFF) + } + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } +}//Scope(\_SB.PCI0.RP01) +#endif + +#if defined (ASL_RC_PORT_1) && (ASL_RC_PORT_1==1) +Scope(\_SB.PCI0.RP02) +{ + // + // Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR2, LTRE) + Store (PML2, LMSL) + Store (PNL2, LNSL) + Store (OBF2, OBFF) + } + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } +}//Scope(\_SB.PCI0.RP02) +#endif + +#if defined (ASL_RC_PORT_2) && (ASL_RC_PORT_2==1) +Scope(\_SB.PCI0.RP03) +{ + // + // Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR3, LTRE) + Store (PML3, LMSL) + Store (PNL3, LNSL) + Store (OBF3, OBFF) + } + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } +}//Scope(\_SB.PCI0.RP03) +#endif + +#if defined (ASL_RC_PORT_3) && (ASL_RC_PORT_3==1) +Scope(\_SB.PCI0.RP04) +{ + // + // Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR4, LTRE) + Store (PML4, LMSL) + Store (PNL4, LNSL) + Store (OBF4, OBFF) + } + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } +}//Scope(\_SB.PCI0.RP04) +#endif + +#if defined (ASL_RC_PORT_4) && (ASL_RC_PORT_4==1) +Scope(\_SB.PCI0.RP05) +{ + // + // Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR5, LTRE) + Store (PML5, LMSL) + Store (PNL5, LNSL) + Store (OBF5, OBFF) + } + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } +}//Scope(\_SB.PCI0.RP05) +#endif + +#if defined (ASL_RC_PORT_5) && (ASL_RC_PORT_5==1) +Scope(\_SB.PCI0.RP06) +{ + // + // Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR6, LTRE) + Store (PML6, LMSL) + Store (PNL6, LNSL) + Store (OBF6, OBFF) + } + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } +}//Scope(\_SB.PCI0.RP06) +#endif + +#if defined (ASL_RC_PORT_6) && (ASL_RC_PORT_6==1) +Scope(\_SB.PCI0.RP07) +{ + // + // Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR7, LTRE) + Store (PML7, LMSL) + Store (PNL7, LNSL) + Store (OBF7, OBFF) + } + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } +}//Scope(\_SB.PCI0.RP07) +#endif + +#if defined (ASL_RC_PORT_7) && (ASL_RC_PORT_7==1) +Scope(\_SB.PCI0.RP08) +{ + // + // Pass LTRx to LTRE so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR8, LTRE) + Store (PML8, LMSL) + Store (PNL8, LNSL) + Store (OBF8, OBFF) + } + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } +}//Scope(\_SB.PCI0.RP08) +#endif +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/SBCspLib.h b/Chipset/SB/SBCspLib.h new file mode 100644 index 0000000..e16cf63 --- /dev/null +++ b/Chipset/SB/SBCspLib.h @@ -0,0 +1,1536 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SBCspLib.h 11 5/16/14 6:16a Barretlin $ +// +// $Revision: 11 $ +// +// $Date: 5/16/14 6:16a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SBCspLib.h $ +// +// 11 5/16/14 6:16a Barretlin +// [TAG] EIP167087 +// [Category] Improvement +// [Description] BIOS security improvement on Haswell CRB project +// [Files] SBGeneric.c SBDxe.c SBCspLib.h Sb.sdl Sb.sd +// +// 10 4/19/13 6:36a Wesleychen +// [TAG] None +// [Category] Improvement +// [Description] Update GbES02SxWorkaround() and add +// UsbS02SxWorkaround() for SBPwrBtnHandler(). +// [Files] SBSMI.c; SBSMI.h; SBGeneric.c; SBCspLib.h +// +// 9 3/19/13 8:33a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Improve alternate access mode enable/disable routine. +// [Files] SBGeneric.c, SBCspLib.h, SBSMI.c +// +// 8 1/10/13 8:20a Scottyang +// [TAG] EIP111666 +// [Category] New Feature +// [Description] Support OEM reset callback function Elink. +// [Files] SB.mak, SBCspLib.h, SBGeneric.c, SB.sdl, PchReset.c +// +// 7 11/21/12 3:07a Scottyang +// +// 5 9/12/12 5:17a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Remove useless HdmiVerbTable. +// [Files] SB.sdl, SBCspLib.h, SBDxe.c, SBGeneric.c +// +// 4 8/24/12 6:49a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Remove useless SB_SHADOW_CONTROL. +// [Files] SB.sdl, SBCspLib.h, SBGeneric.c +// +// 3 8/13/12 10:25a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Implement BIOS Lock function. +// [Files] SBCspLib.h, SBDxe.c, SBSMI.c, SBSMI.dxs, SBSMI.sdl +// +// 2 7/02/12 10:18a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Updated and modified for PCH RC 0.6.0. +// [Files] SBGeneric.c, SB.sdl, SBCspLib.h, SBDxe.c, SBPEI.c +// +// 1 2/08/12 8:24a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SBCspLib.h +// +// Description: This file contains South Bridge chipset porting functions +// and data structures definition for both PEI & DXE stage. +// +//<AMI_FHDR_END> +//************************************************************************* + +#ifndef __SBLIB_H__ +#define __SBLIB_H__ + +//--------------------------------------------------------------------------- +#include <Token.h> +#include <Efi.h> +#include <Pei.h> +#include <AmiDxeLib.h> +#include <PciBus.h> +#include <ppi\ReadOnlyVariable2.h> +#include <Protocol\PciRootBridgeIo.h> +#include <Protocol\PciIo.h> +#include <Protocol\AmiSio.h> + +#if ACPI_SUPPORT + #if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A) + #include <Protocol\S3SaveState.h> + #else + #include <Protocol\BootScriptSave.h> + #endif +#endif + + +#if CSM_SUPPORT +#include <Protocol\LegacyInterrupt.h> +#endif + +#ifndef AMI_S3_SAVE_PROTOCOL + #if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A) +#define AMI_S3_SAVE_PROTOCOL EFI_S3_SAVE_STATE_PROTOCOL +#define AMI_S3_SAVE_PROTOCOL_GUID &gEfiS3SaveStateProtocolGuid + #else +#define AMI_S3_SAVE_PROTOCOL EFI_BOOT_SCRIPT_SAVE_PROTOCOL +#define AMI_S3_SAVE_PROTOCOL_GUID &gEfiBootScriptSaveGuid + #endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef CORE_VERSION +#define CORE_VERSION ( CORE_MAJOR_VERSION * 1000 + \ + CORE_MINOR_VERSION * 100 + \ + CORE_REVISION * 10 + \ + CORE_BUILD_NUMBER ) +#endif + +#ifndef PCIBUS_VERSION +#define PCIBUS_VERSION ( PCI_BUS_MAJOR_VER * 10000 + \ + PCI_BUS_MINOR_VER * 100 + \ + PCI_BUS_REVISION ) +#endif + +#define COMPLETE_SAVE_RESTORE_STD_CMOS 0x00 +#define ENABLE_NMI_BEFORE_SMI_EXIT 0x01 +#define DISABLE_NMI_BEFORE_SMI_EXIT 0x02 + +#ifndef EFI_SIGNATURE_16 +#define EFI_SIGNATURE_16(A, B) ((A) | (B << 8)) +#endif + +#ifndef EFI_SIGNATURE_32 +#define EFI_SIGNATURE_32(A, B, C, D) (EFI_SIGNATURE_16 (A, B) | (EFI_SIGNATURE_16 (C, D) << 16)) +#endif + +#define KBShift 10 +#define MBShift 20 + +typedef enum { + PchH = 1, + PchLp, + PchUnknownSeries +} PCH_SERIES; + +// Type Definition(s) + +typedef struct { + UINT64 Address; + EFI_BOOT_SCRIPT_WIDTH Width; + UINT32 Mask; +} BOOT_SCRIPT_SB_PCI_REG_SAVE; + +typedef enum { + SbResetFull, + SbResetGlobal +} SB_EXT_RESET_TYPE; + +typedef enum { + AnyType, + DescriptorType, + BiosType, + MeType, + GbeType, + PlatformDataType, + DeviceExpansionType, + SecondaryBiosType, + BfpregType, + PchSpiRangeTypeMax +} AMI_SB_SPI_RANGE_TYPE; + +typedef struct{ + UINTN ProtectedRangeType; + BOOLEAN WriteProtectEnable; + BOOLEAN ReadProtectEnable; + UINTN ProtectedRangeBase; + UINTN ProtectedRangeLength; +} SPI_PROTECTED_RANGE_CONIFG; + +#if CSM_SUPPORT + +EFI_STATUS SBGen_InitializeRouterRegisters ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRBIo +); + +UINT8 SBGen_GetPIRQIndex ( + IN UINT8 PIRQRegister +); + +EFI_STATUS SBGen_ReadPirq ( + IN EFI_LEGACY_INTERRUPT_PROTOCOL *This, + IN UINT8 PirqNumber, + OUT UINT8 *PirqData +); + +EFI_STATUS SBGen_WritePirq ( + IN EFI_LEGACY_INTERRUPT_PROTOCOL *This, + IN UINT8 PirqNumber, + IN UINT8 PirqData +); + +#endif + +EFI_STATUS SBProtectedPciDevice ( + IN PCI_DEV_INFO *PciDevice +); + +EFI_STATUS SBProgramPciDevice ( + IN PCI_DEV_INFO *PciDevice +); + +EFI_STATUS SBUpdatePciDeviceAttributes ( + IN PCI_DEV_INFO *PciDevice, + IN OUT UINT64 *Attributes, + IN UINT64 Capabilities, + IN BOOLEAN Set +); + +EFI_STATUS ReadSPIDescriptor ( + IN UINT8 FDSS, + IN UINT8 FDSI, + OUT UINT32 *FDOD +); + +UINT32 GetTotalFlashRomSize( VOID ); + +EFI_STATUS SbGetSpiRangeAddresses( + IN AMI_SB_SPI_RANGE_TYPE RangeType, + OUT UINT32 *BaseAddress, + OUT UINT32 *EndAddress +); + +EFI_STATUS SbFlashProtectedRange( VOID ); + +UINT32 SbFindCapPtr( + IN UINT64 PciAddress, + IN UINT8 CapId +); + +VOID SBSwSmiWriteToBootScript ( + IN AMI_S3_SAVE_PROTOCOL *BootScriptSave +); + +EFI_STATUS SBGen_WriteBootScript ( + IN AMI_S3_SAVE_PROTOCOL *BootScriptSave +); + +VOID WriteIo8IdxDataS3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT16 IoBase16, + IN UINT8 IoReg8, + IN UINT8 WriteValue8 +); + +VOID RwIo8IdxDataS3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT16 IoBase16, + IN UINT8 IoReg8, + IN UINT8 SetBit8, + IN UINT8 ResetBit8 +); + +VOID WriteIo8S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT16 IoBaseReg16, + IN UINT8 WriteValue8 +); + +VOID WriteIo16S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT16 IoBaseReg16, + IN UINT16 WriteValue16 +); + +VOID WriteIo32S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT16 IoBaseReg16, + IN UINT32 WriteValue32 +); + +VOID RwIo8S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT16 IoBaseReg16, + IN UINT8 SetBit8, + IN UINT8 ResetBit8 +); + +VOID RwIo16S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT16 IoBaseReg16, + IN UINT16 SetBit16, + IN UINT16 ResetBit16 +); + +VOID RwIo32S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT16 IoBaseReg16, + IN UINT32 SetBit32, + IN UINT32 ResetBit32 +); + +VOID SBLib_BeforeShutdown ( VOID ); + +VOID SBLib_Shutdown ( VOID ); +VOID GbES0ToS1Workaround(VOID); +VOID GbES0ToSxWorkaround(VOID); +VOID Enable_GbE_PME(VOID); +VOID ClearMeWakeSts(VOID); +VOID EHCIAdditionalRequirement(VOID); + +BOOLEAN SBIsDefaultConfigMode ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *ReadVariablePpi +); + +UINT8 SBLib_CmosRead( + IN UINT8 Index +); + +VOID SBLib_CmosWrite( + IN UINT8 Index, + IN UINT8 Value +); + +PCH_SERIES +EFIAPI +GetPchSeries ( + VOID +); + +UINT8 +EFIAPI +GetPchMaxPciePortNum ( + VOID +); + +UINT8 +EFIAPI +GetPchMaxSataPortNum ( + VOID +); + +UINT8 +EFIAPI +GetPchUsbMaxPhysicalPortNum ( + VOID +); + +UINT8 +EFIAPI +GetPchXhciMaxUsb3PortNum ( + VOID +); + +UINT8 +EFIAPI +GetPchEhciMaxControllerNum ( + VOID +); + +EFI_STATUS +SbLib_RunTimeResetCallback( + IN EFI_RESET_TYPE ResetType + ); + +#if SB_RESET_PPI_SUPPORT +VOID SBLib_ResetSystem ( + IN EFI_RESET_TYPE ResetType +); +#endif + +VOID SBLib_ExtResetSystem ( + IN SB_EXT_RESET_TYPE ResetType +); + +#if SB_STALL_PPI_SUPPORT +EFI_STATUS CountTime ( + IN UINTN DelayTime, + IN UINT16 BaseAddr // only needs to be 16 bit for I/O address +); +#endif + +#if SMM_SUPPORT +EFI_STATUS SBSmmSaveRestoreStates ( + IN BOOLEAN Save +); +#endif + +//--------------------------------------------------------------------------- +// CMOS Manager Support +// +// Southbridge should implement functions to support access to additional +// CMOS banks that exist beyond the first 128 bytes. +//--------------------------------------------------------------------------- + +#if CMOS_MANAGER_SUPPORT +#include <CmosAccess.h> + +EFI_STATUS ReadWriteCmosBank2 ( + IN EFI_PEI_SERVICES **PeiServices, // NULL in DXE phase + IN CMOS_ACCESS_TYPE AccessType, + IN UINT16 CmosRegister, + IN OUT UINT8 *CmosParameterValue +); + +BOOLEAN SbGetRtcPowerStatus ( + IN EFI_PEI_SERVICES **PeiServices // NULL in DXE phase +); + +#endif // #if CMOS_MANAGER_SUPPORT + +//--------------------------------------------------------------------------- + +//UINT8 ReadCmos (IN UINT8 Index); +//VOID WriteCmos (IN UINT8 Index, IN UINT8 Value); +BOOLEAN SbLib_GetSmiState (VOID); +VOID SbLib_SmiDisable (VOID); +VOID SbLib_SmiEnable (VOID); +VOID CspLibCheckPowerLoss (VOID); + +//--------------------------------------------------------------------------- + +VOID ChipsetFlashDeviceWriteEnable (VOID); +VOID ChipsetFlashDeviceWriteDisable (VOID); + +//--------------------------------------------------------------------------- + +EFI_STATUS SbLib_SetLpcDeviceDecoding ( + IN EFI_PCI_IO_PROTOCOL *LpcPciIo, + IN UINT16 Base, + IN UINT8 DevUid, + IN SIO_DEV_TYPE Type +); + +EFI_STATUS SbLib_SetLpcGenericDecoding ( + IN EFI_PCI_IO_PROTOCOL *LpcPciIo, + IN UINT16 Base, + IN UINT16 Length, + IN BOOLEAN Enable +); + +//--------------------------------------------------------------------------- +UINT8 RtcRead ( + IN UINT8 Location +); + +UINT8 ReadIo8IdxData ( + IN UINT16 IoBase16, + IN UINT8 RegIdx8 +); + +VOID WriteIo8IdxData ( + IN UINT16 IoBase16, + IN UINT8 RegIdx8, + IN UINT8 WriteValue8 +); + +VOID RwIo8IdxData ( + IN UINT16 IoBase16, + IN UINT8 RegIdx8, + IN UINT8 SetBit8, + IN UINT8 ResetBit8 +); + +VOID BiosLockEnableSMIFlashHook ( + IN UINT8 SwSmiNum, + IN OUT UINT64 Buffer +); + +VOID SwitchAlternateAccessMode //Improve alternate access mode >> +( + BOOLEAN Switch +); + +UINT8 ReadPort70h ( VOID ); //Improve alternate access mode << +//--------------------------------------------------------------------------- +// Standard I/O Macros, No Porting Required. +//--------------------------------------------------------------------------- +#define ReadIo8(IoAddr) IoRead8(IoAddr) +#define READ_IO8(IoAddr) IoRead8(IoAddr) +#define WriteIo8(IoAddr, bVal) IoWrite8(IoAddr, bVal) +#define WRITE_IO8(IoAddr, bVal) IoWrite8(IoAddr, bVal) +#define SET_IO8(IoAddr, bSet) IoWrite8(IoAddr, IoRead8(IoAddr) | (bSet)) +#define RESET_IO8(IoAddr, bRst) IoWrite8(IoAddr, IoRead8(IoAddr) & ~(bRst)) +#define RW_IO8(Bx, Set, Rst) IoWrite8(Bx, IoRead8(Bx) & ~(Rst) | (Set)) +#define ReadIo16(IoAddr) IoRead16(IoAddr) +#define READ_IO16(IoAddr) IoRead16(IoAddr) +#define WriteIo16(IoAddr, wVal) IoWrite16(IoAddr, wVal) +#define WRITE_IO16(IoAddr, wVal) IoWrite16(IoAddr, wVal) +#define SET_IO16(IoAddr, wSet) IoWrite16(IoAddr, IoRead16(IoAddr) | (wSet)) +#define RESET_IO16(IoAddr, Rst) IoWrite16(IoAddr, IoRead16(IoAddr) & ~(Rst)) +#define RW_IO16(Bx, Set, Rst) IoWrite16(Bx, IoRead16(Bx) & ~(Rst) | (Set)) +#define ReadIo32(IoAddr) IoRead32(IoAddr) +#define READ_IO32(IoAddr) IoRead32(IoAddr) +#define WriteIo32(IoAddr, dVal) IoWrite32(IoAddr, dVal) +#define WRITE_IO32(IoAddr, dVal) IoWrite32(IoAddr, dVal) +#define SET_IO32(IoAddr, dSet) IoWrite32(IoAddr, IoRead32(IoAddr) | (dSet)) +#define RESET_IO32(IoAddr, Rst) IoWrite32(IoAddr, IoRead32(IoAddr) & ~(Rst)) +#define RW_IO32(Bx, Set, Rst) IoWrite32(Bx, IoRead32(Bx) & ~(Rst) | (Set)) + +#define WRITE_IO8_S3(mBtScSv, IoAddr16, bValue) \ + WriteIo8S3(mBtScSv, IoAddr16, bValue) +#define SET_IO8_S3(mBtScSv, IoAddr16, bSet) \ + RwIo8S3(mBtScSv, IoAddr16, bSet, 0) +#define RESET_IO8_S3(mBtScSv, IoAddr16, bReset) \ + RwIo8S3(mBtScSv, IoAddr16, 0, bReset) +#define RW_IO8_S3(mBtScSv, IoAddr16, bSet, bReset) \ + RwIo8S3(mBtScSv, IoAddr16, bSet, bReset) +#define WRITE_IO16_S3(mBtScSv, IoAddr16, wValue) \ + WriteIo16S3(mBtScSv, IoAddr16, wValue) +#define SET_IO16_S3(mBtScSv, IoAddr16, wSet) \ + RwIo16S3(mBtScSv, IoAddr16, wSet, 0) +#define RESET_IO16_S3(mBtScSv, IoAddr16, wReset) \ + RwIo16S3(mBtScSv, IoAddr16, 0, wReset) +#define RW_IO16_S3(mBtScSv, IoAddr16, wSet, wReset) \ + RwIo16S3(mBtScSv, IoAddr16, wSet, wReset) +#define WRITE_IO32_S3(mBtScSv, IoAddr16, dValue) \ + WriteIo32S3(mBtScSv, IoAddr16, dValue) +#define SET_IO32_S3(mBtScSv, IoAddr16, dSet) \ + RwIo32S3(mBtScSv, IoAddr16, dSet, 0) +#define RESET_IO32_S3(mBtScSv, IoAddr16, dReset) \ + RwIo32S3(mBtScSv, IoAddr16, 0, dReset) +#define RW_IO32_S3(mBtScSv, IoAddr16, dSet, dReset) \ + RwIo32S3(mBtScSv, IoAddr16, dSet, dReset) + +//--------------------------------------------------------------------------- +// Chipset PCI Macros, Porting Required. +//--------------------------------------------------------------------------- + +#define READ_PCI8_SB(Rx) READ_PCI8(SB_BUS, SB_DEV, SB_FUN, Rx) +#define WRITE_PCI8_SB(Rx, Val) WRITE_PCI8(SB_BUS, SB_DEV, SB_FUN, Rx, Val) +#define SET_PCI8_SB(Rx, Set) SET_PCI8(SB_BUS, SB_DEV, SB_FUN, Rx, Set) +#define RESET_PCI8_SB(Rx, Rst) RESET_PCI8(SB_BUS, SB_DEV, SB_FUN, Rx, Rst) +#define RW_PCI8_SB(Rx, St, Rt) RW_PCI8(SB_BUS, SB_DEV, SB_FUN, Rx, St, Rt) +#define READ_PCI16_SB(Rx) READ_PCI16(SB_BUS, SB_DEV, SB_FUN, Rx) +#define WRITE_PCI16_SB(Rx, Val) WRITE_PCI16(SB_BUS, SB_DEV, SB_FUN, Rx, Val) +#define SET_PCI16_SB(Rx, Set) SET_PCI16(SB_BUS, SB_DEV, SB_FUN, Rx, Set) +#define RESET_PCI16_SB(Rx, Rst) RESET_PCI16(SB_BUS, SB_DEV, SB_FUN, Rx, Rst) +#define RW_PCI16_SB(Rx, St, Rt) RW_PCI16(SB_BUS, SB_DEV, SB_FUN, Rx, St, Rt) +#define READ_PCI32_SB(Rx) READ_PCI32(SB_BUS, SB_DEV, SB_FUN, Rx) +#define WRITE_PCI32_SB(Rx, Val) WRITE_PCI32(SB_BUS, SB_DEV, SB_FUN, Rx, Val) +#define SET_PCI32_SB(Rx, Set) SET_PCI32(SB_BUS, SB_DEV, SB_FUN, Rx, Set) +#define RESET_PCI32_SB(Rx, Rst) RESET_PCI32(SB_BUS, SB_DEV, SB_FUN, Rx, Rst) +#define RW_PCI32_SB(Rx, St, Rt) RW_PCI32(SB_BUS, SB_DEV, SB_FUN, Rx, St, Rt) + +//--------------------------------------------------------------------------- + +#define READ_PCI8_SATA(Rx) \ + READ_PCI8(SATA_BUS, SATA_DEV, SATA_FUN, Rx) +#define WRITE_PCI8_SATA(Rx, Val) \ + WRITE_PCI8(SATA_BUS, SATA_DEV, SATA_FUN, Rx, Val) +#define SET_PCI8_SATA(Rx, Set) \ + SET_PCI8(SATA_BUS, SATA_DEV, SATA_FUN, Rx, Set) +#define RESET_PCI8_SATA(Rx, Rst) \ + RESET_PCI8(SATA_BUS, SATA_DEV, SATA_FUN, Rx, Rst) +#define RW_PCI8_SATA(Rx, Set, Rst) \ + RW_PCI8(SATA_BUS, SATA_DEV, SATA_FUN, Rx, Set, Rst) +#define READ_PCI16_SATA(Rx) \ + READ_PCI16(SATA_BUS, SATA_DEV, SATA_FUN, Rx) +#define WRITE_PCI16_SATA(Rx, Val) \ + WRITE_PCI16(SATA_BUS, SATA_DEV, SATA_FUN, Rx, Val) +#define SET_PCI16_SATA(Rx, Set) \ + SET_PCI16(SATA_BUS, SATA_DEV, SATA_FUN, Rx, Set) +#define RESET_PCI16_SATA(Rx, Rst) \ + RESET_PCI16(SATA_BUS, SATA_DEV, SATA_FUN, Rx, Rst) +#define RW_PCI16_SATA(Rx, Set, Rst) \ + RW_PCI16(SATA_BUS, SATA_DEV, SATA_FUN, Rx, Set, Rst) +#define READ_PCI32_SATA(Rx) \ + READ_PCI32(SATA_BUS, SATA_DEV, SATA_FUN, Rx) +#define WRITE_PCI32_SATA(Rx, Val) \ + WRITE_PCI32(SATA_BUS, SATA_DEV, SATA_FUN, Rx, Val) +#define SET_PCI32_SATA(Rx, Set) \ + SET_PCI32(SATA_BUS, SATA_DEV, SATA_FUN, Rx, Set) +#define RESET_PCI32_SATA(Rx, Rst) \ + RESET_PCI32(SATA_BUS, SATA_DEV, SATA_FUN, Rx, Rst) +#define RW_PCI32_SATA(Rx, Set, Rst) \ + RW_PCI32(SATA_BUS, SATA_DEV, SATA_FUN, Rx, Set, Rst) + +//--------------------------------------------------------------------------- + +#define READ_PCI8_SATA2(Rx) \ + READ_PCI8(SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx) +#define WRITE_PCI8_SATA2(Rx, Val) \ + WRITE_PCI8(SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Val) +#define SET_PCI8_SATA2(Rx, Set) \ + SET_PCI8(SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Set) +#define RESET_PCI8_SATA2(Rx, Rst) \ + RESET_PCI8(SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Rst) +#define RW_PCI8_SATA2(Rx, Set, Rst) \ + RW_PCI8(SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Set, Rst) +#define READ_PCI16_SATA2(Rx) \ + READ_PCI16(SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx) +#define WRITE_PCI16_SATA2(Rx, Val) \ + WRITE_PCI16(SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Val) +#define SET_PCI16_SATA2(Rx, Set) \ + SET_PCI16(SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Set) +#define RESET_PCI16_SATA2(Rx, Rst) \ + RESET_PCI16(SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Rst) +#define RW_PCI16_SATA2(Rx, Set, Rst) \ + RW_PCI16(SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Set, Rst) +#define READ_PCI32_SATA2(Rx) \ + READ_PCI32(SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx) +#define WRITE_PCI32_SATA2(Rx, Val) \ + WRITE_PCI32(SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Val) +#define SET_PCI32_SATA2(Rx, Set) \ + SET_PCI32(SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Set) +#define RESET_PCI32_SATA2(Rx, Rst) \ + RESET_PCI32(SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Rst) +#define RW_PCI32_SATA2(Rx, Set, Rst) \ + RW_PCI32(SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Set, Rst) + +//--------------------------------------------------------------------------- + +#define READ_PCI8_PCIEBRS(Rx) \ + READ_PCI8(PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx) +#define WRITE_PCI8_PCIEBRS(Rx, Val) \ + WRITE_PCI8(PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Val) +#define SET_PCI8_PCIEBRS(Rx, Set) \ + SET_PCI8(PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Set) +#define RESET_PCI8_PCIEBRS(Rx, Rst) \ + RESET_PCI8(PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Rst) +#define RW_PCI8_PCIEBRS(Rx, Set, Rst) \ + RW_PCI8(PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Set, Rst) +#define READ_PCI16_PCIEBRS(Rx) \ + READ_PCI16(PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx) +#define WRITE_PCI16_PCIEBRS(Rx, Val) \ + WRITE_PCI16(PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Val) +#define SET_PCI16_PCIEBRS(Rx, Set) \ + SET_PCI16(PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Set) +#define RESET_PCI16_PCIEBRS(Rx, Rst) \ + RESET_PCI16(PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Rst) +#define RW_PCI16_PCIEBRS(Rx, Set, Rst) \ + RW_PCI16(PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Set, Rst) +#define READ_PCI32_PCIEBRS(Rx) \ + READ_PCI32(PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx) +#define WRITE_PCI32_PCIEBRS(Rx, Val) \ + WRITE_PCI32(PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Val) +#define SET_PCI32_PCIEBRS(Rx, Set) \ + SET_PCI32(PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Set) +#define RESET_PCI32_PCIEBRS(Rx, Rst) \ + RESET_PCI32(PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Rst) +#define RW_PCI32_PCIEBRS(Rx, Set, Rst) \ + RW_PCI32(PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Set, Rst) + +//--------------------------------------------------------------------------- + +#define READ_PCI8_PCIBR(Rx) \ + READ_PCI8(PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx) +#define WRITE_PCI8_PCIBR(Rx, Val) \ + WRITE_PCI8(PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Val) +#define SET_PCI8_PCIBR(Rx, Set) \ + SET_PCI8(PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Set) +#define RESET_PCI8_PCIBR(Rx, Rst) \ + RESET_PCI8(PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Rst) +#define RW_PCI8_PCIBR(Rx, Set, Rst) \ + RW_PCI8(PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Set, Rst) +#define READ_PCI16_PCIBR(Rx) \ + READ_PCI16(PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx) +#define WRITE_PCI16_PCIBR(Rx, Val) \ + WRITE_PCI16(PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Val) +#define SET_PCI16_PCIBR(Rx, Set) \ + SET_PCI16(PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Set) +#define RESET_PCI16_PCIBR(Rx, Rst) \ + RESET_PCI16(PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Rst) +#define RW_PCI16_PCIBR(Rx, Set, Rst) \ + RW_PCI16(PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Set, Rst) +#define READ_PCI32_PCIBR(Rx) \ + READ_PCI32(PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx) +#define WRITE_PCI32_PCIBR(Rx, Val) \ + WRITE_PCI32(PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Val) +#define SET_PCI32_PCIBR(Rx, Set) \ + SET_PCI32(PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Set) +#define RESET_PCI32_PCIBR(Rx, Rst) \ + RESET_PCI32(PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Rst) +#define RW_PCI32_PCIBR(Rx, Set, Rst) \ + RW_PCI32(PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Set, Rst) + +//--------------------------------------------------------------------------- + +#define READ_PCI8_EHCI(Rx) READ_PCI8(EHCI_BUS, EHCI_DEV, EHCI_FUN, Rx) +#define WRITE_PCI8_EHCI(Rx, Vx) WRITE_PCI8(EHCI_BUS, EHCI_DEV, EHCI_FUN, Rx, Vx) +#define SET_PCI8_EHCI(Rx, Set) SET_PCI8(EHCI_BUS, EHCI_DEV, EHCI_FUN, Rx, Set) +#define RESET_PCI8_EHCI(Rx, Rt) RESET_PCI8(EHCI_BUS, EHCI_DEV, EHCI_FUN, Rx, Rt) +#define RW_PCI8_EHCI(Rx,St,Rt) RW_PCI8(EHCI_BUS, EHCI_DEV, EHCI_FUN, Rx, St, Rt) +#define READ_PCI16_EHCI(Rx) READ_PCI16(EHCI_BUS, EHCI_DEV, EHCI_FUN, Rx) +#define WRITE_PCI16_EHCI(Rx, Vx) WRITE_PCI16(EHCI_BUS, EHCI_DEV, EHCI_FUN, Rx, Vx) +#define SET_PCI16_EHCI(Rx, Set) SET_PCI16(EHCI_BUS, EHCI_DEV, EHCI_FUN, Rx, Set) +#define RESET_PCI16_EHCI(Rx, Rt) RESET_PCI16(EHCI_BUS, EHCI_DEV, EHCI_FUN, Rx, Rt) +#define RW_PCI16_EHCI(Rx,St,Rt) RW_PCI16(EHCI_BUS, EHCI_DEV, EHCI_FUN, Rx, St,Rt) +#define READ_PCI32_EHCI(Rx) READ_PCI32(EHCI_BUS, EHCI_DEV, EHCI_FUN, Rx) +#define WRITE_PCI32_EHCI(Rx, Vx) WRITE_PCI32(EHCI_BUS, EHCI_DEV, EHCI_FUN, Rx, Vx) +#define SET_PCI32_EHCI(Rx, Set) SET_PCI32(EHCI_BUS, EHCI_DEV, EHCI_FUN, Rx, Set) +#define RESET_PCI32_EHCI(Rx, Rt) RESET_PCI32(EHCI_BUS, EHCI_DEV, EHCI_FUN, Rx, Rt) +#define RW_PCI32_EHCI(Rx,St,Rt) RW_PCI32(EHCI_BUS, EHCI_DEV, EHCI_FUN, Rx, St,Rt) + +//--------------------------------------------------------------------------- + +#define READ_PCI8_EHCI2(Rx) \ + READ_PCI8(EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx) +#define WRITE_PCI8_EHCI2(Rx, Val) \ + WRITE_PCI8(EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Val) +#define SET_PCI8_EHCI2(Rx, Set) \ + SET_PCI8(EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Set) +#define RESET_PCI8_EHCI2(Rx, Rst) \ + RESET_PCI8(EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Rst) +#define RW_PCI8_EHCI2(Rx, Set, Rst) \ + RW_PCI8(EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Set, Rst) +#define READ_PCI16_EHCI2(Rx) \ + READ_PCI16(EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx) +#define WRITE_PCI16_EHCI2(Rx, Val) \ + WRITE_PCI16(EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Val) +#define SET_PCI16_EHCI2(Rx, Set) \ + SET_PCI16(EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Set) +#define RESET_PCI16_EHCI2(Rx, Rst) \ + RESET_PCI16(EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Rst) +#define RW_PCI16_EHCI2(Rx, Set, Rst) \ + RW_PCI16(EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Set, Rst) +#define READ_PCI32_EHCI2(Rx) \ + READ_PCI32(EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx) +#define WRITE_PCI32_EHCI2(Rx, Val) \ + WRITE_PCI32(EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Val) +#define SET_PCI32_EHCI2(Rx, Set) \ + SET_PCI32(EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Set) +#define RESET_PCI32_EHCI2(Rx, Rst) \ + RESET_PCI32(EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Rst) +#define RW_PCI32_EHCI2(Rx, Set, Rst) \ + RW_PCI32(EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Set, Rst) + +//--------------------------------------------------------------------------- + +#define READ_PCI8_LAN(Rx) READ_PCI8(LAN_BUS, LAN_DEV, LAN_FUN, Rx) +#define WRITE_PCI8_LAN(Rx, Vx) WRITE_PCI8(LAN_BUS, LAN_DEV, LAN_FUN, Rx, Vx) +#define SET_PCI8_LAN(Rx, Set) SET_PCI8(LAN_BUS, LAN_DEV, LAN_FUN, Rx, Set) +#define RESET_PCI8_LAN(Rx, Rt) RESET_PCI8(LAN_BUS, LAN_DEV, LAN_FUN, Rx, Rt) +#define RW_PCI8_LAN(Rx,St,Rt) RW_PCI8(LAN_BUS, LAN_DEV, LAN_FUN, Rx, St, Rt) +#define READ_PCI16_LAN(Rx) READ_PCI16(LAN_BUS, LAN_DEV, LAN_FUN, Rx) +#define WRITE_PCI16_LAN(Rx, Vx) WRITE_PCI16(LAN_BUS, LAN_DEV, LAN_FUN, Rx, Vx) +#define SET_PCI16_LAN(Rx, Set) SET_PCI16(LAN_BUS, LAN_DEV, LAN_FUN, Rx, Set) +#define RESET_PCI16_LAN(Rx, Rt) RESET_PCI16(LAN_BUS, LAN_DEV, LAN_FUN, Rx, Rt) +#define RW_PCI16_LAN(Rx,St,Rt) RW_PCI16(LAN_BUS, LAN_DEV, LAN_FUN, Rx, St,Rt) +#define READ_PCI32_LAN(Rx) READ_PCI32(LAN_BUS, LAN_DEV, LAN_FUN, Rx) +#define WRITE_PCI32_LAN(Rx, Vx) WRITE_PCI32(LAN_BUS, LAN_DEV, LAN_FUN, Rx, Vx) +#define SET_PCI32_LAN(Rx, Set) SET_PCI32(LAN_BUS, LAN_DEV, LAN_FUN, Rx, Set) +#define RESET_PCI32_LAN(Rx, Rt) RESET_PCI32(LAN_BUS, LAN_DEV, LAN_FUN, Rx, Rt) +#define RW_PCI32_LAN(Rx,St,Rt) RW_PCI32(LAN_BUS, LAN_DEV, LAN_FUN, Rx, St,Rt) + +//--------------------------------------------------------------------------- + +#define READ_PCI8_HDA(Rx) READ_PCI8(HDA_BUS, HDA_DEV, HDA_FUN, Rx) +#define WRITE_PCI8_HDA(Rx, Vx) WRITE_PCI8(HDA_BUS, HDA_DEV, HDA_FUN, Rx, Vx) +#define SET_PCI8_HDA(Rx, Set) SET_PCI8(HDA_BUS, HDA_DEV, HDA_FUN, Rx, Set) +#define RESET_PCI8_HDA(Rx, Rt) RESET_PCI8(HDA_BUS, HDA_DEV, HDA_FUN, Rx, Rt) +#define RW_PCI8_HDA(Rx,St,Rt) RW_PCI8(HDA_BUS, HDA_DEV, HDA_FUN, Rx, St, Rt) +#define READ_PCI16_HDA(Rx) READ_PCI16(HDA_BUS, HDA_DEV, HDA_FUN, Rx) +#define WRITE_PCI16_HDA(Rx, Vx) WRITE_PCI16(HDA_BUS, HDA_DEV, HDA_FUN, Rx, Vx) +#define SET_PCI16_HDA(Rx, Set) SET_PCI16(HDA_BUS, HDA_DEV, HDA_FUN, Rx, Set) +#define RESET_PCI16_HDA(Rx, Rt) RESET_PCI16(HDA_BUS, HDA_DEV, HDA_FUN, Rx, Rt) +#define RW_PCI16_HDA(Rx,St,Rt) RW_PCI16(HDA_BUS, HDA_DEV, HDA_FUN, Rx, St,Rt) +#define READ_PCI32_HDA(Rx) READ_PCI32(HDA_BUS, HDA_DEV, HDA_FUN, Rx) +#define WRITE_PCI32_HDA(Rx, Vx) WRITE_PCI32(HDA_BUS, HDA_DEV, HDA_FUN, Rx, Vx) +#define SET_PCI32_HDA(Rx, Set) SET_PCI32(HDA_BUS, HDA_DEV, HDA_FUN, Rx, Set) +#define RESET_PCI32_HDA(Rx, Rt) RESET_PCI32(HDA_BUS, HDA_DEV, HDA_FUN, Rx, Rt) +#define RW_PCI32_HDA(Rx,St,Rt) RW_PCI32(HDA_BUS, HDA_DEV, HDA_FUN, Rx, St,Rt) + +//--------------------------------------------------------------------------- + +#define READ_PCI8_SMBUS(Rx) \ + READ_PCI8(SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx) +#define WRITE_PCI8_SMBUS(Rx, Val) \ + WRITE_PCI8(SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Val) +#define SET_PCI8_SMBUS(Rx, Set) \ + SET_PCI8(SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Set) +#define RESET_PCI8_SMBUS(Rx, Rst) \ + RESET_PCI8(SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Rst) +#define RW_PCI8_SMBUS(Rx, Set, Rst) \ + RW_PCI8(SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Set, Rst) +#define READ_PCI16_SMBUS(Rx) \ + READ_PCI16(SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx) +#define WRITE_PCI16_SMBUS(Rx, Val) \ + WRITE_PCI16(SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Val) +#define SET_PCI16_SMBUS(Rx, Set) \ + SET_PCI16(SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Set) +#define RESET_PCI16_SMBUS(Rx, Rst) \ + RESET_PCI16(SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Rst) +#define RW_PCI16_SMBUS(Rx, Set, Rst) \ + RW_PCI16(SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Set, Rst) +#define READ_PCI32_SMBUS(Rx) \ + READ_PCI32(SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx) +#define WRITE_PCI32_SMBUS(Rx, Val) \ + WRITE_PCI32(SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Val) +#define SET_PCI32_SMBUS(Rx, Set) \ + SET_PCI32(SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Set) +#define RESET_PCI32_SMBUS(Rx, Rst) \ + RESET_PCI32(SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Rst) +#define RW_PCI32_SMBUS(Rx, Set, Rst) \ + RW_PCI32(SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Set, Rst) + +//--------------------------------------------------------------------------- + +#define READ_PCI8_HECI(Rx) \ + READ_PCI8(HECI_BUS, HECI_DEV, HECI_FUN, Rx) +#define WRITE_PCI8_HECI(Rx, Val) \ + WRITE_PCI8(HECI_BUS, HECI_DEV, HECI_FUN, Rx, Val) +#define SET_PCI8_HECI(Rx, Set) \ + SET_PCI8(HECI_BUS, HECI_DEV, HECI_FUN, Rx, Set) +#define RESET_PCI8_HECI(Rx, Rst) \ + RESET_PCI8(HECI_BUS, HECI_DEV, HECI_FUN, Rx, Rst) +#define RW_PCI8_HECI(Rx, Set, Rst) \ + RW_PCI8(HECI_BUS, HECI_DEV, HECI_FUN, Rx, Set, Rst) +#define READ_PCI16_HECI(Rx) \ + READ_PCI16(HECI_BUS, HECI_DEV, HECI_FUN, Rx) +#define WRITE_PCI16_HECI(Rx, Val) \ + WRITE_PCI16(HECI_BUS, HECI_DEV, HECI_FUN, Rx, Val) +#define SET_PCI16_HECI(Rx, Set) \ + SET_PCI16(HECI_BUS, HECI_DEV, HECI_FUN, Rx, Set) +#define RESET_PCI16_HECI(Rx, Rst) \ + RESET_PCI16(HECI_BUS, HECI_DEV, HECI_FUN, Rx, Rst) +#define RW_PCI16_HECI(Rx, Set, Rst) \ + RW_PCI16(HECI_BUS, HECI_DEV, HECI_FUN, Rx, Set, Rst) +#define READ_PCI32_HECI(Rx) \ + READ_PCI32(HECI_BUS, HECI_DEV, HECI_FUN, Rx) +#define WRITE_PCI32_HECI(Rx, Val) \ + WRITE_PCI32(HECI_BUS, HECI_DEV, HECI_FUN, Rx, Val) +#define SET_PCI32_HECI(Rx, Set) \ + SET_PCI32(HECI_BUS, HECI_DEV, HECI_FUN, Rx, Set) +#define RESET_PCI32_HECI(Rx, Rst) \ + RESET_PCI32(HECI_BUS, HECI_DEV, HECI_FUN, Rx, Rst) +#define RW_PCI32_HECI(Rx, Set, Rst) \ + RW_PCI32(HECI_BUS, HECI_DEV, HECI_FUN, Rx, Set, Rst) + +//--------------------------------------------------------------------------- + +#define READ_PCI8_HECI2(Rx) \ + READ_PCI8(HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx) +#define WRITE_PCI8_HECI2(Rx, Val) \ + WRITE_PCI8(HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Val) +#define SET_PCI8_HECI2(Rx, Set) \ + SET_PCI8(HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Set) +#define RESET_PCI8_HECI2(Rx, Rst) \ + RESET_PCI8(HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Rst) +#define RW_PCI8_HECI2(Rx, Set, Rst) \ + RW_PCI8(HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Set, Rst) +#define READ_PCI16_HECI2(Rx) \ + READ_PCI16(HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx) +#define WRITE_PCI16_HECI2(Rx, Val) \ + WRITE_PCI16(HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Val) +#define SET_PCI16_HECI2(Rx, Set) \ + SET_PCI16(HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Set) +#define RESET_PCI16_HECI2(Rx, Rst) \ + RESET_PCI16(HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Rst) +#define RW_PCI16_HECI2(Rx, Set, Rst) \ + RW_PCI16(HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Set, Rst) +#define READ_PCI32_HECI2(Rx) \ + READ_PCI32(HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx) +#define WRITE_PCI32_HECI2(Rx, Val) \ + WRITE_PCI32(HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Val) +#define SET_PCI32_HECI2(Rx, Set) \ + SET_PCI32(HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Set) +#define RESET_PCI32_HECI2(Rx, Rst) \ + RESET_PCI32(HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Rst) +#define RW_PCI32_HECI2(Rx, Set, Rst) \ + RW_PCI32(HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Set, Rst) + +//--------------------------------------------------------------------------- + +#define WRITE_PCI8_SB_S3(mBoot, Rx, Val) \ + WRITE_PCI8_S3(mBoot, SB_BUS, SB_DEV, SB_FUN, Rx, Val) +#define SET_PCI8_SB_S3(mBoot, Rx, Set) \ + SET_PCI8_S3(mBoot, SB_BUS, SB_DEV, SB_FUN, Rx, Set) +#define RESET_PCI8_SB_S3(mBoot, Rx, Reset) \ + RESET_PCI8_S3(mBoot, SB_BUS, SB_DEV, SB_FUN, Rx, Reset) +#define RW_PCI8_SB_S3(mBoot, Rx, Set, Rst) \ + RW_PCI8_S3(mBoot, SB_BUS, SB_DEV, SB_FUN, Rx, Set, Rst) +#define WRITE_PCI16_SB_S3(mBoot, Rx, Val) \ + WRITE_PCI16_S3(mBoot, SB_BUS, SB_DEV, SB_FUN, Rx, Val) +#define SET_PCI16_SB_S3(mBoot, Rx, Set) \ + SET_PCI16_S3(mBoot, SB_BUS, SB_DEV, SB_FUN, Rx, Set) +#define RESET_PCI16_SB_S3(mBoot, Rx, Reset) \ + RESET_PCI16_S3(mBoot, SB_BUS, SB_DEV, SB_FUN, Rx, Reset) +#define RW_PCI16_SB_S3(mBoot, Rx, Set, Rst) \ + RW_PCI16_S3(mBoot, SB_BUS, SB_DEV, SB_FUN, Rx, Set, Rst) +#define WRITE_PCI32_SB_S3(mBoot, Rx, Val) \ + WRITE_PCI32_S3(mBoot, SB_BUS, SB_DEV, SB_FUN, Rx, Val) +#define SET_PCI32_SB_S3(mBoot, Rx, Set) \ + SET_PCI32_S3(mBoot, SB_BUS, SB_DEV, SB_FUN, Rx, Set) +#define RESET_PCI32_SB_S3(mBoot, Rx, Reset) \ + RESET_PCI32_S3(mBoot, SB_BUS, SB_DEV, SB_FUN, Rx, Reset) +#define RW_PCI32_SB_S3(mBoot, Rx, Set, Rst) \ + RW_PCI32_S3(mBoot, SB_BUS, SB_DEV, SB_FUN, Rx, Set, Rst) + +//--------------------------------------------------------------------------- + +#define WRITE_PCI8_SATA_S3(mBoot, Rx, Val) \ + WRITE_PCI8_S3(mBoot, SATA_BUS, SATA_DEV, SATA_FUN, Rx, Val) +#define SET_PCI8_SATA_S3(mBoot, Rx, Set) \ + SET_PCI8_S3(mBoot, SATA_BUS, SATA_DEV, SATA_FUN, Rx, Set) +#define RESET_PCI8_SATA_S3(mBoot, Rx, Rst) \ + RESET_PCI8_S3(mBoot, SATA_BUS, SATA_DEV, SATA_FUN, Rx, Rst) +#define RW_PCI8_SATA_S3(mBoot, Rx, Set, Rst) \ + RW_PCI8_S3(mBoot, SATA_BUS, SATA_DEV, SATA_FUN, Rx, Set, Rst) +#define WRITE_PCI16_SATA_S3(mBoot, Rx, Val) \ + WRITE_PCI16_S3(mBoot, SATA_BUS, SATA_DEV, SATA_FUN, Rx, Val) +#define SET_PCI16_SATA_S3(mBoot, Rx, Set) \ + SET_PCI16_S3(mBoot, SATA_BUS, SATA_DEV, SATA_FUN, Rx, Set) +#define RESET_PCI16_SATA_S3(mBoot, Rx, Rst) \ + RESET_PCI16_S3(mBoot, SATA_BUS, SATA_DEV, SATA_FUN, Rx, Rst) +#define RW_PCI16_SATA_S3(mBoot, Rx, Set, Rst) \ + RW_PCI16_S3(mBoot, SATA_BUS, SATA_DEV, SATA_FUN, Rx, Set, Rst) +#define WRITE_PCI32_SATA_S3(mBoot, Rx, Val) \ + WRITE_PCI32_S3(mBoot, SATA_BUS, SATA_DEV, SATA_FUN, Rx, Val) +#define SET_PCI32_SATA_S3(mBoot, Rx, Set) \ + SET_PCI32_S3(mBoot, SATA_BUS, SATA_DEV, SATA_FUN, Rx, Set) +#define RESET_PCI32_SATA_S3(mBoot, Rx, Rst) \ + RESET_PCI32_S3(mBoot, SATA_BUS, SATA_DEV, SATA_FUN, Rx, Rst) +#define RW_PCI32_SATA_S3(mBoot, Rx, Set, Rst) \ + RW_PCI32_S3(mBoot, SATA_BUS, SATA_DEV, SATA_FUN, Rx, Set, Rst) + +//--------------------------------------------------------------------------- + +#define WRITE_PCI8_SATA2_S3(mBoot, Rx, Val) \ + WRITE_PCI8_S3(mBoot, SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Val) +#define SET_PCI8_SATA2_S3(mBoot, Rx, Set) \ + SET_PCI8_S3(mBoot, SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Set) +#define RESET_PCI8_SATA2_S3(mBoot, Rx, Rst) \ + RESET_PCI8_S3(mBoot, SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Rst) +#define RW_PCI8_SATA2_S3(mBoot, Rx, Set, Rst) \ + RW_PCI8_S3(mBoot, SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Set, Rst) +#define WRITE_PCI16_SATA2_S3(mBoot, Rx, Val) \ + WRITE_PCI16_S3(mBoot, SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Val) +#define SET_PCI16_SATA2_S3(mBoot, Rx, Set) \ + SET_PCI16_S3(mBoot, SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Set) +#define RESET_PCI16_SATA2_S3(mBoot, Rx, Rst) \ + RESET_PCI16_S3(mBoot, SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Rst) +#define RW_PCI16_SATA2_S3(mBoot, Rx, Set, Rst) \ + RW_PCI16_S3(mBoot, SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Set, Rst) +#define WRITE_PCI32_SATA2_S3(mBoot, Rx, Val) \ + WRITE_PCI32_S3(mBoot, SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Val) +#define SET_PCI32_SATA2_S3(mBoot, Rx, Set) \ + SET_PCI32_S3(mBoot, SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Set) +#define RESET_PCI32_SATA2_S3(mBoot, Rx, Rst) \ + RESET_PCI32_S3(mBoot, SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Rst) +#define RW_PCI32_SATA2_S3(mBoot, Rx, Set, Rst) \ + RW_PCI32_S3(mBoot, SATA2_BUS, SATA2_DEV, SATA2_FUN, Rx, Set, Rst) + +//--------------------------------------------------------------------------- + +#define WRITE_PCI8_PCIEBRS_S3(mBoot, Rx, Val) \ + WRITE_PCI8_S3(mBoot, PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Val) +#define SET_PCI8_PCIEBRS_S3(mBoot, Rx, Set) \ + SET_PCI8_S3(mBoot, PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Set) +#define RESET_PCI8_PCIEBRS_S3(mBoot, Rx, Rst) \ + RESET_PCI8_S3(mBoot, PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Rst) +#define RW_PCI8_PCIEBRS_S3(mBoot, Rx, St, Rt) \ + RW_PCI8_S3(mBoot, PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, St, Rt) +#define WRITE_PCI16_PCIEBRS_S3(mBoot, Rx, Val) \ + WRITE_PCI16_S3(mBoot, PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Val) +#define SET_PCI16_PCIEBRS_S3(mBoot, Rx, Set) \ + SET_PCI16_S3(mBoot, PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Set) +#define RESET_PCI16_PCIEBRS_S3(mBoot, Rx, Rst) \ + RESET_PCI16_S3(mBoot, PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Rst) +#define RW_PCI16_PCIEBRS_S3(mBoot, Rx, St, Rt) \ + RW_PCI16_S3(mBoot, PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, St, Rt) +#define WRITE_PCI32_PCIEBRS_S3(mBoot, Rx, Val) \ + WRITE_PCI32_S3(mBoot, PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Val) +#define SET_PCI32_PCIEBRS_S3(mBoot, Rx, Set) \ + SET_PCI32_S3(mBoot, PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Set) +#define RESET_PCI32_PCIEBRS_S3(mBoot, Rx, Rst) \ + RESET_PCI32_S3(mBoot, PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, Rst) +#define RW_PCI32_PCIEBRS_S3(mBoot, Rx, St, Rt) \ + RW_PCI32_S3(mBoot, PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, Rx, St, Rt) + +//--------------------------------------------------------------------------- + +#define WRITE_PCI8_PCIBR_S3(mBoot, Rx, Val) \ + WRITE_PCI8_S3(mBoot, PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Val) +#define SET_PCI8_PCIBR_S3(mBoot, Rx, Set) \ + SET_PCI8_S3(mBoot, PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Set) +#define RESET_PCI8_PCIBR_S3(mBoot, Rx, Rst) \ + RESET_PCI8_S3(mBoot, PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Rst) +#define RW_PCI8_PCIBR_S3(mBoot, Rx, St, Rt) \ + RW_PCI8_S3(mBoot, PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, St, Rt) +#define WRITE_PCI16_PCIBR_S3(mBoot, Rx, Val) \ + WRITE_PCI16_S3(mBoot, PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Val) +#define SET_PCI16_PCIBR_S3(mBoot, Rx, Set) \ + SET_PCI16_S3(mBoot, PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Set) +#define RESET_PCI16_PCIBR_S3(mBoot, Rx, Rst) \ + RESET_PCI16_S3(mBoot, PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Rst) +#define RW_PCI16_PCIBR_S3(mBoot, Rx, St, Rt) \ + RW_PCI16_S3(mBoot, PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, St, Rt) +#define WRITE_PCI32_PCIBR_S3(mBoot, Rx, Val) \ + WRITE_PCI32_S3(mBoot, PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Val) +#define SET_PCI32_PCIBR_S3(mBoot, Rx, Set) \ + SET_PCI32_S3(mBoot, PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Set) +#define RESET_PCI32_PCIBR_S3(mBoot, Rx, Rst) \ + RESET_PCI32_S3(mBoot, PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, Rst) +#define RW_PCI32_PCIBR_S3(mBoot, Rx, St, Rt) \ + RW_PCI32_S3(mBoot, PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, Rx, St, Rt) + +//--------------------------------------------------------------------------- + +#define WRITE_PCI8_EHCI_S3(mBoot, Rx, Val) \ + WRITE_PCI8_S3(mBoot, EHCI_BUS, EHCI_DEV, EHCI_DEV, Rx, Val) +#define SET_PCI8_EHCI_S3(mBoot, Rx, Set) \ + SET_PCI8_S3(mBoot, EHCI_BUS, EHCI_DEV, EHCI_DEV, Rx, Set) +#define RESET_PCI8_EHCI_S3(mBoot, Rx, Rst) \ + RESET_PCI8_S3(mBoot, EHCI_BUS, EHCI_DEV, EHCI_DEV, Rx, Rst) +#define RW_PCI8_EHCI_S3(mBoot, Rx, Set, Rst) \ + RW_PCI8_S3(mBoot, EHCI_BUS, EHCI_DEV, EHCI_DEV, Rx, Set, Rst) +#define WRITE_PCI16_EHCI_S3(mBoot, Rx, Val) \ + WRITE_PCI16_S3(mBoot, EHCI_BUS, EHCI_DEV, EHCI_DEV, Rx, Val) +#define SET_PCI16_EHCI_S3(mBoot, Rx, Set) \ + SET_PCI16_S3(mBoot, EHCI_BUS, EHCI_DEV, EHCI_DEV, Rx, Set) +#define RESET_PCI16_EHCI_S3(mBoot, Rx, Rst) \ + RESET_PCI16_S3(mBoot, EHCI_BUS, EHCI_DEV, EHCI_DEV, Rx, Rst) +#define RW_PCI16_EHCI_S3(mBoot, Rx, Set, Rst) \ + RW_PCI16_S3(mBoot, EHCI_BUS, EHCI_DEV, EHCI_DEV, Rx, Set, Rst) +#define WRITE_PCI32_EHCI_S3(mBoot, Rx, Val) \ + WRITE_PCI32_S3(mBoot, EHCI_BUS, EHCI_DEV, EHCI_DEV, Rx, Val) +#define SET_PCI32_EHCI_S3(mBoot, Rx, Set) \ + SET_PCI32_S3(mBoot, EHCI_BUS, EHCI_DEV, EHCI_DEV, Rx, Set) +#define RESET_PCI32_EHCI_S3(mBoot, Rx, Rst) \ + RESET_PCI32_S3(mBoot, EHCI_BUS, EHCI_DEV, EHCI_DEV, Rx, Rst) +#define RW_PCI32_EHCI_S3(mBoot, Rx, Set, Rst) \ + RW_PCI32_S3(mBoot, EHCI_BUS, EHCI_DEV, EHCI_DEV, Rx, Set, Rst) + +//--------------------------------------------------------------------------- + +#define WRITE_PCI8_EHCI2_S3(mBoot, Rx, Val) \ + WRITE_PCI8_S3(mBoot, EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Val) +#define SET_PCI8_EHCI2_S3(mBoot, Rx, Set) \ + SET_PCI8_S3(mBoot, EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Set) +#define RESET_PCI8_EHCI2_S3(mBoot, Rx, Rst) \ + RESET_PCI8_S3(mBoot, EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Rst) +#define RW_PCI8_EHCI2_S3(mBoot, Rx, Set, Rst) \ + RW_PCI8_S3(mBoot, EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Set, Rst) +#define WRITE_PCI16_EHCI2_S3(mBoot, Rx, Val) \ + WRITE_PCI16_S3(mBoot, EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Val) +#define SET_PCI16_EHCI2_S3(mBoot, Rx, Set) \ + SET_PCI16_S3(mBoot, EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Set) +#define RESET_PCI16_EHCI2_S3(mBoot, Rx, Rst) \ + RESET_PCI16_S3(mBoot, EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Rst) +#define RW_PCI16_EHCI2_S3(mBoot, Rx, Set, Rst) \ + RW_PCI16_S3(mBoot, EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Set, Rst) +#define WRITE_PCI32_EHCI2_S3(mBoot, Rx, Val) \ + WRITE_PCI32_S3(mBoot, EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Val) +#define SET_PCI32_EHCI2_S3(mBoot, Rx, Set) \ + SET_PCI32_S3(mBoot, EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Set) +#define RESET_PCI32_EHCI2_S3(mBoot, Rx, Rst) \ + RESET_PCI32_S3(mBoot, EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Rst) +#define RW_PCI32_EHCI2_S3(mBoot, Rx, Set, Rst) \ + RW_PCI32_S3(mBoot, EHCI2_BUS, EHCI2_DEV, EHCI2_FUN, Rx, Set, Rst) + +//--------------------------------------------------------------------------- + +#define WRITE_PCI8_LAN_S3(mBoot, Rx, Val) \ + WRITE_PCI8_S3(mBoot, LAN_BUS, LAN_DEV, LAN_FUN, Rx, Val) +#define SET_PCI8_LAN_S3(mBoot, Rx, Set) \ + SET_PCI8_S3(mBoot, LAN_BUS, LAN_DEV, LAN_FUN, Rx, Set) +#define RESET_PCI8_LAN_S3(mBoot, Rx, Rst) \ + RESET_PCI8_S3(mBoot, LAN_BUS, LAN_DEV, LAN_FUN, Rx, Rst) +#define RW_PCI8_LAN_S3(mBoot, Rx, Set, Rst) \ + RW_PCI8_S3(mBoot, LAN_BUS, LAN_DEV, LAN_FUN, Rx, Set, Rst) +#define WRITE_PCI16_LAN_S3(mBoot, Rx, Val) \ + WRITE_PCI16_S3(mBoot, LAN_BUS, LAN_DEV, LAN_FUN, Rx, Val) +#define SET_PCI16_LAN_S3(mBoot, Rx, Set) \ + SET_PCI16_S3(mBoot, LAN_BUS, LAN_DEV, LAN_FUN, Rx, Set) +#define RESET_PCI16_LAN_S3(mBoot, Rx, Rst) \ + RESET_PCI16_S3(mBoot, LAN_BUS, LAN_DEV, LAN_FUN, Rx, Rst) +#define RW_PCI16_LAN_S3(mBoot, Rx, Set, Rst) \ + RW_PCI16_S3(mBoot, LAN_BUS, LAN_DEV, LAN_FUN, Rx, Set, Rst) +#define WRITE_PCI32_LAN_S3(mBoot, Rx, Val) \ + WRITE_PCI32_S3(mBoot, LAN_BUS, LAN_DEV, LAN_FUN, Rx, Val) +#define SET_PCI32_LAN_S3(mBoot, Rx, Set) \ + SET_PCI32_S3(mBoot, LAN_BUS, LAN_DEV, LAN_FUN, Rx, Set) +#define RESET_PCI32_LAN_S3(mBoot, Rx, Rst) \ + RESET_PCI32_S3(mBoot, LAN_BUS, LAN_DEV, LAN_FUN, Rx, Rst) +#define RW_PCI32_LAN_S3(mBoot, Rx, Set, Rst) \ + RW_PCI32_S3(mBoot, LAN_BUS, LAN_DEV, LAN_FUN, Rx, Set, Rst) + +//--------------------------------------------------------------------------- + +#define WRITE_PCI8_HDA_S3(mBoot, Rx, Val) \ + WRITE_PCI8_S3(mBoot, HDA_BUS, HDA_DEV, HDA_FUN, Rx, Val) +#define SET_PCI8_HDA_S3(mBoot, Rx, Set) \ + SET_PCI8_S3(mBoot, HDA_BUS, HDA_DEV, HDA_FUN, Rx, Set) +#define RESET_PCI8_HDA_S3(mBoot, Rx, Rst) \ + RESET_PCI8_S3(mBoot, HDA_BUS, HDA_DEV, HDA_FUN, Rx, Rst) +#define RW_PCI8_HDA_S3(mBoot, Rx, Set, Rst) \ + RW_PCI8_S3(mBoot, HDA_BUS, HDA_DEV, HDA_FUN, Rx, Set, Rst) +#define WRITE_PCI16_HDA_S3(mBoot, Rx, Val) \ + WRITE_PCI16_S3(mBoot, HDA_BUS, HDA_DEV, HDA_FUN, Rx, Val) +#define SET_PCI16_HDA_S3(mBoot, Rx, Set) \ + SET_PCI16_S3(mBoot, HDA_BUS, HDA_DEV, HDA_FUN, Rx, Set) +#define RESET_PCI16_HDA_S3(mBoot, Rx, Rst) \ + RESET_PCI16_S3(mBoot, HDA_BUS, HDA_DEV, HDA_FUN, Rx, Rst) +#define RW_PCI16_HDA_S3(mBoot, Rx, Set, Rst) \ + RW_PCI16_S3(mBoot, HDA_BUS, HDA_DEV, HDA_FUN, Rx, Set, Rst) +#define WRITE_PCI32_HDA_S3(mBoot, Rx, Val) \ + WRITE_PCI32_S3(mBoot, HDA_BUS, HDA_DEV, HDA_FUN, Rx, Val) +#define SET_PCI32_HDA_S3(mBoot, Rx, Set) \ + SET_PCI32_S3(mBoot, HDA_BUS, HDA_DEV, HDA_FUN, Rx, Set) +#define RESET_PCI32_HDA_S3(mBoot, Rx, Rst) \ + RESET_PCI32_S3(mBoot, HDA_BUS, HDA_DEV, HDA_FUN, Rx, Rst) +#define RW_PCI32_HDA_S3(mBoot, Rx, Set, Rst) \ + RW_PCI32_S3(mBoot, HDA_BUS, HDA_DEV, HDA_FUN, Rx, Set, Rst) + +//--------------------------------------------------------------------------- + +#define WRITE_PCI8_SMBUS_S3(mBoot, Rx, Val) \ + WRITE_PCI8_S3(mBoot, SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Val) +#define SET_PCI8_SMBUS_S3(mBoot, Rx, Set) \ + SET_PCI8_S3(mBoot, SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Set) +#define RESET_PCI8_SMBUS_S3(mBoot, Rx, Rst) \ + RESET_PCI8_S3(mBoot, SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Rst) +#define RW_PCI8_SMBUS_S3(mBoot, Rx, St, Rt) \ + RW_PCI8_S3(mBoot, SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, St, Rt) +#define WRITE_PCI16_SMBUS_S3(mBoot, Rx, Val) \ + WRITE_PCI16_S3(mBoot, SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Val) +#define SET_PCI16_SMBUS_S3(mBoot, Rx, Set) \ + SET_PCI16_S3(mBoot, SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Set) +#define RESET_PCI16_SMBUS_S3(mBoot, Rx, Rst) \ + RESET_PCI16_S3(mBoot, SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Rst) +#define RW_PCI16_SMBUS_S3(mBoot, Rx, St, Rt) \ + RW_PCI16_S3(mBoot, SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, St, Rt) +#define WRITE_PCI32_SMBUS_S3(mBoot, Rx, Val) \ + WRITE_PCI32_S3(mBoot, SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Val) +#define SET_PCI32_SMBUS_S3(mBoot, Rx, Set) \ + SET_PCI32_S3(mBoot, SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Set) +#define RESET_PCI32_SMBUS_S3(mBoot, Rx, Rst) \ + RESET_PCI32_S3(mBoot, SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, Rst) +#define RW_PCI32_SMBUS_S3(mBoot, Rx, St, Rt) \ + RW_PCI32_S3(mBoot, SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, Rx, St, Rt) + +//--------------------------------------------------------------------------- + +#define WRITE_PCI8_HECI_S3(mBoot, Rx, Val) \ + WRITE_PCI8_S3(mBoot, HECI_BUS, HECI_DEV, HECI_FUN, Rx, Val) +#define SET_PCI8_HECI_S3(mBoot, Rx, Set) \ + SET_PCI8_S3(mBoot, HECI_BUS, HECI_DEV, HECI_FUN, Rx, Set) +#define RESET_PCI8_HECI_S3(mBoot, Rx, Rst) \ + RESET_PCI8_S3(mBoot, HECI_BUS, HECI_DEV, HECI_FUN, Rx, Rst) +#define RW_PCI8_HECI_S3(mBoot, Rx, Set, Rst) \ + RW_PCI8_S3(mBoot, HECI_BUS, HECI_DEV, HECI_FUN, Rx, Set, Rst) +#define WRITE_PCI16_HECI_S3(mBoot, Rx, Val) \ + WRITE_PCI16_S3(mBoot, HECI_BUS, HECI_DEV, HECI_FUN, Rx, Val) +#define SET_PCI16_HECI_S3(mBoot, Rx, Set) \ + SET_PCI16_S3(mBoot, HECI_BUS, HECI_DEV, HECI_FUN, Rx, Set) +#define RESET_PCI16_HECI_S3(mBoot, Rx, Rst) \ + RESET_PCI16_S3(mBoot, HECI_BUS, HECI_DEV, HECI_FUN, Rx, Rst) +#define RW_PCI16_HECI_S3(mBoot, Rx, Set, Rst) \ + RW_PCI16_S3(mBoot, HECI_BUS, HECI_DEV, HECI_FUN, Rx, Set, Rst) +#define WRITE_PCI32_HECI_S3(mBoot, Rx, Val) \ + WRITE_PCI32_S3(mBoot, HECI_BUS, HECI_DEV, HECI_FUN, Rx, Val) +#define SET_PCI32_HECI_S3(mBoot, Rx, Set) \ + SET_PCI32_S3(mBoot, HECI_BUS, HECI_DEV, HECI_FUN, Rx, Set) +#define RESET_PCI32_HECI_S3(mBoot, Rx, Rst) \ + RESET_PCI32_S3(mBoot, HECI_BUS, HECI_DEV, HECI_FUN, Rx, Rst) +#define RW_PCI32_HECI_S3(mBoot, Rx, Set, Rst) \ + RW_PCI32_S3(mBoot, HECI_BUS, HECI_DEV, HECI_FUN, Rx, Set, Rst) + +//--------------------------------------------------------------------------- + +#define WRITE_PCI8_HECI2_S3(mBoot, Rx, Val) \ + WRITE_PCI8_S3(mBoot, HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Val) +#define SET_PCI8_HECI2_S3(mBoot, Rx, Set) \ + SET_PCI8_S3(mBoot, HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Set) +#define RESET_PCI8_HECI2_S3(mBoot, Rx, Rst) \ + RESET_PCI8_S3(mBoot, HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Rst) +#define RW_PCI8_HECI2_S3(mBoot, Rx, Set, Rst) \ + RW_PCI8_S3(mBoot, HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Set, Rst) +#define WRITE_PCI16_HECI2_S3(mBoot, Rx, Val) \ + WRITE_PCI16_S3(mBoot, HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Val) +#define SET_PCI16_HECI2_S3(mBoot, Rx, Set) \ + SET_PCI16_S3(mBoot, HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Set) +#define RESET_PCI16_HECI2_S3(mBoot, Rx, Rst) \ + RESET_PCI16_S3(mBoot, HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Rst) +#define RW_PCI16_HECI2_S3(mBoot, Rx, Set, Rst) \ + RW_PCI16_S3(mBoot, HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Set, Rst) +#define WRITE_PCI32_HECI2_S3(mBoot, Rx, Val) \ + WRITE_PCI32_S3(mBoot, HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Val) +#define SET_PCI32_HECI2_S3(mBoot, Rx, Set) \ + SET_PCI32_S3(mBoot, HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Set) +#define RESET_PCI32_HECI2_S3(mBoot, Rx, Rst) \ + RESET_PCI32_S3(mBoot, HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Rst) +#define RW_PCI32_HECI2_S3(mBoot, Rx, Set, Rst) \ + RW_PCI32_S3(mBoot, HECI2_BUS, HECI2_DEV, HECI2_FUN, Rx, Set, Rst) + +//--------------------------------------------------------------------------- +// Chipset MMIO Macros, Porting Required. +//--------------------------------------------------------------------------- + +#define READ_MEM8_RCRB(wReg) READ_MEM8(SB_RCRB_BASE_ADDRESS | wReg) +#define WRITE_MEM8_RCRB(wReg, bVal) WRITE_MEM8(SB_RCRB_BASE_ADDRESS | wReg,bVal) +#define SET_MEM8_RCRB(wReg, Set) RW_MEM8(SB_RCRB_BASE_ADDRESS | wReg, Set, 0) +#define RESET_MEM8_RCRB(wReg, Rst) RW_MEM8(SB_RCRB_BASE_ADDRESS | wReg,0,Rst) +#define RW_MEM8_RCRB(wReg,Set,Rst) RW_MEM8(SB_RCRB_BASE_ADDRESS|wReg,Set,Rst) +#define READ_MEM16_RCRB(wReg) READ_MEM16(SB_RCRB_BASE_ADDRESS | wReg) +#define WRITE_MEM16_RCRB(wReg,Val) WRITE_MEM16(SB_RCRB_BASE_ADDRESS|wReg,Val) +#define SET_MEM16_RCRB(wReg, Set) RW_MEM16(SB_RCRB_BASE_ADDRESS|wReg, Set,0) +#define RESET_MEM16_RCRB(wReg, Rst) RW_MEM16(SB_RCRB_BASE_ADDRESS|wReg, 0,Rst) +#define RW_MEM16_RCRB(Reg,Set,Rst) RW_MEM16(SB_RCRB_BASE_ADDRESS|Reg,Set,Rst) +#define READ_MEM32_RCRB(wReg) READ_MEM32(SB_RCRB_BASE_ADDRESS | wReg) +#define WRITE_MEM32_RCRB(wReg,Val) WRITE_MEM32(SB_RCRB_BASE_ADDRESS|wReg,Val) +#define SET_MEM32_RCRB(wReg,Set) RW_MEM32(SB_RCRB_BASE_ADDRESS|wReg, Set,0) +#define RESET_MEM32_RCRB(wReg,Rst) RW_MEM32(SB_RCRB_BASE_ADDRESS|wReg,0,Rst) +#define RW_MEM32_RCRB(Reg,Set,Rst) RW_MEM32(SB_RCRB_BASE_ADDRESS|Reg,Set,Rst) + +//--------------------------------------------------------------------------- +#define WRITE_MEM8_RCRB_S3(mBoot, wReg, bVal) \ + WRITE_MEM8_S3(mBoot, SB_RCRB_BASE_ADDRESS|wReg, bVal) +#define SET_MEM8_RCRB_S3(mBoot, wReg, Set) \ + SET_MEM8_S3(mBoot, SB_RCRB_BASE_ADDRESS|wReg, Set) +#define RESET_MEM8_RCRB_S3(mBoot, wReg, Rst) \ + RESET_MEM8_S3(mBoot, SB_RCRB_BASE_ADDRESS|wReg, Rst) +#define RW_MEM8_RCRB_S3(mBoot, wReg, Set, Rst) \ + RW_MEM8_S3(mBoot, SB_RCRB_BASE_ADDRESS|wReg, Set,Rst) +#define WRITE_MEM16_RCRB_S3(mBoot, wReg, wVal) \ + WRITE_MEM16_S3(mBoot, SB_RCRB_BASE_ADDRESS|wReg,wVal) +#define SET_MEM16_RCRB_S3(mBoot, wReg, Set) \ + SET_MEM16_S3(mBoot, SB_RCRB_BASE_ADDRESS|wReg, Set) +#define RESET_MEM16_RCRB_S3(mBoot, wReg, Rst) \ + RESET_MEM16_S3(mBoot, SB_RCRB_BASE_ADDRESS|wReg, Rst) +#define RW_MEM16_RCRB_S3(mBoot, wReg, Set, Rst) \ + RW_MEM16_S3(mBoot,SB_RCRB_BASE_ADDRESS|wReg, Set,Rst) +#define WRITE_MEM32_RCRB_S3(mBoot, wReg, dVal) \ + WRITE_MEM32_S3(mBoot, SB_RCRB_BASE_ADDRESS|wReg,dVal) +#define SET_MEM32_RCRB_S3(mBoot, wReg, Set) \ + SET_MEM32_S3(mBoot, SB_RCRB_BASE_ADDRESS|wReg, Set) +#define RESET_MEM32_RCRB_S3(mBoot, wReg, Rst) \ + RESET_MEM32_S3(mBoot, SB_RCRB_BASE_ADDRESS|wReg, Rst) +#define RW_MEM32_RCRB_S3(mBoot, wReg, Set, Rst) \ + RW_MEM32_S3(mBoot,SB_RCRB_BASE_ADDRESS|wReg, Set,Rst) + +//--------------------------------------------------------------------------- +// SPI MMIO Macros, Porting Required. +//--------------------------------------------------------------------------- + +#define READ_MEM8_SPI(wReg) READ_MEM8(SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS| wReg) +#define WRITE_MEM8_SPI(wReg, bVal) WRITE_MEM8(SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS | wReg,bVal) +#define SET_MEM8_SPI(wReg, Set) RW_MEM8(SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS | wReg, Set, 0) +#define RESET_MEM8_SPI(wReg, Rst) RW_MEM8(SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS | wReg,0,Rst) +#define RW_MEM8_SPI(wReg,Set,Rst) RW_MEM8(SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS|wReg,Set,Rst) +#define READ_MEM16_SPI(wReg) READ_MEM16(SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS | wReg) +#define WRITE_MEM16_SPI(wReg,Val) WRITE_MEM16(SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS|wReg,Val) +#define SET_MEM16_SPI(wReg, Set) RW_MEM16(SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS|wReg, Set,0) +#define RESET_MEM16_SPI(wReg, Rst) RW_MEM16(SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS|wReg, 0,Rst) +#define RW_MEM16_SPI(Reg,Set,Rst) RW_MEM16(SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS|Reg,Set,Rst) +#define READ_MEM32_SPI(wReg) READ_MEM32(SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS | wReg) +#define WRITE_MEM32_SPI(wReg,Val) WRITE_MEM32(SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS|wReg,Val) +#define SET_MEM32_SPI(wReg,Set) RW_MEM32(SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS|wReg, Set,0) +#define RESET_MEM32_SPI(wReg,Rst) RW_MEM32(SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS|wReg,0,Rst) +#define RW_MEM32_SPI(Reg,Set,Rst) RW_MEM32(SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS|Reg,Set,Rst) + +//--------------------------------------------------------------------------- +// Chipset I/O Macros, Porting Required. +//--------------------------------------------------------------------------- + +#define READ_IO8_PM(bReg) READ_IO8(PM_BASE_ADDRESS+bReg) +#define WRITE_IO8_PM(bReg, bVal) WRITE_IO8(PM_BASE_ADDRESS+bReg, bVal) +#define SET_IO8_PM(bReg, Set) SET_IO8(PM_BASE_ADDRESS+bReg, Set) +#define RESET_IO8_PM(bReg, Reset) RESET_IO8(PM_BASE_ADDRESS+bReg, Reset) +#define RW_IO8_PM(bReg, Set, Rst) RW_IO8(PM_BASE_ADDRESS+bReg, Set, Rst) +#define READ_IO16_PM(bReg) READ_IO16(PM_BASE_ADDRESS+bReg) +#define WRITE_IO16_PM(bReg, wVal) WRITE_IO16(PM_BASE_ADDRESS+bReg, wVal) +#define SET_IO16_PM(bReg, Set) SET_IO16(PM_BASE_ADDRESS+bReg, Set) +#define RESET_IO16_PM(bReg, Reset) RESET_IO16(PM_BASE_ADDRESS+bReg, Reset) +#define RW_IO16_PM(bReg, Set, Rst) RW_IO16(PM_BASE_ADDRESS+bReg, Set, Rst) +#define READ_IO32_PM(bReg) READ_IO32(PM_BASE_ADDRESS+bReg) +#define WRITE_IO32_PM(bReg, dVal) WRITE_IO32(PM_BASE_ADDRESS+bReg, dVal) +#define SET_IO32_PM(bReg, Set) SET_IO32(PM_BASE_ADDRESS+bReg, Set) +#define RESET_IO32_PM(bReg, Reset) RESET_IO32(PM_BASE_ADDRESS+bReg, Reset) +#define RW_IO32_PM(bReg, Set, Rst) RW_IO32(PM_BASE_ADDRESS+bReg, Set, Rst) + +//--------------------------------------------------------------------------- + +#define READ_IO8_TCO(bReg) READ_IO8(TCO_BASE_ADDRESS+bReg) +#define WRITE_IO8_TCO(bReg, bVal) WRITE_IO8(TCO_BASE_ADDRESS+bReg, bVal) +#define SET_IO8_TCO(bReg, Set) SET_IO8(TCO_BASE_ADDRESS+bReg, Set) +#define RESET_IO8_TCO(bReg, Reset) RESET_IO8(TCO_BASE_ADDRESS+bReg, Reset) +#define RW_IO8_TCO(bReg, Set, Rst) RW_IO8(TCO_BASE_ADDRESS+bReg, Set, Rst) +#define READ_IO16_TCO(bReg) READ_IO16(TCO_BASE_ADDRESS+bReg) +#define WRITE_IO16_TCO(bReg, wVal) WRITE_IO16(TCO_BASE_ADDRESS+bReg, wVal) +#define SET_IO16_TCO(bReg, Set) SET_IO16(TCO_BASE_ADDRESS+bReg, Set) +#define RESET_IO16_TCO(bReg, Reset) RESET_IO16(TCO_BASE_ADDRESS+bReg, Reset) +#define RW_IO16_TCO(bReg, Set, Rst) RW_IO16(TCO_BASE_ADDRESS+bReg, Set, Rst) +#define READ_IO32_TCO(bReg) READ_IO32(TCO_BASE_ADDRESS+bReg) +#define WRITE_IO32_TCO(bReg, dVal) WRITE_IO32(TCO_BASE_ADDRESS+bReg, dVal) +#define SET_IO32_TCO(bReg, Set) SET_IO32(TCO_BASE_ADDRESS+bReg, Set) +#define RESET_IO32_TCO(bReg, Reset) RESET_IO32(TCO_BASE_ADDRESS+bReg, Reset) +#define RW_IO32_TCO(bReg, Set, Rst) RW_IO32(TCO_BASE_ADDRESS+bReg, Set, Rst) + +//--------------------------------------------------------------------------- + +#define WRITE_IO8_PM_S3(mBoot, bReg, bVal) \ + WRITE_IO8_S3(mBoot, PM_BASE_ADDRESS+bReg, bVal) +#define RW_IO8_PM_S3(mBoot, bReg, Set, Reset) \ + RW_IO8_S3(mBoot, PM_BASE_ADDRESS+bReg, Set, Reset) +#define SET_IO8_PM_S3(mBoot, bReg, Set) \ + RW_IO8_S3(mBoot, PM_BASE_ADDRESS+bReg, Set, 0) +#define RESET_IO8_PM_S3(mBoot, bReg, Reset) \ + RW_IO8_S3(mBoot, PM_BASE_ADDRESS+bReg, 0, Reset) + +#define WRITE_IO16_PM_S3(mBoot, bReg, bVal) \ + WRITE_IO16_S3(mBoot, PM_BASE_ADDRESS+bReg, bVal) +#define RW_IO16_PM_S3(mBoot, bReg, Set, Rst) \ + RW_IO16_S3(mBoot, PM_BASE_ADDRESS+bReg, Set, Rst) +#define SET_IO16_PM_S3(mBoot, bReg, Set) \ + RW_IO16_S3(mBoot, PM_BASE_ADDRESS+bReg, Set, 0) +#define RESET_IO16_PM_S3(mBoot, bReg, Reset) \ + RW_IO16_S3(mBoot, PM_BASE_ADDRESS+bReg, 0, Reset) + +#define WRITE_IO32_PM_S3(mBoot, bReg, bVal) \ + WRITE_IO32_S3(mBoot, PM_BASE_ADDRESS+bReg, bVal) +#define RW_IO32_PM_S3(mBoot, bReg, Set, Rst) \ + RW_IO32_S3(mBoot, PM_BASE_ADDRESS+bReg, Set, Rst) +#define SET_IO32_PM_S3(mBoot, bReg, Set) \ + RW_IO32_S3(mBoot, PM_BASE_ADDRESS+bReg, Set, 0) +#define RESET_IO32_PM_S3(mBoot, bReg, Reset) \ + RW_IO32_S3(mBoot, PM_BASE_ADDRESS+bReg, 0, Reset) + +//--------------------------------------------------------------------------- + +#define WRITE_IO8_TCO_S3(mBoot, bReg, bVal) \ + WRITE_IO8_S3(mBoot, TCO_BASE_ADDRESS+bReg, bVal) +#define RW_IO8_TCO_S3(mBoot, bReg, Set, Rst) \ + RW_IO8_S3(mBoot, TCO_BASE_ADDRESS+bReg, Set, Rst) +#define SET_IO8_TCO_S3(mBoot, bReg, Set) \ + RW_IO8_S3(mBoot, TCO_BASE_ADDRESS+bReg, Set, 0) +#define RESET_IO8_TCO_S3(mBoot, bReg, Reset) \ + RW_IO8_S3(mBoot, TCO_BASE_ADDRESS+bReg, 0, Reset) + +#define WRITE_IO16_TCO_S3(mBoot, bReg, bVal) \ + WRITE_IO16_S3(mBoot, TCO_BASE_ADDRESS+bReg, bVal) +#define RW_IO16_TCO_S3(mBoot, bReg, Set, Rst) \ + RW_IO16_S3(mBoot, TCO_BASE_ADDRESS+bReg, Set, Rst) +#define SET_IO16_TCO_S3(mBoot, bReg, Set) \ + RW_IO16_S3(mBoot, TCO_BASE_ADDRESS+bReg, Set, 0) +#define RESET_IO16_TCO_S3(mBoot, bReg, Reset) \ + RW_IO16_S3(mBoot, TCO_BASE_ADDRESS+bReg, 0, Reset) + +#define WRITE_IO32_TCO_S3(mBoot, bReg, bVal) \ + WRITE_IO32_S3(mBoot, TCO_BASE_ADDRESS+bReg, bVal) +#define RW_IO32_TCO_S3(mBoot, bReg, Set, Rst) \ + RW_IO32_S3(mBoot, TCO_BASE_ADDRESS+bReg, Set, Rst) +#define SET_IO32_TCO_S3(mBoot, bReg, Set) \ + RW_IO32_S3(mBoot, TCO_BASE_ADDRESS+bReg, Set, 0) +#define RESET_IO32_TCO_S3(mBoot, bReg, Reset) \ + RW_IO32_S3(mBoot, TCO_BASE_ADDRESS+bReg, 0, Reset) + +//--------------------------------------------------------------------------- + +#define READ_IO8_RTC(bReg) ReadIo8IdxData(CMOS_ADDR_PORT, bReg) +#define WRITE_IO8_RTC(bReg, bVal) WriteIo8IdxData(CMOS_ADDR_PORT, bReg, bVal) +#define RW_IO8_RTC(bReg, Set, Rst) RwIo8IdxData(CMOS_ADDR_PORT, bReg, Set, Rst) +#define SET_IO8_RTC(bReg, Set) RwIo8IdxData(CMOS_ADDR_PORT, bReg, Set, 0) +#define RESET_IO8_RTC(bReg, Reset) RwIo8IdxData(CMOS_ADDR_PORT, bReg, 0, Reset) + +//--------------------------------------------------------------------------- + +#define WRITE_IO8_RTC_S3(mBoot, bReg, bVal) \ + WriteIo8IdxDataS3(mBoot, CMOS_ADDR_PORT, bReg, bVal) +#define RW_IO8_RTC_S3(mBoot, bReg, Set, Rst) \ + RwIo8IdxDataS3(mBoot, CMOS_ADDR_PORT, bReg, Set,Rst) +#define SET_IO8_RTC_S3(mBoot, bReg, Set) \ + RwIo8IdxDataS3(mBoot, CMOS_ADDR_PORT, bReg, Set, 0) +#define RESET_IO8_RTC_S3(mBoot, bReg, Rst) \ + RwIo8IdxDataS3(mBoot, CMOS_ADDR_PORT, bReg, 0, Rst) + +//--------------------------------------------------------------------------- + +//----------------------------------------------------------------------- +#ifndef _EFI_MMIO_ACCESS_H_ +#define _EFI_MMIO_ACCESS_H_ + +#define MmioAddress(BaseAddr, Register) \ + ( (UINTN)BaseAddr + (UINTN)(Register) ) + +// 32-bit +#define Mmio32Ptr(BaseAddr, Register) \ + ( (volatile UINT32 *)MmioAddress(BaseAddr, Register) ) + +#define Mmio32(BaseAddr, Register) \ + *Mmio32Ptr(BaseAddr, Register) + +#define MmioRead32(Addr) \ + Mmio32(Addr, 0) + +#define MmioWrite32(Addr, Value) \ + (Mmio32(Addr, 0) = (UINT32)Value) + +#define MmioRW32(Addr, set, reset) \ + (Mmio32(Addr, 0) = ((Mmio32(Addr, 0) & (UINT32)~(reset)) | (UINT32)set)) + +// 16-bit +#define Mmio16Ptr(BaseAddr, Register) \ + ( (volatile UINT16 *)MmioAddress(BaseAddr, Register) ) + +#define Mmio16(BaseAddr, Register) \ + *Mmio16Ptr(BaseAddr, Register) + +#define MmioRead16(Addr) \ + Mmio16(Addr, 0) + +#define MmioWrite16(Addr, Value) \ + (Mmio16(Addr, 0) = (UINT16)Value) + +#define MmioRW16(Addr, set, reset) \ + (Mmio16(Addr, 0) = ((Mmio16(Addr, 0) & (UINT16)~(reset)) | (UINT16)set)) + +// 8-bit +#define Mmio8Ptr(BaseAddr, Register) \ + ( (volatile UINT8 *)MmioAddress(BaseAddr, Register) ) + +#define Mmio8(BaseAddr, Register) \ + *Mmio8Ptr(BaseAddr, Register) + +#define MmioRead8(Addr) \ + Mmio8(Addr, 0) + +#define MmioWrite8(Addr, Value) \ + (Mmio8(Addr, 0) = (UINT8)Value) + +#define MmioRW8(Addr, set, reset) \ + (Mmio8(Addr, 0) = ((Mmio8(Addr, 0) & (UINT8)~(reset)) | (UINT8)set)) + +#endif +//----------------------------------------------------------------------- + + +//----------------------------------------------------------------------- +// +//----------------------------------------------------------------------- +#ifndef _EFI_PCI_ACCESS_H_ +#define _EFI_PCI_ACCESS_H_ + +#ifndef MmPciAddress +#define MmPciAddress(Base, Bus, Device, Function, Register) \ + ( (UINTN)(Base) + \ + (UINTN)(Bus << 20) + \ + (UINTN)(Device << 15) + \ + (UINTN)(Function << 12) + \ + (UINTN)(Register) ) +#endif + +// 32-bit +#define MmPci32Ptr(Bus, Device, Function, Register) \ + ( (volatile UINT32 *)MmPciAddress(PCIEX_BASE_ADDRESS, Bus, Device, Function, Register) ) + +#define MmPci32(Bus, Device, Function, Register) \ + *MmPci32Ptr(Bus, Device, Function, Register) + +#define MmPciRead32(Bus, Device, Function, Register) \ + MmPci32(Bus, Device, Function, Register) + +#define MmPciWrite32(Bus, Device, Function, Register, Value) \ + (MmPci32(Bus, Device, Function, Register) = (UINT32)Value) + +#define MmPciRW32(Bus, Device, Function, Register, set, reset) \ + (MmPci32(Bus, Device, Function, Register) = ((MmPci32(Bus, Device, Function, Register) & (UINT32)~(reset)) | (UINT32)set)) + +// 16-bit +#define MmPci16Ptr(Bus, Device, Function, Register) \ + ( (volatile UINT16 *)MmPciAddress(PCIEX_BASE_ADDRESS, Bus, Device, Function, Register) ) + +#define MmPci16(Bus, Device, Function, Register) \ + *MmPci16Ptr(Bus, Device, Function, Register) + +#define MmPciRead16(Bus, Device, Function, Register) \ + MmPci16(Bus, Device, Function, Register) + +#define MmPciWrite16(Bus, Device, Function, Register, Value) \ + (MmPci16(Bus, Device, Function, Register) = (UINT16)Value) + +#define MmPciRW16(Bus, Device, Function, Register, set, reset) \ + (MmPci16(Bus, Device, Function, Register) = ((MmPci16(Bus, Device, Function, Register) & (UINT16)~(reset)) | (UINT16)set)) + +// 8-bit +#define MmPci8Ptr(Bus, Device, Function, Register) \ + ( (volatile UINT8 *)MmPciAddress(PCIEX_BASE_ADDRESS, Bus, Device, Function, Register) ) + +#define MmPci8(Bus, Device, Function, Register) \ + *MmPci8Ptr(Bus, Device, Function, Register) + +#define MmPciRead8(Bus, Device, Function, Register) \ + MmPci8(Bus, Device, Function, Register) + +#define MmPciWrite8(Bus, Device, Function, Register, Value) \ + (MmPci8(Bus, Device, Function, Register) = (UINT8)Value) + +#define MmPciRW8(Bus, Device, Function, Register, set, reset) \ + (MmPci8(Bus, Device, Function, Register) = ((MmPci8(Bus, Device, Function, Register) & (UINT8)~(reset)) | (UINT8)set)) + +#endif +//----------------------------------------------------------------------- + +UINT32 DummyVerbTable[]; + +#ifdef __cplusplus +} +#endif +#endif + + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/SBDxe.c b/Chipset/SB/SBDxe.c new file mode 100644 index 0000000..91f2cfb --- /dev/null +++ b/Chipset/SB/SBDxe.c @@ -0,0 +1,7266 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Chipset/SB/SBDxe.c 1 11/02/17 1:48a Chienhsieh $ +// +// $Revision: 1 $ +// +// $Date: 11/02/17 1:48a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Chipset/SB/SBDxe.c $ +// +// 1 11/02/17 1:48a Chienhsieh +// [TAG] EIP357393 +// [Category] Improvement +// [Description] [SAx0039] SPI opcode Security Vulnerability +// [Files] Chipset\SB\SBDxe.c +// ReferenceCode\Chipset\LynxPoint\PchInit\Dxe\PchInit.c +// +// 100 1/29/15 4:09a Mirayang +// [TAG] EIP200269 +// [Category] New Feature +// [Description] For add FlashSmi : Label 4.6.5.5_FlashSmi_00 +// ($/Alaska/SOURCE/Modules/FlashSmi) +// +// 99 9/05/14 3:30a Mirayang +// [TAG] EIP182598 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] Missing ULT differentiation in +// InstallDxePchPlatformPolicy() for GbE slot number detection +// [RootCause] In InstallDxePchPlatformPolicy(), there is a ULT +// differentiation missing. +// [Solution] The strap readout, is not the same for LynxPoint LP. Add +// determine to set value. +// +// 98 5/20/14 2:15a Barretlin +// [TAG] EIP N/A +// [Category] Improvement +// [Description] remove unnecessary source code +// [Files] SBDxe.c +// +// 97 5/16/14 6:16a Barretlin +// [TAG] EIP167087 +// [Category] Improvement +// [Description] BIOS security improvement on Haswell CRB project +// [Files] SBGeneric.c SBDxe.c SBCspLib.h Sb.sdl Sb.sd +// +// 96 5/14/14 1:08p Barretlin +// [TAG] EIP167028 +// [Category] Improvement +// [Description] Variable attribute improment +// [Files] SB.sd SBDxe.c WdtAppDxe.c +// +// 95 3/21/14 4:44a Barretlin +// +// 94 3/20/14 8:41a Barretlin +// [TAG] EIP158783 +// [Category] Improvement +// [Description] Fix programming error +// [Files] SbDxe.c +// +// 93 3/13/14 11:30a Barretlin +// [TAG] EIP153695 +// [Category] Improvement +// [Description] USB Per port control is not reasonable when +// OEM_USBPREPORT_DISABLE_SUPPORT token is Enabled and USB devices are +// behind hubs +// [Files] Sb.sdl Sb.sd Sb.uni GetSetupData.c SbDxe.c PchUsbCommon.c +// PchRegsUsb.h +// +// 92 3/13/14 10:13a Barretlin +// [TAG] EIP N/A +// [Category] Improvement +// [Description] Fix build error when remove or disable CSM module +// [Files] SbDxe.c +// +// 91 11/19/13 7:32a Barretlin +// [TAG] EIP141917 +// [Category] New Feature +// [Description] Support SetTimer() with HPET Timer on Lynx Point +// [Files] SB.sdl SBGeneric.c SBDxe.c SbHpet.h sbProtocal.cif +// SamrtTimer.sdl +// +// 90 11/11/13 6:26a Barretlin +// [TAG] EIP N/A +// [Category] Improvement +// [Description] Fix build error +// [Files] SBDxe.c +// +// 89 10/28/13 10:58p Barretlin +// [TAG] EIP141266 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] CPU exception error after apply "Save/Restore Bit25 of +// PxCMD" solution +// [RootCause] PciIO point is NULL +// [Solution] if PciIO point is NULL, skip this Option ROM, because it +// must not be SATA Option Rom +// [Files] SBDxe.c +// +// 88 10/06/13 2:22a Barretlin +// +// 86 9/17/13 2:00p Barretlin +// [TAG] EIP N/A +// [Category] Improvement +// [Description] set a token to enable/disable SATA DLAE bit +// [Files] SB.sdl SBDxe.c +// +// 85 9/17/13 9:31a Barretlin +// [TAG] EIP134850 +// [Category] New Feature +// [Description] Save/Restore Bit25 of PxCMD in Aptio Chipset Module +// [Files] SBDxe.c +// +// 84 9/17/13 8:51a Barretlin +// [TAG] EIP N/A +// [Category] Improvement +// [Description] update AhciPlatformPolicy default value for AHCI module +// rev.24 +// [Files] SBDxe.c +// +// 83 8/13/13 7:46a Scottyang +// [TAG] EIP132701 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] Coding error. +// [RootCause] Incorrect offset of IO APIC data register. +// [Solution] Correct the offset. +// [Files] SBDxe.c +// +// 82 8/01/13 4:26a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add PCIE LTR setup items. +// [Files] SB.sd, SB.uni, SBDxe.c, GetSetupData.c, SbSetupData.c +// +// 81 7/15/13 10:13p Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Fixed build error at SharkBay DT. +// [Files] SBDxe.c +// +// 80 7/15/13 3:19a Scottyang +// [TAG] EIP129089 +// [Category] Improvement +// [Description] Update PCH RC 1.6.1. +// [Files] SBDxe.c, SB.asl, ..\ReferenceCode\Chipset\LynxPoint\*.* +// +// 79 7/12/13 1:51a Scottyang +// [TAG] EIP126943 +// [Category] Improvement +// [Description] Create S3 boot script tabel for SATA2 controller even +// SATA1 hiden. +// [Files] SBDxe.c +// +// 78 7/09/13 5:15a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Create "PCH Cross Throttling" setup item.(Only ULT +// support) +// [Files] SBDxe.c, SB.sd, SB.uni, GetSetupData.c, SB.sd +// +// 77 7/07/13 10:14p Scottyang +// [TAG] EIP127410 +// [Category] Improvement +// [Description] Update DSDT taable when PCIE port swap function enable. +// [Files] SBDxe.c +// +// 76 7/03/13 8:00a Scottyang +// [TAG] EIP124410 +// [Category] Improvement +// [Description] Implement SMBIOS type 88h for CRID. +// [Files] SBDxe.c, SB.sdl, SB.sd, SBSetup.c, SBSetup.sdl +// +// 75 6/24/13 7:04a Scottyang +// [TAG] EIP127217 +// [Category] Improvement +// [Description] Only update RC's ASL code for L event. +// [Files] SBDxe.c, GPE.asl +// +// 74 6/24/13 6:29a Scottyang +// [TAG] EIP127297 +// [Category] Improvement +// [Description] Update PCH RC 1.6.0. +// [Files] SB.sd, SBDxe.c, ..\ReferenceCode\Chipset\LynxPoint\*.* +// +// 73 6/14/13 12:00a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Make sure the USB preport disable call back function +// processing is performed only once. +// [Files] SBDxe.c +// +// 72 6/13/13 11:53p Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Update RC 150 GNVS. +// [Files] SBDxe.c, SB.uni, SB.sd +// +// 71 6/06/13 10:25p Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Remove XHCB at Dsdt table update. +// [Files] SBDxe.c +// +// 70 6/03/13 3:40a Scottyang +// [TAG] EIP125453 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] Build field when enable "FORCE_USER_TO_SETUP_IF_CMOS_BAD" +// [RootCause] Miss the header file. +// [Files] SBDxe.c +// +// 69 5/23/13 1:56a Scottyang +// [TAG] EIP120623 +// [Category] Improvement +// [Description] LCD turn on automatically when resume from S3. +// [Files] SBPEI.c, SBDxe.c, AcpiModeEnable.c +// +// 68 5/21/13 8:49a Scottyang +// [TAG] EIP121740 +// [Category] Bug Fix +// [Severity] Critical +// [Symptom] Event log has HAL error after resume from S3. +// [RootCause] Coding error for S3 script type. +// [Solution] Correct the S3 script type. +// [Files] SBDxe.c +// +// 67 5/20/13 6:21a Scottyang +// [TAG] EIP124245 +// [Category] Improvement +// [Description] On S3 resume under Raid mode System may gets hangs. +// [Files] SBDxe.c +// +// 66 5/13/13 8:56a Scottyang +// [TAG] EIP123496 +// [Category] Improvement +// [Description] Update PCH RC 1.5.0. +// [Files] ..\ReferenceCode\Chipset\LynxPoint\*.* , SBDxe.C, SBPEI.c, +// SB.sd, SB.uni, SbSetupData.h, GetSetupData.c +// +// 65 5/03/13 4:39a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Make sure Clear the Start and FIS Receive Enable bit +// [Files] SBDxe.c +// +// 64 4/24/13 6:48a Scottyang +// [TAG] EIP82149 +// [Category] Improvement +// [Description] Intel(R) 8 Series Chipset Family Deep Sx and CPU +// Soft-Strap BIOS Override Co-Existence Issue. If the soft-strap override +// feature is required and enabled, BIOS must disable Deep Sx +// functionality. +// [Files] SBDxe.c, SB.sd, SBPlatformData.h +// +// 63 4/15/13 10:50p Wesleychen +// [TAG] None +// [Category] Improvement +// [Description] Hide HPET device if it is disabled. +// [Files] SBDXE.c +// +// 62 4/15/13 10:47p Wesleychen +// [TAG] EIP120857 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] TCO S3 Boot Script in wrong order. +// After S3 resume, TCO_EN bit din't be +// restored. +// [RootCause] Lockdown TCO bit is set before TCO_EN +// restore. +// [Solution] Relocate PM_BASE+ALTGP_SMI_EN & SMI_EN +// save/restore to SbExitPmAuthProtocolCallback(). +// [Files] SBDxe.c +// +// 61 4/09/13 11:35p Wesleychen +// [TAG] EIP120480 +// [Category] Improvement +// [Description] Always disabling PCH platform policy "ExternalObffEn". +// [Files] SB.SDL, SBDXE.c +// +// 59 4/08/13 2:47a Wesleychen +// [TAG] EIP120159 +// [Category] Improvement +// [Description] Update for Intel PCH LPT RC140. +// Added new tokens: +// 1. "PCH_RESET_CYCLE_DURATION" +// 2. "LEGACY_DMA_DISABLE" +// [Files] SB.SDL, SBDXE.c +// +// 58 4/08/13 2:37a Wesleychen +// [TAG] EIP116939 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] The available memory size is less than +// 2GB in Windowss 7 32 bit. +// [RootCause] The "SB_TEMP_MMIO_BASE" is too low. +// [Solution] Rearrange "SB_TEMP_MMIO_BASE" to +// 4GB - 16M(ROM) - 64KB (Intel Required). +// [Files] SB.SDL; SBDxe.c +// +// 57 3/26/13 5:54a Wesleychen +// [TAG] None +// [Category] Improvement +// [Description] Update the address of operation region "XHCB" for +// Intel ACPI RC 1.3.1 compatible. +// [Files] SBDxe.c +// +// 56 3/22/13 5:15a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Wireless LAN PHY use SLP_WLAN# pin +// [Files] SB.sdl, SBDxe.c +// +// 55 3/19/13 8:19a Scottyang +// [TAG] EIP118158 +// [Category] Improvement +// [Description] Correct SBLib_CmosRead () offset. +// [Files] SmiHandlerPorting2.c, SBDxe.c, SBGeneric.c, SBSmm.c, +// SmiHandlerPorting.c +// +// 54 3/19/13 4:56a Scottyang +// [TAG] EIP118480 +// [Category] Improvement +// [Description] Use another array for +// ULT_USB_OVER_CURRENT_MAPPING_SETTINGS. +// [Files] SBDxe.c +// +// 53 3/15/13 3:33a Scottyang +// [TAG] EIP118121 +// [Category] Improvement +// [Description] Update PCH RC 1.3.0. +// [Files] ..\ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, +// SB.sd, SB.uni, GetSetupData.c, SbSetupData.h +// +// 51 3/14/13 2:50a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Fixed coding error for OEM USB preport disable after +// setup menu. +// [Files] SBDxe.c +// +// 49 2/26/13 1:21a Scottyang +// [TAG] EIP116154 +// [Category] Improvement +// [Description] Update PCH RC 1.2.0. +// [Files] .\ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c +// +// 48 2/25/13 5:12a Scottyang +// [TAG] EIP113678 +// [Category] Improvement +// [Description] Disable BIOS lock when recovery and capsule BIOS flash. +// [Files] SBDxe.c +// +// 47 2/19/13 10:35p Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Correct UsbOverCurrentMapping array size fot LPT-LP +// [Files] SBDxe.c +// +// 46 2/09/13 12:12a Scottyang +// [TAG] EIP114922 +// [Category] Improvement +// [Description] Update PCH RC 1.1.0. +// [Files] ..\ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, +// SB.sd, SB.uni, GetSetupData.c, SbSetupDara.h +// +// 45 1/31/13 10:54a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add Serial IO GNVS setup option. +// [Files] SBDxe.c, SB.sd, SB.uni, SbSetupData.h, GetSetupData.c +// +// 44 1/28/13 4:16a Scottyang +// [TAG] EIP108803 +// [Category] Improvement +// [Description] Disable usb port after setup. +// [Files] SB.sdl, SBDxe.c, PchUsbCommon.c +// +// 43 1/27/13 11:01p Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Capsule 2.0 crash dump link function. +// [Files] SBPEI.c +// SBDxe.c +// SBRun.c +// +// 42 1/11/13 2:34a Scottyang +// [TAG] EIP92011 +// [Category] Improvement +// [Description] EC SMI inactive when system resume from iRST sleep +// [Files] SBDxe.c +// +// 41 1/11/13 1:51a Scottyang +// [TAG] EIP88358 +// [Category] Improvement +// [Description] Add FORCE_USER_TO_SETUP_IF_CMOS_BAD token +// [Files] SBDex.c, SBPei.c, RTC.h, SB.sdl +// +// 40 1/10/13 4:53a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Create DTIO value and DM value option +// [Files] SB.sd, SB.uni, SbSetupData.h, GetSetupData.c, SBDxe.c +// +// 39 1/04/13 4:47a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] ADSP Interrupt Mode should same with LPSS Interrupt +// Mode +// [Files] SBDxe.c +// +// 38 12/24/12 5:51a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add option for XHCI Idel L1 workaroung. +// [Files] GetSetupData.c, SbSetupData.h, SB.sd, SB.uni, SBDxe.c, +// SBPEI.c +// +// 37 12/22/12 2:07a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add PCIE "L1 Substates"setup option. +// [Files] GetSetupData.c, SbSetupData.h, SB.sd, SB.uni, SBDxe.c +// +// 36 12/18/12 6:10a Scottyang +// [TAG] EIP109697 +// [Category] Improvement +// [Description] Update PCH RC 0.8.1 +// [Files] ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, SB.sd, +// SbSetupData.c, GetSetupDate.c +// +// 35 12/17/12 6:45a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add setup menu for LPSS and ECTG. +// [Files] GetSetupData.c +// SbSetupData.h +// SB.sd +// SB.uni +// SBDxe.c +// +// 34 11/20/12 9:47a Scottyang +// [TAG] EIP107014 +// [Category] Improvement +// [Description] Update RC 0.8.0 +// [Files] ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, +// SB.sd, SbSetupData.c, GetSetupDate.c +// +// 33 11/19/12 9:57p Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Support RAID mode device ID for WS and server. +// [Files] SBDxe.c, PchSata.c +// +// 32 11/08/12 9:46a Scottyang +// [TAG] Initialize8259 +// +// [Category] Improvement +// +// [Description] To prevent the unexpected interrupt asserted in 8259 +// initialization. +// +// [Files] SBDxe.c +// +// 31 11/08/12 8:44a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add device item that connect LPSS. +// [Files] GetSetupData.c, SbSetupData.h, SBDxe.c, SB.sd, SB.uni +// +// 30 11/06/12 8:12a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Reduce function "GetPchSeries()". +// [Files] SBPEI.c, SBDxe.c, SmiHandlerPorting.c, SmiHandlerPorting2.c +// +// 29 11/05/12 6:24a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Change memory type for RTC. +// [Files] SBDxe.c +// +// 28 11/01/12 4:57a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Remove token "SOLUTION_FOR_EIP95440". +// [Files] SBDxe.c, SB.sdl +// +// 27 10/30/12 8:40a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] ULT do not need. +// +// 26 10/26/12 3:05a Scottyang +// [TAG] None +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] After S3 resime R_PCH_SPI_VSCC1 cannot restore. +// [RootCause] R_PCH_SPI_VSCC0 set first than R_PCH_SPI_VSCC1 cannot +// restore. +// [Solution] change order for R_PCH_SPI_VSCC1 restore first. +// [Files] SBDxe.c +// +// 25 10/26/12 3:00a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Change all L event, GPRW and pcidock at DSDT for ULT. +// [Files] SBDxe.c +// +// 24 10/23/12 10:30p Scottyang +// [TAG] None +// [Category] Improvement +// [Description] After S3 resume EC can not use GPI to trigger SMI +// [Files] SBDxe.c +// +// 23 10/23/12 8:28a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Create Device Sleep at setup menu +// [Files] SB.sd, SB.uni, SBDxe.c, GetSetupData.c, SbSetupData.h +// +// 22 10/23/12 8:17a Scottyang +// [TAG] EIP73607 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] Intruder Detect state is cleaned by BIOS POST. +// [Files] SBDXE.c; SBSECInit.asm +// +// 21 10/23/12 2:09a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Already program at SBPEI.c +// +// 20 10/18/12 5:56a Scottyang +// [TAG] EIP101204 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] Azalia PME bit doesn't been set when Enabled "Azalia PME" +// [RootCause] PME bit will be cleared by AMI PCI bus driver. +// [Solution] Reprogram PME bit in SbInitAfterDeviceInstall(). +// [Files] SBDXE.c +// +// 19 10/16/12 3:56a Scottyang +// [TAG] EIP103924 +// +// [Category] Improvement +// +// [Description] Update RC 0.7.1 +// +// [Files] ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SB.sd, +// SbSetupData.c, GetSetupDate.c +// + + +// 17 10/15/12 8:42a Scottyang +// [TAG] ULTDsdtTableUpdate +// [Category] Improvement +// [Description] Update DSDT when ULT. +// +// 16 10/14/12 8:33a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] One rom for two chip and one chip. +// [Files] SPPEIBoard.c, SB.sd, SBDxe.c, SBPEI.c, PCH.asl +// +// 15 10/12/12 7:46a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Clear all SB warm reset flag +// +// 14 10/12/12 2:04a Scottyang +// [TAG] EIP76432 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] It will BSOD ,while system boot to OS at "starting windows" +// press the KB in succession. +// [RootCause] System BSOD is caused by a large number of SMI generated. +// [Solution] Disable legacy USB SMI in ACPI enable stage. +// [Files] AcpiModeEnable.c; SBDXE.c +// +// 13 10/12/12 2:02a Scottyang +// [TAG] ULT_SUBID +// [Category] Bug Fix +// [Severity] Important +// [Symptom] Win8 BSOD for ULT A0 CPU +// [RootCause] The Sub-device ID not match LPT-LP A0 stepping. +// [Solution] Use old Sub-device ID +// [Files] SBDxe.c +// +// 12 10/01/12 5:53a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Create new token "SOLUTION_FOR_EIP95440" for EIP#95440 +// changed. +// [Files] SB.sdl, SBDXE.c +// +// 11 9/26/12 3:53a Victortu +// [TAG] None +// [Category] Improvement +// [Description] If SPI Flash module support VSCC updated, skip +// programming VSCC. +// [Files] SB.sdl, SBDxe.c +// +// [TAG] None +// [Category] Improvement +// [Description] Update from EIP#95440 to resolve the RAID driver +// compatibility issue. +// [Files] SB.mak, SB.sdl, SBDXE.c +// +// [TAG] None +// [Category] Improvement +// [Description] Update for Intel PCH LPT RC070. +// [Files] SB.sdl, SBDXE.c, SBPEI.c, Pch.sdl, SB.sd, SB.uni +// +// [TAG] None +// [Category] Improvement +// [Description] Update EIP#101515. +// [Files] SBDXE.c +// +// [TAG] None +// [Category] Improvement +// [Description] Update for PCH LP GPIO compatible. +// [Files] SB.sdl, SB.H, AcpiModeEnable.c, AcpiModeEnable.sdl, +// SBDxe.c, SBGeneric.c, SBPEI.c, SBSMI.c, SleepSmi.c, +// SmiHandlerPorting.c, SmiHandlerPorting2.c +// +// [TAG] None +// [Category] Improvement +// [Description] Implement ULT platform LPSS and ADSP setup option. +// [Files] GetSetupData.c, SB.sd, SB.uni, SbSetupData.h, SBDxe.c, +// SB.sdl +// +// 10 9/12/12 5:18a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Remove useless HdmiVerbTable. +// [Files] SB.sdl, SBCspLib.h, SBDxe.c, SBGeneric.c +// +// [TAG] None +// [Category] Improvement +// [Description] Support OEM update VSCC table. +// [Files] SB.H, SB.mak, SB.sdl, SBDXE.c +// +// 9 8/30/12 9:49a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Fixed building error when disable RC_PORT_0. +// [Files] SBDxe.c +// +// 8 8/24/12 6:50a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update RC_PORT_x for PCIe. +// [Files] SB.sdl, SB.sd, SBDxe.c +// +// [TAG] None +// [Category] Improvement +// [Description] Report HPET Function Number to zero for VTD. +// [Files] SBDxe.c +// +// [TAG] None +// [Category] Improvement +// [Description] Implement USB Skip MASS Storage function. +// [Files] SBDxe.c +// +// 7 8/15/12 12:53a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Remove ME_SERVER_SUPPORT. +// [Files] SBDxe.c, SBPEI.c +// +// [TAG] None +// [Category] Improvement +// [Description] Update "SB_TEMP_MMIO_BASE" and +// "EHCI_MMIO_BASE_ADDRESS". +// [Files] SB.sdl, SBDxe.c, SBPEI.c +// +// 6 8/13/12 10:27a Victortu +// [TAG] EIP96150 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] USB Device still can be detected even set USB controllers as +// "Disabled" in BIOS Setup. +// [Solution] Set XHCI disable bit of FD Reg. +// [Files] SBDxe.c +// +// [TAG] None +// [Category] Improvement +// [Description] Implement BIOS Lock function. +// [Files] SBCspLib.h, SBDxe.c, SBSMI.c, SBSMI.dxs, SBSMI.sdl +// +// [TAG] None +// [Category] Improvement +// [Description] Create the token "USB30_OVER_CURRENT_MAPPING_SETTINGS" +// for the policy "Usb30OverCurrentPins". +// [Files] SB.sdl, SBDxe.c +// +// [TAG] None +// [Category] Improvement +// [Description] Improve CheckDisableUsbControllers function. +// [Files] SBDxe.c +// +// [TAG] None +// [Category] Improvement +// [Description] Remove PCH_A0PWRON_SAFEMODE. +// [Files] SBDxe.c, Pch.sdl +// +// [TAG] None +// [Category] Improvement +// [Description] Remove useless Dppm items. +// [Files] GetSetupData.c, SB.sd, SbSetupData.h, SBDxe.c +// +// [TAG] None +// [Category] Improvement +// [Description] Update PCH Policy. +// [Files] SB.sdl, SBDxe.c, SBPEI.c +// +// [TAG] None +// [Category] Improvement +// [Description] Implement USB Precondition option for policy +// "UsbPrecondition". +// [Files] GetSetupData.c, SB.sd, SB.uni, SbSetupData.h, SBDxe.c, +// SBPEI.c +// +// 5 7/27/12 6:13a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update setup items and policies. +// [Files] GetSetupData.c, SB.sdl, SB.sd, SB.uni, SbSetupData.h, +// SBPEI.c, SBDXE.c +// +// [TAG] None +// [Category] Improvement +// [Description] Update to support ULT Platform. +// [Files] SB.H, SB.mak, SB.sdl, SB.sd, SBSetup.c, +// AcpiModeEnable.c, SBDxe.c, SBPEI.c, SBSMI.c, SleepSmi.c, +// SmiHandlerPorting.c, SmiHandlerPorting2.c, SBPPI.h, Pch.sdl +// +// 4 7/02/12 10:18a Victortu +// [TAG] None +// [Category] Improvement +// [Description] SETUP.MassStorageOpRom will instead of SETUP.SataRaidRom +// to decide the launching policy of RAID UEFI driver/Legacy OpRom if +// CsmOptOut_SUPPORT enabled. +// [Files] SBDex.c, SB.sd +// +// [TAG] None +// [Category] Improvement +// [Description] Updated and modified for PCH RC 0.6.0. +// [Files] SBGeneric.c, SB.sdl, SBCspLib.h, SBDxe.c, SBPEI.c +// +// 3 6/13/12 11:34p Victortu +// [TAG] None +// [Category] Improvement +// [Description] Implement Warm Boot function for Secure Flash feature. +// [Files] SB.H, SB.mak, SB.sdl, SBDxe.c, SBGeneric.c, SBPEI.c, +// SBSMI.c +// +// 2 4/25/12 9:10a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Relayout PCH USB Setup. +// [Files] GetSetupData.c; SB.sd; SB.uni; SbSetupData.h; SBDxe.c +// +// [TAG] None +// [Category] Improvement +// [Description] Fixed GenericSio use 0x0 ~ 0xfff issue. +// [Files] SBDxe.c +// +// 1 2/08/12 8:24a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SBDxe.C +// +// Description: This file contains code for Template Southbridge +// initialization in the DXE stage +// +//<AMI_FHDR_END> +//************************************************************************* + +//--------------------------------------------------------------------------- +// Include(s) +//--------------------------------------------------------------------------- + +#include <Efi.h> +#include <token.h> +#include <AmiLib.h> +#include <AmiDxeLib.h> +#include <Setup.h> +#include <Dxe.h> +#include <PCI.h> +#include <AmiHobs.h> +#include <AmiCspLib.h> +#include "HDAVBTBL.h" +#include <AcpiRes.h> +#include <Protocol\BusSpecificDriverOverride.h> +#include <Protocol\LoadedImage.h> +#include <protocol\DriverBinding.h> + +// Consumed Protocols +#include <Protocol\PciIo.h> +#include <Protocol\Cpu.h> +#include <Protocol\PciRootBridgeIo.h> +#include <Protocol\DevicePath.h> +#if SB_PCIE_ERROR_LOG_SUPPORT +#include <Protocol\GenericElog.h> +#endif + +#if ACPI_SUPPORT + #if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x00010014) + #include <Protocol\AcpiSystemDescriptionTable.h> + #else + #include <Protocol\AcpiSupport.h> + #endif +#endif + +#if defined(CsmOptOut_SUPPORT) && (CsmOptOut_SUPPORT == 1) +#include <AmiLoadCsmPolicy.h> +#endif + +#if CSM_SUPPORT +#include <Protocol\CsmPlatform.h> +#include <Protocol\LegacyBiosExt.h> +#endif + +// Produced Protocols +#include <Protocol\RealTimeClock.h> +#include <Protocol\WatchdogTimer.h> +#include <Protocol\Timer.h> +#include <Protocol\Legacy8259.h> + +#if defined HPET_PROTOCOL_SUPPORT && HPET_PROTOCOL_SUPPORT == 1 +#include <Protocol\SbHpet.h> +#endif + +#if defined(IntelPchInclude_SUPPORT) && IntelPchInclude_SUPPORT +#include <PchAccess.h> +#endif +#include <Protocol\PchPlatformPolicy\PchPlatformPolicy.h> + +#if defined iME_SUPPORT && iME_SUPPORT +#include <Guid\MeBiosExtensionSetup\MeBiosExtensionSetup.h> +#endif + +#include <Protocol\SBPlatformData.h> +#include <Board\EM\Platform\PlatformSetup.h> + +#if defined INTEL_CRB_DXE_KSC_LIB_SUPPORT && INTEL_CRB_DXE_KSC_LIB_SUPPORT +#if defined CRB_EC_SUPPORT && CRB_EC_SUPPORT +#include <KscLib.h> +#include <Protocol\ECACCESS.h> +#endif +#endif + +#if SecureMod_SUPPORT +#include <Flash.h> +#endif +#if defined (SPI_INITIALIZE_WITH_VSCC) && (SPI_INITIALIZE_WITH_VSCC == 1) +#include <Protocol\FlashProtocol.h> +#endif +#if defined AMIUSB_SUPPORT && AMIUSB_SUPPORT == 1 +#include <Protocol\AmiUsbController.h> +#endif + +#if defined OEM_USB_PER_PORT_DISABLE_SUPPORT && OEM_USB_PER_PORT_DISABLE_SUPPORT == 1 +#include <Protocol\UsbIo.h> +#endif + +#include <Protocol\GlobalNvsArea\GlobalNvsArea.h> +#include <RTC.h> +#include "protocol\BlockIo.h" +#include "Protocol\PDiskInfo.h" +#include "Protocol\PIDEController.h" +#include "Protocol\PIDEBus.h" +#include "Protocol\PAhciBus.h" +#include <Protocol\SMBios.h> //(EIP124410) + +//--------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//--------------------------------------------------------------------------- +// Constant Definition(s) + +// Build flag adjustments +#ifndef SMM_SUPPORT +#define SMM_SUPPORT 0 +#endif + +// Timer Constants +#define SYSTEM_TIMER_IRQ 0 + +// Timer Period +#define TIMER_TICK 838 // ns + +// default duration is 0xffff ticks +#define DEFAULT_TICK_DURATION ((65535 * 838 + 50) / 100) +#define MAX_TICK_DURATION DEFAULT_TICK_DURATION + +//8259 PIC defines +#define ICW1 0x11 // Slave exists and ICW4 required. +#define ICW3_M 1 << 2 // IRQ 2 connects to slave +#define ICW3_S 2 // IRQ 2 connects to master +#define ICW4 1 // Bit 4 Normal Nested Mode + // Bit 3 Non-buffered Mode + // Bit 2 Unused with non-buffered mode + // Bit 1 Set manual EOI instead of automatic + // Bit 0 8086/8088 mode + +#define OCW1_M 0xff // Master Mask +#define OCW1_S 0xff // Slave Mask + +#define EOI_COMMAND 0x20 // EOI Command + +#define FLASH_DEVICE_BASE_ADDRESS (0xffffffff - FLASH_SIZE + 1) + +#define PCI_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x00 +#define PCI_CLASS_NETWORK_OTHER 0x80 + +#define SPI_OPCODE_READ_ID_INDEX 0x4 + +#if defined HPET_PROTOCOL_SUPPORT && HPET_PROTOCOL_SUPPORT == 1 +#define LEGACY_TIMER_0_COUNT 0x40 +#define LEGACY_TIMER_1_COUNT 0x41 +#define LEGACY_TIMER_CTRL 0x43 +#define TIMER_1_COUNT LEGACY_TIMER_1_COUNT +#endif + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +EFI_STATUS WatchdogInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +); + +EFI_STATUS Initialize8259( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +); + +EFI_STATUS PciPlatformInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +); + +EFI_STATUS +SBDXE_BoardInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +); + +VOID SbInitAfterDeviceInstall ( + IN EFI_EVENT Event, + IN VOID *Context +); + +VOID EFIAPI WatchdogHandler ( + IN EFI_EVENT Event, + IN VOID *Context +); + +EFI_STATUS EFIAPI RegisterHandler ( + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction +); + +EFI_STATUS EFIAPI WatchdogSetTimerPeriod ( + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod +); + +EFI_STATUS EFIAPI WatchdogGetTimerPeriod ( + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN UINT64 *TimerPeriod +); + +EFI_STATUS EFIAPI TimerInit ( + IN EFI_EVENT Event, + IN VOID *Context +); + +EFI_STATUS TimerRegisterHandler ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN EFI_TIMER_NOTIFY NotifyFunction +); + +EFI_STATUS SetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod +); + +EFI_STATUS GetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN UINT64 *TimerPeriod +); + +EFI_STATUS GenerateSoftIntr ( + IN EFI_TIMER_ARCH_PROTOCOL *This +); + +VOID SaveRestoreRegisters ( + IN BOOLEAN Save +); + +VOID CreateSbAcpiComponent ( VOID ); + +EFI_STATUS ReserveSbResources ( + IN EFI_HANDLE ImgHandle, + IN EFI_HANDLE CntrHandle +); + +EFI_STATUS AddLpcStdIoSpace ( VOID ); + //(EIP124410)>> +VOID UpdateSmbios136Table( + IN EFI_EVENT Event, + IN VOID *Context +); + //(EIP124410)<< + // [EIP134850] >> +#if defined CSM_SUPPORT && CSM_SUPPORT == 1 +VOID SBSataRegSaveRestore( + IN EFI_EVENT Event, + IN VOID *Context +); +#endif + // [EIP134850] << + +VOID InitSbRegsBeforeBoot ( + IN EFI_EVENT Event, + IN VOID *Context +); + +VOID InitSbRegsBeforeLagecyBoot ( + IN EFI_EVENT Event, + IN VOID *Context +); + +#if defined OEM_USB_PER_PORT_DISABLE_SUPPORT && OEM_USB_PER_PORT_DISABLE_SUPPORT == 1 +VOID USBPrePortDisableCallback ( + IN EFI_EVENT Event, + IN VOID *Context +); +#endif + +VOID EHCIWorkAround ( + IN UINT8 EhciDev +); + +VOID ConfigPciDevices ( + IN EFI_SYSTEM_TABLE *SystemTable +); + +VOID ReportSBDxeError ( + IN EFI_STATUS Status +); + +#ifdef CSM_OPRROM_POLICY_GUID +VOID SbCheckOprom ( + IN EFI_EVENT Event, + IN VOID *Context +); +#endif + +VOID SbSetupNvramUpdatedCallback ( + IN EFI_EVENT Event, + IN VOID *Context +); + +VOID SbExitPmAuthProtocolCallback ( + IN EFI_EVENT Event, + IN VOID *Context +); + +EFI_STATUS +InstallDxePchPlatformPolicy (VOID); + +VOID SBSpiProgramVSCC(VOID); +VOID SBS3SaveSpi(VOID); // [ EIP357393 ] + +VOID SBClearRTC_AlarmFlag(VOID); + +VOID LocatePublishIdeSataAcpiTables(VOID); + +EFI_STATUS SbSmmInit( + IN EFI_EVENT Event, + IN VOID *Context +); + +//--------------------------------------------------------------------------- +// Variable and External Declaration(s) +//--------------------------------------------------------------------------- +// Variable Declaration(s) +typedef struct { + UINT16 Address; + UINT16 Length; +} LPC_IO_STD_DECODE; + +typedef struct { + UINT8 Bus; + UINT8 Dev; + UINT8 Fun; + VOID *Process; +} DEVICES_AFTER_PCIIO; + +typedef struct { + UINT32 Signature; + UINT32 Length; +} EFI_ACPI_COMMON_HEADER; + +DEVICES_AFTER_PCIIO gDevicesTable[] = { + { PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, NULL }, + { PCIEBRS2_BUS, PCIEBRS2_DEV, PCIEBRS2_FUN, NULL }, + { PCIEBRS3_BUS, PCIEBRS3_DEV, PCIEBRS3_FUN, NULL }, + { PCIEBRS4_BUS, PCIEBRS4_DEV, PCIEBRS4_FUN, NULL }, + { PCIEBRS5_BUS, PCIEBRS5_DEV, PCIEBRS5_FUN, NULL }, + { PCIEBRS6_BUS, PCIEBRS6_DEV, PCIEBRS6_FUN, NULL }, + { PCIEBRS7_BUS, PCIEBRS7_DEV, PCIEBRS7_FUN, NULL }, + { PCIEBRS8_BUS, PCIEBRS8_DEV, PCIEBRS8_FUN, NULL }, + { HDA_BUS, HDA_DEV, HDA_FUN, NULL }, //(EIP101204) + { SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, NULL }, + { SATA_BUS, SATA_DEV, SATA_FUN, NULL }, + { 0xFF, 0xFF, 0xFF, NULL } +}; +UINTN gEventCount = sizeof(gDevicesTable) / sizeof(DEVICES_AFTER_PCIIO); + +typedef struct { + UINT32 VidDid; + UINT32 Vscc; +} SPI_VSCC_TABLE; + //(EIP124410)>> +#pragma pack (1) +typedef struct { + SMBIOS_STRUCTURE_HEADER Header; + UINT16 OemInfo; + UINT16 Zero; //terminator +} EFI_MISC_OEM_TYPE_0x88; +#pragma pack () + //(EIP124410)<< +EFI_HANDLE mTimerProtocolHandle = NULL; +EFI_HANDLE mWatchdogHandle = NULL; +EFI_EVENT mWatchdogEvent; + +// Save daylight when set. +UINT8 gDaylight = 0; +UINT8 gMasterBase; +UINT8 gSlaveBase; + +// Initially in protected mode. (0 = Real, 1 = 32 bit protected) +UINT8 gMode = 1; + +// Initially all Real IRQs masked, protected masked +UINT16 gIrqMask[2] = {0xffff, 0xffff}; + +// Initially all Real IRQs Edge, protected Edge. +UINT16 gIrqTrigger[2] = {0, 0}; +UINT64 mWatchdogPeriod = 0; +UINT64 mProgrammedTimerValue; + +BOOLEAN gErrorLoggingFlag = FALSE; + +EFI_TIMER_NOTIFY mNotifyFunction; +EFI_LEGACY_8259_PROTOCOL *mLegacy8259 = NULL; +EFI_WATCHDOG_TIMER_NOTIFY mWatchdogNotifyFunction = NULL; +EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *gPciRootBridgeIo = NULL; +AMI_S3_SAVE_PROTOCOL *gBootScript = NULL; +VOID *gSbInitNotifyReg = NULL; +VOID *gCsmOpromReg = NULL; +VOID *gSbSetupNvramUpdatedReg = NULL; +VOID *gSbExitPmAuthProtocolReg = NULL; +VOID *gSbSataIdeProtocolReg = NULL; +EFI_STATUS LocateSBSATAIDESupportProtocol (IN EFI_GUID *Protocol,OUT VOID **Instance,IN BOOLEAN Type ); + + +SB_SETUP_DATA *gSbSetupData = NULL; +SB_PLATFORM_DATA SbPlatformData; +#if defined(CsmOptOut_SUPPORT) && (CsmOptOut_SUPPORT == 1) +VOID *gInterface = NULL; +#endif +#if defined CSM_SUPPORT && CSM_SUPPORT == 1 // [EIP134850] >> +VOID *SataOpRomRegistration; +static EFI_GUID OpRomStartEndProtocolGuid = OPROM_START_END_PROTOCOL_GUID; +UINT8 SaveSataReg = 0; +UINT8 IsSataOpROM = 0; +UINT8 DLAE = 0; +#endif // [EIP134850] << +BOOLEAN gDisableAllUsbControllers = FALSE; +#if defined AMIUSB_SUPPORT && AMIUSB_SUPPORT == 1 +EFI_EVENT gEvtUsbProtocol = NULL; +VOID *gRegUsbProtocol = NULL; +EFI_USB_PROTOCOL *gUsbProtocol = NULL; +#endif + //(EIP124410)>> +EFI_SMBIOS_PROTOCOL *gSmbiosProtocol = NULL; +EFI_GUID gEfiSmbiosProtocolGuid = EFI_SMBIOS_PROTOCOL_GUID; + //(EIP124410)<< +#if SB_PCIE_ERROR_LOG_SUPPORT +EFI_GUID gElogProtocolGuid = EFI_SM_ELOG_PROTOCOL_GUID; +#endif +#define IDE_SATA_ACPI_TABLE_STORAGE_GUID \ + { 0x22046D50,0xF390,0x498c,0x92,0xE5,0x5B,0xA4,0xF8,0xE7,0xF8,0xB6} +EFI_GUID IdeSataAcpiTableStorageGuid = IDE_SATA_ACPI_TABLE_STORAGE_GUID; +#if defined(CsmOptOut_SUPPORT) && (CsmOptOut_SUPPORT == 1) +EFI_GUID gAmiLoadCsmGuid = AMI_LOAD_CSM_GUID; +#endif +#if SecureMod_SUPPORT +EFI_GUID gBiosLockEnableEventGuid = AMI_EVENT_FLASH_WRITE_LOCK; +#endif + +#if defined(HPET_APIC_INTERRUPT_MODE) && (HPET_APIC_INTERRUPT_MODE != 0) +extern UINT8 gBspLocalApicID; +#endif + +CSP_RES_ITEM gSbResTable[] = { +//---------------------------------------------------------------------------- +// ResBase ResLength ResType Attributes +//---------------------------------------------------------------------------- +// Always reserve 16MB for ROM image. +{ RESERVED_ROM_BASE, RESERVED_ROM_LENGTH, EfiGcdMemoryTypeMemoryMappedIo ,\ + (EFI_MEMORY_UC | EFI_MEMORY_RUNTIME)}, +// IOAPICs dedicated Space +{ APCB, APCL, EfiGcdMemoryTypeMemoryMappedIo , \ + (EFI_MEMORY_UC|EFI_MEMORY_RUNTIME)}, +#if FEC00000_APIC_AUTODETECT +{ APCB + APCL, 0x00100000 - APCL, EfiGcdMemoryTypeMemoryMappedIo , \ + EFI_MEMORY_UC}, +#endif + +#if HPET_SUPPORT +// HPET dedicated Space +{ HPET_BASE_ADDRESS, 0x00004000, EfiGcdMemoryTypeMemoryMappedIo , \ + (EFI_MEMORY_UC|EFI_MEMORY_RUNTIME)}, +#endif +// Reserve for RCRB Base, the attributes of this region should be defined to +// RUNTIME because it includes the SPI_BASE_ADDRESS. +{ SB_RCRB_BASE_ADDRESS, SB_RCRB_LENGTH, EfiGcdMemoryTypeMemoryMappedIo , \ + (EFI_MEMORY_UC|EFI_MEMORY_RUNTIME)}, +// SB Temp Memory Mapped Space +{ SB_TEMP_MMIO_BASE, SB_TEMP_MMIO_BASE_LENGTH, EfiGcdMemoryTypeMemoryMappedIo, (EFI_MEMORY_UC) }, +// HECI Memory Mapped Space +{ HECI_BASE_ADDRESS, 0x10000, EfiGcdMemoryTypeMemoryMappedIo, (EFI_MEMORY_UC) }, +// HECI2 Memory Mapped Space +{ HECI2_BASE_ADDRESS, 0x10000, EfiGcdMemoryTypeMemoryMappedIo, (EFI_MEMORY_UC) }, +// IO Used by PM register block +{ PM_BASE_ADDRESS, PMLN ,EfiGcdIoTypeIo , -1 }, +// IO Used by SMBus register block +{ SMBUS_BASE_ADDRESS, SMBL ,EfiGcdIoTypeIo , -1 }, +// IO Used by GPIO register block +{ GPIO_BASE_ADDRESS, GPLN ,EfiGcdIoTypeIo , -1 }, +}; + +UINTN gSbResTableCount = sizeof(gSbResTable) / sizeof(CSP_RES_ITEM); + +#define ONBOARD_RAID_GUID \ + { 0x5d206dd3, 0x516a, 0x47dc, 0xa1, 0xbc, 0x6d, 0xa2, 0x4, 0xaa, 0xbe, 0x8 }; + +#define EXIT_PM_AUTH_PROTOCOL_GUID \ + { 0xd088a413, 0xa70, 0x4217, 0xba, 0x55, 0x9a, 0x3c, 0xb6, 0x5c, 0x41, 0xb3 }; + +#if SataDriver_SUPPORT +#define PCH_EFI_RAID_DRIVER_EXECUTION_GUID \ + { 0x99D5757C, 0xD906, 0x11E0, 0x8D, 0x78, 0x8D, 0xE4, 0x48, 0x24, 0x01, 0x9B }; +#endif + +// GUID Definition(s) +EFI_GUID gOnboardRaidGuid = ONBOARD_RAID_GUID; +EFI_GUID gEfiTimerArchProtocolGuid = EFI_TIMER_ARCH_PROTOCOL_GUID; +EFI_GUID gEfiLegacy8259ProtocolGuid = EFI_LEGACY_8259_PROTOCOL_GUID; +EFI_GUID gEfiPciIoProtocolGuid = EFI_PCI_IO_PROTOCOL_GUID; +EFI_GUID gDevicePathProtocolGuid = EFI_DEVICE_PATH_PROTOCOL_GUID; +EFI_GUID gEfiPciPlatformProtocolGuid = EFI_PCI_PLATFORM_PROTOCOL_GUID; +EFI_GUID gDxeSvcTblGuid = DXE_SERVICES_TABLE_GUID; +EFI_GUID gSetupNvramUpdatedGuid = AMITSE_NVRAM_UPDATE_GUID; +EFI_GUID gDxePchPlatformPolicyProtocolGuid = DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID; +EFI_GUID gWatchdogGuid = EFI_WATCHDOG_TIMER_ARCH_PROTOCOL_GUID; +EFI_GUID gEfiPciRootBridgeIoProtocolGuid = EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID; +EFI_GUID gExitPmAuthProtocolGuid = EXIT_PM_AUTH_PROTOCOL_GUID; +#if defined AMIUSB_SUPPORT && AMIUSB_SUPPORT == 1 +EFI_GUID gEfiUsbProtocolGuid = EFI_USB_PROTOCOL_GUID; +#endif + +EFI_GUID BeforeBootProtocolGuid = AMITSE_EVENT_BEFORE_BOOT_GUID; +#if CSM_SUPPORT +EFI_GUID BeforeLegacyBootProtocolGuid = EFI_AMI_LEGACYBOOT_PROTOCOL_GUID; +#endif + +#ifdef CSM_OPRROM_POLICY_GUID +EFI_GUID gCsmOpromPolicyGuid = CSM_OPRROM_POLICY_GUID; +#endif + +extern EFI_GUID gEfiSmmControlProtocolGuid; + +EFI_GUID GuidListCheckForRaid[] = { BUS_OVERRIDE_GUIDS_FOR_RAID NULL }; +EFI_HANDLE ImageHandleArray[5] = {NULL}; +BOOLEAN LoadedImageDone = FALSE; + +EFI_STATUS RaidGetDriver( + IN EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL *This, + IN OUT EFI_HANDLE *DriverImageHandle +); + +static EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL RaidBusSpecificDriverOverride = { + RaidGetDriver +}; + +static AHCI_PLATFORM_POLICY_PROTOCOL AhciPlatformPolicy= { +#ifndef DiPM_SUPPORT + FALSE, // Legacy Raid option selected + TRUE // Ahcibus driver handles the ATAPI devices +#else + FALSE, // Legacy Raid option selected + TRUE, // Ahcibus driver handles the ATAPI devices +#if !defined SB_SATA_DLAE || SB_SATA_DLAE == 0 + FALSE, // Drive LED on ATAPI Enable (DLAE) +#else + TRUE, +#endif +#ifdef POWERUP_IN_STANDBY_SUPPORT + POWERUP_IN_STANDBY_SUPPORT, // PowerUpInStandby feature is supported or not +#else + FALSE, +#endif +#ifdef POWERUP_IN_STANDBY_MODE + POWERUP_IN_STANDBY_MODE, // PowerUpInStandby mode +#else + FALSE, +#endif + DiPM_SUPPORT // Device Initiated power management +#endif +}; + +// Protocol Definition(s) + +// Architectural Protocol Definitions +EFI_WATCHDOG_TIMER_ARCH_PROTOCOL mWatchdog = { + RegisterHandler, + WatchdogSetTimerPeriod, + WatchdogGetTimerPeriod +}; + +EFI_TIMER_ARCH_PROTOCOL mTimerProtocol = { + TimerRegisterHandler, + SetTimerPeriod, + GetTimerPeriod, + GenerateSoftIntr +}; + +#if defined AMIUSB_SUPPORT && AMIUSB_SUPPORT == 1 +VOID SbUsbProtocolCallback ( + IN EFI_EVENT Event, + IN VOID *Context +); +#endif + +#if SecureMod_SUPPORT +VOID BiosLockEnableCallback ( + IN EFI_EVENT Event, + IN VOID *Context +); +#endif + +VOID ULTDsdtTableUpdate ( + IN ACPI_HDR *DsdtTable +); + +VOID DsdtTableUpdate ( + IN ACPI_HDR *DsdtTable +); +// External Declaration(s) + +extern EFI_STATUS CountTime ( + IN UINTN DelayTime, + IN UINT16 BaseAddr +); + +VOID ClearWarmResetFlag (VOID); + +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: RetrainLink +// +// Description: Retrain PCIE Device Link +// +// Input: IN UINT32 Address +// +// Output: +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID RetrainLink(IN UINT32 Address) +{ + SET_MEM8(Address + R_PCH_PCIE_LCTL, BIT05); // 0x50 + CountTime(10, PM_BASE_ADDRESS); + while (READ_MEM16(Address + R_PCH_PCIE_LSTS) & BIT11); // 0x52 +} + +#if SataDriver_SUPPORT +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InstallPchSataUefiDriver +// +// Description: Install SATA UEFI RAID driver GUID for PCH SataDriver. +// +// Input: None +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID InstallPchSataUefiDriver ( VOID ) +{ +#if defined(CsmOptOut_SUPPORT) && (CsmOptOut_SUPPORT == 1) + SETUP_DATA SetupData; + EFI_GUID SetupGuid = SETUP_GUID; + UINTN Size = sizeof(SETUP_DATA); +#endif // CsmOptOut_SUPPORT + BOOLEAN InstallRaidDriver = TRUE; + EFI_HANDLE Handle = NULL; + EFI_STATUS Status; + EFI_HANDLE RaidDriverHandle=NULL; + EFI_GUID PchEfiRaidDriverExecutionGuid = \ + PCH_EFI_RAID_DRIVER_EXECUTION_GUID; + + if (gSbSetupData->SataInterfaceMode == SATA_MODE_RAID) { + +#if defined(CsmOptOut_SUPPORT) && (CsmOptOut_SUPPORT == 1) + Status = pBS->LocateProtocol( &gAmiLoadCsmGuid, \ + NULL, \ + &gInterface ); + if(!EFI_ERROR(Status)) { + + Status = pRS->GetVariable ( L"Setup", \ + &SetupGuid, \ + NULL,\ + &Size, \ + &SetupData ); + if (!EFI_ERROR(Status)) { + if ((SetupData.MassStorageOpRom == 0) || \ + (SetupData.MassStorageOpRom == 2)) + InstallRaidDriver = FALSE; + } + } +#else + if (gSbSetupData->SataRaidRom == 0) InstallRaidDriver = FALSE; +#endif // CsmOptOut_SUPPORT + + // + // By default Legacy Raid option settings initilized + // + AhciPlatformPolicy.RaidDriverMode= FALSE; + AhciPlatformPolicy.AhciBusAtapiSupport= TRUE; + + if (InstallRaidDriver) { + Status = pBS->InstallProtocolInterface( \ + &Handle, \ + &PchEfiRaidDriverExecutionGuid, \ + EFI_NATIVE_INTERFACE, \ + NULL); + ASSERT_EFI_ERROR(Status); + + // + // UEFI Raid driver enabled + // + AhciPlatformPolicy.RaidDriverMode= TRUE; + // + // Uefi Raid driver supports the ATAPI device. So Ahcibus doesn't need to handle the ATAPI devices + // + AhciPlatformPolicy.AhciBusAtapiSupport= FALSE; + } + + Status = pBS->InstallProtocolInterface( &RaidDriverHandle, + &gAciPlatformPolicyProtocolGuid, + EFI_NATIVE_INTERFACE, + &AhciPlatformPolicy); + } +} +#endif + +#if FORCE_USER_TO_SETUP_IF_CMOS_BAD // [EIP88358] >> +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ForceSetupIfCmosBad +// +// Description: BIOS force to enter setup if CMOS was bad. +// +// Input: None +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID ForceSetupIfCmosBad (VOID) +{ + EFI_STATUS Status = EFI_SUCCESS; + CMOS_BAD_HOB *CmosBadHob; + UINT32 BootFlow = BOOT_FLOW_CONDITION_FIRST_BOOT; + EFI_GUID guidBootFlow = BOOT_FLOW_VARIABLE_GUID; + EFI_GUID ghoblistguid = HOB_LIST_GUID; + EFI_GUID CmosBadHobGuid = CMOS_BAD_HOB_GUID; + + CmosBadHob = GetEfiConfigurationTable( //get hob list + pST, + &ghoblistguid); + + if(CmosBadHob == NULL) return; + + Status = FindNextHobByGuid( //the hob exit when cmos is bad and creat hob success. + &CmosBadHobGuid, + &CmosBadHob); + + if(!EFI_ERROR(Status)) { + TRACE((-1, "SB: Force to Setup.\n")); + pRS->SetVariable( + L"BootFlow", + &guidBootFlow, + EFI_VARIABLE_BOOTSERVICE_ACCESS, + sizeof(BootFlow), + &BootFlow); + } +} +#endif // [EIP88358] << + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBDXE_Init +// +// Description: This function is the entry point for this DXE. This function +// initializes the chipset SB +// +// Input: ImageHandle - Image handle +// SystemTable - Pointer to the system table +// +// Output: Return Status based on errors that occurred while waiting for +// time to expire. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SBDXE_Init ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + + EFI_STATUS Status = EFI_SUCCESS; + EFI_EVENT Event; + CPUINFO_HOB *CpuInfoHob; + EFI_GUID HobListGuid = HOB_LIST_GUID; + EFI_GUID AmiCpuinfoHobGuid = AMI_CPUINFO_HOB_GUID; + EFI_GUID SetupGuid = SETUP_GUID; + UINTN VariableSize = sizeof(SB_SETUP_DATA); + EFI_EVENT BeforeBootEvent; + EFI_EVENT LegacyBootEvent; + EFI_EVENT CRIDSmbiosEvent; //(EIP124410) +#if defined CSM_SUPPORT && CSM_SUPPORT == 1 + EFI_EVENT SbSataOptEvent; // [EIP134850] +#endif + VOID *Protocol = NULL; + VOID *NotifyReg = NULL; +#if SecureMod_SUPPORT + EFI_EVENT BleEvtProtocol = NULL; + VOID *BleProtocolReg = NULL; +#endif + VOID *Registration = NULL; + + InitAmiLib(ImageHandle, SystemTable); + + PROGRESS_CODE (DXE_SB_INIT); + + ClearWarmResetFlag(); + + Status = pBS->LocateProtocol( &gEfiPciRootBridgeIoProtocolGuid, \ + NULL, \ + &gPciRootBridgeIo ); + ReportSBDxeError(Status); + + Status = pBS->LocateProtocol( AMI_S3_SAVE_PROTOCOL_GUID, \ + NULL, \ + &gBootScript ); + ReportSBDxeError(Status); + + //Find APIC ID Hob. + CpuInfoHob = (CPUINFO_HOB*)GetEfiConfigurationTable( SystemTable, \ + &HobListGuid ); + if (CpuInfoHob == NULL) Status = EFI_UNSUPPORTED; + else Status = FindNextHobByGuid( &AmiCpuinfoHobGuid, (VOID**)&CpuInfoHob); + ASSERT_EFI_ERROR(Status); + +#if defined(HPET_APIC_INTERRUPT_MODE) && (HPET_APIC_INTERRUPT_MODE != 0) + gBspLocalApicID = CpuInfoHob->Cpuinfo[0].ApicId; +#endif + + // Put the I/O APIC in Virtual wire mode + // CHIPSET PROGRAMMING TO ENABLE IOAPIC GOES HERE + + WRITE_MEM8_S3(gBootScript, APCB, 0); // IO APIC index (0) + WRITE_MEM32_S3(gBootScript, APCB + 0x10, (NCPU << 24)); // APIC ID // [EIP132701] + WRITE_MEM8_S3(gBootScript, APCB, 0x10); // Index 0x10 + // INT0 - EXT INT unmasked + WRITE_MEM32_S3(gBootScript, APCB + 0x10, 0x700); // [EIP132701] + + // Install 8259 services + Initialize8259(ImageHandle, SystemTable); + + // Install watchdog timer services + WatchdogInit(ImageHandle, SystemTable); + +#if SmartTimer_SUPPORT == 0 + // Install Legacy timer services + TimerInit(ImageHandle, SystemTable); +#endif + + + Status = pBS->AllocatePool( EfiBootServicesData, \ + VariableSize, \ + &gSbSetupData ); + ASSERT_EFI_ERROR(Status); + + GetSbSetupData( pRS, gSbSetupData, FALSE ); + + // + // Enable or Disable the Devices depending upon the Setup. + // + + PROGRESS_CODE (DXE_SB_DEVICES_INIT); + + ConfigPciDevices(SystemTable); + + CreateSbAcpiComponent(); + + // Clear RTC Reg C Alarm Flag + SBClearRTC_AlarmFlag(); + + Status = SBDXE_BoardInit(ImageHandle, SystemTable); + + Status = RegisterProtocolCallback( &gEfiPciIoProtocolGuid, \ + SbInitAfterDeviceInstall, \ + NULL, \ + &Event, \ + &gSbInitNotifyReg ); + ReportSBDxeError( Status ); + +#ifdef CSM_OPRROM_POLICY_GUID + Status = RegisterProtocolCallback( &gCsmOpromPolicyGuid, \ + SbCheckOprom, \ + NULL, \ + &Event, \ + &gCsmOpromReg ); + + ReportSBDxeError( Status ); +#endif + + Status = RegisterProtocolCallback( &gSetupNvramUpdatedGuid, \ + SbSetupNvramUpdatedCallback, \ + NULL, \ + &Event, \ + &gSbSetupNvramUpdatedReg ); + ReportSBDxeError( Status ); + + + Status = ReserveSbResources(ImageHandle, SystemTable); + + ReportSBDxeError(Status); + + Status = RegisterProtocolCallback( &gExitPmAuthProtocolGuid, \ + SbExitPmAuthProtocolCallback, \ + NULL, \ + &Event, \ + &gSbExitPmAuthProtocolReg ); + ReportSBDxeError( Status ); + +#if defined AMIUSB_SUPPORT && AMIUSB_SUPPORT == 1 + Status = RegisterProtocolCallback( &gEfiUsbProtocolGuid,\ + SbUsbProtocolCallback,\ + NULL,\ + &gEvtUsbProtocol,\ + &gRegUsbProtocol ); +#endif + +#if SecureMod_SUPPORT + Status = RegisterProtocolCallback( &gBiosLockEnableEventGuid,\ + BiosLockEnableCallback,\ + NULL,\ + &BleEvtProtocol,\ + &BleProtocolReg ); +#endif + + Status = CreateReadyToBootEvent( TPL_NOTIFY, InitSbRegsBeforeBoot, \ + NULL, &BeforeBootEvent ); + ReportSBDxeError(Status); + //(EIP124410)>> + Status = CreateReadyToBootEvent( TPL_NOTIFY, UpdateSmbios136Table, \ + NULL, &CRIDSmbiosEvent ); + ReportSBDxeError(Status); + //(EIP124410)<< + Status = CreateLegacyBootEvent( TPL_CALLBACK, \ + InitSbRegsBeforeLagecyBoot, \ + NULL, \ + &LegacyBootEvent ); + ReportSBDxeError(Status); + +#if defined OEM_USB_PER_PORT_DISABLE_SUPPORT && OEM_USB_PER_PORT_DISABLE_SUPPORT == 1 + RegisterProtocolCallback( + &BeforeBootProtocolGuid, + USBPrePortDisableCallback, + NULL, &Event, &Registration + ); + +#if CSM_SUPPORT + RegisterProtocolCallback( + &BeforeLegacyBootProtocolGuid, + USBPrePortDisableCallback, + NULL, &Event, &Registration + ); + + CreateLegacyBootEvent(TPL_CALLBACK, &USBPrePortDisableCallback, NULL, &LegacyBootEvent); +#endif + + pBS->CreateEvent( + EVT_SIGNAL_EXIT_BOOT_SERVICES,TPL_CALLBACK, + &USBPrePortDisableCallback, NULL, &Event + ); +#endif + + Status = InstallDxePchPlatformPolicy(); + ReportSBDxeError(Status); + + //Program SPI base VSCC + SBSpiProgramVSCC(); + //Restore SPI register for S3 resume // [ EIP357393 ] + SBS3SaveSpi(); // [ EIp357393 ] + +//- Status = AddLpcStdIoSpace(); + +#if SataDriver_SUPPORT + InstallPchSataUefiDriver(); +#endif +#if defined CSM_SUPPORT && CSM_SUPPORT == 1 // [EIP134850] >> + if(gSbSetupData->SataInterfaceMode == SATA_MODE_RAID){ + Status = RegisterProtocolCallback(&OpRomStartEndProtocolGuid, + SBSataRegSaveRestore, + NULL, + &SbSataOptEvent, + &SataOpRomRegistration); + TRACE((TRACE_ALWAYS, "Register OpRomStartEndProtocol callback() = %r\n", Status)); + } +#endif // [EIP134850] << + +#if FORCE_USER_TO_SETUP_IF_CMOS_BAD // [EIP88358] >> + ForceSetupIfCmosBad(); +#endif // [EIP88358] << + +#if defined SMM_SUPPORT && SMM_SUPPORT == 1 + Status = pBS->LocateProtocol(&gEfiSmmControlProtocolGuid, NULL, &Protocol); + if (EFI_ERROR(Status)) + { + Status = RegisterProtocolCallback( + &gEfiSmmControlProtocolGuid, + SbSmmInit, + NULL, + &Event, + &NotifyReg); + ASSERT_EFI_ERROR(Status); + } + else + { + Status = SbSmmInit(NULL, NULL); + if (Status != EFI_SUCCESS) + { + TRACE((TRACE_ALWAYS, "SbSmmInit() = %r\n", Status)); + ASSERT_EFI_ERROR(Status); + } + } +#endif + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SBClearRTC_AlarmFlag +// +// Description: Clear RTC Reg C Alarm Flag +// +// Input: None +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SBClearRTC_AlarmFlag(VOID) +{ + + // Clear all SMI status here. + // Must read RTC Reg C to be able to clear SMM RTC alarm flag. + SBLib_CmosRead(0x0C); + + WRITE_IO16_PM(ACPI_IOREG_PM1_STS, 0xcd31); // 0x00 + if (GetPchSeries() == PchLp) { + WRITE_IO32_PM(ACPI_PCHLP_IOREG_GPE0_STS + 0x0c, 0xffffffff); // 0x8C + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_ALTGP_SMI_STS, 0xffffffff); // 0x50 + } else { + WRITE_IO32_PM(ACPI_IOREG_GPE0_STS, 0xffffffff); // 0x20 + WRITE_IO32_PM(ACPI_IOREG_GPE0_STS + 4, 0xffffffff); // 0x24 + WRITE_IO16_PM(ACPI_IOREG_ALTGP_SMI_STS, 0xffff); // 0x3A + } + WRITE_IO16_PM(ACPI_IOREG_DEVACT_STS, 0xffff); // 0x44 + WRITE_IO16_TCO(TCO_IOREG_STS1, 0xffff); // 0x04 + WRITE_IO16_TCO(TCO_IOREG_STS2, 0xfffe); // 0x06, Skip Intrusion [EIP73607] + WRITE_IO32_PM(ACPI_IOREG_SMI_STS, 0xffffffff); // 0x34 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SBSpiProgramVSCC +// +// Description: Program SPI VSCC. +// +// Input: None +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SBSpiProgramVSCC(VOID) +{ + EFI_STATUS Status; + UINT32 Data32 = 0; + UINT32 dUVSCC = 0; + UINT32 Mask = 0xFFFFFFFF; + UINT8 Data8 = 0; +#if defined (SPI_INITIALIZE_WITH_VSCC) && (SPI_INITIALIZE_WITH_VSCC == 1) + static FLASH_PROTOCOL *Flash = NULL; +#endif +#if defined (OEM_UPDATE_VSCC_TABLE_SUPPORT) && (OEM_UPDATE_VSCC_TABLE_SUPPORT == 1) + SPI_VSCC_TABLE SpiVsccTbl[] = { OEM_SPI_VSCC_TABLE }; + UINTN VsccTableCount = sizeof (SpiVsccTbl) / sizeof (SPI_VSCC_TABLE); + UINT16 SpiCmd =0; + UINT32 Timeout; + UINTN i; +#endif + + TRACE((TRACE_ALWAYS, "[[ SBSpiProgramVSCC() Start. ]]\n")); + + // If Flash module support VSCC updated, skip programming VSCC. + // If enable OEM_UPDATE_VSCC_TABLE_SUPPORT, override VSCC value by ELINK. + if (((0 == READ_MEM32_SPI(R_RCRB_SPI_UVSCC)) && + (0 == READ_MEM32_SPI(R_RCRB_SPI_LVSCC))) || + (OEM_UPDATE_VSCC_TABLE_SUPPORT == 1)) { +#if defined (SPI_INITIALIZE_WITH_VSCC) && (SPI_INITIALIZE_WITH_VSCC == 1) + Status = pBS->LocateProtocol(&gFlashProtocolGuid, NULL, &Flash); + if (!EFI_ERROR(Status)) { + // Identify Flash through FlashWriteEnable Hook. + Flash->DeviceWriteEnable(); + Flash->DeviceWriteDisable(); + } + if (((0 == READ_MEM32_SPI(R_RCRB_SPI_UVSCC)) && + (0 == READ_MEM32_SPI(R_RCRB_SPI_LVSCC))) || + (OEM_UPDATE_VSCC_TABLE_SUPPORT == 1)) +#endif + { + dUVSCC = ((UINT32)(READ_MEM8_SPI(R_RCRB_SPI_OPMENU + 2)) << 8); + + Data8 = READ_MEM8_SPI(R_RCRB_SPI_PREOP + 1); + if ((Data8 == 0x50) || (Data8 == 0x39)) + dUVSCC |= BIT03; + + if (Data8 == 0x39 ) { + dUVSCC |= (BIT04 + BIT02); + } else if(Data8 != 0x50) { + dUVSCC |= BIT02; + } + + if (READ_MEM8_SPI(R_RCRB_SPI_OPMENU + 2) == 0xD8) + dUVSCC |= (BIT00 + BIT01); + else + dUVSCC |= (BIT00); + +#if defined (OEM_UPDATE_VSCC_TABLE_SUPPORT) && (OEM_UPDATE_VSCC_TABLE_SUPPORT == 1) + // Set SPI read-address = 0 + WRITE_MEM32_SPI(R_RCRB_SPI_FADDR, 0); + SpiCmd = SPI_OPCODE_READ_ID_INDEX << 4; + SpiCmd += ( ( 3 - 1 ) << 8 ); + SpiCmd += ( 1 << 14 ); + // Go (BIT1) + WRITE_MEM16_SPI(R_RCRB_SPI_SSFCTL, SpiCmd | BIT01); + + // WaitForSpiCycleDone + for ( Timeout = 0, i = 0; Timeout < 0x4000000; Timeout++ ) { + i = READ_MEM8_SPI(R_RCRB_SPI_SSFSTS); + if ( i & BIT02 ) break; + } + // IoDelay + for ( Timeout = 0; Timeout < 33; Timeout++ ) { + IoWrite8( 0xEB, 0x55 ); + IoWrite8( 0xEB, 0xAA ); + } + // write BIT2 to clear CycleDone status + WRITE_MEM8_SPI(R_RCRB_SPI_SSFSTS, BIT02); + // Get Flash ID + Data32 = READ_MEM32_SPI(R_RCRB_SPI_FDATA0) & 0x00FFFFFF; + // Swap MSB/LSB + Data32 = (((Data32 & 0xff) << 16) | ((Data32 & 0xff0000) >>16) | ((Data32 & 0xff00))); + + for ( i =0; i < VsccTableCount; i++ ) { + if (SpiVsccTbl[i].VidDid == Data32) { + dUVSCC = SpiVsccTbl[i].Vscc; + } + } +#endif + WRITE_MEM32_SPI(R_RCRB_SPI_UVSCC, dUVSCC); + WRITE_MEM32_SPI(R_RCRB_SPI_LVSCC, dUVSCC); + } + } +//#### } + + Status = ReadSPIDescriptor(0x01, 0x00, &Data32); + if (!EFI_ERROR(Status)) + { + Data8 = (UINT8)((Data32 & (BIT27 | BIT28 | BIT29)) >> 27); + SET_MEM8_SPI(R_RCRB_SPI_SSFCTL + 2, Data8); + } + TRACE((TRACE_ALWAYS, "[[ SBSpiProgramVSCC() Done. ]]\n")); +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IsMobileSku +// +// Description: This function will check the South Bridge whether it is +// mobile SKU. +// +// Input: None +// +// Output: BOOLEAN +// TRUE - The South Bridge is mobile SKU. +// FALSE - The South Bridge is not mobile SKU. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN IsMobileSku (VOID) +{ + return TRUE; // TODO +} + +//---------------------------------------------------------------------------- +#if (ACPI_SUPPORT) + +#include <Acpi20.h> +#include <Protocol\AcpiSupport.h> + +EFI_EVENT mAcpiEvent; +VOID *mAcpiReg; +UINT64 gHpetBase = HPET_BASE_ADDRESS; +UINTN mHpetTblHandle; +SB_ASL_BUFFER *gSbAslBufPtr = NULL; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: CreateSbAcpiCallback +// +// Description: This function will create all ACPI components for SB when +// ACPI support protocol is available. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID CreateSbAcpiCallback ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + EFI_STATUS Status = EFI_SUCCESS; + EFI_GUID SbAslBufPtrGuid = SB_ASL_BUFFER_PTR_GUID; + CHAR16 SbAslBufPtrVar[] = SB_ASL_BUFFER_PTR_VARIABLE; + HPET_20 *Hpet; + EFI_ACPI_SUPPORT_PROTOCOL *As; + ACPI_HDR *DsdtPtr = NULL; + FACP_20 *Table = NULL; + UINT8 *OtRegDataPtr = NULL; + ASL_OBJ_INFO AslObj; + EFI_ACPI_TABLE_VERSION Version; + UINTN Handle; + UINTN Index; + UINT32 SbAslBufVarPtr; + UINT32 OldSbAslBufVarPtr = 0; + UINT32 Attributes = 0; + UINTN VarSize; + UINT8 OemId[6] = CONVERT_TO_STRING(T_ACPI_OEM_ID); + UINT8 OemTblId[8] = \ + CONVERT_TO_STRING(T_ACPI_OEM_TBL_ID); + + // It must be only one instance of such protocol + Status = pBS->LocateProtocol(&gEfiAcpiSupportGuid, NULL, &As); + if(EFI_ERROR(Status)) { + TRACE((-1, "ACPI Support Protocol is not ready for SB components\n")); + return; + } + TRACE((-1,"SB Locate Protocol(ACPISupport)- %r Success\n", Status)); + + if (gSbSetupData->Hpet) { + + Hpet = MallocZ(sizeof(HPET_20)); + ASSERT(Hpet); + if (Hpet) { + // Fill Table header; + Hpet->Header.Signature = HPET_SIG; + Hpet->Header.Length = sizeof(HPET_20); + Hpet->Header.Revision = 1; + Hpet->Header.Checksum = 0; + MemCpy(&(Hpet->Header.OemId[0]), OemId, 6); + MemCpy(&(Hpet->Header.OemTblId[0]), OemTblId, 8); + Hpet->Header.OemRev = ACPI_OEM_REV; + Hpet->Header.CreatorId = 0x2e494d41;//"AMI." + Hpet->Header.CreatorRev = CORE_REVISION; + + // Fill HPET Fields + // The GAS structure + Hpet->BaseAddress.AddrSpcID = GAS_SYS_MEM; + Hpet->BaseAddress.RegBitWidth = 64; + Hpet->BaseAddress.RegBitOffs = 0; + // Base address of 1K HPET RegBlock space + Hpet->BaseAddress.Address = gHpetBase; + + Hpet->EvtTmrBlockId.TMR_BLK_ID = *(UINT32*)(UINTN)gHpetBase; + + Hpet->MinTickPeriod = 14318; // Approx 1ms + + // Add table + Status = As->SetAcpiTable( As, \ + Hpet, \ + TRUE, \ + EFI_ACPI_TABLE_VERSION_ALL, \ + &mHpetTblHandle ); + TRACE((-1,"ACPISupport.SetAcpiTable() = %r \n", Status)); + ASSERT_EFI_ERROR(Status); + + // Free memory used for table image + pBS->FreePool(Hpet); + } + } + + // Find DSDT ACPI Table + for (Index = 0; Index < ACPI_RSDT_TABLE_NUM; Index++) { + Status = As->GetAcpiTable(As, Index, &Table, &Version, &Handle); + if (EFI_ERROR(Status)) break;//no more tables left + + if ((Table->Header.Signature == FACP_SIG) && (DsdtPtr == NULL)) { + DsdtPtr = (ACPI_HDR*)Table->DSDT; + TRACE((-1, "SBDXE: Found DSDT Table at 0x%08X\n", DsdtPtr)); + break; + } + } + + Status = pBS->AllocatePool( EfiReservedMemoryType, \ + sizeof(SB_ASL_BUFFER), \ + (VOID**)&gSbAslBufPtr ); + if (!EFI_ERROR(Status)) { + MemSet(gSbAslBufPtr, sizeof(SB_ASL_BUFFER), 0); + Status = GetAslObj( (UINT8*)(DsdtPtr + 1), \ + DsdtPtr->Length - sizeof(ACPI_HDR)-1, \ + "CPSB", \ + otOpReg, \ + &AslObj ); + if (!EFI_ERROR(Status)) { + OtRegDataPtr = (UINT8*)AslObj.DataStart; + SbAslBufVarPtr = (UINT32)gSbAslBufPtr; + *(UINT32*)(OtRegDataPtr + 2) = SbAslBufVarPtr; + + VarSize = sizeof(SbAslBufVarPtr); + Status = pRS->GetVariable( SbAslBufPtrVar, \ + &SbAslBufPtrGuid, \ + &Attributes, \ + &VarSize, \ + &OldSbAslBufVarPtr ); + if ((EFI_ERROR(Status)) || (SbAslBufVarPtr != OldSbAslBufVarPtr)) + if (EFI_ERROR(Status)) Attributes = (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS); + Status = pRS->SetVariable( SbAslBufPtrVar, \ + &SbAslBufPtrGuid, \ + Attributes, + sizeof(SbAslBufVarPtr), \ + &SbAslBufVarPtr ); + } + } + + LocatePublishIdeSataAcpiTables(); + + // Kill the Event + pBS->CloseEvent(Event); +} + +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ConfigPciDevices +// +// Description: This function will Enable/Disable onchip PCI device in SB +// depend on SETUP questions. +// +// Input: SystemTable - Pointer to the system table +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID ConfigPciDevices ( + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: CreateSbAcpiComponent +// +// Description: This function creates all ACPI components supported by SB. +// +// Input: None +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID CreateSbAcpiComponent (VOID) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINT8 Buffer8 = 0; + +//HPET Support +#if (HPET_SUPPORT) + if (gSbSetupData->Hpet) { + Buffer8 = (UINT8)((HPET_BASE_ADDRESS >> 12) & 3) | 0x80; + // Enable HPET (0x3404) + WRITE_MEM32_RCRB_S3(gBootScript, RCRB_MMIO_HPTC, Buffer8); + } else { + RESET_MEM32_RCRB_S3(gBootScript, RCRB_MMIO_HPTC, 0x80); + } +#endif + +#if (ACPI_SUPPORT) + Status = RegisterProtocolCallback( &gEfiAcpiSupportGuid, \ + CreateSbAcpiCallback, \ + NULL, \ + &mAcpiEvent, \ + &mAcpiReg ); + // If AcpiSupport protocol has been installed we can use it rigth on + // the way + pBS->SignalEvent( mAcpiEvent ); +#endif + + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetExtCapStrucAddr +// +// Description: This function tries to find the specific PCI Express extended +// capabilities ID structure address. +// +// Input: Bus - The PCI Bus number. +// Dev - The PCI Device number. +// Fun - The PCI Function number. +// FindCapId - the specific extended capabilities ID will be +// found. +// +// Output: EFI_STATUS +// EFI_SUCCESS - Found the extended capabilities structure +// successfully, the input CapPtr16 will +// have the structure address. +// EFI_NOT_FOUND - Not found the extended capabilities +// structure. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS GetExtCapStrucAddr ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 FindCapId, + IN UINT16 *CapPtr16 ) +{ + UINT32 Buffer32; + + *CapPtr16 = 0x100; + + Buffer32 = READ_PCI32(Bus, Dev, Fun, *CapPtr16); + while (Buffer32 != 0xffffffff) { + if ((UINT16)Buffer32 == FindCapId) return EFI_SUCCESS; + *CapPtr16 = (UINT16)((Buffer32 >> 20) & 0xfffc); + if (*CapPtr16 == 0) break; + Buffer32 = READ_PCI32(Bus, Dev, Fun, *CapPtr16); + } + return EFI_NOT_FOUND; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetLegCapStrucAddr +// +// Description: This function tries to find the specific capabilities +// ID structure address. +// +// Input: Bus - The PCI Bus number. +// Dev - The PCI Device number. +// Fun - The PCI Function number. +// FindCapId - the specific legacy capabilities ID will be +// found. +// +// Output: EFI_STATUS +// EFI_SUCCESS - Found the legacy capabilities structure +// successfully, the input CapPtr16 will +// have the structure address. +// EFI_NOT_FOUND - Not found the extended capabilities +// structure. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS GetLegCapStrucAddr ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT8 FindCapId, + IN UINT16 *CapPtr16 ) +{ + UINT8 Buffer8; + + if (READ_PCI32(Bus, Dev, Fun, PCI_VID) != 0xffffffff) { + if (READ_PCI16(Bus, Dev, Fun, PCI_STS) & 0x10) { + *CapPtr16 = ((READ_PCI8(Bus, Dev, Fun, PCI_HDR) & 0x7f) == 2) ? \ + 0x14:0x34; + *CapPtr16 = (UINT16)READ_PCI8(Bus, Dev, Fun, *CapPtr16); + if (*CapPtr16 == 0) return EFI_NOT_FOUND; + Buffer8 = READ_PCI8(Bus, Dev, Fun, *CapPtr16); + while (Buffer8 != 0) { + if (Buffer8 == FindCapId) return EFI_SUCCESS; + Buffer8 = (UINT8)(*CapPtr16) + 1; + *CapPtr16 = (UINT16)(READ_PCI8(Bus, Dev, Fun, Buffer8)); + if (*CapPtr16 == 0) break; + Buffer8 = READ_PCI8(Bus, Dev, Fun, *CapPtr16); + } + } + } + + return EFI_NOT_FOUND; +} + +#if SB_PCIE_ERROR_LOG_SUPPORT +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbEnablePciDevErr +// +// Description: Enable the error register of PCI-Express Device. +// +// Input: Address - PCI Express Config MMIO of device. +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID SbEnablePciDevErr(IN UINT64 Address) +{ + UINT32 DevBaseAddr = (UINT32)Address; + UINT8 CapPtr; + + CapPtr = SbFindCapPtr(DevBaseAddr, 0x10); + if(CapPtr != 0) + { + // Clear Error Status + WRITE_MEM8_S3(gBootScript, DevBaseAddr + CapPtr + 0x0A, (BIT0 | BIT1 | BIT2)); + + // Enable CEE/NFE/FEE + // Root? + if ((READ_MEM8(DevBaseAddr + CapPtr + 0x02) & 0xF0) == 0x40) + WRITE_MEM8_S3(gBootScript, DevBaseAddr + CapPtr + 0x1C, (BIT0 | BIT1 | BIT2)); + + // End-Device? + else if ((READ_MEM8(DevBaseAddr + CapPtr + 0x02) & 0xF0) == 0x00) + WRITE_MEM8_S3(gBootScript, DevBaseAddr + CapPtr + 0x08, (BIT0 | BIT1 | BIT2)); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SbPciExpressDeviceInitialize +// +// Description: Initialize PCI Express Device Error Handle. +// +// Input: Address - PCI Express Config MMIO of device. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID SbPciExpressDeviceInitialize(IN UINT64 Address) +{ + UINT8 Dev; + UINT8 Func; + UINT8 CurrentBus; + UINT16 Buffer16; + UINT64 DevAddress; + UINT8 PciFun = (Address >> 12) & 0x07; + UINT8 CapPtr; + UINT8 Buffer8; + + CapPtr = SbFindCapPtr(Address, 0x10); + Buffer8 = READ_MEM8(Address + CapPtr + 0x08); + Buffer8 &= 0xF0; + if (gSbSetupData->PcieRootPortURE[PciFun]) + Buffer8 |= BIT03; + + if (gSbSetupData->PcieRootPortFEE[PciFun]) + Buffer8 |= BIT02; + + if (gSbSetupData->PcieRootPortNFE[PciFun]) + Buffer8 |= BIT01; + + if (gSbSetupData->PcieRootPortCEE[PciFun]) + Buffer8 |= BIT00; + + WRITE_MEM8_S3( gBootScript, \ + Address + CapPtr + 0x08, \ + Buffer8 ); + + CurrentBus = READ_MEM8((UINT32)Address + PCIBR_REG_SBUSN); + + for (Dev = 0; Dev < 32; Dev++) + { + for (Func = 0; Func < 8; Func++) + { + DevAddress = (UINT64)SB_PCIE_CFG_ADDRESS(CurrentBus, Dev, Func, 0); + + if (READ_MEM16(DevAddress) == 0xFFFF) + continue; + + SbEnablePciDevErr(DevAddress); + + Buffer16 = READ_MEM16((UINT32)SB_PCIE_CFG_ADDRESS(CurrentBus, Dev, 0, 0) + PCI_SCC); + if (Buffer16 == 0x0604) + { + DevAddress = (UINT64)SB_PCIE_CFG_ADDRESS(CurrentBus, Dev, 0, 0); + SbPciExpressDeviceInitialize(DevAddress); + } + } + } +} +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbInitAfterDeviceInstall +// +// Description: This callback function is called when a PCI I/O Protocol is +// installed. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SbInitAfterDeviceInstall ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + EFI_STATUS Status; + UINTN BufferSize = 20 * sizeof(EFI_HANDLE); + EFI_HANDLE Handle; + EFI_PCI_IO_PROTOCOL *PciIo; + PCI_STD_DEVICE Pci; + UINTN i = 0; + UINTN PciSeg; + UINTN PciBus; + UINTN PciDev; + UINTN PciFun; +#if SB_PCIE_ERROR_LOG_SUPPORT + UINT64 Address = 0; + EFI_SM_ELOG_PROTOCOL *GenericElogProtocol = NULL; +#endif + + Status = pBS->LocateHandle( ByRegisterNotify, \ + NULL, \ + gSbInitNotifyReg, \ + &BufferSize, \ + &Handle ); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) return; + // + // Locate PciIo protocol installed on Handle + // + + Status = pBS->HandleProtocol( Handle, &gEfiPciIoProtocolGuid, &PciIo ); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) return; + + // Get PCI Device Bus/Device/Function Numbers + Status = PciIo->GetLocation( PciIo, &PciSeg, &PciBus, &PciDev, &PciFun ); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) return; + + TRACE((TRACE_ALWAYS, "PCI Bus, Device, function = %X, %X,%X\n", PciBus, PciDev, PciFun )); + + if (((UINT8)PciBus == SMBUS_BUS) && \ + ((UINT8)PciDev == SMBUS_DEV) && \ + ((UINT8)PciFun == SMBUS_FUN)) { + if ((READ_PCI32_SMBUS(SMBUS_REG_MBASE0_ADDR) & 0xFFFFFFF0) && \ + ((READ_PCI8_SMBUS(SMBUS_REG_PCICMD) & B_PCH_SMBUS_PCICMD_MSE) == 0)) + SET_PCI8_SMBUS(SMBUS_REG_PCICMD, B_PCH_SMBUS_PCICMD_MSE); + + if ((READ_PCI16_SMBUS(SMBUS_REG_BASE_ADDR) & 0xFFC0) && \ + ((READ_PCI8_SMBUS(SMBUS_REG_PCICMD) & B_PCH_SMBUS_PCICMD_IOSE) == 0)) + SET_PCI8_SMBUS(SMBUS_REG_PCICMD, B_PCH_SMBUS_PCICMD_IOSE); + + gEventCount -= 1; + } + //(EIP101204)>> + if (((UINT8)PciBus == HDA_BUS) && \ + ((UINT8)PciDev == HDA_DEV) && \ + ((UINT8)PciFun == HDA_FUN)) { + if(gSbSetupData->AzaliaPme){ + SET_PCI16_HDA(R_PCH_HDA_PCS, B_PCH_HDA_PCS_PMEE); + } + gEventCount -= 1; + } //<<(EIP101204) + + if (((UINT8)PciBus == SATA_BUS) && \ + ((UINT8)PciDev == SATA_DEV) && \ + ((UINT8)PciFun == SATA_FUN)) { + Status = PciIo->Pci.Read (PciIo, + EfiPciIoWidthUint32, + 0, + sizeof (Pci) / sizeof (UINT32), + &Pci); + + //Check for Onboard Raid controller and if's it's onboard install the Guid on that Handle. + if (!EFI_ERROR (Status)) + { + if ( Pci.Header.ClassCode[1] == PCI_CL_MASS_STOR_SCL_RAID && \ + Pci.Header.VendorId == 0x8086 && \ + (Pci.Header.DeviceId == 0x282A || Pci.Header.DeviceId == 0x2822 || Pci.Header.DeviceId == 0x2826) ) { // for mobile, Desktop, WS and Server + + pBS->InstallProtocolInterface(&Handle, \ + &gOnboardRaidGuid, \ + EFI_NATIVE_INTERFACE, \ + NULL); + + // + // Install the Bus Specific Override Protocol on the Raid Controller Handle + // + Status = pBS->InstallMultipleProtocolInterfaces(&Handle, + &gEfiBusSpecificDriverOverrideProtocolGuid, + &RaidBusSpecificDriverOverride, + NULL); + + ASSERT_EFI_ERROR(Status); + } + } + gEventCount -= 1; + } + + if (((UINT8)PciBus == PCIEBRS_BUS) && \ + ((UINT8)PciDev == PCIEBRS_DEV) && \ + (((UINT8)PciFun >= PCIEBRS_FUN) || ((UINT8)PciFun >= PCIEBRS8_FUN))) { +#if SB_PCIE_ERROR_LOG_SUPPORT + Status = pBS->LocateProtocol( &gElogProtocolGuid, + NULL, + &GenericElogProtocol ); + if (!EFI_ERROR (Status)) { + gErrorLoggingFlag = TRUE; + Address = SB_PCIE_CFG_ADDRESS((UINT8)PciBus, (UINT8)PciDev, (UINT8)PciFun, 0); + SbPciExpressDeviceInitialize(Address); + } +#endif + gEventCount -= 1; + } + + // Kill the Event + if (gEventCount == 1) + pBS->CloseEvent(Event); +} + +#ifdef CSM_OPRROM_POLICY_GUID +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbCheckOprom +// +// Description: This callback function is called before/after processing all +// PCI optonal ROM. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SbCheckOprom ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + EFI_STATUS Status; + UINTN BufferSize = sizeof(EFI_HANDLE); + EFI_HANDLE Handle; + CSM_PLATFORM_POLICY_DATA *Data; + UINTN Seg; + UINTN Bus; + UINTN Dev; + UINTN Fun; + + Status = pBS->LocateHandle( ByRegisterNotify, \ + NULL, \ + gCsmOpromReg, \ + &BufferSize, \ + &Handle ); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) return; + + // Locate CSM Platform Policy data + Status = pBS->HandleProtocol( Handle, &gCsmOpromPolicyGuid, &Data ); + + if ( EFI_ERROR(Status) ) return; + if (Data == NULL) return; + if (Data->ExecuteThisRom == FALSE) return; + if(Data->PciIo == NULL) return; + + Status = Data->PciIo->GetLocation( Data->PciIo, &Seg, &Bus, &Dev, &Fun ); + +#if SataDriver_SUPPORT +#if !defined(CsmOptOut_SUPPORT) || (CsmOptOut_SUPPORT == 0) + if ((Bus == SATA_BUS) && (Dev == SATA_DEV) && (Fun == SATA_FUN)) { + if (gSbSetupData->SataInterfaceMode == SATA_MODE_RAID) { + if (gSbSetupData->SataRaidRom != 1) + Data->ExecuteThisRom = TRUE; + else + Data->ExecuteThisRom = FALSE; + } + } +#endif +#endif + + // Close the event if needed. + // pBS->CloseEvent(Event); +} +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ReserveSbResources +// +// Description: This function reserves system resources for SB internal +// device(s). +// +// Input: ImgHandle - Image handle +// CntrHandle - Control handle +// +// Output: Return Status based on errors that occurred while waiting for +// time to expire. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS ReserveSbResources ( + IN EFI_HANDLE ImgHandle, + IN EFI_HANDLE CntrHandle ) +{ + EFI_STATUS Status; + +#if (CORE_VERSION >= 4600) + Status = LibAllocCspResource( gSbResTable, \ + gSbResTableCount, \ + ImgHandle, \ + CntrHandle ); +#else + DXE_SERVICES *gDxeSvcTbl; + UINTN i; + + gDxeSvcTbl = (DXE_SERVICES*)GetEfiConfigurationTable(pST,&gDxeSvcTblGuid); + if(gDxeSvcTbl == NULL) return EFI_NOT_AVAILABLE_YET; + + for (i = 0; i < gSbResTableCount; i++) { + // Remove gSbResTable existant IO to non-existant IO + if (gSbResTable[i].Attributes == 0xffffffffffffffff) { + Status = gDxeSvcTbl->RemoveIoSpace( gSbResTable[i].ResBase, \ + gSbResTable[i].ResLength ); + } else { + Status = gDxeSvcTbl->RemoveMemorySpace( gSbResTable[i].ResBase, \ + gSbResTable[i].ResLength); + } + if (EFI_ERROR(Status)) { + TRACE((-1, "RemoveSpace B=%lX, L=%X, i=%d, S=%r\n", \ + gSbResTable[i].ResBase, gSbResTable[i].ResLength, i, Status)); + ASSERT_EFI_ERROR(Status); + break; + } + } + + // Convert gSbResTable non-existant IO to existant IO + Status = AllocCspResource( gDxeSvcTbl, gSbResTable, gSbResTableCount, \ + ImgHandle, CntrHandle, TRUE ); + if(EFI_ERROR(Status)) return Status; +#endif + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: AddLpcStdIoSpace +// +// Description: This function adds LPC I/O or I/O resources to the global +// coherency domain of the processor. +// +// Input: None +// +// Output: Return Status based on errors that occurred while waiting for +// time to expire. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS AddLpcStdIoSpace ( VOID ) +{ + EFI_STATUS Status; + DXE_SERVICES *DxeSvcTbl; + LPC_IO_STD_DECODE LpcIoStdDecode[] = { + {0x3F8, 8}, {0x2F8, 8}, {0x220, 8}, {0x228, 8},\ + {0x238, 8}, {0x2E8, 8}, {0x338, 8}, {0x3E8, 8},\ + {0x378, 8}, {0x778, 8}, {0x278, 8}, {0x678, 8},\ + {0x3BC, 4}, {0x7BC, 4}, {0x3F0, 6}, {0x3F7, 1},\ + {0x370, 6}, {0x377, 1}, {0x200, 8}, {0x208, 8},\ + {0x060, 1}, {0x064, 1}, {0x062, 1}, {0x066, 1},\ + {0x02E, 1}, {0x02F, 1}, {0x04E, 1}, {0x04F, 1} + }; + UINT8 TableLength = sizeof(LpcIoStdDecode) / sizeof(LPC_IO_STD_DECODE); + UINT8 i; + UINT8 j; + UINT8 AddressMask; + UINT16 GenDecodeBase; + UINT16 GenDecodeLength = 0; + + DxeSvcTbl = (DXE_SERVICES*)GetEfiConfigurationTable(pST,&gDxeSvcTblGuid); + if(DxeSvcTbl == NULL) return EFI_NOT_AVAILABLE_YET; + + for (i = 0; i < TableLength; i++) { + + Status = DxeSvcTbl->AddIoSpace ( EfiGcdIoTypeIo,\ + LpcIoStdDecode[i].Address, \ + LpcIoStdDecode[i].Length ); + } + + for (i = 0; i < 4; i++) { + GenDecodeBase = READ_PCI16_SB(SB_REG_GEN1_DEC + i * 4) & 0xFFFC; + AddressMask = READ_PCI8_SB((SB_REG_GEN1_DEC + 2) + i * 4) & 0x00FC; + + if (GenDecodeBase == 0) continue; + + for (j = 2; j < 8; j++) { + if (AddressMask & (BIT00 << j)) GenDecodeLength += (BIT00 << j); + } + GenDecodeLength += 4; + + Status = DxeSvcTbl->AddIoSpace ( EfiGcdIoTypeIo,\ + GenDecodeBase, \ + GenDecodeLength ); + } + + return Status; +} + +//********************************************************************** + +BOOT_SCRIPT_SB_PCI_REG_SAVE gPciRegistersSave[] = { + SB_REG(SB_REG_PIRQ_A) , EfiBootScriptWidthUint32, 0xffffffff, // 0x60 The register will be filled in later. + SB_REG(SB_REG_PIRQ_E) , EfiBootScriptWidthUint32, 0xffffffff, // 0x68 The register will be filled in later. + SB_REG(SB_REG_LPC_IO_DEC) , EfiBootScriptWidthUint16, 0xffff, // 0x80 + SB_REG(SB_REG_LPC_EN) , EfiBootScriptWidthUint16, 0xffff, // 0x82 + SB_REG(SB_REG_GEN1_DEC) , EfiBootScriptWidthUint32, 0xffffffff, // 0x84 + SB_REG(SB_REG_GEN2_DEC) , EfiBootScriptWidthUint32, 0xffffffff, // 0x88 + SB_REG(SB_REG_GEN3_DEC) , EfiBootScriptWidthUint32, 0xffffffff, // 0x8C + SB_REG(SB_REG_GEN4_DEC) , EfiBootScriptWidthUint32, 0xffffffff, // 0x90 + SB_REG(SB_REG_GEN_PMCON_1) , EfiBootScriptWidthUint16, 0xffffffff, // 0xA0 + SB_REG(SB_REG_BIOS_CNTL) , EfiBootScriptWidthUint8, 0xffffffff, // 0xDC, + + PCIBR_REG(PCIBR_REG_PBUSN) , EfiBootScriptWidthUint32, 0xffffffff, // 0x18 + PCIBR_REG(PCIBR_REG_IOBASE) , EfiBootScriptWidthUint16, 0xffffffff, // 0x1C + PCIBR_REG(PCIBR_REG_MBASE) , EfiBootScriptWidthUint32, 0xffffffff, // 0x20 + PCIBR_REG(PCIBR_REG_PMBASE) , EfiBootScriptWidthUint32, 0xffffffff, // 0x24 + PCIBR_REG(PCIBR_REG_PMBASEU) , EfiBootScriptWidthUint32, 0xffffffff, // 0x28 + PCIBR_REG(PCIBR_REG_INTR_LN) , EfiBootScriptWidthUint8, 0xffffffff, // 0x3C + PCIBR_REG(PCIBR_REG_SPDH) , EfiBootScriptWidthUint16, 0xffffffff, // 0x40 + PCIBR_REG(PCIBR_REG_DTC) , EfiBootScriptWidthUint32, 0xffffffff, // 0x44 + PCIBR_REG(PCIBR_REG_BPC) , EfiBootScriptWidthUint32, 0xffffffff, // 0x4C + PCIBR_REG(PCIBR_REG_PCICMD) , EfiBootScriptWidthUint8, 0xffffffff, // 0x04 + + HDA_REG(R_PCH_HDA_HDBARL) , EfiBootScriptWidthUint32, 0xffffffff, // 0x10 + HDA_REG(R_PCH_HDA_HDBARU) , EfiBootScriptWidthUint32, 0xffffffff, // 0x14 + + SMBUS_REG(SMBUS_REG_MBASE0_ADDR), EfiBootScriptWidthUint32, 0xffffffff, // 0x10 + SMBUS_REG(SMBUS_REG_MBASE1_ADDR), EfiBootScriptWidthUint32, 0xffffffff, // 0x14 + SMBUS_REG(SMBUS_REG_BASE_ADDR) , EfiBootScriptWidthUint32, 0xffffffff, // 0x20 + SMBUS_REG(SMBUS_REG_INTR_LN) , EfiBootScriptWidthUint16, 0xffffffff, // 0x3C + SMBUS_REG(SMBUS_REG_PCICMD) , EfiBootScriptWidthUint16, 0xffffffff, // 0x04 + + THERMAL_REG(THERMAL_REG_TBAR) , EfiBootScriptWidthUint32, 0xffffffff, // 0x10 Thermal device is not getting restored, don't know why + THERMAL_REG(THERMAL_REG_PCICMD), EfiBootScriptWidthUint16, 0xffffffff, // 0x04 Thermal device is not getting restored, don't know why + THERMAL_REG(THERMAL_REG_INTR_LN), EfiBootScriptWidthUint32, 0xffffffff, // 0x3C Thermal device is not getting restored, don't know why +}; + +BOOT_SCRIPT_SB_PCI_REG_SAVE gSata1RegistersSave[] = { + SATA_REG(SATA_REG_MAP) , EfiBootScriptWidthUint8, 0xffffffff, // 0x90 + SATA_REG(SATA_REG_PCIPI) , EfiBootScriptWidthUint8, 0xffffffff, // 0x09 + SATA_REG(SATA_REG_INTR_LN) , EfiBootScriptWidthUint8, 0xffffffff, // 0x3c + SATA_REG(SATA_REG_IDETIM) , EfiBootScriptWidthUint32, 0xffffffff, // 0x40 + SATA_REG(SATA_REG_SIDETIM) , EfiBootScriptWidthUint8, 0xffffffff, // 0x44 + SATA_REG(SATA_REG_SDMACTL) , EfiBootScriptWidthUint8, 0xffffffff, // 0x48 + SATA_REG(SATA_REG_SDMATIM) , EfiBootScriptWidthUint16, 0xffffffff, // 0x4a + SATA_REG(SATA_REG_IDE_CONFIG), EfiBootScriptWidthUint32, 0xffffffff, // 0x54 + SATA_REG(SATA_REG_PMCS) , EfiBootScriptWidthUint16, 0xffffffff, // 0x74 + SATA_REG(SATA_REG_PCS) , EfiBootScriptWidthUint16, 0xffffffff, // 0x92 + SATA_REG(SATA_REG_PCMD_BAR) , EfiBootScriptWidthUint32, 0xffffffff, // 0x10 + SATA_REG(SATA_REG_PCNL_BAR) , EfiBootScriptWidthUint32, 0xffffffff, // 0x14 + SATA_REG(SATA_REG_SCMD_BAR) , EfiBootScriptWidthUint32, 0xffffffff, // 0x18 + SATA_REG(SATA_REG_SCNL_BAR) , EfiBootScriptWidthUint32, 0xffffffff, // 0x1c + SATA_REG(SATA_REG_BM_BASE) , EfiBootScriptWidthUint32, 0xffffffff, // 0x20 + SATA_REG(SATA_REG_ABAR) , EfiBootScriptWidthUint32, 0xffffffff, // 0x24 + SATA_REG(SATA_REG_PCICMD) , EfiBootScriptWidthUint8, 0xffffffff, // 0x04 +}; + +BOOT_SCRIPT_SB_PCI_REG_SAVE gSata2RegistersSave[] = { + SATA2_REG(SATA_REG_MAP) , EfiBootScriptWidthUint8, 0xffffffff, // 0x90 + SATA2_REG(SATA_REG_PCIPI) , EfiBootScriptWidthUint8, 0xffffffff, // 0x09 + SATA2_REG(SATA_REG_INTR_LN) , EfiBootScriptWidthUint8, 0xffffffff, // 0x3c + SATA2_REG(SATA_REG_IDETIM) , EfiBootScriptWidthUint32, 0xffffffff, // 0x40 + SATA2_REG(SATA_REG_SIDETIM) , EfiBootScriptWidthUint8, 0xffffffff, // 0x44 + SATA2_REG(SATA_REG_SDMACTL) , EfiBootScriptWidthUint8, 0xffffffff, // 0x48 + SATA2_REG(SATA_REG_SDMATIM) , EfiBootScriptWidthUint16, 0xffffffff, // 0x4a + SATA2_REG(SATA_REG_IDE_CONFIG), EfiBootScriptWidthUint32, 0xffffffff, // 0x54 + SATA2_REG(SATA_REG_PMCS) , EfiBootScriptWidthUint16, 0xffffffff, // 0x74 + SATA2_REG(SATA_REG_PCS) , EfiBootScriptWidthUint16, 0xffffffff, // 0x92 + SATA2_REG(SATA_REG_PCMD_BAR) , EfiBootScriptWidthUint32, 0xffffffff, // 0x10 + SATA2_REG(SATA_REG_PCNL_BAR) , EfiBootScriptWidthUint32, 0xffffffff, // 0x14 + SATA2_REG(SATA_REG_SCMD_BAR) , EfiBootScriptWidthUint32, 0xffffffff, // 0x18 + SATA2_REG(SATA_REG_SCNL_BAR) , EfiBootScriptWidthUint32, 0xffffffff, // 0x1c + SATA2_REG(SATA_REG_BM_BASE) , EfiBootScriptWidthUint32, 0xffffffff, // 0x20 + SATA2_REG(SATA_REG_ABAR) , EfiBootScriptWidthUint32, 0xffffffff, // 0x24 + SATA2_REG(SATA_REG_PCICMD) , EfiBootScriptWidthUint8, 0xffffffff, // 0x04 +}; + +#if defined AMIUSB_SUPPORT && AMIUSB_SUPPORT == 1 +VOID CheckDisableUsbControllers(VOID) +{ + UINT32 FunctionDisable; + EFI_STATUS Status; + EFI_GUID EfiGlobalVariableGuid = EFI_GLOBAL_VARIABLE; + UINTN BootOrderSize = 0; + UINT16 *BootOrder = NULL; + PCH_SERIES PchSeries = GetPchSeries(); + + Status = pBS->LocateProtocol( &gEfiUsbProtocolGuid, + NULL, + &gUsbProtocol ); + if (EFI_ERROR(Status)) return; + + if (gDisableAllUsbControllers) { + + Status = pRS->GetVariable( L"BootOrder", \ + &EfiGlobalVariableGuid, \ + NULL, \ + &BootOrderSize, \ + &BootOrder ); + if (Status == EFI_NOT_FOUND) return; + + // Shutdown legacy + gUsbProtocol->UsbRtShutDownLegacy(); + + WRITE_PCI16_EHCI(EHCI_REG_PCICMD, 0); + if (PchSeries != PchLp) { + WRITE_PCI16_EHCI2(EHCI_REG_PCICMD, 0); + } + WRITE_PCI16(XHCI_BUS, XHCI_DEV, XHCI_FUN, XHCI_REG_PCICMD, 0); + + FunctionDisable = (READ_MEM32_RCRB(RCRB_MMIO_FD) | BIT13 | BIT15 | BIT27); + WRITE_MEM32_RCRB_S3(gBootScript, RCRB_MMIO_FD, FunctionDisable); + }/* else if ((gSbSetupData->PchUsb20[0] == 0) && (gSbSetupData->PchUsb20[1] == 0)) { + WRITE_PCI16_EHCI(EHCI_REG_PCICMD, 0); + if (PchSeries != PchLp) { + WRITE_PCI16_EHCI2(EHCI_REG_PCICMD, 0); + } + FunctionDisable = (READ_MEM32_RCRB(RCRB_MMIO_FD) | BIT13 | BIT15); + WRITE_MEM32_RCRB_S3(gBootScript, RCRB_MMIO_FD, FunctionDisable); + }*/ +} +#endif + //(EIP124410)>> +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: UpdateSmbios136Table +// +// Description: Build and fill SmBios type 0x88 for CRID. +// +// Input: EFI_EVENT - Event, +// VOID - *Context +// +// Output: EFI_STATUS - EFI_SUCCESS. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +UpdateSmbios136Table( + IN EFI_EVENT Event, + IN VOID *Context +) +{ + EFI_STATUS Status; + EFI_MISC_OEM_TYPE_0x88 Data88; + DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy; + + Status = pBS->LocateProtocol(&gEfiSmbiosProtocolGuid, NULL, &gSmbiosProtocol); + if (EFI_ERROR(Status)) return; + + //Clear all data + pBS->SetMem (&Data88, sizeof(EFI_MISC_OEM_TYPE_0x88), 0); + + Data88.Header.Type = 0x88; + Data88.Header.Length = 6; + Data88.Header.Handle = 0; + + Status = pBS->LocateProtocol ( &gDxePchPlatformPolicyProtocolGuid, \ + NULL, \ + &PchPlatformPolicy); + if (!EFI_ERROR (Status)) { + if (PchPlatformPolicy->DeviceEnabling->Crid == 1){ + Data88.OemInfo = 0x5a5a; + } + } + + Status = gSmbiosProtocol->SmbiosAddStructure((UINT8 *)&Data88, sizeof(EFI_MISC_OEM_TYPE_0x88)); + + pBS->CloseEvent(Event); +} + //(EIP124410)<< +#if defined CSM_SUPPORT && CSM_SUPPORT == 1 // [EIP134850] >> +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SBSataRegSaveRestore +// +// Description: This callback will be called before and after installing legacy OpROM +// +// Input: +// IN EFI_EVENT Event - Callback event +// IN VOID *Context - pointer to calling context +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID SBSataRegSaveRestore( + IN EFI_EVENT Event, + IN VOID *Context +) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + UINTN Size = sizeof(EFI_HANDLE); + UINTN Seg, Bus, Dev, Fun; + UINT32 ABar, RegVal; + UINT8 Index = 0; + CSM_PLATFORM_POLICY_DATA *OpRomStartEndProtocol; + EFI_PCI_IO_PROTOCOL *PciIo; + PCH_SERIES PchSeries = GetPchSeries(); + + TRACE((TRACE_ALWAYS, "SBSataRegSaveRestore() !!!\n")); + Status = pBS->LocateHandle(ByRegisterNotify, NULL, SataOpRomRegistration, &Size, &Handle); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) return; + + Status = pBS->HandleProtocol(Handle, &OpRomStartEndProtocolGuid, &OpRomStartEndProtocol); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) return; + + if(OpRomStartEndProtocol != NULL) { + //pre-process OpROM callback + PciIo = OpRomStartEndProtocol->PciIo; + + if (PciIo == NULL){ + // this OpROM is not Intel SATA RAID OpROM + IsSataOpROM = 0; + return; + } + + PciIo->GetLocation(PciIo, &Seg, &Bus, &Dev, &Fun); + TRACE((TRACE_ALWAYS, "OpRom Location: Seg:%x, Bus:%x, Dev:%x, Fun:%x\n", Seg, Bus, Dev, Fun)); + if((Bus == SATA_BUS) && (Dev == SATA_DEV) && (Fun == SATA_FUN)){ + // This OpROM is Intel SATA RAID OpROM + TRACE((TRACE_ALWAYS, "Before execute SATA OpROM... save sata regs...\n")); + if (SaveSataReg != 0) return; + SaveSataReg = 1; + IsSataOpROM = 1; + DLAE = 0; + // Save PxCMD bit 25 of each Sata ports + ABar = READ_MMIO32(SATA_PCIE_REG(SATA_REG_ABAR)); + TRACE((TRACE_ALWAYS, "ABar = %x Index = %x MaxPortNumber = %x\n", ABar, Index, GetPchMaxSataPortNum())); + while(Index < GetPchMaxSataPortNum()){ + RegVal = READ_MMIO32((UINT64)(ABar + 0x118 + (0x80 * Index))); // R_PCH_SATA_AHCI_P0CMD + TRACE((TRACE_ALWAYS, "Index = %x, RegVal = %x\n", Index, RegVal)); + if ((RegVal != 0xFFFFFFFF) && (RegVal & BIT24)){ + DLAE |= (UINT8)((RegVal & BIT25) >> (25 - Index)); + } + Index++; + } + TRACE((TRACE_ALWAYS, "DLAE = %x\n", DLAE)); + } else { + // this OpROM is not Intel SATA RAID OpROM + IsSataOpROM = 0; + } + } else { + //post-process OpROM callback + if ((SaveSataReg == 1) && (IsSataOpROM == 1)){ + TRACE((TRACE_ALWAYS, "After execute SATA OpROM... restore sata regs...\n")); + // Restore PxCMD bit 25 of each Sata ports + ABar = READ_MMIO32(SATA_PCIE_REG(SATA_REG_ABAR)); + while(Index < GetPchMaxSataPortNum()){ + RegVal = READ_MMIO32((UINT64)(ABar + 0x118 + (0x80 * Index))); // R_PCH_SATA_AHCI_P0CMD + if(RegVal != 0xFFFFFFFF){ + if(DLAE & (BIT0 << Index)){ + RegVal |= BIT25; + WRITE_MMIO32((UINT64)(ABar + 0x118 + (0x80 * Index)), RegVal); + TRACE((TRACE_ALWAYS, "Sata Port %x restore done\n", Index)); + } + } + Index++; + } + } + } +} +#endif // [EIP134850] << + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitSbRegsBeforeBoot +// +// Description: This function can initialize any SB registers before DXE +// stage exiting. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID InitSbRegsBeforeBoot ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + UINT32 i, j; + UINT8 *SbRcba = (UINT8*)(UINTN)SB_RCRB_BASE_ADDRESS; + UINT32 Data32; + UINT32 PortImplemented = 0x0f; + UINT32 GlobalPchControl; + UINT64 AHCIBar = 0; +// UINT16 Offset; //[EIP124245] + UINT8 Data8; + UINT32 Index; + EFI_ACPI_SUPPORT_PROTOCOL *As; + FACP_20 *Table = NULL; + EFI_ACPI_TABLE_VERSION Version; + UINTN Handle; + ACPI_HDR *DsdtPtr = NULL; + EFI_STATUS Status; + PCH_SERIES PchSeries = GetPchSeries(); + + for (i = 0; i < sizeof(gPciRegistersSave)/ sizeof(BOOT_SCRIPT_SB_PCI_REG_SAVE); ++i) { + gPciRootBridgeIo->Pci.Read( \ + gPciRootBridgeIo, \ + gPciRegistersSave[i].Width, \ + gPciRegistersSave[i].Address, \ + 1, \ + &Data32); + + Data32 &= gPciRegistersSave[i].Mask; + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( \ + gBootScript, \ + gPciRegistersSave[i].Width, \ + gPciRegistersSave[i].Address, \ + 1, \ + &Data32); + } + if (PchSeries != PchLp) { + gPciRootBridgeIo->Pci.Read( \ + gPciRootBridgeIo, \ + EfiBootScriptWidthUint32, \ + SB_REG(SB_REG_GPI_ROUT) , \ + 1, \ + &Data32); + + Data32 &= 0xffffffff; + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( \ + gBootScript, \ + EfiBootScriptWidthUint32, \ + SB_REG(SB_REG_GPI_ROUT) , \ + 1, \ + &Data32); + }else{ + Data32 = IoRead32(GPIO_BASE_ADDRESS + GP_IOREG_GPI_ROUT2); + Data32 &= 0xffffffff; + BOOT_SCRIPT_S3_IO_WRITE_MACRO( \ + gBootScript, \ + EfiBootScriptWidthUint32, \ + GPIO_BASE_ADDRESS + GP_IOREG_GPI_ROUT2, \ + 1, \ + &Data32); + } + +#if defined (HOST_WLAN_PP_EN) && HOST_WLAN_PP_EN == 1 + + Data32 = READ_MEM32_RCRB(ICH_RCRB_PMCFG) | BIT04; // 0x3318 + WRITE_MEM32_RCRB (ICH_RCRB_PMCFG , Data32); + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( \ + gBootScript, \ + EfiBootScriptWidthUint32, \ + SbRcba + ICH_RCRB_PMCFG, \ + 1, \ + &Data32); + +#endif + + Data32 = READ_MEM32_RCRB(RCRB_MMIO_FD); // 0x3418 + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( \ + gBootScript, \ + EfiBootScriptWidthUint32, \ + SbRcba + R_PCH_RCRB_FUNC_DIS, \ + 1, \ + &Data32); + + // Trap Configuration + for (i = RCRB_MMIO_IO_TRAP_0; i < (RCRB_MMIO_IO_TRAP_3 + 8); i += 4) { + Data32 = *(UINT32 *)(SbRcba + i); + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( \ + gBootScript, \ + EfiBootScriptWidthUint32, \ + SbRcba + i, \ + 1, \ + &Data32); + } + + //RootPort register save + for(i = 0; i <= 7; i++) + { + gPciRootBridgeIo->Pci.Read ( + gPciRootBridgeIo, \ + EfiPciWidthUint32, \ + SB_PCI_CFG_ADDRESS(PCIEBRS_BUS, PCIEBRS_DEV, i, 0x00), \ + 1, \ + &Data32); + if(Data32 != 0xffffffff) + { + for(j = 0x18; j < 0x34; j += 4) + { + gPciRootBridgeIo->Pci.Read ( \ + gPciRootBridgeIo, \ + EfiPciWidthUint32, \ + SB_PCI_CFG_ADDRESS(PCIEBRS_BUS, PCIEBRS_DEV, i, j), \ + 1, \ + &Data32); + + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( \ + gBootScript, \ + EfiBootScriptWidthUint32, \ + SB_PCI_CFG_ADDRESS(PCIEBRS_BUS, PCIEBRS_DEV, i, j), \ + 1, \ + &Data32); + } + } + } + //End + +//Save Onboard LAN BAR- Efi aware Vista GBE bar is not restored by OS if network driver is not installed. + + gPciRootBridgeIo->Pci.Read ( \ + gPciRootBridgeIo, \ + EfiPciWidthUint32, \ + LAN_REG(0x00), \ + 1, \ + &Data32); + if(Data32 != 0xffffffff) + { + for(j = 0x10; j < 0x1B; j += 4) + { + gPciRootBridgeIo->Pci.Read ( \ + gPciRootBridgeIo, \ + EfiPciWidthUint32, \ + LAN_REG(j), \ + 1, \ + &Data32); + + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( + gBootScript, \ + EfiBootScriptWidthUint32, \ + LAN_REG(j), \ + 1, \ + &Data32); + } + } + +//Save Sata and ABAR S3 reg. + gPciRootBridgeIo->Pci.Read( \ + gPciRootBridgeIo, \ + EfiBootScriptWidthUint32, \ + SATA_REG(PCI_VID), \ + 1, \ + &Data32); + if (Data32 != 0xffffffff) { + for (i = 0; i < sizeof(gSata1RegistersSave)/ sizeof(BOOT_SCRIPT_SB_PCI_REG_SAVE); ++i) { + gPciRootBridgeIo->Pci.Read( \ + gPciRootBridgeIo, \ + gSata1RegistersSave[i].Width, \ + gSata1RegistersSave[i].Address, \ + 1, \ + &Data32); + Data32 &= gSata1RegistersSave[i].Mask; + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( + gBootScript, \ + gSata1RegistersSave[i].Width, \ + gSata1RegistersSave[i].Address, \ + 1, \ + &Data32); + } + + //If SATA is in AHCI or RAID Mode Save/Restore additional registers. + gPciRootBridgeIo->Pci.Read(gPciRootBridgeIo, EfiBootScriptWidthUint8, SATA_REG(SATA_REG_MAP), 1, &Data8); // 0x90 + if ( Data8 & 0xC0 ) { // AHCI or RAID + + gPciRootBridgeIo->Pci.Read(gPciRootBridgeIo, EfiBootScriptWidthUint32, SATA_REG(SATA_REG_ABAR), 1, &(UINT32)AHCIBar); // 0x24 + AHCIBar &= 0xFFFFFFF0; + + gPciRootBridgeIo->Mem.Read(gPciRootBridgeIo, EfiPciIoWidthUint32, AHCIBar + 0x04, 1, &GlobalPchControl); + BOOT_SCRIPT_S3_MEM_WRITE_MACRO(gBootScript, EfiBootScriptWidthUint32, AHCIBar + 0x04, 1, &GlobalPchControl); + + gPciRootBridgeIo->Mem.Read(gPciRootBridgeIo, EfiPciIoWidthUint32, AHCIBar + 0x0c, 1, &PortImplemented); + BOOT_SCRIPT_S3_MEM_WRITE_MACRO(gBootScript, EfiBootScriptWidthUint32, AHCIBar + 0xc, 1, &PortImplemented); + + + //[EIP124245]>> +/* for (i = 0, Offset = 0x100; i < 6 ; i++, Offset += 0x80) { + if ( PortImplemented & (BIT00 << i) ) { + gPciRootBridgeIo->Mem.Read(gPciRootBridgeIo, EfiPciIoWidthUint32, AHCIBar + Offset, 1, &Data32); + BOOT_SCRIPT_S3_MEM_WRITE_MACRO(gBootScript, EfiBootScriptWidthUint32, AHCIBar + Offset, 1, &Data32); + + gPciRootBridgeIo->Mem.Read(gPciRootBridgeIo, EfiPciIoWidthUint32, AHCIBar + Offset + 0x04, 1, &Data32); + BOOT_SCRIPT_S3_MEM_WRITE_MACRO(gBootScript, EfiBootScriptWidthUint32, AHCIBar + Offset + 0x04, 1, &Data32); + + gPciRootBridgeIo->Mem.Read(gPciRootBridgeIo, EfiPciIoWidthUint32, AHCIBar + Offset + 0x04, 1, &Data32); + BOOT_SCRIPT_S3_MEM_WRITE_MACRO(gBootScript, EfiBootScriptWidthUint32, AHCIBar + Offset + 0x04, 1, &Data32); + + gPciRootBridgeIo->Mem.Read(gPciRootBridgeIo, EfiPciIoWidthUint32, AHCIBar + Offset + 0x08, 1, &Data32); + BOOT_SCRIPT_S3_MEM_WRITE_MACRO(gBootScript, EfiBootScriptWidthUint32, AHCIBar + Offset + 0x08, 1, &Data32); + + gPciRootBridgeIo->Mem.Read(gPciRootBridgeIo, EfiPciIoWidthUint32, AHCIBar + Offset + 0x0c, 1, &Data32); + BOOT_SCRIPT_S3_MEM_WRITE_MACRO(gBootScript, EfiBootScriptWidthUint32, AHCIBar + Offset + 0x0c, 1, &Data32); + + gPciRootBridgeIo->Mem.Read(gPciRootBridgeIo, EfiPciIoWidthUint32, AHCIBar + Offset + 0x18, 1, &Data32); + Data32 &= 0xFFFFFFEE; //Make sure Clear the Start and FIS Receive Enable bit + BOOT_SCRIPT_S3_MEM_WRITE_MACRO(gBootScript, EfiBootScriptWidthUint32, AHCIBar + Offset + 0x18, 1, &Data32); + + gPciRootBridgeIo->Mem.Read(gPciRootBridgeIo, EfiPciIoWidthUint32, AHCIBar + Offset + 0x2c, 1, &Data32); + BOOT_SCRIPT_S3_MEM_WRITE_MACRO(gBootScript, EfiBootScriptWidthUint32, AHCIBar + Offset + 0x2c, 1, &Data32); + } + }*/ //[EIP124245]<< + + gPciRootBridgeIo->Mem.Read (gPciRootBridgeIo, EfiPciIoWidthUint32, AHCIBar, 1, &Data32); + BOOT_SCRIPT_S3_MEM_WRITE_MACRO(gBootScript, EfiBootScriptWidthUint32, AHCIBar,1,&Data32); + } + } // if SATA 1 = ffffffff + //(EIP126943)>> + //Controller in IDE Mode. Save/Restore Secondary SataController (B0:D1F:F5) Registers also. + + gPciRootBridgeIo->Pci.Read( + gPciRootBridgeIo, + EfiBootScriptWidthUint32, + SATA2_REG(0), + 1, + &Data32 + ); + if (Data32 != 0xFFFFFFFF) { + for (i = 0; i < sizeof(gSata2RegistersSave)/ sizeof(BOOT_SCRIPT_SB_PCI_REG_SAVE); ++i) { + gPciRootBridgeIo->Pci.Read( + gPciRootBridgeIo, + gSata2RegistersSave[i].Width, + gSata2RegistersSave[i].Address, + 1, + &Data32 + ); + Data32 &= gSata2RegistersSave[i].Mask; + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( + gBootScript, + gSata2RegistersSave[i].Width, + gSata2RegistersSave[i].Address, + 1, + &Data32 + ); + } + }// if SATA 2 = ffffffff //(EIP126943)<< + + + if (gErrorLoggingFlag == TRUE) { + Data8 = SW_SMI_SB_EL_S3; + WRITE_IO8(SW_SMI_IO_ADDRESS, Data8 ); + BOOT_SCRIPT_S3_IO_WRITE_MACRO( gBootScript, \ + EfiBootScriptWidthUint8, \ + SW_SMI_IO_ADDRESS, \ + 1, \ + &Data8); + } + +#if SB_SWSMI_WRITE_TO_BOOTSCRIPT + SBSwSmiWriteToBootScript(gBootScript); +#endif + +#if defined AMIUSB_SUPPORT && AMIUSB_SUPPORT == 1 + CheckDisableUsbControllers(); +#endif + //(EIP127410)>> + if (PchSeries == PchLp) { + WRITE_PCI16_SB(SB_REG_GEN_PMCON_1, (READ_PCI16_SB(SB_REG_GEN_PMCON_1) | 0x800)); + TRACE((TRACE_ALWAYS, "SB_REG_GEN_PMCON_1= %x\n", READ_PCI16_SB(SB_REG_GEN_PMCON_1))); + } + + Status = pBS->LocateProtocol(&gEfiAcpiSupportGuid, NULL, &As); + + // Find DSDT ACPI Table + for (Index = 0; Index < ACPI_RSDT_TABLE_NUM; Index++) { + Status = As->GetAcpiTable(As, Index, &Table, &Version, &Handle); + if (EFI_ERROR(Status)) break;//no more tables left + + if ((Table->Header.Signature == FACP_SIG) && (DsdtPtr == NULL)) { + DsdtPtr = (ACPI_HDR*)Table->DSDT; + TRACE((-1, "SBDxe: Found DSDT Table at 0x%08X\n", DsdtPtr)); + if (PchSeries == PchLp) { + ULTDsdtTableUpdate (DsdtPtr); + } else { + DsdtTableUpdate (DsdtPtr); + } + break; + } + } //(EIP127410)<< + + // + //Kill the Event + // + pBS->CloseEvent(Event); + +} + +#if defined AMIUSB_SUPPORT && AMIUSB_SUPPORT == 1 +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbUsbProtocolCallback +// +// Description: This callback function is called after USB Protocol is +// installed. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SbUsbProtocolCallback ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + EFI_STATUS Status = EFI_SUCCESS; + USB_SKIP_LIST SkipMassTable[] = { {1, 0, 0xff, 0, 0, 0x8}, + {0, 0, 0, 0, 0, 0 } + }; + + if (gDisableAllUsbControllers) + { + Status = pBS->LocateProtocol( &gEfiUsbProtocolGuid, + NULL, + &gUsbProtocol ); + if (EFI_ERROR(Status)) return; + gUsbProtocol->UsbCopySkipTable(SkipMassTable, sizeof(SkipMassTable)/sizeof (USB_SKIP_LIST)); + } + + pBS->CloseEvent(Event); +} +#endif + +#if SecureMod_SUPPORT +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: BiosLockEnableCallback +// +// Description: This callback function is called after AMI_EVENT_FLASH_WRITE_LOCK is +// installed. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID BiosLockEnableCallback ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + EFI_STATUS Status; + DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy; + + Status = pBS->LocateProtocol ( &gDxePchPlatformPolicyProtocolGuid, \ + NULL, \ + &PchPlatformPolicy); + if (!EFI_ERROR (Status)) { + if ((gSbSetupData->BiosLock == PCH_DEVICE_ENABLE) && + (PchPlatformPolicy->LockDownConfig->PchBiosLockIoTrapAddress != 0)) { + IoWrite32 (PchPlatformPolicy->LockDownConfig->PchBiosLockIoTrapAddress, PCH_BWP_SIGNATURE); + } + } + + pBS->CloseEvent(Event); +} +#endif + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure : LocatePublishIdeSataAcpiTables +// +// Description : This function will locate and publish the IDE.asl or SATA.asl +// depending upon the mode IDE/AHCI. +// +// Input :None +// +// Output :None +// +//<AMI_PHDR_END> +//********************************************************************** +VOID LocatePublishIdeSataAcpiTables(VOID) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + EFI_FV_FILETYPE FileType; + UINT32 FvStatus; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINTN Size; + UINTN k; + EFI_FIRMWARE_VOLUME_PROTOCOL *FwVol = NULL; + INTN Instance; + EFI_ACPI_TABLE_VERSION Version; + EFI_ACPI_COMMON_HEADER *CurrentTable; + UINTN AcpiTableHandle; + ACPI_HDR *AcpiTable = NULL; + ACPI_HDR *TableHeader; + UINT8 Data; + EFI_ACPI_SUPPORT_PROTOCOL *AcpiSupport =0; + BOOLEAN AhciFlag = FALSE; + + //Locate the PcirootbridgeIoprotocol + Status = pBS->LocateProtocol(&gEfiPciRootBridgeIoProtocolGuid, NULL, &gPciRootBridgeIo); + ASSERT_EFI_ERROR(Status); + + //Read the Sub class code register to check for ide/Ahci mode. + Data = READ_PCI8_SATA(R_PCH_SATA_SUB_CLASS_CODE); + + if (Data == V_PCH_SATA_SUB_CLASS_CODE_AHCI || \ + Data == V_PCH_SATA_SUB_CLASS_CODE_RAID) + AhciFlag = TRUE; + // + // Locate protocol. + // There is little chance we can't find an FV protocol + // + Status = pBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolumeProtocolGuid, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + ASSERT_EFI_ERROR (Status); + + // + // Looking for FV with ACPI storage file + // + for (k = 0; k < NumberOfHandles; k++) { + // + // Get the protocol on this handle + // This should not fail because of LocateHandleBuffer + // + Status = pBS->HandleProtocol ( + HandleBuffer[k], + &gEfiFirmwareVolumeProtocolGuid, + &FwVol + ); + ASSERT_EFI_ERROR (Status); + + // + // See if it has the ACPI storage file + // + Size = 0; + FvStatus = 0; + Status = FwVol->ReadFile ( + FwVol, + &IdeSataAcpiTableStorageGuid, + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + // + // If we found it, then we are done + // + if (Status == EFI_SUCCESS) { + break; + } + } + + // + // Our exit status is determined by the success of the previous operations + // If the protocol was found, Instance already points to it. + // + // + // Free any allocated buffers + // + pBS->FreePool (HandleBuffer); + + // + // Sanity check that we found our data file + // + ASSERT (FwVol); + + // + // By default, a table belongs in all ACPI table versions published. + // + Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0; + + // + // Find the AcpiSupport protocol + // + Status = LocateSBSATAIDESupportProtocol ( + &gEfiAcpiSupportGuid, + &AcpiSupport, + FALSE + ); + ASSERT_EFI_ERROR (Status); + // + // Read tables from the storage file. + // + Instance = 0; + CurrentTable = NULL; + + while (Status == EFI_SUCCESS) { + Status = FwVol->ReadSection ( + FwVol, + &IdeSataAcpiTableStorageGuid, + EFI_SECTION_RAW, + Instance, + &CurrentTable, + &Size, + &FvStatus + ); + + if (!EFI_ERROR (Status)) { + // + // Check the table ID to modify the table + // + TableHeader = (ACPI_HDR *) CurrentTable; + + if(AhciFlag) { + //AHCI mode is Enabled + //Locate and publish ACPItable for SATA.asl + + if (MemCmp (&TableHeader->OemTblId, "SataTabl", 8) == 0) { + AcpiTable = (ACPI_HDR*) CurrentTable; + } + } else { + //AHCI mode is Disabled + //Locate and publish ACPItable for Ide.asl + if (MemCmp (&TableHeader->OemTblId, "IdeTable", 8) == 0) { + AcpiTable = (ACPI_HDR*) CurrentTable; + } + } + // + // Increment the instance + // + Instance++; + CurrentTable = NULL; + } + } + + // + // Update the SSDT table in the ACPI tables. + // + AcpiTableHandle = 0; + + Status = AcpiSupport->SetAcpiTable (AcpiSupport, AcpiTable, TRUE, Version, &AcpiTableHandle); + ASSERT_EFI_ERROR (Status); + pBS->FreePool (AcpiTable); + + // + // Publish all ACPI Tables + // + Status = AcpiSupport->PublishTables (AcpiSupport, Version); + ASSERT_EFI_ERROR (Status); + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: LocateSBSATAIDESupportProtocol +// +// Description: Locate the first instance of a protocol. If the protocol requested is an +// FV protocol, then it will return the first FV that contains the ACPI table +// storage file. +// +// Input: Protocol The protocol to find. +// Instance Return pointer to the first instance of the protocol +// Type TRUE if the desired protocol is a FV protocol +// +// Output: EFI_SUCCESS The function completed successfully. +// EFI_NOT_FOUND The protocol could not be located. +// EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +LocateSBSATAIDESupportProtocol ( + IN EFI_GUID *Protocol, + OUT VOID **Instance, + IN BOOLEAN Type + ) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + EFI_FV_FILETYPE FileType; + UINT32 FvStatus; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINTN Size; + UINTN i; + + FvStatus = 0; + // + // Locate protocol. + // + Status = pBS->LocateHandleBuffer ( + ByProtocol, + Protocol, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + // + // Defined errors at this time are not found and out of resources. + // + return Status; + } + // + // Looking for FV with ACPI storage file + // + for (i = 0; i < NumberOfHandles; i++) { + // + // Get the protocol on this handle + // This should not fail because of LocateHandleBuffer + // + Status = pBS->HandleProtocol ( + HandleBuffer[i], + Protocol, + Instance + ); + ASSERT (!EFI_ERROR (Status)); + + if (!Type) { + // + // Not looking for the FV protocol, so find the first instance of the + // protocol. There should not be any errors because our handle buffer + // should always contain at least one or LocateHandleBuffer would have + // returned not found. + // + break; + } + + // + // See if it has the ACPI storage file + // + Status = ((EFI_FIRMWARE_VOLUME_PROTOCOL *) (*Instance))->ReadFile ( + *Instance, + &IdeSataAcpiTableStorageGuid, + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + // + // If we found it, then we are done + // + if (Status == EFI_SUCCESS) { + break; + } + } + + // + // Our exit status is determined by the success of the previous operations + // If the protocol was found, Instance already points to it. + // + + // + // Free any allocated buffers + // + pBS->FreePool (HandleBuffer); + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitSbRegsBeforeLagecyBoot +// +// Description: This function can initialize any SB registers before legacy +// OS booting. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID InitSbRegsBeforeLagecyBoot ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + pBS->CloseEvent(Event); +} + +#if defined OEM_USB_PER_PORT_DISABLE_SUPPORT && OEM_USB_PER_PORT_DISABLE_SUPPORT == 1 +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: DisableRmhDownPort +// +// Description: +// +// Input: EFI_USB_IO_PROTOCOL - *UsbIo +// UINT8 - Port +// +// Output: EFI_STATUS Status +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS DisableRmhDownPort ( + IN EFI_USB_IO_PROTOCOL *UsbIo, + IN UINT8 Port +) +{ + EFI_STATUS Status; + EFI_USB_DEVICE_REQUEST DevReq; + UINT32 Timeout; + UINT32 UsbStatus; + + DevReq.RequestType = 0x23; + DevReq.Request = 0x01; + DevReq.Value = 0x1; + DevReq.Index = Port; + DevReq.Length = 0; + Timeout = 3000; + Status = UsbIo->UsbControlTransfer(UsbIo, &DevReq, + EfiUsbNoData, Timeout, NULL, 0, &UsbStatus); + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: USBPrePortDisableCallback +// +// Description: This function can disable USB preport before OS booting. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID USBPrePortDisableCallback ( + IN EFI_EVENT Event, + IN VOID *Context +) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + EFI_GUID EfiUsbIoProtocolGuid = EFI_USB_IO_PROTOCOL_GUID; + UINTN HandleCount = 0; + PCH_SERIES PchSeries = GetPchSeries(); + EFI_USB_IO_PROTOCOL *UsbIo; + EFI_USB_IO_PROTOCOL *Ehci1RmhUsbIo = NULL; + EFI_USB_IO_PROTOCOL *Ehci2RmhUsbIo = NULL; + EFI_USB_DEVICE_DESCRIPTOR DevDesc = {0}; + UINT32 Index; + UINT8 EHCIPort1 = 0; + UINT8 EHCIPort2 = 0; + UINT8 XhciPortDisableFlage[21]; + UINT32 XhciUsb2Pdo = 0; + UINT32 XhciUsb3Pdo = 0; + UINT32 XhciIndex; + UINT16 RegData16; + UINT32 XhciUsb2InternalPortNumberLookUpTable[] = {0,1,2,3,8,9,12,13,4,5,6,7,10,11,12,13}; + static BOOLEAN USBPrePortDisableDone = FALSE; + + /// + /// Table: USB2 Pins Mapping between XHCI/EHCI Port + /// ------------------------------------------- + /// | USB2 Pin | EHCI Port | XHCI Port | + /// |--------------+----------------+-----------| + /// | USB[P,N][0] | EHCI 1 Port 0 | Port 0 | + /// | USB[P,N][1] | EHCI 1 Port 1 | Port 1 | + /// | USB[P,N][2] | EHCI 1 Port 2 | Port 2 | + /// | USB[P,N][3] | EHCI 1 Port 3 | Port 3 | + /// | USB[P,N][4] | EHCI 1 Port 4 | Port 8 | + /// | USB[P,N][5] | EHCI 1 Port 5 | Port 9 | + /// | USB[P,N][6] | EHCI 1 Port 6 | Port 12 | + /// | USB[P,N][7] | EHCI 1 Port 7 | Port 13 | + /// | USB[P,N][8] | EHCI 2 Port 8 | Port 4 | + /// | USB[P,N][9] | EHCI 2 Port 9 | Port 5 | + /// | USB[P,N][10] | EHCI 2 Port 10 | Port 6 | + /// | USB[P,N][11] | EHCI 2 Port 11 | Port 7 | + /// | USB[P,N][12] | EHCI 2 Port 12 | Port 10 | + /// | USB[P,N][13] | EHCI 2 Port 13 | Port 11 | + /// ------------------------------------------- + /// + + //Make sure the processing is performed only once. + if (USBPrePortDisableDone){ + pBS->CloseEvent(Event); + return; + } + + TRACE((-1, "OEM_USB_PER_PORT_DISABLE_SUPPORT - Start\n")); + + // Locate handle buffer for USB Io Protocol + Status = pBS->LocateHandleBuffer( ByProtocol, + &EfiUsbIoProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer); + if (EFI_ERROR(Status)){ + TRACE((-1, "ERROR: Cannot Locate handle buffer for USB Io Protocol !!!\n")); + } else { + TRACE((-1, "USB Io Protocol user are %d Handles!!!\n", HandleCount)); + } + + // Initial Xhci Port Disable Flage + // for PCH-LP + // Index: 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 + // SS/HS: HS HS HS HS HS HS HS HS HS xx SS SS SS SS + // for PCH-H + // SS/HS: HS HS HS HS HS HS HS HS HS HS HS HS HS HS xx SS SS SS SS SS SS + for (Index=0;Index<21;Index++) XhciPortDisableFlage[Index] = 0; + + for ( Index=0; Index < HandleCount; Index++ ) { + pBS->HandleProtocol(HandleBuffer[Index], &gEfiUsbIoProtocolGuid, &UsbIo); + Status = UsbIo->UsbGetDeviceDescriptor(UsbIo, &DevDesc); + if (EFI_ERROR(Status)) { + continue; + } + if (DevDesc.IdVendor != 0x8087) { + continue; + } + switch (DevDesc.IdProduct) { + case 0x8000: + Ehci1RmhUsbIo = UsbIo; + break; + case 0x8008: + Ehci2RmhUsbIo = UsbIo; + break; + default: + break; + } // switch + } // for loop + +// Intel_RC >>> + if (gSbSetupData->PchUsbPerPortCtl == PCH_DEVICE_ENABLE){ + /// + /// Open the Per-Port Disable Control Override + /// + + RegData16 = IoRead16 ((UINTN) ((UINT64) (PM_BASE_ADDRESS + R_PCH_UPRWC))); + RegData16 |= B_PCH_UPRWC_WR_EN; + IoWrite16 ((UINTN) ((UINT64) (PM_BASE_ADDRESS + R_PCH_UPRWC)), RegData16); + + /// + /// To support RapidStart resume from G3 state, all resume well registers need to be saved + /// into S3 Script table. + /// + BOOT_SCRIPT_S3_IO_WRITE_MACRO ( gBootScript, + EfiBootScriptWidthUint16, + (PM_BASE_ADDRESS + R_PCH_UPRWC), + 1, + &RegData16); + + for (Index = 0; Index < GetPchUsbMaxPhysicalPortNum (); Index++) { + if ((Index < 8) && (gSbSetupData->PchUsb20[0] == PCH_DEVICE_ENABLE) && (gSbSetupData->PchUsb30Mode != 1)) { + /// + /// EHCI1 PDO for Port 0 to 7 + /// + if (gSbSetupData->PchUsbPort[Index] == PCH_DEVICE_DISABLE) { + EHCIPort1 |= B_PCH_EHCI_PDO_DIS_PORT0 << Index; + if (Ehci1RmhUsbIo != NULL) { + DisableRmhDownPort(Ehci1RmhUsbIo, (Index + 1)); + } + } else { + EHCIPort1 &= ~(B_PCH_EHCI_PDO_DIS_PORT0 << Index); + } + } // EHCI1 PDO + if (PchSeries == PchH) { + if ((Index >= 8) && (Index < 14) && (gSbSetupData->PchUsb20[1] == PCH_DEVICE_ENABLE) && (gSbSetupData->PchUsb30Mode != 1)) { + /// + /// EHCI2 PDO for Port 8 to 13 + /// + if (gSbSetupData->PchUsbPort[Index] == PCH_DEVICE_DISABLE) { + EHCIPort2 |= B_PCH_EHCI_PDO_DIS_PORT0 << (Index - 8); + if (Ehci1RmhUsbIo != NULL) { + DisableRmhDownPort(Ehci2RmhUsbIo, (Index - 7)); + } + } else { + EHCIPort2 &= ~(B_PCH_EHCI_PDO_DIS_PORT0 << (Index - 8)); + } + } // EHCI2 PDO + } // PchSeries == PchH + } // for loop + + if((gSbSetupData->PchUsb20[0] == PCH_DEVICE_ENABLE) && (gSbSetupData->PchUsb30Mode != 1)){ + /// + /// To support RapidStart resume from G3 state, all resume well registers need to be saved + /// into S3 Script table. + /// + TRACE((-1, "Write back Ehci1 PDO value: %x to PDO register\n", EHCIPort1)); + WRITE_PCI8 (0, 29, 0, R_PCH_EHCI_PDO, EHCIPort1); + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( gBootScript, + EfiBootScriptWidthUint32, + SB_PCI_CFG_ADDRESS(0, 29, 0, R_PCH_EHCI_PDO), + 1, + &EHCIPort1); + + if (PchSeries == PchH && (gSbSetupData->PchUsb20[1] == PCH_DEVICE_ENABLE)) { + TRACE((-1, "Write back Ehci2 PDO value: %x to PDO register\n", EHCIPort2)); + WRITE_PCI8 (0, 26, 0, R_PCH_EHCI_PDO, EHCIPort2); + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( gBootScript, + EfiBootScriptWidthUint32, + SB_PCI_CFG_ADDRESS(0, 26, 0, R_PCH_EHCI_PDO), + 1, + &EHCIPort2); + } // PchSeries == PchH && Echi2 enable + } // Echi1 enable + + if (gSbSetupData->PchUsb30Mode != 0){ + for (Index = 0; Index < GetPchUsbMaxPhysicalPortNum (); Index++) { + XhciIndex = Index; + if (PchSeries == PchH) { + /// + /// Translate physical pins to internal ports numbering + /// + XhciIndex = XhciUsb2InternalPortNumberLookUpTable[Index]; + } + if (gSbSetupData->PchUsbPort[Index] == PCH_DEVICE_DISABLE) { + XhciUsb2Pdo |= (UINT32) (B_PCH_XHCI_USB2PDO_DIS_PORT0 << XhciIndex); + XhciPortDisableFlage[XhciIndex] |= 1; + } else { + XhciUsb2Pdo &= (UINT32)~(B_PCH_XHCI_USB2PDO_DIS_PORT0 << XhciIndex); + } // XCHI PDO + } // for loop + + /// + /// XHCI PDO for SS + /// + for (Index = 0; Index < GetPchXhciMaxUsb3PortNum (); Index++) { + if (gSbSetupData->PchUsb30Port[Index] == PCH_DEVICE_DISABLE) { + XhciUsb3Pdo |= (UINT32) (B_PCH_XHCI_USB3PDO_DIS_PORT0 << Index); + if (PchSeries == PchH){ + XhciPortDisableFlage[Index + 15] |= 1; + } else { + XhciPortDisableFlage[Index + 10] |= 1; + } // PCH sku + } else { + XhciUsb3Pdo &= (UINT32)~(B_PCH_XHCI_USB3PDO_DIS_PORT0 << Index); + } // XHCI PDO + } // for loop + /// + /// USB2PDO and USB3PDO are Write-Once registers and bits in them are in the SUS Well. + /// + TRACE((-1, "Write back Xhci HS PDO value: %x to HS PDO register\n", XhciUsb2Pdo)); + WRITE_PCI32(0, 20, 0, R_PCH_XHCI_USB2PDO, XhciUsb2Pdo); + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( gBootScript, + EfiBootScriptWidthUint32, + SB_PCI_CFG_ADDRESS(0, 20, 0, R_PCH_XHCI_USB2PDO), + 1, + &XhciUsb2Pdo); + + TRACE((-1, "Write back Xhci SS PDO value: %x to SS PDO register\n", XhciUsb3Pdo)); + WRITE_PCI32(0, 20, 0, R_PCH_XHCI_USB3PDO, XhciUsb3Pdo); + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( gBootScript, + EfiBootScriptWidthUint32, + SB_PCI_CFG_ADDRESS(0, 20, 0, R_PCH_XHCI_USB3PDO), + 1, + &XhciUsb3Pdo); + + /// + /// Close the Per-Port Disable Control Override + /// + + RegData16 &= (~B_PCH_UPRWC_WR_EN); + IoWrite16 ((UINTN) ((UINT64) (PM_BASE_ADDRESS + R_PCH_UPRWC)), RegData16); + + /// + /// To support RapidStart resume from G3 state, all resume well registers need to be saved + /// into S3 Script table. + /// + + BOOT_SCRIPT_S3_IO_WRITE_MACRO ( gBootScript, + EfiBootScriptWidthUint16, + (PM_BASE_ADDRESS + R_PCH_UPRWC), + 1, + &RegData16); + } // gSbSetupData->PchUsb30Mode != 0 + } // gSbSetupData->PchUsbPerPortCtl == PCH_DEVICE_ENABLE +// Intel_RC <<< +// Disable usb port under Xhci controller >>> +{ + UINT8 counter; + UINT32 RegVal; + UINT64 XhciBar; + + // Read back Xhci MMIO addrss + if ((MmPciRead32(XHCI_BUS, XHCI_DEV, XHCI_FUN, R_PCH_XHCI_MEM_BASE) & 0x6) == 0x4){ + XhciBar = (((UINT64) MmPciRead32(XHCI_BUS, XHCI_DEV, XHCI_FUN, R_PCH_XHCI_MEM_BASE + 4) << 32) | + ((UINT64) MmPciRead32(XHCI_BUS, XHCI_DEV, XHCI_FUN, R_PCH_XHCI_MEM_BASE) & (~0x0F))); + } else { + XhciBar = MmPciRead32(XHCI_BUS, XHCI_DEV, XHCI_FUN, R_PCH_XHCI_MEM_BASE) & (~0x0F); + } + TRACE((-1, "Xhci Bar = %x\n", XhciBar)); + + // Disable Xhci port which are disconnected + for(Index=0;Index<21;Index++){ + if (XhciPortDisableFlage[Index] != 0){ + TRACE((-1, "Disable port%d under Xhci controller(start number:1)\n", (Index + 1))); + if (PchSeries ==PchLp){ + // for PCH-LP + // Index: 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 + // SS/HS: HS HS HS HS HS HS HS HS HS xx SS SS SS SS + TRACE((-1, "this PCH is ULT sku\n")); + if (Index > 13) break; + + if (Index < 9){ + //HS port + RegVal = MmioRead32(XhciBar + R_PCH_XHCI_PORTSC01USB2 + 0x10 * Index); + if (RegVal & B_PCH_XHCI_PORTSCXUSB2_PED){ + RegVal = (B_PCH_XHCI_PORTSCXUSB2_PED | B_PCH_XHCI_PORTSCXUSB2_PP); + MmioWrite32((XhciBar + R_PCH_XHCI_PORTSC01USB2 + 0x10 * Index), RegVal); + for(counter=0;counter<200;counter++){ + RegVal = MmioRead32(XhciBar + R_PCH_XHCI_PORTSC01USB2 + 0x10 * Index); + if(!(RegVal & B_PCH_XHCI_PORTSCXUSB2_PED)) break; + pBS->Stall(100); + } // for loop + } // PED bit is enable + } else { + //SS port + RegVal = MmioRead32(XhciBar + R_PCH_LP_XHCI_PORTSC1USB3 + 0x10 * Index); + if (RegVal & B_PCH_XHCI_PORTSCXUSB3_PED){ + RegVal = (B_PCH_XHCI_PORTSCXUSB3_PR | B_PCH_XHCI_PORTSCXUSB3_PP); + MmioWrite32((XhciBar + R_PCH_LP_XHCI_PORTSC1USB3 + 0x10 * Index), RegVal); + for(counter=0;counter<3000;counter++){ + RegVal = MmioRead32(XhciBar + R_PCH_LP_XHCI_PORTSC1USB3 + 0x10 * Index); + if(RegVal & B_PCH_XHCI_PORTSCXUSB3_PRC) break; + pBS->Stall(100); + } // for loop + + // Clear Warm Port Reset Change and Port Reset Change bits + //RegVal = (B_PCH_XHCI_PORTSCXUSB3_WRC | B_PCH_XHCI_PORTSCXUSB3_PRC | B_PCH_XHCI_PORTSCXUSB3_PP); + //MmioWrite32((XhciBar + R_PCH_LP_XHCI_PORTSC1USB3 + 0x10 * Index), RegVal); + } // PED bit is enable + }// SS/HS port + } else { + // for PCH-H + // Index: 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 + // SS/HS: HS HS HS HS HS HS HS HS HS HS HS HS HS HS xx SS SS SS SS SS SS + TRACE((-1, "this PCH is MB/DT sku\n")); + if (Index < 14){ + //HS port + RegVal = MmioRead32(XhciBar + R_PCH_XHCI_PORTSC01USB2 + 0x10 * Index); + if (RegVal & B_PCH_XHCI_PORTSCXUSB2_PED){ + RegVal = (B_PCH_XHCI_PORTSCXUSB2_PED | B_PCH_XHCI_PORTSCXUSB2_PP); + MmioWrite32((XhciBar + R_PCH_XHCI_PORTSC01USB2 + 0x10 * Index), RegVal); + for(counter=0;counter<200;counter++){ + RegVal = MmioRead32(XhciBar + R_PCH_XHCI_PORTSC01USB2 + 0x10 * Index); + if(!(RegVal & B_PCH_XHCI_PORTSCXUSB2_PED)) break; + pBS->Stall(100); + } // for loop + } // PED bit is enable + } else { + //SS port + RegVal = MmioRead32(XhciBar + R_PCH_H_XHCI_PORTSC1USB3 + 0x10 * Index); + if (RegVal & B_PCH_XHCI_PORTSCXUSB3_PED){ + RegVal = (B_PCH_XHCI_PORTSCXUSB3_PR | B_PCH_XHCI_PORTSCXUSB3_PP); + MmioWrite32((XhciBar + R_PCH_H_XHCI_PORTSC1USB3 + 0x10 * Index), RegVal); + for(counter=0;counter<3000;counter++){ + RegVal = MmioRead32(XhciBar + R_PCH_H_XHCI_PORTSC1USB3 + 0x10 * Index); + if(RegVal & B_PCH_XHCI_PORTSCXUSB3_PRC) break; + pBS->Stall(100); + } // for loop + + // Clear Warm Port Reset Change and Port Reset Change bits + //RegVal = (B_PCH_XHCI_PORTSCXUSB3_WRC | B_PCH_XHCI_PORTSCXUSB3_PRC | B_PCH_XHCI_PORTSCXUSB3_PP); + //MmioWrite32((XhciBar + R_PCH_H_XHCI_PORTSC1USB3 + 0x10 * Index), RegVal); + } // PED bit is enable + } // SS/HS port + } // PCH sku + } // XhciPortDisableFlage[counter] != 0 + } // for loop + + pBS->FreePool(HandleBuffer); +} +// Disable usb port under Xhci controller <<< + + USBPrePortDisableDone = TRUE; + TRACE((-1, "OEM_USB_PER_PORT_DISABLE_SUPPORT - End\n")); + pBS->CloseEvent(Event); +} +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbSetupNvramUpdatedCallback +// +// Description: This callback function is called after Setup NVRAM variable +// being updated. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SbSetupNvramUpdatedCallback ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + EFI_STATUS Status; + SB_SETUP_DATA *SetupData = NULL; + UINTN VariableSize = sizeof(SB_SETUP_DATA); + + Status = pBS->AllocatePool( EfiBootServicesData, \ + VariableSize, \ + &SetupData ); + ASSERT_EFI_ERROR(Status); + + GetSbSetupData( pRS, SetupData, FALSE ); + + // Free memory used for setup data + pBS->FreePool( SetupData ); + + pBS->CloseEvent(Event); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbExitPmAuthProtocolCallback +// +// Description: This callback function is called after Setup NVRAM variable +// being updated. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SbExitPmAuthProtocolCallback ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + EFI_STATUS Status; + // [EIP120623]> + UINT8 Data8; + // <[EIP120623] +// [ EIP357393 ]->>> +// UINT32 Data32; +// UINT32 i; +// UINT32 SpiRegister[] = { +// R_PCH_SPI_SSFS, +// R_PCH_SPI_PREOP, +// R_PCH_SPI_OPMENU, +// R_PCH_SPI_OPMENU + 4, +// R_PCH_SPI_VSCC1, +// R_PCH_SPI_VSCC0 +// }; +// [ EIP357393 ]-<<< + VOID *ProtocolPointer; + UINT32 SmiEn; + UINT16 Pm1Sts; + PCH_SERIES PchSeries = GetPchSeries(); + + // + // Check whether this is real ExitPmAuth notification, or just a SignalEvent + // + Status = pBS->LocateProtocol (&gExitPmAuthProtocolGuid, NULL, &ProtocolPointer); + if (EFI_ERROR (Status)) return; + + // + // Save SPI Registers for S3 resume usage + // +// [ EIP357393 ]->>> +// for (i = 0; i < sizeof (SpiRegister) / sizeof (UINT32); i++) { +// Data32 = READ_MEM32_RCRB (SpiRegister[i]); +// BOOT_SCRIPT_S3_MEM_WRITE_MACRO( gBootScript, \ +// EfiBootScriptWidthUint32, \ +// SB_RCRB_BASE_ADDRESS + SpiRegister[i], \ +// 1, \ +// &Data32 +// ); +// } +// [ EIP357393 ]-<<< + + // [EIP120623]> + Data8 = IoRead8 (PM_BASE_ADDRESS + ACPI_IOREG_PM1_CNTL); //0x04 + Data8 |= B_PCH_ACPI_PM1_CNT_SCI_EN; + + BOOT_SCRIPT_S3_IO_WRITE_MACRO ( \ + gBootScript, \ + EfiBootScriptWidthUint8, \ + PM_BASE_ADDRESS + ACPI_IOREG_PM1_CNTL, \ + 1, \ + &Data8); + // <[EIP120623] + + SmiEn = IoRead32 (PM_BASE_ADDRESS + ACPI_IOREG_SMI_EN); //0x30 + SmiEn &= ~B_PCH_SMI_EN_SWSMI_TMR; + // [EIP76432]>> +#if defined EMUL6064_SUPPORT && EMUL6064_SUPPORT == 1 + SmiEn &= ~B_PCH_SMI_EN_LEGACY_USB; +#endif + // <<[EIP76432] + BOOT_SCRIPT_S3_IO_WRITE_MACRO ( \ + gBootScript, \ + EfiBootScriptWidthUint32, \ + PM_BASE_ADDRESS + ACPI_IOREG_SMI_EN, \ + 1, \ + &SmiEn); + // [EIP92011] >> + if (PchSeries != PchLp) { + SmiEn = IoRead16 (PM_BASE_ADDRESS + ACPI_IOREG_ALTGP_SMI_EN); // Alternate GPI SMI Enable Reg. + //0x38 + BOOT_SCRIPT_S3_IO_WRITE_MACRO ( \ + gBootScript, \ + EfiBootScriptWidthUint16, \ + PM_BASE_ADDRESS + ACPI_IOREG_ALTGP_SMI_EN, \ + 1, \ + &SmiEn); + }else{ + SmiEn = IoRead16 (GPIO_BASE_ADDRESS + GP_IOREG_ALTGP_SMI_EN); // Alternate GPI SMI Enable Reg. + //0x54 + BOOT_SCRIPT_S3_IO_WRITE_MACRO ( \ + gBootScript, \ + EfiBootScriptWidthUint16, \ + GPIO_BASE_ADDRESS + GP_IOREG_ALTGP_SMI_EN, \ + 1, \ + &SmiEn); + } + //[EIP92011] << + + // Clear bus master status bit on S3 resume + Pm1Sts = B_PCH_ACPI_PM1_STS_BM; + //0x00 + BOOT_SCRIPT_S3_IO_WRITE_MACRO ( \ + gBootScript, \ + EfiBootScriptWidthUint16, \ + PM_BASE_ADDRESS + ACPI_IOREG_PM1_STS, \ + 1, \ + &Pm1Sts); +/* // [ EIP357393 ]->>> + // EIP167087 >>> + TRACE((-1, "Programming SPI Protected Range registers")); + Status = SbFlashProtectedRange(); + TRACE((-1, " %r !!!\n", Status)); + ASSERT_EFI_ERROR(Status); + + // Write SPI Protected Range registers to S3 script + for(i=0;i<5;i++){ + Data32 = READ_MEM32_RCRB(SPI_BASE_ADDRESS + (R_SB_RCRB_SPI_PR0 + (i * 4))); + TRACE((-1, "PR%d value @ %x: %x\n", i, (SB_RCBA + SPI_BASE_ADDRESS + (R_SB_RCRB_SPI_PR0 + (i * 4))), Data32)); + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( gBootScript, \ + EfiBootScriptWidthUint32, \ + SB_RCBA + SPI_BASE_ADDRESS + (R_SB_RCRB_SPI_PR0 + (i * 4)), \ + 1, \ + &Data32 + ); + } + // EIP167087 <<< +*/ // [ EIP357393 ]-<<< + + pBS->CloseEvent(Event); +} + + +// [ EIP357393 ]+>>> +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBS3SaveSpi +// +// Description: Restore SPI register for S3 resume +// +// Input: NoneE +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SBS3SaveSpi(VOID) +{ + EFI_STATUS Status; + UINT32 Data32; + UINT32 i; + UINT32 SpiRegister[] = { + R_PCH_SPI_SSFS, + R_PCH_SPI_PREOP, + R_PCH_SPI_OPMENU, + R_PCH_SPI_OPMENU + 4, + R_PCH_SPI_VSCC1, + R_PCH_SPI_VSCC0 + }; + + // + // Save SPI Registers for S3 resume usage + // + for (i = 0; i < sizeof (SpiRegister) / sizeof (UINT32); i++) { + Data32 = READ_MEM32_RCRB (SpiRegister[i]); + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( gBootScript, \ + EfiBootScriptWidthUint32, \ + SB_RCRB_BASE_ADDRESS + SpiRegister[i], \ + 1, \ + &Data32 + ); + } + + // EIP167087 >>> + TRACE((-1, "Programming SPI Protected Range registers")); + Status = SbFlashProtectedRange(); + TRACE((-1, " %r !!!\n", Status)); + ASSERT_EFI_ERROR(Status); + + // Write SPI Protected Range registers to S3 script + for(i=0;i<5;i++){ + Data32 = READ_MEM32_RCRB(SPI_BASE_ADDRESS + (R_SB_RCRB_SPI_PR0 + (i * 4))); + TRACE((-1, "PR%d value @ %x: %x\n", i, (SB_RCBA + SPI_BASE_ADDRESS + (R_SB_RCRB_SPI_PR0 + (i * 4))), Data32)); + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( gBootScript, \ + EfiBootScriptWidthUint32, \ + SB_RCBA + SPI_BASE_ADDRESS + (R_SB_RCRB_SPI_PR0 + (i * 4)), \ + 1, \ + &Data32 + ); + } + // EIP167087 <<< +} +// [ EIP357393 ]+<<< + + +//---------------------------------------------------------------------------- +// USUALLY NO PORTING REQUIRED FOR THE FOLLOWING ROUTINES +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ClearWarmResetFlag +// +// Description: This function resets warm reset variable. +// +// Input: None +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID ClearWarmResetFlag (VOID) +{ + EFI_STATUS Status; + EFI_GUID SbWarmResetGuid = SB_WARM_RESET_GUID; + CHAR16 SbWarmResetVar[] = SB_WARM_RESET_VARIABLE; + UINT32 SbWarmResetFlag = 0; + UINT32 Attributes = 0; + UINTN VarSize = sizeof(SbWarmResetFlag); + static EFI_GUID guidHob = HOB_LIST_GUID; + EFI_HOB_HANDOFF_INFO_TABLE *pHit; + + Status = pRS->GetVariable( SbWarmResetVar, \ + &SbWarmResetGuid, \ + &Attributes, \ + &VarSize, \ + &SbWarmResetFlag ); + if ((!EFI_ERROR(Status)) && (SbWarmResetFlag == SB_WARM_RESET_TAG)) { + SbWarmResetFlag ^= 0xffffffff; + Status = pRS->SetVariable( SbWarmResetVar, \ + &SbWarmResetGuid, \ + Attributes, \ + 0, \ + &SbWarmResetFlag ); + + //Get Boot Mode + pHit = GetEfiConfigurationTable(pST, &guidHob); + if (pHit && (pHit->BootMode == BOOT_WITH_FULL_CONFIGURATION)) { + // Update Boot mode for ME. + pHit->BootMode = BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; + } + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ReportSBDxeError +// +// Description: This function reports DXE_SB_ERROR code to system during SB +// DXE initialzation if needed. +// +// Input: Status - EFI status. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID ReportSBDxeError ( + IN EFI_STATUS Status ) +{ + if (Status != EFI_SUCCESS) { + // Report Error code + ERROR_CODE (DXE_SB_ERROR, EFI_ERROR_MAJOR); + ASSERT_EFI_ERROR(Status); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WatchdogHandler +// +// Description: This function is called when the watchdog timer event is +// signalled. It calls the registered handler and then +// resets the system +// +// Inout: Event - Watchdog event +// Context - Context pointer +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID EFIAPI WatchdogHandler ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + // Call the registered handler if there is one + if (mWatchdogNotifyFunction != NULL) { + mWatchdogNotifyFunction (mWatchdogPeriod); + } + + // Reset the system + pRS->ResetSystem( EfiResetCold, EFI_TIMEOUT, 0, NULL ); +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RegisterHandler +// +// Description: This function registers a handler that is called when the +// Timer event has been signalled +// +// Input: *This - Pointer to the instance of the Architectural +// Protocol +// NotifyFunction - The function to call when the interrupt fires +// +// Output: EFI_STATUS +// EFI_SUCCESS - When new handle is registered +// EFI_ALREADY_STARTED - If notify function is already +// defined +// EFI_INVALID_PARAMETER - If notify function is NULL +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EFIAPI RegisterHandler ( + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction ) +{ + // Only register the handler if it is still NULL + if (NotifyFunction && mWatchdogNotifyFunction) + return EFI_ALREADY_STARTED; + if (!NotifyFunction && !mWatchdogNotifyFunction) + return EFI_INVALID_PARAMETER; + + mWatchdogNotifyFunction = NotifyFunction; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WatchdogSetTimerPeriod +// +// Description: This function sets the timer period before the watchdog goes +// off every TimerPeriod number of 100ns intervals, if the +// period is set to 0 the timer event is cancelled +// +// Input: *This - Pointer to the instance of the Architectural +// Protocol +// TimerPeriod - The number of 100ns intervals to which the +// watchdog will be programmed. +// +// Output: EFI_STATUS +// EFI_SUCCESS - The event has been set to be +// signaled at the requested time. +// EFI_INVALID_PARAMETER - WatchdogEvent or TimerDelayType +// is not valid. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EFIAPI WatchdogSetTimerPeriod ( + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod ) +{ + EFI_TIMER_DELAY TimerDelayType; + + // Store new timer length + mWatchdogPeriod = TimerPeriod; + + // Cancel timer event if Timer Period is 0 + TimerDelayType = (TimerPeriod) ? TimerRelative : TimerCancel; + + // Set the timer for the event + return pBS->SetTimer( mWatchdogEvent, TimerDelayType, mWatchdogPeriod ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WatchdogGetTimerPeriod +// +// Description: This function returns the current watchdog timer period +// +// Input: *This - Pointer to the instance of the Architectural +// Protocol +// *TimerPeriod - Pointer to a memory location to load the +// current Timer period into +// +// Output: *TimerPeriod - Current Timer Period if function returns +// EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EFIAPI WatchdogGetTimerPeriod ( + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This, + IN UINT64 *TimerPeriod ) +{ + // return the current Watchdog period + *TimerPeriod = mWatchdogPeriod; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WatchdogInit +// +// Description: This function installs the the Watchdog Timer protocol on its +// handle, and initializes the Watchdog timer. +// +// Input: ImageHandle - ImageHandle of the loaded driver +// SystemTable - Pointer to the System Table +// +// Output: EFI_STATUS +// EFI_SUCCESS - The Watchdog Timer protocol was +// installed. +// EFI_OUT_OF_RESOURCES - Space for a new handle could not +// be allocated. +// EFI_INVALID_PARAMETER - One of the parameters has an +// invalid value. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS WatchdogInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status; + + // Use the Timer event to trigger the Watchdog. No specific hardware + // exists for this + Status = pBS->CreateEvent( EVT_TIMER | EVT_NOTIFY_SIGNAL, \ + TPL_NOTIFY, \ + WatchdogHandler, \ + NULL, \ + &mWatchdogEvent ); + + // Create a handle for the ArchProtocol and install Watchdog Arch + // Protocol on the handle + Status = pBS->InstallProtocolInterface( &mWatchdogHandle, \ + &gWatchdogGuid, \ + EFI_NATIVE_INTERFACE, \ + &mWatchdog ); + + return Status; +} + +#if defined(HPET_PROTOCOL_SUPPORT) && (HPET_PROTOCOL_SUPPORT != 0) +// Mask used for counter and comparator calculations to adjust for a 32-bit or 64-bit counter. +UINT64 gCounterMask; +// Cached state of the HPET General Capabilities register managed by this driver. +// Caching the state reduces the number of times the configuration register is read. +volatile HPET_GENERAL_CAPABILITIES_ID_REGISTER gHpetGeneralCapabilities; +// Cached state of the HPET General Configuration register managed by this driver. +// Caching the state reduces the number of times the configuration register is read. +volatile HPET_GENERAL_CONFIGURATION_REGISTER gHpetGeneralConfiguration; +// Cached state of the Configuration register for the HPET Timer managed by +// this driver. Caching the state reduces the number of times the configuration +// register is read. +volatile HPET_TIMER_CONFIGURATION_REGISTER gTimerConfiguration; + +EFI_EVENT gHpetLegacyBootEvent; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EnableHpetInChipset +// +// Description: This function enables HPET register decode. +// +// Input: None +// +// Output: None +// +// Notes: Porting required. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID EnableHpetInChipset( VOID ) +{ + // Porting required. +// WRITE_MEM32_RCRB_S3(gBootScriptSave, RCRB_MMIO_HPTC, ((HPET_BASE_ADDRESS >> 12) & 3) | 0x80); +WRITE_MEM32_RCRB_S3(gBootScript, RCRB_MMIO_HPTC, ((HPET_BASE_ADDRESS >> 12) & 3) | 0x80); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HpetRead +// +// Description: This function reads a 64-bit register from the HPET register. +// +// Input: Offset - Specifies the offset of the HPET register to read. +// +// Output: The 64-bit value read from the HPET register specified by +// Offset. +// +// Notes: No porting required. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT64 HpetRead ( + IN UINTN Offset ) +{ + return MMIO_READ64( HPET_BASE_ADDRESS + Offset ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HpetWrite +// +// Description: This function writes a 64-bit HPET register. +// +// Input: Offset - Specifies the ofsfert of the HPET register to write. +// Value - Specifies the value to write to the HPET register +// specified by Offset. +// +// Output: The 64-bit value written to HPET register specified by Offset. +// +// Notes: No porting required. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT64 HpetWrite ( + IN UINTN Offset, + IN UINT64 Value ) +{ + MMIO_WRITE64( HPET_BASE_ADDRESS + Offset, Value ); + return HpetRead( Offset ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HpetEnable +// +// Description: This function enables or disables the main counter in the +// HPET Timer. +// +// Input: Enable TRUE - Enable the main counter in the HPET Timer. +// FALSE - Disable the main counter in the HPET Timer. +// Output: None +// +// Notes: No porting required. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID HpetEnable ( + IN BOOLEAN Enable ) +{ + gHpetGeneralConfiguration.Bits.MainCounterEnable = Enable ? 1 : 0; + HpetWrite( HPET_GENERAL_CONFIGURATION_OFFSET, + gHpetGeneralConfiguration.Uint64); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: StopHpetBeforeLagecyBoot +// +// Description: This function stops HPET counter & interrupt. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID StopHpetBeforeLagecyBoot ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + // Disable HPET and Legacy Replacement Support. + HpetEnable (FALSE); + CountTime ((HPET_DEFAULT_TICK_DURATION / 10) * 2, PM_BASE_ADDRESS); + HpetWrite (HPET_TIMER_CONFIGURATION_OFFSET + HPET_OFFSET * HPET_TIMER_STRIDE, 0); + +#if defined(HPET_APIC_INTERRUPT_MODE) && (HPET_APIC_INTERRUPT_MODE != 0) + IoApicDisableIrq(HPET_APIC_INTERRUPT_PIN); +#else + gHpetGeneralConfiguration.Bits.LegacyRouteEnable = 0; + + HpetEnable (FALSE); +#endif + + pBS->CloseEvent(Event); +} +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TimerRegisterHandler +// +// Description: This function registers a handler that is called every time +// the timer interrupt fires +// +// Input: *This - Pointer to the instance of the Architectural +// Protocol +// NotifyFunction - The function to call when the interrupt fires +// +// Output: EFI_STATUS +// EFI_SUCCESS - New handle registered +// EFI_ALREADY_STARTED - if Notify function is already +// defined +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS TimerRegisterHandler ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN EFI_TIMER_NOTIFY NotifyFunction ) +{ + // Check to see if the handler has already been installed + if ((NotifyFunction != NULL) && (mNotifyFunction != NULL)) { + return EFI_ALREADY_STARTED; + } + + // If not install it + mNotifyFunction = NotifyFunction; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SetTimerPeriod +// +// Description: This function sets the timer to create an Intr on IRQ0 +// every TimerPeriod number of 100ns intervals +// +// Input: *This - Pointer to the instance of the Architectural +// Protocol +// TimerPeriod - The number of 100ns intervals to which the +// timer will be programmed. This value will +// be rounded up to the nearest timer interval. +// +// Output: EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod ) +{ +#if defined(HPET_PROTOCOL_SUPPORT) && (HPET_PROTOCOL_SUPPORT != 0) + UINTN Remainder; + UINT64 TimerCount; + + // Disable HPET timer when adjusting the timer period + HpetEnable (FALSE); +#else +// EFI_STATUS Status; + UINT32 NumberOfTicks; + UINT8 Value8; +#endif + + // Find the CPU Architectural Protocol + //Status = pBS->LocateProtocol( &gEfiCpuArchProtocolGuid, NULL, &CpuArch ); + + // If timer period is 0 then disable the Timer interrupt + if (TimerPeriod == 0) { +#if defined(HPET_APIC_INTERRUPT_MODE) && (HPET_APIC_INTERRUPT_MODE != 0) + IoApicDisableIrq(HPET_APIC_INTERRUPT_PIN); +#endif + // DisableIrq(SYSTEM_TIMER_IRQ); + mLegacy8259->DisableIrq( mLegacy8259, SYSTEM_TIMER_IRQ ); + } else { +#if defined(HPET_PROTOCOL_SUPPORT) && (HPET_PROTOCOL_SUPPORT != 0) + // Convert TimerPeriod to femtoseconds and divide by the number if + // femtoseconds per tick of the HPET counter to determine the number + // of HPET counter ticks in TimerPeriod 100 ns units. + TimerCount = Div64( Mul64( TimerPeriod, 100000000 ), + gHpetGeneralCapabilities.Bits.CounterClockPeriod, + &Remainder ); + + // Reset Main Counter + HpetWrite (HPET_MAIN_COUNTER_OFFSET, 0); + // ValueSetEnable must be set if the timer is set to periodic mode. + gTimerConfiguration.Bits.ValueSetEnable = 1; + HpetWrite (HPET_TIMER_CONFIGURATION_OFFSET + HPET_OFFSET * HPET_TIMER_STRIDE, gTimerConfiguration.Uint64); + // Clear ValueSetEnable bit. + gTimerConfiguration.Bits.ValueSetEnable = 0; + HpetWrite (HPET_TIMER_COMPARATOR_OFFSET + HPET_OFFSET * HPET_TIMER_STRIDE, TimerCount); + +#else + // otherwise change the timer period into number of ticks and set + // the timer + if (TimerPeriod > MAX_TICK_DURATION) TimerPeriod = MAX_TICK_DURATION; + // NumberOfTicks = TimerPeriod * 100 /TIMER_TICK; + // Since TimerPeriod in 100ns units and TIMER_TICK in ns + // We have to multiple TimerPeriod by 100 + // To round up result: + // NumberOfTicks = TimerPeriod * 100/TIMER_TICK + 0.5 = + // (TimerPeriod*100+TIMER_TICK/2)/TIMER_TICK + NumberOfTicks = ((UINT32)TimerPeriod * 100 + TIMER_TICK / 2) \ + / TIMER_TICK; + // Write to port 0x43 to setup the timer + IoWrite8 ( LEGACY_TIMER_CTRL, 0x36 ); + // Write to port 0x40 to set the time + IoWrite8 ( LEGACY_TIMER_0_COUNT, (UINT8)NumberOfTicks ); + IoWrite8 ( LEGACY_TIMER_0_COUNT, *(((UINT8*)&NumberOfTicks) + 1) ); + + Value8 = 0x36; + BOOT_SCRIPT_S3_IO_WRITE_MACRO(gBootScript, EfiBootScriptWidthUint8, LEGACY_TIMER_CTRL, 1, &Value8); + Value8 = (UINT8)NumberOfTicks; + BOOT_SCRIPT_S3_IO_WRITE_MACRO(gBootScript, EfiBootScriptWidthUint8, LEGACY_TIMER_0_COUNT, 1, &Value8); + Value8 = *(((UINT8*)&NumberOfTicks)+1); + BOOT_SCRIPT_S3_IO_WRITE_MACRO(gBootScript, EfiBootScriptWidthUint8, LEGACY_TIMER_0_COUNT, 1, &Value8); + +#endif + + // Now enable the interrupt +#if defined(HPET_APIC_INTERRUPT_MODE) && (HPET_APIC_INTERRUPT_MODE != 0) + IoApicEnableIrq(HPET_APIC_INTERRUPT_PIN, HPET_INTERRUPT_TRIGGER, (HPET_INTERRUPT_POLARITY == 0) ? TRUE : FALSE); +#endif + // EnableIrq(SYSTEM_TIMER_IRQ); + mLegacy8259->EnableIrq( mLegacy8259, SYSTEM_TIMER_IRQ, FALSE ); + +#if defined(HPET_PROTOCOL_SUPPORT) && (HPET_PROTOCOL_SUPPORT != 0) + // Enable HPET Interrupt Generation + gTimerConfiguration.Bits.InterruptEnable = 1; + HpetWrite (HPET_TIMER_CONFIGURATION_OFFSET + HPET_OFFSET * HPET_TIMER_STRIDE, gTimerConfiguration.Uint64); + + // Enable the HPET counter once new timer period has been established + // The HPET counter should run even if the HPET Timer interrupts are + // disabled. This is used to account for time passed while the interrupt + // is disabled. + HpetEnable (TRUE); +#endif + } + + mProgrammedTimerValue = TimerPeriod; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetTimerPeriod +// +// Description: This function returns the current timer period +// +// Input: *This - Pointer to the instance of the Architectural +// Protocol +// *TimerPeriod - pointer to a memory location to load the +// current Timer period into +// +// Output: EFI_SUCCESS - *TimerPeriod - Current Timer Period +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS GetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN OUT UINT64 *TimerPeriod ) +{ + *TimerPeriod = mProgrammedTimerValue; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GenerateSoftIntr + +// +// Description: This function generates a soft timer interrupt +// +// Input: *This - Pointer to the instance of the Architectural Protocol +// +// Output: EFI_UNSUPPORTED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS GenerateSoftIntr ( + IN EFI_TIMER_ARCH_PROTOCOL *This ) +{ + return EFI_UNSUPPORTED; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TimerInterruptHandler +// +// Description: This function is called when the Timer reaches 0. It raises +// the TPL and then calls the registered notify function +// +// Input: InterruptType - Interrupt type +// SystemContext - System context +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID TimerInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_SYSTEM_CONTEXT SystemContext ) +{ + EFI_TPL OldTpl; + static volatile UINT32 StoreCF8; +#if defined(HPET_APIC_INTERRUPT_MODE) && (HPET_APIC_INTERRUPT_MODE != 0) && defined(HPET_INTERRUPT_TRIGGER) && (HPET_INTERRUPT_TRIGGER == 1) + static volatile UINT64 HpetGenIntSts; +#endif + + OldTpl = pBS->RaiseTPL (TPL_HIGH_LEVEL); + + SaveRestoreRegisters( TRUE ); + + StoreCF8 = IoRead32(0xcf8); // Store CF8 (PCI index) + +#if defined(HPET_APIC_INTERRUPT_MODE) && (HPET_APIC_INTERRUPT_MODE != 0) + IoApicEoi(GetHpetApicPin()); + +#if defined(HPET_INTERRUPT_TRIGGER) && (HPET_INTERRUPT_TRIGGER == 1) + HpetGenIntSts = HpetRead(HPET_GENERAL_INTERRUPT_STATUS_OFFSET); + HpetWrite (HPET_GENERAL_INTERRUPT_STATUS_OFFSET, Shl64(BIT0, HPET_OFFSET)); +#endif +#else + // Clear the interrupt flag + mLegacy8259->EndOfInterrupt(mLegacy8259,SYSTEM_TIMER_IRQ); +#endif + + // This checks for the existance of a registered notify function and + // if it exists it calls the function with the current programmed Timer + // Period + if (mNotifyFunction) + { +#if defined(HPET_APIC_INTERRUPT_MODE) && (HPET_APIC_INTERRUPT_MODE != 0) && defined(HPET_INTERRUPT_TRIGGER) && (HPET_INTERRUPT_TRIGGER == 1) + if (HpetGenIntSts & Shl64(BIT0, HPET_OFFSET)) + { + mNotifyFunction (mProgrammedTimerValue); + } +#else + mNotifyFunction (mProgrammedTimerValue); +#endif + } + + IoWrite32(0xcf8, StoreCF8); // Restore 0xCF8 (PCI index) + + SaveRestoreRegisters( FALSE ); + + pBS->RestoreTPL (OldTpl); +} + +#if defined(HPET_APIC_INTERRUPT_MODE) && (HPET_APIC_INTERRUPT_MODE != 0) +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: Irq0InterruptHandler +// +// Description: This function is called when the 8254 Timer 0 reaches 0. +// It raises the TPL and then calls the registered notify +// function. +// +// Input: InterruptType - Interrupt type +// SystemContext - System context +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID Irq0InterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_SYSTEM_CONTEXT SystemContext ) +{ + EFI_TPL OldTpl; + + + OldTpl = pBS->RaiseTPL (TPL_HIGH_LEVEL); + + // Clear the interrupt flag + mLegacy8259->EndOfInterrupt(mLegacy8259, SYSTEM_TIMER_IRQ); + + pBS->RestoreTPL (OldTpl); +} +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TimerInit +// +// Description: This function installs the the timer protocol on its handle, +// and initializes the timer. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: EFI_STATUS +// EFI_SUCCESS - The Timer protocol was installed +// EFI_OUT_OF_RESOURCES - Space for a new handle could not +// be allocated. +// EFI_INVALID_PARAMETER - One of the parameters has an +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EFIAPI TimerInit ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + EFI_STATUS Status; + EFI_CPU_ARCH_PROTOCOL *CpuArch; + // TimerVector must be initialized to 0, since GetVector only modifies + // the lowest byte, and RegisterInterruptHandler requires TimerVector + // to be 4 bytes. + UINT32 TimerVector = 0; + UINT32 Irq0TimerVector = 0; + UINT8 Value; + + Status = pBS->LocateProtocol ( &gEfiLegacy8259ProtocolGuid, \ + NULL, \ + &mLegacy8259 ); + ASSERT_EFI_ERROR(Status); + +#if defined(HPET_PROTOCOL_SUPPORT) && (HPET_PROTOCOL_SUPPORT != 0) + // Enable HPET (0x3404) + EnableHpetInChipset(); + + // Retrieve HPET Capabilities and Configuration Information + gHpetGeneralCapabilities.Uint64 = HpetRead (HPET_GENERAL_CAPABILITIES_ID_OFFSET); + gHpetGeneralConfiguration.Uint64 = HpetRead (HPET_GENERAL_CONFIGURATION_OFFSET); + + // If Revision is not valid, then ASSERT() and unload the driver because the HPET + // device is not present. + if (gHpetGeneralCapabilities.Uint64 == 0 || gHpetGeneralCapabilities.Uint64 == 0xFFFFFFFFFFFFFFFF) { + TRACE((-1, "HPET device is not present. Unload HPET driver.\n")); + return EFI_DEVICE_ERROR; + } + + // Force the HPET timer to be disabled while setting everything up + HpetEnable (FALSE); +#if defined(HPET_APIC_INTERRUPT_MODE) && (HPET_APIC_INTERRUPT_MODE == 0) + // Enable Legacy Interrupt + gHpetGeneralConfiguration.Bits.LegacyRouteEnable = 1; +#endif +#endif + + // Disable timer, make sure no interrupt will be created + Status = SetTimerPeriod ( &mTimerProtocol, 0 ); + ASSERT_EFI_ERROR(Status); + +#if defined(HPET_PROTOCOL_SUPPORT) && (HPET_PROTOCOL_SUPPORT != 0) + // Configure the selected HPET Timer (Timer#0), clear InterruptEnable to keep + // interrupts disabled until full init is complete + // Enable PeriodicInterruptEnable to use perioidic mode + // Configure as a 32-bit counter + gTimerConfiguration.Uint64 = HpetRead (HPET_TIMER_CONFIGURATION_OFFSET + HPET_OFFSET * HPET_TIMER_STRIDE); + gTimerConfiguration.Bits.InterruptEnable = 0; + gTimerConfiguration.Bits.PeriodicInterruptEnable = 1; + gTimerConfiguration.Bits.CounterSizeEnable = 1; // 32bit + gTimerConfiguration.Bits.LevelTriggeredInterrupt = HPET_INTERRUPT_TRIGGER; +#if defined(HPET_APIC_INTERRUPT_MODE) && (HPET_APIC_INTERRUPT_MODE != 0) + gTimerConfiguration.Bits.InterruptRoute = HPET_APIC_INTERRUPT_PIN; +#endif + HpetWrite (HPET_TIMER_CONFIGURATION_OFFSET + HPET_OFFSET * HPET_TIMER_STRIDE, gTimerConfiguration.Uint64); + + // Read the HPET Timer Capabilities and Configuration register back again. + // CounterSizeEnable will be read back as a 0 if it is a 32-bit only timer + gTimerConfiguration.Uint64 = HpetRead (HPET_TIMER_CONFIGURATION_OFFSET + HPET_OFFSET * HPET_TIMER_STRIDE); +#if defined(HPET_APIC_INTERRUPT_MODE) && (HPET_APIC_INTERRUPT_MODE != 0) + // If the interrupt pin isn't supported by the particular timer, then the value read back won't match that is written. + if (gTimerConfiguration.Bits.InterruptRoute != HPET_APIC_INTERRUPT_PIN) { + ASSERT_EFI_ERROR (EFI_UNSUPPORTED); + return EFI_UNSUPPORTED; + } +#endif + if ((gTimerConfiguration.Bits.CounterSizeEnable == 1) && (sizeof (UINTN) == sizeof (UINT64))) { + // 64-bit BIOS can use 64-bit HPET timer + gCounterMask = 0xffffffffffffffff; + // Set timer back to 64-bit + gTimerConfiguration.Bits.CounterSizeEnable = 0; + HpetWrite (HPET_TIMER_CONFIGURATION_OFFSET + HPET_OFFSET * HPET_TIMER_STRIDE, gTimerConfiguration.Uint64); + } else { + gCounterMask = 0x00000000ffffffff; + } +#endif + + // Find the CPU Arch Protocol + Status = pBS->LocateProtocol ( &gEfiCpuArchProtocolGuid, \ + NULL, \ + &CpuArch ); + ASSERT_EFI_ERROR(Status); + +#if defined(HPET_APIC_INTERRUPT_MODE) && (HPET_APIC_INTERRUPT_MODE != 0) + TimerVector = MASTER_INTERRUPT_BASE + HPET_APIC_INTERRUPT_PIN; + + Status = mLegacy8259->GetVector ( mLegacy8259, \ + Efi8259Irq0, \ + (UINT8 *)&Irq0TimerVector ); + ASSERT_EFI_ERROR(Status); + + Status = CpuArch->RegisterInterruptHandler ( CpuArch, \ + Irq0TimerVector, \ + Irq0InterruptHandler ); + ASSERT_EFI_ERROR(Status); +#else + Status = mLegacy8259->GetVector ( mLegacy8259, \ + Efi8259Irq0, \ + (UINT8 *)&TimerVector ); + ASSERT_EFI_ERROR(Status); +#endif + + Status = CpuArch->RegisterInterruptHandler ( CpuArch, \ + TimerVector, \ + TimerInterruptHandler ); + ASSERT_EFI_ERROR(Status); + + // Initialize the handle pointer + mNotifyFunction = NULL; + +#if defined(HPET_PROTOCOL_SUPPORT) && (HPET_PROTOCOL_SUPPORT != 0) + // Init default for Timer 1 + IoWrite8( LEGACY_TIMER_CTRL, 0x36 ); + IoWrite8( LEGACY_TIMER_0_COUNT, 0 ); + IoWrite8( LEGACY_TIMER_0_COUNT, 0 ); + // Add boot script programming + Value = 0x36; + BOOT_SCRIPT_S3_IO_WRITE_MACRO(gBootScript, EfiBootScriptWidthUint8, LEGACY_TIMER_CTRL, 1, &Value); + Value = 0x0; + BOOT_SCRIPT_S3_IO_WRITE_MACRO(gBootScript, EfiBootScriptWidthUint8, LEGACY_TIMER_0_COUNT, 1, &Value); + BOOT_SCRIPT_S3_IO_WRITE_MACRO(gBootScript, EfiBootScriptWidthUint8, LEGACY_TIMER_0_COUNT, 1, &Value); + + // The default value of 10000 100 ns units is the same as 1 ms. + Status = SetTimerPeriod ( &mTimerProtocol, HPET_DEFAULT_TICK_DURATION ); + + + + Status = CreateLegacyBootEvent( TPL_CALLBACK, + StopHpetBeforeLagecyBoot, + NULL, + &gHpetLegacyBootEvent ); +#else + // Force the timer to be enabled at its default period + Status = SetTimerPeriod ( &mTimerProtocol, DEFAULT_TICK_DURATION ); +#endif + ASSERT_EFI_ERROR (Status); + + //Program Timer1 to pass certain customer's test + IoWrite8( LEGACY_TIMER_CTRL, 0x54 ); + IoWrite8( LEGACY_TIMER_1_COUNT, 0x12 ); + //add boot script programming + Value = 0x54; + BOOT_SCRIPT_S3_IO_WRITE_MACRO(gBootScript, EfiBootScriptWidthUint8, LEGACY_TIMER_CTRL, 1, &Value); + Value = 0x12; + BOOT_SCRIPT_S3_IO_WRITE_MACRO(gBootScript, EfiBootScriptWidthUint8, LEGACY_TIMER_1_COUNT, 1, &Value); + + + // Install the Timer Architectural Protocol onto a new handle + Status = pBS->InstallProtocolInterface ( &mTimerProtocolHandle, \ + &gEfiTimerArchProtocolGuid, \ + EFI_NATIVE_INTERFACE, \ + &mTimerProtocol ); + ASSERT_EFI_ERROR(Status); + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ProgramIrqMaskTrigger +// +// Description: Program the Irq Mask and Trigger. +// +// Input: None +// +// Output: None +// +// Notes: Here is the control flow of this function: +// 1. Program Master Irq Mask. +// 2. Program Slave Irq Mask. +// 3. Program Trigger Level. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID ProgramIrqMaskTrigger (VOID) +{ + IoWrite8(LEGACY_8259_MASK_REGISTER_MASTER, (UINT8)gIrqMask[gMode]); + IoWrite8(LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8)(gIrqMask[gMode] >> 8)); + + // 4d0 can not be accessed as by IoWrite16, we have to split + IoWrite8(LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, \ + (UINT8)gIrqTrigger[gMode]); + IoWrite8(LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, \ + (UINT8)(gIrqTrigger[gMode] >> 8)); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SetVectorBase +// +// Description: Initializes the interrupt controller and program the Irq +// Master and Slave Vector Base. +// +// Input: *This - Pointer to this object +// MasterBase - IRQ base for the master 8259 controller +// SlaveBase - IRQ base for the slave 8259 controller +// +// Output: EFI_SUCCESS - Interrupt on the interrupt controllers was +// enabled. +// +// Notes: Here is the control flow of this function: +// 1. If Master base is changed, initialize master 8259 setting +// the interrupt offset. +// 2. If Slave base is changed, initialize slave 8259 setting +// the interrupt offset. +// 3. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SetVectorBase ( + IN EFI_LEGACY_8259_PROTOCOL *This, + IN UINT8 MasterBase, + IN UINT8 SlaveBase ) +{ + // 8259 Master + if (MasterBase != gMasterBase) { + // Start 8259 Master Initialization. + IoWrite8(LEGACY_8259_CONTROL_REGISTER_MASTER, ICW1); // 0x20 + // Set Interrupt Offset + IoWrite8(LEGACY_8259_MASK_REGISTER_MASTER, MasterBase); // 0x21 + // Set Slave IRQ. + IoWrite8(LEGACY_8259_MASK_REGISTER_MASTER, ICW3_M); // 0x21 + // Set 8259 mode. See ICW4 comments with #define. + IoWrite8(LEGACY_8259_MASK_REGISTER_MASTER, ICW4); // 0x21 + gMasterBase = MasterBase; + } + + // 8259 Slave + if (SlaveBase != gSlaveBase) { + // Start 8259 Slave Initialization. + IoWrite8(LEGACY_8259_CONTROL_REGISTER_SLAVE, ICW1); // 0xA0 + // Set Interrupt Offset + IoWrite8(LEGACY_8259_MASK_REGISTER_SLAVE, SlaveBase); // 0xA1 + // Set Slave IRQ. + IoWrite8(LEGACY_8259_MASK_REGISTER_SLAVE, ICW3_S); // 0xA1 + // Set 8259 mode. See ICW4 comments with #define. + IoWrite8(LEGACY_8259_MASK_REGISTER_SLAVE, ICW4); // 0xA1 + gSlaveBase = SlaveBase; + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetMask +// +// Description: Get the Master/Slave Irq Mask, Irq Level for Legacy real +// mode and protected mode. +// +// Input: *This - Pointer to this object +// *LegacyMask - Legacy mode interrupt mask +// *LegacyEdgeLevel - Legacy mode edge/level trigger value +// *ProtectedMask - Protected mode interrupt mask +// *ProtectedEdgeLevel - Protected mode edge/level trigger value +// +// Output: EFI_SUCCESS - Returned irq mask/level. +// +// Notes: Here is the control flow of this function: +// 1. If *LegacyMask not NULL, get legacy Mask. +// 2. If *LegacyEdgeLevel not NULL, get legacy Trigger Level. +// 3. If *ProtectedMask not NULL, get protected Mask. +// 4. If *ProtectedEdgeLevel not NULL, get protected trigger +// level. +// 5. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS GetMask ( + IN EFI_LEGACY_8259_PROTOCOL *This, + OUT UINT16 *LegacyMask OPTIONAL, + OUT UINT16 *LegacyEdgeLevel OPTIONAL, + OUT UINT16 *ProtectedMask OPTIONAL, + OUT UINT16 *ProtectedEdgeLevel OPTIONAL ) +{ + if (LegacyMask) *LegacyMask = gIrqMask[0]; + if (LegacyEdgeLevel) *LegacyEdgeLevel = gIrqTrigger[0]; + if (ProtectedMask) *ProtectedMask = gIrqMask[1]; + if (ProtectedEdgeLevel) *ProtectedEdgeLevel = gIrqTrigger[1]; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SetMask +// +// Description: Set the Master/Slave Irq Mask, Irq Level for Legacy real mode +// and protected mode. +// +// Input: *This - Pointer to this object +// *LegacyMask - Legacy mode interrupt mask +// *LegacyEdgeLevel - Legacy mode edge/level trigger value +// *ProtectedMask - Protected mode interrupt mask +// *ProtectedEdgeLevel - Protected mode edge/level trigger value +// +// Output: EFI_SUCCESS - Set irq mask/level. +// +// Notes: Here is the control flow of this function: +// 1. If *LegacyMask not NULL, set legacy mask variable. +// 2. If *LegacyEdgeLevel not NULL, set legacy Trigger Level +// variable. +// 3. If *ProtectedMask not NULL, set protected mask variable. +// 4. If *ProtectedEdgeLevel not NULL, set protected trigger +// level variable. +// 5. Call function to program 8259 with mask/trigger of +// current mode. +// 6. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SetMask ( + IN EFI_LEGACY_8259_PROTOCOL *This, + IN UINT16 *LegacyMask OPTIONAL, + IN UINT16 *LegacyEdgeLevel OPTIONAL, + IN UINT16 *ProtectedMask OPTIONAL, + IN UINT16 *ProtectedEdgeLevel OPTIONAL ) +{ + if (LegacyMask) gIrqMask[0] = *LegacyMask; + if (LegacyEdgeLevel) gIrqTrigger[0] = *LegacyEdgeLevel; + if (ProtectedMask) gIrqMask[1] = *ProtectedMask; + if (ProtectedEdgeLevel) gIrqTrigger[1] = *ProtectedEdgeLevel; + + ProgramIrqMaskTrigger(); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SetMode +// +// Description: Sets the interrupt mode operation to legacy or protected. +// New mask and edge/level status can be provided as input +// +// Input: *This - Pointer to this object +// Mode - Interrupt mode setting +// *Mask - New interrupt mask for this mode +// *EdgeLevel - New edge/level trigger value for this mode +// +// Output: EFI_SUCCESS - Set mode was successful +// +// Notes: Here is the control flow of this function: +// 1. If invalid mode, return EFI_INVALID_PARAMETER. +// 2. If *Mask not NULL, set mode mask variable. +// 3. If *EdgeLevel not NULL, set mode trigger level variable. +// 4. Call function to program 8259 with mask/trigger of +// current mode. +// 5. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SetMode ( + IN EFI_LEGACY_8259_PROTOCOL *This, + IN EFI_8259_MODE Mode, + IN UINT16 *Mask OPTIONAL, + IN UINT16 *EdgeLevel OPTIONAL ) +{ + if (Mode >= Efi8259MaxMode) return EFI_INVALID_PARAMETER; +#if defined (HPET_INTERRUPT_TRIGGER) && (HPET_INTERRUPT_TRIGGER == 1) + if (Mode == Efi8259LegacyMode) + gTimerConfiguration.Bits.InterruptEnable = 0; + else // Efi8259ProtectedMode + gTimerConfiguration.Bits.InterruptEnable = 1; + + HpetWrite (HPET_TIMER_CONFIGURATION_OFFSET + HPET_OFFSET * HPET_TIMER_STRIDE, gTimerConfiguration.Uint64); +#endif + + gMode = Mode; + if (Mask) gIrqMask[Mode] = *Mask; + if (EdgeLevel) gIrqTrigger[Mode] = *EdgeLevel; + + ProgramIrqMaskTrigger(); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetVector +// +// Description: Returns the vector number for the requested IRQ +// +// Input: This - Legacy8259 protocol object +// Irq - IRQ number for which vector is needed +// Vector - Vector value is returned in this pointer +// +// Output: EFI_STATUS +// EFI_INVALID_PARAMETER - Invalid IRQ. +// EFI_SUCCESS - Get Irq Vector for IRQ. +// +// Notes: Here is the control flow of this function: +// 1. If invalid IRQ, return EFI_INVALID_PARAMETER. +// 2. If Set *Vector to Irq base + interrupt offset. +// 3. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS GetVector ( + IN EFI_LEGACY_8259_PROTOCOL *This, + IN EFI_8259_IRQ Irq, + OUT UINT8 *Vector ) +{ + if ((UINT8)Irq >= (UINT8)Efi8259IrqMax) return EFI_INVALID_PARAMETER; + *Vector = (Irq <= Efi8259Irq7) ? gMasterBase + Irq : gSlaveBase + Irq - 8; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EnableIrq +// +// Description: Enable the Interrupt controllers to respond in a specific IRQ. +// +// Input: This - Legacy8259 protocol object +// Irq - IRQ that has to be enabled +// LevelTriggered - Trigger mechanism (level or edge) for this +// IRQ +// +// Output: EFI_STATUS +// EFI_SUCCESS - Interrupt on the interrupt +// controllers was enabled. +// EFI_INVALID_PARAMETER - Interrupt not existent. +// The 8259 master/slave supports +// IRQ 0-15. +// +// Notes: Here is the control flow of this function: +// 1. Check if IRQ is valid. If not, return EFI_INVALID_PARAMETER +// 2. Clear interrupt mask bit in variable of current mode. +// 3. Set/Clear bit of trigger level variable of current mode. +// 4. Program mask/trigger. +// 5. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EnableIrq ( + IN EFI_LEGACY_8259_PROTOCOL *This, + IN EFI_8259_IRQ Irq, + IN BOOLEAN LevelTriggered ) +{ + if ((UINT8)Irq > (UINT8)15) return EFI_INVALID_PARAMETER; + + gIrqMask[gMode] &= (UINT16)(~(1 << Irq)); // Clear mask for the Irq. + + gIrqTrigger[gMode] &= (UINT16)(~(1 << Irq)); // Mask Irq to change. + + // Change irq bit, 0 = edge, 1 = level. + if (LevelTriggered) gIrqTrigger[gMode] |= (1 << Irq); + + ProgramIrqMaskTrigger(); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: DisableIrq +// +// Description: Disable the Interrupt controllers to stop responding to +// a specific IRQ. +// +// Input: This - Legacy8259 protocol object +// Irq - IRQ that has to be disabled +// +// Output: EFI_STATUS +// EFI_SUCCESS - Interrupt on the interrupt +// controllers was enabled. +// EFI_INVALID_PARAMETER - Interrupt not existent. +// The 8259 master/slave supports +// IRQ 0-15. +// +// Notes: Here is the control flow of this function: +// 1. Check if IRQ is valid. If not, return EFI_INVALID_PARAMETER +// 2. Set interrupt mask bit in variable of current mode. +// 3. Program mask/trigger. +// 4. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS DisableIrq ( + IN EFI_LEGACY_8259_PROTOCOL *This, + IN EFI_8259_IRQ Irq ) +{ + if ((UINT8)Irq > (UINT8)15) return EFI_INVALID_PARAMETER; + + gIrqMask[gMode] |= (1 << Irq); // Set mask for the IRQ. + + ProgramIrqMaskTrigger(); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetInterruptLine +// +// Description: Get IRQ vector asigned to PCI card. +// +// Input: This - Pointer to this object +// PciHandle - PCI handle for this device +// Vector - Interrupt vector this device +// +// Output: EFI_STATUS +// EFI_SUCCESS - Vector returned. +// EFI_INVALID_PARAMETER - Invalid PciHandle. +// +// Notes: Here is the control flow of this function: +// 1. Get Handle of PciIo installed on PciHandle. +// 2. If PciIo not installed, return EFI_INVALID_DEVICE. +// 3. Set *vector to Irq vector programmed into card. +// 4. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS GetInterruptLine ( + IN EFI_LEGACY_8259_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT UINT8 *Vector ) +{ + EFI_STATUS Status; + EFI_PCI_IO_PROTOCOL *PciIo; + + Status = pBS->HandleProtocol( PciHandle, \ + &gEfiPciIoProtocolGuid, \ + &PciIo ); + if (EFI_ERROR(Status)) return EFI_INVALID_PARAMETER; + + // Read vector from card. + PciIo->Pci.Read( PciIo, \ + EfiPciIoWidthUint8, \ + PCI_INTLINE, \ + 1, \ + Vector ); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EndOfInterrupt +// +// Description: Send end of interrupt command to interrupt controller(s). +// +// Input: This - Pointer to this object +// Irq - IRQ number for this EOI has to be sent +// +// Output: EFI_STATUS +// EFI_SUCCESS - EOI command sent to controller(s) +// EFI_INVALID_PARAMETER - Interrupt not existent. The 8259 +// master/slave supports IRQ 0-15. +// +// Notes: Here is the control flow of this function: +// 1. Check if IRQ is valid. If not, return EFI_INVALID_PARAMETER +// 2. If Irq >= 8, then Send EOI to slave controller. +// 3. Send EOI to master controller. (This is for both master / +// slave IRQs) +// 4. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EndOfInterrupt ( + IN EFI_LEGACY_8259_PROTOCOL *This, + IN EFI_8259_IRQ Irq ) +{ + if (Irq > 15) return EFI_INVALID_PARAMETER; + + if (Irq >= 8) { // If Slave, send EOI to slave first. + // Send Slave EOI + IoWrite8 (LEGACY_8259_CONTROL_REGISTER_SLAVE, EOI_COMMAND); + } + // Send Master EOI + IoWrite8 (LEGACY_8259_CONTROL_REGISTER_MASTER, EOI_COMMAND); + + return EFI_SUCCESS; +} + +EFI_LEGACY_8259_PROTOCOL gLegacy8259Protocol = { + SetVectorBase, + GetMask, SetMask, + SetMode, + GetVector, + EnableIrq, DisableIrq, + GetInterruptLine, + EndOfInterrupt +}; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: Initialize8259 +// +// Description: Initialize 8259 Interrupt Controller. +// +// Input: ImageHandle - Image handle for this driver +// SystemTable - Pointer to the sytem table +// +// Output: EFI_STATUS +// EFI_SUCCESS - The legacy 8259 Protocols were +// installed. +// EFI_ALREADY_STARTED - The legacy 8259 Protocol was passed +// in that is already present in the +// handle database. +// EFI_OUT_OF_RESOURCES - There was not enought memory in +// pool to install all the protocols. +// +// Notes: Here is the control flow of this function: +// 1. Initialize the Cpu setting vector bases. +// 2. Set Cpu Mode, mask, and trigger level. +// 3. Install Legacy 8259 Interface. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS Initialize8259 ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status; + UINT16 Mask = 0xffff; // Mask all interrupts. + UINT16 EdgeLevel = 0x00; // Set all edge. + BOOLEAN IntState = CPULib_GetInterruptState(); + + CPULib_DisableInterrupt(); + + // Set the protected mode vectors for MASTER and SLAVE PICs + SetVectorBase(0, MASTER_INTERRUPT_BASE, SLAVE_INTERRUPT_BASE); + SetMode(0, Efi8259ProtectedMode, &Mask, &EdgeLevel); + + // Install the Legacy8259Protocol + Status = pBS->InstallMultipleProtocolInterfaces( \ + &ImageHandle, \ + &gEfiLegacy8259ProtocolGuid, \ + &gLegacy8259Protocol, \ + NULL ); + if (EFI_ERROR(Status)) return Status; + + if(IntState)CPULib_EnableInterrupt(); + + return EFI_SUCCESS; +} + + +// Protocols that are installed +DXE_PCH_PLATFORM_POLICY_PROTOCOL mPchPolicyData = { 0 }; +PCH_DEVICE_ENABLING mPchDeviceEnabling = { 0 }; +PCH_USB_CONFIG mPchUsbConfig = { 0 }; +PCH_PCI_EXPRESS_CONFIG mPchPciExpressConfig = { 0 }; +PCH_SATA_CONFIG mPchSataConfig = { 0 }; +PCH_AZALIA_CONFIG mPchAzaliaConfig = { 0 }; +PCH_SMBUS_CONFIG mPchSmbusConfig = { 0 }; +PCH_MISC_PM_CONFIG mPchMiscPmConfig = { 0 }; +PCH_IO_APIC_CONFIG mPchIoApicConfig = { 0 }; +PCH_DEFAULT_SVID_SID mPchDefaultSvidSid = { 0 }; +PCH_LOCK_DOWN_CONFIG mPchLockDownConfig = { 0 }; +PCH_THERMAL_CONFIG mPchThermalConfig = { 0 }; +PCH_LPC_HPET_CONFIG mPchHpetConfig = { 0 }; +PCH_LPC_SIRQ_CONFIG mSerialIrqConfig = { 0 }; +PCH_DMI_CONFIG mPchDmiConfig = { 0 }; +PCH_PWR_OPT_CONFIG mPchPwrOptConfig = { 0 }; +PCH_MISC_CONFIG mPchMiscConfig = { 0 }; +PCH_AUDIO_DSP_CONFIG mPchAudioDspConfig = { 0 }; +PCH_SERIAL_IO_CONFIG mSerialIoConfig = { 0 }; + +UINT8 mSmbusRsvdAddresses[DIMM_SLOT_NUM] = { + DIMM1_SMBUS_ADDRESS, + DIMM2_SMBUS_ADDRESS, + DIMM3_SMBUS_ADDRESS, + DIMM4_SMBUS_ADDRESS +}; + +PCH_PCIE_DEVICE_ASPM_OVERRIDE mDevAspmOverride[] = { + // + // Intel PRO/Wireless + // + {0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel WiMAX/WiFi Link + // + {0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Crane Peak WLAN NIC + // + {0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Crane Peak w/BT WLAN NIC + // + {0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Kelsey Peak WiFi, WiMax + // + {0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Centrino Wireless-N 105 + // + {0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Centrino Wireless-N 135 + // + {0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Centrino Wireless-N 2200 + // + {0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Centrino Wireless-N 2230 + // + {0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Centrino Wireless-N 6235 + // + {0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel CampPeak 2 Wifi + // + {0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel WilkinsPeak 1 Wifi + // + {0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003}, + {0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003}, + {0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003}, + {0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003}, + // + // Intel Wilkins Peak 2 Wifi + // + {0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003}, + {0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003}, + {0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003}, + {0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003}, + // + // Intel Wilkins Peak PF Wifi + // + {0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF} + +#if defined OEM_SB_PCIE_ASPM_OVERRIDE_TABLE + OEM_SB_PCIE_ASPM_OVERRIDE_TABLE, +#endif +}; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: InstallDxePchPlatformPolicy +// +// Description: Install Dxe Pch Platform Policy. +// +// Input: ImageHandle - Image handle +// SystemTable - Pointer to the system table +// +// Output: Return Status based on errors that occurred while waiting for +// time to expire. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +InstallDxePchPlatformPolicy (VOID) +{ + EFI_HANDLE Handle; + EFI_STATUS Status; + UINT8 PortIndex; + UINT8 PortDataOut = 0; + UINTN VariableSize; + EFI_GUID SetupGuid = SETUP_GUID; + SETUP_DATA SetupData; + UINT32 SetupDataAttributes = 0; + UINT32 PchSpiStrp9; +#if defined iME_SUPPORT && iME_SUPPORT + ME_BIOS_EXTENSION_SETUP MeBiosExtensionSetupData; + EFI_GUID EfiMeBiosExtensionSetupGuid = EFI_ME_BIOS_EXTENSION_SETUP_GUID; + CHAR16 EfiMeBiosExtensionSetupName[] = EFI_ME_BIOS_EXTENSION_SETUP_VARIABLE_NAME; +#endif + UINT16 GpioBase = 0; + UINT16 UsbPortLength[LPTH_USB_MAX_PHYSICAL_PORTS] = {USB_PORTS_LENGTH}; + UINT8 UsbPortLocation[LPTH_USB_MAX_PHYSICAL_PORTS] = {USB_PORT_LOCATION_CONFIG}; + UINT8 UsbOverCurrentMapping[LPTH_USB_MAX_PHYSICAL_PORTS] = {USB_OVER_CURRENT_MAPPING_SETTINGS}; + UINT8 ULTUsbOverCurrentMapping[LPTLP_USB_MAX_PHYSICAL_PORTS]= {ULT_USB_OVER_CURRENT_MAPPING_SETTINGS}; //[EIP118480] + UINT8 Usb30OverCurrentMapping[LPTH_XHCI_MAX_USB3_PORTS] = {USB30_OVER_CURRENT_MAPPING_SETTINGS}; + UINT16 LpcDeviceId; + EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea; + EFI_GUID gEfiGlobalNvsAreaProtocolGuid = EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID; + PCH_SERIES PchSeries = GetPchSeries(); + UINT32 GbePortSel; +#if defined(RC_PORT_0) && (RC_PORT_0 == 1) + BOOLEAN PcieRPMap[] = { RC_PORT_0, RC_PORT_1, RC_PORT_2, RC_PORT_3, + RC_PORT_4, RC_PORT_5, RC_PORT_6, RC_PORT_7 }; +#endif + static EFI_GUID guidHob = HOB_LIST_GUID; + EFI_HOB_HANDOFF_INFO_TABLE *pHit; + + // + // Locate the Global NVS Protocol. + // + Status = pBS->LocateProtocol ( + &gEfiGlobalNvsAreaProtocolGuid, + NULL, + &GlobalNvsArea + ); + ASSERT_EFI_ERROR (Status); + + LpcDeviceId = READ_PCI16_SB(R_PCH_LPC_DEVICE_ID); + + // Read the SB Platform Data + VariableSize = sizeof (SB_PLATFORM_DATA); + Status = pRS->GetVariable ( + L"SbPlatformData", + &SetupGuid, + NULL, + &VariableSize, + &SbPlatformData + ); + + VariableSize = sizeof (SETUP_DATA); + Status = pRS->GetVariable ( + L"Setup", + &SetupGuid, + &SetupDataAttributes, + &VariableSize, + &SetupData + ); + ASSERT_EFI_ERROR (Status); + + if ((READ_MEM16_RCRB(R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FDV) == B_PCH_SPI_HSFS_FDV) { + RESET_MEM32_RCRB(R_PCH_SPI_FDOC, (UINT32) (B_PCH_SPI_FDOC_FDSS_MASK | B_PCH_SPI_FDOC_FDSI_MASK)); + SET_MEM32_RCRB(R_PCH_SPI_FDOC, (UINT32) (V_PCH_SPI_FDOC_FDSS_PCHS | R_PCH_SPI_STRP9)); + PchSpiStrp9 = READ_MEM32_RCRB(R_PCH_SPI_FDOD); + + // Get GbePortSel + GbePortSel = (UINT8)(( PchSpiStrp9 & B_PCH_SPI_STRP9_GBE_PCIE_PSC) >> N_PCH_SPI_STRP9_GBE_PCIE_PSC); + + // Get GbE slot number (zero based value) from descriptor and Get Subtractive decode enable bit from descriptor + if ( PchSeries == PchLp ) { + switch(GbePortSel) { + case 0: + SbPlatformData.GbePciePortNum = 2; // Root Port 3 + break; + case 1: + SbPlatformData.GbePciePortNum = 3; // Root Port 4 + break; + case 2: // Root Port 5, lane 0 + case 3: // Root Port 5, lane 1 + case 4: // Root Port 5, lane 2 + case 5: // Root Port 5, lane 3 + SbPlatformData.GbePciePortNum = 4; + break; + default: + SbPlatformData.GbePciePortNum = GbePortSel; + break; + } + } else { + SbPlatformData.GbePciePortNum = GbePortSel; + } + + SbPlatformData.PcieSBDE = (UINT8)(( PchSpiStrp9 & + B_PCH_SPI_STRP9_PCIE_SBDE_EN) >> + N_PCH_SPI_STRP9_PCIE_SBDE_EN); + } else { + SbPlatformData.GbePciePortNum = 5; + SbPlatformData.PcieSBDE = 0; + } + + // General intialization + mPchPolicyData.Revision = DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_7; + mPchPolicyData.BusNumber = 0; + mPchPolicyData.DeviceEnabling = &mPchDeviceEnabling; + mPchPolicyData.UsbConfig = &mPchUsbConfig; + mPchPolicyData.PciExpressConfig = &mPchPciExpressConfig; + mPchPolicyData.SataConfig = &mPchSataConfig; + mPchPolicyData.AzaliaConfig = &mPchAzaliaConfig; + mPchPolicyData.SmbusConfig = &mPchSmbusConfig; + mPchPolicyData.MiscPmConfig = &mPchMiscPmConfig; + mPchPolicyData.IoApicConfig = &mPchIoApicConfig; + mPchPolicyData.DefaultSvidSid = &mPchDefaultSvidSid; + mPchPolicyData.LockDownConfig = &mPchLockDownConfig; + mPchPolicyData.ThermalConfig = &mPchThermalConfig; + mPchPolicyData.HpetConfig = &mPchHpetConfig; + mPchPolicyData.SerialIrqConfig = &mSerialIrqConfig; + mPchPolicyData.DmiConfig = &mPchDmiConfig; + mPchPolicyData.PwrOptConfig = &mPchPwrOptConfig; + mPchPolicyData.MiscConfig = &mPchMiscConfig; + mPchPolicyData.AudioDspConfig = &mPchAudioDspConfig; + mPchPolicyData.SerialIoConfig = &mSerialIoConfig; + + // PCH BIOS Spec Section 5.1.1 security recommendations, + // Intel strongly recommends that BIOS sets the BIOS Interface Lock Down bit. Enabling this bit + // will mitigate malicious software attempts to replace the system BIOS option ROM with its own code. + // We always enable this as a platform policy. + mPchPolicyData.LockDownConfig->BiosInterface = gSbSetupData->BiosInterfaceLock; + + // Intel strongly recommends that BIOS enables SMI_LOCK (B0:D31:F0:Offset A0h [4]=1) + // which prevent writes to the Global SMI Enable bit (GLB_SMI_EN PMBASE + 30h Bit + // [0]). Enabling this bit will mitigate malicious software attempts to gain system management + // mode privileges. + // We always enable this as a platform policy. + mPchPolicyData.LockDownConfig->GlobalSmi = gSbSetupData->SmiLock; + + mPchPolicyData.LockDownConfig->GpioLockDown = gSbSetupData->GpioLock; + mPchPolicyData.LockDownConfig->RtcLock = gSbSetupData->RtcLock; + + // + // While BiosLock is enabled, BIOS can only be modified from SMM after ExitPmAuth. + // + mPchPolicyData.LockDownConfig->BiosLock = gSbSetupData->BiosLock; + // [EIP113678] >> + pHit = GetEfiConfigurationTable(pST, &guidHob); +// if (pHit && ((pHit->BootMode == BOOT_IN_RECOVERY_MODE) || \ +// (pHit->BootMode == BOOT_ON_FLASH_UPDATE))) { +// mPchPolicyData.LockDownConfig->BiosLock = 0; +// } + // <<[EIP113678] +// mPchPolicyData.LockDownConfig->PchBiosLockSwSmiNumber = SW_SMI_BIOS_LOCK; // Deprecated from Revision 2 !!! DO NOT USE !!! + mPchPolicyData.LockDownConfig->PchBiosLockIoTrapAddress = 0; // Dynamic updated by IoTrap driver. + + // DeviceEnables + mPchPolicyData.DeviceEnabling->Lan = gSbSetupData->PchLan; + if ((READ_MEM16_RCRB(R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FDV) == B_PCH_SPI_HSFS_FDV) { + if ((PchSpiStrp9 & B_PCH_SPI_STRP9_GBE_PCIE_EN) == 0) { + mPchPolicyData.DeviceEnabling->Lan = PCH_DEVICE_DISABLE; + } + } + mPchPolicyData.DeviceEnabling->Azalia = gSbSetupData->PchAzalia; + mPchPolicyData.DeviceEnabling->Sata = gSbSetupData->PchSata; + mPchPolicyData.DeviceEnabling->Smbus = PCH_DEVICE_ENABLE; + mPchPolicyData.DeviceEnabling->PciClockRun = gSbSetupData->PchPciClockRun; + mPchPolicyData.DeviceEnabling->Display = gSbSetupData->PchDisplay; + mPchPolicyData.DeviceEnabling->Crid = gSbSetupData->PchEnableCrid; + if (PchSeries == PchLp) { + SbPlatformData.LPTType = 1; + mPchPolicyData.DeviceEnabling->SerialIoDma = gSbSetupData->LpssDmaEnable; + mPchPolicyData.DeviceEnabling->SerialIoI2c0 = gSbSetupData->LpssI2c0Enable; + mPchPolicyData.DeviceEnabling->SerialIoI2c1 = gSbSetupData->LpssI2c1Enable; + mPchPolicyData.DeviceEnabling->SerialIoSpi0 = gSbSetupData->LpssSpi0Enable; + mPchPolicyData.DeviceEnabling->SerialIoSpi1 = gSbSetupData->LpssSpi1Enable; + mPchPolicyData.DeviceEnabling->SerialIoUart0 = gSbSetupData->LpssUart0Enable; + mPchPolicyData.DeviceEnabling->SerialIoUart1 = gSbSetupData->LpssUart1Enable; + mPchPolicyData.DeviceEnabling->SerialIoSdio = gSbSetupData->LpssSdioEnable; + mPchPolicyData.DeviceEnabling->AudioDsp = gSbSetupData->ADspEnable; + if( mPchPolicyData.DeviceEnabling->AudioDsp == PCH_DEVICE_ENABLE) + mPchPolicyData.DeviceEnabling->Azalia = PCH_DEVICE_DISABLE; + } else { + SbPlatformData.LPTType = 0; + mPchPolicyData.DeviceEnabling->SerialIoDma = PCH_DEVICE_DISABLE; + mPchPolicyData.DeviceEnabling->SerialIoI2c0 = PCH_DEVICE_DISABLE; + mPchPolicyData.DeviceEnabling->SerialIoI2c1 = PCH_DEVICE_DISABLE; + mPchPolicyData.DeviceEnabling->SerialIoSpi0 = PCH_DEVICE_DISABLE; + mPchPolicyData.DeviceEnabling->SerialIoSpi1 = PCH_DEVICE_DISABLE; + mPchPolicyData.DeviceEnabling->SerialIoUart0 = PCH_DEVICE_DISABLE; + mPchPolicyData.DeviceEnabling->SerialIoUart1 = PCH_DEVICE_DISABLE; + mPchPolicyData.DeviceEnabling->SerialIoSdio = PCH_DEVICE_DISABLE; + mPchPolicyData.DeviceEnabling->AudioDsp = PCH_DEVICE_DISABLE; + } +#if defined iAMT_SUPPORT && iAMT_SUPPORT + mPchPolicyData.UsbConfig->Ehci1Usbr = PCH_DEVICE_DISABLE; //gSbSetupData->KvmEnabled; + mPchPolicyData.UsbConfig->Ehci2Usbr = PCH_DEVICE_DISABLE; //gSbSetupData->KvmEnabled; +#else + mPchPolicyData.UsbConfig->Ehci1Usbr = PCH_DEVICE_DISABLE; + mPchPolicyData.UsbConfig->Ehci2Usbr = PCH_DEVICE_DISABLE; +#endif + +#if defined iME_SUPPORT && iME_SUPPORT + VariableSize = sizeof (MeBiosExtensionSetupData); + Status = pRS->GetVariable ( + EfiMeBiosExtensionSetupName, + &EfiMeBiosExtensionSetupGuid, + NULL, + &VariableSize, + &MeBiosExtensionSetupData ); + if (!EFI_ERROR (Status)) { + mPchPolicyData.UsbConfig->Ehci1Usbr |= (MeBiosExtensionSetupData.KvmEnable & KVM_ENABLE); + mPchPolicyData.UsbConfig->Ehci2Usbr |= (MeBiosExtensionSetupData.KvmEnable & KVM_ENABLE); + } +#endif + + if (PchSeries == PchLp) { + if ((gSbSetupData->PchUsb20[0] == 0) && + (gSbSetupData->PchUsb30Mode == 0)) { + gDisableAllUsbControllers = TRUE; + } + } else { + if ((gSbSetupData->PchUsb20[0] == 0) && + (gSbSetupData->PchUsb20[1] == 0) && + (gSbSetupData->PchUsb30Mode == 0)) { + gDisableAllUsbControllers = TRUE; + } + } + + mPchPolicyData.UsbConfig->Usb20Settings[0].Enable = gSbSetupData->PchUsb20[0]; + if (PchSeries == PchLp) { + mPchPolicyData.UsbConfig->Usb20Settings[1].Enable = PCH_DEVICE_DISABLE; + } else { + mPchPolicyData.UsbConfig->Usb20Settings[1].Enable = gSbSetupData->PchUsb20[1]; + } + + if ((mPchPolicyData.UsbConfig->Usb20Settings[0].Enable == PCH_DEVICE_DISABLE) && + (mPchPolicyData.UsbConfig->Usb20Settings[1].Enable == PCH_DEVICE_DISABLE)) { + // Force enable EHCI#1 & 2 then disable them in InitSbRegsBeforeBoot() + // if all USB controllers are disabled. + // USB Device 29 configuration + mPchPolicyData.UsbConfig->Usb20Settings[0].Enable = PCH_DEVICE_ENABLE; + if (PchSeries != PchLp) { + // USB Device 26 configuration + mPchPolicyData.UsbConfig->Usb20Settings[1].Enable = PCH_DEVICE_ENABLE; + } + } + + mPchPolicyData.UsbConfig->UsbPerPortCtl = gSbSetupData->PchUsbPerPortCtl; + + for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) { + + if (gSbSetupData->PchUsbPerPortCtl != PCH_DEVICE_DISABLE) { + mPchPolicyData.UsbConfig->Port30Settings[PortIndex].Enable = gSbSetupData->PchUsb30Port[PortIndex]; + } else { + mPchPolicyData.UsbConfig->Port30Settings[PortIndex].Enable = PCH_DEVICE_ENABLE; + } + } + for (PortIndex = 0; PortIndex < GetPchUsbMaxPhysicalPortNum (); PortIndex++) { + + if (gSbSetupData->PchUsbPerPortCtl != PCH_DEVICE_DISABLE) { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Enable = gSbSetupData->PchUsbPort[PortIndex]; + } else { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Enable = PCH_DEVICE_ENABLE; + } + + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20PortLength = UsbPortLength[PortIndex]; + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Location = UsbPortLocation[PortIndex]; + + if (PchSeries == PchH) { + mPchPolicyData.UsbConfig->Usb20OverCurrentPins[PortIndex] = UsbOverCurrentMapping[PortIndex]; //[EIP118480] + if (IS_PCH_LPT_LPC_DEVICE_ID_DESKTOP (LpcDeviceId)) { + if (mPchPolicyData.UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationBackPanel) { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 4; //Back Panel + } else { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 3; //Front Panel + } + + if (mPchPolicyData.UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationBackPanel) { + if (mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x80) { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Back Panel, less than 7.9" + } else if (mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x130) { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 3; //Back Panel, 8"-12.9" + } else { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 4; //Back Panel, 13" onward + } + } else { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Front Panel + } + } else if (IS_PCH_LPT_LPC_DEVICE_ID_MOBILE (LpcDeviceId)) { + if (mPchPolicyData.UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationInternalTopology) { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 5; // Internal Topology + } else if (mPchPolicyData.UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationDock) { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 4; // Dock + } else { + if (mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x70) { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 5; //Back Panel, less than 7" + } else { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 6; //Back Panel, 7" onward + } + } + + if (mPchPolicyData.UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationInternalTopology) { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; // Internal Topology + } else if (mPchPolicyData.UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationDock) { + if (mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x50) { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 1; //Dock, less than 5" + } else { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Dock, 5" onward + } + } else { + if (mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x100) { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Back Panel, less than 10" + } else { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 3; //Back Panel, 10" onward + } + } + } + } else if (PchSeries == PchLp) { + mPchPolicyData.UsbConfig->Usb20OverCurrentPins[PortIndex] = ULTUsbOverCurrentMapping[PortIndex]; //[EIP118480] + if ((mPchPolicyData.UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationBackPanel) || + (mPchPolicyData.UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationMiniPciE)) { + if (mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x70) { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 5; //Back Panel, less than 7" + } else { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 6; //Back Panel, 7" onward + } + } else if (mPchPolicyData.UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationDock) { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 4; // Dock + } else { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 5; // Internal Topology + } + + if ((mPchPolicyData.UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationBackPanel) || + (mPchPolicyData.UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationMiniPciE)) { + if (mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x100) { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Back Panel, less than 10" + } else { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 3; //Back Panel, 10" onward + } + } else if (mPchPolicyData.UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationDock) { + if (mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x50) { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 1; //Dock, less than 5" + } else { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Dock, 5" onward + } + } else { + mPchPolicyData.UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; // Internal Topology + } + } + } + + // + // PCH BIOS Spec Section 13.1 xHCI controller options in Reference Code + // Please refer to Table 13-1 in PCH BIOS Spec for USB Port Operation with no xHCI + // pre-boot software. + // Please refer to Table 13-2 in PCH BIOS Spec for USB Port Operation with xHCI + // pre-boot software. + // + // The xHCI modes that available in BIOS are: + // Disabled - forces only USB 2.0 to be supported in the OS. The xHCI controller is turned off + // and hidden from the PCI space. + // Enabled - allows USB 3.0 to be supported in the OS. The xHCI controller is turned on. The + // shareable ports are routed to the xHCI controller. OS needs to provide drivers + // to support USB 3.0. + // Auto - This mode uses ACPI protocol to provide an option that enables the xHCI controller + // and reroute USB ports via the _OSC ACPI method call. Note, this mode switch requires + // special OS driver support for USB 3.0. + // Smart Auto - This mode is similar to Auto, but it adds the capability to route the ports to xHCI + // or EHCI according to setting used in previous boots (for non-G3 boot) in the pre-boot + // environment. This allows the use of USB 3.0 devices prior to OS boot. Note, this mode + // switch requires special OS driver support for USB 3.0 and USB 3.0 software available + // in the pre-boot enviroment. + // Recommendations: + // - If BIOS supports xHCI pre-boot driver then use Smart Auto mode as default + // - If BIOS does not support xHCI pre-boot driver then use AUTO mode as default + // + mPchPolicyData.UsbConfig->Usb30Settings.Mode = gSbSetupData->PchUsb30Mode; + + // + // Automatically disable EHCI when XHCI Mode is Enabled to save power. + // + if (mPchPolicyData.UsbConfig->Usb30Settings.Mode == 1) { + mPchPolicyData.UsbConfig->Usb20Settings[0].Enable = PCH_DEVICE_DISABLE; + if (PchSeries == PchH) { + mPchPolicyData.UsbConfig->Usb20Settings[1].Enable = PCH_DEVICE_DISABLE; + } + } + + if (gSbSetupData->PchUsb30Mode == 3) { + mPchPolicyData.UsbConfig->Usb30Settings.PreBootSupport = 1; + } else { + mPchPolicyData.UsbConfig->Usb30Settings.PreBootSupport = gSbSetupData->PchUsb30PreBootSupport; + } +// mPchPolicyData.UsbConfig->Usb30Settings.XhciStreams = gSbSetupData->XhciStreams; + + if (gSbSetupData->PchUsb30Mode == 4) { + mPchPolicyData.UsbConfig->Usb30Settings.Mode = 2; + mPchPolicyData.UsbConfig->Usb30Settings.ManualMode = PCH_DEVICE_ENABLE; + } else { + mPchPolicyData.UsbConfig->Usb30Settings.ManualMode = PCH_DEVICE_DISABLE; + } + + // + // XhciIdleL1 can be set to disable for LPT-LP Ax stepping to workaround USB3 hot plug will fail after 1 hot plug removal. + // + mPchPolicyData.UsbConfig->Usb30Settings.XhciIdleL1 = gSbSetupData->PchUsb30IdleL1; + + // + // Btcg is for enabling/disabling trunk clock gating. + // + mPchPolicyData.UsbConfig->Usb30Settings.Btcg = gSbSetupData->PchUsb30Btcg; + + for (PortIndex = 0; PortIndex < GetPchUsbMaxPhysicalPortNum (); PortIndex++) { + if (gSbSetupData->PchUsb20PinRoute == 1){ + mPchPolicyData.UsbConfig->Usb30Settings.ManualModeUsb20PerPinRoute[PortIndex] = 0; + } else if (gSbSetupData->PchUsb20PinRoute == 2){ + mPchPolicyData.UsbConfig->Usb30Settings.ManualModeUsb20PerPinRoute[PortIndex] = 1; + } else { + mPchPolicyData.UsbConfig->Usb30Settings.ManualModeUsb20PerPinRoute[PortIndex] = gSbSetupData->ManualModeUsb20PerPinRoute[PortIndex]; + } + } + + for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) { + if (gSbSetupData->PchUsb30PinEnable == 1){ + mPchPolicyData.UsbConfig->Usb30Settings.ManualModeUsb30PerPinEnable[PortIndex] = 0; + } else if (gSbSetupData->PchUsb30PinEnable == 2){ + mPchPolicyData.UsbConfig->Usb30Settings.ManualModeUsb30PerPinEnable[PortIndex] = 1; + } else { + mPchPolicyData.UsbConfig->Usb30Settings.ManualModeUsb30PerPinEnable[PortIndex] = gSbSetupData->ManualModeUsb30PerPinEnable[PortIndex]; + } + mPchPolicyData.UsbConfig->Usb30OverCurrentPins[PortIndex] = Usb30OverCurrentMapping[PortIndex]; + } + mPchPolicyData.UsbConfig->UsbPrecondition = gSbSetupData->UsbPrecondition; + +#ifdef USB_PRECONDITION_ENABLE_FLAG + /// + /// Update Precondition option for S4 resume. + /// Skip Precondition for S4 resume in case this boot may not connect BIOS USB driver. + /// If BIOS USB driver will be connected always for S4, then disable below update. + /// To keep consistency during boot, must enabled or disabled below function in both PEI and DXE + /// PlatformPolicyInit driver. + /// + if (mPchUsbConfig.UsbPrecondition == TRUE) { + if (pHit && (pHit->BootMode == BOOT_ON_S4_RESUME)) { + mPchUsbConfig.UsbPrecondition = FALSE; + TRACE((-1, "BootMode is BOOT_ON_S4_RESUME, disable Precondition\n")); + } + } +#endif // USB_PRECONDITION_ENABLE_FLAG + + GlobalNvsArea->Area->XhciMode = (UINT8)gSbSetupData->PchUsb30Mode; + + // PCI Express related settings from setup variable + mPchPolicyData.PciExpressConfig->RootPortClockGating = gSbSetupData->PcieClockGating; + mPchPolicyData.PciExpressConfig->DevAspmOverride = mDevAspmOverride; + mPchPolicyData.PciExpressConfig->NumOfDevAspmOverride = sizeof (mDevAspmOverride) / sizeof (PCH_PCIE_DEVICE_ASPM_OVERRIDE); + mPchPolicyData.PciExpressConfig->RootPortFunctionSwapping = gSbSetupData->RootPortFunctionSwapping; + + mPchPolicyData.PciExpressConfig->TempRootPortBusNumMin = PCH_PCIE_TEMP_RP_BUS_NUM_MIN; + mPchPolicyData.PciExpressConfig->TempRootPortBusNumMax = PCH_PCIE_TEMP_RP_BUS_NUM_MAX; + + for (PortIndex = 0; PortIndex < GetPchMaxPciePortNum (); PortIndex++) { +#if defined(RC_PORT_0) && (RC_PORT_0 == 1) + if (PcieRPMap[PortIndex]) + mPchPolicyData.PciExpressConfig->RootPort[PortIndex].Enable = gSbSetupData->PcieRootPortEn[PortIndex]; + else +#endif + mPchPolicyData.PciExpressConfig->RootPort[PortIndex].Enable = PCH_DEVICE_DISABLE; + + mPchPolicyData.PciExpressConfig->RootPort[PortIndex].SlotImplemented = gSbSetupData->PcieRootPortEn[PortIndex]; + mPchPolicyData.PciExpressConfig->RootPort[PortIndex].FunctionNumber = PortIndex; + mPchPolicyData.PciExpressConfig->RootPort[PortIndex].PhysicalSlotNumber = PortIndex; + mPchPolicyData.PciExpressConfig->RootPort[PortIndex].Aspm = gSbSetupData->PcieRootPortAspm[PortIndex]; + mPchPolicyData.PciExpressConfig->RootPort[PortIndex].PmSci = gSbSetupData->PcieRootPortPMCE[PortIndex]; + mPchPolicyData.PciExpressConfig->RootPort[PortIndex].HotPlug = gSbSetupData->PcieRootPortHPE[PortIndex]; + mPchPolicyData.PciExpressConfig->RootPort[PortIndex].AdvancedErrorReporting = PCH_PCIE_ADVANCED_ERROR_REPORTING; + mPchPolicyData.PciExpressConfig->RootPort[PortIndex].UnsupportedRequestReport = gSbSetupData->PcieRootPortURE[PortIndex]; + mPchPolicyData.PciExpressConfig->RootPort[PortIndex].FatalErrorReport = gSbSetupData->PcieRootPortFEE[PortIndex]; + mPchPolicyData.PciExpressConfig->RootPort[PortIndex].NoFatalErrorReport = gSbSetupData->PcieRootPortNFE[PortIndex]; + mPchPolicyData.PciExpressConfig->RootPort[PortIndex].CorrectableErrorReport = gSbSetupData->PcieRootPortCEE[PortIndex]; + mPchPolicyData.PciExpressConfig->RootPort[PortIndex].PmeInterrupt = PCH_PCIE_PME_INTERRUPT; + mPchPolicyData.PciExpressConfig->RootPort[PortIndex].SystemErrorOnFatalError = gSbSetupData->PcieRootPortSFE[PortIndex]; + mPchPolicyData.PciExpressConfig->RootPort[PortIndex].SystemErrorOnNonFatalError = gSbSetupData->PcieRootPortSNE[PortIndex]; + mPchPolicyData.PciExpressConfig->RootPort[PortIndex].SystemErrorOnCorrectableError = gSbSetupData->PcieRootPortSCE[PortIndex]; + mPchPolicyData.PciExpressConfig->RootPort[PortIndex].CompletionTimeout = PCH_PCIE_COMPLETION_TIME_OUT; + mPchPolicyData.PciExpressConfig->RootPort[PortIndex].L1Substates = gSbSetupData->PcieRootPortL1S[PortIndex]; + } + + if (SbPlatformData.PcieSBDE) { + mPchPolicyData.PciExpressConfig->EnableSubDecode = gSbSetupData->PcieRootPortSBDE; + mPchPolicyData.PciExpressConfig->PchPcieSbdePort = gSbSetupData->PcieSBDEPort; + } else { + mPchPolicyData.PciExpressConfig->EnableSubDecode = PCH_DEVICE_DISABLE; + mPchPolicyData.PciExpressConfig->PchPcieSbdePort = 0; + } + + // SATA configuration + for (PortIndex = 0; PortIndex < GetPchMaxSataPortNum (); PortIndex++) { + if ((gSbSetupData->SataInterfaceMode) == 0) { // for IDE + mPchPolicyData.SataConfig->PortSettings[PortIndex].Enable = PCH_DEVICE_ENABLE; + } else { + mPchPolicyData.SataConfig->PortSettings[PortIndex].Enable = gSbSetupData->SataPort[PortIndex]; + } + + mPchPolicyData.SataConfig->PortSettings[PortIndex].HotPlug = gSbSetupData->SataHotPlug[PortIndex]; + mPchPolicyData.SataConfig->PortSettings[PortIndex].InterlockSw = gSbSetupData->SataMechanicalSw[PortIndex]; + mPchPolicyData.SataConfig->PortSettings[PortIndex].External = gSbSetupData->ExternalSata[PortIndex]; + mPchPolicyData.SataConfig->PortSettings[PortIndex].SolidStateDrive = gSbSetupData->SolidStateDrive[PortIndex]; + mPchPolicyData.SataConfig->PortSettings[PortIndex].SpinUp = gSbSetupData->SataSpinUp[PortIndex]; + mPchPolicyData.SataConfig->PortSettings[PortIndex].DevSlp = gSbSetupData->SataDevSlp[PortIndex]; + mPchPolicyData.SataConfig->PortSettings[PortIndex].EnableDitoConfig = gSbSetupData->EnableDitoConfig[PortIndex]; + mPchPolicyData.SataConfig->PortSettings[PortIndex].DmVal = gSbSetupData->DmVal[PortIndex]; + mPchPolicyData.SataConfig->PortSettings[PortIndex].DitoVal = gSbSetupData->DitoVal[PortIndex]; + } + GlobalNvsArea->Area->DVS0 = gSbSetupData->SataDevSlp[0]; + GlobalNvsArea->Area->DVS1 = gSbSetupData->SataDevSlp[1]; + GlobalNvsArea->Area->DVS2 = gSbSetupData->SataDevSlp[2]; + GlobalNvsArea->Area->DVS3 = gSbSetupData->SataDevSlp[3]; + + mPchPolicyData.SataConfig->RaidAlternateId = gSbSetupData->SataAlternateId; + mPchPolicyData.SataConfig->Raid0 = gSbSetupData->SataRaidR0; + mPchPolicyData.SataConfig->Raid1 = gSbSetupData->SataRaidR1; + mPchPolicyData.SataConfig->Raid10 = gSbSetupData->SataRaidR10; + mPchPolicyData.SataConfig->Raid5 = gSbSetupData->SataRaidR5; + mPchPolicyData.SataConfig->Irrt = gSbSetupData->SataRaidIrrt; + mPchPolicyData.SataConfig->OromUiBanner = gSbSetupData->SataRaidOub; + mPchPolicyData.SataConfig->HddUnlock = gSbSetupData->SataHddlk; + mPchPolicyData.SataConfig->LedLocate = gSbSetupData->SataLedl; + mPchPolicyData.SataConfig->IrrtOnly = gSbSetupData->SataRaidIooe; + mPchPolicyData.SataConfig->SmartStorage = gSbSetupData->SmartStorage; + mPchPolicyData.SataConfig->OromUiDelay = gSbSetupData->OromUiDelay; + mPchPolicyData.SataConfig->TestMode = gSbSetupData->SataTestMode; + mPchPolicyData.SataConfig->SalpSupport = gSbSetupData->SalpSupport; + mPchPolicyData.SataConfig->LegacyMode = PCH_DEVICE_DISABLE; + mPchPolicyData.SataConfig->SpeedSupport = gSbSetupData->SataControllerSpeed; + + // AzaliaConfig + mPchPolicyData.AzaliaConfig->Pme = gSbSetupData->AzaliaPme; + mPchPolicyData.AzaliaConfig->DS = gSbSetupData->AzaliaDs; + + if (!IS_PCH_LPT_LPC_DEVICE_ID_MOBILE (LpcDeviceId)) { + // These boards do not have KSC - set Azalia as "Not Docked" + mPchPolicyData.AzaliaConfig->DA = 0; + } else { + // Call KSC lib to get dock status +#if defined INTEL_CRB_DXE_KSC_LIB_SUPPORT && INTEL_CRB_DXE_KSC_LIB_SUPPORT +#if defined CRB_EC_SUPPORT && CRB_EC_SUPPORT + if (mPchPolicyData.AzaliaConfig->DS == PCH_DEVICE_ENABLE) { + InitializeKscLib (); + Status = SendKscCommand (KSC_C_DOCK_STATUS); + if (Status == EFI_SUCCESS) { + Status = ReceiveKscData ((UINT8 *) &PortDataOut); + if (PortDataOut & KSC_B_DOCK_STATUS_ATTACH) { + + // Bit 0 is dock status: 1 = docked + mPchPolicyData.AzaliaConfig->DA = 1; + } else { + mPchPolicyData.AzaliaConfig->DA = 0; + } + } + } +#endif +#endif + } + + mPchPolicyData.AzaliaConfig->AzaliaVerbTableNum = sizeof (HdaVerbTbl) / sizeof (PCH_AZALIA_VERB_TABLE); + mPchPolicyData.AzaliaConfig->AzaliaVerbTable = (PCH_AZALIA_VERB_TABLE*)HdaVerbTbl; + mPchPolicyData.AzaliaConfig->ResetWaitTimer = HDA_RESET_WAIT_TIMER; + + // Reserved SMBus Address + mPchPolicyData.SmbusConfig->NumRsvdSmbusAddresses = DIMM_SLOT_NUM; + mPchPolicyData.SmbusConfig->RsvdSmbusAddressTable = mSmbusRsvdAddresses; + + // MiscPm Configuration + if (IS_PCH_LPT_LPC_DEVICE_ID_MOBILE (LpcDeviceId)) { + mPchPolicyData.MiscPmConfig->PchDeepSxPol = gSbSetupData->DeepSxBattMode; + if (gSbSetupData->BoardCapability == 0) + mPchPolicyData.MiscPmConfig->PchDeepSxPol = PchDeepSxPolDisable; + } else { + mPchPolicyData.MiscPmConfig->PchDeepSxPol = gSbSetupData->DeepSxMode; + } + + // [EIP82149]> + // Intel(R) 8 Series Chipset Family Deep Sx and CPU Soft-Strap BIOS Override Co-Existence Issue. + // If the soft-strap override feature is required and enabled, BIOS must disable Deep Sx functionality. + if (READ_MEM32_RCRB(R_PCH_SPI_SRD) & B_PCH_SPI_SRD_SSD) { + mPchPolicyData.MiscPmConfig->PchDeepSxPol = PchDeepSxPolDisable; + SbPlatformData.HideDeepSx = 1; + } + // <[EIP82149] + + mPchPolicyData.MiscPmConfig->WakeConfig.PmeB0S5Dis = PCH_DEVICE_DISABLE; + mPchPolicyData.MiscPmConfig->WakeConfig.WolEnableOverride = gSbSetupData->PchWakeOnLan; + mPchPolicyData.MiscPmConfig->WakeConfig.Gp27WakeFromDeepSx = gSbSetupData->Gp27Wake; + mPchPolicyData.MiscPmConfig->WakeConfig.PcieWakeFromDeepSx = gSbSetupData->PcieWake; + mPchPolicyData.MiscPmConfig->PowerResetStatusClear.MeWakeSts = ME_WAKE_STS; + mPchPolicyData.MiscPmConfig->PowerResetStatusClear.MeHrstColdSts = ME_HRST_COLD_STS; + mPchPolicyData.MiscPmConfig->PowerResetStatusClear.MeHrstWarmSts = ME_HRST_WARM_STS; + mPchPolicyData.MiscPmConfig->PchSlpS3MinAssert = PCH_SLP_S3_MIN_ASSERT_VALUE; + mPchPolicyData.MiscPmConfig->PchSlpS4MinAssert = gSbSetupData->SlpS4AssW; + mPchPolicyData.MiscPmConfig->PchSlpSusMinAssert = PCH_SLP_SUS_MIN_ASSERT_VALUE; + mPchPolicyData.MiscPmConfig->PchSlpAMinAssert = PCH_SLPA_MIN_ASSERT_VALUE; + mPchPolicyData.MiscPmConfig->PchPwrCycDur = PCH_RESET_CYCLE_DURATION; // 4-5 seconds (PCH default setting) + mPchPolicyData.MiscPmConfig->SlpStrchSusUp = SLP_STRCH_SUS_UP; + mPchPolicyData.MiscPmConfig->SlpLanLowDc = gSbSetupData->SlpLanLow; + + // Thermal configuration - Initialize policy to SETUP values. + mPchPolicyData.ThermalConfig->ThermalAlertEnable.TselLock = PCH_DEVICE_ENABLE; +// mPchPolicyData.ThermalConfig->ThermalAlertEnable.TspcLock = gSbSetupData->TSPCLock; // Deprecated from Revision 2 !!! DO NOT USE !!! + mPchPolicyData.ThermalConfig->ThermalAlertEnable.TscLock = PCH_DEVICE_ENABLE; + mPchPolicyData.ThermalConfig->ThermalAlertEnable.TsmicLock = PCH_DEVICE_ENABLE; + mPchPolicyData.ThermalConfig->ThermalAlertEnable.PhlcLock = PCH_DEVICE_ENABLE; + + mPchPolicyData.ThermalConfig->ThermalThrottling.TTLevels.SuggestedSetting = TTLEVELS_SUGGEST; + mPchPolicyData.ThermalConfig->ThermalThrottling.TTLevels.PchCrossThrottling = gSbSetupData->PchCrossThrottling; + mPchPolicyData.ThermalConfig->ThermalThrottling.DmiHaAWC.SuggestedSetting = DMIHAAWC_SUGGEST; + mPchPolicyData.ThermalConfig->ThermalThrottling.SataTT.SuggestedSetting = SATATT_SUGGEST; + mPchPolicyData.ThermalConfig->PchHotLevel = gSbSetupData->PchHotLevel;; + + // PCH thermal device D31:F6 needs to be enabled for DPPM or validation. + mPchPolicyData.ThermalConfig->ThermalDeviceEnable = gSbSetupData->ThermalDeviceEnable; + + if (mPchPolicyData.DeviceEnabling->Lan != PCH_DEVICE_ENABLE) + SbPlatformData.GbePciePortNum = 0xff; + + // Set IOAPIC BDF + mPchPolicyData.IoApicConfig->BdfValid = 1; + mPchPolicyData.IoApicConfig->BusNumber = 0xF0; + mPchPolicyData.IoApicConfig->DeviceNumber = 0x1F; + mPchPolicyData.IoApicConfig->FunctionNumber = 0; + mPchPolicyData.IoApicConfig->IoApicEntry24_39 = PCH_DEVICE_ENABLE; + + // Set HPET BDF + mPchPolicyData.HpetConfig->BdfValid = 1; + for (PortIndex=0; PortIndex<PCH_HPET_BDF_MAX; PortIndex++) { + mPchPolicyData.HpetConfig->Hpet[PortIndex].BusNumber = 0xF0; + mPchPolicyData.HpetConfig->Hpet[PortIndex].DeviceNumber = 0x0F; + mPchPolicyData.HpetConfig->Hpet[PortIndex].FunctionNumber = 0; + } + + // Initialize Serial IRQ Config + mPchPolicyData.SerialIrqConfig->SirqEnable = SIRQ_ENABLE; + mPchPolicyData.SerialIrqConfig->StartFramePulse = SIRQ_START_FRAME_PULSE; + mPchPolicyData.SerialIrqConfig->SirqMode = gSbSetupData->SirqMode; + + // Set these two policies to 0 for skip ProgramSvidSid(). (PchInit.c) + // ULT_SUBID>> + // SB SSID programming has done in ProgramSBSubId(). (SBPEI.c) + + mPchPolicyData.DefaultSvidSid->SubSystemVendorId = 0; + mPchPolicyData.DefaultSvidSid->SubSystemId = 0; + // <<ULT_SUBID + + // + // DMI related settings + // + mPchPolicyData.DmiConfig->DmiAspm = gSbSetupData->PchDmiAspm; + mPchPolicyData.DmiConfig->DmiExtSync = gSbSetupData->PchDmiExtSync; + mPchPolicyData.DmiConfig->DmiIot = PCH_DEVICE_DISABLE; + /// + /// Power Optimizer related settings + /// + mPchPolicyData.PwrOptConfig->PchPwrOptDmi = PCH_PWR_OPT_DMI; + mPchPolicyData.PwrOptConfig->PchPwrOptGbe = PCH_PWR_OPT_GBE; + mPchPolicyData.PwrOptConfig->PchPwrOptXhci = PCH_PWR_OPT_XHCI; + mPchPolicyData.PwrOptConfig->PchPwrOptEhci = PCH_PWR_OPT_EHCI; + mPchPolicyData.PwrOptConfig->PchPwrOptSata = PCH_PWR_OPT_SATA; + mPchPolicyData.PwrOptConfig->MemCloseStateEn = MEM_CLOSE_STATE_EN; + mPchPolicyData.PwrOptConfig->InternalObffEn = INTERNAL_OBFF_EN; + mPchPolicyData.PwrOptConfig->ExternalObffEn = PCH_DEVICE_DISABLE; // De-feature OBFF from LPT-H/LPT-LP.(RC v1.2.0) + mPchPolicyData.PwrOptConfig->NumOfDevLtrOverride = NUM_OF_DEVLTR_OVERRID; +#if defined DEVLTR_OVERRID && DEVLTR_OVERRID == 1 + mPchPolicyData.PwrOptConfig->DevLtrOverride = 1; +#else + mPchPolicyData.PwrOptConfig->DevLtrOverride = NULL; +#endif + for (PortIndex = 0; PortIndex < GetPchMaxPciePortNum (); PortIndex++) { + mPchPolicyData.PwrOptConfig->PchPwrOptPcie[PortIndex].LtrEnable = gSbSetupData->PcieLtrEnable[PortIndex]; + // + // De-feature OBFF from LPT-H/LPT-LP. + // Doesn't enable Obff policy anymore. + // + mPchPolicyData.PwrOptConfig->PchPwrOptPcie[PortIndex].ObffEnable = PCH_DEVICE_DISABLE; + } + + GlobalNvsArea->Area->LTRE1 = gSbSetupData->PcieLtrEnable[0]; + GlobalNvsArea->Area->LTRE2 = gSbSetupData->PcieLtrEnable[1]; + GlobalNvsArea->Area->LTRE3 = gSbSetupData->PcieLtrEnable[2]; + GlobalNvsArea->Area->LTRE4 = gSbSetupData->PcieLtrEnable[3]; + GlobalNvsArea->Area->LTRE5 = gSbSetupData->PcieLtrEnable[4]; + GlobalNvsArea->Area->LTRE6 = gSbSetupData->PcieLtrEnable[5]; + GlobalNvsArea->Area->LTRE7 = gSbSetupData->PcieLtrEnable[6]; + GlobalNvsArea->Area->LTRE8 = gSbSetupData->PcieLtrEnable[7]; + + mPchPolicyData.PwrOptConfig->LegacyDmaDisable = LEGACY_DMA_DISABLE; + for (PortIndex = 0; PortIndex < GetPchMaxPciePortNum (); PortIndex++) { + if (PchSeries == PchLp) { + mPchPolicyData.PwrOptConfig->PchPwrOptPcie[PortIndex].LtrMaxSnoopLatency = 0x1003; + mPchPolicyData.PwrOptConfig->PchPwrOptPcie[PortIndex].LtrMaxNoSnoopLatency = 0x1003; + } + if (PchSeries == PchH) { + mPchPolicyData.PwrOptConfig->PchPwrOptPcie[PortIndex].LtrMaxSnoopLatency = 0x0846; + mPchPolicyData.PwrOptConfig->PchPwrOptPcie[PortIndex].LtrMaxNoSnoopLatency = 0x0846; + } + mPchPolicyData.PwrOptConfig->PchPwrOptPcie[PortIndex].LtrConfigLock = gSbSetupData->PcieLtrConfigLock[PortIndex]; + mPchPolicyData.PwrOptConfig->PchPwrOptPcie[PortIndex].SnoopLatencyOverrideMode = gSbSetupData->PcieSnoopLatencyOverrideMode[PortIndex]; + mPchPolicyData.PwrOptConfig->PchPwrOptPcie[PortIndex].SnoopLatencyOverrideMultiplier = gSbSetupData->PcieSnoopLatencyOverrideMultiplier[PortIndex]; + mPchPolicyData.PwrOptConfig->PchPwrOptPcie[PortIndex].SnoopLatencyOverrideValue = gSbSetupData->PcieSnoopLatencyOverrideValue[PortIndex]; + mPchPolicyData.PwrOptConfig->PchPwrOptPcie[PortIndex].NonSnoopLatencyOverrideMode = gSbSetupData->PcieNonSnoopLatencyOverrideMode[PortIndex]; + mPchPolicyData.PwrOptConfig->PchPwrOptPcie[PortIndex].NonSnoopLatencyOverrideMultiplier = gSbSetupData->PcieNonSnoopLatencyOverrideMultiplier[PortIndex]; + mPchPolicyData.PwrOptConfig->PchPwrOptPcie[PortIndex].NonSnoopLatencyOverrideValue = gSbSetupData->PcieNonSnoopLatencyOverrideValue[PortIndex]; + } + /// + /// Interrupt Settings + /// + mPchPolicyData.IoApicConfig->IoApicEntry24_39 = PCH_DEVICE_ENABLE; + + /// + /// Misc. Config + /// + /// FviSmbiosType is the SMBIOS OEM type (0x80 to 0xFF) defined in SMBIOS Type 14 - Group + /// Associations structure - item type. FVI structure uses it as SMBIOS OEM type to provide + /// version information. The default value is type 221. + /// + mPchPolicyData.MiscConfig->FviSmbiosType = 0xDD; + + /// + /// DCI (Direct Connect Interface) Configuration + /// + mPchPolicyData.MiscConfig->DciEn = PCH_DEVICE_DISABLE; + + mPchPolicyData.AudioDspConfig->AudioDspD3PowerGating = gSbSetupData->ADspD3PG; + GlobalNvsArea->Area->AudioDspCodec = (UINT8)gSbSetupData->ADspCodecSelect; + mPchPolicyData.AudioDspConfig->AudioDspBluetoothSupport = gSbSetupData->ADspBluetooth; + mPchPolicyData.AudioDspConfig->AudioDspAcpiMode = gSbSetupData->ADspMode; //1: ACPI mode, 0: PCI mode + mPchPolicyData.AudioDspConfig->AudioDspAcpiInterruptMode = !(gSbSetupData->LpssIntMode); //1: ACPI mode, 0: PCI mode + mPchPolicyData.AudioDspConfig->AudioDspBluetoothSupport = PCH_DEVICE_DISABLE; // Bluetooth SCO disabled + + mPchPolicyData.SerialIoConfig->SerialIoMode = gSbSetupData->LpssMode; + mPchPolicyData.SerialIoConfig->SerialIoInterruptMode = gSbSetupData->LpssIntMode; + mPchPolicyData.SerialIoConfig->Ddr50Support = PCH_DEVICE_DISABLE; + mPchPolicyData.SerialIoConfig->I2c0VoltageSelect = gSbSetupData->I2C0VoltageSelect; + mPchPolicyData.SerialIoConfig->I2c1VoltageSelect = gSbSetupData->I2C1VoltageSelect; + if(gSbSetupData->SensorHub){ + GlobalNvsArea->Area->SDS0 = GlobalNvsArea->Area->SDS0 | BIT0; + } + if(gSbSetupData->TPD4){ + GlobalNvsArea->Area->SDS0 = GlobalNvsArea->Area->SDS0 | BIT2; + } + if(gSbSetupData->AtmelTPL){ + GlobalNvsArea->Area->SDS1 = GlobalNvsArea->Area->SDS1 | BIT0; + } + if(gSbSetupData->ElanTPL){ + GlobalNvsArea->Area->SDS1 = GlobalNvsArea->Area->SDS1 | BIT1; + } + if(gSbSetupData->ElanTPD){ + GlobalNvsArea->Area->SDS1 = GlobalNvsArea->Area->SDS1 | BIT2; + } + if(gSbSetupData->SynaTPD){ + GlobalNvsArea->Area->SDS1 = GlobalNvsArea->Area->SDS1 | BIT3; + } + if(gSbSetupData->NtriTPL){ + GlobalNvsArea->Area->SDS1 = GlobalNvsArea->Area->SDS1 | BIT5; + } + if(gSbSetupData->EetiTPL){ + GlobalNvsArea->Area->SDS1 = GlobalNvsArea->Area->SDS1 | BIT6; + } + if(gSbSetupData->AlpsTPD){ + GlobalNvsArea->Area->SDS1 = GlobalNvsArea->Area->SDS1 | BIT7; + } + if(gSbSetupData->CyprTPD){ + GlobalNvsArea->Area->SDS1 = GlobalNvsArea->Area->SDS1 | BIT8; + } + if(gSbSetupData->LpssI2c0Enable){ + GlobalNvsArea->Area->PEPC = GlobalNvsArea->Area->PEPC | BIT5; + } + if(gSbSetupData->LpssI2c1Enable){ + GlobalNvsArea->Area->PEPC = GlobalNvsArea->Area->PEPC | BIT6; + } + if(gSbSetupData->LpssUart0Enable){ + GlobalNvsArea->Area->PEPC = GlobalNvsArea->Area->PEPC | BIT2; + } + if(gSbSetupData->LpssUart1Enable){ + GlobalNvsArea->Area->PEPC = GlobalNvsArea->Area->PEPC | BIT3; + } + if(gSbSetupData->LpssSdioEnable){ + GlobalNvsArea->Area->PEPC = GlobalNvsArea->Area->PEPC | BIT4; + } + if(gSbSetupData->ADspEnable){ + GlobalNvsArea->Area->PEPC = GlobalNvsArea->Area->PEPC | BIT9; + } + if(gSbSetupData->PchAzalia){ + GlobalNvsArea->Area->PEPC = GlobalNvsArea->Area->PEPC | BIT8; + } + if(gSbSetupData->PchUsb30Mode != 0){ + GlobalNvsArea->Area->PEPC = GlobalNvsArea->Area->PEPC | BIT7; + } + GlobalNvsArea->Area->DOSD = gSbSetupData->LpssDmaEnable; + GlobalNvsArea->Area->SDS4 = gSbSetupData->Bluetooth0; + GlobalNvsArea->Area->SDS5 = gSbSetupData->Bluetooth1; + + GlobalNvsArea->Area->SSH0 = gSbSetupData->I2C0SSH; + GlobalNvsArea->Area->SSL0 = gSbSetupData->I2C0SSL; + GlobalNvsArea->Area->SSD0 = gSbSetupData->I2C0SSD; + GlobalNvsArea->Area->FMH0 = gSbSetupData->I2C0FMH; + GlobalNvsArea->Area->FML0 = gSbSetupData->I2C0FML; + GlobalNvsArea->Area->FMD0 = gSbSetupData->I2C0FMD; + GlobalNvsArea->Area->FPH0 = gSbSetupData->I2C0FPH; + GlobalNvsArea->Area->FPL0 = gSbSetupData->I2C0FPL; + GlobalNvsArea->Area->FPD0 = gSbSetupData->I2C0FPD; + GlobalNvsArea->Area->M0C0 = gSbSetupData->I2C0M0C0; + GlobalNvsArea->Area->M1C0 = gSbSetupData->I2C0M1C0; + GlobalNvsArea->Area->M2C0 = gSbSetupData->I2C0M2C0; + + GlobalNvsArea->Area->SSH1 = gSbSetupData->I2C1SSH; + GlobalNvsArea->Area->SSL1 = gSbSetupData->I2C1SSL; + GlobalNvsArea->Area->SSD1 = gSbSetupData->I2C1SSD; + GlobalNvsArea->Area->FMH1 = gSbSetupData->I2C1FMH; + GlobalNvsArea->Area->FML1 = gSbSetupData->I2C1FML; + GlobalNvsArea->Area->FMD1 = gSbSetupData->I2C1FMD; + GlobalNvsArea->Area->FPH1 = gSbSetupData->I2C1FPH; + GlobalNvsArea->Area->FPL1 = gSbSetupData->I2C1FPL; + GlobalNvsArea->Area->FPD1 = gSbSetupData->I2C1FPD; + GlobalNvsArea->Area->M0C1 = gSbSetupData->I2C1M0C1; + GlobalNvsArea->Area->M1C1 = gSbSetupData->I2C1M1C1; + GlobalNvsArea->Area->M2C1 = gSbSetupData->I2C1M2C1; + + GlobalNvsArea->Area->M0C2 = gSbSetupData->SPI0M0C2; + GlobalNvsArea->Area->M1C2 = gSbSetupData->SPI0M1C2; + + GlobalNvsArea->Area->M0C3 = gSbSetupData->SPI1M0C3; + GlobalNvsArea->Area->M1C3 = gSbSetupData->SPI1M1C3; + + GlobalNvsArea->Area->M0C4 = gSbSetupData->UAR0M0C4; + GlobalNvsArea->Area->M1C4 = gSbSetupData->UAR0M1C4; + + GlobalNvsArea->Area->M0C5 = gSbSetupData->UAR1M0C5; + GlobalNvsArea->Area->M1C5 = gSbSetupData->UAR1M1C5; + + GlobalNvsArea->Area->ECTG = gSbSetupData->ECTG; + + SbPlatformData.PchRid = READ_PCI8_SB(R_PCH_LPC_RID); + + // Save SB PLATFORM DATA variables. + Status = pRS->SetVariable ( + L"SbPlatformData", + &SetupGuid, + EFI_VARIABLE_BOOTSERVICE_ACCESS, + sizeof (SB_PLATFORM_DATA), + &SbPlatformData + ); + ASSERT_EFI_ERROR (Status); + +#if (defined SB_SETUP_SUPPORT && SB_SETUP_SUPPORT) || \ + (defined OEM_SB_SETUP_SUPPORT && OEM_SB_SETUP_SUPPORT) + SetupData.TrEnabled = gSbSetupData->TrEnabled; +#endif + + Status = pRS->SetVariable ( + L"Setup", + &SetupGuid, + SetupDataAttributes, + sizeof (SETUP_DATA), + &SetupData + ); + ASSERT_EFI_ERROR (Status); + + Handle = NULL; + Status = pBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gDxePchPlatformPolicyProtocolGuid, + &mPchPolicyData, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: RaidGetDriver +// +// Description: Get the the DriverImage Handle order to Start the +// Raid Controller handle +// +// Input: This - EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL +// DriverImageHandle - Driver Image Handle +// +// Output: DriverImageHandle - Returns the Driver Image handle +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS RaidGetDriver( + IN EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL *This, + IN OUT EFI_HANDLE *DriverImageHandle +) +{ + UINTN HandleCount; + EFI_HANDLE *HandleBuffer=NULL; + UINTN Index; + EFI_LOADED_IMAGE_PROTOCOL *LoadedImage; + EFI_DRIVER_BINDING_PROTOCOL *DriverBindingProtocol=NULL; + EFI_GUID gEfiLoadedImageGuid = EFI_LOADED_IMAGE_PROTOCOL_GUID; + static UINT8 GuidCount=0; + EFI_STATUS Status; + + + // + // Validate the the Input parameters + // + if (DriverImageHandle == NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // If already Found all the images,proceed to return the data + // + if( !LoadedImageDone ) { + + LoadedImageDone = TRUE; + + // + // Locate all the driver binding protocols + // + Status = pBS->LocateHandleBuffer ( + ByProtocol, + &gEfiDriverBindingProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + for (Index = 0; Index < HandleCount; Index++) { + + // + // Get the Driver Binding Protocol Interface + // + Status = pBS->HandleProtocol(HandleBuffer[Index], + &gEfiDriverBindingProtocolGuid, + &DriverBindingProtocol); + + if(EFI_ERROR(Status) || DriverBindingProtocol == NULL){ + continue; + } + + // + // Get the LoadedImage Protocol from ImageHandle + // + Status = pBS->HandleProtocol(DriverBindingProtocol->ImageHandle, + &gEfiLoadedImageGuid, + &LoadedImage); + + if(EFI_ERROR(Status)){ + continue; + } + + // + //Compare the File guid with driver's needs to launched first + // + if(guidcmp(&(((MEDIA_FW_VOL_FILEPATH_DEVICE_PATH*)(LoadedImage->FilePath))->NameGuid) + , &GuidListCheckForRaid[GuidCount]) != 0) { + continue; + } + + // + // Driver Image handle found. Add it in the Array + // + ImageHandleArray[GuidCount] = DriverBindingProtocol->ImageHandle; + GuidCount++; + + // + // Start from the begining + // + Index = -1; + + // + // Check All the Guid's are found. If found break the loop + // + if(GuidCount >= (sizeof(GuidListCheckForRaid)/sizeof(EFI_GUID) -1 )) { + break; + } + + } + + // + // Free the HandleBuffer Memory. + // + if (HandleBuffer) { + pBS->FreePool (HandleBuffer); + } + + } + + if(GuidCount == 0) { + // + // Image handle not found + // + return EFI_NOT_FOUND; + } + + // + //If the *DriverImageHandle is NULL , return the first Imagehandle + // + if( *DriverImageHandle == NULL ) { + if(ImageHandleArray[0] != NULL) { + *DriverImageHandle = ImageHandleArray[0]; + return EFI_SUCCESS; + } + } else { + // + // If *DriverImageHandle not NULL , return the next Imagehandle + // from the avilable image handle list + // + for (Index = 0; Index < 4; Index++) { + if( *DriverImageHandle == ImageHandleArray[Index] && (ImageHandleArray[Index+1] != NULL) ) { + *DriverImageHandle = ImageHandleArray[Index+1]; + return EFI_SUCCESS; + } + } + } + + // + // No more Image handle found to handle the controller. + // + return EFI_NOT_FOUND; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ULTDsdtTableUpdate +// +// Description: Update the ULT DSDT table +// +// Input: DsdtTable - The table points to DSDT table. +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +ULTDsdtTableUpdate ( + IN ACPI_HDR *DsdtTable + ) +{ + UINT8 *CurrPtr; + UINT8 *DsdtPointer; + UINT32 *Signature; + UINT8 HexStr[36] = {'0','1','2','3','4','5','6','7','8','9','A','B','C','D','E','F','G','H',\ + 'I','J','K','L','M','N','O','P','Q','R','S','T','U','V','W','X','Y','Z'}; + UINT8 ReturnVaule = 0; + UINT32 *SignaturePcieAdrs; //(EIP127410)>> + UINT8 RPFN[6]; //Root Port Function Number + UINT8 i; //(EIP127410)<< + UINT8 RP06Done = 0; +#if LOW_POWER_S0_IDLE_CAPABLE == 1 + SETUP_DATA *SetupData = NULL; + EFI_GUID SetupGuid = SETUP_GUID; + UINTN VariableSize = sizeof(SETUP_DATA); + EFI_STATUS Status; + UINT8 S0ID; + + Status = pBS->AllocatePool( EfiBootServicesData, + VariableSize, + &SetupData ); + ASSERT_EFI_ERROR(Status); + + Status = pRS->GetVariable( L"Setup", + &SetupGuid, + NULL, + &VariableSize, + SetupData ); + + S0ID = SetupData->AcpiLowPowerS0Idle; + + if (SetupData != NULL) { + pBS->FreePool(SetupData); + } +#endif + //(EIP127410)>> + for(i = 0 ; i < 6; i++){ + RPFN[i] = ((UINT8)(MmioRead32(SB_RCRB_BASE_ADDRESS + R_PCH_RCRB_RPFN) >> 4*i)) & 0x07; + TRACE((-1, "\nRCBA RPFN%x = %x\n", i, RPFN[i])); + } + //(EIP127410)<< + CurrPtr = (UINT8 *) DsdtTable; + for (DsdtPointer = CurrPtr; + DsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length); + DsdtPointer++ ) + { + Signature = (UINT32 *) DsdtPointer; + switch(*Signature){ + //************** GPE event case ************** + case (EFI_SIGNATURE_32 ('X', 'L', '0', 'B')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', '3')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', '4')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', 'C')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', 'E')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', '5')): + //************************************************* + case (EFI_SIGNATURE_32 ('X', 'L', '0', '9')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', 'D')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', '1')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', '2')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', '6')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', '7')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', '8')): + *DsdtPointer = '_'; + *(DsdtPointer + 2) = HexStr[6]; //6 + DsdtPointer = DsdtPointer + 3; + break; + case (EFI_SIGNATURE_32 ('X', 'L', '1', 'E')): + *DsdtPointer = '_'; + *(DsdtPointer + 3) = HexStr[11]; //B + DsdtPointer = DsdtPointer + 3; + break; + //************** Return vaule case ************** + case (EFI_SIGNATURE_32 ('G', 'P', 'R', 'W')): + ReturnVaule = *(DsdtPointer + 5); + switch (ReturnVaule){ + case 0x03: + case 0x04: + case 0x05: + case 0x08: + case 0x09: + case 0x0B: + case 0x0C: + case 0x0D: + case 0x0E: + *(DsdtPointer + 5) = ReturnVaule + 0x60; + break; + default: + break; + } + + DsdtPointer = DsdtPointer + 7; + break; + #if LOW_POWER_S0_IDLE_CAPABLE == 1 + //************** Change Dock case ************** + case (EFI_SIGNATURE_32 ('_', 'D', 'C', 'K')): + if (S0ID == 1){ + *DsdtPointer = HexStr[33]; //X + DsdtPointer = DsdtPointer + 3; + } + break; + #endif + //************** PCIE Adress **************** //(EIP127410)>> + case (EFI_SIGNATURE_32 ('R', 'P', '0', '1')): + if (gSbSetupData->RootPortFunctionSwapping){ + DsdtPointer = DsdtPointer + 5; + SignaturePcieAdrs = (UINT32 *) DsdtPointer; + switch(*SignaturePcieAdrs){ + case (EFI_SIGNATURE_32 ('_', 'A', 'D', 'R')): + DsdtPointer = DsdtPointer + 5; + *DsdtPointer = RPFN[0]; + break; + default: + break; + } + } + break; + case (EFI_SIGNATURE_32 ('R', 'P', '0', '2')): + if (gSbSetupData->RootPortFunctionSwapping){ + DsdtPointer = DsdtPointer + 5; + SignaturePcieAdrs = (UINT32 *) DsdtPointer; + switch(*SignaturePcieAdrs){ + case (EFI_SIGNATURE_32 ('_', 'A', 'D', 'R')): + DsdtPointer = DsdtPointer + 5; + *DsdtPointer = RPFN[1]; + break; + default: + break; + } + } + break; + case (EFI_SIGNATURE_32 ('R', 'P', '0', '3')): + if (gSbSetupData->RootPortFunctionSwapping){ + DsdtPointer = DsdtPointer + 5; + SignaturePcieAdrs = (UINT32 *) DsdtPointer; + switch(*SignaturePcieAdrs){ + case (EFI_SIGNATURE_32 ('_', 'A', 'D', 'R')): + DsdtPointer = DsdtPointer + 5; + *DsdtPointer = RPFN[2]; + break; + default: + break; + } + } + break; + case (EFI_SIGNATURE_32 ('R', 'P', '0', '4')): + if (gSbSetupData->RootPortFunctionSwapping){ + DsdtPointer = DsdtPointer + 5; + SignaturePcieAdrs = (UINT32 *) DsdtPointer; + switch(*SignaturePcieAdrs){ + case (EFI_SIGNATURE_32 ('_', 'A', 'D', 'R')): + DsdtPointer = DsdtPointer + 5; + *DsdtPointer = RPFN[3]; + break; + default: + break; + } + } + break; + case (EFI_SIGNATURE_32 ('R', 'P', '0', '5')): + if (gSbSetupData->RootPortFunctionSwapping){ + DsdtPointer = DsdtPointer + 5; + SignaturePcieAdrs = (UINT32 *) DsdtPointer; + switch(*SignaturePcieAdrs){ + case (EFI_SIGNATURE_32 ('_', 'A', 'D', 'R')): + DsdtPointer = DsdtPointer + 5; + *DsdtPointer = RPFN[4]; + break; + default: + break; + } + } + break; + case (EFI_SIGNATURE_32 ('R', 'P', '0', '6')): + if (gSbSetupData->RootPortFunctionSwapping){ + DsdtPointer = DsdtPointer + 5; + SignaturePcieAdrs = (UINT32 *) DsdtPointer; + switch(*SignaturePcieAdrs){ + case (EFI_SIGNATURE_32 ('_', 'A', 'D', 'R')): + DsdtPointer = DsdtPointer + 5; + *DsdtPointer = RPFN[5]; + break; + default: + break; + } + } + while(RP06Done != 1){ + DsdtPointer++; + SignaturePcieAdrs = (UINT32 *) DsdtPointer; + + switch(*SignaturePcieAdrs){ + case (EFI_SIGNATURE_32 ('A', 'R', '0', '9')): + *(DsdtPointer + 3) = HexStr[8]; //8 + DsdtPointer = DsdtPointer + 3; + break; + + case (EFI_SIGNATURE_32 ('P', 'R', '0', '9')): + *(DsdtPointer + 3) = HexStr[8]; //8 + DsdtPointer = DsdtPointer + 3; + RP06Done = 1; + break; + + default: + break; + } + } + break; //(EIP127410)<< + default: + break; + }// end switch + }// end of for loop +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: DsdtTableUpdate +// +// Description: Update the DSDT table +// +// Input: DsdtTable - The table points to DSDT table. +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +DsdtTableUpdate ( + IN ACPI_HDR *DsdtTable + ) +{ + UINT8 *CurrPtr; + UINT8 *DsdtPointer; + UINT32 *Signature; + UINT8 HexStr[36] = {'0','1','2','3','4','5','6','7','8','9','A','B','C','D','E','F','G','H',\ + 'I','J','K','L','M','N','O','P','Q','R','S','T','U','V','W','X','Y','Z'}; + UINT8 ReturnVaule = 0; + UINT32 *SignaturePcieAdrs; //(EIP127410)>> + UINT8 RPFN[8]; //Root Port Function Number + UINT8 i; //(EIP127410)<< + + CurrPtr = (UINT8 *) DsdtTable; + //(EIP127410)>> + for(i = 0 ; i < 8; i++){ + RPFN[i] = ((UINT8)(MmioRead32(SB_RCRB_BASE_ADDRESS + R_PCH_RCRB_RPFN) >> 4*i)) & 0x07; + TRACE((-1, "\nRCBA RPFN%x = %x\n", i, RPFN[i])); + } + //(EIP127410)<< + for (DsdtPointer = CurrPtr; + DsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length); + DsdtPointer++ ) + { + Signature = (UINT32 *) DsdtPointer; + switch(*Signature){ + //************** GPE event case ************** + case (EFI_SIGNATURE_32 ('X', 'L', '0', 'B')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', '3')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', '4')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', 'C')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', 'E')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', '5')): + //************************************************* + case (EFI_SIGNATURE_32 ('X', 'L', '0', '9')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', 'D')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', '1')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', '2')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', '6')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', '7')): + case (EFI_SIGNATURE_32 ('X', 'L', '0', '8')): + *DsdtPointer = '_'; + DsdtPointer = DsdtPointer + 3; + break; + case (EFI_SIGNATURE_32 ('X', 'L', '1', 'E')): + *DsdtPointer = '_'; + DsdtPointer = DsdtPointer + 3; + break; + //************** PCIE Adress **************** //(EIP127410)>> + case (EFI_SIGNATURE_32 ('R', 'P', '0', '1')): + if (gSbSetupData->RootPortFunctionSwapping){ + DsdtPointer = DsdtPointer + 5; + SignaturePcieAdrs = (UINT32 *) DsdtPointer; + switch(*SignaturePcieAdrs){ + case (EFI_SIGNATURE_32 ('_', 'A', 'D', 'R')): + DsdtPointer = DsdtPointer + 5; + *DsdtPointer = RPFN[0]; + break; + default: + break; + } + } + break; + case (EFI_SIGNATURE_32 ('R', 'P', '0', '2')): + if (gSbSetupData->RootPortFunctionSwapping){ + DsdtPointer = DsdtPointer + 5; + SignaturePcieAdrs = (UINT32 *) DsdtPointer; + switch(*SignaturePcieAdrs){ + case (EFI_SIGNATURE_32 ('_', 'A', 'D', 'R')): + DsdtPointer = DsdtPointer + 5; + *DsdtPointer = RPFN[1]; + break; + default: + break; + } + } + break; + case (EFI_SIGNATURE_32 ('R', 'P', '0', '3')): + if (gSbSetupData->RootPortFunctionSwapping){ + DsdtPointer = DsdtPointer + 5; + SignaturePcieAdrs = (UINT32 *) DsdtPointer; + switch(*SignaturePcieAdrs){ + case (EFI_SIGNATURE_32 ('_', 'A', 'D', 'R')): + DsdtPointer = DsdtPointer + 5; + *DsdtPointer = RPFN[2]; + break; + default: + break; + } + } + break; + case (EFI_SIGNATURE_32 ('R', 'P', '0', '4')): + if (gSbSetupData->RootPortFunctionSwapping){ + DsdtPointer = DsdtPointer + 5; + SignaturePcieAdrs = (UINT32 *) DsdtPointer; + switch(*SignaturePcieAdrs){ + case (EFI_SIGNATURE_32 ('_', 'A', 'D', 'R')): + DsdtPointer = DsdtPointer + 5; + *DsdtPointer = RPFN[3]; + break; + default: + break; + } + } + break; + case (EFI_SIGNATURE_32 ('R', 'P', '0', '5')): + if (gSbSetupData->RootPortFunctionSwapping){ + DsdtPointer = DsdtPointer + 5; + SignaturePcieAdrs = (UINT32 *) DsdtPointer; + switch(*SignaturePcieAdrs){ + case (EFI_SIGNATURE_32 ('_', 'A', 'D', 'R')): + DsdtPointer = DsdtPointer + 5; + *DsdtPointer = RPFN[4]; + break; + default: + break; + } + } + break; + case (EFI_SIGNATURE_32 ('R', 'P', '0', '6')): + if (gSbSetupData->RootPortFunctionSwapping){ + DsdtPointer = DsdtPointer + 5; + SignaturePcieAdrs = (UINT32 *) DsdtPointer; + switch(*SignaturePcieAdrs){ + case (EFI_SIGNATURE_32 ('_', 'A', 'D', 'R')): + DsdtPointer = DsdtPointer + 5; + *DsdtPointer = RPFN[5]; + break; + default: + break; + } + } + break; + case (EFI_SIGNATURE_32 ('R', 'P', '0', '7')): + if (gSbSetupData->RootPortFunctionSwapping){ + DsdtPointer = DsdtPointer + 5; + SignaturePcieAdrs = (UINT32 *) DsdtPointer; + switch(*SignaturePcieAdrs){ + case (EFI_SIGNATURE_32 ('_', 'A', 'D', 'R')): + DsdtPointer = DsdtPointer + 5; + *DsdtPointer = RPFN[6]; + break; + default: + break; + } + } + break; + case (EFI_SIGNATURE_32 ('R', 'P', '0', '8')): + if (gSbSetupData->RootPortFunctionSwapping){ + DsdtPointer = DsdtPointer + 5; + SignaturePcieAdrs = (UINT32 *) DsdtPointer; + switch(*SignaturePcieAdrs){ + case (EFI_SIGNATURE_32 ('_', 'A', 'D', 'R')): + DsdtPointer = DsdtPointer + 5; + *DsdtPointer = RPFN[7]; + break; + default: + break; + } + } + break; //(EIP127410)<< + default: + break; + }// end switch + }// end of for loop +} +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/SBGeneric.c b/Chipset/SB/SBGeneric.c new file mode 100644 index 0000000..efdedd4 --- /dev/null +++ b/Chipset/SB/SBGeneric.c @@ -0,0 +1,3717 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SBGeneric.c 27 1/29/15 4:14a Mirayang $ +// +// $Revision: 27 $ +// +// $Date: 1/29/15 4:14a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SBGeneric.c $ +// +// 27 1/29/15 4:14a Mirayang +// [TAG] EIP200269 +// [Category] New Feature +// [Description] For add FlashSmi : Label 4.6.5.5_FlashSmi_00 +// ($/Alaska/SOURCE/Modules/FlashSmi) +// +// 26 5/16/14 6:16a Barretlin +// [TAG] EIP167087 +// [Category] Improvement +// [Description] BIOS security improvement on Haswell CRB project +// [Files] SBGeneric.c SBDxe.c SBCspLib.h Sb.sdl Sb.sd +// +// 25 1/24/14 2:49a Barretlin +// [TAG] EIP136638 +// [Category] Improvement +// [Description] fix programming error +// [Files] SBGeneric.c PchResetCommon.c +// +// 24 12/30/13 6:01a Barretlin +// [TAG] EIP144559 +// [Category] Improvement +// [Description] S3 can't resume via USB KB & MS under usb3.0 port in +// special case +// [Files] SBSMI.c SBSMI.h SBGeneric.c +// +// 23 11/19/13 7:32a Barretlin +// [TAG] EIP141917 +// [Category] New Feature +// [Description] Support SetTimer() with HPET Timer on Lynx Point +// [Files] SB.sdl SBGeneric.c SBDxe.c SbHpet.h sbProtocal.cif +// SamrtTimer.sdl +// +// 22 4/29/13 1:58a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] THe NMI read port should before index update. +// [Files] SBGeneric.c +// +// 21 4/19/13 6:35a Wesleychen +// [TAG] None +// [Category] Improvement +// [Description] Update GbES02SxWorkaround() and add +// UsbS02SxWorkaround() for SBPwrBtnHandler(). +// [Files] SBSMI.c; SBSMI.h; SBGeneric.c; SBCspLib.h +// +// 20 4/01/13 6:43a Scottyang +// [TAG] EIP119703 +// [Category] Improvement +// [Description] Clear RTC before BIOS flash capsule function enter S3. +// [Files] SBGeneric.c +// +// 19 3/19/13 8:33a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Improve alternate access mode enable/disable routine. +// [Files] SBGeneric.c, SBCspLib.h, SBSMI.c +// +// 18 3/19/13 8:19a Scottyang +// [TAG] EIP118158 +// [Category] Improvement +// [Description] Correct SBLib_CmosRead () offset. +// [Files] SmiHandlerPorting2.c, SBDxe.c, SBGeneric.c, SBSmm.c, +// SmiHandlerPorting.c +// +// 17 3/12/13 7:44a Scottyang +// [TAG] EIP106722 +// [Category] Improvement +// [Description] Clear RTC before capsule function enter S3. +// [Files] SBGeneric.c +// +// 16 1/11/13 4:36a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add ReadCmos() / WriteCmos() from SB template. +// [Files] SBGeneric.c +// +// 15 1/11/13 12:46a Scottyang +// [TAG] EIP81593 +// [Category] Improvement +// [Description] Added new SDL token "COLD_RESET_WITH_POWER_CYCLE". +// [Files] SB.sdl, SBGeneric.c, PchResetCommon.c, +// PchResetCommonLib.sdl +// +// 14 1/10/13 8:20a Scottyang +// [TAG] EIP111666 +// [Category] New Feature +// [Description] Support OEM reset callback function Elink. +// [Files] SB.mak, SBCspLib.h, SBGeneric.c, SB.sdl, PchReset.c +// +// 13 11/21/12 3:07a Scottyang +// +// 11 11/19/12 3:52a Scottyang +// [TAG] EIP106353 +// [Category] Bug Fix +// [Severity] Critical +// [Symptom] The system has assert error when PFAT is Disabled and Debug +// Mode is Enabled. +// [RootCause] Use build time PFAT flag that make some code not run whrn +// PFAT disable. +// [Solution] Detect PFAT flag useing MSR. +// [Files] SBGeneric, SB.mak +// +// 10 10/30/12 10:02p Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Remove clear SMI state and Y2K roller for PFAT +// function. +// [Files] SBSMI.c, SBGeneric.c +// +// 9 10/25/12 11:57p Scottyang +// [TAG] EIP100108 +// [Category] Improvement +// [Description] Support Capsule 2.0. +// [Files] SBGeneric.c +// +// 8 10/19/12 2:46a Scottyang +// [TAG] EIP93461 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] System halt when AFUDOS is running with /N /ME command. +// [RootCause] An unexpected BIOSWR_STS is set, it causes BIOS stuck +// at SMM dispatcher. +// [Solution] Clear BIOSWR_STS if BIOS Lock Enable is not set. +// [Files] SmiHandlerPorting2.c; SmmChildDispatch2Main.c +// SmmChildDispatcher2.sdl; SmmChildDispatch2.h +// SB\SBGeneric.c +// +// 7 10/01/12 5:53a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update for PFTA support. +// [Files] SBGeneric.c +// +// 6 9/26/12 3:54a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update for PCH LP GPIO compatible. +// [Files] SB.sdl, SB.H, AcpiModeEnable.c, AcpiModeEnable.sdl, +// SBDxe.c, SBGeneric.c, SBPEI.c, SBSMI.c, SleepSmi.c, +// SmiHandlerPorting.c, SmiHandlerPorting2.c +// +// 5 9/12/12 5:19a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Remove useless HdmiVerbTable. +// [Files] SB.sdl, SBCspLib.h, SBDxe.c, SBGeneric.c +// +// 4 8/24/12 6:50a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Remove useless SB_SHADOW_CONTROL. +// [Files] SB.sdl, SBCspLib.h, SBGeneric.c +// +// 3 7/02/12 10:17a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Updated and modified for PCH RC 0.6.0. +// [Files] SBGeneric.c, SB.sdl, SBCspLib.h, SBDxe.c, SBPEI.c +// +// 2 6/13/12 11:34p Victortu +// [TAG] None +// [Category] Improvement +// [Description] Implement Warm Boot function for Secure Flash feature. +// [Files] SB.H, SB.mak, SB.sdl, SBDxe.c, SBGeneric.c, SBPEI.c, +// SBSMI.c +// +// 1 2/08/12 8:24a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SBGeneric.C +// +// Description: This file contains south bridge related code that is needed +// for both PEI & DXE stage. +// To avoid code duplication this file is made as a library and +// linked both in PEI & DXE south bridge FFS. +// +// Notes: MAKE SURE NO PEI OR DXE SPECIFIC CODE IS NEEDED +// +//<AMI_FHDR_END> +//************************************************************************* + +//--------------------------------------------------------------------------- +// Include(s) +//--------------------------------------------------------------------------- + +#include <Efi.h> +#include <Token.h> +#include <AmiPeiLib.h> +#include <AmiDxeLib.h> +#include <Protocol\PciRootBridgeIo.h> +#include <AmiCspLib.h> +#include "PchAccess.h" +#include "RTC.h" +#if Capsule2_0_SUPPORT +#include <capsule.h> //CAPSULE20 +#endif +#include <Include\PchRegs.h> +#include <Include\PchRegs\PchRegsLpc.h> + +#if CSM_SUPPORT +#include <Protocol\LegacyInterrupt.h> +#endif + +#include "CpuRegs.h" // EIP106353 + +#if defined HPET_PROTOCOL_SUPPORT && HPET_PROTOCOL_SUPPORT == 1 +#include <Protocol\SbHpet.h> +#endif + +//--------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//--------------------------------------------------------------------------- +// Constant Definition(s) + +#ifndef BIT35 // EIP106353 >> +#define BIT35 0x0000000800000000ULL +#endif // EIP106353 << + +#if CSM_SUPPORT + +#define MAX_PIRQS 8 // Porting Required. + +#endif + +#ifndef CAPSULE_SUPPORT + +#if defined Capsule2_0_SUPPORT && Capsule2_0_SUPPORT +#define CAPSULE_SUPPORT 1 +#else +#define CAPSULE_SUPPORT 0 +#endif + +#endif + +// Macro Definition(s) + +// Type Definition(s) + +typedef VOID (SB_OEM_S3_WARMRESET_CALLBACK) (VOID); + +typedef EFI_STATUS (SB_RUN_RESET_CALLBACK) ( + IN EFI_RESET_TYPE ResetType +); + +typedef struct { + UINT8 Device; + UINT8 Function; +} USB_CONTROLLER; + +// Function Prototype(s) + +//--------------------------------------------------------------------------- +// Variable and External Declaration(s) +//--------------------------------------------------------------------------- +// Variable Declaration(s) +#if defined CAPSULE_SUPPORT && CAPSULE_SUPPORT == 1 +extern SB_OEM_S3_WARMRESET_CALLBACK \ + SB_OEM_S3_WARMRESET_CALLBACK_LIST EndOfList; +SB_OEM_S3_WARMRESET_CALLBACK* SbS3InsteadOfWarmResetCallBackList[] = \ + {SB_OEM_S3_WARMRESET_CALLBACK_LIST NULL}; +#endif + +extern SB_RUN_RESET_CALLBACK SB_RUN_RESET_CALLBACK_LIST EndOfList1; +SB_RUN_RESET_CALLBACK* SbRunResetCallbackList[] = {SB_RUN_RESET_CALLBACK_LIST NULL}; + +//--------------------------------------------------------------------------- +// The following table contains the information regarding the PIRQ routing +// registers and other South Bridge registers that need to be restored +// during the S3 wakeup. +// Mention all register address (bus, device, function , register), specify +// the size of the register ans the mask also. +//--------------------------------------------------------------------------- + +BOOT_SCRIPT_SB_PCI_REG_SAVE gSBRegsSaveTbl[] = { + {SB_REG(SB_REG_PIRQ_A), EfiBootScriptWidthUint8, 0xff}, + {SB_REG(SB_REG_PIRQ_B), EfiBootScriptWidthUint8, 0xff}, + {SB_REG(SB_REG_PIRQ_C), EfiBootScriptWidthUint8, 0xff}, + {SB_REG(SB_REG_PIRQ_D), EfiBootScriptWidthUint8, 0xff}, + {SB_REG(SB_REG_PIRQ_E), EfiBootScriptWidthUint8, 0xff}, + {SB_REG(SB_REG_PIRQ_F), EfiBootScriptWidthUint8, 0xff}, + {SB_REG(SB_REG_PIRQ_G), EfiBootScriptWidthUint8, 0xff}, + {SB_REG(SB_REG_PIRQ_H), EfiBootScriptWidthUint8, 0xff}, + {SB_REG(SB_REG_GEN_PMCON_1),EfiBootScriptWidthUint16, 0xffff},// SMI Timer + {SB_REG(SB_REG_GEN_PMCON_3),EfiBootScriptWidthUint16, 0xffff},// SMI Timer + {SB_REG(SB_REG_LPC_IO_DEC), EfiBootScriptWidthUint16, 0xffff}, + {SB_REG(SB_REG_LPC_EN), EfiBootScriptWidthUint16, 0xffff}, + {SB_REG(SB_REG_GEN1_DEC), EfiBootScriptWidthUint32, 0xffffffff}, + {SB_REG(SB_REG_GEN2_DEC), EfiBootScriptWidthUint32, 0xffffffff}, + {SB_REG(SB_REG_GEN3_DEC), EfiBootScriptWidthUint32, 0xffffffff}, + {SB_REG(SB_REG_GEN4_DEC), EfiBootScriptWidthUint32, 0xffffffff}, +}; + +#define NUM_SB_PCI_REG_SAVE \ + sizeof(gSBRegsSaveTbl)/ sizeof(BOOT_SCRIPT_SB_PCI_REG_SAVE) + +#if CSM_SUPPORT + +UINT8 bMaxPIRQ = MAX_PIRQS; // For CSM +UINT8 bRouterBus = SB_BUS; // PORTING REQUIRED (Use appropriate Equate) +UINT8 bRouterDevice = SB_DEV; // PORTING REQUIRED (Use appropriate Equate) +UINT8 bRouterFunction = SB_FUN; // PORTING REQUIRED (Use appropriate Equate) +UINT8 RRegs[MAX_PIRQS] = { SB_REG_PIRQ_A, \ + SB_REG_PIRQ_B, \ + SB_REG_PIRQ_C, \ + SB_REG_PIRQ_D, \ + SB_REG_PIRQ_E, \ + SB_REG_PIRQ_F, \ + SB_REG_PIRQ_G, \ + SB_REG_PIRQ_H }; // Porting required + +#endif +// Local variable +static EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *gPciRootBridgeIo; + +// GUID Definition(s) + +// Protocol Definition(s) + +// External Declaration(s) + +// Function Definition(s) +BOOLEAN CheckOff20hBit28(IN UINT32 GbEBase); +//--------------------------------------------------------------------------- + +//--------------------------------------------------------------------------- +// Start OF CSM Related Porting Hooks +//--------------------------------------------------------------------------- + +#if CSM_SUPPORT + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBGen_InitializeRouterRegisters +// +// Description: This function is clears the routing registers to default +// values +// +// Input: PciRBIo - Root bridge IO protocol pointer +// +// Output: EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SBGen_InitializeRouterRegisters ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRBIo ) +{ + UINT8 RegIdx; + + gPciRootBridgeIo = PciRBIo; // Save RB IO value for later use + + for (RegIdx = 0; RegIdx < MAX_PIRQS; RegIdx++) + WRITE_PCI8_SB(RRegs[RegIdx], 0x80); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBGen_GetPIRQIndex +// +// Description: This function returns the 0 based PIRQ index (PIRQ0, 1 etc) +// based on the PIRQ register number specified in the routing +// table. +// +// Input: PIRQRegister - Register number of the PIR +// +// Output: An 8Bit Index for RRegs table, its range is 0 - (MAX_PIRQ -1) +// if PIRQRegister is invalid, then 0xff will be returned. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT8 SBGen_GetPIRQIndex ( + IN UINT8 PIRQRegister ) +{ + UINT8 rrIndx = 0; + + while ((rrIndx < MAX_PIRQS) && (RRegs[rrIndx] != PIRQRegister)) rrIndx++; + + if (rrIndx == MAX_PIRQS) return 0xff; + + return rrIndx; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBGen_ReadPirq +// +// Description: This function reads the IRQ associated with the PIRQ from +// the chipset register +// +// Input: This - Pointer to Legacy interrupt protocol +// PirqNumber - PIRQ number to read +// PirqData - IRQ programmed for this PIRQ (BIT7 will be +// set if the PIRQ is not programmed) +// +// Output: EFI_STATUS +// EFI_SUCCESS - On successfull IRQ value return +// EFI_INVALID_PARAMETER - If PirqNumber is greater than max +// PIRQs +// +// Notes: Here is the control flow of this function: +// 1. If Invalid PirqNumber, return EFI_INVALID_PARAMETER. +// 2. Read into *PriqData from PIRQ register for Pirq requested +// 3. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SBGen_ReadPirq ( + IN EFI_LEGACY_INTERRUPT_PROTOCOL *This, + IN UINT8 PirqNumber, + OUT UINT8 *PirqData ) +{ + if (PirqNumber > MAX_PIRQS) return EFI_INVALID_PARAMETER; + + // If Pirq is not routed, bit 7 is set, however specification does not + // specify a return error for this condition. + *PirqData = READ_PCI8_SB(RRegs[PirqNumber]); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBGen_WritePirq +// +// Description: This function writes an IRQ value allocated for the PIRQ by +// programming the chipset register +// +// Input: This - Pointer to Legacy interrupt protocol +// PirqNumber - PIRQ number to read +// PirqData - IRQ to be programmed +// +// Output: EFI_STATUS +// EFI_SUCCESS - On successfull IRQ value return +// EFI_INVALID_PARAMETER - If PirqNumber is greater than +// max PIRQs or PirqData is greater +// than 15 (MAX IRQ) +// +// Notes: Here is the control flow of this function: +// 1. If Invalid PirqNumber or PirqData is greater than 15, +// return EFI_INVALID_PARAMETER. +// 2. Write PirqData to PIRQ register for Pirq requested. +// 3. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SBGen_WritePirq ( + IN EFI_LEGACY_INTERRUPT_PROTOCOL *This, + IN UINT8 PirqNumber, + IN UINT8 PirqData ) +{ + UINT8 PirqValue = PirqData & 0x0f; + + if (PirqNumber > MAX_PIRQS) return EFI_INVALID_PARAMETER; + if (PirqData > 15) return EFI_INVALID_PARAMETER; + + WRITE_PCI8_SB(RRegs[PirqNumber], PirqValue); + + return EFI_SUCCESS; +} + +//--------------------------------------------------------------------------- +#endif // END OF CSM Related Porting Hooks +//--------------------------------------------------------------------------- +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SbFindCapPtr +// +// Description: This function searches the PCI address space for the PCI +// device specified for a particular capability ID and returns +// the offset in the PCI address space if one found +// +// Input: UINT64 PciAddress, +// UINT8 CapId +// +// Output: Capability ID Address if one found +// Otherwise returns 0 +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT32 SbFindCapPtr( + IN UINT64 PciAddress, + IN UINT8 CapId +) +{ + UINT8 Value; + UINT32 Address = (UINT32)PciAddress; + + Address = (Address & 0xffffff00) | 6; //PCI Status Register. + Value = READ_MEM8(Address + 0); + + if (Value == 0xff) return 0; // No device. + if (!(Value & (1 << 4))) return 0; // Check if capabilities list. + + *(UINT8*)&Address = 0x34; // Register to First capabilities pointer + // if 0, then capabilities + for(;;) + { + Value = READ_MEM8(Address + 0); + if (Value == 0) return 0; + + *(UINT8*)&Address = Value; // PciAddress = ptr to CapID + Value = READ_MEM8(Address + 0); // New cap ptr. + + //If capablity ID, return register that points to it. + if (Value == CapId) return Address; + + ++Address; // Equals to next capability pointer. + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBSwSmiWriteToBootScript +// +// Description: Write SB necessary SW SMIs to boot script. +// +// Input: *BootScriptSave - Pointer to Boot Scrpit Save Protocol. +// +// Output: EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID SBSwSmiWriteToBootScript ( + IN AMI_S3_SAVE_PROTOCOL *BootScriptSave ) +{ + + UINT8 Value8; + + // Generate an ACPI Enable SMI when S3 resuming. + Value8 = SW_SMI_ACPI_ENABLE; + BOOT_SCRIPT_S3_IO_WRITE_MACRO( BootScriptSave, \ + EfiBootScriptWidthUint8, \ + SW_SMI_IO_ADDRESS, \ + 1, \ + &Value8 ); + + // Generate a Software SMI to enable SB patched codes when S3 resuming. + Value8 = SW_SMI_SB_ACPI_S3; + BOOT_SCRIPT_S3_IO_WRITE_MACRO( BootScriptSave, \ + EfiBootScriptWidthUint8, \ + SW_SMI_IO_ADDRESS, \ + 1, \ + &Value8); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBGen_WriteBootScript +// +// Description: This writes the PIRQ to boot script before booting. +// +// Input: *BootScriptSave - Pointer to Boot Scrpit Save Protocol. +// +// Output: EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS SBGen_WriteBootScript ( + IN AMI_S3_SAVE_PROTOCOL *BootScriptSave ) +{ + UINTN i; + UINT32 Value32; + + //Porting required: Write Boot Script + for (i = 0; i < NUM_SB_PCI_REG_SAVE; ++i) { + gPciRootBridgeIo->Pci.Read( gPciRootBridgeIo, \ + gSBRegsSaveTbl[i].Width, + gSBRegsSaveTbl[i].Address, + 1, + &Value32 ); + Value32 &= gSBRegsSaveTbl[i].Mask; + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( BootScriptSave, \ + gSBRegsSaveTbl[i].Width, \ + gSBRegsSaveTbl[i].Address, \ + 1, \ + &Value32 ); + } + + SBSwSmiWriteToBootScript(BootScriptSave); + + return EFI_SUCCESS; +} + +#if SB_RESET_PPI_SUPPORT +#if defined CAPSULE_SUPPORT && CAPSULE_SUPPORT == 1 +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBLib_S3InsteadOfWarmResetCallBack +// +// Description: This function calls registered callbacks for S3 RTC/Timer +// (WarmBoot) eLink. +// +// Input: None +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SBLib_S3InsteadOfWarmResetCallBack (VOID) +{ + UINTN i; + + for (i = 0; SbS3InsteadOfWarmResetCallBackList[i] != NULL; i++) + SbS3InsteadOfWarmResetCallBackList[i](); +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBLib_S3InsteadOfWarmReset +// +// Description: This function puts system into ACPI S3 State. +// if token ENABLE_RTC_ONE_SECOND_WAKEUP = 1, then it setups RTC +// 1 second alarm as well. +// +// Input: None +// +// Output: None, system will enter ACPI S3 State. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SBLib_S3InsteadOfWarmReset (VOID) +{ +#if ENABLE_RTC_ONE_SECOND_WAKEUP + UINT8 Hour; + UINT8 Minute; + UINT8 Second; + BOOLEAN InBCD = TRUE; + + // Determine if RTC is in BCD mode + if ( READ_IO8_RTC(0x0b) & 0x4 ) InBCD = FALSE; // Bit 2 + + // Wait for time update to complete before reading the values, + // while bit 7 is set the time update is in progress. + while( READ_IO8_RTC(0x0a) & 0x80 ); + + // Read current hour, minute, second + Hour = READ_IO8_RTC(0x04); // Hours + Minute = READ_IO8_RTC(0x02); // Minutes + Second = READ_IO8_RTC(0x00); // Seconds + + // Convert second to decimal from BCD and increment by 1 + if (InBCD) Second = (Second >> 4) * 10 + (Second & 0x0F); + Second += 2; + + if (Second > 59) { + Second -= 60; + if (InBCD) Minute = (Minute >> 4) * 10 + (Minute & 0x0F); + Minute++; + if (Minute > 59){ + Minute = 0; + if (InBCD) Hour = (Hour >> 4) * 10 + (Hour & 0x0F); + Hour++; + // Check 24 hour mode/12 hour mode, Bit1 1=24hour else 12 hour + if ( READ_IO8_RTC(0x0b) & 0x2 ) { + if(Hour > 23) Hour = 0; + } else { + if(Hour > 11) Hour = 0; + } + + if (InBCD) Hour = Hour % 10 + ( (Hour / 10) << 4 ) ; + } + + if (InBCD) Minute = Minute % 10 + ( (Minute / 10) << 4 ) ; + } + + // Convert from decimal to BCD + if (InBCD) Second = Second % 10 + ( (Second / 10) << 4 ) ; + + // Set the alarm + WRITE_IO8_RTC(0x05, Hour); // Hours Alarm + WRITE_IO8_RTC(0x03, Minute); // Minutes Alarm + WRITE_IO8_RTC(0x01, Second); // Seconds Alarm + + // [EIP119703]> + // Clear date alarm. + WRITE_IO8_RTC(0x0D, READ_IO8_RTC(0x0D) & BIT07); + // <[EIP119703] + + // Enable the alarm + SET_IO8_RTC(0x0b, 0x20); // Bit 5 + + if (READ_IO16_PM(ACPI_IOREG_PM1_STS) & 0x400) { + READ_IO8_RTC(0x8C); + WRITE_IO16_PM(ACPI_IOREG_PM1_STS, 0x400); // 0x00 + } + + // Set RTC_EN bit in PM1_EN to wake up from the alarm + SET_IO16_PM(ACPI_IOREG_PM1_EN, 0x400 ); // 0x02 +#endif + + // Do any specific porting if needed. + SBLib_S3InsteadOfWarmResetCallBack(); + + // Enable Sleep SMI for all S3 sleep SMI callback functions. + SET_IO32_PM(ACPI_IOREG_SMI_EN, BIT04); // 0x30 + // Triger S3 sleep callback functions. + RW_IO32_PM(ACPI_IOREG_PM1_CNTL, 0x1400, 0x1c00 ); // 0x04 + SET_IO32_PM(ACPI_IOREG_PM1_CNTL, 0x2000 ); // 0x04 +} +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------------------- +// Procedure: SB_Shutdown +// Description: This function Shuts the system down (S5) +// +// Input: VOID +// +// Output: VOID +// +//----------------------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID SB_Shutdown(VOID) +{ + //Check if Sleep SMI is enabled we will disable it. + RESET_IO16_PM(R_PCH_SMI_EN, BIT04); // 0x30 + + //Clear All PM Statuses + WRITE_IO16_PM(R_PCH_ACPI_PM1_STS, \ + READ_IO16_PM(R_PCH_ACPI_PM1_STS)); // 0x00 + + //Go to S5 + SET_IO16_PM(R_PCH_ACPI_PM1_CNT, 0x0f << 10); // 0x04 + + EFI_DEADLOOP() +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ClearGPIOResetSelect +// +// Description: Intel PCH Specification update rev 1.02, +// Document Changes 24. Update sec 19.5 +// 19.5 Addttional Consideration, Step 2 +// System BIOS is recommended to clear "GPIO Reset Select" +// registers [GP_RST_SEL1(GPIOBASE + offset 60h), GP_RST_SEL2 +// (GPIOBASE + offset 64h), GP_RST_SEL3(GPIOBASE + offset 68h) +// before issuing a hard or global reset unless specially +// requested by the platform designer. +// +// Input: None +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID ClearGPIOResetSelect(VOID) +{ + WRITE_IO32 (GPIO_BASE_ADDRESS + GP_IOREG_GP_RST_SEL1, BIT30); // 0x60 + WRITE_IO32 (GPIO_BASE_ADDRESS + GP_IOREG_GP_RST_SEL2, BIT30); // 0x64 + WRITE_IO32 (GPIO_BASE_ADDRESS + GP_IOREG_GP_RST_SEL3, BIT30); // 0x68 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SbLib_RunTimeResetCallback +// +// Description: Dispatch E-Link SbRuntimeResetElinkList. +// +// Input: IN EFI_RESET_TYPE ResetType +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +SbLib_RunTimeResetCallback( + IN EFI_RESET_TYPE ResetType + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINTN i; + + for (i = 0; SbRunResetCallbackList[i] != NULL; i++) + Status = SbRunResetCallbackList[i](ResetType); + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBLib_ResetSystem +// +// Description: This function is the reset call interface function published +// by the reset PPI +// +// Input: ResetType - Type of reset to be generated +// +// Output: SYSTEM RESET +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SBLib_ResetSystem ( + IN EFI_RESET_TYPE ResetType ) +{ + UINT8 OutputData; + UINT32 Data32; + UINT16 Data16; +#if defined CAPSULE_SUPPORT && CAPSULE_SUPPORT == 1 + EFI_GUID SbWarmResetGuid = SB_WARM_RESET_GUID; + CHAR16 SbWarmResetVar[] = SB_WARM_RESET_VARIABLE; + UINT32 SbWarmResetFlag = SB_WARM_RESET_TAG; + EFI_STATUS Status = EFI_SUCCESS; + EFI_GUID gCapsuleVendorGuid = EFI_CAPSULE_AMI_GUID; + EFI_PHYSICAL_ADDRESS IoData; + UINTN Size = sizeof(EFI_PHYSICAL_ADDRESS); +#endif + + SbLib_RunTimeResetCallback(ResetType); + + switch (ResetType) { + case EfiResetWarm: +#if defined CAPSULE_SUPPORT && CAPSULE_SUPPORT == 1 + if (pRS->GetVariable(CAPSULE_UPDATE_VAR,&gCapsuleVendorGuid, NULL, &Size, &IoData) == EFI_SUCCESS) { + Status = pRS->SetVariable( SbWarmResetVar, \ + &SbWarmResetGuid, \ + EFI_VARIABLE_NON_VOLATILE | \ + EFI_VARIABLE_BOOTSERVICE_ACCESS | \ + EFI_VARIABLE_RUNTIME_ACCESS, \ + sizeof(SbWarmResetFlag), \ + &SbWarmResetFlag ); + + SBLib_S3InsteadOfWarmReset(); + return; + } +#endif + WRITE_IO8 (R_PCH_RST_CNT, V_PCH_RST_CNT_SOFTSTARTSTATE); + OutputData = V_PCH_RST_CNT_SOFTRESET; + break; + + case EfiResetCold: + WRITE_IO8 (R_PCH_RST_CNT, V_PCH_RST_CNT_HARDSTARTSTATE); + // [EIP81593]> +#if defined COLD_RESET_WITH_POWER_CYCLE && \ + COLD_RESET_WITH_POWER_CYCLE == 1 + OutputData = V_PCH_RST_CNT_FULLRESET; +#else + OutputData = V_PCH_RST_CNT_HARDRESET; +#endif + // <[EIP81593] + break; + + case EfiResetShutdown: + // + // Firstly, ACPI decode must be enabled + // + SET_PCI8_SB(R_PCH_LPC_ACPI_CNT, B_PCH_LPC_ACPI_CNT_ACPI_EN); + + // + // Then, GPE0_EN should be disabled to avoid any GPI waking up the system from S5 + // + Data16 = 0; + + WRITE_IO32_PM(R_PCH_ACPI_GPE0a_EN, Data16); + WRITE_IO16_PM(R_PCH_ACPI_GPE0b_EN, Data16); + + // + // Secondly, PwrSts register must be cleared + // + // Write a "1" to bit[8] of power button status register at + // (PM_BASE + PM1_STS_OFFSET) to clear this bit + // + Data16 = B_PCH_SMI_STS_PM1_STS_REG; + WRITE_IO16_PM(R_PCH_ACPI_PM1_STS, Data16); + + // + // Finally, transform system into S5 sleep state + // + Data32 = READ_IO32_PM(R_PCH_ACPI_PM1_CNT); + Data32 &= ~(B_PCH_ACPI_PM1_CNT_SLP_TYP + B_PCH_ACPI_PM1_CNT_SLP_EN); + Data32 |= V_PCH_ACPI_PM1_CNT_S5; + WRITE_IO32_PM(R_PCH_ACPI_PM1_CNT, Data32); + Data32 = Data32 | B_PCH_ACPI_PM1_CNT_SLP_EN; + WRITE_IO32_PM(R_PCH_ACPI_PM1_CNT, Data32); + + EFI_DEADLOOP () + + default: + return; + } + + WRITE_IO8 (R_PCH_RST_CNT, OutputData); + // + // Waiting for system reset + // + EFI_DEADLOOP () +} + +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBLib_ExtResetSystem +// +// Description: This function is the extended reset call interface function +// provided by SB. +// +// Input: ResetType - The extended type of reset to be generated +// +// Output: SYSTEM RESET +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SBLib_ExtResetSystem ( + IN SB_EXT_RESET_TYPE ResetType ) +{ + UINT16 GpioBase; + UINT8 OutputData; + EFI_STATUS Status = EFI_SUCCESS; + + GpioBase = READ_PCI16_SB (R_PCH_LPC_GPIO_BASE) & B_PCH_LPC_GPIO_BASE_BAR; + + // Issue some delay before system reset. +#if SB_STALL_PPI_SUPPORT + Status = CountTime(4000, PM_BASE_ADDRESS); // 1ms +#endif + + // Disable All SMI Enables, include the Global SMI. + WRITE_IO32_PM(ACPI_IOREG_SMI_EN, 0); // 0x30 + + switch (ResetType) { + case SbResetFull: + case SbResetGlobal: + WRITE_IO32 ((GpioBase + R_PCH_GP_RST_SEL), 0); + WRITE_IO32 ((GpioBase + R_PCH_GP_RST_SEL2), 0); + WRITE_IO32 ((GpioBase + R_PCH_GP_RST_SEL3), 0); + + if (ResetType == SbResetGlobal) + SET_PCI32_SB(R_PCH_LPC_PMIR, B_PCH_LPC_PMIR_CF9GR); + + OutputData = V_PCH_RST_CNT_FULLRESET; + break; + + default: + return; + } + + WRITE_IO8 (R_PCH_RST_CNT, OutputData); + + // We should never get this far + EFI_DEADLOOP(); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: StopUsb +// +// Description: This routine stops all USB controller action. +// +// Input: Bus - The PCI bus number for the USB controller +// Dev - The PCI device number for the USB controller +// Fun - The PCI function number for the USB controller +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID StopUsb ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun ) +{ +//#### UINT32 MmioBase; +//#### UINT16 IoBase; +//#### UINT16 TimeOut = 0x1000; + +//#### if (READ_PCI32(Bus, Dev, Fun, 0) != 0xffffffff) { +//#### if ((READ_PCI32(Bus, Dev, Fun, 4) & 0x3) == 0) return; +//#### if (READ_PCI8(Bus, Dev, Fun, USB_REG_PI) == 0x20) { // USB 2.0 +//#### WRITE_PCI8(Bus, Dev, Fun, USB20_REG_LEGSUP_EXTCS, 0); // 0x6C +//#### MmioBase = READ_PCI32(Bus, Dev, Fun, USB20_REG_MEM_BASE_ADDR); +//#### RESET_MEM32(MmioBase | 0x20, 1); +//#### while (READ_MEM32(MmioBase | 0x20) & 1) { +//#### TimeOut--; +//#### if (TimeOut == 0) break; +//#### } +//#### } else { // USB 1.1 +//#### WRITE_PCI8(Bus, Dev, Fun, USB_REG_LEGSUP, 0); // 0xC0 +//#### IoBase = READ_PCI32(Bus, Dev, Fun, USB_REG_BASE_ADDR) & 0xfffe; +//#### RESET_IO16(IoBase, 1); +//#### while (IoRead16(IoBase) & 1) { +//#### TimeOut--; +//#### if (TimeOut == 0) break; +//#### } +//#### } +//#### } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: UsbS02SxWorkaround +// +// Description: PCH BIOS Spec Rev 0.5.0, Section 12.10.1 +// Additional Programming Requirements prior to enter S4/S5 +// +// Input: None +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +UsbS02SxWorkaround ( + VOID + ) +{ + UINT8 Index; + UINTN EhciPciRegBase; + UINT32 UsbBar; + UINT16 CmdReg; + UINT16 PowerState; + USB_CONTROLLER EhciControllersMap[PchEhciControllerMax] = { + { + PCI_DEVICE_NUMBER_PCH_USB, + PCI_FUNCTION_NUMBER_PCH_EHCI + }, + { + PCI_DEVICE_NUMBER_PCH_USB_EXT, + PCI_FUNCTION_NUMBER_PCH_EHCI2 + } + }; + + /// + /// System BIOS must execute the following steps prior to enter S4/S5. + /// + for (Index = 0; Index < GetPchEhciMaxControllerNum (); Index++) { + /// + /// Step 1 + /// Read "Memory Base Address (MEM_BASE) Register" of D26/D29:F0 + /// + EhciPciRegBase = MmPciAddress (PCIEX_BASE_ADDRESS, 0, EhciControllersMap[Index].Device, EhciControllersMap[Index].Function, 0); + UsbBar = MmioRead32 (EhciPciRegBase + R_PCH_EHCI_MEM_BASE); + CmdReg = MmioRead16 (EhciPciRegBase + R_PCH_EHCI_COMMAND_REGISTER); + PowerState = MmioRead16 (EhciPciRegBase + R_PCH_EHCI_PWR_CNTL_STS); + + if (UsbBar != 0xFFFFFFFF) { + /// + /// Check if the Ehci device is in D3 power state + /// + if ((PowerState & B_PCH_EHCI_PWR_CNTL_STS_PWR_STS) == V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D3) { + /// + /// Step 2 + /// Set "Power State" bit of PWR_CNTL_STS register, D26/D29:F0:54h [1:0] = 0h + /// + MmioWrite16 (EhciPciRegBase + R_PCH_EHCI_PWR_CNTL_STS, (PowerState &~B_PCH_EHCI_PWR_CNTL_STS_PWR_STS)); + /// + /// Step 3 + /// Write back the value from step 1 to the "Memory Base Address (MEM_BASE) Register" of D26/D29:F0 + /// + MmioWrite32 (EhciPciRegBase + R_PCH_EHCI_MEM_BASE, UsbBar); + /// + /// Step 4 + /// Enable "Memory Space Enable (MSE)" bit, set D26/D29:F0:04h [1] = 1b. + /// + SET_MEM16 ( + EhciPciRegBase + R_PCH_EHCI_COMMAND_REGISTER, + (UINT16) (B_PCH_EHCI_COMMAND_MSE) + ); + } + /// + /// Step 5 + /// Clear "Asynchronous Schedule Enable" and "Periodic Schedule Enable" bits, if "Run/Stop (RS)" bit, MEM_BASE + offset 20h [0] = 1b. + /// Proceed to steps below if "Run/Stop (RS)" bit, MEM_BASE + offset 20h [0] = 0b. + /// + if (!(MmioRead32 (UsbBar + R_PCH_EHCI_USB2CMD) & B_PCH_EHCI_USB2CMD_RS)) { + RESET_MEM32 (UsbBar + R_PCH_EHCI_USB2CMD, (UINT32)(B_PCH_EHCI_USB2CMD_ASE | B_PCH_EHCI_USB2CMD_PSE)); + SET_MEM32 (UsbBar + R_PCH_EHCI_USB2CMD, B_PCH_EHCI_USB2CMD_RS); + } + /// + /// Step 6 + /// If "Port Enabled/Disabled" bit of Port N Status and Control (PORTSC) Register is set, MEM_BASE + 64h [2] = 1b, + /// proceed steps below else continue with S4/S5. + /// + if ((MmioRead32 (UsbBar + R_PCH_EHCI_PORTSC0) & R_PCH_EHCI_PORTSC0_PORT_EN_DIS)) { + /// + /// Step 7 + /// Ensure that "Suspend" bit of Port N Status and Control (PORTSC) Register is set, MEM_BASE + 64h [7] = 1b. + /// + if (!(MmioRead32 (UsbBar + R_PCH_EHCI_PORTSC0) & R_PCH_EHCI_PORTSC0_SUSPEND)) { + SET_MEM32 (UsbBar + R_PCH_EHCI_PORTSC0, R_PCH_EHCI_PORTSC0_SUSPEND); + } + /// + /// Step 8 + /// Set delay of 25ms + /// + CountTime((25 * 1000), PM_BASE_ADDRESS); + /// + /// Step 9 + /// Clear "Run/Stop (RS)" bit, MEM_BASE + offset 20h [0] = 0b. + /// + RESET_MEM32 (UsbBar + R_PCH_EHCI_USB2CMD, (UINT32)(B_PCH_EHCI_USB2CMD_RS)); + } + /// + /// If the EHCI device is in D3 power state before executing this WA + /// + if ((PowerState & B_PCH_EHCI_PWR_CNTL_STS_PWR_STS) == V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D3) { + /// + /// Restore PCI Command Register + /// + MmioWrite16 (EhciPciRegBase + R_PCH_EHCI_COMMAND_REGISTER, CmdReg); + /// + /// Set "Power State" bit of PWR_CNTL_STS register to D3 state, D26/D29:F0:54h [1:0] = 3h + /// + MmioWrite16 (EhciPciRegBase + R_PCH_EHCI_PWR_CNTL_STS, PowerState); + } + /// + /// Step 10 + /// Continue with S4/S5 + /// + } + } +} + // [EIP83075]> +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: XhciS5Workaround +// +// Description: PCH BIOS Spec Rev 0.7.0, Section 13.5 +// Additional xHCI Controller Configurations Prior to Entering S5 +// +// Input: None +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID XhciS5Workaround ( VOID ) +{ + UINT32 XhciMmioBase; + // + // Check if XHCI controller is enabled + // + if ((READ_MEM32_RCRB(R_PCH_RCRB_FUNC_DIS) & B_PCH_RCRB_FUNC_DIS_XHCI) != 0) { + return ; + } + // + // System BIOS must execute the following steps for all steppings prior to S5 + // + // + XhciMmioBase = READ_PCI32( DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_XHCI, \ + PCI_FUNCTION_NUMBER_PCH_XHCI, \ + R_PCH_XHCI_MEM_BASE + ) & ~(0x0F); + + if (XhciMmioBase != 0) { + //Clear "Run/Stop (RS)" bit, + RESET_MEM32(XhciMmioBase + R_PCH_XHCI_USBCMD, B_PCH_XHCI_USBCMD_RS); + } + // Step 1 + // Set D3hot state - 11b + // + SET_PCI8( DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_XHCI, \ + PCI_FUNCTION_NUMBER_PCH_XHCI, \ + R_PCH_XHCI_PWR_CNTL_STS, \ + (BIT00 | BIT01) + ); + + // + // Step 2 + // Set "PME Enable" bit of PWR_CNTL_STS register, D20:F0:74h[8] = 1h + // + SET_PCI16( DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_XHCI, \ + PCI_FUNCTION_NUMBER_PCH_XHCI, \ + R_PCH_XHCI_PWR_CNTL_STS, \ + BIT08 + ); +} + // <[EIP83075] + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBLib_BeforeShutdown +// +// Description: This routine will be called before shutdown or ACPI S5,(If +// S5 Sleep SMI is enabled. +// +// Input: None +// +// Output: None +// +// Notes: Porting required if any workaround is needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SBLib_BeforeShutdown (VOID) +{ + UINT8 DevNo; + UINT8 FunNo; + +//#### StopUsb( EUSB_BUS, EUSB_DEV, EUSB_FUN ); + + for (DevNo = 0; DevNo < 0x20 ; DevNo++) { + if (READ_PCI32(0, DevNo, 0, PCI_VID) != 0xffffffff) { + FunNo = (READ_PCI8(0, DevNo, 0, PCI_HDR) & 0x80) ? 8 : 1; + do { + FunNo--; + if (READ_PCI32(0, DevNo, FunNo, PCI_VID) != 0xffffffff) { + RESET_PCI16(0, DevNo, FunNo, PCI_CMD, 4); + } + } while (FunNo); + } + } +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBLib_Shutdown +// +// Description: Shutdown the system (Enter soft-off/S5) +// +// Input: None +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SBLib_Shutdown (VOID) +{ + UINT16 Buffer16; + + // Clear ME wake status + ClearMeWakeSts(); + + UsbS02SxWorkaround(); + XhciS5Workaround(); // [EIP83075] + + // Disable Sleep SMI + RESET_IO32_PM(ACPI_IOREG_SMI_EN, 0x10); // 0x30 + + SBLib_BeforeShutdown(); + + // Clear power button status + Buffer16 = READ_IO16(PM_BASE_ADDRESS) | (UINT16)(1 << 8); + do { + WRITE_IO16(PM_BASE_ADDRESS, Buffer16); + for (Buffer16 = 0; Buffer16 < 0x100; Buffer16++) + WRITE_IO8(IO_DELAY_PORT, (UINT8)Buffer16); + Buffer16 = READ_IO16(PM_BASE_ADDRESS); + } while (Buffer16 & 0x100); + + // Enter soft-off/S5 + RW_IO16(PM_BASE_ADDRESS + ACPI_IOREG_PM1_CNTL, \ + (SLP_S5 | 8 ) << 10, 15 << 10); + + // We should never get this far + EFI_DEADLOOP(); +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure:ClearMeWakeSts +// +// Description: Clear the ME wake up status. +// +// Input: None +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID ClearMeWakeSts(VOID) +{ +// Mmio32(SB_RCBA, ICH_RCRB_PRSTS) |= BIT00; + SET_MEM8_RCRB(R_PCH_RCRB_PRSTS, BIT00); +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: Enable_GbE_PME +// +// Description: Enable the Gigabit Ethernet Controller PME +// +// Input: None +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID Enable_GbE_PME(VOID) +{ + if (READ_PCI16_LAN(R_PCH_LAN_VENDOR_ID) != 0xffff) + { + if (GetPchSeries() == PchLp) { + WRITE_IO16_PM(ACPI_PCHLP_IOREG_GPE0_STS+0x0c, BIT13); + SET_IO16_PM(ACPI_PCHLP_IOREG_GPE0_EN+0x0c, BIT13); + } else { + WRITE_IO16_PM(ACPI_IOREG_GPE0_STS, BIT13); + SET_IO16_PM(ACPI_IOREG_GPE0_EN, BIT13); + } + SET_PCI16_LAN(R_PCH_LAN_PMCS, BIT08); + } +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HighBitSet32 +// +// Description: Returns the bit position of the highest bit set in a 32-bit value. Equivalent +// to log2(x). +// +// Input: Operand - Operand The 32-bit operand to evaluate. +// +// Output: Position of the highest bit set in Operand if found. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +INTN +EFIAPI +HighBitSet32 ( + IN UINT32 Operand + ) +{ + INTN BitIndex; + + for (BitIndex = -1; Operand != 0; BitIndex++, Operand >>= 1); + return BitIndex; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetPowerOfTwo32 +// +// Description: Returns the value of the highest bit set in a 32-bit value. Equivalent to +// 1 << HighBitSet32(x). +// +// Input: Operand - Operand The 32-bit operand to evaluate. +// +// Output: Return 1 << HighBitSet32(Operand) +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT32 +EFIAPI +GetPowerOfTwo32 ( + IN UINT32 Operand + ) +{ + if (Operand == 0) { + return 0; + } + + return 1ul << HighBitSet32 (Operand); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ChipsetFlashDeviceWriteEnable +// +// Description: This function is invoked to do any chipset specific +// operations, that are necessary when enabling the Flash Part +// for writing. +// +// Input: None +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID ChipsetFlashDeviceWriteEnable (VOID) +{ +// UINT32 Data32; + + // + // Set BIOSWE bit (B0:D31:F0 Offset DCh [0]) = 1b + // + RW_PCI8_SB(SB_REG_BIOS_CNTL, BIT00, BIT05); + + // + // PCH BIOS Spec Section 3.7 BIOS Region SMM Protection Enabling + // If the following steps are implemented: + // - Set the SMM_BWP bit (B0:D31:F0 Offset DCh [5]) = 1b + // - Follow the 1st recommendation in section 3.6 + // the BIOS Region can only be updated by following the steps bellow: + // - Once all threads enter SMM + // - Read memory location FED30880h OR with 00000001h, place the result in EAX, + // and write data to lower 32 bits of MSR 1FEh (sample code available) + // - Set BIOSWE bit (B0:D31:F0 Offset DCh [0]) = 1b + // - Modify BIOS Region + // - Clear BIOSWE bit (B0:D31:F0 Offset DCh [0]) = 0b + // - Read memory location FED30880h AND with FFFFFFFEh, place the result in EAX, + // and write data to lower 32 bits of MSR 1FEh (sample code available) + // + + // + // Check if SMM_BWP bit and BLE bit are both set + // + if ((READ_PCI8_SB(SB_REG_BIOS_CNTL) & 0x22) == 0x22) { + // + // Read memory location FED30880h OR with 00000001h, place the result in EAX, + // and write data to lower 32 bits of MSR 1FEh (sample code available) + // + // EIP106353 >> + if ( !((ReadMsr (MSR_PLATFORM_INFO) & B_MSR_PLATFORM_INFO_PFAT_AVAIL) && + (ReadMsr (MSR_PLAT_FRMW_PROT_CTRL) & B_MSR_PLAT_FRMW_PROT_CTRL_EN)) ) { +// Data32 = MmioRead32 ((UINTN) (0xFED30880)) | (UINT32) (BIT0); +// WriteMsr(0x1FE, Data32); + } + // EIP106353 << + } + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ChipsetFlashDeviceWriteDisable +// +// Description: This function is invoked to do any chipset specific +// operations, that are necessary when disabling the Flash Part +// for writing. +// +// Input: None +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID ChipsetFlashDeviceWriteDisable (VOID) +{ +// UINT32 Data32; + + // + // Clear BIOSWE bit (B0:D31:F0 Offset DCh [0]) = 0b + // + RESET_PCI8_SB(SB_REG_BIOS_CNTL, BIT00); + // + // Check if SMM_BWP bit and BLE bit are both set + // + if ((READ_PCI8_SB(SB_REG_BIOS_CNTL) & 0x22) == 0x22) { + // + // Read memory location FED30880h AND with FFFFFFFEh, place the result in EAX, + // and write data to lower 32 bits of MSR 1FEh (sample code available) + // + // EIP106353 >> + if ( !((ReadMsr (MSR_PLATFORM_INFO) & B_MSR_PLATFORM_INFO_PFAT_AVAIL) && + (ReadMsr (MSR_PLAT_FRMW_PROT_CTRL) & B_MSR_PLAT_FRMW_PROT_CTRL_EN)) ) { +// Data32 = MmioRead32 ((UINTN) (0xFED30880)) & (UINT32) (~BIT0); +// WriteMsr (0x1FE, Data32); + } + // EIP106353 << + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: BiosLockEnableSMIFlashHook +// +// Description: The procedure clears BIOSWR_STS after Enable Flash SWSMI, +// for prevent that AFU write operation fail when BIOS Lock +// is enabled. +// +// Input: UINT8 SwSmiNum +// UINT64 Buffer +// +// Output: UINT64 Buffer +// +// Returns: NONE +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +BiosLockEnableSMIFlashHook ( + IN UINT8 SwSmiNum, + IN OUT UINT64 Buffer +) +{ + if ((SwSmiNum != 0x20) || \ + ((READ_PCI8_SB(R_PCH_LPC_BIOS_CNTL) & B_PCH_LPC_BIOS_CNTL_BLE) == 0)) + return; + + // Clear BIOSWR_STS + SET_IO16_TCO(R_PCH_TCO1_STS, B_PCH_TCO1_STS_BIOSWR); + + // Clear TCO_STS + SET_IO16_PM(R_PCH_SMI_STS, B_PCH_SMI_STS_TCO); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBIsDefaultConfigMode +// +// Description: This function determines if the system should boot with the +// default configuration. +// +// Input: EFI_PEI_SERVICES - Pointer to the PEI services table +// EFI_PEI_READ_ONLY_VARIABLE2_PPI - Pointer to the Read +// Variable#2 PPI +// (The pointer can be used to read and enumerate existing NVRAM +// variables) +// +// Output: TRUE - Firmware will boot with default configuration. +// +// Notes: 1. If boot with default configuration is detected, default +// values for NVRAM variables are used. +// 2. Normally we have to check RTC power status or CMOS clear +// jumper status to determine whether the system should boot +// with the default configuration. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SBIsDefaultConfigMode ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *ReadVariablePpi ) +{ + UINT8 Buffer8; + + Buffer8 = READ_PCI8_SB(SB_REG_GEN_PMCON_3); // 0xA4 + return (Buffer8 & 4) ? TRUE : FALSE; +} + +#if SB_STALL_PPI_SUPPORT + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: CountTime +// +// Description: This function delays for the number of micro seconds passed in +// +// Input: DelayTime - Number of microseconds(us) to delay +// BaseAddr - The I/O base address of the ACPI registers +// +// Output: EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS CountTime ( + IN UINTN DelayTime, + IN UINT16 BaseAddr ) // Only needs to be 16 bit for I/O address +{ +// The following code is to generate delay for specified amount of micro +// seconds using ACPI timer. + UINTN TicksNeeded; + UINT32 TimerValue; + UINT32 NewTimerValue; + UINTN OverFlow; + UINTN TheRest; + UINTN EndValue; + + // Set up timer to point to the ACPI Timer register + BaseAddr += ACPI_IOREG_PM1_TMR; // *** PORTING NEEDED + + // There are 3.58 ticks per us, so we have to convert the number of us + // passed in to the number of ticks that need to pass before the timer has + // expired convert us to Ticks, don't loose significant figures or as few + // as possible do integer math in ticks/tens of ns and then divide by 100 + // to get ticks per us + OverFlow = 0; + +//#### TheRest = TicksNeeded = (DelayTime * 358) /100; + TicksNeeded = DelayTime * 3; //(DelayTime * 3) + TicksNeeded += (DelayTime) / 2; //(DelayTime * 5)/10 + TicksNeeded += (DelayTime * 2) / 25; //(DelayTime * 8)/100 + TheRest = TicksNeeded; + + // 32 bits corresponds to approz 71 mins no delay should be that long + // otherwise get the number of times the counter will have to overflow + // to delay as long as needed + if (NUM_BITS_IN_ACPI_TIMER < MAX_ACPI_TIMER_BITS) { + OverFlow = TicksNeeded / (1 << NUM_BITS_IN_ACPI_TIMER); + TheRest = TicksNeeded % (1 << NUM_BITS_IN_ACPI_TIMER); + } + + // Read ACPI Timer + TimerValue = IoRead32( BaseAddr ); + + // Need to adjust the values based off of the start time + EndValue = TheRest + TimerValue; + + // Check for overflow on addition. possibly a problem + if (EndValue < TimerValue) { + OverFlow++; + } else { + if (NUM_BITS_IN_ACPI_TIMER < MAX_ACPI_TIMER_BITS) { + // Here make sure that EndValue is less than the max value + // of the counter + OverFlow += EndValue / (1 << NUM_BITS_IN_ACPI_TIMER); + EndValue = EndValue % (1 << NUM_BITS_IN_ACPI_TIMER); + } + } + + // Let the timer wrap around as many times as calculated + while (OverFlow) { + // read timer amd look to see if the new value read is less than + // the current timer value. if this happens the timer overflowed + NewTimerValue = IoRead32(BaseAddr); + + if (NewTimerValue < TimerValue) OverFlow--; + + TimerValue = NewTimerValue; + } + + // Now wait for the correct number of ticks that need to occur after + // all the needed overflows + while (EndValue > TimerValue) { + NewTimerValue = IoRead32(BaseAddr); + + // check to see if the timer overflowed. if it did then + // the time has elapsed. Because EndValue should be greater than + // TimerValue + if (NewTimerValue < TimerValue) break; + + TimerValue = NewTimerValue; + } + + return EFI_SUCCESS; +} + + +#endif + +//--------------------------------------------------------------------------- + +#if CMOS_MANAGER_SUPPORT +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ReadWriteCmosBank2 +// +// Description: This function is used to access addresses in the CMOS +// register range (0x80-0xff), for PEI and DXE boot phases. +// +// Input: **PeiServices - PEI Services table pointer +// (NULL in DXE phase) +// AccessType - ReadType or WriteType to specify the +// type of access +// CmosRegister - The CMOS register to access +// *CmosParameterValue - Pointer to the data variable to be +// accessed +// +// Output: EFI_STATUS (return value) +// EFI_SUCCESS - The access operation was successfull. +// Otherwise - A valid EFI error code is returned. +// +// Modified: None +// +// Referrals: IoRead8, IoWrite8 +// +// Notes: This function is used when a translation from logical address +// to index port value is required. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS ReadWriteCmosBank2 ( + IN EFI_PEI_SERVICES **PeiServices, // NULL in DXE phase + IN CMOS_ACCESS_TYPE AccessType, + IN UINT16 CmosRegister, + IN OUT UINT8 *CmosParameterValue ) +{ + if ((CmosRegister < 0x80) || (CmosRegister > 0xff)) + return EFI_INVALID_PARAMETER; + + // Some chipsets require tranlation from the logical CMOS address to a + // physical CMOS index port value. However, other chipsets do not require + // a translation and the index/data port can be directly used for + // accessing the second bank. + + IoWrite8( CMOS_IO_EXT_INDEX, (UINT8)CmosRegister ); + + if (AccessType == ReadType) { + *CmosParameterValue = IoRead8( CMOS_IO_EXT_DATA ); + } else { + IoWrite8( CMOS_IO_EXT_DATA, *CmosParameterValue ); + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbGetRtcPowerStatus +// +// Description: This function is checked CMOS battery is good or not. +// +// Input: **PeiServices - PEI Services table pointer (NULL in DXE phase) +// +// Output: BOOLEAN +// TRUE - The CMOS is battery is good. +// FALSE - The CMOS is battery is bad. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SbGetRtcPowerStatus ( + IN EFI_PEI_SERVICES **PeiServices ) +{ + return (READ_PCI8_SB(SB_REG_GEN_PMCON_3) & 4) ? FALSE : TRUE; // 0xA4 +} + +#endif // #if CMOS_MANAGER_SUPPORT + //Improve alternate access mode >> +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SwitchAlternateAccessMode +// +// Description: Enable or disable Alternate Access Mode. +// +// Input: TRUE: Enable Alternate Access Mode +// FALSE: Disable Alternate Access Mode +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID SwitchAlternateAccessMode +( + BOOLEAN Switch +) +{ + if (Switch) { + do { + // Enable Alternate Access Mode + SET_MEM32_RCRB(R_PCH_RCRB_GCS, B_PCH_RCRB_GCS_AME); + } while((READ_MEM32_RCRB(R_PCH_RCRB_GCS) & B_PCH_RCRB_GCS_AME) == 0); + } else { + do { + // Disable Alternate Access Mode + RESET_MEM32_RCRB(R_PCH_RCRB_GCS, B_PCH_RCRB_GCS_AME); + } while(READ_MEM32_RCRB(R_PCH_RCRB_GCS) & B_PCH_RCRB_GCS_AME); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ReadPort70h +// +// Description: Read port 70h. +// +// Input: None +// +// Output: Data of port 70h. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8 ReadPort70h ( VOID ) +{ + UINT8 Port70h; + + SwitchAlternateAccessMode (TRUE); + + Port70h = IoRead8(RTC_INDEX_REG); + + SwitchAlternateAccessMode (FALSE); + + return Port70h; +} //Improve alternate access mode << + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ReadCmos +// +// Description: This function reads one byte from CMOS register addressed by Index +// +// Input: UINT8 Index +// +// Output: UINT8 - read value +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8 ReadCmos( + IN UINT8 Index +) +{ + // Read bit 7 (NMI setting). + UINT8 NMI = 0; + volatile UINT8 Value; + BOOLEAN IntState = CPULib_GetInterruptState(); + UINT8 RtcIndexPort; + UINT8 RtcDataPort; + + CPULib_DisableInterrupt(); + + if (Index < 0x80) { + // Standard CMOS + RtcIndexPort = RTC_INDEX_REG; + RtcDataPort = RTC_DATA_REG; + + if (Index < 0x80) //Improve alternate access mode >> + // Save current NMI_EN. + NMI = ReadPort70h() & RTC_NMI_MASK; //Improve alternate access mode << + + } else { + // Upper CMOS + RtcIndexPort = CMOS_IO_EXT_INDEX; + RtcDataPort = CMOS_IO_EXT_DATA; + } + + Index &= ~RTC_NMI_MASK; + + IoWrite8(RtcIndexPort, Index | NMI); + Value = IoRead8(RtcDataPort); // Read register. + + if (IntState) CPULib_EnableInterrupt(); + + return (UINT8)Value; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: WriteCmos +// +// Description: This function writes value to CMOS register addressed by Index +// +// Input: UINT8 Index - CMOS register index +// UINT8 Value - value to write +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID WriteCmos( + IN UINT8 Index, + IN UINT8 Value +) +{ + // Read bit 7 (NMI setting). + UINT8 NMI = 0; + BOOLEAN IntState = CPULib_GetInterruptState(); + UINT8 RtcIndexPort; + UINT8 RtcDataPort; + + CPULib_DisableInterrupt(); + + if (Index < 0x80) { + // Standard CMOS + RtcIndexPort = RTC_INDEX_REG; + RtcDataPort = RTC_DATA_REG; + + //Improve alternate access mode >> + // Save current NMI_EN. + NMI = ReadPort70h() & RTC_NMI_MASK; + //Improve alternate access mode << + } else { + // Upper CMOS + RtcIndexPort = CMOS_IO_EXT_INDEX; + RtcDataPort = CMOS_IO_EXT_DATA; + } + + Index &= ~RTC_NMI_MASK; + + IoWrite8(RtcIndexPort, Index | NMI); + IoWrite8(RtcDataPort, Value); // Write Register. + + if (IntState) CPULib_EnableInterrupt(); +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbLib_GetSmiState +// +// Description: This function returns SMI state +// +// Input: None +// +// Output: TRUE - SMI enabled, FALSE - SMI disabled +// +// Note: This function must work at runtime. Do not use boot time +// services/protocols. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SbLib_GetSmiState (VOID) +{ +#if SMM_SUPPORT + static BOOLEAN OriginalSmiState = FALSE; + static BOOLEAN HadBeenCame = FALSE; + volatile BOOLEAN SmiState = (READ_IO32_PM(ACPI_IOREG_SMI_EN) & 1) ? \ + TRUE : FALSE; + + if (HadBeenCame && SmiState) HadBeenCame = FALSE; + + if (HadBeenCame) { + SmiState = OriginalSmiState; + } else { + OriginalSmiState = SmiState; + HadBeenCame = TRUE; + } + + return SmiState; +#else + return FALSE; +#endif +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbLib_SmiDisable +// +// Description: This function disables SMI +// +// Input: None +// +// Output: None +// +// Note: This function should be used ONLY in critical parts of code. +// This function must work at runtime. Do not use boot time +// services/protocols +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SbLib_SmiDisable (VOID) +{ +#if SMM_SUPPORT + RESET_IO32_PM(ACPI_IOREG_SMI_EN, 3); // 0x30 +#endif +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbLib_SmiEnable +// +// Description: This function enables SMI +// +// Input: None +// +// Output: None +// +// Note: This function should be used ONLY in critical parts of code. +// This function must work at runtime. Do not use boot time +// services/protocols +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SbLib_SmiEnable (VOID) +{ + +#if SMM_SUPPORT + SET_IO32_PM(ACPI_IOREG_SMI_EN, 2); // 0x30 + SET_IO32_PM(ACPI_IOREG_SMI_EN, 1); // 0x30 +#endif +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: CspLibCheckPowerLoss +// +// Description: This function is PM Specific function to check and Report to +// the System Status Code - CMOS Battary and Power Supply Power +// loss/failure. Also it responcibe of clearing PM Power Loss +// Statuses +// +// Input: None +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID CspLibCheckPowerLoss (VOID) +{ + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbLib_SetLpcDeviceDecoding +// +// Description: This function sets LPC Bridge Device Decoding +// +// Input: *LpcPciIo - Pointer to LPC PCI IO Protocol +// Base - I/O base address, if Base is 0 means disabled the +// decode of the device +// DevUid - The device Unique ID +// Type - Device Type, please refer to AMISIO.h +// +// Output: EFI_STATUS +// EFI_SUCCESS - Set successfully. +// EFI_UNSUPPORTED - There is not proper Device Decoding +// register for the device UID. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SbLib_SetLpcDeviceDecoding ( + IN EFI_PCI_IO_PROTOCOL *LpcPciIo, + IN UINT16 Base, + IN UINT8 DevUid, + IN SIO_DEV_TYPE Type ) +{ + EFI_STATUS Status = EFI_UNSUPPORTED; + + // Porting Required + UINT16 ComRng[] = { 0x3f8, 0x2f8, 0x220, 0x228, \ + 0x238, 0x2e8, 0x338, 0x3e8, 0}; + UINT16 LptRange[] = { 0x378, 0x278, 0x3bc, 0}; + UINT16 FpcRange[] = { 0x3f0, 0x370, 0}; + UINT16 IoRangeMask16 = 0xffff; + UINT16 IoRangeSet16 = 0; + UINT16 IoEnMask16 = 0xffff; + UINT16 IoEnSet16 = 0; + UINT8 i; + + switch (Type) { + // FDC Address Range + case (dsFDC) : + if (Base == 0) IoEnMask16 &= ~BIT03; + else { + for (i = 0; (FpcRange[i] != 0) && (FpcRange[i] != Base); i++); + if (FpcRange[i]) { + IoEnSet16 |= BIT03; + IoRangeMask16 &= ~BIT12; + IoRangeSet16 |= (i << 12); + } + else return EFI_UNSUPPORTED; + } + break; + + // LPT Address Range + case (dsLPT) : + if (Base == 0) IoEnMask16 &= ~BIT02; + else { + for (i = 0; (LptRange[i] != 0) && (LptRange[i] != Base); i++); + if (LptRange[i]) { + IoEnSet16 |= BIT02; + IoRangeMask16 &= ~(BIT09 | BIT08); + IoRangeSet16 |= (i << 8); + } else return EFI_UNSUPPORTED; + } + break; + + // COM x Address Range + case (dsUART) : + if (Base == 0) { + switch (DevUid) { + case 0 : + IoEnMask16 &= ~BIT00; + break; + case 1 : + IoEnMask16 &= ~BIT01; + break; + case 2 : + break; + case 3 : + break; + default: + break; + } + } else { + if (DevUid < 2) { + for (i = 0; (ComRng[i] != 0) && (ComRng[i] != Base); i++); + if (ComRng[i]) { + if (DevUid) { + IoEnSet16 |= BIT01; + IoRangeMask16 &= ~(BIT06 | BIT05 | BIT04); + IoRangeSet16 |= (i << 4); + } else { + IoEnSet16 |= BIT00; + IoRangeMask16 &= ~(BIT02 | BIT01 | BIT00); + IoRangeSet16 |= i; + } + } else return EFI_UNSUPPORTED; + } else { + SbLib_SetLpcGenericDecoding( LpcPciIo, \ + Base , \ + 8, \ + TRUE ); + } + } + break; + + // KBC Address Enable + case (dsPS2K) : + case (dsPS2M) : + case (dsPS2CK) : + case (dsPS2CM) : + if (Base == 0) IoEnMask16 &= ~BIT10; + else IoEnSet16 |= BIT10; + break; + + // Game Port Address Enable + case (dsGAME) : + if (Base == 0) IoEnMask16 &= ~(BIT09 | BIT08); + else { + if (Base == 0x200) { + IoEnSet16 |= BIT08; + } else { + if (Base == 0x208) IoEnSet16 |= BIT09; + else return EFI_UNSUPPORTED; + } + } + break; + + // Other Address Enable + case (0xff) : + switch (Base) { + case (0x2e) : + IoEnSet16 |= BIT12; + break; + case (0x4e) : + IoEnSet16 |= BIT13; + break; + case (0x62) : + case (0x63) : + case (0x64) : + case (0x65) : + case (0x66) : + IoEnSet16 |= BIT11; + break; + case (0) : + return EFI_UNSUPPORTED; + break; + default : + SbLib_SetLpcGenericDecoding( LpcPciIo, \ + Base , \ + 4, \ + TRUE ); + break; + } + +//#### if (Base == 0x2e) IoEnSet16 |= BIT12; +//#### else { +//#### if (Base == 0x4e) IoEnSet16 |= BIT13; +//#### else { +//#### if (Base) SbLib_SetLpcGenericDecoding( LpcPciIo, \ +//#### Base , \ +//#### 4, \ +//#### TRUE ); +//#### else return EFI_UNSUPPORTED; +//#### } +//#### } + + break; + + default : + return EFI_UNSUPPORTED; + } + + RW_PCI16_SB(SB_REG_LPC_IO_DEC, IoRangeSet16, ~IoRangeMask16); // 0x80 + RW_PCI16_SB(SB_REG_LPC_EN, IoEnSet16, ~IoEnMask16); // 0x82 + // Porting End + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbLib_SetLpcGenericDecoding +// +// Description: This function sets LPC Bridge Generic Decoding +// +// Input: *LpcPciIo - Pointer to LPC PCI IO Protocol +// Base - I/O base address +// Length - I/O Length +// Enabled - Enable/Disable the generic decode range register +// +// Output: EFI_STATUS +// EFI_SUCCESS - Set successfully. +// EFI_UNSUPPORTED - This function is not implemented or the +// Length more than the maximum supported +// size of generic range decoding. +// EFI_INVALID_PARAMETER - the Input parameter is invalid. +// EFI_OUT_OF_RESOURCES - There is not available Generic +// Decoding Register. +// EFI_NOT_FOUND - the generic decode range will be disabled +// is not found. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SbLib_SetLpcGenericDecoding ( + IN EFI_PCI_IO_PROTOCOL *LpcPciIo, + IN UINT16 Base, + IN UINT16 Length, + IN BOOLEAN Enable ) +{ + // Porting Required + UINT32 IoGenDecode32; + UINT16 IoGenDecIndex; + UINT16 Buffer16; + UINT8 Bsf8 = 0; + UINT8 Bsr8 = 0; + + if (Length > 0x100) return EFI_UNSUPPORTED; + + if (Length == 0) return EFI_INVALID_PARAMETER; + + if (Length < 4) Length = 4; + + // Read I/O Generic Decodes Register. + for (IoGenDecIndex = 0; IoGenDecIndex < 4; IoGenDecIndex++) { + IoGenDecode32 = READ_PCI32_SB(SB_REG_GEN1_DEC + IoGenDecIndex * 4); + if (Enable) { + if ((IoGenDecode32 & 1) == 0) break; + } else { + if (((IoGenDecode32 & 0xfffc) == Base) && (IoGenDecode32 & 1)) { + IoGenDecode32 = 0; // Disable & clear the base/mask fields + break; + } + } + } + + if (Enable) { + if (IoGenDecIndex == 4) return EFI_OUT_OF_RESOURCES; + + Buffer16 = Length; + while ((Buffer16 % 2) == 0) { + Buffer16 /= 2; + Bsf8++; + } + + while (Length) { + Length >>= 1; + Bsr8++; + } + + if (Bsf8 == (Bsr8 - 1)) Bsr8--; + + Length = (1 << Bsr8) - 1 ; + + Base &= (~Length); + + IoGenDecode32 = Base | (UINT32)((Length >> 2) << 18) | 1; + + } else { + if (IoGenDecIndex == 4) return EFI_NOT_FOUND; + } + + WRITE_PCI32_SB(SB_REG_GEN1_DEC + IoGenDecIndex * 4, IoGenDecode32); + // Porting End + + return EFI_SUCCESS; + +} + +//--------------------------------------------------------------------------- +#if SMM_SUPPORT +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBSmmSaveRestoreStates +// +// Description: This hook is called in the very SMI entry and exit. +// Save/Restore chipset data if needed. +// +// Input: Save - TRUE = Save / FALSE = Restore +// +// Output: EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SBSmmSaveRestoreStates ( + IN BOOLEAN Save ) +{ + static volatile UINT8 StoreCMOS; + static volatile UINT8 StoreExtCMOS; + static volatile UINT32 StoreCF8; + static volatile UINT32 AltAcc; + static volatile UINT8 RtcRegA; + UINT8 SbCmosMiscFlag = 0; +#if defined(HPET_APIC_INTERRUPT_MODE) && (HPET_APIC_INTERRUPT_MODE != 0) + static volatile BOOLEAN IsHpetApicEn = FALSE; + static volatile UINT8 StoreIoApicIndex; + volatile UINT8 Irq; +#endif + UINT32 Data32 =0; + + if (Save) { + StoreCF8 = IoRead32(0xcf8); // Store CF8 (PCI index) + + // Save Alternate access bit. + AltAcc = READ_MEM32_RCRB(RCRB_MMIO_GCS) & 0x10; + + StoreCMOS = ReadPort70h(); // Save 0x70 + + StoreExtCMOS = IoRead8(CMOS_IO_EXT_INDEX); // Save 0x72 + +#if defined CMOS_MANAGER_SUPPORT && CMOS_MANAGER_SUPPORT + IoWrite8(CMOS_IO_EXT_INDEX, SB_CMOS_MISC_FLAG_REG); + IoWrite8(CMOS_IO_EXT_DATA, 0); +#endif +#if defined(HPET_APIC_INTERRUPT_MODE) && (HPET_APIC_INTERRUPT_MODE != 0) + StoreIoApicIndex = MMIO_READ8(APCB); + IsHpetApicEn = IsHpetApicEnable(); + if (IsHpetApicEn) { + Irq = GetHpetApicPin(); + IoApicMaskIrq(Irq); + } +#endif + + Data32 = MmioRead32 ((UINTN) (0xFED30880)) | (UINT32) (BIT0); + WriteMsr(0x1FE, Data32); + + } else { + do { + RtcRegA = SBLib_CmosRead(RTC_REG_A_INDEX); + } while (RtcRegA & 0x80); + +#if defined CMOS_MANAGER_SUPPORT && CMOS_MANAGER_SUPPORT + IoWrite8(CMOS_IO_EXT_INDEX, SB_CMOS_MISC_FLAG_REG); + SbCmosMiscFlag = IoRead8(CMOS_IO_EXT_DATA); + + if (SbCmosMiscFlag & ENABLE_NMI_BEFORE_SMI_EXIT) + StoreCMOS &= ~BIT07; // Enable NMI_EN + + if (SbCmosMiscFlag & DISABLE_NMI_BEFORE_SMI_EXIT) + StoreCMOS |= BIT07; // Disable NMI_EN +#endif + + IoWrite8(CMOS_ADDR_PORT, StoreCMOS); // Restore 0x70 + IoWrite8(CMOS_IO_EXT_INDEX, StoreExtCMOS); // Restore 0x72 + + // Restore Alternate access bit. + do { //Improve alternate access mode >> + RW_MEM32_RCRB(RCRB_MMIO_GCS, AltAcc, 0x10); + } while ((READ_MEM32_RCRB(RCRB_MMIO_GCS) & 0x10) != AltAcc); //Improve alternate access mode << + + IoWrite32(0xcf8, StoreCF8); // Restore 0xCF8 (PCI index) + +#if defined(HPET_APIC_INTERRUPT_MODE) && (HPET_APIC_INTERRUPT_MODE != 0) + if (IsHpetApicEn) { + Irq = GetHpetApicPin(); + IoApicUnmaskIrq(Irq); + IoApicEoi(Irq); + } + + MMIO_WRITE8(APCB, StoreIoApicIndex); + StoreIoApicIndex = MMIO_READ8(APCB); +#endif + + Data32 = MmioRead32 ((UINTN) (0xFED30880)) & (UINT32) (~BIT0); + WriteMsr(0x1FE, Data32); + + } + + return EFI_SUCCESS; +} + +//--------------------------------------------------------------------------- +#endif // END OF SMM Related Porting Hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBProtectedPciDevice +// +// Description: This function is called by PCI Bus Driver before configuring +// or disabling any PCI device. This function should examine the +// Vendor/Device ID or PCI Bus, Device and Function numbers to +// make sure it is not a south bridge device or any other device +// which should no be configured by PCI Bus Driver. +// +// Input: *PciDevice - Pointer to PCI Device Info structure. +// +// Output: EFI_STATUS +// EFI_SUCCESS - SKIP this device, do not touch +// PCI Command register. +// EFI_UNSUPPORTED - DON'T SKIP this device do complete +// enumeration as usual. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS SBProtectedPciDevice ( + IN PCI_DEV_INFO *PciDevice ) +{ + +//####if ((PciDevice->Address.Addr.Bus == SMBUS_BUS) && \ +//#### (PciDevice->Address.Addr.Device == SMBUS_DEV) && \ +//#### (PciDevice->Address.Addr.Function == SMBUS_FUN)) { +//#### +//#### return EFI_SUCCESS; +//####} + + return EFI_UNSUPPORTED; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBProgramPciDevice +// +// Description: This function is called by PCI Bus Driver before installing +// Protocol Interface for the input device. +// +// Input: *PciDevice - Pointer to PCI Device Info structure. +// +// Output: EFI_SUCCESS +// +// Notes: All resource in the device had been assigned, but the command +// register is disabled. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS SBProgramPciDevice ( + IN PCI_DEV_INFO *PciDevice ) +{ + +//####if ((PciDevice->Address.Addr.Bus == EUSB_BUS) && \ +//#### (PciDevice->Address.Addr.Device == EUSB_DEV) && \ +//#### (PciDevice->Address.Addr.Function == EUSB_FUN)) { +//#### // Do any porting if needed. +//####} + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBUpdatePciDeviceAttributes +// +// Description: This function is called by PCI Bus Driver, can be used to +// the attributes of the PCI device. +// +// Input: *PciDevice - Pointer to PCI Device Info structure. +// *Attributes - Attributes bitmask which caller whants to +// change. +// Capabilities - The PCI device supports Capabilityes +// Set - Specifies weathere to set or reset given +// "Attributes". +// +// Output: EFI_SUCCESS +// +// Notes: This routine may be invoked twice depend on the device type, +// the first time is at BDS phase, the second is before +// legacy boot. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS SBUpdatePciDeviceAttributes ( + IN PCI_DEV_INFO *PciDevice, + IN OUT UINT64 *Attributes, + IN UINT64 Capabilities, + IN BOOLEAN Set ) +{ + +//####if ((PciDevice->Address.Addr.Bus == EUSB_BUS) && \ +//#### (PciDevice->Address.Addr.Device == EUSB_DEV) && \ +//#### (PciDevice->Address.Addr.Function == EUSB_FUN)) { +//#### // Do any porting if needed. +//####} + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ReadSPIDescriptor +// +// Description: Read SPI Descriptor. +// +// Input: FDSS - Flash Descriptor Section Select. +// FDSI - Flash Descriptor Section Index. +// FDOD - Flash Descriptor Observability Data +// +// Output:EFI_SUCCESS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS ReadSPIDescriptor( + IN UINT8 FDSS, + IN UINT8 FDSI, + OUT UINT32 *FDOD +) +{ + UINT32 Buffer32; + + WRITE_MEM32_SPI(R_RCRB_SPI_FDOC, 0); + + Buffer32 = READ_MEM32_SPI(R_RCRB_SPI_FDOD); + + if (Buffer32 != 0x0ff0a55a) //Improve alternate access mode + return EFI_NOT_FOUND; + + Buffer32 = ((UINT32)FDSS << 12) | ((UINT32)FDSI << 2); + WRITE_MEM32_SPI(R_RCRB_SPI_FDOC, Buffer32); + *FDOD = READ_MEM32_SPI(R_RCRB_SPI_FDOD); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: GetTotalFlashRomSize +// +// Description: Read SPI Descriptor to get Total Flash size. +// +// Input: None +// +// Output: UINT32 - Flash Rom Size +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT32 GetTotalFlashRomSize ( VOID ) +{ + UINT32 TotalRomSize = 0; + UINT32 CtrlData; + UINT8 NumSpi = 0; + + // Select to Flash Map 0 Register to get the number of flash Component + CtrlData = MmioRead32((SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS + R_RCRB_SPI_FDOC)); + CtrlData &= (UINT32)(~(B_PCH_SPI_FDOC_FDSS_MASK | B_PCH_SPI_FDOC_FDSI_MASK)); + CtrlData |= (UINT32)(V_PCH_SPI_FDOC_FDSS_FSDM | R_PCH_SPI_FDBAR_FLASH_MAP0); + MmioWrite32((SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS + R_RCRB_SPI_FDOC), CtrlData); + + switch ( MmioRead16 (SB_RCBA + R_PCH_SPI_FDOD) & B_PCH_SPI_FDBAR_NC ) { + case V_PCH_SPI_FDBAR_NC_1: + NumSpi = 1; + break; + case V_PCH_SPI_FDBAR_NC_2: + NumSpi = 2; + break; + default: + break; + } + //if (NumSpi == 0) ASSERT_EFI_ERROR(EFI_DEVICE_ERROR); + + // Select to Flash Components Register to get the Component 1 Density + CtrlData = MmioRead32((SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS + R_RCRB_SPI_FDOC)); + CtrlData &= (UINT32)(~(B_PCH_SPI_FDOC_FDSS_MASK | B_PCH_SPI_FDOC_FDSI_MASK)); + CtrlData |= (UINT32)(V_PCH_SPI_FDOC_FDSS_COMP | R_PCH_SPI_FCBA_FLCOMP); + MmioWrite32((SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS + R_RCRB_SPI_FDOC), CtrlData); + + /// Copy Component 1 Density + switch ( (UINT8) MmioRead32 (SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS + R_RCRB_SPI_FDOD) & B_PCH_SPI_FLCOMP_COMP1_MASK ) { + case V_PCH_SPI_FLCOMP_COMP1_512KB: + TotalRomSize += (UINT32) (512 << KBShift); + break; + case V_PCH_SPI_FLCOMP_COMP1_1MB: + TotalRomSize += (UINT32) (1 << MBShift); + break; + case V_PCH_SPI_FLCOMP_COMP1_2MB: + TotalRomSize += (UINT32) (2 << MBShift); + break; + case V_PCH_SPI_FLCOMP_COMP1_4MB: + TotalRomSize += (UINT32) (4 << MBShift); + break; + case V_PCH_SPI_FLCOMP_COMP1_8MB: + TotalRomSize += (UINT32) (8 << MBShift); + break; + case V_PCH_SPI_FLCOMP_COMP1_16MB: + TotalRomSize += (UINT32) (16 << MBShift); + break; + case V_PCH_SPI_FLCOMP_COMP1_32MB: + TotalRomSize += (UINT32) (32 << MBShift); + break; + case V_PCH_SPI_FLCOMP_COMP1_64MB: + TotalRomSize += (UINT32) (64 << MBShift); + break; + default: + break; + } // end of switch + + // Copy Component 2 Density + if(NumSpi == 2){ + switch ( (UINT8) MmioRead32 (SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS + R_RCRB_SPI_FDOD) & B_PCH_SPI_FLCOMP_COMP2_MASK ) { + case V_PCH_SPI_FLCOMP_COMP2_512KB: + TotalRomSize += (UINT32) (512 << KBShift); + break; + case V_PCH_SPI_FLCOMP_COMP2_1MB: + TotalRomSize += (UINT32) (1 << MBShift); + break; + case V_PCH_SPI_FLCOMP_COMP2_2MB: + TotalRomSize += (UINT32) (2 << MBShift); + break; + case V_PCH_SPI_FLCOMP_COMP2_4MB: + TotalRomSize += (UINT32) (4 << MBShift); + break; + case V_PCH_SPI_FLCOMP_COMP2_8MB: + TotalRomSize += (UINT32) (8 << MBShift); + break; + case V_PCH_SPI_FLCOMP_COMP2_16MB: + TotalRomSize += (UINT32) (16 << MBShift); + break; + case V_PCH_SPI_FLCOMP_COMP2_32MB: + TotalRomSize += (UINT32) (32 << MBShift); + break; + case V_PCH_SPI_FLCOMP_COMP2_64MB: + TotalRomSize += (UINT32) (64 << MBShift); + break; + default: + break; + } // end of switch + }// end of if + //if (TotalRomSize == 0) ASSERT_EFI_ERROR(EFI_DEVICE_ERROR); + + return TotalRomSize; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SbGetSpiRegionAddresses +// +// Description: Read SPI Descriptor to get flash rom base address and length +// of one region +// +// Input: AMI_SB_SPI_RANGE_TYPE - Region Type +// +// Output: UINT32 - BaseAddress +// UINT32 - EndAddress +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS SbGetSpiRangeAddresses( + IN AMI_SB_SPI_RANGE_TYPE RangeType, + OUT UINT32 *BaseAddress, + OUT UINT32 *EndAddress ) +{ + UINT32 ReadValue = 0; + + if (!((RangeType > AnyType) && (RangeType < PchSpiRangeTypeMax))) { + return EFI_INVALID_PARAMETER; + } + + if (RangeType <= SecondaryBiosType) { + ReadValue = MmioRead32 (SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS + R_SB_RCRB_SPI_FREG0_FLASHD + (S_SB_SPI_FREGX * ((UINTN) (RangeType - 1)))); + *BaseAddress = (ReadValue & B_SB_SPI_FREGX_BASE_MASK) << 12; + *EndAddress = ((ReadValue & B_SB_SPI_FREGX_LIMIT_MASK) >> 4) | 0x00000FFF; + } else if (RangeType == BfpregType) { + ReadValue = MmioRead32 (SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS + R_SB_RCRB_SPI_BFPR); + *BaseAddress = (ReadValue & B_SB_SPI_BFPR_PRB) << 12; + *EndAddress = ((ReadValue & B_SB_SPI_BFPR_PRL) >> 4) | 0x00000FFF; + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbFlashProtectedRegion +// +// Description: This routine provides H/W read/write-protection of the BIOS +// region. If chipset supports "SPI Flash Protected Range +// registers", then program them to protect BIOS region in SPI +// Flash. +// +// Input: None +// +// Output: EFI_STATUS +// EFI_SUCCESS - Set successfully. +// EFI_OUT_OF_RESOURCES - There is no available register +// for this call. +// EFI_INVALID_PARAMETER - The parameter of input is +// invalid +// EFI_UNSUPPORTED - Chipset or H/W is not supported. +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SbFlashProtectedRange( VOID ) +{ + // + // Porting required if chipset is able to support H/W protection of + // BIOS region. + // + EFI_STATUS Status = EFI_SUCCESS; + UINT32 RegIndex; + UINT32 TotalFlashRomSize; + UINT32 FlashRangeBaseAddr = 0; + UINT32 FlashRangeEndAddr = 0; + volatile UINT32 Value32, AddrCheck; + SPI_PROTECTED_RANGE_CONIFG SpiProtectedRange[] = {SPI_PROTECTED_RANGE_0, + SPI_PROTECTED_RANGE_1, + SPI_PROTECTED_RANGE_2, + SPI_PROTECTED_RANGE_3, + SPI_PROTECTED_RANGE_4}; + + // Get Total ROM size first + TotalFlashRomSize = GetTotalFlashRomSize(); + + for (RegIndex = 0; RegIndex < 5; RegIndex++) { + // Check Read or Write protected is enable or not + if (!(SpiProtectedRange[RegIndex].ReadProtectEnable || \ + SpiProtectedRange[RegIndex].WriteProtectEnable)) + continue; + + // Check Protected Range Length should not be 0 + if(SpiProtectedRange[RegIndex].ProtectedRangeLength == 0) + continue; + + switch (SpiProtectedRange[RegIndex].ProtectedRangeType){ + case BiosType: + case MeType: + case GbeType: + Status = SbGetSpiRangeAddresses(SpiProtectedRange[RegIndex].ProtectedRangeType, &FlashRangeBaseAddr, &FlashRangeEndAddr); + if(!EFI_ERROR(Status)){ + AddrCheck = (UINT32)(SpiProtectedRange[RegIndex].ProtectedRangeBase) + FlashRangeBaseAddr; + if (AddrCheck > FlashRangeEndAddr) + return EFI_INVALID_PARAMETER; + AddrCheck += (UINT32)(SpiProtectedRange[RegIndex].ProtectedRangeLength - 1); + if (AddrCheck > FlashRangeEndAddr) + return EFI_INVALID_PARAMETER; + + Value32 = *(UINT32 *)(SB_RCBA + SPI_BASE_ADDRESS + (R_SB_RCRB_SPI_PR0 + (RegIndex * 4))); + Value32 = (((UINT32)(SpiProtectedRange[RegIndex].ProtectedRangeBase) + FlashRangeBaseAddr) & 0x1FFF000) >> 12; + Value32 |= ((((UINT32)(SpiProtectedRange[RegIndex].ProtectedRangeBase + SpiProtectedRange[RegIndex].ProtectedRangeLength - 1) + FlashRangeBaseAddr) & 0x1FFF000) << 4); + } else return Status; + + break; + case AnyType: + // Exceed the address of protected range base. + if (SpiProtectedRange[RegIndex].ProtectedRangeBase >= (UINTN)TotalFlashRomSize) + return EFI_INVALID_PARAMETER; + + Value32 = *(UINT32 *)(SB_RCBA + SPI_BASE_ADDRESS + (R_SB_RCRB_SPI_PR0 + (RegIndex * 4))); + Value32 = (UINT32)(SpiProtectedRange[RegIndex].ProtectedRangeBase & 0x1FFF000) >> 12; + Value32 |= (((UINT32)(SpiProtectedRange[RegIndex].ProtectedRangeBase + SpiProtectedRange[RegIndex].ProtectedRangeLength - 1) & 0x1FFF000) << 4); + break; + } // end of switch + + if (SpiProtectedRange[RegIndex].ReadProtectEnable) Value32 |= B_SB_SPI_PRx_RPE; + if (SpiProtectedRange[RegIndex].WriteProtectEnable) Value32 |= B_SB_SPI_PRx_WPE; + *(UINT32 *)(SB_RCBA + SPI_BASE_ADDRESS + (R_SB_RCRB_SPI_PR0 + (RegIndex * 4))) = Value32; + } // for loop + + return Status; +} + +//--------------------------------------------------------------------------- +// Standard I/O Access Routines, No Porting Required. +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RtcRead +// +// Description: Read specific RTC/CMOS RAM +// +// Input: Location Point to RTC/CMOS RAM offset for read +// +// Output: nONE +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8 RtcRead ( IN UINT8 Location ) +{ + return ReadCmos(Location); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RtcWrite +// +// Description: Write specific RTC/CMOS RAM +// +// Parameters: Location Point to RTC/CMOS RAM offset for write +// Value The data that will be written to RTC/CMOS RAM +// +// Returns: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +RtcWrite ( + IN UINT8 Location, + IN UINT8 Value + ) +{ + WriteCmos(Location, Value); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ReadIo8IdxData +// +// Description: This function reads an 8bit value from a specific I/O +// Index/Data port. +// +// Input: IoBase16 - A 16 Bit I/O Address for Index I/O Port +// RegIdx8 - An 8 Bit Register offset +// +// Output: An 8Bit data read from the specific Index/Data I/O port. +// +// Notes: The default Data I/O Port is the Index I/O Port plus 1, if +// your Data I/O Port is not that, please modify below +// "++IoBase16". +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT8 ReadIo8IdxData ( + IN UINT16 IoBase16, + IN UINT8 RegIdx8 ) +{ + IoWrite8( IoBase16, RegIdx8 ); + return IoRead8( ++IoBase16 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteIo8IdxData +// +// Description: This function writes an 8bit value to a specific I/O +// Index/Data port. +// +// Input: IoBase16 - A 16 Bit I/O Address for Index I/O Port +// RegIdx8 - An 8 Bit Register Index +// Value8 - An 8 Bit Value to write. +// +// Output: None +// +// Notes: The default Data I/O Port is the Index I/O Port plus 1, if +// your Data I/O Port is not that, please modify below +// "++IoBase16". +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteIo8IdxData ( + IN UINT16 IoBase16, + IN UINT8 RegIdx8, + IN UINT8 Value8 ) +{ + IoWrite8( IoBase16, RegIdx8 ); + IoWrite8( ++IoBase16, Value8 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwIo8IdxData +// +// Description: This function reads an 8bit value from a specific I/O +// Index/Data port, then applies Set/Reset masks and writes +// it back. +// +// Input: IoBase16 - A 16 Bit I/O Address for Index I/O Port +// RegIdx8 - An 8 Bit Register Index +// SetBit8 - Mask of 8bits to set (1 = Set) +// ResetBit8 - Mask of 8bits to reset (1 = Reset) +// +// Output: None +// +// Notes: The default Data I/O Port is the Index I/O Port plus 1, if +// your Data I/O Port is not that, please modify IoRead8IdxData +// and IoWrite8IdxData's "++IoBase16". +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwIo8IdxData ( + IN UINT16 IoBase16, + IN UINT8 RegIdx8, + IN UINT8 SetBit8, + IN UINT8 ResetBit8 ) +{ + UINT8 Buffer8 ; + + Buffer8 = ReadIo8IdxData( IoBase16, RegIdx8 ) & ~ResetBit8 | SetBit8; + WriteIo8IdxData( IoBase16, RegIdx8, Buffer8 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteIo8S3 +// +// Description: This function writes an 8bit value to a specific I/O port +// and writes a copy to Boot Script Table. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// IoBaseReg16 - A 16 Bit I/O Port Address +// Value8 - An 8 Bit Value to write. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteIo8S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT16 IoBaseReg16, + IN UINT8 Value8 ) +{ + IoWrite8( IoBaseReg16, Value8 ); + + BOOT_SCRIPT_S3_IO_WRITE_MACRO( mBootScriptSave, \ + EfiBootScriptWidthUint8, \ + IoBaseReg16, \ + 1, \ + &Value8 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteIo16S3 +// +// Description: This function writes a 16bit value to a specific I/O port +// and writes a copy to Boot Script Table. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// IoBaseReg16 - A 16 Bit I/O Port Address +// Value16 - A 16 Bit Value to write. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteIo16S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT16 IoBaseReg16, + IN UINT16 Value16 ) +{ + IoWrite16( IoBaseReg16, Value16 ); + + BOOT_SCRIPT_S3_IO_WRITE_MACRO( mBootScriptSave, \ + EfiBootScriptWidthUint16,\ + IoBaseReg16, \ + 1, \ + &Value16 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteIo32S3 +// +// Description: This function writes a 32bit value to a specific I/O port +// and writes a copy to Boot Script Table. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// IoBaseReg16 - A 16 Bit I/O Port Address +// Value32 - a 32 Bit Value to write. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteIo32S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT16 IoBaseReg16, + IN UINT32 Value32 ) +{ + IoWrite32( IoBaseReg16, Value32 ); + + BOOT_SCRIPT_S3_IO_WRITE_MACRO( mBootScriptSave, \ + EfiBootScriptWidthUint32,\ + IoBaseReg16, \ + 1, \ + &Value32 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwIo8S3 +// +// Description: This function reads an 8bit value from a specific I/O port, +// then applies Set/Reset masks, and writes it back, then +// writes a copy to Boot Script Table. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// IoBaseReg16 - A 16 Bit I/O Port Address +// SetBit8 - Mask of 8bits to set (1 = Set) +// ResetBit8 - Mask of 8bits to reset (1 = Reset) +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwIo8S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT16 IoBaseReg16, + IN UINT8 SetBit8, + IN UINT8 ResetBit8 ) +{ + + RW_IO8( IoBaseReg16, SetBit8, ResetBit8 ); + + ResetBit8 = ~ResetBit8; + + BOOT_SCRIPT_S3_IO_READ_WRITE_MACRO( mBootScriptSave, \ + EfiBootScriptWidthUint8, \ + IoBaseReg16, \ + &SetBit8, \ + &ResetBit8 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwIo16S3 +// +// Description: This function reads a 16bit value from a specific I/O port, +// then applies Set/Reset masks, and writes it back, then +// writes a copy to Boot Script Table. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// IoBaseReg16 - A 16 Bit I/O Port Address +// SetBit16 - Mask of 16bits to set (1 = Set) +// ResetBit16 - Mask of 16bits to reset (1 = Reset) +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwIo16S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT16 IoBaseReg16, + IN UINT16 SetBit16, + IN UINT16 ResetBit16 ) +{ + RW_IO16( IoBaseReg16, SetBit16, ResetBit16 ); + + ResetBit16 = ~ResetBit16; + + BOOT_SCRIPT_S3_IO_READ_WRITE_MACRO( mBootScriptSave, \ + EfiBootScriptWidthUint16, \ + IoBaseReg16, \ + &SetBit16, \ + &ResetBit16 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwIo32S3 +// +// Description: This function reads a 32bit value from a specific I/O port, +// then applies Set/Reset masks, and writes it back, then +// writes a copy to Boot Script Table. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// IoBaseReg16 - A 16 Bit I/O Port Address +// SetBit32 - Mask of 32bits to set (1 = Set) +// ResetBit32 - Mask of 32bits to reset (1 = Reset) +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwIo32S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT16 IoBaseReg16, + IN UINT32 SetBit32, + IN UINT32 ResetBit32 ) +{ + RW_IO32( IoBaseReg16, SetBit32, ResetBit32 ); + + ResetBit32 = ~ResetBit32; + + BOOT_SCRIPT_S3_IO_READ_WRITE_MACRO( mBootScriptSave, \ + EfiBootScriptWidthUint32, \ + IoBaseReg16, \ + &SetBit32, \ + &ResetBit32 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteIo8IdxDataS3 +// +// Description: This function writes an 8bit value to a specific I/O +// Index/Data ports and writes a copy to Boot Script Table. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// IoBase16 - A 16 Bit I/O Address for Index I/O Port +// RegIdx8 - An 8 Bit Register Index +// Value8 - An 8 Bit Value to write. +// +// Output: None +// +// Notes: The default Data I/O Port is the Index I/O Port plus 1, if +// your Data I/O Port is not that, please modify below +// "IoBase16+1". +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteIo8IdxDataS3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT16 IoBase16, + IN UINT8 IoReg8, + IN UINT8 Value8 ) +{ + WriteIo8S3(mBootScriptSave, IoBase16, IoReg8); + WriteIo8S3(mBootScriptSave, IoBase16 + 1, Value8); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwIo8IdxDataS3 +// +// Description: This function reads an 8bit value from a specific I/O +// Index/Data ports, then applies Set/Reset masks, and writes +// it back. Also writes a copy to Boot Script Table. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// IoBase16 - A 16 Bit I/O Address for Index I/O Port +// RegIdx8 - An 8 Bit Register Index +// SetBit8 - Mask of 8bits to set (1 = Set) +// ResetBit8 - Mask of 8bits to reset (1 = Reset) +// +// Output: An 8Bit data read from the specific Index/Data I/O port +// after appling Set/Reset masks. +// +// Notes: The default Data I/O Port is the Index I/O Port plus 1, if +// your Data I/O Port is not that, please modify below +// "IoBase16+1" and IoWrite8IdxData's "++IoBase16". +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwIo8IdxDataS3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT16 IoBase16, + IN UINT8 IoReg8, + IN UINT8 SetBit8, + IN UINT8 ResetBit8 ) +{ + RwIo8IdxData(IoBase16, IoReg8, SetBit8, ResetBit8); + + BOOT_SCRIPT_S3_IO_WRITE_MACRO( mBootScriptSave, \ + EfiBootScriptWidthUint8,\ + IoBase16, \ + 1, \ + &IoReg8 ); + ResetBit8 = ~ResetBit8; + BOOT_SCRIPT_S3_IO_READ_WRITE_MACRO( mBootScriptSave, \ + EfiBootScriptWidthUint8, \ + IoBase16 + 1, \ + &SetBit8, \ + &ResetBit8 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBLib_CmosRead +// +// Description: Read the RTC value at the given Index. +// +// Input: Index - RTC Index +// +// Output: RTC Value read from the provided Index +// +// Notes: Here is the control flow of this function: +// 1. Read port 0x70 (RTC Index Register) to get bit 7. +// Bit 7 is the NMI bit-it should not be changed. +// 2. Set Index with the NMI bit setting. +// 3. Output 0x70 with the Index and NMI bit setting. +// 4. Read 0x71 for Data. Getting Dec when appropriate. +// 5. Return the Data. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT8 SBLib_CmosRead ( + IN UINT8 Index ) +{ + return ReadCmos(Index); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBLib_CmosWrite +// +// Description: Write the RTC value at the given Index. +// +// Input: Index - RTC Index +// Value - Value to write +// +// Output: None +// +// Notes: Here is the control flow of this function: +// 1. Read port 0x70 (RTC Index Register) to get bit 7. +// Bit 7 is the NMI bit-it should not be changed. +// 2. Set Index with the NMI bit setting. +// 3. Output 0x70 with the Index. Switch to BCD when needed. +// 4. Write the data to 0x71. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SBLib_CmosWrite ( + IN UINT8 Index, + IN UINT8 Value ) +{ + WriteCmos(Index, Value); +} + +PCH_SERIES +EFIAPI +GetPchSeries ( + VOID + ) +/** + + Return Pch Series + + @param[in] None + + @retval PCH_SERIES Pch Series + +**/ +{ + UINT16 LpcDeviceId; + UINT32 PchSeries; + + LpcDeviceId = READ_PCI16_SB(R_PCH_LPC_DEVICE_ID); + + if (IS_PCH_LPTH_LPC_DEVICE_ID (LpcDeviceId)) { + PchSeries = PchH; + } else if (IS_PCH_LPTLP_LPC_DEVICE_ID (LpcDeviceId)) { + PchSeries = PchLp; + } else { + PchSeries = PchUnknownSeries; + } + + return PchSeries; +} + +UINT8 +EFIAPI +GetPchMaxPciePortNum ( + VOID + ) +/** + + Get Pch Maximum Pcie Root Port Number + + @param[in] None + + @retval Pch Maximum Pcie Root Port Number + +**/ +{ + PCH_SERIES PchSeries; + + PchSeries = GetPchSeries(); + switch (PchSeries) { + case PchLp: + return LPTLP_PCIE_MAX_ROOT_PORTS; + + case PchH: + return LPTH_PCIE_MAX_ROOT_PORTS; + + default: + return 0; + } +} + +UINT8 +EFIAPI +GetPchMaxSataPortNum ( + VOID + ) +/** + + Get Pch Maximum Sata Port Number + + @param[in] None + + @retval Pch Maximum Sata Port Number + +**/ +{ + PCH_SERIES PchSeries; + + PchSeries = GetPchSeries(); + switch (PchSeries) { + case PchLp: + return LPTLP_AHCI_MAX_PORTS; + + case PchH: + return LPTH_AHCI_MAX_PORTS; + + default: + return 0; + } +} + +UINT8 +EFIAPI +GetPchUsbMaxPhysicalPortNum ( + VOID + ) +/** + + Get Pch Usb Maximum Physical Port Number + + @param[in] None + + @retval Pch Usb Maximum Physical Port Number + +**/ +{ + PCH_SERIES PchSeries; + + PchSeries = GetPchSeries(); + switch (PchSeries) { + case PchLp: + return LPTLP_USB_MAX_PHYSICAL_PORTS; + + case PchH: + return LPTH_USB_MAX_PHYSICAL_PORTS; + + default: + return 0; + } +} + +UINT8 +EFIAPI +GetPchXhciMaxUsb3PortNum ( + VOID + ) +/** + + Get Pch Maximum Usb3 Port Number of XHCI Controller + + @param[in] None + + @retval Pch Maximum Usb3 Port Number of XHCI Controller + +**/ +{ + PCH_SERIES PchSeries; + + PchSeries = GetPchSeries(); + switch (PchSeries) { + case PchLp: + return LPTLP_XHCI_MAX_USB3_PORTS; + + case PchH: + return LPTH_XHCI_MAX_USB3_PORTS; + + default: + return 0; + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetPchEhciMaxControllerNum +// +// Description: Get Pch Maximum EHCI Controller Number +// +// Input: None +// +// Output: Pch Maximum EHCI Controller Number +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8 +EFIAPI +GetPchEhciMaxControllerNum ( + VOID + ) +{ + PCH_SERIES PchSeries; + + PchSeries = GetPchSeries(); + switch (PchSeries) { + case PchLp: + return LPTLP_EHCI_MAX_CONTROLLERS; + + case PchH: + return LPTH_EHCI_MAX_CONTROLLERS; + + default: + return 0; + } +} + +UINT32 DummyVerbTable[] = { + // + // Dummy Verb Table + // + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF +}; + +#if defined(HPET_APIC_INTERRUPT_MODE) && (HPET_APIC_INTERRUPT_MODE != 0) +//---------------------------------------------------------------------------- +// Generic IO APIC routine. +//---------------------------------------------------------------------------- +UINT8 gBspLocalApicID = 0; +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IoApicBase +// +// Description: This routine returns a structure pointer to the I/O APIC. +// +// Input: None +// +// Output: IO_APIC structure. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +struct IO_APIC* IoApicBase( VOID ) +{ + static UINT32 IoApicAddr = 0; + if (IoApicAddr == 0 || IoApicAddr == -1) { + // This value may need to read from chipset registers. + IoApicAddr = APCB; + } + + return (struct IO_APIC*)IoApicAddr; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IoApicWrite +// +// Description: This function writes a 32bits data to the register of +// I/O APIC. +// +// Input: UINT8 Reg - The register offset to be written. +// UINT32 Value - A 32bits data will be written to the register +// of I/O APIC. +// +// Output: EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS IoApicWrite ( + IN UINT8 Reg, + IN UINT32 Value ) +{ + struct IO_APIC *IoApicStruct = IoApicBase(); + + MMIO_WRITE8((UINT64)&IoApicStruct->Index, Reg); + MMIO_WRITE32((UINT64)&IoApicStruct->Data, Value); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IoApicRead +// +// Description: This function reads a 32bits data from the register of +// I/O APIC. +// +// Input: UINT8 Reg - the register offset to be read. +// +// Output: UINT32 - A 32bits data read from the register of I/O APIC. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT32 IoApicRead ( + IN UINT8 Reg ) +{ + struct IO_APIC *IoApicStruct = IoApicBase(); + + MMIO_WRITE8((UINT64)&IoApicStruct->Index, Reg); + return MMIO_READ32((UINT64)&IoApicStruct->Data); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IoApicEnableIrq +// +// Description: This function enables the specific interrupt pin of I/O APIC. +// +// Input: UINT8 Irq - The pin number of I/O APIC +// BOOLEAN LevelTriggered - Trigger mechanism (level or edge) +// for this INT pin. +// BOOLEAN Polarity - Specifies the polarity of the INT pin. +// (Active High or Active Low) +// Output: EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS IoApicEnableIrq ( + IN UINT8 Irq, + IN BOOLEAN LevelTriggered, + IN BOOLEAN Polarity ) +{ + IO_APIC_ROUTE_ENTRY ApicEntry; + union ENTRY_UNION Eu = {{0, 0}}; + + ApicEntry.DestMode = 0; // 0: physical + ApicEntry.Mask = 0; // 0 : enable + ApicEntry.Dest = gBspLocalApicID; // suppose the BSP handle interrupt. + ApicEntry.DeliveryMode = 0; // 000: FIXED + ApicEntry.Polarity = (Polarity) ? 1 : 0; + ApicEntry.Trigger = (LevelTriggered) ? 1 : 0; + ApicEntry.Vector = MASTER_INTERRUPT_BASE + Irq; + + Eu.Entry = ApicEntry; + IoApicWrite(IO_APIC_REDIR_TABLE_HIGH + 2 * Irq, Eu.W2); + IoApicWrite(IO_APIC_REDIR_TABLE_LOW + 2 * Irq, Eu.W1); + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IoApicDisableIrq +// +// Description: This function disables the specific interrupt pin of I/O APIC. +// +// Input: UINT8 Irq - The pin number of I/O APIC +// +// Output: EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS IoApicDisableIrq ( + IN UINT8 Irq ) +{ + union ENTRY_UNION Eu = {{0, 0}}; + + Eu.W1 = IoApicRead(IO_APIC_REDIR_TABLE_LOW + 2 * Irq); + Eu.W2 = IoApicRead(IO_APIC_REDIR_TABLE_HIGH + 2 * Irq); + Eu.Entry.Mask = 1; + IoApicWrite(IO_APIC_REDIR_TABLE_LOW + 2 * Irq, Eu.W1); + IoApicWrite(IO_APIC_REDIR_TABLE_HIGH + 2 * Irq, Eu.W2); + IoApicEoi(Irq); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IoApicMaskIrq +// +// Description: This routine masks the specific interrupt pin of I/O APIC. +// +// Input: UINT8 Irq - The pin number of I/O APIC +// +// Output: EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS IoApicMaskIrq ( + IN UINT8 Irq ) +{ + union ENTRY_UNION Eu = {{0, 0}}; + + Eu.W1 = IoApicRead(IO_APIC_REDIR_TABLE_LOW + 2 * Irq); + Eu.Entry.Mask = 1; + IoApicWrite(IO_APIC_REDIR_TABLE_LOW + 2 * Irq, Eu.W1); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IoApicUnmaskIrq +// +// Description: This routine unmasks the specific interrupt pin of I/O APIC. +// +// Input: UINT8 Irq - The pin number of I/O APIC +// +// Output: EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS IoApicUnmaskIrq ( + IN UINT8 Irq ) +{ + union ENTRY_UNION Eu = {{0, 0}}; + + Eu.W1 = IoApicRead(IO_APIC_REDIR_TABLE_LOW + 2 * Irq); + Eu.Entry.Mask = 0; + IoApicWrite(IO_APIC_REDIR_TABLE_LOW + 2 * Irq, Eu.W1); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IoApicEoi +// +// Description: This routine issues an EOI to the specific pin of I/O APIC. +// +// Input: UINT8 Irq - The pin number of I/O APIC +// +// Output: EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS IoApicEoi ( + IN UINT8 Irq ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINT32 Vector = MASTER_INTERRUPT_BASE + Irq; + struct IO_APIC *IoApicStruct = IoApicBase(); + UINT32 Isr = 0; + union ENTRY_UNION Eu = {{0, 0}}; + + do { + MMIO_WRITE32((UINT64)&IoApicStruct->Eoi, Vector); + Eu.W1 = IoApicRead(IO_APIC_REDIR_TABLE_LOW + 2 * Irq); + } while (Eu.Entry.Irr); + + do { + MMIO_WRITE32(LOCAL_APIC_BASE + APIC_EOI_REGISTER, Vector); + Isr = MMIO_READ32(LOCAL_APIC_BASE + ISR_REG (Vector)); + } while (Isr & ISR_BIT(Vector)); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetHpetApicPin +// +// Description: This routine gets the pin number of I/O APIC for HPET. +// +// Input: None +// +// Output: UINT8 Irq - The pin number of I/O APIC for HPET. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT8 GetHpetApicPin (VOID) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINT8 Irq = 0; + + volatile HPET_TIMER_CONFIGURATION_REGISTER TimerConfiguration; + + TimerConfiguration.Uint64 = MMIO_READ64( HPET_BASE_ADDRESS + HPET_TIMER_CONFIGURATION_OFFSET + HPET_OFFSET * HPET_TIMER_STRIDE ); + Irq = TimerConfiguration.Bits.InterruptRoute; + + return Irq; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IsHpetApicEnable +// +// Description: This routine checks the pin of I/O APIC for HPET is enabled or +// not. +// +// Input: None +// +// Output: TRUE - The pin of I/O APIC for HPET is enabled +// FALSE - The pin of I/O APIC for HPET is disabled +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN IsHpetApicEnable (VOID) +{ + union ENTRY_UNION Eu = {{0, 0}}; + UINT8 Irq; + + Irq = GetHpetApicPin(); + + Eu.W1 = IoApicRead(IO_APIC_REDIR_TABLE_LOW + 2 * Irq); + + return (Eu.Entry.Mask) ? FALSE : TRUE; +} +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/SBPEI.c b/Chipset/SB/SBPEI.c new file mode 100644 index 0000000..918f226 --- /dev/null +++ b/Chipset/SB/SBPEI.c @@ -0,0 +1,3430 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SBPEI.c 57 5/27/15 2:26a Dennisliu $ +// +// $Revision: 57 $ +// +// $Date: 5/27/15 2:26a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SBPEI.c $ +// +// 57 5/27/15 2:26a Dennisliu +// [TAG] EIP219399 +// [Category] Improvement +// [Description] Static code analysis issue found in Aptio4 Intel +// LynxPoint PCH module +// [Files] Chipset\SB\SBPEI.c +// +// 56 11/17/14 7:24a Mirayang +// [TAG] EIP190402 +// [Category] New Feature +// [Description] Support BootScriptHide eModule on Sharkbay CRB project +// +// 55 9/23/14 6:12a Mirayang +// [TAG] EIP183246 +// [Category] Bug Fix +// [Severity] Important +// [Symptom] BIOS capsule update usb issue +// [RootCause] Boot mode conditions miss "BOOT_ON_FLASH_UPDATE" in +// InitUsbMisc(). +// [Solution] Add "BOOT_ON_FLASH_UPDATE" this boot mode conditions . +// +// 54 7/21/14 10:42p Mirayang +// [TAG] EIP176923 +// [Category] Improvement +// [Description] Program BUC.SDO to 1 on normal boot in PCH component. +// +// 53 4/01/14 10:18p Barretlin +// [TAG] EIP156783 +// [Category] Improvement +// [Description] fix build error when removing usb recovery module +// [Files] SbPei.c +// +// 52 1/14/14 1:37a Barretlin +// [TAG] EIP150529 +// [Category] Improvement +// [Description] System hang due to dysfunctional MRC delay routine +// [Files] SBPei.c +// +// 51 1/08/14 11:18p Barretlin +// [TAG] EIP149596 +// [Category] Improvement +// [Description] system cannot enter to recovery mode when CMOS is bad +// [Files] SBPEI.c +// +// 50 10/29/13 12:38a Barretlin +// [TAG] EIP136997 +// [Category] Improvement +// [Description] fix build error when SUPPORT_RAID_DRIVER token is 0 +// [Files] SBPei.c +// +// 49 10/06/13 2:31a Barretlin +// [TAG] EIP138340 +// [Category] Improvement +// [Description] SATA drive detection issue in PCH Platform BIOS +// reference code revision 1.6.2 +// [Files] SB.sdl SBPEI.c +// +// 48 9/17/13 2:48p Barretlin +// [TAG] EIP N/A +// [Category] Improvement +// [Description] use token to decide SATA RxEq policy vaule +// [Files] SB.sdl SBPei.c +// +// 47 9/17/13 8:43a Barretlin +// [TAG] EIP136354 +// [Category] Improvement +// [Description] remove setting RCBA Coprocessor Error Enable bit +// [Files] SB.sdl SbPei.c +// +// 46 8/23/13 4:34a Barretlin +// [TAG] EIP133819 +// [Category] Improvement +// [Description] change platform policy revision to 4 +// [Files] SBPEI.c +// +// 45 8/23/13 3:42a Barretlin +// [TAG] EIP133819 +// [Category] Improvement +// [Description] update for Intel PCH RC 1.6.2.0 +// [Files] SB.sdl SBPEI.c +// +// 44 7/17/13 8:01a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Let's GPIO GPINDIS bit setting by custom define except +// GPO. +// [Files] SBPEI.c +// +// 43 5/23/13 1:56a Scottyang +// [TAG] EIP120623 +// [Category] Improvement +// [Description] LCD turn on automatically when resume from S3. +// [Files] SBPEI.c, SBDxe.c, AcpiModeEnable.c +// +// 42 5/13/13 9:14a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Set time to default when clear cmos by jumper or +// remove battery. +// [Files] SBPEI.c +// +// 40 5/08/13 4:37a Scottyang +// [TAG] EIP123117 +// [Category] Improvement +// [Description] Fixed enable USB precondition, and do power off, power +// on, it will hang 9C. +// [Files] SBPEI.c +// +// 39 5/08/13 3:09a Scottyang +// [TAG] None +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] Enable bit set at wrong place. +// [RootCause] The offset error. +// [Solution] Make offset correct. +// [Files] SBPEI.c +// +// 37 5/03/13 1:42a Scottyang +// [TAG] EIP115528 +// [Category] Improvement +// [Description] Support XHCI port recovery when reset after boot to OS +// with XHCI driver. +// [Files] SBPEI.c +// +// 36 4/24/13 6:42a Scottyang +// [TAG] EIP114861 +// [Category] Improvement +// [Description] For PTT(Fast boot) 15 can reduce post for CD-ROM. +// [Files] SBPEI.c +// +// 35 4/24/13 4:20a Scottyang +// [TAG] EIP118667 +// [Category] Improvement +// [Description] For ULT when GPIO is GPO will also set GPI_DIS_DISABLE. +// [Files] SBPEI.c +// +// 34 4/24/13 2:15a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Porting GPI interrupt by LPT-LP EDS 1.5. +// [Files] SB.sdl, SB.H, SBPPI.h, SBPEI.c +// +// 33 4/23/13 4:51a Wesleychen +// [TAG] None +// [Category] Improvement +// [Description] Add token "ONLY_CLEAR_RTC_EN_IN_PEI" for improve +// "EIP120623". +// [Files] AcpiModeEnable.c; SB.SDL; SBPEI.c +// +// 31 4/18/13 12:18a Wesleychen +// [TAG] EIP120623 +// [Category] Bug Fix +// [Severity] Important +// [Symptom] LCD doesn't turn on automatically when resume from S3. +// [RootCause] PM1_STS (PMBASE+00h) are cleared in EnableAcpiMode(). +// [Solution] Avoid PM1_STS clearing behavior is occurring in S3 +// resuming. +// *AcpiModeEnable.c Rev#8~11(EIP101628 & EIP118531) are are +// no need be existence. +// [Files] SBPEI.c; AcpiModeEnable.c +// +// 29 3/15/13 3:33a Scottyang +// [TAG] EIP118121 +// [Category] Improvement +// [Description] Update PCH RC 1.3.0. +// [Files] ..\ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, +// SB.sd, SB.uni, GetSetupData.c, SbSetupData.h +// +// 28 3/12/13 7:40a Scottyang +// [TAG] EIP115528 +// [Category] Improvement +// [Description] USB ports are connected to EHCI not XHCI When recovery. +// [Files] SBPEI.c +// +// 27 2/26/13 1:02a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Follow intel BIOS V112 to change IRQ rout. +// [Files] SB.sdl, SBPEI.c +// +// 26 2/09/13 12:12a Scottyang +// [TAG] EIP114922 +// [Category] Improvement +// [Description] Update PCH RC 1.1.0. +// [Files] ..\ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, +// SB.sd, SB.uni, GetSetupData.c, SbSetupDara.h +// +// 25 1/31/13 10:51a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add delay for HDD recovery. +// [Files] SBPEI.c +// +// 24 1/30/13 1:15a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Fix build error at 4653. +// [Files] SBPEI.c +// +// 23 1/27/13 11:01p Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Capsule 2.0 crash dump link function. +// [Files] SBPEI.c +// SBDxe.c +// SBRun.c +// +// 22 1/11/13 1:51a Scottyang +// [TAG] EIP88358 +// [Category] Improvement +// [Description] Add FORCE_USER_TO_SETUP_IF_CMOS_BAD token +// [Files] SBDex.c, SBPei.c, RTC.h, SB.sdl +// +// 21 12/24/12 5:51a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add option for XHCI Idel L1 workaroung. +// [Files] GetSetupData.c, SbSetupData.h, SB.sd, SB.uni, SBDxe.c, +// SBPEI.c +// +// 20 12/18/12 6:10a Scottyang +// [TAG] EIP109697 +// [Category] Improvement +// [Description] Update PCH RC 0.8.1 +// [Files] ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, SB.sd, +// SbSetupData.c, GetSetupDate.c +// +// 19 12/13/12 10:31a Scottyang +// [TAG] EIP106687 +// [Category] Improvement +// [Description] Add option for delay to detect PCIE card. +// [Files] SBPEI.c, SB.sd, SB.uni, GetSetupData.c, SbSetupData.h, +// PciBus.c +// +// 18 12/13/12 10:17a Scottyang +// [TAG] EIP107424 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] System stops at CKP 0x9C when system performs a cool boot +// and AMI debugger is enabled. +// [RootCause] Unexpected USB EHCI Legacy Support Extended status is +// rised, it is out of USB module control. +// [Solution] Clear unexpected USB EHCI Legacy Support Extended +// status. +// [Files] SBPEI.c +// +// 17 11/20/12 9:47a Scottyang +// [TAG] EIP107014 +// [Category] Improvement +// [Description] Update RC 0.8.0 +// [Files] ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, +// SB.sd, SbSetupData.c, GetSetupDate.c +// +// 16 11/06/12 8:12a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Reduce function "GetPchSeries()". +// [Files] SBPEI.c, SBDxe.c, SmiHandlerPorting.c, SmiHandlerPorting2.c +// +// 15 10/25/12 8:16a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add new device and remove device which no use +// [Files] SBPEI.c, SB.sdl +// +// 14 10/16/12 4:16a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Assign IRQ for device 21 +// +// 13 10/14/12 8:33a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] One rom for two chip and one chip. +// [Files] SPPEIBoard.c, SB.sd, SBDxe.c, SBPEI.c, PCH.asl +// +// 12 10/12/12 4:55a Scottyang +// [TAG] EIP87695 +// [Category] Improvement +// [Description] System should reboot successfully next time if S3 +// resume fail +// [Files] SB.sdl, SBPei.c +// +// 11 10/11/12 11:15p Scottyang +// [TAG] EIP86096 +// [Category] Improvement +// [Description] Fix SATA AHCI port4 & 5 can't loading recovery image. +// [Files] SBPei.c +// +// 10 9/26/12 3:55a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update for Intel PCH LPT RC070. +// [Files] SB.sdl, SBDXE.c, SBPEI.c, Pch.sdl, SB.sd, SB.uni +// +// [TAG] None +// [Category] Improvement +// [Description] Update for PCH LP GPIO compatible. +// [Files] SB.sdl, SB.H, AcpiModeEnable.c, AcpiModeEnable.sdl, +// SBDxe.c, SBGeneric.c, SBPEI.c, SBSMI.c, SleepSmi.c, +// SmiHandlerPorting.c, SmiHandlerPorting2.c +// +// 9 9/12/12 5:20a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Force HPET enabled for MRC initialization. +// [Files] SB.sd, SBPEI.c +// +// [TAG] None +// [Category] Improvement +// [Description] Modify for ULT GPIO changed by PCH LPT-LP EDS 1.0. +// [Files] SB.H, SB.sdl, AcpiModeEnable.c, AcpiModeEnable.sdl, +// SBPEI.c +// +// 8 8/24/12 6:51a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Sync USB policy for UsbPrecondition function. +// [Files] SBPEI.c +// +// 7 8/14/12 11:26p Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update "SB_TEMP_MMIO_BASE" and +// "EHCI_MMIO_BASE_ADDRESS". +// [Files] SB.sdl, SBDxe.c, SBPEI.c +// +// 6 8/13/12 10:29a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update correct MMIO BASE for TempMemBaseAddr policy. +// [Files] SBPEI.c +// +// [TAG] None +// [Category] Improvement +// [Description] Update PCH Policy. +// [Files] SB.sdl, SBDxe.c, SBPEI.c +// +// [TAG] None +// [Category] Improvement +// [Description] Implement USB Precondition option for policy +// "UsbPrecondition". +// [Files] GetSetupData.c, SB.sd, SB.uni, SbSetupData.h, SBDxe.c, +// SBPEI.c +// +// 5 7/27/12 6:14a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update setup items and policies. +// [Files] GetSetupData.c, SB.sdl, SB.sd, SB.uni, SbSetupData.h, +// SBPEI.c, SBDXE.c +// +// [TAG] None +// [Category] Improvement +// [Description] Update to support ULT Platform. +// [Files] SB.H, SB.mak, SB.sdl, SB.sd, SBSetup.c, +// AcpiModeEnable.c, SBDxe.c, SBPEI.c, SBSMI.c, SleepSmi.c, +// SmiHandlerPorting.c, SmiHandlerPorting2.c, SBPPI.h, Pch.sdl +// +// 4 7/02/12 10:17a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Updated and modified for PCH RC 0.6.0. +// [Files] SBGeneric.c, SB.sdl, SBCspLib.h, SBDxe.c, SBPEI.c +// +// 3 6/13/12 11:34p Victortu +// [TAG] None +// [Category] Improvement +// [Description] Implement Warm Boot function for Secure Flash feature. +// [Files] SB.H, SB.mak, SB.sdl, SBDxe.c, SBGeneric.c, SBPEI.c, +// SBSMI.c +// +// 2 2/24/12 2:35a Victortu +// Support RapidStart_SUPPORT. +// +// 1 2/08/12 8:24a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SBPEI.C +// +// Description: This file contains code for South Bridge initialization +// in the PEI stage +// +//<AMI_FHDR_END> +//************************************************************************* + +//---------------------------------------------------------------------------- +// Include(s) +//---------------------------------------------------------------------------- + +#include <Efi.h> +#include <Pei.h> +#include <Token.h> +#include <AmiPeiLib.h> +#include <Hob.h> +#include <Setup.h> +#include <AmiCspLib.h> +// Produced/used PPI interfaces +#include <ppi\PciCfg2.h> +#include <ppi\SBPPI.h> +#include <ppi\CpuIo.h> +#include <ppi\CspLibPpi.h> +#include <RTC.h> +#include <PchAccess.h> +#include <Ppi\PchUsbPolicy\PchUsbPolicy.h> +#include <Ppi\PchInit\PchInit.h> + +#include <Ppi\SmbusPolicy\SmbusPolicy.h> +#include <Ppi\PchPlatformPolicy\PchPlatformPolicy.h> + +#if defined iME_SUPPORT && iME_SUPPORT +#include <Guid\MeBiosExtensionSetup\MeBiosExtensionSetup.h> +#endif + +#if SB_RESET_PPI_SUPPORT +#include <Ppi\Reset.h> +#endif + +#if ATAPI_RECOVERY_SUPPORT +#include <Ppi\AtaController.h> +#endif + +#if SB_STALL_PPI_SUPPORT +#include <Ppi\Stall.h> +#endif + +#if WdtPei_SUPPORT +#include "ppi\Wdt\Wdt.h" +#endif +#include <ppi\NBPPI.h> + +#if Capsule2_0_SUPPORT +#include <ppi\capsule.h> //CAPSULE20 +#endif + +#if defined(SUPPORT_RAID_DRIVER) && SUPPORT_RAID_DRIVER && (PTT_VER > 15) +#include <FastBoot.h> + +#define SATA1_BDF (0x1f << 3 | 0x02) +#define SATA2_BDF (0x1f << 3 | 0x05) +#endif +//---------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//---------------------------------------------------------------------------- +// Constant Definition(s) +#define EHCI_MEMORY_SPACE 0x400 +#define TIMER_RESOLUTION 1 +#define S3_SLP_TYP 0x05 + +#ifndef SMM_SUPPORT + #define SMM_SUPPORT 0 +#endif + +#define RETRAIN_DELAY 50 // [EIP106687] + +// Macro Definition(s) + +// Type Definition(s) +#if defined iME_SUPPORT && iME_SUPPORT +// TS on DIMM defines +#define TS_ON_CHANNEL0_SLOT_0_DIMM 0x1 +#define TS_ON_CHANNEL1_SLOT_0_DIMM 0x2 +#define TS_ON_C0_S0_AND_C1_S0_DIMM 0x3 +#endif + +#ifndef CAPSULE_SUPPORT + +#if defined Capsule2_0_SUPPORT && Capsule2_0_SUPPORT +#define CAPSULE_SUPPORT 1 +#else +#define CAPSULE_SUPPORT 0 +#endif + +#endif + +typedef struct _SATA_LENGTH_CONFIG { + UINT8 SataGen1RxEqEnable; + UINT8 SataGen1RxEqValue; + UINT8 SataGen2RxEqEnable; + UINT8 SataGen2RxEqValue; + UINT8 SataGen3RxEqEnable; + UINT8 SataGen3RxEqValue; +} SATA_LENGTH_CONFIG; +// Function Prototype(s) + +BOOLEAN IsRecovery ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg, + IN EFI_PEI_CPU_IO_PPI *CpuIo +); + +#if SB_RESET_PPI_SUPPORT +EFI_STATUS SBPEI_ResetSystem ( + IN EFI_PEI_SERVICES **PeiServices +); +#endif + +#if SB_STALL_PPI_SUPPORT +EFI_STATUS SBPEI_Stall ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_STALL_PPI *This, + IN UINTN Microseconds +); +#endif + +#if ATAPI_RECOVERY_SUPPORT +EFI_STATUS EFIAPI EnableAtaChannel ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_ATA_CONTROLLER_PPI *This, + IN UINT8 ChannelIndex +); +#endif + +BOOLEAN IsS3 ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo +); + +VOID ProgramGPIO ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo, + IN SB_SETUP_DATA *SbSetupData, + IN AMI_GPIO_INIT_TABLE_STRUCT *pTable +); + +VOID ProgramSBSubId( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg, + IN AMI_PEI_SB_CUSTOM_PPI *SBPeiOemPpi +); + +VOID InitPCIe ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg +); + +VOID InitSMBus ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg +); + +VOID InitUsbMisc ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg, + IN EFI_BOOT_MODE BootMode +); + +EFI_STATUS UpdateBootMode ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg +); + +EFI_STATUS ProgramSBRegAfterMemInstalled ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *InvokePpi +); + +EFI_STATUS ProgramSBRegBeforeEndofPei ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *InvokePpi +); + +EFI_STATUS ProgramSBRegAfterMrc ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *InvokePpi +); + +EFI_STATUS ProgramSBRegEndOfMrc ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *InvokePpi +); + +VOID InitPMRegs( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo, + IN SB_SETUP_DATA *SbSetupData +); + +VOID InitRTC( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo +); + +VOID WriteSBDefaultSubId ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg +); + +VOID ProgramRCRBMmio ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo +); + +EFI_STATUS +ProgramSBIoDecodeRegs ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg +); + +EFI_STATUS +ProgramPchDeviceBase ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg +); + +EFI_STATUS +GeneralPowerFailureHandler ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg +); + +EFI_STATUS +SetTheStateToGoAfterG3 ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg, + IN SB_SETUP_DATA *SbSetupData +); + +EFI_STATUS InstallPchPlatformPolicyPpi ( + IN EFI_PEI_SERVICES **PeiServices, + IN SB_SETUP_DATA *SbSetupData +); + +EFI_STATUS +InstallAmtPlatformPolicyPpi ( + IN EFI_PEI_SERVICES **PeiServices, + IN SB_SETUP_DATA *SbSetupData +); + +EFI_STATUS +CreateAmtForcePushPetPolicyHob( + IN EFI_PEI_SERVICES **PeiServices +); + +//---------------------------------------------------------------------------- +// Variable and External Declaration(s) +//---------------------------------------------------------------------------- +// Variable Declaration(s) + +// GUID Definition(s) +EFI_GUID gAmiPEISBInitPolicyGuid = AMI_PEI_SBINIT_POLICY_PPI_GUID; +EFI_GUID gAmiPEIPCITableInitPpiGuid = AMI_PEI_PCI_TABLE_INIT_PPI_GUID; +EFI_GUID gMasterBootModeGuid = EFI_PEI_MASTER_BOOT_MODE_PEIM_PPI; +EFI_GUID gRecoveryBootModeGuid = EFI_PEI_BOOT_IN_RECOVERY_MODE_PEIM_PPI; +EFI_GUID gEfiPeiPermMemInstalledGuid = EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI; +EFI_GUID gEfiPeiEndOfPeiPhasePpiGuid = EFI_PEI_END_OF_PEI_PHASE_PPI_GUID; +EFI_GUID gPeiSmbusPolicyPpiGuid = PEI_SMBUS_POLICY_PPI_GUID; +EFI_GUID gPchPlatformPolicyPpiGuid = PCH_PLATFORM_POLICY_PPI_GUID; +EFI_GUID gSetupGuid = SETUP_GUID; +EFI_GUID gPchUsbPolicyPpiGuid = PCH_USB_POLICY_PPI_GUID; +EFI_GUID gPchInitPpiGuid = PCH_INIT_PPI_GUID; + +EFI_GUID gPeiCompleteMRCGuid = AMI_PEI_AFTER_MRC_GUID; + +#if SB_STALL_PPI_SUPPORT +EFI_GUID gStallPpiGuid = EFI_PEI_STALL_PPI_GUID; +#endif + +#if SB_RESET_PPI_SUPPORT +EFI_GUID gPeiResetPpiGuid = EFI_PEI_RESET_PPI_GUID; +#endif + +#if ATAPI_RECOVERY_SUPPORT +EFI_GUID gPeiAtaControllerPpiGuid = PEI_ATA_CONTROLLER_PPI_GUID; +#endif + +#if WdtPei_SUPPORT +EFI_GUID gWdtPpiGuid = WDT_PPI_GUID; +#endif + +EFI_GUID gOemPchPlatformPolicyOverridePpiGuid = AMI_PEI_SB_OEM_PLATFORM_POLICY_OVERRIDE_PPI_GUID; + +// PPI Definition(s) + +static AMI_PEI_SBINIT_POLICY_PPI mAMIPEISBInitPolicyPpi = { + TRUE +}; + +#if ATAPI_RECOVERY_SUPPORT +static PEI_ATA_CONTROLLER_PPI mAtaControllerPpi = { + EnableAtaChannel +}; +#endif + +#if SB_STALL_PPI_SUPPORT +static EFI_PEI_STALL_PPI mStallPpi = { + TIMER_RESOLUTION, + SBPEI_Stall +}; +#endif + +#if SB_RESET_PPI_SUPPORT +static EFI_PEI_RESET_PPI mResetPpi = { + SBPEI_ResetSystem +}; +#endif + +// PPI that are installed + +#if SB_STALL_PPI_SUPPORT +static EFI_PEI_PPI_DESCRIPTOR mBeforeBootModePpiList[] = { + { EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, \ + &gStallPpiGuid, &mStallPpi }, +}; +#endif + +static EFI_PEI_PPI_DESCRIPTOR mBootModePpi[] = { + { EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, \ + &gMasterBootModeGuid, NULL }, +}; + +static EFI_PEI_PPI_DESCRIPTOR mRecoveryModePpi[] = { + { EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, \ + &gRecoveryBootModeGuid, NULL }, +}; + +static EFI_PEI_PPI_DESCRIPTOR mPpiList[] = { +#if ATAPI_RECOVERY_SUPPORT + { EFI_PEI_PPI_DESCRIPTOR_PPI, \ + &gPeiAtaControllerPpiGuid, &mAtaControllerPpi }, +#endif +#if SB_RESET_PPI_SUPPORT + { EFI_PEI_PPI_DESCRIPTOR_PPI, &gPeiResetPpiGuid, &mResetPpi }, +#endif + { EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, \ + &gAmiPEISBInitPolicyGuid, &mAMIPEISBInitPolicyPpi } +}; + +// PPI that are notified + +static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = { + { EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | \ + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, \ + &gEfiPeiEndOfPeiPhasePpiGuid, ProgramSBRegBeforeEndofPei }, +}; + +static EFI_PEI_NOTIFY_DESCRIPTOR mMemoryReadyNotify[] = { + { EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | \ + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gEfiPeiPermMemInstalledGuid, ProgramSBRegAfterMemInstalled } +}; + +static EFI_PEI_NOTIFY_DESCRIPTOR AfterMrcNotifyList[] = { + { EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | \ + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, \ + &gAmiPeiAfterMrcGuid, ProgramSBRegAfterMrc }, +}; +static EFI_PEI_NOTIFY_DESCRIPTOR EndOfMrcNotifyList[] = { + { EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | \ + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, \ + &gAmiPeiEndOfMemDetectGuid, ProgramSBRegEndOfMrc }, +}; + +static EFI_PEI_PPI_DESCRIPTOR StallPpiDescriptor_InMemory[] = +{ + { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gStallPpiGuid, + &mStallPpi + } +}; + +// External Declaration(s) + +extern AMI_GPIO_INIT_TABLE_STRUCT stSB_GPIODefaultInitTable[]; +extern AMI_GPIO_INIT_TABLE_STRUCT stSB_GPIODefaultULTInitTable[]; + +extern EFI_STATUS CountTime ( + IN UINTN DelayTime, + IN UINT16 BaseAddr +); + +#if SB_RESET_PPI_SUPPORT +extern VOID SBLib_ResetSystem ( + IN EFI_RESET_TYPE ResetType +); +#endif + +// Function Definition(s) + +#ifdef RAPID_START_FLAG + +#define RAPID_START_FLAG_ENTRY_DONE BIT0 + +EFI_STATUS +RapidStartGetFlag ( + OUT UINT8 *Value + ) +{ + *Value = RtcRead (FFS_NV_FLAG_REG); + return EFI_SUCCESS; +} + +BOOLEAN +RapidStartResumeCheck ( + VOID +) +{ + EFI_STATUS Status; + BOOLEAN RapidStartFlag; + + Status = RapidStartGetFlag (&RapidStartFlag); + if ( !EFI_ERROR (Status) && ((RapidStartFlag & RAPID_START_FLAG_ENTRY_DONE) != 0)) { + return TRUE; + } + + return FALSE; +} +#endif + +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IsS3 +// +// Description: This function determines if the system is resuming from an S3 +// sleep state. +// +// Input: PeiServices - Pointer to the Pei Services function and data +// structure. +// +// Output: TRUE - It is an S3 Resume +// FALSE - It is not an S3 Resume +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN IsS3 ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo ) +{ + // Check PWR_FLR Bit + if ((READ_PCI8_SB(R_PCH_LPC_GEN_PMCON_3) & B_PCH_LPC_GEN_PMCON_PWR_FLR) == 0) // 0xA4 + // Check PWRBTN override + if ((READ_IO16_PM(R_PCH_ACPI_PM1_STS) & B_PCH_ACPI_PM1_STS_PRBTNOR) == 0) // 0x00 + // Check WAK_STS bit + if ((READ_IO16_PM(R_PCH_ACPI_PM1_STS) & B_PCH_ACPI_PM1_STS_WAK)) // 0x00 + // Check the sleep type + if ((READ_IO16_PM(R_PCH_ACPI_PM1_CNT) & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S3) //0x04 + return TRUE; + + return FALSE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IsS4 +// +// Description: This function determines if the system is resuming from an S4 +// sleep state. +// +// Input: PeiServices - Pointer to the Pei Services function and data +// structure. +// +// Output: TRUE - It is an S4 Resume +// FALSE - It is not an S4 Resume +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN IsS4 ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo ) +{ + if ((READ_IO16_PM(ACPI_IOREG_PM1_CNTL) & 0x1c00) == 0x1800) //0x04 + return TRUE; + return FALSE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IsCmosBad +// +// Description: This function determines CMOS data is available. +// +// Input: PeiServices - Pointer to the Pei Services function and data +// structure. +// +// Output: TRUE - CMOS data is bad +// FALSE - CMOS DATA is available +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN IsCmosBad ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo ) +{ + return (READ_IO8_RTC(CMOS_BAD_REG | RTC_NMI_MASK) & 0xc0) ? TRUE : FALSE; +} + +#if KBC_SUPPORT && Recovery_SUPPORT +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ResetKbc +// +// Description: This function resets Keyboard controller for Ctrl-Home +// recovery function. +// +// Input: PeiServices - Pointer to the Pei Services function and +// data structure +// CpuIo - Pointer to the CPU I/O PPI +// PciCfg - Pointer to the PCI Configuration PPI +// +// Output: None +// +// Notes: No porting required. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID ResetKbc ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg +) +{ + volatile UINT8 KbcSts = 0; + volatile UINT8 Buffer8; + UINT32 TimeOut = 0x100; + + // Reset KBC + if (CpuIo->IoRead8( PeiServices, CpuIo, KBC_IO_STS ) != 0xff) { + // Clear KBC buffer + do { + Buffer8 = CpuIo->IoRead8( PeiServices, CpuIo, KBC_IO_DATA ); + KbcSts = CpuIo->IoRead8( PeiServices, CpuIo, KBC_IO_STS ); // 0x64 + TimeOut--; + } while ((KbcSts & 3) && (TimeOut != 0)); + + + // Send BAT command + CpuIo->IoWrite8( PeiServices, CpuIo, KBC_IO_STS, 0xaa ); // 0x64 + + // IBFree + for (TimeOut = 0; TimeOut < 0x1000; TimeOut++) { + CpuIo->IoWrite8( PeiServices, CpuIo, IO_DELAY_PORT, KbcSts ); + KbcSts = CpuIo->IoRead8( PeiServices, CpuIo, KBC_IO_STS ); // 0x64 + if ((KbcSts & 2) == 0) break; + } + + // OBFree + for (TimeOut = 0; TimeOut < 0x500; TimeOut++) { + CpuIo->IoWrite8( PeiServices, CpuIo, IO_DELAY_PORT, KbcSts ); + KbcSts = CpuIo->IoRead8( PeiServices, CpuIo, KBC_IO_STS ); // 0x64 + if (KbcSts & 1) break; + } + + // Get result if needed + if (KbcSts & 1) + Buffer8 = CpuIo->IoRead8( PeiServices, CpuIo, KBC_IO_DATA ); + } + + // Clear KBC status buffer. + KbcSts = CpuIo->IoRead8 ( PeiServices, CpuIo, KBC_IO_STS ); // 0x64 +} +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: UpdateBootMode +// +// Description: This function determines the boot mode of the system. +// After the correct boot mode has been determined, the PEI +// Service function SetBootMode is called and then +// the MasterBootModePpi is installed +// +// Input: PeiServices - Pointer to the Pei Services function and +// data structure +// CpuIo - Pointer to the CPU I/O PPI +// PciCfg - Pointer to the PCI Configuration PPI +// +// Output: Always returns EFI_SUCCESS +// Also defines the boot mode for the system +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS UpdateBootMode ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg +) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + + // Check for changes in the possible boot modes. This should be made in + // prioritized order. At the end of this function the boot mode is + // determined. The EFI_BOOT_MODE is defined in the PEI Spec + + Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode); + if (EFI_ERROR(Status) || (BootMode != BOOT_IN_RECOVERY_MODE)) + BootMode = BOOT_WITH_FULL_CONFIGURATION; + + // Returns 0 if no S3 resume detected returns -1 if this is an S3 boot + if (IsS3(PeiServices, CpuIo)) { + BootMode = BOOT_ON_S3_RESUME; + PEI_TRACE((-1,PeiServices, "Boot mode = BOOT_ON_S3_RESUME\n")); + } else { + // Check for S4 resume + if (IsS4(PeiServices, CpuIo)) { + BootMode = BOOT_ON_S4_RESUME; + PEI_TRACE((-1, PeiServices, "Boot mode = BOOT_ON_S4_RESUME\n")); + } + // Check for recovery mode + #if KBC_SUPPORT && Recovery_SUPPORT && PERFORM_KBC_RESET + ResetKbc(PeiServices, CpuIo, PciCfg); + #endif + + if (IsRecovery(PeiServices, PciCfg, CpuIo)) + BootMode = BOOT_IN_RECOVERY_MODE; + } + + if (IsCmosBad(PeiServices, CpuIo)) { + if (BootMode != BOOT_IN_RECOVERY_MODE){ + BootMode = BOOT_WITH_DEFAULT_SETTINGS; + PEI_TRACE((-1,PeiServices,"Boot mode = BOOT_WITH_DEFAULT_SETTING\n")); + } + +#if FORCE_USER_TO_SETUP_IF_CMOS_BAD // [EIP88358] >> +{ + EFI_STATUS Status; + UINT16 HobSize = sizeof(CMOS_BAD_HOB); + EFI_GUID CmosBadHobGuid = CMOS_BAD_HOB_GUID; + CMOS_BAD_HOB *CmosBadHob; + + Status = (*PeiServices)->CreateHob( PeiServices, + EFI_HOB_TYPE_GUID_EXTENSION, + HobSize, + &CmosBadHob); + if(!EFI_ERROR(Status)) { + CmosBadHob->Header.Name = CmosBadHobGuid; + } +} +#endif // [EIP88358] << + } +#if Capsule2_0_SUPPORT + +#else + #if CAPSULE_SUPPORT + if (!EFI_ERROR(CheckIfCapsuleAvailable())) + BootMode = BOOT_ON_FLASH_UPDATE; + #endif +#endif + // Set the system BootMode + (*PeiServices)->SetBootMode(PeiServices, BootMode); + + // Let everyone know that boot mode has been determined by installing the + // MasterBootMode PPI + (*PeiServices)->InstallPpi(PeiServices, mBootModePpi ); + + (*PeiServices)->GetBootMode (PeiServices, &BootMode); + + if (BootMode == BOOT_IN_RECOVERY_MODE) // Recovery Boot Mode PPI + (*PeiServices)->InstallPpi( PeiServices, mRecoveryModePpi ); + + // [EIP87695]> +#if SYSTEM_REBOOT_NORMALLY_IF_S3_IS_FAILED + if (BootMode == BOOT_ON_S3_RESUME) //S3 Boot Mode PPI + WRITE_IO16_PM(ACPI_IOREG_PM1_CNTL, READ_IO16_PM(ACPI_IOREG_PM1_CNTL) & 0xe3ff ); // Clear S3 for avoiding S3 resume twice +#endif + // <[EIP87695] + + return EFI_SUCCESS; +} + +#if defined(SUPPORT_RAID_DRIVER) && SUPPORT_RAID_DRIVER && (PTT_VER > 15) +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: DetectSataPortInfo +// +// Description: This function provides SATA Port Information +// +// Input: PeiServices - Pointer to the PEI services table +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID DetectSataPortInfo ( + IN EFI_PEI_SERVICES **PeiServices) +{ + EFI_STATUS Status; + UINT16 HobSize = sizeof(SATA_PRESENT_HOB); + EFI_GUID SataPresentHobGuid = AMI_SATA_PRESENT_HOB_GUID; + SATA_PRESENT_HOB *SataPresentHob; + UINT16 SataClassCode; + UINT8 SataPortStatus; + UINT8 SataPortEnable = 0; + SB_SETUP_DATA SbSetupData; + UINT8 i; + + Status = (*PeiServices)->CreateHob (PeiServices, + EFI_HOB_TYPE_GUID_EXTENSION, + HobSize, + &SataPresentHob); + if(EFI_ERROR(Status)) return; + + SataPresentHob->EfiHobGuidType.Name = SataPresentHobGuid; + + for (i = 0; i < 4; i++) { + SataPresentHob->SataInfo[i].ClassCode = 0; + SataPresentHob->SataInfo[i].PresentPortBitMap = 0; + } + + // The SATA Mode Select should be configured in PchInitPeim. + SataClassCode = READ_PCI16_SATA(R_PCH_SATA_SUB_CLASS_CODE); + SataPresentHob->SataInfo[0].ClassCode = SataClassCode; + + if ((SataClassCode & 0xFF) == V_PCH_SATA_SUB_CLASS_CODE_IDE) { + // Lynx Point-LP didn't support IDE mode, so code should not enter here. + SataPortStatus = READ_PCI16_SATA(R_PCH_SATA_PCS) >> 8; + SataPresentHob->SataInfo[0].PresentPortBitMap = (SATA1_BDF << 16) | (SataPortStatus & 0xF); // Port 0~3 + SataPortStatus = READ_PCI16_SATA2(R_PCH_SATA_PCS) >> 8; + SataPresentHob->SataInfo[1].PresentPortBitMap = (SATA2_BDF << 16) | (SataPortStatus & 0x3); // Port 4~5 + SataPresentHob->SataInfo[1].ClassCode = SataClassCode; + SataPresentHob->ControllerCount = 2; + } else { // AHCI or Raid + GetSbSetupData (PeiServices, &SbSetupData, TRUE); + SataPortStatus = READ_PCI16_SATA(R_PCH_SATA_PCS) >> 8; + for (i = 0; i < GetPchMaxSataPortNum(); i++) { + // SataPort controll is done in DXE, so check Setup value here. + SataPortEnable |= (SbSetupData.SataPort[i] << i); + } + SataPortStatus &= SataPortEnable; + SataPresentHob->SataInfo[0].PresentPortBitMap = (SATA1_BDF << 16) | (SataPortStatus & 0x3F); // Port 0~5 + SataPresentHob->ControllerCount = 1; + } +} +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBPEI_Init +// +// Description: This function is the entry point for this PEI. This function +// initializes the chipset SB +// +// Input: FfsHeader - Pointer to the FFS file header +// PeiServices - Pointer to the PEI services table +// +// Output: Return Status based on errors that occurred while waiting for +// time to expire. +// +// Notes: This function should initialize South Bridge for memory +// detection. +// Install AMI_PEI_SBINIT_POLICY_PPI to indicate that SB Init +// PEIM is installed +// Following things can be done at this point: +// - Enabling top of 4GB decode for full flash ROM +// - Programming South Bridge ports to enable access to +// South Bridge and other I/O bridge access +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EFIAPI SBPEI_Init ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices ) +{ + EFI_STATUS Status; + IN EFI_PEI_PCI_CFG2_PPI *PciCfg; + EFI_PEI_CPU_IO_PPI *CpuIo; + AMI_PEI_PCI_TABLE_INIT_PPI *AMIPCITableInit; + SB_SETUP_DATA SbSetupData; + AMI_GPIO_INIT_TABLE_STRUCT *pTable; + AMI_PEI_SB_CUSTOM_PPI *SBPeiOemPpi = NULL; + PCH_SERIES PchSeries = GetPchSeries(); + + // Get pointer to the PCI config PPI + PciCfg = (*PeiServices)->PciCfg; + CpuIo = (*PeiServices)->CpuIo; + + PEI_PROGRESS_CODE (PeiServices, PEI_CAR_SB_INIT); + WRITE_IO8(PORTB_IO_CNTL, 0x0c); // Disable IOCHK NMI #, PCI SERR#. (0x61) + + // Locate AMI PCI Table Init PPI + Status = (*PeiServices)->LocatePpi( PeiServices, \ + &gAmiPEIPCITableInitPpiGuid, \ + 0, \ + NULL, \ + &AMIPCITableInit ); + + // Assert if not found - the AMI PCI Table Init PPI should exist + ASSERT_PEI_ERROR( PeiServices, Status ); + + GetSbSetupData( PeiServices, &SbSetupData, TRUE ); + +#if WdtPei_SUPPORT +{ + WDT_PPI *WdtPpi; + + // Locate WDT PPI for access to Wdt->Disable() + // + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gWdtPpiGuid, + 0, + NULL, + &WdtPpi + ); + if (!EFI_ERROR (Status)) { + WdtPpi->Disable(); + } +} +#endif + // Program Pch devices bar base + ProgramPchDeviceBase(PeiServices, PciCfg); + +#if SB_STALL_PPI_SUPPORT + // Install the SB Stall PPI + Status = (*PeiServices)->InstallPpi( PeiServices, \ + &mBeforeBootModePpiList[0] ); + ASSERT_PEI_ERROR( PeiServices, Status ); +#endif + + // Program Pch RCBA base + ProgramRCRBMmio(PeiServices, CpuIo); + + UpdateBootMode( PeiServices, CpuIo, PciCfg ); + + // Install PchPlatformPolicyPpi, it will notify to PchInitialize. + InstallPchPlatformPolicyPpi( PeiServices, &SbSetupData); + + //DeCode LPC IO + ProgramSBIoDecodeRegs( PeiServices, PciCfg); + + //Program GPIOs. + //Program the default GPIO Setting for chipset. +#if defined PROGRAM_DEFAULT_GPIO && PROGRAM_DEFAULT_GPIO == 1 + if (PchSeries == PchLp) { + pTable = stSB_GPIODefaultULTInitTable; + }else{ + pTable = stSB_GPIODefaultInitTable; + } + + ProgramGPIO( PeiServices, \ + CpuIo, \ + &SbSetupData, \ + pTable); +#endif + + //Program the OEM GPIO Setting for board. + Status = (*PeiServices)->LocatePpi( PeiServices, \ + &gAmiPeiSBCustomPpiGuid, \ + 0, \ + NULL, \ + &SBPeiOemPpi ); + + if (Status == EFI_SUCCESS) { + if (SBPeiOemPpi->GpioInit != NULL) { + pTable = SBPeiOemPpi->GpioInit->GpioTable; + ProgramGPIO( PeiServices, \ + CpuIo, \ + &SbSetupData, \ + pTable); + } + } else { + SBPeiOemPpi = NULL; + } + + // Program SB Devices' Subsystem Vendor ID & Subsystem ID + ProgramSBSubId( PeiServices, PciCfg, SBPeiOemPpi ); + + //Program PM Regs. + InitPMRegs(PeiServices, CpuIo, &SbSetupData); + + // General power failure handling + GeneralPowerFailureHandler(PeiServices, CpuIo, PciCfg); + + InitRTC( PeiServices, CpuIo ); + + // Set what state (S0/S5) to go to when power is re-applied after a power failure (G3 state) + SetTheStateToGoAfterG3(PeiServices, CpuIo, PciCfg, &SbSetupData); + + InitPCIe( PeiServices, CpuIo, PciCfg ); + + InitSMBus( PeiServices, CpuIo, PciCfg ); + + + // Install the SB Init Policy PPI + Status = (*PeiServices)->InstallPpi( PeiServices, &mPpiList[0] ); + ASSERT_PEI_ERROR( PeiServices, Status ); + + // Setup a SBPEI entry after PEI permantent memory be installed + + Status = (*PeiServices)->NotifyPpi( PeiServices, AfterMrcNotifyList ); + + Status = (*PeiServices)->NotifyPpi ( PeiServices, mMemoryReadyNotify ); + ASSERT_PEI_ERROR( PeiServices, Status ); + +#if defined iME_SUPPORT && iME_SUPPORT == 0 + if (!IsS3(PeiServices, CpuIo)) { + WRITE_IO16_PM(ACPI_IOREG_PM1_CNTL, 0x20); // Clear Sleep Type + } +#endif + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ProgramGPIO +// +// Description: This function initializes SB GPIOs +// +// Input: PeiServices - Pointer to the PEI services table +// CpuIo - Pointer to the CPU I/O PPI +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID ProgramGPIO ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo, + IN SB_SETUP_DATA *SbSetupData, + IN AMI_GPIO_INIT_TABLE_STRUCT *pTable +) +{ + UINT16 i; + UINT32 OWN1; + UINT32 OWN2; + UINT32 OWN3; + UINT32 GPN_CFG1[96]; + UINT32 GPN_CFG2[96]; + UINT32 USE1_SEL; + UINT32 USE2_SEL; + UINT32 USE3_SEL; + UINT32 IO1_SEL; + UINT32 IO2_SEL; + UINT32 IO3_SEL; + UINT32 LVL1_SEL; + UINT32 LVL2_SEL; + UINT32 LVL3_SEL; + UINT32 INV1_SEL; + UINT32 RST1_SEL; + UINT32 RST2_SEL; + UINT32 RST3_SEL; + UINT32 BLNK_SEL; + UINT32 INT1_SEL; + UINT32 INT2_SEL; + UINT32 INT3_SEL; + UINT16 Offset; + UINT16 LpcDeviceId; + PCH_SERIES PchSeries = GetPchSeries(); + + LpcDeviceId = READ_PCI16_SB(R_PCH_LPC_DEVICE_ID); + + if (pTable[0].GpioNo != 0xffff) { + if (PchSeries == PchLp) { + OWN1 = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_OWN1); // 0x00 + OWN2 = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_OWN2); // 0x04 + OWN3 = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_OWN3); // 0x08 + INT1_SEL = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_INT_SEL1); // 0x90 + INT2_SEL = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_INT_SEL2); // 0x94 + INT3_SEL = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_INT_SEL3); // 0x98 + } else { + USE1_SEL = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_USE_SEL); // 0x00 + IO1_SEL = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_IO_SEL); // 0x04 + LVL1_SEL = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_LVL); // 0x0C + INV1_SEL = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GPI_INV); // 0x2C + + USE2_SEL = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_USE_SEL2); // 0x30 + IO2_SEL = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_IO_SEL2); // 0x34 + LVL2_SEL = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_LVL2); // 0x38 + + USE3_SEL = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_USE_SEL3); // 0x40 + IO3_SEL = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_IO_SEL3); // 0x44 + LVL3_SEL = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_LVL3); // 0x48 + } + BLNK_SEL = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GPO_BLINK); // 0x18 + RST1_SEL = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_RST_SEL1); // 0x60 + RST2_SEL = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_RST_SEL2); // 0x64 + RST3_SEL = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_RST_SEL3); // 0x68 + + for (i = 0; pTable[i].GpioNo != 0xffff; i++) { + + Offset = pTable[i].GpioNo; + if (PchSeries == PchLp) { + GPN_CFG1[Offset] = READ_IO32(GPIO_BASE_ADDRESS + (GP_IOREG_GP_GPN_CFG1 + GP_GPIO_CONFIG_SIZE*Offset)); // 0x100 + n*8h + GPN_CFG2[Offset] = READ_IO32(GPIO_BASE_ADDRESS + (GP_IOREG_GP_GPN_CFG2 + GP_GPIO_CONFIG_SIZE*Offset)); // 0x104 + n*8h + + GPN_CFG1[Offset] = (GPN_CFG1[Offset] & ~(BIT31)) | (pTable[i].GpioCfg.Fileds.LVL << 31); + GPN_CFG1[Offset] = (GPN_CFG1[Offset] & ~(BIT4)) | (pTable[i].GpioCfg.Fileds.LEB << 4); + GPN_CFG1[Offset] = (GPN_CFG1[Offset] & ~(BIT3)) | (pTable[i].GpioCfg.Fileds.INV << 3); + GPN_CFG1[Offset] = (GPN_CFG1[Offset] & ~(BIT2)) | (pTable[i].GpioCfg.Fileds.IO << 2); + GPN_CFG1[Offset] = (GPN_CFG1[Offset] & ~(1)) | (pTable[i].GpioCfg.Fileds.USE); + GPN_CFG2[Offset] = (GPN_CFG2[Offset] & ~(BIT2)) | (pTable[i].GpioCfg.Fileds.DIS << 2); + //(EIP118667)>> + if(pTable[i].GpioCfg.Fileds.IO == 0 && pTable[i].GpioCfg.Fileds.USE == 1){ + GPN_CFG2[Offset] = (GPN_CFG2[Offset] & ~(BIT2)) | (BIT2); + } + //(EIP118667)<< + GPN_CFG2[Offset] = (GPN_CFG2[Offset] & ~(3)) | (pTable[i].GpioCfg.Fileds.WP); + } + + if (Offset < 32) { + if (PchSeries == PchLp) { + OWN1 = (OWN1 & ~(1 << Offset)) | (pTable[i].GpioCfg.Fileds.OWN << Offset); + INT1_SEL = (INT1_SEL & ~(1 << Offset)) | (pTable[i].GpioCfg.Fileds.INT << Offset); + } else { + USE1_SEL = (USE1_SEL & ~(1 << Offset)) | (pTable[i].GpioCfg.Fileds.USE << Offset); + IO1_SEL = (IO1_SEL & ~(1 << Offset)) | (pTable[i].GpioCfg.Fileds.IO << Offset); + LVL1_SEL = (LVL1_SEL & ~(1 << Offset)) | (pTable[i].GpioCfg.Fileds.LVL << Offset); + INV1_SEL = (INV1_SEL & ~(1 << Offset)) | (pTable[i].GpioCfg.Fileds.INV << Offset); + } + RST1_SEL = (RST1_SEL & ~(1 << Offset)) | (pTable[i].GpioCfg.Fileds.RST << Offset); + BLNK_SEL = (BLNK_SEL & ~(1 << Offset)) | (pTable[i].GpioCfg.Fileds.BLK << Offset); + } else if ((Offset >= 32) && (Offset < 64)) { + if (PchSeries == PchLp) { + OWN2 = (OWN2 & ~(1 << (Offset - 32))) | (pTable[i].GpioCfg.Fileds.OWN << (Offset - 32)); + INT2_SEL = (INT2_SEL & ~(1 << (Offset - 32))) | (pTable[i].GpioCfg.Fileds.INT << (Offset - 32)); + } else { + USE2_SEL = (USE2_SEL & ~(1 << (Offset - 32))) | (pTable[i].GpioCfg.Fileds.USE << (Offset - 32)); + IO2_SEL = (IO2_SEL & ~(1 << (Offset - 32))) | (pTable[i].GpioCfg.Fileds.IO << (Offset - 32)); + LVL2_SEL = (LVL2_SEL & ~(1 << (Offset - 32))) | (pTable[i].GpioCfg.Fileds.LVL << (Offset - 32)); + } + RST2_SEL = (RST2_SEL & ~(1 << (Offset - 32))) | (pTable[i].GpioCfg.Fileds.RST << (Offset - 32)); + } else { + if (PchSeries == PchLp) { + OWN3 = (OWN3 & ~(1 << (Offset - 64))) | (pTable[i].GpioCfg.Fileds.OWN << (Offset - 64)); + INT3_SEL = (INT3_SEL & ~(1 << (Offset - 64))) | (pTable[i].GpioCfg.Fileds.INT << (Offset - 64)); + } else { + USE3_SEL = (USE3_SEL & ~(1 << (Offset - 64))) | (pTable[i].GpioCfg.Fileds.USE << (Offset - 64)); + IO3_SEL = (IO3_SEL & ~(1 << (Offset - 64))) | (pTable[i].GpioCfg.Fileds.IO << (Offset - 64)); + LVL3_SEL = (LVL3_SEL & ~(1 << (Offset - 64))) | (pTable[i].GpioCfg.Fileds.LVL << (Offset - 64)); + } + RST3_SEL = (RST3_SEL & ~(1 << (Offset - 64))) | (pTable[i].GpioCfg.Fileds.RST << (Offset - 64)); + } + if (PchSeries == PchLp) { + WRITE_IO32(GPIO_BASE_ADDRESS + (GP_IOREG_GP_GPN_CFG1 + GP_GPIO_CONFIG_SIZE*Offset), GPN_CFG1[Offset]); // 0x100 + n*8h + WRITE_IO32(GPIO_BASE_ADDRESS + (GP_IOREG_GP_GPN_CFG2 + GP_GPIO_CONFIG_SIZE*Offset), GPN_CFG2[Offset]); // 0x104 + n*8h + } + } + + if (PchSeries == PchLp) { + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_OWN1, OWN1); // 0x00 + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_OWN2, OWN2); // 0x04 + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_OWN3, OWN3); // 0x08 + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_INT_SEL1, INT1_SEL); // 0x90 + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_INT_SEL2, INT2_SEL); // 0x94 + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_INT_SEL3, INT3_SEL); // 0x98 + WRITE_IO32(GPIO_BASE_ADDRESS + GPI_IRQ_2_IOAPIC, GPI_IRQ_2_IOXAPIC); // 0x10 + } else { + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_USE_SEL, USE1_SEL); // 0x00 + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_IO_SEL, IO1_SEL); // 0x04 + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_LVL, LVL1_SEL); // 0x0C + + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GPI_INV, INV1_SEL); // 0x2C + + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_USE_SEL2, USE2_SEL); // 0x30 + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_IO_SEL2, IO2_SEL); // 0x34 + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_LVL2, LVL2_SEL); // 0x38 + + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_USE_SEL3, USE3_SEL); // 0x40 + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_IO_SEL3, IO3_SEL); // 0x44 + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_LVL3, LVL3_SEL); // 0x48 + } + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GPO_BLINK, BLNK_SEL); // 0x18 + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_RST_SEL1, RST1_SEL); // 0x60 + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_RST_SEL2, RST2_SEL); // 0x64 + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_GP_RST_SEL3, RST3_SEL); // 0x68 + } + + // BIOS implementation for SUS_PWR_DN_ACK + // As soon as platform BARs are initialized, BIOS must ensure that the following things + // are set high on all boot flows: + // (1) GPIO_BASE_ADDRESS + 0x60[30] + // (2) GPIO[30] pin (GPIO_BASE_ADDRESS + GP_LVL) (Done in GPIO.SDL) + if (IS_PCH_LPT_LPC_DEVICE_ID_MOBILE (LpcDeviceId)) { + SET_IO32 (GPIO_BASE_ADDRESS + GP_IOREG_GP_RST_SEL1, BIT30); // 0x60 + } + // + // Now enable LANPHY_PC GPIO if LAN is enabled in the setup. + // Enabling this GPIO for all the boards. Both Red Fort and Buffalo Trail uses GPIO12 for this. + // Electric Peak does not use GPIO12, so changing the value for all boards should not effect + if (SbSetupData->PchLan) { + if (PchSeries == PchLp) { + SET_IO32 (GPIO_BASE_ADDRESS + (GP_IOREG_GP_GPN_CFG1 + GP_GPIO_CONFIG_SIZE*22), BIT31); // 0x190 + } else { + SET_IO32 (GPIO_BASE_ADDRESS + GP_IOREG_GP_LVL, BIT12); // 0x0C + } + } + + // Clear GPI Status + if (PchSeries == PchLp) { + WRITE_IO16_PM(ACPI_PCHLP_IOREG_GPE0_STS, 0xffff); // 0x80 + WRITE_IO16_PM(ACPI_PCHLP_IOREG_GPE0_STS + 4, 0xffff); // 0x84 + WRITE_IO16_PM(ACPI_PCHLP_IOREG_GPE0_STS + 8, 0xffff); // 0x88 + } else { + WRITE_IO16_PM(ACPI_IOREG_GPE0_STS + 2, 0xffff); // 0x22 + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IsSBDevice +// +// Description: This function detimines SB PCI devices +// +// Input: UINT64 PciAddress +// UINT8 *PciSidReg +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS IsSBDevice( + IN UINT64 PciAddress, + IN OUT UINT8 *PciSidReg +) +{ + UINT8 i; + AMI_SB_PCI_DEVICES_TABLE_STRUCT PchDeviceTable[] = { HECI_BUS_DEV_FUN, ME_REG_SVID, + HECI2_BUS_DEV_FUN, ME_REG_SVID, + IDER_BUS_DEV_FUN, ME_REG_SVID, + KT_BUS_DEV_FUN, ME_REG_SVID, + XHCI_BUS_DEV_FUN, XHCI_REG_SVID, + LAN_BUS_DEV_FUN, LAN_REG_SVID, + EHCI2_BUS_DEV_FUN, EHCI_REG_SVID, + HDA_BUS_DEV_FUN, HDA_REG_SVID, + PCIEBRS_BUS_DEV_FUN, PCIEBRS_REG_SVID, + PCIEBRS2_BUS_DEV_FUN, PCIEBRS_REG_SVID, + PCIEBRS3_BUS_DEV_FUN, PCIEBRS_REG_SVID, + PCIEBRS4_BUS_DEV_FUN, PCIEBRS_REG_SVID, + PCIEBRS5_BUS_DEV_FUN, PCIEBRS_REG_SVID, + PCIEBRS6_BUS_DEV_FUN, PCIEBRS_REG_SVID, + PCIEBRS7_BUS_DEV_FUN, PCIEBRS_REG_SVID, + PCIEBRS8_BUS_DEV_FUN, PCIEBRS_REG_SVID, + PCIBR_BUS_DEV_FUN, PCIBR_REG_SVID, + EHCI_BUS_DEV_FUN, EHCI_REG_SVID, + SB_BUS_DEV_FUN, R_PCH_LPC_SS, + SATA_BUS_DEV_FUN, SATA_REG_SVID, + SMBUS_BUS_DEV_FUN, SMBUS_REG_SVID, + SATA2_BUS_DEV_FUN, SATA_REG_SVID, + THERMAL_BUS_DEV_FUN, R_PCH_LPC_SS + }; + UINT32 TableSize = sizeof(PchDeviceTable) / sizeof(AMI_SB_PCI_DEVICES_TABLE_STRUCT); + + for (i = 0; i < TableSize; i++) { + + if (PciAddress != PchDeviceTable[i].PciAddr) { + continue; + } else { + if (READ_PCI32((UINT8)(Shr64(PchDeviceTable[i].PciAddr, 24) & 0xff), \ + (UINT8)(Shr64(PchDeviceTable[i].PciAddr, 16) & 0xff), \ + (UINT8)(Shr64(PchDeviceTable[i].PciAddr, 8) & 0xff), \ + 0) == 0xffffffff) + return EFI_UNSUPPORTED; + + *PciSidReg = PchDeviceTable[i].PciSidReg; + return EFI_SUCCESS; + } + } + return EFI_UNSUPPORTED; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ProgramSBSubId +// +// Description: This function programs SB PCI devices sub-vendor ID and +// sub-system ID. +// +// Input: PeiServices - Pointer to the PEI services table +// PciCfg - Pointer to the PCI Configuration PPI +// +// Output: VOID +// +// Notes: 1. This routine only programs the PCI device in SB, hence, we +// have to check the bus/device/function numbers whether they +// are a SB PCI device or not. +// 2. This routine is invoked by PEI phase.(After PEI permantent +// memory be installed) +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID ProgramSBSubId ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg, + IN AMI_PEI_SB_CUSTOM_PPI *SBPeiOemPpi +) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINTN i = 0; + UINT32 PciSid = 0xffffffff; + UINT8 PciSidReg = 0xff; + AMI_SB_PCI_SSID_TABLE_STRUCT DefaultSIdTbl[] = {SB_PCI_DEVICES_SSID_TABLE}; + AMI_SB_PCI_SSID_TABLE_STRUCT *SsidTblPtr = DefaultSIdTbl; + + if ((SBPeiOemPpi != NULL) && (SBPeiOemPpi->SsidTable != NULL)) + SsidTblPtr = SBPeiOemPpi->SsidTable; + + while (SsidTblPtr[i].PciAddr != 0xffffffffffffffff) { + if (IsSBDevice(SsidTblPtr[i].PciAddr, &PciSidReg) == EFI_SUCCESS) { + if (SsidTblPtr[i].Sid == 0xffffffff) { + Status = PciCfg->Read( PeiServices, + PciCfg, + EfiPeiPciCfgWidthUint32, + SsidTblPtr[i].PciAddr, + &PciSid); + } else { + PciSid = SsidTblPtr[i].Sid; + } + + if (SsidTblPtr[i].PciAddr == EHCI_BUS_DEV_FUN) + SET_PCI8_EHCI(R_PCH_EHCI_ACCESS_CNTL, 1); + else if (SsidTblPtr[i].PciAddr == EHCI2_BUS_DEV_FUN) + SET_PCI8_EHCI2(R_PCH_EHCI_ACCESS_CNTL, 1); + + Status = PciCfg->Write( PeiServices, + PciCfg, + EfiPeiPciCfgWidthUint32, + SsidTblPtr[i].PciAddr | PciSidReg, + &PciSid); + + if (SsidTblPtr[i].PciAddr == EHCI_BUS_DEV_FUN) + RESET_PCI8_EHCI(R_PCH_EHCI_ACCESS_CNTL, 1); + else if (SsidTblPtr[i].PciAddr == EHCI2_BUS_DEV_FUN) + RESET_PCI8_EHCI2(R_PCH_EHCI_ACCESS_CNTL, 1); + } + i++; + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitPCIe +// +// Description: This function initializes SB PCI Express controller(s) +// +// Input: PeiServices - Pointer to the PEI services table +// CpuIo - Pointer to the CPU I/O PPI +// PciCfg - Pointer to the PCI Configuration PPI +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID InitPCIe ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg +) +{ + // TODO +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitSMBus +// +// Description: This function initializes SB SMBUS controller(s) +// +// Input: PeiServices - Pointer to the PEI services table +// CpuIo - Pointer to the CPU I/O PPI +// PciCfg - Pointer to the PCI Configuration PPI +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID InitSMBus ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg +) +{ + // TODO +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitUsbMisc +// +// Description: Miscellaneous USB initialization. +// +// Input: PeiServices - Pointer to the PEI services table +// CpuIo - Pointer to the CPU I/O PPI +// PciCfg - Pointer to the PCI Configuration PPI +// BootMode - Boot Mode +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID InitUsbMisc ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg, + IN EFI_BOOT_MODE BootMode +) +{ + PCH_SERIES PchSeries = GetPchSeries(); +#ifndef PEI_XHCI_MMIOBASE + UINT32 XhciMmioBase = 0xFE400000; //[EIP156783] +#else + UINT32 XhciMmioBase = PEI_XHCI_MMIOBASE; //[EIP115528] >> +#endif + UINT8 XhciCapLength; + UINT8 XhciMaxPorts; + UINT32 XhciPort; + EFI_PEI_STALL_PPI *StallPpi; + StallPpi = &mStallPpi; + +if ((BootMode == BOOT_IN_RECOVERY_MODE) || (BootMode == BOOT_ON_FLASH_UPDATE)) { + WRITE_PCI32( DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_XHCI, \ + PCI_FUNCTION_NUMBER_PCH_XHCI, \ + 0x10, \ + XhciMmioBase); + WRITE_PCI8( DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_XHCI, \ + PCI_FUNCTION_NUMBER_PCH_XHCI, \ + 0x04, \ + 0x06); + WRITE_PCI8( DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_XHCI, \ + PCI_FUNCTION_NUMBER_PCH_XHCI, \ + R_PCH_XHCI_USB3PR, \ + 0x3F); + + //Add some delay to wait that device links are stable + StallPpi->Stall(PeiServices, StallPpi, 500 * 1000); + + XhciCapLength = READ_MEM8(XhciMmioBase); + if (PchSeries == PchH) { + switch ((READ_MEM8(XhciMmioBase + R_PCH_XHCI_FUS)) & B_PCH_XHCI_FUS_SSPRTCNT) { + case V_PCH_XHCI_FUS_SSPRTCNT_11B: + XhciMaxPorts = 0x0F; + break; + + case V_PCH_XHCI_FUS_SSPRTCNT_10B: + XhciMaxPorts = 0x11; + break; + + case V_PCH_XHCI_FUS_SSPRTCNT_01B: + XhciMaxPorts = 0x13; + break; + + case V_PCH_XHCI_FUS_SSPRTCNT_00B: + default: + XhciMaxPorts = 0x15; + break; + } + } else { + XhciMaxPorts = READ_MEM8(XhciMmioBase + 0x7); + } + //Clear each xHCI port power + for (XhciPort = 0; XhciPort < XhciMaxPorts; XhciPort++) { + RESET_MEM32(XhciMmioBase + XhciCapLength + 0x400 + (0x10 * XhciPort), BIT9); + } + // Set xHCI D0h & D8h as power-on default value. + WRITE_PCI16( DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_XHCI, \ + PCI_FUNCTION_NUMBER_PCH_XHCI, \ + R_PCH_XHCI_USB2PR, \ + 0 ); + WRITE_PCI8( DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_XHCI, \ + PCI_FUNCTION_NUMBER_PCH_XHCI, \ + R_PCH_XHCI_USB3PR, \ + 0 ); + WRITE_PCI8( DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_XHCI, \ + PCI_FUNCTION_NUMBER_PCH_XHCI, \ + 0x04, \ + 0); + WRITE_PCI32( DEFAULT_PCI_BUS_NUMBER_PCH, \ + PCI_DEVICE_NUMBER_PCH_XHCI, \ + PCI_FUNCTION_NUMBER_PCH_XHCI, \ + 0x10, \ + 0); + } + + + // [EIP107424] [EIP123117]> + if (BootMode != BOOT_ON_S3_RESUME) { + // + // Clear unexpected USB EHCI Legacy Support Extended status. + // Set B0:D1A/1D:F0 Reg#6Ch[31:29] = '111b'. + // + WRITE_PCI32_EHCI ( R_PCH_EHCI_LEGEXT_CS, \ + B_PCH_EHCI_LEGEXT_CS_SMIBAR | \ + B_PCH_EHCI_LEGEXT_CS_SMIPCI | \ + B_PCH_EHCI_LEGEXT_CS_SMIOS); + if (PchSeries == PchH) { + WRITE_PCI32_EHCI ( R_PCH_EHCI_LEGEXT_CS, \ + B_PCH_EHCI_LEGEXT_CS_SMIBAR | \ + B_PCH_EHCI_LEGEXT_CS_SMIPCI | \ + B_PCH_EHCI_LEGEXT_CS_SMIOS); + } + } + // <[EIP107424] [EIP123117] + //[EIP115528]<< +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ProgramSBRegAfterMemInstalled +// +// Description: This function can be used to program any SB regisater after +// PEI permantent memory be installed. +// +// Input: FfsHeader - Pointer to the desired FFS header. +// PeiServices - Pointer to the PEI services table. +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS ProgramSBRegAfterMemInstalled ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *InvokePpi ) +{ + EFI_STATUS Status = EFI_SUCCESS; + EFI_PEI_CPU_IO_PPI *CpuIo; + IN EFI_PEI_PCI_CFG2_PPI *PciCfg; + EFI_BOOT_MODE BootMode; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *ReadOnlyVariable; + UINTN VariableSize; + UINT32 SbAslBufVarPtr; + EFI_GUID SbAslBufPtrGuid = SB_ASL_BUFFER_PTR_GUID; + CHAR16 SbAslBufPtrVar[] = SB_ASL_BUFFER_PTR_VARIABLE; + + CpuIo = (*PeiServices)->CpuIo; + PciCfg = (*PeiServices)->PciCfg; + + PEI_PROGRESS_CODE (PeiServices, PEI_MEM_SB_INIT); + + Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode); + + InitUsbMisc( PeiServices, CpuIo, PciCfg, BootMode ); + +#if (ACPI_SUPPORT) + if (BootMode == BOOT_ON_S3_RESUME) { + Status = (*PeiServices)->LocatePpi( PeiServices, \ + &gEfiPeiReadOnlyVariable2PpiGuid, \ + 0, \ + NULL, \ + &ReadOnlyVariable ); + ASSERT_PEI_ERROR( PeiServices, Status ); + VariableSize = sizeof(SbAslBufVarPtr); + Status = ReadOnlyVariable->GetVariable( ReadOnlyVariable, \ + SbAslBufPtrVar, \ + &SbAslBufPtrGuid, \ + NULL, \ + &VariableSize, \ + &SbAslBufVarPtr ); + if (!EFI_ERROR(Status)) { + // Update ACPI RTC status + RESET_MEM8(SbAslBufVarPtr, 1); // Clear ACPI RTC status + if (READ_IO16_PM(ACPI_IOREG_PM1_STS) & 0x400) + SET_MEM8(SbAslBufVarPtr, 1); // Set ACPI RTC status + } +#if defined BootScriptHide_SUPPORT && BootScriptHide_SUPPORT + //SCI_EN = 1 + SET_IO8_PM(ACPI_IOREG_PM1_CNTL, B_PCH_ACPI_PM1_CNT_SCI_EN); //PM1_CNT +#endif + } +#endif + // Clear Global Reset Bit + RESET_PCI32_SB(SB_REG_LPC_PMIR, B_ICH_LPC_PMIR_CF9GR); + + // Set up necessary PPI notifications after PEI permantent memory + // be installed + Status = (*PeiServices)->NotifyPpi( PeiServices, &mNotifyList[0] ); + ASSERT_PEI_ERROR ( PeiServices, Status ); + +#if defined RapidStart_SUPPORT && RapidStart_SUPPORT + if (BootMode == BOOT_ON_S4_RESUME) + if (RtcRead(FFS_NV_FLAG_REG) & BIT0) + return EFI_SUCCESS; +#endif + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ProgramSBRegBeforeEndofPei +// +// Description: This function can be used to program any SB regisater before +// end of PEI phase. +// +// Input: PeiServices - Pointer to the PEI services table +// NotifyDescriptor - Pointer to the descriptor for the +// notification event. +// InvokePpi - Pointer to the PPI that was installed +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS ProgramSBRegBeforeEndofPei ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *InvokePpi ) +{ + EFI_STATUS Status = EFI_SUCCESS; + EFI_PEI_CPU_IO_PPI *CpuIo; + IN EFI_PEI_PCI_CFG2_PPI *PciCfg; + EFI_BOOT_MODE BootMode; + + CpuIo = (*PeiServices)->CpuIo; + PciCfg = (*PeiServices)->PciCfg; + + Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode); + + if (BootMode == BOOT_ON_S3_RESUME) { + // [EIP87695]> +#if SYSTEM_REBOOT_NORMALLY_IF_S3_IS_FAILED + WRITE_IO16_PM(ACPI_IOREG_PM1_CNTL, READ_IO16_PM(ACPI_IOREG_PM1_CNTL) & 0xe3ff | (S3_SLP_TYP << 10)); // Clear S3 for avoiding S3 resume twice +#endif + // <[EIP87695] + // Porting if needed. + } else { + // Porting if needed. + } + + // Setting 8254 + // program timer 1 as refresh timer + IoWrite8(LEGACY_TIMER_CTRL,0x54); + IoWrite8(LEGACY_TIMER_1_COUNT,0x12); + +#if defined(SUPPORT_RAID_DRIVER) && SUPPORT_RAID_DRIVER && (PTT_VER > 15) + DetectSataPortInfo(PeiServices); +#endif + + return EFI_SUCCESS; +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IsRtcUipAlwaysSet +// +// Description: Check RTC Time Update In Progress. +// +// Input: PeiServices - Pointer to the PEI services table +// +// Output: Boolean +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +BOOLEAN IsRtcUipAlwaysSet( + IN EFI_PEI_SERVICES **PeiServices + ) +{ + + EFI_PEI_STALL_PPI *StallPpi; + UINTN Count; + + StallPpi = &mStallPpi; + + for (Count = 0; Count < 500; Count++) { // Maximum waiting approximates to 1.5 seconds (= 3 msec * 500) + if ((READ_IO8_RTC(RTC_NMI_MASK | RTC_REG_A_INDEX) & BIT07) == 0) { + return FALSE; + } + StallPpi->Stall (PeiServices, StallPpi, 3000); + } + + return TRUE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitRTC +// +// Description: This function initializes SB RTC related registers +// +// Input: PeiServices - Pointer to the PEI services table +// CpuIo - Pointer to the CPU I/O PPI +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID InitRTC ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo ) +{ + UINT8 Buffer8; + UINT16 Buffer16; + BOOLEAN RtcUipIsAlwaysSet; + + // + // PCH BIOS Specification 0.6.0 - Section 19.2, "Power Failure Consideration" + // + // When the RTC_PWR_STS bit is set, it indicates that the RTCRST# signal went low. + // Software should clear this bit. For example, changing the RTC battery sets this bit. + // System BIOS should reset CMOS to default values if the RTC_PWR_STS is set. + // + // The System BIOS should execute the sequence below if the RTC_PWR_STS bit is set before memory initialization. + // This will ensure that the RTC state machine has been initialized. + // 1. If the RTC_PWR_STS bit is set, which indicates a new coin-cell batttery + // insertion or a battery failure, steps 2 through 5 should be executed. + // 2. Set RTC Register 0Ah[6:4] to '110b' or '111b'. + // 3. Set RTC Register 0Bh[7]. + // 4. Set RTC Register 0Ah[6:4] to '010b'. + // 5. Clear RTC Register 0Bh[7]. + Buffer16 = READ_PCI16_SB(R_PCH_LPC_GEN_PMCON_3); // 0xA4 + RtcUipIsAlwaysSet = IsRtcUipAlwaysSet(PeiServices); + if ((Buffer16 & B_PCH_LPC_GEN_PMCON_RTC_PWR_STS) || RtcUipIsAlwaysSet) { + + // + // Step 1. + // BIOS clears this bit by writing a '0' to it. + // + if (Buffer16 & B_PCH_LPC_GEN_PMCON_RTC_PWR_STS) { + Buffer16 &= ~B_PCH_LPC_GEN_PMCON_RTC_PWR_STS; + WRITE_PCI16_SB(R_PCH_LPC_GEN_PMCON_3, Buffer16); + WRITE_IO8_RTC((RTC_NMI_MASK | RTC_DAY_OF_MONTH_REG), 0xFF); + WRITE_IO8_RTC((RTC_NMI_MASK | RTC_HOURS_REG), 0xFF); + } + + // + // Step 2. + // Set RTC Register 0Ah[6:4] to '110' or '111'. + // + WRITE_IO8_RTC((RTC_NMI_MASK | RTC_REG_A_INDEX), 0x66); + + // + // Step 3. + // Set RTC Register 0Bh[7]. + // + Buffer8 = (READ_IO8_RTC(RTC_NMI_MASK | RTC_REG_B_INDEX) | 0x80); + WRITE_IO8_RTC((RTC_NMI_MASK | RTC_REG_B_INDEX), Buffer8); + + // + // Step 4. + // Set RTC Register 0Ah[6:4] to '010'. + // + WRITE_IO8_RTC((RTC_NMI_MASK | RTC_REG_A_INDEX), 0x26); + + // + // Step 5. + // Clear RTC Register 0Bh[7]. + // + Buffer8 = (READ_IO8_RTC(RTC_NMI_MASK | RTC_REG_B_INDEX) & ~0x80); + WRITE_IO8_RTC((RTC_NMI_MASK | RTC_REG_B_INDEX), Buffer8); + } + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitPMRegs +// +// Description: This function initializes SB Power Management registers. +// +// Input: PeiServices - Pointer to the PEI services table +// CpuIo - Pointer to the CPU I/O PPI +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID InitPMRegs ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo, + IN SB_SETUP_DATA *SbSetupData) +{ + EFI_STATUS Status = EFI_SUCCESS; + EFI_BOOT_MODE BootMode = 0; + PCH_SERIES PchSeries = GetPchSeries(); + + Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode); + if (BootMode != BOOT_ON_S3_RESUME) { + WRITE_IO16_PM(ACPI_IOREG_PM1_EN, 0); + } + if (PchSeries == PchLp) { + WRITE_IO32_PM(ACPI_PCHLP_IOREG_GPE0_EN+0x0c, 0); + } else { + WRITE_IO32_PM(ACPI_IOREG_GPE0_EN, 0); + WRITE_IO32_PM(ACPI_IOREG_GPE0_EN + 4, 0); + } + + // Clear Alternate GPI SMI Status Reg. + if (PchSeries == PchLp) { + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_ALTGP_SMI_STS, 0xFFFFFFFF); + } else { + WRITE_IO16_PM(ACPI_IOREG_ALTGP_SMI_STS, 0xFFFF); + } + +#if EHCI_CON_DISCON_WAKE_UP_SUPPORT + if (SbSetupData->EhciConDisConWakeUp) + RESET_MEM8_RCRB(RCRB_MMIO_RMHWKCTL , 0xFF); + else + SET_MEM8_RCRB(RCRB_MMIO_RMHWKCTL , (BIT00 | BIT01 | BIT04 | BIT05)); +#endif + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ProgramRCRBMmio +// +// Description: This function initializes SB Root Complex registers +// +// Input: PeiServices - Pointer to the PEI services table +// CpuIo - Pointer to the CPU I/O PPI +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID ProgramRCRBMmio ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo ) +{ + PCH_SERIES PchSeries = GetPchSeries(); + + //Enable IOAPIC Decoding and FERR# + if(PchSeries == PchLp){ + SET_MEM16_RCRB(R_PCH_RCRB_OIC, B_PCH_RCRB_OIC_AEN); + } else { + SET_MEM16_RCRB(R_PCH_RCRB_OIC, (B_PCH_RCRB_OIC_AEN | (PCH_RCRB_OIC_CEN << 9))); + } + + // Enable No Reboot, Boot BIOS Destination + SET_MEM32_RCRB(R_PCH_RCRB_GCS, (BIT06 | B_PCH_RCRB_GCS_NR)); + + SET_MEM32_RCRB (R_PCH_RCRB_FD2, BIT00); //0x3428 + + // PIRQ routing Info + // Device 31 Interrupt Pin, reg#3100h + WRITE_MEM32_RCRB(R_PCH_RCRB_D31IP, (RCRB_IRQB << 8) + + (RCRB_IRQC << 12) + + (RCRB_IRQD << 16) + + (RCRB_IRQB << 20) + + (RCRB_IRQC << 24)); + + // Device 30 Interrupt Pin, reg#3104h - Read Only + + // Device 29 Interrupt Pin, reg#3108h + WRITE_MEM32_RCRB(R_PCH_RCRB_D29IP, (RCRB_IRQA << 0) + + (RCRB_IRQB << 4) + + (RCRB_IRQC << 8) + + (RCRB_IRQD << 12) + + (RCRB_IRQA << 16)); + + // Device 28 Interrupt Pin, reg#310Ch + WRITE_MEM32_RCRB(R_PCH_RCRB_D28IP, (RCRB_IRQA << 0) + + (RCRB_IRQB << 4) + + (RCRB_IRQC << 8) + + (RCRB_IRQD << 12) + + (RCRB_IRQA << 16) + + (RCRB_IRQB << 20) + + (RCRB_IRQC << 24) + + (RCRB_IRQD << 28)); + + // Device 27 Interrupt Pin, reg#3110h + WRITE_MEM32_RCRB(R_PCH_RCRB_D27IP, (RCRB_IRQA << 0)); + + // Device 26 Interrupt Pin, reg#3114h + WRITE_MEM32_RCRB(R_PCH_RCRB_D26IP, (RCRB_IRQA << 0) + + (RCRB_IRQB << 4) + + (RCRB_IRQC << 8) + + (RCRB_IRQD << 12)); + + // Device 25 Interrupt Pin, reg#3118h + WRITE_MEM32_RCRB(R_PCH_RCRB_D25IP, (RCRB_IRQA << 0)); + + // Device 22 Interrupt Pin, reg#3124h + WRITE_MEM16_RCRB(R_PCH_RCRB_D22IP, (RCRB_IRQA << 0) + + (RCRB_IRQB << 4) + + (RCRB_IRQC << 8) + + (RCRB_IRQB << 12)); + + // Device 20 Interrupt Pin, reg#3128h + WRITE_MEM32_RCRB(R_PCH_RCRB_D20IP, (RCRB_IRQA << 0)); + + // Device 31 Interrupt Route, reg#3140h + WRITE_MEM16_RCRB(R_PCH_RCRB_D31IR, (RCRB_PIRQD << 4) + + (RCRB_PIRQC << 8) + + (RCRB_PIRQA << 12)); + + // Device 29 Interrupt Route, reg#3144h + WRITE_MEM16_RCRB(R_PCH_RCRB_D29IR, (RCRB_PIRQH << 0) + + (RCRB_PIRQD << 4) + + (RCRB_PIRQA << 8) + + (RCRB_PIRQC << 12)); + + // Device 28 Interrupt Route, reg#3146h + WRITE_MEM16_RCRB(R_PCH_RCRB_D28IR, (RCRB_PIRQA << 0) + + (RCRB_PIRQB << 4) + + (RCRB_PIRQC << 8) + + (RCRB_PIRQD << 12)); + + // Device 27 Interrupt Route, reg#3148h + WRITE_MEM16_RCRB(R_PCH_RCRB_D27IR, (RCRB_PIRQG << 0) + + (RCRB_PIRQB << 4) + + (RCRB_PIRQC << 8) + + (RCRB_PIRQD << 12)); + + // Device 26 Interrupt Route, reg#314Ch + WRITE_MEM16_RCRB(R_PCH_RCRB_D26IR, (RCRB_PIRQA << 0) + + (RCRB_PIRQF << 4) + + (RCRB_PIRQC << 8) + + (RCRB_PIRQD << 12)); + + // Device 25 Interrupt Route, reg#3150h + WRITE_MEM16_RCRB(R_PCH_RCRB_D25IR, (RCRB_PIRQE << 0) + + (RCRB_PIRQF << 4) + + (RCRB_PIRQG << 8) + + (RCRB_PIRQH << 12)); + + if (PchSeries == PchLp) { + // Device 23 Interrupt Route, reg#3158h + WRITE_MEM16_RCRB(R_PCH_RCRB_D23IR, (RCRB_PIRQG << 0)); + } + + // Device 22 Interrupt Route, reg#315Ch + WRITE_MEM16_RCRB(R_PCH_RCRB_D22IR, (RCRB_PIRQA << 0) + + (RCRB_PIRQD << 4) + + (RCRB_PIRQC << 8) + + (RCRB_PIRQB << 12)); + + if (PchSeries == PchLp) { + // Device 21 Interrupt Route, reg#3164h + WRITE_MEM16_RCRB(R_PCH_RCRB_D21IR, (RCRB_PIRQE << 0) + + (RCRB_PIRQE << 4) + + (RCRB_PIRQF << 8) + + (RCRB_PIRQF << 12)); + } + + // Device 20 Interrupt Route, reg#3160h + WRITE_MEM16_RCRB(R_PCH_RCRB_D20IR, (RCRB_PIRQA << 0) + + (RCRB_PIRQB << 4) + + (RCRB_PIRQC << 8) + + (RCRB_PIRQD << 12)); + + if (PchSeries == PchLp) { + // Device 19 Interrupt Route, reg#3168h + WRITE_MEM16_RCRB(R_PCH_RCRB_D19IR, (RCRB_PIRQH << 0)); + } + + // EIP176923 + #if defined DISABLE_DAYLIGHT_SAVINGS && DISABLE_DAYLIGHT_SAVINGS == 1 + SET_MEM16_RCRB(R_PCH_RCRB_BUC, B_PCH_RCRB_BUC_SDO); + #endif +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ProgramSBIoDecodeRegs +// +// Description: This function initializes SB IO Decide Registers. +// +// Input: PeiServices - Pointer to the PEI services table +// PciCfg - Pointer to the PCI Configuration PPI +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +ProgramSBIoDecodeRegs ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg +) +{ + +#if defined EMUL6064_SUPPORT && EMUL6064_SUPPORT == 1 + // Force KBC_LPC_EN bit (B0:D31:F0 Reg 82h[10]) = 1 if EMUL6064_SUPPORT = 1. + SbLib_SetLpcDeviceDecoding(NULL, 0x60, 0, dsPS2K); +#endif + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ProgramPchDeviceBase +// +// Description: This function initializes SB Devices Base +// +// Input: PeiServices - Pointer to the PEI services table +// PciCfg - Pointer to the PCI Configuration PPI +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +ProgramPchDeviceBase ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg +) +{ + + // Program RCBA Base + WRITE_PCI32_SB(SB_REG_RCBA, SB_RCRB_BASE_ADDRESS | 1);//0xF0 + + // Write Heci Base Address and enable Heci device + WRITE_PCI32_HECI(ME_REG_HECI_MBAR, HECI_BASE_ADDRESS); + WRITE_PCI16_HECI(ME_REG_PCICMD, 0x06); + + // Write Heci Base Address and enable Heci device + WRITE_PCI32_HECI2(ME_REG_HECI_MBAR, HECI2_BASE_ADDRESS); + WRITE_PCI16_HECI2(ME_REG_PCICMD, 0x06); + + // Program PM Base + WRITE_PCI16_SB(SB_REG_PMBASE, PM_BASE_ADDRESS); + WRITE_PCI8_SB(SB_REG_ACPI_CNTL, 0x80); + + // Program GPIO Base + WRITE_PCI16_SB(SB_REG_GPIOBASE, GPIO_BASE_ADDRESS); + WRITE_PCI8_SB(SB_REG_GC, 0x10); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GeneralPowerFailureHandler +// +// Description: When the PWR_FLR bit is set, it indicates the trickle power +// from the main battery or tricle supply failed while in suspend +// or since last boot. This bit us ub the RTC well and is cleared +// only by RTCRST#. Software writes a "1" to clear this bit. +// System BIUOS should follow cold boot path if PWR_FLR, GEN_RST_STS +// or PWRBTNOR_STS is set to 1 regardless of the value in the SLP_TYP +// field. +// +// Input: PeiServices - Pointer to the PEI services table +// CpuIo - Pointer to the CPU I/O PPI +// PciCfg - Pointer to the PCI Configuration PPI +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +GeneralPowerFailureHandler ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg +) +{ + + UINT16 DataUint16; + UINT8 DataUint8; + + // + // PCH BIOS Specification 0.6.0 - Section 19.2, "Power Failure Considerations" + // + // When the PWR_FLR bit is set, it indicates the trickle power from the main + // battery or tricle supply failed while in suspend or since last boot. + // System BIOS should follow cold boot path if PWR_FLR, GEN_RST_STS or + // PWRBTNOR_STS is set to 1 regardless of the value in the SLP_TYP field. + // + DataUint16 = READ_PCI16_SB(R_PCH_LPC_GEN_PMCON_3); + if ((DataUint16 & (B_PCH_LPC_GEN_PMCON_GEN_RST_STS | B_PCH_LPC_GEN_PMCON_PWR_FLR)) || \ + (READ_IO16_PM(R_PCH_ACPI_PM1_STS) & B_PCH_ACPI_PM1_STS_PRBTNOR)) { + // + // BIOS clears these bits by writing a '1' to them. + // + WRITE_PCI16_SB(R_PCH_LPC_GEN_PMCON_3, DataUint16); + WRITE_IO16_PM(R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_PRBTNOR); + + // + // Clear Wake Status (WAK_STS) and Sleep Type (SLP_TYP) + // + WRITE_IO16_PM(ACPI_IOREG_PM1_STS, B_PCH_ACPI_PM1_STS_WAK); + DataUint16 = (READ_IO16_PM(ACPI_IOREG_PM1_CNTL) & ~B_PCH_ACPI_PM1_CNT_SLP_TYP); + WRITE_IO16_PM(ACPI_IOREG_PM1_CNTL, DataUint16); + } + + // + // When the CPUPWR_FLR bit is set, it indicates VRMPWRGD signal from + // the CPU VRM went low. This bit is now set if VRMPWRGD goes low + // during Intel (R) SpeedStep Technology transition. + // Software must clear this bit if set. + // + DataUint8 = READ_PCI8_SB(R_PCH_LPC_GEN_PMCON_2); + if (DataUint8 & B_PCH_LPC_GEN_PMCON_SYSPWR_FLR) { + // + // BIOS clears this bit by writing a '0' to it. + // + DataUint8 &= ~B_PCH_LPC_GEN_PMCON_SYSPWR_FLR; + WRITE_PCI8_SB(R_PCH_LPC_GEN_PMCON_2, DataUint8); + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SetTheStateToGoAfterG3 +// +// Description: Set what state (S0/S5) to go to when power is re-applied +// after a power failure (G3 state) +// +// Input: PeiServices - Pointer to the PEI services table +// CpuIo - Pointer to the CPU I/O PPI +// PciCfg - Pointer to the PCI Configuration PPI +// SbSetupData - Pointer to the SbSetupData +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +SetTheStateToGoAfterG3 ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_CPU_IO_PPI *CpuIo, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg, + IN SB_SETUP_DATA *SbSetupData +) +{ + UINT16 DataUint16; + // + // Make sure we have a setup data, if not, just return. + // + if (SbSetupData == NULL) { + return EFI_UNSUPPORTED; + } + + DataUint16 = READ_PCI16_SB(R_PCH_LPC_GEN_PMCON_3); + if(SbSetupData->LastState == 0) { + DataUint16 |= B_PCH_LPC_GEN_PMCON_AFTERG3_EN; + } else { + DataUint16 &= ~B_PCH_LPC_GEN_PMCON_AFTERG3_EN; + } + +// Done in PchMisc.c +//#### DataUint16 |= (SbSetupData->SlpS4AssW << 4); + + WRITE_PCI16_SB(R_PCH_LPC_GEN_PMCON_3, DataUint16); + + return EFI_SUCCESS; +} + +static UINT8 mSmbusRsvdAddresses[DIMM_SLOT_NUM] = { + DIMM1_SMBUS_ADDRESS, + DIMM2_SMBUS_ADDRESS, + DIMM3_SMBUS_ADDRESS, + DIMM4_SMBUS_ADDRESS +}; + +static PEI_SMBUS_POLICY_PPI mSmbusPolicyPpi = { + SMBUS_BASE_ADDRESS, + SMBUS_BUS_DEV_FUN, + DIMM_SLOT_NUM, + mSmbusRsvdAddresses +}; + +EFI_PEI_PPI_DESCRIPTOR SmbusPolicy_PpiDescriptor = { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gPeiSmbusPolicyPpiGuid, + &mSmbusPolicyPpi +}; + // [EIP106687]> +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbPcieDetectNonComplaintPcieDevice +// +// Description: +// +// Input: IN UINT8 Index, +// IN PCH_PCIE_CONFIG *PcieConfig +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +SbPcieDetectNonComplaintPcieDevice ( + IN EFI_PEI_SERVICES **PeiServices, + IN UINT8 Index, + IN PCH_PCIE_CONFIG *PcieConfig, + IN SB_SETUP_DATA *SbSetupData +) +{ + if ((PcieConfig->PcieSpeed[Index] == PchPcieAuto) && \ + (SbSetupData->PcieRootPortEn[Index]!= 0)) + { + PEI_TRACE((-1,PeiServices, "Enhance Detect Non-Compliance PCIE Device @B:0|D:1C|F:%x Start .\n", Index)); + // Assign temp bus + PEI_TRACE((-1,PeiServices, "Assign temp bus ...\n")); + WRITE_PCI16(PCIEBRS_BUS, PCIEBRS_DEV, Index, R_PCH_PCIE_BNUM+1, 0x0101); + // Do a dummy Write + WRITE_PCI32(1, 0, 0, PCI_VID, 0x12345678); + + if (READ_PCI16(1, 0, 0, PCI_VID) == 0xFFFF) { + PEI_TRACE((-1,PeiServices, "Can't find Device... Retrain device first.\n")); + WRITE_PCI8(PCIEBRS_BUS, PCIEBRS_DEV, Index, R_PCH_PCIE_LCTL, B_PCH_PCIE_LCTL_LD); + CountTime((RETRAIN_DELAY * 10), PM_BASE_ADDRESS); //delay 500us + WRITE_PCI8(PCIEBRS_BUS, PCIEBRS_DEV, Index, R_PCH_PCIE_LCTL, B_PCH_PCIE_LCTL_RL); + CountTime((RETRAIN_DELAY * 8000), PM_BASE_ADDRESS); //delay 400ms + if (READ_PCI16(1, 0, 0, PCI_VID) == 0xFFFF) { + PEI_TRACE((-1,PeiServices, "Still can't find Device in Gen2 Speed... Speed is setted in Gen1 and delay 200 ms.\n")); + // Set Speed to Gen1 + RW_PCI8(PCIEBRS_BUS, PCIEBRS_DEV, Index, R_PCH_PCIE_LCTL2, 0x01, 0x03); + CountTime((RETRAIN_DELAY * 4000), PM_BASE_ADDRESS); //delay 200ms + + if (READ_PCI16(1, 0, 0, PCI_VID) == 0xFFFF) { + PEI_TRACE((-1,PeiServices, "Still can't find Device in Gen1 Speed... Retrain device again !!!\n")); + WRITE_PCI8(PCIEBRS_BUS, PCIEBRS_DEV, Index, R_PCH_PCIE_LCTL, B_PCH_PCIE_LCTL_LD); + CountTime((RETRAIN_DELAY * 10), PM_BASE_ADDRESS); //delay 500us + WRITE_PCI8(PCIEBRS_BUS, PCIEBRS_DEV, Index, R_PCH_PCIE_LCTL, B_PCH_PCIE_LCTL_RL); + CountTime((RETRAIN_DELAY * 8000), PM_BASE_ADDRESS); //delay 400ms + + if (READ_PCI16(1, 0, 0, PCI_VID) != 0xFFFF) PcieConfig->PcieSpeed[Index] = PchPcieGen1; + } + else PcieConfig->PcieSpeed[Index] = PchPcieGen1; + } + } + + // Remove temp bus + PEI_TRACE((-1,PeiServices, "Remove temp bus.\n")); + WRITE_PCI32(PCIEBRS_BUS, PCIEBRS_DEV, Index, PCI_PBUS, 0xFF000000); + + PEI_TRACE((-1,PeiServices, "Enhance Detect Non-Compliance PCIE Device end.\n")); + } +} + // <[EIP106687] +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InstallPchPlatformPolicyPpi +// +// Description: Install Pch Platform Policy Ppi +// +// Input: IN EFI_PEI_SERVICES **PeiServices, +// IN SB_SETUP_DATA *SbSetupData +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +InstallPchPlatformPolicyPpi ( + IN EFI_PEI_SERVICES **PeiServices, + IN SB_SETUP_DATA *SbSetupData +) +{ + + UINT8 *SbRcba = (UINT8*)(UINTN)SB_RCRB_BASE_ADDRESS; + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *PchPlatformPolicyPpiDesc; + PCH_PLATFORM_POLICY_PPI *PchPlatformPolicyPpi; + PCH_THERMAL_MANAGEMENT *ThermalMgmt; + PCH_MEMORY_THROTTLING *MemoryThrottling; + PCH_HPET_CONFIG *HpetConfig; + PCH_IOAPIC_CONFIG *IoApicConfig; + PCH_SATA_CONTROL *SataConfig; + PCH_SATA_TRACE_CONFIG *SataTraceConfig; + PCH_GBE_CONFIG *GbeConfig; + PCH_PCIE_CONFIG *PcieConfig; + PCH_USB_CONFIG *UsbConfig; + EFI_BOOT_MODE BootMode; + UINT8 Index; + PCH_PLATFORM_DATA *PlatformData; + UINT16 LpcDeviceId = READ_PCI16_SB(R_PCH_LPC_DEVICE_ID); + UINT16 Data16; + UINT8 PortIndex; + UINT16 UsbPortLength[LPTH_USB_MAX_PHYSICAL_PORTS] = {USB_PORTS_LENGTH}; + UINT8 UsbPortLocation[LPTH_USB_MAX_PHYSICAL_PORTS] = {USB_PORT_LOCATION_CONFIG}; + UINT8 UsbOverCurrentMapping[LPTH_USB_MAX_PHYSICAL_PORTS] = {USB_OVER_CURRENT_MAPPING_SETTINGS}; + UINT8 Usb30OverCurrentMapping[LPTH_XHCI_MAX_USB3_PORTS] = {USB30_OVER_CURRENT_MAPPING_SETTINGS}; + PCH_SERIES PchSeries = GetPchSeries(); + SATA_LENGTH_CONFIG SataLengthConfigTable[] = {SATA_PORT1_LENGTH_CONFIG, + SATA_PORT2_LENGTH_CONFIG, + SATA_PORT3_LENGTH_CONFIG, + SATA_PORT4_LENGTH_CONFIG, + SATA_PORT5_LENGTH_CONFIG, + SATA_PORT6_LENGTH_CONFIG}; +#if defined iME_SUPPORT && iME_SUPPORT + EFI_PEI_READ_ONLY_VARIABLE2_PPI *ReadOnlyVariable; + UINTN VariableSize; + ME_BIOS_EXTENSION_SETUP MeBiosExtensionSetupData; + EFI_GUID EfiMeBiosExtensionSetupGuid = EFI_ME_BIOS_EXTENSION_SETUP_GUID; + CHAR16 EfiMeBiosExtensionSetupName[] = EFI_ME_BIOS_EXTENSION_SETUP_VARIABLE_NAME; +#endif + + BootMode = BOOT_WITH_FULL_CONFIGURATION; + + // Install SmbusPolicy PPI + Status = (**PeiServices).InstallPpi (PeiServices, &SmbusPolicy_PpiDescriptor); + ASSERT_PEI_ERROR (PeiServices, Status); + + // Allocate descriptor and PPI structures. Since these are dynamically updated + // we cannot do a global variable PPI. + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (EFI_PEI_PPI_DESCRIPTOR), &PchPlatformPolicyPpiDesc); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) PchPlatformPolicyPpiDesc, sizeof (EFI_PEI_PPI_DESCRIPTOR), 0); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_PLATFORM_POLICY_PPI), &PchPlatformPolicyPpi); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) PchPlatformPolicyPpi, sizeof (PCH_PLATFORM_POLICY_PPI), 0); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_HPET_CONFIG), &HpetConfig); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) HpetConfig, sizeof (PCH_HPET_CONFIG), 0); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_THERMAL_MANAGEMENT), &ThermalMgmt); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) ThermalMgmt, sizeof (PCH_THERMAL_MANAGEMENT), 0); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_IOAPIC_CONFIG), &IoApicConfig); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) IoApicConfig, sizeof (PCH_IOAPIC_CONFIG), 0); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_MEMORY_THROTTLING), &MemoryThrottling); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) MemoryThrottling, sizeof (PCH_MEMORY_THROTTLING), 0); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_SATA_CONTROL), &SataConfig); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) SataConfig, sizeof (PCH_SATA_CONTROL), 0); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_SATA_TRACE_CONFIG), &SataTraceConfig); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) SataTraceConfig, sizeof (PCH_SATA_TRACE_CONFIG), 0); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_GBE_CONFIG), &GbeConfig); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) GbeConfig, sizeof (PCH_GBE_CONFIG), 0); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_PCIE_CONFIG), &PcieConfig); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) PcieConfig, sizeof (PCH_PCIE_CONFIG), 0); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_PLATFORM_DATA), &PlatformData); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) PlatformData, sizeof (PCH_PLATFORM_DATA), 0); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_USB_CONFIG), &UsbConfig); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) UsbConfig, sizeof (PCH_USB_CONFIG), 0); + + PchPlatformPolicyPpi->Revision = PCH_PLATFORM_POLICY_PPI_REVISION_4; + PchPlatformPolicyPpi->BusNumber = 0; + PchPlatformPolicyPpi->Rcba = SB_RCRB_BASE_ADDRESS; + PchPlatformPolicyPpi->PmBase = PM_BASE_ADDRESS; + PchPlatformPolicyPpi->GpioBase = GPIO_BASE_ADDRESS; + PchPlatformPolicyPpi->Port80Route = RESERVED_PAGE_ROUTE; + + PchPlatformPolicyPpi->GbeConfig = GbeConfig; + PchPlatformPolicyPpi->ThermalMgmt = ThermalMgmt; + PchPlatformPolicyPpi->HpetConfig = HpetConfig; + PchPlatformPolicyPpi->SataConfig = SataConfig; + PchPlatformPolicyPpi->PcieConfig = PcieConfig; + PchPlatformPolicyPpi->IoApicConfig = IoApicConfig; + PchPlatformPolicyPpi->PlatformData = PlatformData; + PchPlatformPolicyPpi->UsbConfig = UsbConfig; + +//- ThermalMgmt->ThermalBaseB = SB_THERMAL_BASE_ADDRESS; + ThermalMgmt->MemoryThrottling = MemoryThrottling; + + GbeConfig->EnableGbe = 1; +//- GbeConfig->GbeMemBaseAddr = 0xFFFF8000; //PCH_LAN_MBARB_BASE_ADDRESS; + + for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) + PcieConfig->PcieSpeed[Index] = PchPcieAuto; + + HpetConfig->Enable = PCH_DEVICE_ENABLE; + HpetConfig->Base = HPET_BASE_ADDRESS; + + + IoApicConfig->IoApicId = PCH_IO_APIC_ID; + IoApicConfig->ApicRangeSelect = PCH_APIC_RANGE_SELECT; + IoApicConfig->IoApicEntry24_39 = PCH_DEVICE_ENABLE; + + if(SbSetupData != NULL) { + GbeConfig->EnableGbe = SbSetupData->PchLan; + + if ((READ_MEM16_RCRB(R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FDV) == B_PCH_SPI_HSFS_FDV) { + RESET_MEM32_RCRB(R_PCH_SPI_FDOC, (UINT32) (B_PCH_SPI_FDOC_FDSS_MASK | B_PCH_SPI_FDOC_FDSI_MASK)); + SET_MEM32_RCRB(R_PCH_SPI_FDOC, (UINT32) (V_PCH_SPI_FDOC_FDSS_PCHS | R_PCH_SPI_STRP9)); + if ((READ_MEM32_RCRB (R_PCH_SPI_FDOD) & B_PCH_SPI_STRP9_GBE_PCIE_EN) == 0) { + GbeConfig->EnableGbe = PCH_DEVICE_DISABLE; + } + } + + PchPlatformPolicyPpi->Port80Route = SbSetupData->Port80Route; // 0 - Forward to LPC. 1 - Forward to PCI. + SataConfig->SataMode = SbSetupData->SataInterfaceMode; + SataConfig->SataTraceConfig = SataTraceConfig; +// HpetConfig->Enable = SbSetupData->Hpet; // Force HPET enabled for MRC initialization. + // [EIP106687]> + for (Index = 0; Index < GetPchMaxPciePortNum (); Index++){ + PcieConfig->PcieSpeed[Index] = SbSetupData->PcieRootPortSpeed[Index]; + + //Enhance Detect Non-Compliance PCIE Device + if ((SbSetupData->PcieRPDetectNonComplaint[Index] == 1) && (SbSetupData->PcieRootPortEn[0]!= 0)) + SbPcieDetectNonComplaintPcieDevice(PeiServices, Index, PcieConfig, SbSetupData); + } + // <[EIP106687] + //In case of recovery change the SATA mode to IDE + (*PeiServices)->GetBootMode (PeiServices, &BootMode); + if(BootMode == BOOT_IN_RECOVERY_MODE) { + SataConfig->SataMode = PchSataModeIde; + } + + SataTraceConfig->TestMode = PCH_DEVICE_DISABLE; + PEI_TRACE((-1,PeiServices, "SBPei SATA RxEq Policy setting:\n")); + for( PortIndex = 0; PortIndex < GetPchMaxSataPortNum(); PortIndex++ ) { + SataTraceConfig->PortRxEq[PortIndex].GenSpeed[0].Enable = SataLengthConfigTable[PortIndex].SataGen1RxEqEnable; + SataTraceConfig->PortRxEq[PortIndex].GenSpeed[1].Enable = SataLengthConfigTable[PortIndex].SataGen2RxEqEnable; + SataTraceConfig->PortRxEq[PortIndex].GenSpeed[2].Enable = SataLengthConfigTable[PortIndex].SataGen3RxEqEnable; + SataTraceConfig->PortRxEq[PortIndex].GenSpeed[0].RxEq = SataLengthConfigTable[PortIndex].SataGen1RxEqValue; + SataTraceConfig->PortRxEq[PortIndex].GenSpeed[1].RxEq = SataLengthConfigTable[PortIndex].SataGen2RxEqValue; + SataTraceConfig->PortRxEq[PortIndex].GenSpeed[2].RxEq = SataLengthConfigTable[PortIndex].SataGen3RxEqValue; + PEI_TRACE((-1,PeiServices, "SATA Port%x: %x %x %x %x %x %x\n", PortIndex,\ + SataLengthConfigTable[PortIndex].SataGen1RxEqEnable, SataLengthConfigTable[PortIndex].SataGen1RxEqValue,\ + SataLengthConfigTable[PortIndex].SataGen2RxEqEnable, SataLengthConfigTable[PortIndex].SataGen2RxEqValue,\ + SataLengthConfigTable[PortIndex].SataGen3RxEqEnable, SataLengthConfigTable[PortIndex].SataGen3RxEqValue)); + } + // + // Thermal configuration - Initialize policy to SETUP values. + // +#if defined iME_SUPPORT && iME_SUPPORT + MemoryThrottling->Enable = SbSetupData->TrEnabled; +#else + MemoryThrottling->Enable = PCH_DEVICE_DISABLE; +#endif + MemoryThrottling->TsGpioPinSetting[TsGpioC].PmsyncEnable = TSGPIO_C_PMSYN; + MemoryThrottling->TsGpioPinSetting[TsGpioD].PmsyncEnable = TSGPIO_D_PMSYN; + MemoryThrottling->TsGpioPinSetting[TsGpioC].C0TransmitEnable = TSGPIO_C_C0_TRANSMIT; + MemoryThrottling->TsGpioPinSetting[TsGpioD].C0TransmitEnable = TSGPIO_D_C0_TRANSMIT; + MemoryThrottling->TsGpioPinSetting[TsGpioC].PinSelection = TSGPIO_C_PIN_SEL; + MemoryThrottling->TsGpioPinSetting[TsGpioD].PinSelection = TSGPIO_D_PIN_SEL; + /// + /// UsbConfig should be initialized based on platform configuration if UsbPrecondition feature is + /// enabled. Otherwise, the remaining data of UsbConfig can stay in zero. + /// + UsbConfig->UsbPrecondition = SbSetupData->UsbPrecondition; +#ifdef RAPID_START_FLAG + if (RapidStartResumeCheck () == TRUE) { + /// + /// This is RapidStart resume, skip the UsbPrecondition feature in PEI phase + /// + UsbConfig->UsbPrecondition = 0; + } +#endif + +#ifdef USB_PRECONDITION_ENABLE_FLAG + /// + /// Update Precondition option for S4 resume. + /// Skip Precondition for S4 resume in case this boot may not connect BIOS USB driver. + /// If BIOS USB driver will be connected always for S4, then disable below update. + /// To keep consistency during boot, must enabled or disabled below function in both PEI and DXE + /// PlatformPolicyInit driver. + /// + if (UsbConfig->UsbPrecondition == TRUE) { + (*PeiServices)->GetBootMode (PeiServices, &BootMode); + if ((BootMode == BOOT_ON_S4_RESUME) || (BootMode == BOOT_IN_RECOVERY_MODE)){ + UsbConfig->UsbPrecondition = FALSE; + PEI_TRACE((-1,PeiServices, "BootMode is BOOT_ON_S4_RESUME or BOOT_IN_RECOVERY_MODE, disable Precondition")); + } + } +#endif // USB_PRECONDITION_ENABLE_FLAG + + if (UsbConfig->UsbPrecondition) { +#if defined iAMT_SUPPORT && iAMT_SUPPORT + UsbConfig->Ehci1Usbr = PCH_DEVICE_DISABLE; + UsbConfig->Ehci2Usbr = PCH_DEVICE_DISABLE; +#else + UsbConfig->Ehci1Usbr = PCH_DEVICE_DISABLE; + UsbConfig->Ehci2Usbr = PCH_DEVICE_DISABLE; +#endif + +#if defined iME_SUPPORT && iME_SUPPORT + Status = (*PeiServices)->LocatePpi( PeiServices, + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + &ReadOnlyVariable ); + if (ReadOnlyVariable != NULL) { + VariableSize = sizeof (MeBiosExtensionSetupData); + Status = ReadOnlyVariable->GetVariable( ReadOnlyVariable, + EfiMeBiosExtensionSetupName, + &EfiMeBiosExtensionSetupGuid, + NULL, + &VariableSize, + &MeBiosExtensionSetupData ); + if (!EFI_ERROR (Status)) { + UsbConfig->Ehci1Usbr |= (MeBiosExtensionSetupData.KvmEnable & KVM_ENABLE); + UsbConfig->Ehci2Usbr |= (MeBiosExtensionSetupData.KvmEnable & KVM_ENABLE); + } + } +#endif + + UsbConfig->Usb20Settings[0].Enable = SbSetupData->PchUsb20[0]; + if (PchSeries == PchLp) { + // [ EIP219399 ] + //UsbOverCurrentMapping[LPTH_USB_MAX_PHYSICAL_PORTS]=ULT_USB_OVER_CURRENT_MAPPING_SETTINGS; + UINT8 UltUsbOverCurrentMapping[LPTH_USB_MAX_PHYSICAL_PORTS] = {ULT_USB_OVER_CURRENT_MAPPING_SETTINGS}; + (*PeiServices)->CopyMem(UsbOverCurrentMapping, UltUsbOverCurrentMapping, LPTH_USB_MAX_PHYSICAL_PORTS); + + UsbConfig->Usb20Settings[1].Enable = PCH_DEVICE_DISABLE; + } else { + UsbConfig->Usb20Settings[1].Enable = SbSetupData->PchUsb20[1]; + } + + if ((UsbConfig->Usb20Settings[0].Enable == PCH_DEVICE_DISABLE) && + (UsbConfig->Usb20Settings[1].Enable == PCH_DEVICE_DISABLE)) { + UsbConfig->Usb20Settings[0].Enable = PCH_DEVICE_ENABLE; + if (PchSeries == PchLp) { + UsbConfig->Usb20Settings[1].Enable = PCH_DEVICE_ENABLE; + } + } + + UsbConfig->UsbPerPortCtl = SbSetupData->PchUsbPerPortCtl; + + for (PortIndex = 0; PortIndex < GetPchUsbMaxPhysicalPortNum (); PortIndex++) { + if (SbSetupData->PchUsbPerPortCtl != PCH_DEVICE_DISABLE) { + UsbConfig->PortSettings[PortIndex].Enable = SbSetupData->PchUsbPort[PortIndex]; + } else { + UsbConfig->PortSettings[PortIndex].Enable = PCH_DEVICE_ENABLE; + } + + UsbConfig->Usb20OverCurrentPins[PortIndex] = UsbOverCurrentMapping[PortIndex]; + UsbConfig->PortSettings[PortIndex].Usb20PortLength = UsbPortLength[PortIndex]; + UsbConfig->PortSettings[PortIndex].Location = UsbPortLocation[PortIndex]; + + if (PchSeries == PchH) { + if (IS_PCH_LPT_LPC_DEVICE_ID_DESKTOP (LpcDeviceId)) { + if (UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationBackPanel) { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 4; //Back Panel + } else { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 3; //Front Panel + } + + if (UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationBackPanel) { + if (UsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x80) { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Back Panel, less than 7.9" + } else if (UsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x130) { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 3; //Back Panel, 8"-12.9" + } else { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 4; //Back Panel, 13" onward + } + } else { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Front Panel + } + } else if (IS_PCH_LPT_LPC_DEVICE_ID_MOBILE (LpcDeviceId)) { + if (UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationInternalTopology) { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 5; // Internal Topology + } else if (UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationDock) { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 4; // Dock + } else { + if (UsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x70) { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 5; //Back Panel, less than 7" + } else { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 6; //Back Panel, 7" onward + } + } + + if (UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationInternalTopology) { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; // Internal Topology + } else if (UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationDock) { + if (UsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x50) { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 1; //Dock, less than 5" + } else { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Dock, 5" onward + } + } else { + if (UsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x100) { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Back Panel, less than 10" + } else { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 3; //Back Panel, 10" onward + } + } + } + } else if (PchSeries == PchLp) { + if ((UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationBackPanel) || + (UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationMiniPciE)) { + if (UsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x70) { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 5; //Back Panel, less than 7" + } else { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 6; //Back Panel, 7" onward + } + } else if (UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationDock) { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 4; // Dock + } else { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 5; // Internal Topology + } + + if ((UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationBackPanel) || + (UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationMiniPciE)) { + if (UsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x100) { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Back Panel, less than 10" + } else { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 3; //Back Panel, 10" onward + } + } else if (UsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationDock) { + if (UsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x50) { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 1; //Dock, less than 5" + } else { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Dock, 5" onward + } + } else { + UsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; // Internal Topology + } + } + } + + UsbConfig->Usb30Settings.Mode = SbSetupData->PchUsb30Mode; + + // + // Automatically disable EHCI when XHCI Mode is Enabled to save power. + // + if (UsbConfig->Usb30Settings.Mode == 1) { + UsbConfig->Usb20Settings[0].Enable = PCH_DEVICE_DISABLE; + if (PchSeries == PchH) { + UsbConfig->Usb20Settings[1].Enable = PCH_DEVICE_DISABLE; + } + } + + if (SbSetupData->PchUsb30Mode == 3) { + UsbConfig->Usb30Settings.PreBootSupport = 1; + } else { + UsbConfig->Usb30Settings.PreBootSupport = SbSetupData->PchUsb30PreBootSupport; + } + + if (SbSetupData->PchUsb30Mode == 4) { + UsbConfig->Usb30Settings.Mode = 2; + UsbConfig->Usb30Settings.ManualMode = PCH_DEVICE_ENABLE; + } else { + UsbConfig->Usb30Settings.ManualMode = PCH_DEVICE_DISABLE; + } + + // + // XhciIdleL1 can be set to disable for LPT-LP Ax stepping to workaround USB3 hot plug will fail after 1 hot plug removal. + // + UsbConfig->Usb30Settings.XhciIdleL1 = SbSetupData->PchUsb30IdleL1; + + // + // Btcg is for enabling/disabling trunk clock gating. + // + UsbConfig->Usb30Settings.Btcg = SbSetupData->PchUsb30Btcg; + + for (PortIndex = 0; PortIndex < GetPchUsbMaxPhysicalPortNum (); PortIndex++) { + if (SbSetupData->PchUsb20PinRoute == 1){ + UsbConfig->Usb30Settings.ManualModeUsb20PerPinRoute[PortIndex] = 0; + } else if (SbSetupData->PchUsb20PinRoute == 2){ + UsbConfig->Usb30Settings.ManualModeUsb20PerPinRoute[PortIndex] = 1; + } else { + UsbConfig->Usb30Settings.ManualModeUsb20PerPinRoute[PortIndex] = SbSetupData->ManualModeUsb20PerPinRoute[PortIndex]; + } + } + + for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) { + if (SbSetupData->PchUsb30PinEnable == 1){ + UsbConfig->Usb30Settings.ManualModeUsb30PerPinEnable[PortIndex] = 0; + } else if (SbSetupData->PchUsb30PinEnable == 2){ + UsbConfig->Usb30Settings.ManualModeUsb30PerPinEnable[PortIndex] = 1; + } else { + UsbConfig->Usb30Settings.ManualModeUsb30PerPinEnable[PortIndex] = SbSetupData->ManualModeUsb30PerPinEnable[PortIndex]; + } + UsbConfig->Usb30OverCurrentPins[PortIndex] = Usb30OverCurrentMapping[PortIndex]; + } + } // if (UsbConfig->UsbPrecondition) + + if (IS_PCH_LPT_LPC_DEVICE_ID_MOBILE (LpcDeviceId)) { + // Save R_PCH_LPC_ENABLES in Data16. + Data16 = READ_PCI16_SB(R_PCH_LPC_ENABLES); + + if (!(Data16 & B_PCH_LPC_ENABLES_MC_EN)) + SET_PCI16_SB(R_PCH_LPC_ENABLES, B_PCH_LPC_ENABLES_MC_EN); + + if (READ_IO8(0x66) != 0xFF) PlatformData->EcPresent = 1; + + // Restore R_PCH_LPC_ENABLES. + WRITE_PCI16_SB(R_PCH_LPC_ENABLES, Data16); + } + + } // (SbSetupData != NULL) + + /// + /// PlatformData->SmmBwp value directly depends on the value of CpuConfig->Pfat + /// (found in CpuPolicyInitPei.c file) + /// If CpuConfig->Pfat is set to 1 (enabled) then + /// PlatformData->SmmBwp has to be set to 1 (enabled) + /// This is a PFAT Security requirement that needs to be addressed + /// If CpuConfig->Pfat is set to 0 (disabled) then + /// PlatformData->SmmBwp value don't care, it can be set to either + /// 1 (enabled) or 0 (disabled) based on customer implementation + /// + PlatformData->SmmBwp = 0; + + /// + /// Temporary Memory Base Address for PCI devices to be used to initialize MMIO registers. + /// Minimum size is 64KB bytes. + /// + PlatformData->TempMemBaseAddr = SB_TEMP_MMIO_BASE; + + PchPlatformPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + PchPlatformPolicyPpiDesc->Ppi = PchPlatformPolicyPpi; + + // + // Install OEM PCH Platform Policy Override PPI + // + PchPlatformPolicyPpiDesc->Guid = &gOemPchPlatformPolicyOverridePpiGuid; + Status = (**PeiServices).InstallPpi (PeiServices, PchPlatformPolicyPpiDesc); + ASSERT_PEI_ERROR (PeiServices, Status); + + // + // Install PCH Platform Policy PPI + // + PchPlatformPolicyPpiDesc->Guid = &gPchPlatformPolicyPpiGuid; + Status = (**PeiServices).InstallPpi (PeiServices, PchPlatformPolicyPpiDesc); + ASSERT_PEI_ERROR (PeiServices, Status); + + // [EIP120438]> + if ((HpetConfig->Enable) && (HpetConfig->Base != 0)) { + WRITE_MEM32(HpetConfig->Base + 0xF0, 0); + } + // <[EIP120438] + + return EFI_SUCCESS; + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ProgramSBRegAfterMrc +// +// Description: This function can be used to program any SB regisater after +// memory is detected. +// +// Input: PeiServices - Pointer to the PEI services table +// NotifyDescriptor - Pointer to the descriptor for the +// notification event. +// InvokePpi - Pointer to the PPI that was installed +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS ProgramSBRegAfterMrc ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *InvokePpi ) +{ + EFI_STATUS Status = EFI_SUCCESS; + IN EFI_BOOT_MODE BootMode; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *ReadOnlyVariable; + UINTN VariableSize; + EFI_GUID WarmResetGuid = SB_WARM_RESET_GUID; + CHAR16 WarmResetVar[] = SB_WARM_RESET_VARIABLE; + UINT32 WarmResetFlag = 0; +#if Capsule2_0_SUPPORT + PEI_CAPSULE_PPI *Capsule; +#endif + + PEI_TRACE((-1,PeiServices, "ProgramSBRegAfterMrc(): Start.\n")); + + Status = (*PeiServices)->GetBootMode( PeiServices, &BootMode ); + + if (BootMode == BOOT_ON_S3_RESUME) { + + PEI_TRACE((-1,PeiServices, "ProgramSBRegAfterMrc(): S3 Resume.\n")); + + Status = (*PeiServices)->LocatePpi( PeiServices, \ + &gEfiPeiReadOnlyVariable2PpiGuid, \ + 0, \ + NULL, \ + &ReadOnlyVariable ); + if (!EFI_ERROR(Status)) { + VariableSize = sizeof(WarmResetFlag); + Status = ReadOnlyVariable->GetVariable( ReadOnlyVariable, \ + WarmResetVar, \ + &WarmResetGuid, \ + NULL, \ + &VariableSize, \ + &WarmResetFlag ); + if (WarmResetFlag == SB_WARM_RESET_TAG) { + PEI_TRACE((-1,PeiServices, "ProgramSBRegAfterMrc(): Update BootMode.\n")); + BootMode = BOOT_WITH_FULL_CONFIGURATION; + +#if Capsule2_0_SUPPORT + // + // Update BootMode, if Capsule 2.0 PPI is available. + // + Status = (*PeiServices)->LocatePpi ( PeiServices, \ + &gPeiCapsulePpiGuid, \ + 0, \ + NULL, \ + &Capsule); + + if (!EFI_ERROR(Status)) { + BootMode = BOOT_ON_FLASH_UPDATE; + Status = (*PeiServices)->NotifyPpi( PeiServices, EndOfMrcNotifyList ); + + } else { + // Clear ACPI Sleep Type + RESET_IO32_PM(ACPI_IOREG_PM1_CNTL, 0x1c00 ); // 0x04 + } + + (*PeiServices)->SetBootMode(PeiServices, BootMode); +#else + (*PeiServices)->SetBootMode(PeiServices, BootMode); + // Clear ACPI Sleep Type + RESET_IO32_PM(ACPI_IOREG_PM1_CNTL, 0x1c00 ); // 0x04 +#endif + } + } + } + + PEI_TRACE((-1,PeiServices, "ProgramSBRegAfterMrc(): End.\n")); + + return EFI_SUCCESS; +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ProgramSBRegEndOfMrc +// +// Description: This function can be used to program any SB regisater at +// end of MRC. +// +// Input: PeiServices - Pointer to the PEI services table +// NotifyDescriptor - Pointer to the descriptor for the +// notification event. +// InvokePpi - Pointer to the PPI that was installed +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS ProgramSBRegEndOfMrc ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *InvokePpi ) +{ + IN EFI_BOOT_MODE BootMode; + EFI_STATUS Status; + VOID *RecoveryModePpi; + + PEI_TRACE((-1,PeiServices, "ProgramSBRegEndOfMrc(): Start.\n")); + + Status = (*PeiServices)->LocatePpi (PeiServices, \ + &gRecoveryBootModeGuid, \ + 0, \ + NULL, \ + &RecoveryModePpi); + + if (EFI_ERROR(Status)) { + // Update Bootmode + (*PeiServices)->GetBootMode( PeiServices, &BootMode ); + PEI_TRACE((-1,PeiServices, "Before change BootMode = %X\n", BootMode)); + BootMode = BOOT_WITH_FULL_CONFIGURATION; + (*PeiServices)->SetBootMode(PeiServices, BootMode); + } + PEI_TRACE((-1,PeiServices, "ProgramSBRegEndOfMrc(): End.\n")); + + return EFI_SUCCESS; +} + +#if SB_RESET_PPI_SUPPORT + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBPEI_ResetSystem +// +// Description: This function is the reset call interface function published +// by the reset PPI +// +// Input: PeiServices Pointer to the PEI services table +// +// Output: SYSTEM RESET +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SBPEI_ResetSystem ( + IN EFI_PEI_SERVICES **PeiServices ) +{ +#if WdtPei_SUPPORT + WDT_PPI *Wdt; + EFI_STATUS Status; + + Status = (*PeiServices)->LocatePpi ( PeiServices, \ + &gWdtPpiGuid, \ + 0, \ + NULL, \ + &Wdt ); + + ASSERT_PEI_ERROR (PeiServices, Status); + + Wdt->AllowKnownReset(); +#endif + + SBLib_ResetSystem(EfiResetCold); + + // We should never get this far + return EFI_SUCCESS; +} + +#endif + +#if SB_STALL_PPI_SUPPORT + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBPEI_Stall +// +// Description: This function provides a blocking stall at least number +// of microseconds by SB ACPI timer +// +// Input: PeiServices - Pointer to the PEI services table +// This - Pointer to the Stall PPI +// MicroSeconds - Number of microseconds for which to stall +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SBPEI_Stall ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_STALL_PPI *This, + IN UINTN MicroSeconds ) +{ + EFI_STATUS Status; + EFI_PEI_PCI_CFG2_PPI *PciCfg; + + // Locate PciCfg PPI + PciCfg = (*PeiServices)->PciCfg; + + // At this time no manipulation needed. The value passed in is in + // MicroSeconds(us) and that is what the library function uses + + // Call Library function that is shared with Metronome + // Architecture Protocol + + + Status = CountTime(MicroSeconds, PM_BASE_ADDRESS); + + return Status; +} + +#endif + +#if ATAPI_RECOVERY_SUPPORT + +EFI_GUID gIdeRecoveryNativeModePpiGuid = \ + PEI_IDE_RECOVERY_NATIVE_MODE_PPI_GUID; + +PEI_IDE_RECOVERY_NATIVE_MODE_PPI IdeRecoveryNativeModePpi = { + SB_TEMP_IO_BASE+0x200, + SB_TEMP_IO_BASE+0x282, + SB_TEMP_IO_BASE+0x300, + SB_TEMP_IO_BASE+0x382 +}; + +EFI_PEI_PPI_DESCRIPTOR IdeRecoveryNativeModePpiDescriptor = { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), \ + &gIdeRecoveryNativeModePpiGuid, &IdeRecoveryNativeModePpi +}; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitSATARegs +// +// Description: This function initializes SATA controller registers +// for ATA/ATAPI recovery support. +// +// Input: PeiServices - Pointer to the PEI services table +// PciCfg - Pointer to the PCI Configuration PPI +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID InitSATARegs ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg +) +{ + // TODO +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EnableAtaChannel +// +// Description: This function enables the specific channel of ATA/SATA +// controller(s) depend on input ChannelMask +// +// Input: PeiServices - Pointer to the PEI services table +// This - Pointer to the ATA Controller PPI +// ChannelMask - Mask for the specific channel. +// +// Output: EFI_STATUS +// +// Notes: Normally we have to enables all chennels on ATA/SATA +// controller(s) regardless of ChannelMask. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EnableAtaChannel ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_ATA_CONTROLLER_PPI *This, + IN UINT8 ChannelMask ) +{ + EFI_STATUS Status; + + // SATA 0 (B0:D31:F2) + // Initialize the controller to IDE mode + RW_PCI8_SATA(R_PCH_SATA_MAP, 0, B_PCH_SATA_MAP_SMS_MASK | B_PCH_SATA_PORT_TO_CONTROLLER_CFG); // [EIP86096]>> + + //Enable the SATA2 for setting IDE mode to recovery + RESET_MEM32_RCRB (R_PCH_RCRB_FUNC_DIS ,BIT25); // <<[EIP86096] + + // Initialize Primary/Secondary IDE controller to operate in Legacy mode + RW_PCI8_SATA(R_PCH_SATA_PI_REGISTER, 0, B_PCH_SATA_PI_REGISTER_PNE | B_PCH_SATA_PI_REGISTER_SNE); + + // Enable IO space decode + RW_PCI16_SATA(R_PCH_SATA_COMMAND, B_PCH_SATA_COMMAND_IOSE, 0); + + if ((ChannelMask & PEI_ICH_IDE_PRIMARY) == PEI_ICH_IDE_PRIMARY) + // Enable Primary IDE Controller decode + RW_PCI16_SATA(R_PCH_SATA_TIMP, B_PCH_SATA_TIM_IDE, 0); + + if ((ChannelMask & PEI_ICH_IDE_SECONDARY) == PEI_ICH_IDE_SECONDARY) + // Enable Secondary IDE Controller decode + RW_PCI16_SATA(R_PCH_SATA_TIMS, B_PCH_SATA_TIM_IDE, 0); + + // Enable SATA ports 0, 1, 2 and 3. + RW_PCI16_SATA(R_PCH_SATA_PCS, (B_PCH_SATA_PCS_PORT0_EN | B_PCH_SATA_PCS_PORT1_EN | B_PCH_SATA_PCS_PORT2_EN | B_PCH_SATA_PCS_PORT3_EN), 0); + + // SATA 1 (B0:D31:F5) + RW_PCI16_SATA2(R_PCH_SATA_PCMD_BAR, SB_TEMP_IO_BASE + 0x200, 0); + RW_PCI16_SATA2(R_PCH_SATA_PCNL_BAR, SB_TEMP_IO_BASE + 0x282, 0); + RW_PCI16_SATA2(R_PCH_SATA_SCMD_BAR, SB_TEMP_IO_BASE + 0x300, 0); + RW_PCI16_SATA2(R_PCH_SATA_SCNL_BAR, SB_TEMP_IO_BASE + 0x382, 0); + + // Enable IO space decode + RW_PCI16_SATA2(R_PCH_SATA_COMMAND, B_PCH_SATA_COMMAND_IOSE, 0); + + if ((ChannelMask & PEI_ICH_IDE_PRIMARY) == PEI_ICH_IDE_PRIMARY) + // Enable Primary IDE Controller decode + RW_PCI16_SATA2(R_PCH_SATA_TIMP, B_PCH_SATA_TIM_IDE, 0); + + if ((ChannelMask & PEI_ICH_IDE_SECONDARY) == PEI_ICH_IDE_SECONDARY) + // Enable Secondary IDE Controller decode + RW_PCI16_SATA2(R_PCH_SATA_TIMS, B_PCH_SATA_TIM_IDE, 0); + + // Enable SATA1 ports 0(4) and 1(5). + RW_PCI16_SATA2(R_PCH_SATA_PCS, (B_PCH_SATA_PCS_PORT0_EN | B_PCH_SATA_PCS_PORT1_EN), 0); + + // Delay 1ms for HDD devices ready. + CountTime(1000, PM_BASE_ADDRESS); + + Status = (**PeiServices).InstallPpi( PeiServices, \ + &IdeRecoveryNativeModePpiDescriptor); + if (EFI_ERROR (Status)) return Status; + + return EFI_SUCCESS; +} +#endif // ATAPI_RECOVERY_SUPPORT + + + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/SBRun.c b/Chipset/SB/SBRun.c new file mode 100644 index 0000000..a5f9430 --- /dev/null +++ b/Chipset/SB/SBRun.c @@ -0,0 +1,1144 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Chipset/SB/SBRun.c 1 4/19/16 7:42a Chienhsieh $ +// +// $Revision: 1 $ +// +// $Date: 4/19/16 7:42a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Chipset/SB/SBRun.c $ +// +// 1 4/19/16 7:42a Chienhsieh +// +// 5 7/17/13 1:54a Scottyang +// [TAG] EIP128233 +// [Category] Improvement +// [Description] Improving UEFI PXE image downloading proformance. +// [Files] RTC.h +// SBRun.c +// +// 4 3/19/13 8:24a Scottyang +// [TAG] EIP106509 +// [Category] Improvement +// [Description] 3. Improve the Intel UEFI GbE driver performance in +// IPv4 connection. +// [Files] SBRun.c +// +// 3 1/27/13 11:01p Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Capsule 2.0 crash dump link function. +// [Files] SBPEI.c +// SBDxe.c +// SBRun.c +// +// 2 12/20/12 9:59p Scottyang +// [TAG] EIP77459 +// [Category] Improvement +// [Description] Update for Intel flash utility "FPT.efi" support. +// [Files] SBRun.c +// +// 1 2/08/12 8:24a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SBRUN.C +// +// Description: This file contains code for general Southbridge runtime +// protocol +// +//<AMI_FHDR_END> +//************************************************************************* + +//--------------------------------------------------------------------------- +// Include(s) +//--------------------------------------------------------------------------- + +#include <Efi.h> +#include <Token.h> +#include <AmiLib.h> +#include <AmiDxeLib.h> +#include <AmiCspLib.h> +#include "RTC.h" + +// Produced Protocols +#include <Protocol\Metronome.h> +#include <Protocol\Reset.h> +#include <Protocol\RealTimeClock.h> +#include <Protocol\Timer.h> + +//--------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//--------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +EFI_STATUS WaitForTick ( + IN EFI_METRONOME_ARCH_PROTOCOL *This, + IN UINT32 TickNumber +); + +//--------------------------------------------------------------------------- +// Variable and External Declaration(s) +//--------------------------------------------------------------------------- +// Variable Declaration(s) + +EFI_HANDLE mResetProtocolHandle = NULL; +static BOOLEAN gTimeOut = FALSE; + // [EIP77459]> +UINT16 gTimeZone; +UINT8 gDaylight; + // <[EIP77459] + +EFI_RESET_SYSTEM gCallSavedIntelPointer; + +// This the number of days in a month - 1. (0 Based) +UINT8 DaysInMonth[] = { 30, 27, 30, 29, 30, 29, 30, 30, 29, 30, 29, 30 }; + // (EIP128233)>> +#pragma pack(push, 1) +typedef struct { + INT16 TimeZone; + UINT8 Daylight; + } TIME_VARIABLE; +#pragma pack(pop) + +static TIME_VARIABLE CachedTimeVariable; +static BOOLEAN CachedTimeVariableValid = FALSE; + // <<(EIP128233) +// GUID Definition(s) + +EFI_GUID gEfiMetronomeArchProtocolGuid = EFI_METRONOME_ARCH_PROTOCOL_GUID; +EFI_GUID guidReset = EFI_RESET_ARCH_PROTOCOL_GUID; +EFI_GUID gEfiRtcArchProtocolGuid = EFI_REAL_TIME_CLOCK_ARCH_PROTOCOL_GUID; +EFI_GUID gEfiTimeVariableGuid = EFI_TIME_VARIABLE_GUID; + +// Protocol Definition(s) + +EFI_METRONOME_ARCH_PROTOCOL mMetronomeProtocol = { + WaitForTick, + 1 +}; + +// External Declaration(s) + +// Function Definition(s) + +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiResetSystem +// +// Description: This function is the interface for the reset function. +// In the future, this may allow for a shared library for DXE +// and PEI. +// +// Input: ResetType - Type of reset to perform +// ResetStatus - System status that caused the reset. if part +// of normal operation then this should be +// EFI_SUCCESS, Otherwise it should reflect the +// state of the system that caused it +// DataSize - Size in bytes of the data to be logged +// *ResetData - Pointer to the data buffer that is to be +// logged +// +// Output: None, Even though it should never get that far +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiResetSystem ( + IN EFI_RESET_TYPE ResetType, + IN EFI_STATUS ResetStatus, + IN UINTN DataSize, + IN CHAR16 *ResetData OPTIONAL +) +{ + // Add logging messages here + // do a cold reset of the system + if (ResetType == EfiResetWarm) + { + SBLib_ResetSystem (ResetType); + } + else + { + if (gCallSavedIntelPointer == NULL) + SBLib_ResetSystem (ResetType); + + gCallSavedIntelPointer( ResetType, \ + ResetStatus, \ + DataSize, \ + ResetData ); + } + + // This should not get here + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WaitForTick +// +// Description: This function calculates the time needed to delay and then +// calls a library function to delay that amount of time +// +// Input: *This - Pointer to the instance of the Metronome Arch +// Protocol +// TickNumber - Number of ticks needed based off of tick period +// defined in Protocol Definiton +// +// Output: Return Status based on errors that occurred while waiting for +// time to expire. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS WaitForTick ( + IN EFI_METRONOME_ARCH_PROTOCOL *This, + IN UINT32 TickNumber ) +{ + EFI_STATUS Status; + UINT32 TotalTime; + + // Manipulate TickNumber into a valid value for the library function call + // the Current Resolution is 10us. + // The Library uses Microseconds to count delayed time. + TotalTime = (TickNumber * This->TickPeriod) / 10; + + // Make Library Function call here + Status = CountTime( TotalTime, PM_BASE_ADDRESS ); + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: DecToBCD +// +// Description: This function converts data from DEC to BCD format +// +// Input: UINT8 Dec - Value to be converted +// +// Output: UINT8 - Result of conversion +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT8 DecToBCD ( + IN UINT8 Dec ) +{ + UINT8 FirstDigit = Dec % 10; + UINT8 SecondDigit = Dec / 10; + + // Only for 2 digit BCD. + return (SecondDigit << 4) + FirstDigit; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: BCDToDec +// +// Description: This function converts data from BCD to DEC format +// +// Input: UINT8 Bcd - Value to be converted +// +// Output: UINT8 - Result of conversion +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT8 BCDToDec ( + IN UINT8 Bcd ) +{ + UINT8 FirstDigit = Bcd & 0xf; + UINT8 SecondDigit = Bcd >> 4;; + + // Only for 2 digit BCD. + return SecondDigit * 10 + FirstDigit; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ReadRtcIndex +// +// Description: Read the RTC value at the given Index. +// +// Input: Index - RTC Index +// +// Output: RTC Value read from the provided Index +// +// Notes: Here is the control flow of this function: +// 1. Read port 0x70 (RTC Index Register) to get bit 7. +// Bit 7 is the NMI bit-it should not be changed. +// 2. Set Index with the NMI bit setting. +// 3. Output 0x70 with the Index and NMI bit setting. +// 4. Read 0x71 for Data. Getting Dec when appropriate. +// 5. Return the Data. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT8 ReadRtcIndex ( + IN UINT8 Index ) +{ + volatile UINT8 Value; + BOOLEAN IntState = CPULib_GetInterruptState(); + + CPULib_DisableInterrupt(); + + IoWrite8(CMOS_IO_INDEX_BACKDOOR, Index); + Value = IoRead8(CMOS_IO_DATA_BACKDOOR); // Read register. + + if (IntState) CPULib_EnableInterrupt(); + + if ((Index <= RTC_YEAR_REG) || (Index == ACPI_CENTURY_CMOS)) + Value = BCDToDec(Value); + + return (UINT8)Value; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteRtcIndex +// +// Description: Write the RTC value at the given Index. +// +// Input: Index - RTC Index +// Value - Value to write +// +// Output: None +// +// Notes: Here is the control flow of this function: +// 1. Read port 0x70 (RTC Index Register) to get bit 7. +// Bit 7 is the NMI bit-it should not be changed. +// 2. Set Index with the NMI bit setting. +// 3. Output 0x70 with the Index. Switch to BCD when needed. +// 4. Write the data to 0x71. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteRtcIndex ( + IN UINT8 Index, + IN UINT8 Value ) +{ + BOOLEAN IntState = CPULib_GetInterruptState(); + + if ((Index <= RTC_YEAR_REG) || (Index == ACPI_CENTURY_CMOS)) + Value = DecToBCD(Value); + + CPULib_DisableInterrupt(); + + IoWrite8(CMOS_IO_INDEX_BACKDOOR, Index); + IoWrite8(CMOS_IO_DATA_BACKDOOR, Value); // Write Register. + + if (IntState) CPULib_EnableInterrupt(); + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitRtc +// +// Description: This function initializes RTC +// +// Input: None +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID InitRtc (VOID) +{ + WriteRtcIndex(RTC_REG_B_INDEX, 0x82); + WriteRtcIndex(RTC_REG_A_INDEX, 0x26); + ReadRtcIndex(RTC_REG_C_INDEX); + ReadRtcIndex(RTC_REG_D_INDEX); + WriteRtcIndex(RTC_REG_B_INDEX, 0x02); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SetUpdate +// +// Description: Enables Disables RTC Date and Time update cicles. +// +// Input: Enable - TRUE or FALSE to Enable\Disabe RTC Update. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SetUpdate ( + IN BOOLEAN Enable ) +{ + RTC_REG_B RegB; + UINT8 Set = (Enable) ? 0 : 1; + + RegB.REG_B = ReadRtcIndex(RTC_REG_B_INDEX); + if (RegB.Set != Set) { + RegB.Set = Set; + WriteRtcIndex(RTC_REG_B_INDEX, RegB.REG_B); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: CheckUpdateCmplete +// +// Description: Check if RTC Date and Time update in progress and waits till +// it's over. +// +// Input: None +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID CheckUpdateCmplete (VOID) +{ + volatile RTC_REG_A RegA; + UINTN TimeOut = 0; + + RegA.REG_A = ReadRtcIndex(RTC_REG_A_INDEX); + while (RegA.UpdInProgr) { + RegA.REG_A = ReadRtcIndex(RTC_REG_A_INDEX); + TimeOut++; + if (TimeOut >= 0x0fffff) { + gTimeOut = TRUE; + return; + } + } + + gTimeOut = FALSE; +} + +BOOLEAN IsLeapYear ( + IN EFI_TIME *Time ) +{ + if (Time->Year % 4 == 0) { + if (Time->Year % 100 == 0) { + if (Time->Year % 400 == 0) { + return TRUE; + } else { + return FALSE; + } + } else { + return TRUE; + } + } else { + return FALSE; + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: VerifyTime +// +// Description: This routine verifies if time and data if needed, before +// setting the RTC +// +// Input: *Time - Time to verify with +// +// Output: TRUE if valid time and date +// +// Notes: Here is the control flow of this function: +// 1. Decrease month and date to change to 0-base +// 2. Validate Year, Month and Day. If invalid, return FALSE. +// 3. Validate Hour, Minute and Second. If invalid, return FALSE. +// 4. Return True. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN VerifyTime ( + IN EFI_TIME *Time ) +{ + // Always check these to satisfy EFI compliancy test even for setting + // wake-up time. + UINT8 Month = Time->Month - 1; + UINT8 Day = Time->Day - 1; + + if ((Time->Year < EARLIEST_YEAR) || (Time->Year > 9999)) return FALSE; + if (Month > 11) return FALSE; // 0 based month + if ((Month != 1) || (!IsLeapYear(Time))) { // Not leap year or not February. + // All values already adjusted for 0 based. + if (Day > DaysInMonth[Month]) return FALSE; + } else { + if (Day > 28) return FALSE; // February + } + + if (Time->Hour > 23) return FALSE; + if (Time->Minute > 59) return FALSE; + if (Time->Second > 59) return FALSE; + + // Check these to satisfy EFI compliancy test. + if (Time->Nanosecond > 999999999) return FALSE; // 999,999,999 + if (Time->TimeZone < -1440) return FALSE; + if (Time->TimeZone > 1440 && Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) + return FALSE; + + return TRUE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetDayOfTheWeek +// +// Description: Returns an index that represents the day of the week of the +// date passed in +// +// Input: *Time - Pointer to EFI_TIME structure +// +// Output: Returns the index to the day of the week. 0 = Sunday, +// 1 = Monday ... 6 = Saturday +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT8 GetDayOfTheWeek ( + IN EFI_TIME *Time ) +{ + UINT16 a; + UINT16 m; + UINT16 d; + UINT16 y; + + a = (14 - Time->Month) / 12; + y = Time->Year - a; + m = Time->Month + 12 * a - 2; + d = (Time->Day + y + y / 4 - y / 100 + y / 400 + (31 * m) / 12) % 7; + + return (UINT8)d; +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: CheckRtc +// +// Description: Check if RTC Mode and Format have appropriate values and sets +// them if necessary +// +// Input: Set - if true, force Rtc to 24 hour mode and binary format. +// +// Output: EFI_STATUS +// EFI_SUCCESS - RTC mode and format have appropriate values. +// EFI_DEVICE_ERROR - RTC mode and/or format are invalid. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS CheckRtc ( + IN BOOLEAN Set ) +{ + RTC_REG_B RegB; + + // Check RTC Conditions and stuff + RegB.REG_B = ReadRtcIndex(RTC_REG_B_INDEX); + if((RegB.Mode == 0) || (RegB.Format == 1)) { + if (Set) { + RegB.Mode = 1; // 1 - 24 hour mode + RegB.Format = 0; // 0 - BCD Format + WriteRtcIndex(RTC_REG_B_INDEX, RegB.REG_B); + } else { + return EFI_DEVICE_ERROR; + } + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiGetTime +// +// Description: Return the current date and time +// +// Input: *Time - Current time filled in EFI_TIME structure +// *Capabilities - Time capabilities (OPTIONAL) +// +// Output: EFI_SUCCESS +// EFI_INVALID_PARAMETER - A NULL Time. +// EFI_DEVICE_ERROR - RTC mode and/or format are invalid +// EFI_SUCCESS - Read the current date and time successfully. +// +// +// Notes: Here is the control flow of this function: +// 1. Read the original time format 12/24 hours and BCD/binary. +// 2. Set the format to 24 hrs and binary. +// 3. Read the 2 digit year. +// 4. Add either 1900 or 2000, so the year is between 1998 - 2097 +// 5. Read the month, day, hour, minute, second. +// 6. Set the nanosecond to 0. +// 7. Set the time to zone to unspecified. +// 8. Set daylight savings value to 0. +// 9. Restore the original time format. +// 10.Set Capabilities with 1 sec Resolution, 0 Accuracy +// (Unknown), and False SetsToZero. +// 11.Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiGetTime ( + OUT EFI_TIME *Time, + OUT EFI_TIME_CAPABILITIES *Capabilities OPTIONAL ) +{ + EFI_STATUS Status; + UINT8 Year; + BOOLEAN IntState; + BOOLEAN SmiState; + UINTN TimeVarSize = sizeof(TIME_VARIABLE); + UINT8 Buffer8; // [EIP77459] + + if (Time == NULL) return EFI_INVALID_PARAMETER; + + // Check RTC Conditions (24h Mode and BCD is ON) + Status = CheckRtc(FALSE); + if (EFI_ERROR(Status)) return Status; + + // Get SMI State and disable it + SmiState = SbLib_GetSmiState(); + SbLib_SmiDisable(); + // Get INTERRUPT State and disable it + IntState = CPULib_GetInterruptState(); + CPULib_DisableInterrupt(); + + // Wait till RTC is safe to read, + CheckUpdateCmplete(); + if (gTimeOut) InitRtc(); + + // After control comes back, we will have 488 u's to read data. + Year = ReadRtcIndex(RTC_YEAR_REG); + Time->Month = ReadRtcIndex(RTC_MONTH_REG); + Time->Day = ReadRtcIndex(RTC_DAY_OF_MONTH_REG); + Time->Hour = ReadRtcIndex(RTC_HOURS_REG); + Time->Minute = ReadRtcIndex(RTC_MINUTES_REG); + Time->Second = ReadRtcIndex(RTC_SECONDS_REG); + + // Restore SMIs and INTERRUPT State + if(IntState) CPULib_EnableInterrupt(); + if(SmiState) SbLib_SmiEnable(); + + // This Register is not affected by UIP bit so read it very last. + // If RTC Year only 1 digit, EFI spec says years rang is 1998 - 2097 + Time->Year = ReadRtcIndex(ACPI_CENTURY_CMOS) * 100 + Year; + + Time->Nanosecond= 0; + + // [EIP77459]> + // Save BIOSWE bit (B0:D31:F0 Reg#DCh[0]) + Buffer8 = READ_PCI8_SB(SB_REG_BIOS_CNTL); + // (EIP128233)>> + if(CachedTimeVariableValid && (Buffer8 & BIT00) != 0) { + Time->TimeZone = CachedTimeVariable.TimeZone; + Time->Daylight = CachedTimeVariable.Daylight; + } else { + Status = pRS->GetVariable( L"EfiTime", \ + &gEfiTimeVariableGuid, \ + NULL, \ + &TimeVarSize, \ + &CachedTimeVariable ); + if (EFI_ERROR(Status)) { + CachedTimeVariable.TimeZone = EFI_UNSPECIFIED_TIMEZONE; + CachedTimeVariable.Daylight = 0; + } + + Time->TimeZone = CachedTimeVariable.TimeZone; + Time->Daylight = CachedTimeVariable.Daylight; + CachedTimeVariableValid = TRUE; + } + + // Restore BIOSWE bit (B0:D31:F0 Reg#DCh[0]) + WRITE_PCI8_SB(SB_REG_BIOS_CNTL, Buffer8); + // <[EIP77459] + // <<(EIP128233) + if (Capabilities != NULL) { + Capabilities->Resolution = 1; + Capabilities->Accuracy = 0; + Capabilities->SetsToZero = 0; + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSetTime +// +// Description: Sets the RTC time +// +// Input: *Time - Time to set +// +// Output: EFI_STATUS +// EFI_SUCCESS - Time is Set +// EFI_INVALID_PARAMETER - Time to Set is not valid. +// +// Notes: Here is the control flow of this function: +// 1. Read the original time format 12/24 hours and BCD/binary. +// 2. Set the format to 24 hrs and binary. +// 3. Verify the time to set. If it is an invalid time, +// restore the time format and return EFI_INVALID_PARAMETER. +// 4. Change the 4 digit year to a 2 digit year. +// 5. Stop the RTC time. +// 6. Store time and data on the RTC. +// 7. Read the month, day, hour, minute, second. +// 8. Start the RTC time. +// 9. Restore the original time format. +// 10.Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSetTime ( + IN EFI_TIME *Time ) +{ + + EFI_STATUS Status = EFI_SUCCESS; + UINTN TimeVarSize = sizeof(TIME_VARIABLE); + + // Check RTC Conditions and stuff + CheckRtc(TRUE); + + if (Time == NULL) return EFI_INVALID_PARAMETER; + if (!VerifyTime(Time)) return EFI_INVALID_PARAMETER; + + SetUpdate(FALSE); + WriteRtcIndex(ACPI_CENTURY_CMOS, Time->Year / 100); + WriteRtcIndex(RTC_YEAR_REG, Time->Year % 100); + WriteRtcIndex(RTC_MONTH_REG, Time->Month); + WriteRtcIndex(RTC_DAY_OF_MONTH_REG, Time->Day); + WriteRtcIndex(RTC_DAY_OF_WEEK_REG, GetDayOfTheWeek(Time) + 1); + + WriteRtcIndex(RTC_HOURS_REG, Time->Hour); + WriteRtcIndex(RTC_MINUTES_REG, Time->Minute); + WriteRtcIndex(RTC_SECONDS_REG, Time->Second); + SetUpdate(TRUE); + + // (EIP128233)>> + if(CachedTimeVariableValid && + CachedTimeVariable.TimeZone == Time->TimeZone && + CachedTimeVariable.Daylight == Time->Daylight) + return EFI_SUCCESS; + + CachedTimeVariable.TimeZone = Time->TimeZone; + CachedTimeVariable.Daylight = Time->Daylight; + + Status = pRS->SetVariable( + L"EfiTime", + &gEfiTimeVariableGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, + sizeof(TIME_VARIABLE), + &CachedTimeVariable + ); + if(!EFI_ERROR(Status)) + CachedTimeVariableValid = TRUE; + // <<(EIP128233) + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiGetWakeupTime +// +// Description: Read the wake time. Read the status if it is enabled or +// if the system has woken up. +// +// Input: *Enabled - Flag indicating the validity of wakeup time +// *Pending - Check if wake up time has expired. +// *Time - Current wake up time setting +// +// Output: EF_STATUS +// EFI_SUCCESS - Read the wake time successfully. +// EFI_INVALID_PARAMETER - Invalid input parameters +// EFI_DEVICE_ERROR - RTC mode and/or format are invalid +// +// Notes: Here is the control flow of this function: +// 1. Read the original time format 12/24 hours and BCD/binary. +// 2. Set the format to 24 hrs and binary. +// 3. Read the status if the wake up time is enabled or if it has expired. +// 4. Set the wakeup time. +// 5. Restore the original time format. +// 6. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiGetWakeupTime ( + OUT BOOLEAN *Enabled, + OUT BOOLEAN *Pending, + OUT EFI_TIME *Time ) +{ + EFI_STATUS Status; + BOOLEAN IntState; + BOOLEAN SmiState; + RTC_REG_B RegB; + RTC_REG_C RegC; +#if ACPI_ALARM_DAY_CMOS + RTC_DATE_ALARM_REG RegDateAlarm; +#endif +#if ACPI_ALARM_MONTH_CMOS + RTC_MONTH_ALARM_REG RegMonthAlarm; +#endif + + if (!Enabled || !Pending || !Time) return EFI_INVALID_PARAMETER; + + // Check RTC Conditions (24h Mode and BCD is ON) + Status = CheckRtc(FALSE); + if (EFI_ERROR(Status)) return Status; + + // Get SMI State and disable it + SmiState = SbLib_GetSmiState(); + SbLib_SmiDisable(); + // Get INTERRUPT State and disable it + IntState = CPULib_GetInterruptState(); + CPULib_DisableInterrupt(); + + // Wait till RTC is safe to read, + CheckUpdateCmplete(); + if (gTimeOut) InitRtc(); + + Time->Hour = ReadRtcIndex(RTC_HOURS_ALARM_REG); + Time->Minute = ReadRtcIndex(RTC_MINUTES_ALARM_REG); + Time->Second = ReadRtcIndex(RTC_SECONDS_ALARM_REG); + + // Restore SMIs and INTERRUPT State + if (IntState) CPULib_EnableInterrupt(); + if (SmiState) SbLib_SmiEnable(); + +#if ACPI_ALARM_DAY_CMOS + RegDateAlarm.REG_DATE_ALARM = ReadRtcIndex(ACPI_ALARM_DAY_CMOS); + Time->Day = BCDToDec(RegDateAlarm.DateAlarm); +#else + Time->Day = 0; +#endif + +#if ACPI_ALARM_MONTH_CMOS + RegMonthAlarm.REG_MONTH_ALARM = ReadRtcIndex(ACPI_ALARM_MONTH_CMOS); + Time->Month = BCDToDec(RegMonthAlarm.MonthAlarm); +#else + Time->Month = 0; +#endif + + RegB.REG_B = ReadRtcIndex(RTC_REG_B_INDEX); + RegC.REG_C = ReadRtcIndex(RTC_REG_C_INDEX); + + + *Enabled = (RegB.AlarmInt == 1) ? TRUE : FALSE; + *Pending = (RegC.AlarmFlag == 1) ? TRUE : FALSE; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSetWakeupTime +// +// Description: Enable/disable and set wakeup time +// +// Input: Enable - Flag indicating whether to enable/disble the time +// *Time - Time to set +// +// Output: EFI_STATUS +// EFI_SUCCESS - Wakeup time is Set and/or Enabled/Disabled. +// EFI_DEVICE_ERROR - RTC mode and/or format are invalid +// EFI_INVALID_PARAMETER - Invalid time or enabling with a +// NULL Time. +// +// Notes: Here is the control flow of this function: +// 1. Read the original time format 12/24 hours and BCD/binary. +// 2. If Time is not NULL, +// a. Verify the wakeup time to set. If it is an invalid +// time, restore the time format and +// return EFI_INVALID_PARAMETER. +// b. Set the wakeup time. +// 3. If Time is NULL and Enable is true, restore original +// time format and return EFI_INVALID_PARAMETER. +// 4. Enable/Disable wakeup. +// 5. Restore the original time format. +// 6. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSetWakeupTime ( + IN BOOLEAN Enable, + IN EFI_TIME *Time OPTIONAL ) +{ + + EFI_STATUS Status; + RTC_REG_B RegB; + RTC_REG_C RegC; +#if ACPI_ALARM_DAY_CMOS + RTC_DATE_ALARM_REG RegDateAlarm; +#endif +#if ACPI_ALARM_MONTH_CMOS + RTC_MONTH_ALARM_REG RegMonthAlarm; +#endif + + // Check RTC Conditions (24h Mode and BCD is ON) + Status = CheckRtc(FALSE); + if(EFI_ERROR(Status)) return Status; + + if (Time != NULL) { + if (!VerifyTime(Time)) return EFI_INVALID_PARAMETER; + } else { + if (Enable) return EFI_INVALID_PARAMETER; + } + + RegB.REG_B = ReadRtcIndex(RTC_REG_B_INDEX); + + SetUpdate(FALSE); + if (Time != NULL) { + WriteRtcIndex(RTC_HOURS_ALARM_REG, Time->Hour); + WriteRtcIndex(RTC_MINUTES_ALARM_REG, Time->Minute); + WriteRtcIndex(RTC_SECONDS_ALARM_REG, Time->Second); +#if ACPI_ALARM_DAY_CMOS + // Day == 0 means don't care + RegDateAlarm.DateAlarm = DecToBCD(Time->Day); + WriteRtcIndex(ACPI_ALARM_DAY_CMOS, RegDateAlarm.REG_DATE_ALARM); +#endif +#if ACPI_ALARM_MONTH_CMOS + // Month == 0 means don't care + RegMonthAlarm.MonthAlarm = DecToBCD(Time->Month); + WriteRtcIndex(ACPI_ALARM_MONTH_CMOS, RegMonthAlarm.REG_MONTH_ALARM); +#endif + } + + // Clear Alarm Flag + RegC.REG_C = ReadRtcIndex(RTC_REG_C_INDEX); + + // Set Enable/Disable + RegB.AlarmInt = (Enable) ? 1 : 0; + WriteRtcIndex(RTC_REG_B_INDEX, RegB.REG_B); + + SetUpdate(TRUE); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SaveIntelResetPointer +// +// Description: +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SaveIntelResetPointer ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + gCallSavedIntelPointer = pRS->ResetSystem; + pRS->ResetSystem = EfiResetSystem; + + pBS->CloseEvent(Event); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBRun_Init +// +// Description: This function is the entry point for this DXE. This function +// installs the runtime services related to SB +// +// Input: ImageHandle - Image handle +// SystemTable - Pointer to the system table +// +// Output: EFI_STATUS +// EFI_SUCCESS - All the protocol interfaces were installed. +// EFI_ALREADY_STARTED - A Device Path instance was passed +// in that is already present in the +// handle database. +// EFI_OUT_OF_RESOURCES - There was not enough memory in +// pool to install all the protocols. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SBRun_Init ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status = EFI_SUCCESS; + EFI_TIME Time; + EFI_TIME NewTime; + EFI_HANDLE Handle = NULL; + UINT8 PM2 = READ_PCI8_SB(SB_REG_GEN_PMCON_2); + UINT8 PM3 = READ_PCI8_SB(SB_REG_GEN_PMCON_3); + RTC_REG_D RegD; + BOOLEAN RtcLostPower = FALSE; + + InitAmiRuntimeLib(ImageHandle, SystemTable, NULL, NULL); + + PROGRESS_CODE(DXE_SBRUN_INIT); + + // CspLib PM Specific function to check and Report + // CMOS Battary and Power Supply Power loss/failure + CspLibCheckPowerLoss(); + + if(PM3 & BIT02) { + // Clear RTC_PWR_STS. + PM3 &= ~BIT02; + RtcLostPower = TRUE; + } + //Write back Cleared Statuses + WRITE_PCI8_SB(SB_REG_GEN_PMCON_2, PM2); + WRITE_PCI8_SB(SB_REG_GEN_PMCON_3, PM3); + + RegD.REG_D = ReadRtcIndex(RTC_REG_D_INDEX); + if (RegD.DataValid == 0) + RtcLostPower = TRUE; + + if (RtcLostPower) { + ERROR_CODE(DXE_SB_BAD_BATTERY, EFI_ERROR_MAJOR); + InitRtc(); + } + + + // MakeSure Mode, Format and REG_A is OK + CheckRtc(TRUE); + + Status = EfiGetTime(&Time, NULL); + if (EFI_ERROR(Status) || !VerifyTime(&Time)) { + ERROR_CODE(GENERIC_BAD_DATE_TIME_ERROR, EFI_ERROR_MINOR); + + TRACE((TRACE_ALWAYS, "\n\nTime: %d/%d/%d %d:%d:%d\n", + Time.Month, + Time.Day, + Time.Year, + Time.Hour, + Time.Minute, + Time.Second + )); + + TRACE((TRACE_ALWAYS, "Nanosecond: %d TimeZone: %d\n\n\n", + Time.Nanosecond, + Time.TimeZone + )); + + // if Time is invalid the battery probably has been removed + // Let's setup RTC_REG_A just in case... + WriteRtcIndex(RTC_REG_A_INDEX, 0x26); + + // Check to see what part of EFI_TIME was wrong. + // reset unrelated to RTC fields. + Time.TimeZone = EFI_UNSPECIFIED_TIMEZONE; + Time.Daylight = 0; + Time.Nanosecond = 0; + + NewTime = Time; + + NewTime.Hour = 0; + NewTime.Minute = 0; + NewTime.Second = 0; + + if (VerifyTime(&NewTime)) { + // if we here that means Time was wrong + Time.Hour = 0; + Time.Minute = 0; + Time.Second = 0; + } else { + // if we here that means Date was wrong + Time.Month = DEFAULT_MONTH; + Time.Day = DEFAULT_DAY; + Time.Year = DEFAULT_YEAR; + } + + // Here is the situation when both Time and Date is Incorrect. + if (!VerifyTime(&Time)) { + Time.Hour = 0; + Time.Minute = 0; + Time.Second = 0; + Time.Month=DEFAULT_MONTH; + Time.Day=DEFAULT_DAY; + Time.Year=DEFAULT_YEAR; + } + + TRACE((TRACE_ALWAYS, "Reseting Date and Time to: %d/%d/%d %d:%d:%d\n", + Time.Month, + Time.Day, + Time.Year, + Time.Hour, + Time.Minute, + Time.Second + )); + EfiSetTime(&Time); + } + + // Install runtime services + pRS->ResetSystem = EfiResetSystem; + + gCallSavedIntelPointer = NULL; + + pRS->GetTime = EfiGetTime; + pRS->SetTime = EfiSetTime; + pRS->GetWakeupTime = EfiGetWakeupTime; + pRS->SetWakeupTime = EfiSetWakeupTime; + + Status = pBS->InstallProtocolInterface( &ImageHandle, \ + &gEfiMetronomeArchProtocolGuid, \ + EFI_NATIVE_INTERFACE, \ + &mMetronomeProtocol ); + ASSERT_EFI_ERROR(Status); +{ + EFI_EVENT Event = NULL; + VOID *Registration = NULL; + + Status = RegisterProtocolCallback( &gEfiResetArchProtocolGuid,\ + SaveIntelResetPointer,\ + NULL,\ + &Event,\ + &Registration ); + ASSERT_EFI_ERROR(Status); +} + + // This protocol is to notify core that the Runtime Table has been + // updated, so it can update the runtime table CRC. + return pBS->InstallMultipleProtocolInterfaces( &Handle, \ + &gEfiRtcArchProtocolGuid, \ + NULL, \ + NULL ); +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/SBSMI.c b/Chipset/SB/SBSMI.c new file mode 100644 index 0000000..a6cae4d --- /dev/null +++ b/Chipset/SB/SBSMI.c @@ -0,0 +1,1744 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SB SMI/SBSMI.c 19 7/12/15 11:08p Dennisliu $ +// +// $Revision: 19 $ +// +// $Date: 7/12/15 11:08p $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SB SMI/SBSMI.c $ +// +// 19 7/12/15 11:08p Dennisliu +// [TAG] None +// [Category] Improvement +// [Description] Coding error in ElogGenerateNmiNow() +// [Files] Chipset\SB\SBSMI.c +// +// 17 12/30/13 5:59a Barretlin +// [TAG] EIP144559 +// [Category] Improvement +// [Description] S3 can't resume via USB KB & MS under usb3.0 port in +// special case +// [Files] SBSMI.c SBSMI.h SBGeneric.c +// +// 16 10/01/13 7:53a Barretlin +// [TAG] EIP137385 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] System hang if power button pushed on BSU, after windows +// shutdown / reboot +// [RootCause] Push power button key on RF keyboard will triger xhci hw +// smi, but xhci is set D3hot state in power button handler, then we can't +// service it +// [Solution] Stop xhci before we set D3hot state and check if +// hciversion is valid +// [Files] SBSMI.c +// +// 15 5/28/13 11:45p Scottyang +// [TAG] None +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] GbE cannot wake form S5 under DOS. +// [RootCause] The base address is incorrect. +// [Solution] Correct base address. +// [Files] SBSMI.c +// +// 14 4/19/13 6:34a Wesleychen +// [TAG] None +// [Category] Improvement +// [Description] Update GbES02SxWorkaround() and add +// UsbS02SxWorkaround() for SBPwrBtnHandler(). +// [Files] SBSMI.c; SBSMI.h; SBGeneric.c; SBCspLib.h +// +// 12 3/21/13 3:39a Scottyang +// [TAG] EIP83075 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] USB3.0 mouse can not resume form S3 if shot down at POST +// before. +// [Solution] Additional xHCI Controller Configurations Prior to Enter +// S5. +// [Files] SBSMI.c +// +// 11 3/19/13 8:37a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Improve alternate access mode enable/disable routine. +// [Files] SBGeneric.c, SBCspLib.h, SBSMI.c +// +// 10 1/11/13 4:46a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Fixed coding error. +// [Files] SBSMI.c +// +// 9 1/04/13 2:45a Scottyang +// [TAG] EIP104199 +// [Category] Improvement +// [Description] Register dummy Handler for all Tco Smi +// [Files] SBSMI.c; +// +// 8 10/30/12 10:04p Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Remove clear SMI state and Y2K roller for PFAT +// function. +// [Files] SBSMI.c, SBGeneric.c +// +// 7 10/26/12 1:11a Scottyang +// [TAG] CHECK_BS_VARIABLE +// [Category] Improvement +// [Description] If project has module NVRamSMI then don't need to check +// this. +// [Files] SBSMI.c +// +// 6 10/12/12 8:06a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Fixed the system hang when Y2K roll over is occur with +// TCO SMI enabled. +// +// 5 9/26/12 3:58a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update for PCH LP GPIO compatible. +// [Files] SB.sdl, SB.H, AcpiModeEnable.c, AcpiModeEnable.sdl, +// SBDxe.c, SBGeneric.c, SBPEI.c, SBSMI.c, SleepSmi.c, +// SmiHandlerPorting.c, SmiHandlerPorting2.c +// +// 4 8/13/12 10:31a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Implement BIOS Lock function. +// [Files] SBCspLib.h, SBDxe.c, SBSMI.c, SBSMI.dxs, SBSMI.sdl +// +// 3 7/27/12 6:17a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update to support ULT Platform. +// [Files] SB.H, SB.mak, SB.sdl, SB.sd, SBSetup.c, +// AcpiModeEnable.c, SBDxe.c, SBPEI.c, SBSMI.c, SleepSmi.c, +// SmiHandlerPorting.c, SmiHandlerPorting2.c, SBPPI.h, Pch.sdl +// +// 2 6/13/12 11:36p Victortu +// [TAG] None +// [Category] Improvement +// [Description] Implement Warm Boot function for Secure Flash feature. +// [Files] SB.H, SB.mak, SB.sdl, SBDxe.c, SBGeneric.c, SBPEI.c, +// SBSMI.c +// +// 1 2/08/12 8:31a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SBSMI.c +// +// Description: This file contains code for all North Bridge SMI events +// +//<AMI_FHDR_END> +//************************************************************************* + +//---------------------------------------------------------------------------- +// Include(s) +//---------------------------------------------------------------------------- + +#include <Token.h> +#include <Setup.h> +#include <AmiDxeLib.h> +#include <AMICSPLIBInc.h> +#include <AmiCspLib.h> +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) +#include <Protocol\SmmPowerButtonDispatch2.h> +#include <Protocol\SmmBase2.h> +#include <Protocol\S3SaveState.h> +#include <Protocol\SmmSwDispatch2.h> +#else +#include <Protocol\SmmPowerButtonDispatch.h> +#include <Protocol\SmmBase.h> +#include <Protocol\BootScriptSave.h> +#include <Protocol\SmmSwDispatch.h> +#endif +#if SB_PCIE_ERROR_LOG_SUPPORT +#include <Protocol\GenericElog.h> +#endif +#include <Protocol\SBSmiProtocol.h> +#include <Edk\Foundation\Framework\Protocol\SmmIchnDispatch\SmmIchnDispatch.h> +#include <Protocol\PchPlatformPolicy\PchPlatformPolicy.h> +#include <ReferenceCode\Chipset\LynxPoint\Protocol\SmmIchnDispatchEx\SmmIchnDispatchEx.h> +#include <ReferenceCode\Chipset\LynxPoint\Protocol\SmmIoTrapDispatch\SmmIoTrapDispatch.h> +#include <Protocol\SBPlatformData.h> +#include <SBSMI.h> + +//---------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//---------------------------------------------------------------------------- +// Constant Definition(s) +#define GBE_MAX_LOOP_TIME 4000 + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) +#define AMI_SMM_SW_DISPATCH_PROTOCOL EFI_SMM_SW_DISPATCH2_PROTOCOL +#define AMI_SMM_SW_DISPATCH_CONTEXT EFI_SMM_SW_REGISTER_CONTEXT +#define AMI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL +#define AMI_SMM_POWER_BUTTON_DISPATCH_CONTEXT EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT +#define SMM_CHILD_DISPATCH_SUCCESS EFI_SUCCESS +#else +#define AMI_SMM_SW_DISPATCH_PROTOCOL EFI_SMM_SW_DISPATCH_PROTOCOL +#define AMI_SMM_SW_DISPATCH_CONTEXT EFI_SMM_SW_DISPATCH_CONTEXT +#define AMI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL EFI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL +#define AMI_SMM_POWER_BUTTON_DISPATCH_CONTEXT EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT +#define SMM_CHILD_DISPATCH_SUCCESS +#endif + +#ifndef NvramSmiSupport +#define CHECK_BS_VARIABLE 1 +#endif + +#if defined NvramSmiSupport && NvramSmiSupport +#define CHECK_BS_VARIABLE 0 +#else +#define CHECK_BS_VARIABLE 1 +#endif + + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//---------------------------------------------------------------------------- +// Variable and External Declaration(s) +//---------------------------------------------------------------------------- +// Variable Declaration(s) +#if SB_PCIE_ERROR_LOG_SUPPORT + +SB_PCIE_ERROR_LOG_DISPATCH_LINK *gSbPcieErrorLogDispatchHead = 0, *gSbPcieErrorLogDispatchTail = 0; + +UINT32 SBPcieBridge[] = +{ + {(UINT32)SB_PCIE_CFG_ADDRESS(PCIEBRS_BUS, PCIEBRS_DEV, PCIEBRS_FUN, PCI_VID)}, + {(UINT32)SB_PCIE_CFG_ADDRESS(PCIEBRS2_BUS, PCIEBRS2_DEV, PCIEBRS2_FUN, PCI_VID)}, + {(UINT32)SB_PCIE_CFG_ADDRESS(PCIEBRS3_BUS, PCIEBRS3_DEV, PCIEBRS3_FUN, PCI_VID)}, + {(UINT32)SB_PCIE_CFG_ADDRESS(PCIEBRS4_BUS, PCIEBRS4_DEV, PCIEBRS4_FUN, PCI_VID)}, + {(UINT32)SB_PCIE_CFG_ADDRESS(PCIEBRS5_BUS, PCIEBRS5_DEV, PCIEBRS5_FUN, PCI_VID)}, + {(UINT32)SB_PCIE_CFG_ADDRESS(PCIEBRS6_BUS, PCIEBRS6_DEV, PCIEBRS6_FUN, PCI_VID)}, + {(UINT32)SB_PCIE_CFG_ADDRESS(PCIEBRS7_BUS, PCIEBRS7_DEV, PCIEBRS7_FUN, PCI_VID)}, + {(UINT32)SB_PCIE_CFG_ADDRESS(PCIEBRS8_BUS, PCIEBRS8_DEV, PCIEBRS8_FUN, PCI_VID)}, + {0xFFFFFFFF} +}; +#endif + +BOOLEAN gIsLastState = FALSE; +BOOLEAN gPchWakeOnLan = FALSE; +EFI_SMM_ICHN_DISPATCH_PROTOCOL *gIchnDispatch; +EFI_RESET_SYSTEM gSmmResetSystem = NULL; +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) +EFI_SMM_BASE2_PROTOCOL *gSmmBase2; +#endif + +// GUID Definition(s) +#if SB_PCIE_ERROR_LOG_SUPPORT +EFI_GUID gSbPcieErrorLogDispatchProtocolGuid = EFI_SB_PCIE_ERROR_LOG_DISPATCH_PROTOCOL_GUID; +EFI_GUID gElogProtocolGuid = EFI_SM_ELOG_PROTOCOL_GUID; +#endif +EFI_GUID gAmiSbSmiProtocolGuid = AMI_SB_SMI_PROTOCOL_GUID; +EFI_GUID gEfiSmmIchnExDispatchProtocolGuid = EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL_GUID; +EFI_GUID gIchnDispatchProtocolGuid = EFI_SMM_ICHN_DISPATCH_PROTOCOL_GUID; +EFI_GUID gDxePchPlatformPolicyProtocolGuid = DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID; +EFI_GUID gEfiSmmIoTrapDispatchProtocolGuid = EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL_GUID; + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION<0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) +EFI_GUID gSwDispatchProtocolGuid = EFI_SMM_SW_DISPATCH_PROTOCOL_GUID; +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: AddLink +// +// Description: Create and add link to specified list. +// +// Parameters: Size - +// Head - +// Tail - +// +// Returns: VOID Pointer +// +// Modified: +// +// Referrals: SmmAllocatePool +// +// Notes: Here is the control flow of this function: +// 1. Allocate Link in Smm Pool. +// 2. Add Link to end. +// 3. Return Link address. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID * AddLink ( + IN UINT32 Size, + IN VOID **Head, + IN VOID **Tail ) +{ + VOID *Link; + + if (pSmst->SmmAllocatePool(0, Size, &Link) != EFI_SUCCESS) return 0; + + ((GENERIC_LINK*)Link)->Link = 0; + if (!*Head) { + *Head = *Tail = Link; + } else { + ((GENERIC_LINK*)*Tail)->Link = Link; + *Tail = Link; + } + + return Link; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RemoveLink +// +// Description: Remove link from specified list. +// +// Parameters: Handle - EFI Handle +// Head - +// Tail - +// +// Returns: BOOLEAN +// TRUE if link was removed. FALSE if link not in the list. +// +// Modified: +// +// Referrals: SmmFreePool +// +// Notes: Here is the control flow of this function: +// 1. Search link list for Link. +// 2. Remove link from list. +// 3. Free link. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN RemoveLink ( + IN EFI_HANDLE Handle, + IN VOID **Head, + IN VOID **Tail ) +{ + GENERIC_LINK *PrevLink,*Link; + + PrevLink = *Head; + + // Is link first. Link address is the same as the Handle. + if (((GENERIC_LINK*)*Head) == Handle) { + if (PrevLink == *Tail) *Tail = 0; // If Tail = Head, then 0. + *Head = PrevLink->Link; + pSmst->SmmFreePool(PrevLink); + return TRUE; + } + + // Find Link. + for (Link=PrevLink->Link; Link; PrevLink=Link, Link=Link->Link) { + if (Link == Handle) { // Link address is the same as the Handle. + if (Link == *Tail) *Tail = PrevLink; + PrevLink->Link = Link->Link; + pSmst->SmmFreePool(Link); + return TRUE; + } + } + + return FALSE; +} + +#if SB_PCIE_ERROR_LOG_SUPPORT +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSbPcieErrorLogEnRegister +// +// Description: Register a Link on SbPcieErrorLog enable SMI. +// +// Parameters: This - +// Function - +// Context - +// +// +// Returns: Handle - +// EFI_STATUS +// +// Modified: gSbPcieErrorLogDispatchHead, gSbPcieErrorLogDispatchTail +// +// Referrals: AddLink +// +// Notes: Here is the control flow of this function: +// 1. Verify if Context if valid. If invalid, +// return EFI_INVALID_PARAMETER. +// 2. Allocate structure and add to link list. +// 3. Fill link. +// 4. Enable Smi Source. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SbPcieErrorLogRegister ( + IN EFI_SB_PCIE_ERROR_LOG_DISPATCH_PROTOCOL *This, + IN EFI_SB_PCIE_ERROR_LOG_DISPATCH Function, + OUT EFI_HANDLE *Handle ) +{ + SB_PCIE_ERROR_LOG_DISPATCH_LINK *NewLink; + + NewLink = AddLink( sizeof(SB_PCIE_ERROR_LOG_DISPATCH_LINK), \ + &gSbPcieErrorLogDispatchHead, \ + &gSbPcieErrorLogDispatchTail ); + if (!NewLink) return EFI_OUT_OF_RESOURCES; + + NewLink->Function = Function; + *Handle = NewLink; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbPcieErrorLogUnregister +// +// Description: Unregister a Link on SbPcieErrorLog enable SMI. +// +// Parameters: This - +// Handle - +// +// Returns: EFI_STATUS +// +// Modified: gSbPcieErrorLogDispatchHead, gSbPcieErrorLogDispatchTail +// +// Referrals: RemoveLink +// +// Notes: Here is the control flow of this function: +// 1. Remove link. If no link, return EFI_INVALID_PARAMETER. +// 2. Disable SMI Source if no other handlers using source. +// 3. Return EFI_SUCCESS. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SbPcieErrorLogUnregister ( + IN EFI_SB_PCIE_ERROR_LOG_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ + if (!RemoveLink(Handle, &gSbPcieErrorLogDispatchHead, &gSbPcieErrorLogDispatchTail)) + return EFI_INVALID_PARAMETER; + return EFI_SUCCESS; +} +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: CheckReadyFlag +// +// Description: Check ready flag to see if writing to MDIC is done. +// +// Parameters: GbEBar - GbE Memory Base Address Register +// +// Returns: EFI_SUCCESS - Successfully completed. +// EFI_TIMEOUT - Checking flag time out. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS CheckReadyFlag ( IN UINT32 GbEBar ) +{ + UINT32 ReadyFlag; + UINT32 LoopTime; + + ReadyFlag = 0; + + for (LoopTime = 0; LoopTime < GBE_MAX_LOOP_TIME; LoopTime++) { + ReadyFlag = READ_MEM32 (GbEBar + R_PCH_MBARA_GBECSR3) & B_PCH_MBARA_GBECSR3_RB; + + if (ReadyFlag) { + break; + } + + CountTime((10), PM_BASE_ADDRESS); + } + + if (LoopTime >= GBE_MAX_LOOP_TIME) { + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GbES02SxWorkaround +// +// Description: PCH BIOS Spec Rev 0.7.0 Section 10.6 +// Additional Internal GbE Controller special cases WOL Support +// +// Parameters: None +// +// Returns: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID GbES02SxWorkaround ( VOID ) +{ + UINTN PciD25F0RegBase; + UINTN PciD31F0RegBase; + UINT32 GbEBar; + UINT32 GbEBarB; + UINT16 CmdReg; + UINT32 RAL0; + UINT32 RAH0; + UINT32 PhyCtrl; + UINT32 ExtCnfCtrl; + UINT32 Buffer; + UINT32 LoopTime; + UINT32 RootComplexBar; + UINT32 PchGpioBase; + EFI_STATUS Status; + + PciD25F0RegBase = MmPciAddress ( + PCIEX_BASE_ADDRESS, + PCI_BUS_NUMBER_PCH_LAN, + PCI_DEVICE_NUMBER_PCH_LAN, + PCI_FUNCTION_NUMBER_PCH_LAN, + 0 + ); + PciD31F0RegBase = MmPciAddress ( + PCIEX_BASE_ADDRESS, + 0, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ); + RootComplexBar = (READ_MEM32 (PciD31F0RegBase + SB_REG_RCBA)) & ~BIT0; + PchGpioBase = (MmioRead32 (PciD31F0RegBase + R_PCH_LPC_GPIO_BASE)) &~BIT0; + GbEBar = 0; + GbEBarB = 0; + CmdReg = 0; + Buffer = 0; + + if (((MmioRead16 (RootComplexBar + R_PCH_RCRB_BUC)) & BIT5) == 0) { + /// + /// System BIOS requires to program the registers listed below for internal GbE to function upon S0 to S3,4,5 transition + /// (When ME off and GbE device in D0) + /// + /// Note: Time out should be applied for MBARA + Offset 20h[28] verification to avoid non respond loop. Upon time out, + /// system BIOS is required to clear MBARA + Offset F00h [5] = 0b before exiting the WA. + /// + /// Check if GbE device is in D0 state + /// + if ((MmioRead16 (PciD25F0RegBase + R_PCH_LAN_PMCS) & (UINT16) B_PCH_LAN_PMCS_PS) == (UINT16) V_PCH_LAN_PMCS_PS0) { + GbEBar = MmioRead32 (PciD25F0RegBase + R_PCH_LAN_MEM_BASE_A); + /// + /// Step 1 + /// If MBARA + Offset 5800h [0] = 1b then proceed the steps below + /// + if (MmioRead32 (GbEBar + R_PCH_MBARA_GBECSR9) & B_PCH_MBARA_GBECSR9_APME) { + /// + /// Step 2 + /// System BIOS perform read to MBARA + Offset 5400h [31:0], MBARA + Offset 5404h [31:0] + /// and MBARA + Offset F00h [31:0] + /// + RAL0 = MmioRead32 (GbEBar + R_PCH_MBARA_GBECSR7); + RAH0 = MmioRead32 (GbEBar + R_PCH_MBARA_GBECSR8); + ExtCnfCtrl = MmioRead32 (GbEBar + R_PCH_MBARA_GBECSR5); + /// + /// Step 3 + /// Ensure that MBARA + Offset F00h [5] = 1b + /// a. Set MBARA + Offset F00h [31:0] value with the value read in step 2 or with 0x20 (set bit 5) + /// b. Read MBARA + Offset F00h + /// c. If MBARA + Offset F00h [5] = 1b (true) continue else wait X Sec and go back to step 3.b for Y times + /// (X*Y totals to ~200mSec) if false - exit flow by jumping to step 32. + /// + MmioWrite32 (GbEBar + R_PCH_MBARA_GBECSR5, ExtCnfCtrl | B_PCH_MBARA_GBECSR5_SWFLAG); + + for (LoopTime = 0; LoopTime < GBE_MAX_LOOP_TIME; LoopTime++) { + ExtCnfCtrl = MmioRead32 (GbEBar + R_PCH_MBARA_GBECSR5); + + if (ExtCnfCtrl & B_PCH_MBARA_GBECSR5_SWFLAG) { + break; + } + + CountTime((50), PM_BASE_ADDRESS); + } + + if (LoopTime >= GBE_MAX_LOOP_TIME) { + goto ExitGbEWa; + } + /// + /// Step 4 + /// If MBARA + Offset 5B54h [15] = 1b then jump to Step 10 + /// + if ((MmioRead32 (GbEBar + 0x5B54) & BIT15) != BIT15) { + /// + /// Step 5 + /// If MBARA + Offset F10h [2] = 1b, then set MBARA + Offset F10h[1] = 1b. Else clear MBARA + Offset F10h[1] = 0b + /// + if (MmioRead32 (GbEBar + R_PCH_MBARA_GBECSR6) & B_PCH_MBARA_GBECSR6_LPLUND) { + SET_MEM32(GbEBar + R_PCH_MBARA_GBECSR6, (UINT32) B_PCH_MBARA_GBECSR6_LPLUD); + } else { + RESET_MEM32 (GbEBar + R_PCH_MBARA_GBECSR6, (UINT32)B_PCH_MBARA_GBECSR6_LPLUD); + } + /// + /// Step 6 + /// Set MBARA + Offset 20h = 0x043f0000. Verify MBARA + Offset 20h[28] = 1b + /// + MmioWrite32 ((GbEBar + R_PCH_MBARA_GBECSR3), 0x043f0000); + + Status = CheckReadyFlag (GbEBar); + if (EFI_ERROR (Status)) { + goto ExitGbEWa; + } + /// + /// Step 7 + /// Wait 4 mSec + /// + CountTime((4 * 1000), PM_BASE_ADDRESS); + /// + /// Step 8 + /// Set MBARA + Offset 20h = 0x04390000 or with 0x400 or with 0x40 if MBARA + Offset F10h [3] = 1b + /// or with 0x04 if MBARA + Offset F10h [2] = 1b + /// + Buffer = 0x04390000 | 0x400; + if (MmioRead32 (GbEBar + R_PCH_MBARA_GBECSR6) & B_PCH_MBARA_GBECSR6_GbE_DIS) { + Buffer |= 0x40; + } + + if (MmioRead32 (GbEBar + R_PCH_MBARA_GBECSR6) & B_PCH_MBARA_GBECSR6_LPLUND) { + Buffer |= 0x04; + } + + MmioWrite32 ((GbEBar + R_PCH_MBARA_GBECSR3), Buffer); + /// + /// Step 9 + /// Verify MBARA + Offset 20h[28] = 1b + /// + Status = CheckReadyFlag (GbEBar); + if (EFI_ERROR (Status)) { + goto ExitGbEWa; + } + } + /// + /// Step 10 + /// Set MBARA + Offset 20h = 0x043f6400 + /// + MmioWrite32 ((GbEBar + R_PCH_MBARA_GBECSR3), 0x043f6400); + /// + /// Step 11 + /// Wait 4 mSec + /// + CountTime((4 * 1000), PM_BASE_ADDRESS); + /// + /// Step 12 + /// Set MBARA + Offset F10h [6] = 1b (read modify write) + /// + PhyCtrl = MmioRead32 (GbEBar + R_PCH_MBARA_GBECSR6); + MmioWrite32 (GbEBar + R_PCH_MBARA_GBECSR6, PhyCtrl | B_PCH_MBARA_GBECSR6_GGD); + /// + /// Step 13 + /// Verify MBARA + Offset 20h[28] = 1b, set MBARA + Offset 20h = 0x4310010 + /// + Status = CheckReadyFlag (GbEBar); + if (EFI_ERROR (Status)) { + goto ExitGbEWa; + } + + MmioWrite32 ((GbEBar + R_PCH_MBARA_GBECSR3), 0x4310010); + /// + /// Step 14 + /// Verify MBARA + Offset 20h[28] = 1b, set MBARA + Offset 20h = 0x4320000 or with + /// the least significant word of MBARA + offset 5400 that read in step 2 + /// + Status = CheckReadyFlag (GbEBar); + if (EFI_ERROR (Status)) { + goto ExitGbEWa; + } + + MmioWrite32 ((GbEBar + R_PCH_MBARA_GBECSR3), (0x4320000 | (RAL0 & 0x0000FFFF))); + /// + /// Step 15 + /// Verify MBARA + Offset 20h[28] = 1b, set MBARA + Offset 20h = 0x4310011 + /// + Status = CheckReadyFlag (GbEBar); + if (EFI_ERROR (Status)) { + goto ExitGbEWa; + } + + MmioWrite32 ((GbEBar + R_PCH_MBARA_GBECSR3), 0x4310011); + /// + /// Step 16 + /// Verify MBARA + Offset 20h[28] = 1b, set MBARA + Offset 20h = 0x4320000 or with + /// the most significant word of MBARA + offset 5400 that read in step 2 + /// + Status = CheckReadyFlag (GbEBar); + if (EFI_ERROR (Status)) { + goto ExitGbEWa; + } + + MmioWrite32 ((GbEBar + R_PCH_MBARA_GBECSR3), (0x4320000 | (RAL0 >> 16))); + /// + /// Step 17 + /// Verify MBARA + Offset 20h[28] = 1b, set MBARA + Offset 20h = 0x4310012 + /// + Status = CheckReadyFlag (GbEBar); + if (EFI_ERROR (Status)) { + goto ExitGbEWa; + } + + MmioWrite32 ((GbEBar + R_PCH_MBARA_GBECSR3), 0x4310012); + /// + /// Step 18 + /// Verify MBARA + Offset 20h[28] = 1b, set MBARA + Offset 20h = 0x4320000 or with + /// the least significant word of MBARA + offset 5404 that read in step 2 + /// + Status = CheckReadyFlag (GbEBar); + if (EFI_ERROR (Status)) { + goto ExitGbEWa; + } + + MmioWrite32 ((GbEBar + R_PCH_MBARA_GBECSR3), (0x4320000 | (RAH0 & B_PCH_MBARA_GBECSR8_RAH))); + /// + /// Step 19 + /// Verify MBARA + Offset 20h[28] = 1b, set MBARA + Offset 20h = 0x4310013 + /// + Status = CheckReadyFlag (GbEBar); + if (EFI_ERROR (Status)) { + goto ExitGbEWa; + } + + MmioWrite32 ((GbEBar + R_PCH_MBARA_GBECSR3), 0x4310013); + /// + /// Step 20 + /// Verify MBARA + Offset 20h[28] = 1b, set MBARA + Offset 20h = 0x4328000 + /// + Status = CheckReadyFlag (GbEBar); + if (EFI_ERROR (Status)) { + goto ExitGbEWa; + } + + MmioWrite32 ((GbEBar + R_PCH_MBARA_GBECSR3), 0x4328000); + /// + /// Step 21 + /// Verify MBARA + Offset 20h[28] = 1b, set MBARA + Offset 20h = 0x4310001 + /// + Status = CheckReadyFlag (GbEBar); + if (EFI_ERROR (Status)) { + goto ExitGbEWa; + } + + MmioWrite32 ((GbEBar + R_PCH_MBARA_GBECSR3), 0x4310001); + /// + /// Step 22 + /// Verify MBARA + Offset 20h[28] = 1b, set MBARA + Offset 20h = 0x8320000 + /// + Status = CheckReadyFlag (GbEBar); + if (EFI_ERROR (Status)) { + goto ExitGbEWa; + } + + MmioWrite32 ((GbEBar + R_PCH_MBARA_GBECSR3), 0x8320000); + /// + /// Step 23 + /// Verify MBARA + Offset 20h[28] = 1b, TEMP[15:0] = MBARA + Offset 20h [15:0] + /// + Status = CheckReadyFlag (GbEBar); + if (EFI_ERROR (Status)) { + goto ExitGbEWa; + } + + Buffer = MmioRead32 (GbEBar + R_PCH_MBARA_GBECSR3) & B_PCH_MBARA_GBECSR3_DATA; + /// + /// Step 24 + /// Set MBARA + Offset 20h = 0x4320000 or TEMP[15:0] or 0x0001 + /// + MmioWrite32 ((GbEBar + R_PCH_MBARA_GBECSR3), 0x4320000 | Buffer | 0x0001); + /// + /// Step 25 + /// Verify MBARA + Offset 20h[28] = 1b, set MBARA + Offset 20h = 0x43f6460 + /// + Status = CheckReadyFlag (GbEBar); + if (EFI_ERROR (Status)) { + goto ExitGbEWa; + } + + MmioWrite32 ((GbEBar + R_PCH_MBARA_GBECSR3), 0x43f6460); + /// + /// Step 26 + /// Wait 4 mSec + /// + CountTime((4 * 1000), PM_BASE_ADDRESS); + /// + /// Step 27 + /// Verify MBARA + Offset 20h[28] = 1b, set MBARA + Offset 20h = 0x4310042 + /// + Status = CheckReadyFlag (GbEBar); + if (EFI_ERROR (Status)) { + goto ExitGbEWa; + } + + MmioWrite32 ((GbEBar + R_PCH_MBARA_GBECSR3), 0x4310042); + /// + /// Step 28 + /// Verify MBARA + Offset 20h[28] = 1b. + /// + Status = CheckReadyFlag (GbEBar); + if (EFI_ERROR (Status)) { + goto ExitGbEWa; + } + + MmioWrite32 ((GbEBar + R_PCH_MBARA_GBECSR3), 0x43F6020); + + /// + /// Step 29 + /// Wait 4 mSec + /// + CountTime((4 * 1000), PM_BASE_ADDRESS); + + /// + /// Step 30 + /// Verify MBARA + Offset 20h[28] = 1b, set MBARA + Offset 20h = 0x8310000 + /// + Status = CheckReadyFlag (GbEBar); + if (EFI_ERROR (Status)) { + goto ExitGbEWa; + } + + MmioWrite32 ((GbEBar + R_PCH_MBARA_GBECSR3), 0x8310000); + /// + /// Step 31 + /// Verify MBARA + Offset 20h[28] = 1b, TEMP[15:0] = MBARA + 20[15:0] + /// + Status = CheckReadyFlag (GbEBar); + if (EFI_ERROR (Status)) { + goto ExitGbEWa; + } + + Buffer = MmioRead32 (GbEBar + R_PCH_MBARA_GBECSR3) & 0x0000FFFF; + + /// + /// Step 32 + /// Verify MBARA + 20h[28] = 1b, set MBARA + 20h = 4310000h or with the TEMP[15:0] or with 10h + /// + Status = CheckReadyFlag (GbEBar); + if (EFI_ERROR (Status)) { + goto ExitGbEWa; + } + +ExitGbEWa: + + MmioWrite32 ((GbEBar + R_PCH_MBARA_GBECSR3), 0x4310000 | Buffer | 0x10); + /// + /// Step 33 + /// Verify MBARA + Offset 20h[28] = 1b + /// + Status = CheckReadyFlag (GbEBar); + + /// + /// Step 34 + /// Clear MBARA + Offset F00h [5] = 0b (read modify write) + /// + MmioWrite32 ((GbEBar + R_PCH_MBARA_GBECSR5), (ExtCnfCtrl & (UINT32) (~BIT5))); + + } + } + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBPwrBtnHandler +// +// Description: If the power button is pressed, then this function is called. +// +// Input: DispatchHandle - Handle of dispatch function, for when interfacing +// with the parent SMM driver, will be the address of linked +// list link in the call back record. +// DispatchContext - Pointer to the dispatch function's context. +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) +EFI_STATUS SBPwrBtnHandler ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *DispatchContext OPTIONAL, + IN OUT VOID *CommBuffer OPTIONAL, + IN OUT UINTN *CommBufferSize OPTIONAL ) +#else +VOID SBPwrBtnHandler( + IN EFI_HANDLE DispatchHandle, + IN AMI_SMM_POWER_BUTTON_DISPATCH_CONTEXT *DispatchContext) +#endif +{ + +// Usage sample code shows that user how to decide NMI_EN bit is diabled or enabled in SMI. +//#### EFI_CMOS_ACCESS_INTERFACE *CmosInterface; +//#### EFI_STATUS Status; +//#### +//#### LOCATE_CMOS_ACCESS_SMM_PROTOCOL(Status, CmosInterface); +//#### if( !EFI_ERROR(Status) ) { +//#### // Example1:Disable NMI +//#### CmosInterface->Write( CmosInterface, +//#### SB_SSP_NMI_CONTROL_BITS, +//#### DISABLE_NMI_BEFORE_SMI_EXIT ); +//#### // Example2:Enable NMI +//####// CmosInterface->Write( CmosInterface, +//####// SB_SSP_NMI_CONTROL_BITS, +//####// ENABLE_NMI_BEFORE_SMI_EXIT ); +//#### } + + // Program AfterG3 bit depend the setup question. + if (gIsLastState) SET_PCI8_SB(SB_REG_GEN_PMCON_3, 1); // 0xA4 + + if (gPchWakeOnLan) GbES02SxWorkaround(); + + return SMM_CHILD_DISPATCH_SUCCESS; +} + +#if SB_PCIE_ERROR_LOG_SUPPORT +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ElogGenerateNmiNow +// +// Description: Generate NmiNow. +// +// Input: None +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID ElogGenerateNmiNow (VOID) +{ + UINT16 PmBase; + UINT8 SaveNmi2SmiEn; + UINT8 SavePort70; + + // + // Get the PM Base Address + // + PmBase = READ_PCI16_SB (SB_REG_PMBASE) & 0xFF80; + + // Read the NMI2SMI_EN bit, save it for future restore + SaveNmi2SmiEn = READ_IO8(PmBase + TCO1_CNT_OFFSET + 1); + + // Set the NMI2SMI_EN bit to 0 + RESET_IO8(PmBase + TCO1_CNT_OFFSET + 1, BIT01); + + SavePort70 = ReadPort70h(); //Improve alternate access mode + + // Enable NMI_EN + WRITE_IO8(CMOS_ADDR_PORT, (SavePort70 & ~BIT07)); //Improve alternate access mode + + // Set NMI_NOW = 1 + SET_IO8(PmBase + TCO1_CNT_OFFSET + 1, BIT00); + + // Clear NMI_NOW = 0 by writing 1 to NMI_NOW bit + RESET_IO8(PmBase + TCO1_CNT_OFFSET + 1, BIT00); + + // Restore NMI2SMI_EN + WRITE_IO8(PmBase + TCO1_CNT_OFFSET + 1, SaveNmi2SmiEn); + + // Clear the DMISERR_STS bit, bit 12 + WRITE_IO16(PmBase + TCO1_STS_OFFSET, BIT12); + + // Clear the NMI2SMI_STS bit if set + if ((READ_IO16(PmBase + TCO1_STS_OFFSET)) & 0x0001) { + // check port 0x61 + if (READ_IO8(NMI_SC_PORT) & 0x80) { + SET_IO8(NMI_SC_PORT, BIT02); + RESET_IO8(NMI_SC_PORT, BIT02); + } + } + + // Restore NMI_EN + WRITE_IO8(CMOS_ADDR_PORT, SavePort70); + + return; + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBErrLogHandler +// +// Description: South bridge error logging handler. +// +// Input: DispatchHandle - Handle of dispatch function, for when interfacing +// with the parent SMM driver, will be the address of linked +// list link in the call back record. +// DispatchContext - Pointer to the dispatch function's context. +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID SBErrLogHandler ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_ICHN_DISPATCH_CONTEXT *DispatchContext +) +{ + EFI_STATUS Status = EFI_SUCCESS; + SB_PCIE_ERROR_LOG_DISPATCH_LINK *Link; + SB_PCIE_ERR ErrorInfo; + UINT8 i; + UINT8 CapPtr; + UINT16 PciStatus; + UINT16 PcieStatus; + UINT16 DeviceStatus; + UINT32 DevBaseAddr; + + if (READ_IO8(NMI_SC_PORT) & BIT7) // SERR#_NMI_STS? + { + // Clear SERR#_NMI_STS & NMI2SMI_STS by set Port 61h[2] = 1 then set it to 0. + SET_IO8(NMI_SC_PORT, BIT02); + RESET_IO8(NMI_SC_PORT, BIT02); + + for (i = 0; SBPcieBridge[i] != 0xFFFFFFFF; i++) + { + DevBaseAddr = SBPcieBridge[i]; + if (READ_MEM32(DevBaseAddr) == 0xFFFFFFFF) + continue; + + PciStatus = READ_MEM16(DevBaseAddr + 0x06); + PcieStatus = READ_MEM16(DevBaseAddr + 0x1E); + + CapPtr = SbFindCapPtr(DevBaseAddr, 0x10); + if (CapPtr != 0) + DeviceStatus = READ_MEM16(DevBaseAddr + CapPtr + 0x0A); + + if ((PciStatus & (BIT8 | BIT15)) || (PcieStatus & (BIT8 | BIT15))) + ErrorInfo.ParityError = TRUE; + else + ErrorInfo.ParityError = FALSE; + + if ((PciStatus & BIT14) || (PcieStatus & BIT14)) + ErrorInfo.SystemError = TRUE; + else + ErrorInfo.SystemError = FALSE; + + if ((ErrorInfo.ParityError) || (ErrorInfo.SystemError)) { + ErrorInfo.PcieAddress = DevBaseAddr; + ErrorInfo.Bus = (DevBaseAddr >> 20) & ((UINT8)((PCIEX_LENGTH >> 20) - 1)); + ErrorInfo.Dev = (DevBaseAddr >> 15) & 0x1F; + ErrorInfo.Fun = (DevBaseAddr >> 12) & 0x07; + ErrorInfo.VendorId = READ_MEM16(DevBaseAddr + 0x00); + ErrorInfo.DeviceId = READ_MEM16(DevBaseAddr + 0x02); + ErrorInfo.PciCommand = READ_MEM16(DevBaseAddr + 0x04); + ErrorInfo.PciCCode = READ_MEM16(DevBaseAddr + 0x0A); + ErrorInfo.BridgeControl = READ_MEM16(DevBaseAddr + 0x3E); + ErrorInfo.Version = READ_MEM8(DevBaseAddr + CapPtr + 0x02) & 0x0F; + ErrorInfo.PortType = (UINT32)((READ_MEM8(DevBaseAddr + CapPtr + 0x02) & 0xF0) >> 4); + + if (CapPtr != 0) { + ErrorInfo.Correctable = (DeviceStatus & BIT0)? TRUE : FALSE; + ErrorInfo.NonFatal = (DeviceStatus & BIT1)? TRUE : FALSE; + ErrorInfo.Fatal = (DeviceStatus & BIT2)? TRUE : FALSE; + } + + // Clear Error status + WRITE_MEM16(DevBaseAddr + 0x06, PciStatus); + WRITE_MEM16(DevBaseAddr + 0x1E, PcieStatus); + + if (CapPtr != 0) + // Clear Error Status + WRITE_MEM16(DevBaseAddr + CapPtr + 0x0A, DeviceStatus); + +//#### if (!ErrorInfo.Correctable) +//#### ElogGenerateNmiNow(); + + for(Link = gSbPcieErrorLogDispatchHead; Link; Link = Link->Link) { + Link->Function(Link, ErrorInfo); + } + } // if ((ErrorInfo.ParityError) || (ErrorInfo.SystemError)) + } + } +} + + +//---------------------------------------------------------------------------- +VOID InitSbSmiLogic(VOID) +{ +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitSbSmiLogicHandler +// +// Description: Initialize SB SMI Logic Handler. +// This handler should be performed in ready to boot +// and S3 rerume. +// +// Input: DispatchHandle - Handle of dispatch function, for when interfacing +// with the parent SMM driver, will be the address of linked +// list link in the call back record. +// DispatchContext - Pointer to the dispatch function's context. +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) +EFI_STATUS InitSbSmiLogicHandler ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *DispatchContext OPTIONAL, + IN OUT VOID *CommBuffer OPTIONAL, + IN OUT UINTN *CommBufferSize OPTIONAL ) +#else +VOID InitSbSmiLogicHandler ( + IN EFI_HANDLE DispatchHandle, + IN AMI_SMM_SW_DISPATCH_CONTEXT *DispatchContext) +#endif +{ + UINT32 PmBase; + UINT32 Buffer32; + + PmBase = READ_PCI16_SB (SB_REG_PMBASE) & 0xFF80; + + // + //Every SERR (System Erors) will generate NMI. So route NMI as a SMI to handle Errors + //Steps to route NMI as a SMI + //Enable NMI2SMI_EN bit in TCO1 Control Register + //UnMask NMI Enable bit in NMI Enable (and Real Time Clock Index) Register + // + + // Set NMI2SMI_EN = '1b', TCO_BASE + 08h[9] + SET_IO16_PM(TCO1_CNT_OFFSET, BIT09); + + // Enable NMI by set Port 70h[7] = '0b' + SwitchAlternateAccessMode (TRUE); //Improve alternate access mode + RESET_IO8(CMOS_ADDR_PORT, BIT07); + SwitchAlternateAccessMode (FALSE); //Improve alternate access mode + + // + //Clear all Spurious Sources of the SMI. + // + Buffer32 = READ_IO32_PM(SMI_STS_OFFSET); + WRITE_IO32_PM(SMI_STS_OFFSET, Buffer32); + + Buffer32 = READ_IO32_PM(TCO1_STS_OFFSET); + WRITE_IO32_PM(TCO1_STS_OFFSET, Buffer32); + + SET_IO8(NMI_SC_PORT, BIT02); + RESET_IO8(NMI_SC_PORT, BIT02); + + return SMM_CHILD_DISPATCH_SUCCESS; +} + +EFI_SB_PCIE_ERROR_LOG_DISPATCH_PROTOCOL gEfiSbPcieErrorLogDispatchProtocol = \ + {SbPcieErrorLogRegister, SbPcieErrorLogUnregister}; +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetSbSmiContext +// +// Description: This is a template SB SMI GetContext for Porting. +// +// Input: None +// +// Output: BOOLEAN +// +// Notes: Here is the control flow of this function: +// 1. Check if NB Smi source. +// 2. If yes, return TRUE. +// 3. If not, return FALSE. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN GetSbSmiContext (VOID) +{ + return FALSE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbSmiHandler +// +// Description: This is a template SB SMI Handler for Porting. +// +// Input: None +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SbSmiHandler (VOID) +{ + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbIchnExGpioUnlockSmiHandler +// +// Description: If the GPIO Lockdown Enable(GLE, B0:D31:F0 R4Ch[0]) bit is +// changed from 1 to 0, then this function is called. +// +// Input: DispatchHandle - EFI Handle +// DispatchContext - Pointer to the EFI_SMM_ICHN_DISPATCH_EX_CONTEXT +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID SbIchnExGpioUnlockSmiHandler ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_ICHN_DISPATCH_EX_CONTEXT *DispatchContext ) +{ + // Set GPIO Lockdown Enable(GLE) bit. + SET_PCI8_SB(SB_REG_GC, BIT00); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: PchBiosWpCallback +// +// Description: This hardware SMI handler will be run every time the BIOS Write Enable bit is set. +// +// Input: DispatchHandle Not used +// DispatchContext Not used +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +static +VOID +PchBiosWpCallback ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_ICHN_DISPATCH_CONTEXT *DispatchContext + ) +{ +#if CHECK_BS_VARIABLE + // Do not need to check the BS attribute variable + // if NvramSmi is enabled. + EFI_STATUS Status; + SB_PLATFORM_DATA SbPlatformData; + EFI_GUID SetupGuid = SETUP_GUID; + UINTN VarSize; + + VarSize = sizeof(SB_PLATFORM_DATA); + Status = pRS->GetVariable( + L"SbPlatformData", + &SetupGuid, + NULL, + &VarSize, + &SbPlatformData ); + if(!EFI_ERROR(Status) || (Status == EFI_ACCESS_DENIED)) return; +#endif + // + // Disable BIOSWE bit to protect BIOS + // + RESET_PCI8_SB(R_PCH_LPC_BIOS_CNTL, B_PCH_LPC_BIOS_CNTL_BIOSWE); + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: PchBiosLockIoTrapCallback +// +// Description: Register an IchnBiosWp callback function to handle TCO BIOSWR SMI +// SMM_BWP and BLE bits will be set here +// +// Input: DispatchHandle Not used +// DispatchContext Not used +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID PchBiosLockIoTrapCallback ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_IO_TRAP_DISPATCH_CALLBACK_CONTEXT *DispatchContext ) +{ + EFI_STATUS Status; + EFI_SMM_ICHN_DISPATCH_CONTEXT IchnContext; + EFI_HANDLE IchnHandle = NULL; + + if (READ_PCI8_SB(R_PCH_LPC_BIOS_CNTL) & B_PCH_LPC_BIOS_CNTL_BLE) { + return; + } + + if ((DispatchContext->Type != WriteTrap) || (DispatchContext->WriteData != PCH_BWP_SIGNATURE)) { + return; + } + + if (gIchnDispatch == NULL) { + return; + } + +#if defined NvramSmiSupport && NvramSmiSupport +#if SMM_BIOS_WRITE_PROTECT_DISABLE + // + // Set SMM_BWP bit before registering IchnBiosWp + // + SET_PCI8_SB(R_PCH_LPC_BIOS_CNTL, B_PCH_LPC_BIOS_CNTL_SMM_BWP); +#endif +#endif + // + // Register an IchnBiosWp callback function to handle TCO BIOSWR SMI + // + IchnContext.Type = IchnBiosWp; + Status = gIchnDispatch->Register ( + gIchnDispatch, + PchBiosWpCallback, + &IchnContext, + &IchnHandle + ); + ASSERT_EFI_ERROR (Status); + + return; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbChildDispatcher +// +// Description: South Bridge SMM Child Dispatcher Handler. +// +// Input: SmmImageHandle - +// *CommunicationBuffer - OPTIONAL +// *SourceSize - OPTIONAL +// +// Output: EFI_STATUS +// +// Modified: +// +// Referrals: EfiSmmSwDispatch EfiSmmSxDispatch +// +// Notes: Here is the control flow of this function: +// 1. Read SMI source status registers. +// 2. If source, call handler. +// 3. Repeat #2 for all sources registered. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SbChildDispatcher ( +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *DispatchContext OPTIONAL, + IN OUT VOID *CommBuffer OPTIONAL, + IN OUT UINTN *CommBufferSize OPTIONAL ) +#else + IN EFI_HANDLE SmmImageHandle, + IN OUT VOID *CommunicationBuffer OPTIONAL, + IN OUT UINTN *SourceSize OPTIONAL ) +#endif +{ + if (GetSbSmiContext()) SbSmiHandler(); + + return EFI_HANDLER_SUCCESS; +} + +//<AMI_PHDR_START> //EIP104199 >> +//---------------------------------------------------------------------------- +// +// Procedure: DummyTcoSmiCallback +// +// Description: +// +// Input: +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +static VOID DummyTcoSmiCallback ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_ICHN_DISPATCH_CONTEXT *DispatchContext + ) +{ + // Dummy routine for clear any unexpected TCO SMIs status. +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RegisterAllTcoSmiDummyHandler +// +// Description: +// +// Input: None +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID RegisterAllTcoSmiDummyHandler ( VOID ) +{ + EFI_STATUS Status; + EFI_HANDLE IchnHandle[12]; + EFI_SMM_ICHN_DISPATCH_CONTEXT IchnContext[12]; + UINT8 Index=0; + + IchnContext[0].Type = IchnMch; + IchnContext[1].Type = IchnPme; + IchnContext[2].Type = IchnRtcAlarm; + IchnContext[3].Type = IchnRingIndicate; + IchnContext[4].Type = IchnAc97Wake; + IchnContext[5].Type = IchnSerialIrq; + IchnContext[6].Type = IchnY2KRollover; + IchnContext[7].Type = IchnTcoTimeout; + IchnContext[8].Type = IchnOsTco; + IchnContext[9].Type = IchnNmi; + IchnContext[10].Type = IchnIntruderDetect; + IchnContext[11].Type = IchnBiosWp; + + for(Index = 0; Index<12; Index++){ + Status = gIchnDispatch->Register ( + gIchnDispatch, + DummyTcoSmiCallback, + &IchnContext[Index], + &IchnHandle[Index] + ); + ASSERT_EFI_ERROR (Status); + } +} + //EIP104199 << +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InSmmFunction +// +// Description: Installs North Bridge SMM Child Dispatcher Handler. +// +// Input: ImageHandle - Image handle +// *SystemTable - Pointer to the system table +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS InSmmFunction ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + AMI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL *PowerButton; +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) + AMI_SMM_POWER_BUTTON_DISPATCH_CONTEXT DispatchContext = {EfiPowerButtonEntry}; + EFI_HANDLE RootHandle; +#else + AMI_SMM_POWER_BUTTON_DISPATCH_CONTEXT DispatchContext = {PowerButtonEntry}; + EFI_SMM_BASE_PROTOCOL *SmmBaseProtocol; +#endif + EFI_HANDLE Handle = NULL; + EFI_STATUS Status; + AMI_S3_SAVE_PROTOCOL *BootScriptSave; + + EFI_HANDLE DummyHandle = NULL; +#if SB_PCIE_ERROR_LOG_SUPPORT + EFI_SM_ELOG_PROTOCOL *GenericElogProtocol = NULL; + AMI_SMM_SW_DISPATCH_CONTEXT SbErrorLogS3PatchContext = {SW_SMI_SB_EL_S3}; + EFI_SMM_ICHN_DISPATCH_CONTEXT IchnContext; +#endif + EFI_SMM_ICHN_DISPATCH_EX_CONTEXT IchnExContext; + EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL *pIchnExDispatch; + + SB_SETUP_DATA *SbSetupData = NULL; + UINTN VariableSize = sizeof(SB_SETUP_DATA); + DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy; + EFI_HANDLE SwHandle = NULL; + AMI_SMM_SW_DISPATCH_PROTOCOL *SwDispatch; +// AMI_SMM_SW_DISPATCH_CONTEXT SwContext; +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) + EFI_SMM_SYSTEM_TABLE2 *pSmst2; +#endif + EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL *PchIoTrap; + EFI_HANDLE PchIoTrapHandle; + EFI_SMM_IO_TRAP_DISPATCH_REGISTER_CONTEXT PchIoTrapContext; + // + // Locate PCH Platform Policy protocol + // + Status = pBS->LocateProtocol ( &gDxePchPlatformPolicyProtocolGuid, \ + NULL, \ + &PchPlatformPolicy); + if (EFI_ERROR (Status)) return Status; + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) + Status = InitAmiSmmLib( ImageHandle, SystemTable ); + + // We are in SMM, retrieve the pointer to SMM System Table + Status = gSmmBase2->GetSmstLocation( gSmmBase2, &pSmst2); + if (EFI_ERROR(Status)) return EFI_UNSUPPORTED; + +#else + Status = pBS->LocateProtocol( &gEfiSmmBaseProtocolGuid, \ + NULL, \ + &SmmBaseProtocol ); +#endif + if (EFI_ERROR(Status)) return Status; + + + Status = pBS->LocateProtocol( AMI_S3_SAVE_PROTOCOL_GUID, \ + NULL, \ + &BootScriptSave ); + + Status = pBS->AllocatePool( EfiBootServicesData, \ + VariableSize, \ + &SbSetupData ); + + GetSbSetupData( pRS, SbSetupData, FALSE ); + + gPchWakeOnLan = (SbSetupData->PchWakeOnLan == 1) ? TRUE : FALSE; + gIsLastState = (SbSetupData->LastState == 2) ? TRUE : FALSE; + + Status = pBS->FreePool( SbSetupData ); + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) + Status = pSmst2->SmmLocateProtocol( &gEfiSmmPowerButtonDispatch2ProtocolGuid, \ + NULL, \ + &PowerButton ); +#else + Status = pBS->LocateProtocol( + &gEfiSmmPowerButtonDispatchProtocolGuid, + NULL, + &PowerButton + ); +#endif + + if (EFI_ERROR(Status)) return Status; + + Status = PowerButton->Register( PowerButton, + SBPwrBtnHandler, + &DispatchContext, + &Handle ); + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) + Status = pSmst2->SmmLocateProtocol( &gEfiSmmSwDispatch2ProtocolGuid, \ + NULL, \ + &SwDispatch ); +#else + Status = pBS->LocateProtocol( &gSwDispatchProtocolGuid, \ + NULL, \ + &SwDispatch ); +#endif + + if (EFI_ERROR(Status)) return Status; + + Status = pBS->LocateProtocol ( &gIchnDispatchProtocolGuid, \ + NULL, \ + &gIchnDispatch ); + if (EFI_ERROR(Status)) return Status; + +#if REGISTER_ALL_TCO_SMI_IN_DUMMY //EIP104199 >> +//Please define this token if need support this function. + RegisterAllTcoSmiDummyHandler(); +#endif //EIP104199 << + +#if SB_PCIE_ERROR_LOG_SUPPORT + Status = pBS->LocateProtocol( &gElogProtocolGuid, + NULL, + &GenericElogProtocol ); + if (!EFI_ERROR (Status)) { + + Status = SwDispatch->Register( SwDispatch, \ + InitSbSmiLogicHandler, \ + &SbErrorLogS3PatchContext, \ + &Handle ); + if (EFI_ERROR(Status)) return Status; + + ASSERT_EFI_ERROR (Status); + + IchnContext.Type = IchnNmi; + Status = gIchnDispatch->Register( gIchnDispatch, \ + SBErrLogHandler, \ + &IchnContext, \ + &Handle ); + ASSERT_EFI_ERROR (Status); + + Status = pBS->InstallProtocolInterface( &DummyHandle, \ + &gSbPcieErrorLogDispatchProtocolGuid, \ + EFI_NATIVE_INTERFACE, \ + &gEfiSbPcieErrorLogDispatchProtocol ); + } + +#endif + + if (PchPlatformPolicy->LockDownConfig->GpioLockDown == PCH_DEVICE_ENABLE) { + Status = pBS->LocateProtocol( &gEfiSmmIchnExDispatchProtocolGuid, \ + NULL, \ + &pIchnExDispatch ); + if (!EFI_ERROR(Status)) { + IchnExContext.Type = IchnExGpioUnlock; + Status = pIchnExDispatch->Register( pIchnExDispatch, \ + SbIchnExGpioUnlockSmiHandler, \ + &IchnExContext, \ + &Handle ); + } + } + + if (PchPlatformPolicy->LockDownConfig->BiosLock == PCH_DEVICE_ENABLE) { + /// + /// Locate the PCH IO TRAP Dispatch protocol + /// + PchIoTrapHandle = NULL; + Status = pBS->LocateProtocol (&gEfiSmmIoTrapDispatchProtocolGuid, NULL, &PchIoTrap); + ASSERT_EFI_ERROR (Status); + + if (!EFI_ERROR(Status)) { + /// + /// Register BIOS Lock IO Trap SMI handler + /// + PchIoTrapContext.Type = WriteTrap; + PchIoTrapContext.Length = 4; + PchIoTrapContext.Address = PchPlatformPolicy->LockDownConfig->PchBiosLockIoTrapAddress; + PchIoTrapContext.Context = NULL; + PchIoTrapContext.MergeDisable = FALSE; + Status = PchIoTrap->Register ( + PchIoTrap, + PchBiosLockIoTrapCallback, + &PchIoTrapContext, + &PchIoTrapHandle ); + if (EFI_ERROR(Status)) return Status; + + if ((PchPlatformPolicy->LockDownConfig->PchBiosLockIoTrapAddress == 0) && + (PchIoTrapContext.Address == 0)) { + TRACE((TRACE_ALWAYS, "Invalid PchIoTrapContext.Address!!!\n")); + } else { + if ((PchPlatformPolicy->LockDownConfig->PchBiosLockIoTrapAddress != 0) && + (PchPlatformPolicy->LockDownConfig->PchBiosLockIoTrapAddress != PchIoTrapContext.Address)) { + TRACE((TRACE_ALWAYS, "Invalid PchIoTrapContext.Address!!!\n")); + } else { + PchPlatformPolicy->LockDownConfig->PchBiosLockIoTrapAddress = PchIoTrapContext.Address; + } + } + } + + } + + Status = pBS->InstallProtocolInterface( &DummyHandle, \ + &gAmiSbSmiProtocolGuid, \ + EFI_NATIVE_INTERFACE, \ + NULL ); + + // Register Callbacks +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) + Status = pSmst2->SmiHandlerRegister( SbChildDispatcher, \ + NULL, \ + &RootHandle ); +#else + Status = SmmBaseProtocol->RegisterCallback( SmmBaseProtocol, \ + ImageHandle, \ + SbChildDispatcher, \ + FALSE, \ + FALSE ); +#endif + + // Update SMM Runtime Service Table + pRS->ResetSystem = gSmmResetSystem; + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NotInSmmFunction +// +// Description: This function is called from outside of SMM during SMM registration. +// +// Input: IN EFI_HANDLE ImageHandle +// IN EFI_SYSTEM_TABLE *SystemTable +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NotInSmmFunction( IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable) +{ + UINT16 Value = 0; + +#if defined PowerButton_SUPPORT && PowerButton_SUPPORT == 0 + //Clear All PM Statuses + Value = IoRead16(PM_BASE_ADDRESS); + IoWrite16(PM_BASE_ADDRESS,Value); + + //Enable PowerButton and Global Enable + IoWrite16(PM_BASE_ADDRESS + 0x02, BIT05 + BIT08); +#endif + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitializeSBSmm +// +// Description: Installs North Bridge SMM Child Dispatcher Handler. +// +// Input: ImageHandle - Image handle +// *SystemTable - Pointer to the system table +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS InitializeSBSmm ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + InitAmiLib(ImageHandle, SystemTable); + + gSmmResetSystem = pRS->ResetSystem; + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) + Status = SystemTable->BootServices->LocateProtocol( \ + &gEfiSmmBase2ProtocolGuid, \ + NULL, \ + &gSmmBase2 ); + ASSERT_EFI_ERROR(Status); +#endif + + return InitSmmHandler(ImageHandle, SystemTable, InSmmFunction, NotInSmmFunction); +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/SBSMI.cif b/Chipset/SB/SBSMI.cif new file mode 100644 index 0000000..45f5dbb --- /dev/null +++ b/Chipset/SB/SBSMI.cif @@ -0,0 +1,12 @@ +<component> + name = "SB SMI" + category = ModulePart + LocalRoot = "Chipset\SB" + RefName = "SBSMI" +[files] +"SBSMI.sdl" +"SBSMI.c" +"SBSMI.h" +"SBSMI.mak" +"SBSMI.dxs" +<endComponent> diff --git a/Chipset/SB/SBSMI.dxs b/Chipset/SB/SBSMI.dxs new file mode 100644 index 0000000..eeaa9c4 --- /dev/null +++ b/Chipset/SB/SBSMI.dxs @@ -0,0 +1,84 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SB SMI/SBSMI.dxs 3 8/13/12 10:31a Victortu $ +// +// $Revision: 3 $ +// +// $Date: 8/13/12 10:31a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SB SMI/SBSMI.dxs $ +// +// 3 8/13/12 10:31a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Implement BIOS Lock function. +// [Files] SBCspLib.h, SBDxe.c, SBSMI.c, SBSMI.dxs, SBSMI.sdl +// +// 2 4/25/12 9:27a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Remove unnecessary dependence. +// [Files] AcpiModeEnable.dxs; SBSMI.dxs; SleepSmi.dxs +// +// 1 2/08/12 8:31a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SBSmi.dxs +// +// Description: This file is the dependency file for the South Bridge SMI +// handler. +// +//<AMI_FHDR_END> +//************************************************************************* +#include <token.h> + +#include <Protocol\SmmSwDispatch.h> + +#include <Edk\Foundation\Framework\Protocol\SmmIchnDispatch\SmmIchnDispatch.h> +#include <ReferenceCode\Chipset\LynxPoint\Protocol\SmmIchnDispatchEx\SmmIchnDispatchEx.h> +#include <ReferenceCode\Chipset\LynxPoint\Protocol\SmmIoTrapDispatch\SmmIoTrapDispatch.h> +#if SB_PCIE_ERROR_LOG_SUPPORT +#include <Protocol\GenericElog.h> +#endif + +DEPENDENCY_START +#if SB_PCIE_ERROR_LOG_SUPPORT + EFI_SM_ELOG_PROTOCOL_GUID AND +#endif + EFI_SMM_SW_DISPATCH_PROTOCOL_GUID AND + EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL_GUID AND + EFI_SMM_ICHN_DISPATCH_PROTOCOL_GUID AND + EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL_GUID +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/SBSMI.h b/Chipset/SB/SBSMI.h new file mode 100644 index 0000000..d6e8542 --- /dev/null +++ b/Chipset/SB/SBSMI.h @@ -0,0 +1,77 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SB SMI/SBSMI.h 4 12/30/13 5:59a Barretlin $ +// +// $Revision: 4 $ +// +// $Date: 12/30/13 5:59a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SB SMI/SBSMI.h $ +// +// 4 12/30/13 5:59a Barretlin +// [TAG] EIP144559 +// [Category] Improvement +// [Description] S3 can't resume via USB KB & MS under usb3.0 port in +// special case +// [Files] SBSMI.c SBSMI.h SBGeneric.c +// +// 3 4/19/13 6:35a Wesleychen +// [TAG] None +// [Category] Improvement +// [Description] Update GbES02SxWorkaround() and add +// UsbS02SxWorkaround() for SBPwrBtnHandler(). +// [Files] SBSMI.c; SBSMI.h; SBGeneric.c; SBCspLib.h +// +// 1 2/08/12 8:31a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +//************************************************************************* +// +// Name: SBSMI.h +// +// Description: This file contains all definitions for South Bridge SMI +// driver +// +//************************************************************************* +//<AMI_FHDR_END> + +#ifndef _SBSMI_H_ +#define _SBSMI_H_ + +// Type Definition(s) + +// Prototypes +VOID SbSmiHandler ( VOID ); + +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/SBSMI.mak b/Chipset/SB/SBSMI.mak new file mode 100644 index 0000000..912df89 --- /dev/null +++ b/Chipset/SB/SBSMI.mak @@ -0,0 +1,80 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SB SMI/SBSMI.mak 1 2/08/12 8:31a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 8:31a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SB SMI/SBSMI.mak $ +# +# 1 2/08/12 8:31a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: SBSMI.MAK +# +# Description: Make file for the SB SMI handler code +# +#<AMI_FHDR_END> +#************************************************************************* +!IFNDEF PI_SPECIFICATION_VERSION +PI_SPECIFICATION_VERSION = 0 +!ENDIF + +all : SBSMI + +SBSMI: $(BUILD_DIR)\SBSMI.mak SBSMIBin + +$(BUILD_DIR)\SBSMI.mak : $(SB_SMI_PATH)\SBSMI.cif $(SB_SMI_PATH)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(SB_SMI_PATH)\SBSMI.cif $(CIF2MAK_DEFAULTS) + +SBSMIBin : $(AMIDXELIB) $(AMICSPLib) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\SBSMI.mak all\ + "CFLAGS=$(CFLAGS) $(SB_INCLUDES) $(INTEL_PCH_INCLUDES)"\ + OBJECTS="$(SB_SMI_OBJECTS)" \ + GUID=7B8DB049-C7C7-4d3b-809F-926DEE47CCA2\ + ENTRY_POINT=InitializeSBSmm\ +!IF $(PI_SPECIFICATION_VERSION) >= 0x1000A && $(CORE_COMBINED_VERSION) >= 0x4028B + TYPE=BS_DRIVER \ + DEPEX1=$(SB_SMI_PATH)\SBSmi.DXS \ +!ELSE + TYPE=BS_DRIVER \ + DEPEX1=$(SB_SMI_PATH)\SBSmi.DXS DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ +!ENDIF + COMPRESS=1 + +# {7B8DB049-C7C7-4d3b-809F-926DEE47CCA2} +# {0x7b8db049, 0xc7c7, 0x4d3b, 0x80, 0x9f, 0x92, 0x6d, 0xee, 0x47, 0xcc, 0xa2} + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/SB/SBSMI.sdl b/Chipset/SB/SBSMI.sdl new file mode 100644 index 0000000..5d97b3c --- /dev/null +++ b/Chipset/SB/SBSMI.sdl @@ -0,0 +1,114 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SB SMI/SBSMI.sdl 2 8/13/12 10:31a Victortu $ +# +# $Revision: 2 $ +# +# $Date: 8/13/12 10:31a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SB SMI/SBSMI.sdl $ +# +# 2 8/13/12 10:31a Victortu +# [TAG] None +# [Category] Improvement +# [Description] Implement BIOS Lock function. +# [Files] SBCspLib.h, SBDxe.c, SBSMI.c, SBSMI.dxs, SBSMI.sdl +# +# 1 2/08/12 8:31a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "SBSMI_SUPPORT" + Value = "1" + Help = "Main switch to enable SB SMI support in Project" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Master = Yes +End + +TOKEN + Name = "SW_SMI_SB_EL_S3" + Value = "0xb9" + Help = "Value to be written into SMI command register \to enable S3 patched codes" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "SB_PCIE_ERROR_LOG_SUPPORT" + Value = "1" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Token = "ErrorLogging_SUPPORT" "=" "1" + Token = "IpmiLib_SUPPORT" "=" "1" + Token = "SmmRuntime_SUPPORT" "=" "1" +End + +TOKEN + Name = "SMM_BIOS_WRITE_PROTECT_DISABLE" + Value = "1" + Help = "SMM BIOS Write Protect Disable(SMM_BWP, B0:D31:F0 Reg#DCh[5]).\0 = BIOS region SMM protection is disabled.\1 = BIOS region SMM protection is enabled." + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Token = "NvramSmiSupport" "=" "1" +End + +PATH + Name = "SB_SMI_PATH" + Path = "Chipset\SB" +End + +MODULE + Help = "Includes SBSMI.mak to Project" + File = "SBSMI.mak" +End + +ELINK + Name = "$(BUILD_DIR)\SBSMI.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + +ELINK + Name = "SB_SMI_OBJECTS" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "$(BUILD_DIR)\$(SB_CHIPSET_DIR)\SBSMI.obj" + Parent = "SB_SMI_OBJECTS" + InvokeOrder = AfterParent +End + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/SB/SBSmm.c b/Chipset/SB/SBSmm.c new file mode 100644 index 0000000..1c1337a --- /dev/null +++ b/Chipset/SB/SBSmm.c @@ -0,0 +1,648 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SBSmm.c 2 3/19/13 8:20a Scottyang $ +// +// $Revision: 2 $ +// +// $Date: 3/19/13 8:20a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SBSmm.c $ +// +// 2 3/19/13 8:20a Scottyang +// [TAG] EIP118158 +// [Category] Improvement +// [Description] Correct SBLib_CmosRead () offset. +// [Files] SmiHandlerPorting2.c, SBDxe.c, SBGeneric.c, SBSmm.c, +// SmiHandlerPorting.c +// +// 1 2/08/12 8:24a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* + + +//<AMI_FHDR_START> +//---------------------------------------------------------------------------- +// +// Name: SBSMM.C +// +// Description: This file contains code for SMM control - the +// protocol defined by Framework +// +//---------------------------------------------------------------------------- +//<AMI_FHDR_END> + + +// Module specific Includes +#include <Efi.h> +#include <token.h> +#include <HOB.h> +#include <DXE.h> +#include <AmiLib.h> +#include <AmiDxeLib.h> +#include <AmiCspLib.h> + +// Used Protocols +#include <Protocol\PciRootBridgeIo.h> +#include <Protocol\BootScriptSave.h> +#include <Protocol\SmmAccess.h> +// Produced Protocols +#include <Protocol\SmmControl.h> +#if PI_SPECIFICATION_VERSION >= 0x0001000A +#include <Protocol\SmmControl2.h> +#endif + +// Function Prototypes +typedef struct { + UINT8 IoReg8; + UINT32 Value32; +} PMIO_BOOT_SCRIPT_STRUCT; + +EFI_STATUS +SBSMM_ClearSMI( + IN EFI_SMM_CONTROL_PROTOCOL *This, + IN BOOLEAN Periodic OPTIONAL +); + +VOID SBSMM_BootScript(); + +EFI_STATUS +SBSMM_TriggerSMI( + IN EFI_SMM_CONTROL_PROTOCOL *This, + IN OUT INT8 *ArgumentBuffer OPTIONAL, + IN OUT UINTN *ArgumentBufferSize OPTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OPTIONAL +); + +EFI_STATUS +SBSMM_GetRegisterInfo( + IN EFI_SMM_CONTROL_PROTOCOL *This, + IN OUT EFI_SMM_CONTROL_REGISTER *SmiRegister +); + +VOID SaveSmiEnBeforeBoot ( + IN EFI_EVENT Event, + IN VOID *Context +); + +#if PI_SPECIFICATION_VERSION >= 0x0001000A +EFI_STATUS SBSMM_TriggerSMI2( + IN CONST EFI_SMM_CONTROL2_PROTOCOL *This, + IN OUT UINT8 *CommandPort OPTIONAL, + IN OUT UINT8 *DataPort OPTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OPTIONAL +); + +EFI_STATUS SBSMM_ClearSMI2( + IN CONST EFI_SMM_CONTROL2_PROTOCOL *This, + IN BOOLEAN Periodic OPTIONAL +); +#endif + +// GUID Definitions +EFI_GUID gEfiSmmAccessProtocolGuid = EFI_SMM_ACCESS_PROTOCOL_GUID; +EFI_GUID gEfiSmmControlProtocolGuid = EFI_SMM_CONTROL_PROTOCOL_GUID; + + +// Global variable declarations +//-extern EFI_BOOT_SCRIPT_SAVE_PROTOCOL *gBootScriptSave; +EFI_SMM_ACCESS_PROTOCOL *gSmmAccess; +EFI_SMM_CONTROL_PROTOCOL mEfiSmmControlProtocol = +{ + SBSMM_TriggerSMI, + SBSMM_ClearSMI, + SBSMM_GetRegisterInfo, + 0 +}; + +EFI_SMM_CONTROL_PROTOCOL *gEfiSmmControlProtocol = NULL; + +#if PI_SPECIFICATION_VERSION >= 0x0001000A +EFI_SMM_CONTROL2_PROTOCOL gEfiSmmControl2Protocol = +{ + SBSMM_TriggerSMI2, + SBSMM_ClearSMI2, + 0 +}; +#endif + +// Portable Constants + +// Function Definition + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SBSMM_EnableSWSmi +// +// Description: This function programs the SB chipset registers to enable +// S/W SMI generation +// +// Input: None +// +// Output: EFI_SUCCESS Always +// +// Notes: CHIPSET AND/OR BOARD PORTING NEEDED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +SBSMM_EnableSWSmi(VOID) +{ +/* + UINT32 Value32; + + SBSMM_ClearSMI(&mEfiSmmControlProtocol, FALSE); + SBSMM_BootScript(); + +//Porting Required. Include code to enable S/W SMI generation + Value32 = IoRead32(PM_BASE_ADDRESS + ICH_IOREG_SMI_EN) | (BIT05 | BIT00); + IoWrite32(PM_BASE_ADDRESS + ICH_IOREG_SMI_EN, Value32); //Enable global SMIs. + + Value32 = 0x00002002B; + BOOT_SCRIPT_S3_IO_WRITE_MACRO(gBootScriptSave, + EfiBootScriptWidthUint32, + PM_BASE_ADDRESS + ICH_IOREG_SMI_EN, + 1, + &Value32); +//End Porting +*/ + + return EFI_SUCCESS; +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SBSMM_TriggerSMI +// +// Description: This function generates a software SMI by writing the provided +// byte value into the software SMI generation register +// +// Input: *This Pointer to the SMM control protocol +// *ArgumentBuffer Contains the value to be written to the +// S/W SMI port. Currently supports byte only +// and this is a optional pointer +// *ArgumentBufferSize Optional. Valid value is 1 +// Periodic Boolean indicating the nature of generation +// TRUE means periodic generation depending on +// timing value provided in the next variable +// CURRENTLY NOT SUPPORTED. EXPECTS FALSE +// ActivationInterval Optional. NOT SUPPORTED +// +// Output: EFI_STATUS +// EFI_SUCCESS S/W SMI triggered successfully +// EFI_INVALID_PARAMETER If Periodic is TRUE or when +// (ArgumentBuffer is not NULL and +// ArgumentBufferSize is not 1) +// +// Notes: CHIPSET AND/OR BOARD PORTING NEEDED +// Here is the control flow of this function: +// 1. If Periodic was TRUE, return EFI_INVALID_PARAMETER. +// 2. If ArgumentBuffer == NULL, use 0xFF as data. +// 3. If not NULL, if valid byte, use it as data. Otherwise +// return EFI_INVALID_PARAMETER. +// 4. Deactive any active SMI status. +// 5. Write the data to the SMI trigger port. +// 6. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SBSMM_TriggerSMI( + IN EFI_SMM_CONTROL_PROTOCOL *This, + IN OUT INT8 *ArgumentBuffer OPTIONAL, + IN OUT UINTN *ArgumentBufferSize OPTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OPTIONAL +) +{ + UINT8 Data; + EFI_STATUS Status = EFI_SUCCESS; + + if (Periodic) + return EFI_INVALID_PARAMETER; + + if (ArgumentBuffer == NULL) + { + Data = 0xFF; // If no data given, use 0xFF to trigger SMI. + } + else + { + if (ArgumentBufferSize == NULL || *ArgumentBufferSize != 1) + return EFI_INVALID_PARAMETER; // Only able to send 1 byte. + Data = *ArgumentBuffer; + } + + // Porting Required. Include code to generate S/W SMI + WRITE_IO32_PM(ICH_IOREG_SMI_EN, (READ_IO32_PM(ICH_IOREG_SMI_EN) | (BIT5 | BIT0))); + WRITE_IO8(SW_SMI_IO_ADDRESS, Data); // This triggers SMI + // Porting End + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SBSMM_ClearSMI +// +// Description: This function clears all SMI status registers and generates +// End-of-SMI (EOS) +// +// Input: *This Pointer to the SMM control protocol +// Periodic Boolean indicating the nature of clearing +// TRUE means periodic SMI clearing +// CURRENTLY NOT SUPPORTED. EXPECTS FALSE +// +// Output: EFI_STATUS +// EFI_SUCCESS SMI status successfully cleared +// EFI_INVALID_PARAMETER If Periodic is TRUE +// +// Notes: CHIPSET AND/OR BOARD PORTING NEEDED +// Here is the control flow of this function: +// 1. If Periodic was TRUE, return EFI_INVALID_PARAMETER. +// 2. Clear SMI Status on all appropriate SMI status registers +// 3. Set EOS. +// 4. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +SBSMM_ClearSMI( + IN EFI_SMM_CONTROL_PROTOCOL *This, + IN BOOLEAN Periodic OPTIONAL +) +{ + + if (Periodic) return EFI_INVALID_PARAMETER; + + // Porting Required. Include code to clear software SMI status only + WRITE_IO8_PM(ICH_IOREG_SMI_STS, 0x20); // 0x34 + + + //Set EOS + SET_IO8_PM(ICH_IOREG_SMI_EN, BIT01); + + // Porting end + + return EFI_SUCCESS; +} + +#if PI_SPECIFICATION_VERSION >= 0x0001000A +EFI_STATUS SBSMM_TriggerSMI2( + IN CONST EFI_SMM_CONTROL2_PROTOCOL *This, + IN OUT UINT8 *CommandPort OPTIONAL, + IN OUT UINT8 *DataPort OPTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OPTIONAL +) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINTN DataSize = 1; + UINT8 Data; + + if (Periodic) + return EFI_INVALID_PARAMETER; + + if (CommandPort == NULL) + { + Data = 0xFF; // If no data given, use 0xFF to trigger SMI. + } + else + { + Data = *CommandPort; + } + + Status = gEfiSmmControlProtocol->Trigger(gEfiSmmControlProtocol, &Data, &DataSize, FALSE, 0); + + return Status; +} + +EFI_STATUS SBSMM_ClearSMI2( + IN CONST EFI_SMM_CONTROL2_PROTOCOL *This, + IN BOOLEAN Periodic OPTIONAL +) +{ + if (Periodic) + return EFI_INVALID_PARAMETER; + + gEfiSmmControlProtocol->Clear(gEfiSmmControlProtocol, FALSE); + + return EFI_SUCCESS; +} +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SBSMM_BootScript +// +// Description: This function clears all SMI enables registers and generates +// End-of-SMI (EOS) in Boot Script +// +// Input: None +// +// Output: None +// +// Notes: CHIPSET AND/OR BOARD PORTING NEEDED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID SBSMM_BootScript(VOID) +{ +/* + UINT16 i; + UINT16 j; + +// 0x00-0x03 +// 0x28-0x2B +// 0x2C-0x2F +// 0x20-0x23 +// 0x24-0x27 +// 0x38-0x3B +// 0x34-0x37 + PMIO_BOOT_SCRIPT_STRUCT PMIoBootScriptTbl[] = { \ + {ICH_IOREG_PM1_STS, 0x01000831},\ + {ICH_IOREG_GPE0_EN, 0},\ + {ICH_IOREG_GPE0_EN + 4, 0},\ + {ICH_IOREG_GPE0_STS, 0xFFFFFFFF},\ + {ICH_IOREG_GPE0_STS + 4, 0xFFFFFFFF},\ + {ICH_IOREG_ALT_GP_SMI_EN + 4, 0xFFFF0000},\ + {ICH_IOREG_SMI_STS, 0xFFFFFFF}}; + + // Use boot script to do : + // 1. Clear PM1 statuses except power button & RTC statuses and + // enable power button, OS will setup it as a wake event anyway. + // 2. disable GPE enables. + // 3. disable SMI enables and clear SMI statuses. + // 4. Enable SCI (SCI_EN). + + j = sizeof(PMIoBootScriptTbl) / sizeof(PMIO_BOOT_SCRIPT_STRUCT); + for (i = 0; i < j; i++) + BOOT_SCRIPT_S3_IO_WRITE_MACRO( \ + gBootScriptSave, \ + EfiBootScriptWidthUint32, \ + PM_BASE_ADDRESS + PMIoBootScriptTbl[i].IoReg8,\ + 1, \ + &PMIoBootScriptTbl[i].Value32 ); + + + // Enable SCI. + i = 1; + j = 0xffff; + BOOT_SCRIPT_S3_IO_READ_WRITE_MACRO( \ + gBootScriptSave, \ + EfiBootScriptWidthUint16, \ + PM_BASE_ADDRESS + ICH_IOREG_PM1_CNT, + &i, \ + &j ); +*/ +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SaveSmiEnBeforeBoot +// +// Description: This function uses boot script to all SMI enables before boot +// to OS. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +// +// Notes: CHIPSET AND/OR BOARD PORTING NEEDED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SaveSmiEnBeforeBoot ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ +/* + // Porting Required. + UINT32 Buffer32; + UINT32 PCIAdd; + UINT8 Data8; + + // Remove SLP_SMI from boot script if needed. + Buffer32 = READ_IO32_PM(ICH_IOREG_SMI_EN) & ~(BIT04 | BIT06); + + BOOT_SCRIPT_S3_IO_WRITE_MACRO( \ + gBootScriptSave, \ + EfiBootScriptWidthUint32, \ + PM_BASE_ADDRESS + ICH_IOREG_SMI_EN, \ + 1, \ + &Buffer32 ); + + + // Save NMI2SMI_EN, TCO_TMR_HLT and TCO_LOCK + Data8 = READ_IO8_TCO(ICH_IOREG_TCO1_CNT + 1) & (BIT01 | BIT03 | BIT04); + BOOT_SCRIPT_S3_IO_WRITE_MACRO( \ + gBootScriptSave, \ + EfiBootScriptWidthUint8, \ + TCO_BASE_ADDRESS + ICH_IOREG_TCO1_CNT + 1, \ + 1, \ + &Data8 ); + + + PCIAdd = EFI_SB_PCI_CFG_ADDRESS(LPC_BUS, LPC_DEVICE, LPC_FUNC, ICH_REG_LPC_VID); + + Data8 = READ_PCI8_SB(ICH_REG_GEN_PMCON_1); + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( \ + gBootScriptSave, \ + EfiPciIoWidthUint8, \ + EFI_SB_PCI_CFG_ADDRESS(LPC_BUS, LPC_DEVICE, LPC_FUNC, ICH_REG_GEN_PMCON_1), \ + 1, \ + &Data8 + ); + + Data8 = READ_PCI8_SB(ICH_REG_GEN_PMCON_3); + Data8 &= ~(BIT01); + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( \ + gBootScriptSave, \ + EfiPciIoWidthUint8, \ + EFI_SB_PCI_CFG_ADDRESS(LPC_BUS, LPC_DEVICE, LPC_FUNC, ICH_REG_GEN_PMCON_3), \ + 1, \ + &Data8 + ); +*/ + + // Porting End + pBS->CloseEvent(Event); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SBSMM_GetRegisterInfo +// +// Description: This function returns the S/W SMI generation register and +// its status register values +// +// Input: *This Pointer to the SMM control protocol +// SmiRegister Pointer to the SMM control register structure +// +// Output: EFI_UNSUPPORTED +// +// Notes: CHIPSET AND/OR BOARD PORTING NEEDED +// 1. Return EFI_UNSUPPORTED. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +SBSMM_GetRegisterInfo( + IN EFI_SMM_CONTROL_PROTOCOL *This, + IN OUT EFI_SMM_CONTROL_REGISTER *SmiRegister +) +{ + + // Porting Required. Include code to return I/O port to generate S/W SMI + SmiRegister->SmiTriggerRegister = SW_SMI_IO_ADDRESS; + SmiRegister->SmiDataRegister = SW_SMI_IO_ADDRESS + 1; + // Porting End + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: DisableAllSmi +// +// Description: This function disables all SMI's which can be caused by +// SouthBridge, include global SMI. +// +// Input: None +// +// Output: None +// +// Notes: CHIPSET AND/OR BOARD PORTING NEEDED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID DisableAllSmi(VOID) +{ + //--WRITE_IO16_PM(ICH_IOREG_PM1_EN, 0x0000); // 0x02 + //--WRITE_IO32_PM(ICH_IOREG_GPE0_EN, 0x00000000); // 0x2C + //--WRITE_IO32_PM(ICH_IOREG_SMI_EN, 0x00000000); // 0x30 + //--WRITE_IO32_PM(ICH_IOREG_ALT_GP_SMI_EN, 0x00000000); // 0x38 +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SBSMM_Init +// +// Description: This function is invoked from SB DXE to initialize SMM +// related stuff in NorthBridge and install appropriate +// SMM protocols such as SMM Access & SMM Control +// +// Input: ImageHandle Image handle +// SystemTable Pointer to the system table +// +// Output: Return Status based on errors that occurred while waiting for +// time to expire. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +SbSmmInit( + IN EFI_EVENT Event, + IN VOID *Context +) +{ + EFI_STATUS Status; + EFI_EVENT mEvent; + UINT8 Value; + + PROGRESS_CODE(DXE_SB_SMM_INIT); + + Status = pBS->LocateProtocol(&gEfiSmmControlProtocolGuid, NULL, &gEfiSmmControlProtocol); + if (EFI_ERROR(Status)) + { + Status = pBS->LocateProtocol(&gEfiSmmAccessProtocolGuid, NULL, &gSmmAccess); + ASSERT_EFI_ERROR(Status); + + // Disable all SMI enables here + DisableAllSmi(); + + //Must read RTC Reg C to be able to clear SMM RTC alarm flag. + Value = SBLib_CmosRead(0x0C); + + // Clear all SMI status here. + //--WRITE_IO16_PM(ICH_IOREG_PM1_STS, 0xCF31); // 0x00 + //--WRITE_IO32_PM(ICH_IOREG_GPE0_STS, 0xFFFFFFFF); // 0x20 + //--WRITE_IO32_PM(ICH_IOREG_GPE0_STS + 4, 0xffffffff); // 0x24 + //--WRITE_IO16_PM(ICH_IOREG_ALT_GP_SMI_STS, 0xFFFF); // 0x3A + //--WRITE_IO16_PM(ICH_IOREG_DEVACT_STS, 0xFFFF); // 0x44 + //--WRITE_IO16_TCO(ICH_IOREG_TCO1_STS, 0xFFFF); // 0x04 + //--WRITE_IO16_TCO(ICH_IOREG_TCO2_STS, (0xFFFF)); // 0x06 + //--WRITE_IO32_PM(ICH_IOREG_SMI_STS, 0xFFFFFFFF); // 0x34 + + // Enable S/W SMI Generation + SBSMM_EnableSWSmi(); + + Status = CreateReadyToBootEvent( TPL_NOTIFY, \ + SaveSmiEnBeforeBoot, \ + NULL, \ + &mEvent ); + ASSERT_EFI_ERROR(Status); + + Status = pBS->InstallMultipleProtocolInterfaces( + &TheImageHandle, + &gEfiSmmControlProtocolGuid, + &mEfiSmmControlProtocol, +#if PI_SPECIFICATION_VERSION >= 0x0001000A + &gEfiSmmControl2ProtocolGuid, + &gEfiSmmControl2Protocol, +#endif + NULL, + NULL + ); + ASSERT_EFI_ERROR(Status); + } + else + { +#if PI_SPECIFICATION_VERSION >= 0x0001000A + Status = pBS->InstallMultipleProtocolInterfaces( + &TheImageHandle, + &gEfiSmmControl2ProtocolGuid, + &gEfiSmmControl2Protocol, + NULL, + NULL + ); + ASSERT_EFI_ERROR(Status); +#endif + } + + return Status; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/SataDriver/SataDriver.cif b/Chipset/SB/SataDriver/SataDriver.cif new file mode 100644 index 0000000..d0e9cac --- /dev/null +++ b/Chipset/SB/SataDriver/SataDriver.cif @@ -0,0 +1,11 @@ +<component> + name = "PchSataDriver" + category = ModulePart + LocalRoot = "Chipset\SB\SataDriver\" + RefName = "SataDriver" +[files] +"SataDriver.sdl" +"SataDriver.mak" +"SataDriver.dxs" +"SataDriver.efi" +<endComponent> diff --git a/Chipset/SB/SataDriver/SataDriver.dxs b/Chipset/SB/SataDriver/SataDriver.dxs new file mode 100644 index 0000000..a53fc90 --- /dev/null +++ b/Chipset/SB/SataDriver/SataDriver.dxs @@ -0,0 +1,64 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SataDriver/SataDriver.dxs 1 2/08/12 8:37a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:37a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SataDriver/SataDriver.dxs $ +// +// 1 2/08/12 8:37a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* + +//<AMI_FHDR_START> +//---------------------------------------------------------------------------- +// +// Name: SataDriver.dxs +// +// Description: Sata UEFI Driver. +// +//---------------------------------------------------------------------------- +//<AMI_FHDR_END> +#include "AutoGen.h" +#include "DxeDepex.h" +#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB) +#include "EfiDepex.h" +#endif + +#define PCH_EFI_RAID_DRIVER_EXECUTION_GUID \ + { 0x99D5757C, 0xD906, 0x11E0, 0x8D, 0x78, 0x8D, 0xE4, 0x48, 0x24, 0x01, 0x9B } + +DEPENDENCY_START + PCH_EFI_RAID_DRIVER_EXECUTION_GUID +DEPENDENCY_END +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//*************************************************************************
\ No newline at end of file diff --git a/Chipset/SB/SataDriver/SataDriver.efi b/Chipset/SB/SataDriver/SataDriver.efi Binary files differnew file mode 100644 index 0000000..f8925f1 --- /dev/null +++ b/Chipset/SB/SataDriver/SataDriver.efi diff --git a/Chipset/SB/SataDriver/SataDriver.mak b/Chipset/SB/SataDriver/SataDriver.mak new file mode 100644 index 0000000..8270404 --- /dev/null +++ b/Chipset/SB/SataDriver/SataDriver.mak @@ -0,0 +1,73 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SataDriver/SataDriver.mak 2 1/10/13 8:28a Scottyang $ +# +# $Revision: 2 $ +# +# $Date: 1/10/13 8:28a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SataDriver/SataDriver.mak $ +# +# 2 1/10/13 8:28a Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Create token for SataDriver path. +# [Files] SataDriver.sdl, SataDriver.mak +# +# 1 2/08/12 8:37a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: SatsDriver.mak +# +# Description: Make file for the Sata Uefi Driver. +# +#<AMI_FHDR_END> +#************************************************************************* +all : $(BUILD_DIR)\SataDriver.ffs + +SataDriver_INCLUDES=\ + $(INTEL_PCH_INCLUDES)\ + $(EdkIIGlueLib_INCLUDES)\ + $(EDK_INCLUDES) + +$(BUILD_DIR)\SataDriver.ffs : $(OEM_SATA_EFI_DRIVER_FILE) $(SataDriver_DIR)\$(@B).mak Core\FFS.mak + $(MAKE) /$(MAKEFLAGS) /f Core\FFS.mak \ + CPFLAGS="$(GLOBAL_DEFINES) /D TIANO_RELEASE_VERSION=0x00080006 $(EXTRA_DEFINES) $(SataDriver_INCLUDES)" \ + BUILD_DIR=$(BUILD_DIR) SOURCE_DIR=$(SataDriver_DIR) \ + GUID=91B4D9C1-141C-4824-8D02-3C298E36EB3F\ + NAME=$(@B)\ + TYPE=EFI_FV_FILETYPE_DRIVER \ + DEPEX1=$(SataDriver_DIR)\SataDriver.dxs\ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + PEFILE=$(OEM_SATA_EFI_DRIVER_FILE) FFSFILE=$@ COMPRESS=1 \ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Chipset/SB/SataDriver/SataDriver.sdl b/Chipset/SB/SataDriver/SataDriver.sdl new file mode 100644 index 0000000..ba1dd02 --- /dev/null +++ b/Chipset/SB/SataDriver/SataDriver.sdl @@ -0,0 +1,88 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SataDriver/SataDriver.sdl 3 1/10/13 8:28a Scottyang $ +# +# $Revision: 3 $ +# +# $Date: 1/10/13 8:28a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SataDriver/SataDriver.sdl $ +# +# 3 1/10/13 8:28a Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Create token for SataDriver path. +# [Files] SataDriver.sdl, SataDriver.mak +# +# 2 7/02/12 10:15a Victortu +# [TAG] None +# [Category] Improvement +# [Description] Set SataDriver_SUPPORT enabled by default. +# [Files] SataDriver.sdl +# +# 1 2/08/12 8:37a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = SataDriver_SUPPORT + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Master = Yes + Help = "Main switch to enable SataDriver support in Project" +End + +MODULE + Help = "Includes SataDriver.mak to Project" + File = "SataDriver.mak" +End + +PATH + Name = "SataDriver_DIR" + Help = "Sata Uefi Raid Driver." +End + +TOKEN + Name = "OEM_SATA_EFI_DRIVER_FILE" + Value = "$(SataDriver_DIR)\SataDriver.efi" + TokenType = Expression + TargetMAK = Yes +End + +ELINK + Name = "$(BUILD_DIR)\SataDriver.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Chipset/SB/SataOrom125.bin b/Chipset/SB/SataOrom125.bin Binary files differnew file mode 100644 index 0000000..3da7af5 --- /dev/null +++ b/Chipset/SB/SataOrom125.bin diff --git a/Chipset/SB/SleepSmi.c b/Chipset/SB/SleepSmi.c new file mode 100644 index 0000000..20408a1 --- /dev/null +++ b/Chipset/SB/SleepSmi.c @@ -0,0 +1,457 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SleepSmi/SleepSmi.c 4 9/26/12 3:59a Victortu $ +// +// $Revision: 4 $ +// +// $Date: 9/26/12 3:59a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SleepSmi/SleepSmi.c $ +// +// 4 9/26/12 3:59a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update for PCH LP GPIO compatible. +// [Files] SB.sdl, SB.H, AcpiModeEnable.c, AcpiModeEnable.sdl, +// SBDxe.c, SBGeneric.c, SBPEI.c, SBSMI.c, SleepSmi.c, +// SmiHandlerPorting.c, SmiHandlerPorting2.c +// +// 3 7/27/12 6:17a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update to support ULT Platform. +// [Files] SB.H, SB.mak, SB.sdl, SB.sd, SBSetup.c, +// AcpiModeEnable.c, SBDxe.c, SBPEI.c, SBSMI.c, SleepSmi.c, +// SmiHandlerPorting.c, SmiHandlerPorting2.c, SBPPI.h, Pch.sdl +// +// 2 6/13/12 11:29p Victortu +// [TAG] None +// [Category] Improvement +// [Description] Program AfterG3 bit depend the setup question in +// S3/S4/S5. +// [Files] SleepSmi.c +// +// 1 2/08/12 8:30a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SleepSmi.C +// +// Description: Provide functions to register and handle Sleep SMI +// functionality. +// +//<AMI_FHDR_END> +//************************************************************************* + +//--------------------------------------------------------------------------- +// Include(s) +//--------------------------------------------------------------------------- + +#include <Token.h> +#include <Setup.h> +#include <AmiDxeLib.h> +#include <AmiCspLib.h> +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) +#include <Protocol\SmmBase2.h> +#include <Protocol\SmmSxDispatch2.h> +#else +#include <Protocol\SmmBase.h> +#include <Protocol\SmmSxDispatch.h> +#endif +#include <PchAccess.h> + +//--------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//--------------------------------------------------------------------------- +// Constant Definition(s) + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) +#define AMI_SMM_SX_DISPATCH_PROTOCOL EFI_SMM_SX_DISPATCH2_PROTOCOL +#define AMI_SMM_SX_DISPATCH_CONTEXT EFI_SMM_SX_REGISTER_CONTEXT +#define SMM_CHILD_DISPATCH_SUCCESS EFI_SUCCESS +#else +#define AMI_SMM_SX_DISPATCH_PROTOCOL EFI_SMM_SX_DISPATCH_PROTOCOL +#define AMI_SMM_SX_DISPATCH_CONTEXT EFI_SMM_SX_DISPATCH_CONTEXT +#define SMM_CHILD_DISPATCH_SUCCESS +#endif + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//--------------------------------------------------------------------------- +// Variable and External Declaration(s) +//--------------------------------------------------------------------------- +// Variable Declaration(s) + +BOOLEAN gIsLastState = FALSE; +BOOLEAN gPchWakeOnLan = FALSE; +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) +EFI_SMM_BASE2_PROTOCOL *gSmmBase2; +#endif + +// GUID Definition(s) + +EFI_GUID gThisFileGuid = \ + {0x6298fe18, 0xd5ef, 0x42b7, 0xbb, 0xc, 0x29, 0x53, 0x28, 0x3f, 0x57, 0x4}; + // {6298FE18-D5EF-42b7-BB0C-2953283F5704} + +// Protocol Definition(s) + +// External Declaration(s) + +// Function Definition(s) + +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ProgramAfterG3Bit +// +// Description: This function will set AfterG3 bit depend the setup question. +// +// Input: None +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID ProgramAfterG3Bit(VOID) +{ + if (gIsLastState) SET_PCI8_SB(SB_REG_GEN_PMCON_3, 1); // 0xA4 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: S1SleepSmiOccurred +// +// Description: This function will be called by EfiSmmSxDispatch when a Sleep +// SMI occurs and the sleep state is S1. +// +// Input: DispatchHandle - SMI dispatcher handle +// *DispatchContext - Pointer to the dispatch context +// +// Output: Nothing +// +// Notes: This function does not need to put the system to sleep. This is +// handled by PutToSleep. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) +EFI_STATUS S1SleepSmiOccurred ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *DispatchContext OPTIONAL, + IN OUT VOID *CommBuffer OPTIONAL, + IN OUT UINTN *CommBufferSize OPTIONAL ) +#else +VOID S1SleepSmiOccurred ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_SX_DISPATCH_CONTEXT *DispatchContext ) +#endif +{ + // Porting required if any workaround is needed. + return SMM_CHILD_DISPATCH_SUCCESS; +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: S3SleepSmiOccurred +// +// Description: This function will be called by EfiSmmSxDispatch when a Sleep +// SMI occurs and the sleep state is S3. +// +// Input: DispatchHandle - SMI dispatcher handle +// *DispatchContext - Pointer to the dispatch context +// +// Output: Nothing +// +// Notes: This function does not need to put the system to sleep. This is +// handled by PutToSleep. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) +EFI_STATUS S3SleepSmiOccurred ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *DispatchContext OPTIONAL, + IN OUT VOID *CommBuffer OPTIONAL, + IN OUT UINTN *CommBufferSize OPTIONAL ) +#else +VOID S3SleepSmiOccurred ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_SX_DISPATCH_CONTEXT *DispatchContext ) +#endif +{ + BOOLEAN IsGpioLocked; + UINT16 LpcDeviceId; + + LpcDeviceId = READ_PCI16_SB(R_PCH_LPC_DEVICE_ID); + + IsGpioLocked = (READ_PCI8_SB(SB_REG_GC) & BIT00)? TRUE:FALSE; + + if (IS_PCH_LPT_LPC_DEVICE_ID_MOBILE (LpcDeviceId)) { + + // Reset GPIO Lockdown Enable (GLE) + if (IsGpioLocked) + RESET_PCI8_SB(SB_REG_GC, BIT00); + + // Set GPIO 60 to low (S3 power) + if (GetPchSeries() == PchLp) { + RESET_IO32( GPIO_BASE_ADDRESS + (GP_IOREG_GP_GPN_CFG1 + GP_GPIO_CONFIG_SIZE*60), ~BIT31); // 0x38 + } else { + RESET_IO32( GPIO_BASE_ADDRESS + GP_IOREG_GP_LVL2, ~0xEFFFFFFF); // 0x38 + } + + // Set GPIO Lockdown Enable (GLE) + if (IsGpioLocked) + SET_PCI8_SB(SB_REG_GC, BIT00); + } + + ProgramAfterG3Bit(); + + return SMM_CHILD_DISPATCH_SUCCESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: S4SleepSmiOccurred +// +// Description: This function will be called by EfiSmmSxDispatch when a Sleep +// SMI occurs and the sleep state is S4. +// +// Input: DispatchHandle - SMI dispatcher handle +// *DispatchContext - Pointer to the dispatch context +// +// Output: Nothing +// +// Notes: This function does not need to put the system to sleep. This is +// handled by PutToSleep. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) +EFI_STATUS S4SleepSmiOccurred ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *DispatchContext OPTIONAL, + IN OUT VOID *CommBuffer OPTIONAL, + IN OUT UINTN *CommBufferSize OPTIONAL ) +#else +VOID S4SleepSmiOccurred ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_SX_DISPATCH_CONTEXT *DispatchContext ) +#endif +{ + ClearMeWakeSts(); + + ProgramAfterG3Bit(); + + return SMM_CHILD_DISPATCH_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: S5SleepSmiOccurred +// +// Description: This function will be called by EfiSmmSxDispatch when a Sleep +// SMI occurs and the sleep state is S1. +// +// Input: DispatchHandle - SMI dispatcher handle +// *DispatchContext - Pointer to the dispatch context +// +// Output: Nothing +// +// Notes: This function does not need to put the system to sleep. This is +// handled by PutToSleep. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) +EFI_STATUS S5SleepSmiOccurred ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *DispatchContext OPTIONAL, + IN OUT VOID *CommBuffer OPTIONAL, + IN OUT UINTN *CommBufferSize OPTIONAL ) +#else +VOID S5SleepSmiOccurred ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_SX_DISPATCH_CONTEXT *DispatchContext ) +#endif +{ + + ClearMeWakeSts(); + SBLib_BeforeShutdown(); + + if (gPchWakeOnLan) Enable_GbE_PME(); + + // Program AfterG3 bit depend the setup question. + ProgramAfterG3Bit(); + + return SMM_CHILD_DISPATCH_SUCCESS; +} + +//---------------------------------------------------------------------------- +// +// Procedure: InSmmFunction +// +// Description: Install Sleep SMI Handlers for south bridge. +// +// Input: ImageHandle - Image handle +// *SystemTable - Pointer to the system table +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS InSmmFunction ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status; + EFI_HANDLE hS1Smi; + EFI_HANDLE hS3Smi; + EFI_HANDLE hS4Smi; + EFI_HANDLE hS5Smi; + AMI_SMM_SX_DISPATCH_PROTOCOL *SxDispatch; + AMI_SMM_SX_DISPATCH_CONTEXT S1DispatchContext = {SxS1, SxEntry}; + AMI_SMM_SX_DISPATCH_CONTEXT S3DispatchContext = {SxS3, SxEntry}; + AMI_SMM_SX_DISPATCH_CONTEXT S4DispatchContext = {SxS4, SxEntry}; + AMI_SMM_SX_DISPATCH_CONTEXT S5DispatchContext = {SxS5, SxEntry}; +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) + EFI_SMM_SYSTEM_TABLE2 *pSmst2; +#endif + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) + Status = InitAmiSmmLib( ImageHandle, SystemTable ); + if (EFI_ERROR(Status)) return Status; + + // We are in SMM, retrieve the pointer to SMM System Table + Status = gSmmBase2->GetSmstLocation( gSmmBase2, &pSmst2); + if (EFI_ERROR(Status)) return EFI_UNSUPPORTED; + + Status = pSmst2->SmmLocateProtocol( &gEfiSmmSxDispatch2ProtocolGuid , \ + NULL, \ + &SxDispatch ); + TRACE((TRACE_ALWAYS, "Smm Locate Protocol gEfiSmmSxDispatch2ProtocolGuid, Status = %r\n",Status)); + +#else + Status = pBS->LocateProtocol( &gEfiSmmSxDispatchProtocolGuid , \ + NULL, \ + &SxDispatch ); +#endif + if (EFI_ERROR(Status)) return Status; + + // Register Sleep SMI Handlers + Status = SxDispatch->Register( SxDispatch, \ + S1SleepSmiOccurred, \ + &S1DispatchContext, \ + &hS1Smi ); + if (EFI_ERROR(Status)) return Status; + + Status = SxDispatch->Register( SxDispatch, \ + S3SleepSmiOccurred, \ + &S3DispatchContext, \ + &hS3Smi ); + if (EFI_ERROR(Status)) return Status; + + Status = SxDispatch->Register( SxDispatch, \ + S4SleepSmiOccurred, \ + &S4DispatchContext, \ + &hS4Smi ); + if (EFI_ERROR(Status)) return Status; + + Status = SxDispatch->Register( SxDispatch, \ + S5SleepSmiOccurred, \ + &S5DispatchContext, \ + &hS5Smi ); + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitSleepSmi +// +// Description: This function Registers Sleep SMI functionality. +// +// Input: ImageHandle - Handle for this FFS image +// *SystemTable- Pointer to the system table +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS InitSleepSmi ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status; + SB_SETUP_DATA *SbSetupData = NULL; + UINTN VariableSize = sizeof(SB_SETUP_DATA); + + InitAmiLib( ImageHandle, SystemTable ); + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) + Status = SystemTable->BootServices->LocateProtocol( \ + &gEfiSmmBase2ProtocolGuid, \ + NULL, \ + &gSmmBase2 ); + ASSERT_EFI_ERROR(Status); +#endif + + // Porting Required + // Put the Setup Vairable to SMM if needed. + Status = pBS->AllocatePool( EfiBootServicesData, \ + VariableSize, \ + &SbSetupData ); + ASSERT_EFI_ERROR(Status); + + GetSbSetupData( pRS, SbSetupData, FALSE ); + + gIsLastState = (SbSetupData->LastState == 2) ? TRUE : FALSE; + gPchWakeOnLan = (SbSetupData->PchWakeOnLan == 1) ? TRUE : FALSE; + Status = pBS->FreePool( SbSetupData ); + + // Porting End + + return InitSmmHandler( ImageHandle, SystemTable, InSmmFunction, NULL ); +} + + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/SleepSmi.cif b/Chipset/SB/SleepSmi.cif new file mode 100644 index 0000000..98f82e7 --- /dev/null +++ b/Chipset/SB/SleepSmi.cif @@ -0,0 +1,11 @@ +<component> + name = "SleepSmi" + category = ModulePart + LocalRoot = "Chipset\SB" + RefName = "SleepSmi" +[files] +"SleepSmi.sdl" +"SleepSmi.mak" +"SleepSmi.c" +"SleepSmi.dxs" +<endComponent> diff --git a/Chipset/SB/SleepSmi.dxs b/Chipset/SB/SleepSmi.dxs new file mode 100644 index 0000000..d6cf554 --- /dev/null +++ b/Chipset/SB/SleepSmi.dxs @@ -0,0 +1,62 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SleepSmi/SleepSmi.dxs 2 4/25/12 9:28a Victortu $ +// +// $Revision: 2 $ +// +// $Date: 4/25/12 9:28a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SleepSmi/SleepSmi.dxs $ +// +// 2 4/25/12 9:28a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Remove unnecessary dependence. +// [Files] AcpiModeEnable.dxs; SBSMI.dxs; SleepSmi.dxs +// +// 1 2/08/12 8:30a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SleepSmi.DXS +// +// Description: Dependency file for the sleep SMI handler driver +// +//<AMI_FHDR_END> +//************************************************************************* +#include <Protocol\SmmSxDispatch.h> + +DEPENDENCY_START + EFI_SMM_SX_DISPATCH_PROTOCOL_GUID +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/SleepSmi.mak b/Chipset/SB/SleepSmi.mak new file mode 100644 index 0000000..845d783 --- /dev/null +++ b/Chipset/SB/SleepSmi.mak @@ -0,0 +1,77 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SleepSmi/SleepSmi.mak 1 2/08/12 8:30a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 8:30a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SleepSmi/SleepSmi.mak $ +# +# 1 2/08/12 8:30a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: SleepSmi.MAK +# +# Description: Make file for the SMM Sleep SMI handler code +# +#<AMI_FHDR_END> +#************************************************************************* +!IFNDEF PI_SPECIFICATION_VERSION +PI_SPECIFICATION_VERSION = 0 +!ENDIF + +all : SleepSmi + +SleepSmi : $(BUILD_DIR)\SleepSmi.mak SleepSmiBin + +$(BUILD_DIR)\SleepSmi.mak : $(SLEEP_SMI_DIR)\SleepSmi.cif $(SLEEP_SMI_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(SLEEP_SMI_DIR)\SleepSmi.cif $(CIF2MAK_DEFAULTS) + +SleepSmiBin : $(AMICSPLib) $(AMIDXELIB) + @set INCLUDE=%%INCLUDE%% + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\SleepSmi.mak all\ + GUID=6298FE18-D5EF-42b7-BB0C-2953283F5704\ + ENTRY_POINT=InitSleepSmi\ + "MY_INCLUDES=$(INTEL_PCH_INCLUDES)" \ +!IF $(PI_SPECIFICATION_VERSION) >= 0x1000A + TYPE=BS_DRIVER \ + DEPEX1=$(SLEEP_SMI_DIR)\SleepSmi.DXS \ +!ELSE + TYPE=BS_DRIVER \ + DEPEX1=$(SLEEP_SMI_DIR)\SleepSmi.DXS DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ +!ENDIF + COMPRESS=1 + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/SB/SleepSmi.sdl b/Chipset/SB/SleepSmi.sdl new file mode 100644 index 0000000..12e2bff --- /dev/null +++ b/Chipset/SB/SleepSmi.sdl @@ -0,0 +1,68 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SleepSmi/SleepSmi.sdl 1 2/08/12 8:30a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 8:30a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SleepSmi/SleepSmi.sdl $ +# +# 1 2/08/12 8:30a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "SleepSmi_SUPPORT" + Value = "1" + Help = "Main switch to enable SleepSmi support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Token = "SmmChildDispatcher_SUPPORT" "=" "1" +End + +PATH + Name = "SLEEP_SMI_DIR" +End + +MODULE + Help = "Includes SleepSmi.mak to Project" + File = "SleepSmi.mak" +End + +ELINK + Name = "$(BUILD_DIR)\SleepSmi.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Chipset/SB/SmBus/SmBus.cif b/Chipset/SB/SmBus/SmBus.cif new file mode 100644 index 0000000..5f3dee2 --- /dev/null +++ b/Chipset/SB/SmBus/SmBus.cif @@ -0,0 +1,20 @@ +<component> + name = "SmBus" + category = ModulePart + LocalRoot = "Chipset\SB\SmBus\" + RefName = "SmBus" +[files] +"SmBus.sdl" +"SmBus.mak" +"SmBusCommon.h" +"SmBusPei.h" +"SmBusDxe.h" +"SmBusCommon.c" +"SmBusPorting.c" +"SmBusPei.c" +"SmBusDxe.c" +"SmBusPciHooks.c" +"SmBusPei.dxs" +"SmBusDxe.dxs" +"SmBusSmm.dxs" +<endComponent> diff --git a/Chipset/SB/SmBus/SmBus.mak b/Chipset/SB/SmBus/SmBus.mak new file mode 100644 index 0000000..7a5148e --- /dev/null +++ b/Chipset/SB/SmBus/SmBus.mak @@ -0,0 +1,146 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#********************************************************************** +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBus.mak 1 6/06/12 8:00a Victortu $ +# +# $Revision: 1 $ +# +# $Date: 6/06/12 8:00a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBus.mak $ +# +# 1 6/06/12 8:00a Victortu +# Implement EFI_PEI_SMBUS2_PPI Support. +# +# 6 7/19/11 8:28a Abelwu +# [TAG] EIP63768 +# [Category] Improvement +# [Description] Supported Core 4.6.5.x PI 1.2 / uEFI 2.3.1 compliance +# [Files] SmBus.mak +# +# 5 6/17/11 5:52p Artems +# EIP 53378: Replaced tabs with spaces, formatted to follow coding +# standard +# +# 4 5/18/11 11:50a Artems +# +# 3 1/27/11 9:48p Abelwu +# Supports SMBUS Protocol in early DXE phase. (EIP#40778) +# +# 2 10/16/09 7:06p Artems +# Updated copyright header +# +# 1 1/09/09 6:53p Artems +# New implementation of SMBus EIP 16730 +# +# 1 3/18/07 5:23p Felixp +# +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: SmBus.mak +# +# Description: This make file builds SMBus PEI and DXE components +# and link them to respective binary. +# +#<AMI_FHDR_END> +#********************************************************************** +!IFNDEF PI_SPECIFICATION_VERSION +PI_SPECIFICATION_VERSION = 0 +!ENDIF + +all : SmBusPei #SmBusDxe + +SMBUS_PEI_OBJECTS=\ +$$(BUILD_DIR)\$(SmBus_DIR)\SmBusCommon.obj\ +$$(BUILD_DIR)\$(SmBus_DIR)\SmBusPorting.obj\ +$$(BUILD_DIR)\$(SmBus_DIR)\SmBusPei.obj + +#SMBUS_DXE_OBJECTS=\ +#$$(BUILD_DIR)\$(SmBus_DIR)\SmBusCommon.obj\ +#$$(BUILD_DIR)\$(SmBus_DIR)\SmBusPorting.obj\ +#$$(BUILD_DIR)\$(SmBus_DIR)\SmBusDxe.obj + +SMBUS_PCI_OBJECTS=\ +$$(BUILD_DIR)\$(SmBus_DIR)\SmBusPciHooks.obj\ + +$(BUILD_DIR)\SmBus.mak : $(SmBus_DIR)\$(@B).cif $(SmBus_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(SmBus_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +#SmBusDxe : $(BUILD_DIR)\SmBus.mak SmBusDxeBin +SmBusPei : $(BUILD_DIR)\SmBus.mak SmBusPeiBin +#PciBusSrc : $(BUILD_DIR)\SmBus.mak SmBusPciHooksBin +$(BUILD_DIR)\AMISmBusLib.lib : $(BUILD_DIR)\SmBus.mak SmBusPciHooksBin + +#SmBusDxeBin : $(AMIDXELIB) +# $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ +# /f $(BUILD_DIR)\SmBus.mak all\ +# NAME=SmBusDxe\ +# MAKEFILE=$(BUILD_DIR)\SmBus.mak \ +# "OBJECTS=$(SMBUS_DXE_OBJECTS)" \ +# GUID=4B680E2D-0D63-4f62-B930-7AE995B9B3A3\ +# ENTRY_POINT=SmBusDxeEntryPoint\ +#!IF $(PI_SPECIFICATION_VERSION) >= 0x1000A +# TYPE=DXESMM_DRIVER \ +# DEPEX1=$(SmBus_DIR)\SmBusSmm.DXS DEPEX1_TYPE=EFI_SECTION_SMM_DEPEX \ +# DEPEX2=$(SmBus_DIR)\SmBusDxe.DXS DEPEX2_TYPE=EFI_SECTION_DXE_DEPEX \ +#!ELSE +# TYPE=BS_DRIVER \ +# DEPEX1=$(SmBus_DIR)\SmBusDxe.DXS DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ +#!ENDIF +# COMPRESS=1\ + +SmBusPeiBin : $(AMICSPLib) $(AMIPEILIB) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\SmBus.mak all\ + NAME=SmBusPei\ + MAKEFILE=$(BUILD_DIR)\SmBus.mak \ +!IF "$(x64_BUILD)"=="1" + BUILD_DIR=$(BUILD_DIR)\IA32\ +!ELSE + BUILD_DIR=$(BUILD_DIR)\ +!ENDIF + "OBJECTS=$(SMBUS_PEI_OBJECTS)" \ + GUID=9EA28D33-0175-4788-BEA8-6950516030A5 \ + ENTRY_POINT=SmBusPeiEntryPoint \ + TYPE=PEIM \ + "MY_INCLUDES=$(INTEL_PCH_INCLUDES)" \ + DEPEX1=$(SmBus_DIR)\SmBusPei.DXS DEPEX1_TYPE=EFI_SECTION_PEI_DEPEX \ + COMPRESS=0 + +SmBusPciHooksBin : + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\SmBus.mak all\ + NAME=AMISmBusLib\ + MAKEFILE=$(BUILD_DIR)\SmBus.mak\ + OBJECTS="$(SMBUS_PCI_OBJECTS)"\ + TYPE=LIBRARY\ + "CFLAGS=$(CFLAGS)" + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#********************************************************************** diff --git a/Chipset/SB/SmBus/SmBus.sdl b/Chipset/SB/SmBus/SmBus.sdl new file mode 100644 index 0000000..e7e6dcb --- /dev/null +++ b/Chipset/SB/SmBus/SmBus.sdl @@ -0,0 +1,61 @@ +TOKEN + Name = "SmBus_SUPPORT" + Value = "1" + Help = "Main switch to enable SmBus support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Token = "PI_SPECIFICATION_VERSION" ">=" "0x10000" +End + +TOKEN + Name = "SMBUS_BLINDING_PROTOCOL_SUPPORT" + Value = "1" + Help = "On - SMBus EFI 1.1 driver support." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "PCH_SPD_WRITE_DISABLE" + Value = "1" + Help = "0: Turn off SPD Write Disable.\1: Turn on SPD Write Disable." + TokenType = Integer + TargetH = Yes +End + +PATH + Name = "SmBus_DIR" +End + +MODULE + Help = "Includes SmBus.mak to Project" + File = "SmBus.mak" +End + +ELINK + Name = "$(BUILD_DIR)\SmBusPei.ffs" + Parent = "FV_BB" + Help = "Template Smbus PEI component" + InvokeOrder = AfterParent +End + +#ELINK +# Name = "$(BUILD_DIR)\SmBusDxe.ffs" +# Parent = "FV_MAIN" +# Help = "Template Smbus DXE component" +# InvokeOrder = AfterParent +#End + +ELINK + Name = "OEM_PCI_DEVICE_CALLBACK(0, 0, SmBusProtectedPciDevice)," + Parent = "OEM_SKIP_PCI_DEVICE" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(BUILD_DIR)\AMISmBusLib.lib" + Parent = "PCIBUSSRCLIB" + InvokeOrder = AfterParent +End diff --git a/Chipset/SB/SmBus/SmBusCommon.c b/Chipset/SB/SmBus/SmBusCommon.c new file mode 100644 index 0000000..e4fbae7 --- /dev/null +++ b/Chipset/SB/SmBus/SmBusCommon.c @@ -0,0 +1,559 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusCommon.c 1 6/06/12 8:00a Victortu $ +// +// $Revision: 1 $ +// +// $Date: 6/06/12 8:00a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusCommon.c $ +// +// 1 6/06/12 8:00a Victortu +// Implement EFI_PEI_SMBUS2_PPI Support. +// +// 5 6/27/11 2:26p Artems +// Updated year in file header +// +// 4 6/17/11 5:53p Artems +// EIP 53378: Replaced tabs with spaces, formatted to follow coding +// standard +// +// 3 10/16/09 7:21p Artems +// Updated copyright header +// +// 2 1/28/09 6:52p Artems +// Modified in accordance with coding standard +// +// 1 1/09/09 6:53p Artems +// New implementation of SMBus EIP 16730 +// +// 1 3/18/07 5:23p Felixp +// +//********************************************************************** + +//<AMI_FHDR_START> +//---------------------------------------------------------------------- +// +// Name: SmBusCommon.c +// +// Description: SMBUS driver common functions implementation +// +//---------------------------------------------------------------------- +//<AMI_FHDR_END> + +#include <AmiLib.h> +#include "SmBusCommon.h" + +UINT8 SmBusSpecReservedAddress[SMBUS_SPEC_RESERVED_ADDRESS] = { + 0x00, // 0000 000 0 General Call Address + // 0000 000 1 START byte + 0x01, // 0000 001 X CBUS address + 0x02, // 0000 010 X Address reserved for different bus format + 0x03, // 0000 011 X Reserved for future use + 0x04, // 0000 1XX X Reserved for future use + 0x05, + 0x06, + 0x07, + 0x28, // 0101 000 X Reserved for ACCESS.bus host + 0x37, // 0110 111 X Reserved for ACCESS.bus default address + 0x78, // 1111 0XX X 10-bit slave addressing + 0x79, + 0x7a, + 0x7b, + 0x7c, // 1111 1XX X Reserved for future use + 0x7d, + 0x7e, + 0x7f, + 0x08, // 0001 000 X SMBus Host + 0x0c, // 0001 100 X SMBus Alert Response Address + 0x61 // 1100 001 X SMBus Device Default Address +}; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmBusRead +// +// Description: This function reads given number of bytes from SMBUS device +// +// Input: IN UINT16 SmBusBase - SMBUS device IO address base +// IN UINT16 Offset - SMBUS device IO address offset +// IN UINTN ByteCount - number of bytes to read +// OUT UINT8 *Buffer - pointer to buffer to store data +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID SmBusRead ( + IN UINT16 SmBusBase, + IN UINT16 Offset, + IN UINTN ByteCount, + OUT UINT8 *Buffer +) +{ + UINTN i; + + for(i = 0; i < ByteCount; i++) + Buffer[i] = IoRead8(SmBusBase + Offset); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmBusWrite +// +// Description: This function writes given number of bytes to SMBUS device +// +// Input: IN UINT16 SmBusBase - SMBUS device IO address base +// IN UINT16 Offset - SMBUS device IO address offset +// IN UINTN ByteCount - number of bytes to write +// IN UINT8 *Buffer - pointer to buffer to get data from +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID SmBusWrite ( + IN UINT16 SmBusBase, + IN UINT16 Offset, + IN UINTN ByteCount, + IN UINT8 *Buffer +) +{ + UINTN i; + + for(i = 0; i < ByteCount; i++) + IoWrite8(SmBusBase + Offset, Buffer[i]); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ArpDevice +// +// Description: This function assign address to specific or all devices connected to SMBUS +// +// Input: IN SMBUS_PRIVATE *Context - SMBUS device private data +// IN BOOLEAN ArpAll - Enumerate all devices flag +// IN EFI_SMBUS_UDID *SmbusUdid - pointer to device ID to assign new address +// IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress - pointer to return assigned address +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS ArpDevice ( + IN SMBUS_PRIVATE *Context, + IN BOOLEAN ArpAll, + IN EFI_SMBUS_UDID *SmbusUdid, OPTIONAL + IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress OPTIONAL +) +{ + if(ArpAll) + return ArpDeviceFull(Context); + else + return ArpDeviceDirected(Context, SmbusUdid, SlaveAddress); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: GetArpMap +// +// Description: This function returns list of enumerated devices connected to SMBUS +// +// Input: IN SMBUS_PRIVATE *Context - SMBUS device private data +// IN OUT UINTN *Length - pointer to store size of address map +// IN OUT EFI_SMBUS_DEVICE_MAP **SmbusDeviceMap - pointer to store pointer to address map +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS GetArpMap ( + IN SMBUS_PRIVATE *Context, + IN OUT UINTN *Length, + IN OUT EFI_SMBUS_DEVICE_MAP **SmbusDeviceMap +) +{ + *Length = Context->ArpDeviceCount; + *SmbusDeviceMap = Context->ArpDeviceList; + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PrepareToArp +// +// Description: This function sends PREPARE_TO_ARP command to devices connected to SMBUS +// +// Input: IN SMBUS_PRIVATE *Context - SMBUS device private data +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS PrepareToArp ( + IN SMBUS_PRIVATE *Context +) +{ + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + EFI_STATUS Status; + UINTN Length; + UINT8 Buffer; + + SlaveAddress.SmbusDeviceAddress = SMBUS_ADDRESS_ARP; + Length = 1; + Buffer = SMBUS_DATA_PREPARE_TO_ARP; + + Status = Execute ( + Context, + SlaveAddress, + SMBUS_DATA_PREPARE_TO_ARP, + EfiSmbusSendByte, + TRUE, + &Length, + &Buffer ); + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: IsAddressAvailable +// +// Description: This function checks if given address is available +// +// Input: IN SMBUS_PRIVATE *Context - SMBUS device private data +// IN UINT8 Address - address to check +// +// Output: TRUE - address is available +// FALSE - address is not available +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +BOOLEAN IsAddressAvailable ( + IN SMBUS_PRIVATE *Context, + IN UINT8 Address +) +{ + UINTN Index; + + for(Index = 0; Index < Context->ArpDeviceCount; Index++) + if(Address == Context->ArpDeviceList[Index].SmbusDeviceAddress.SmbusDeviceAddress) + return FALSE; + + for(Index = 0; Index < Context->BoardReservedAddressCount; Index++) + if(Address == Context->BoardReservedAddressList[Index]) + return FALSE; + + for(Index = 0; Index < SMBUS_SPEC_RESERVED_ADDRESS; Index++) + if(Address == SmBusSpecReservedAddress[Index]) + return FALSE; + + return TRUE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: GetAvailableAddress +// +// Description: This function returns available address +// +// Input: IN SMBUS_PRIVATE *Context - SMBUS device private data +// +// Output: UINT8 - address +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8 GetAvailableAddress ( + IN SMBUS_PRIVATE *Context +) +{ + UINT8 Address; + + for(Address = SMBUS_LOWEST_AVAILABLE_ADDRESS; + Address <= SMBUS_HIGHEST_AVAILABLE_ADDRESS; + Address++) + if(IsAddressAvailable(Context, Address)) + return Address; + + return 0xff; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ArpDeviceFull +// +// Description: This function enumerates all devices connected to SMBUS +// +// Input: IN SMBUS_PRIVATE *Context - SMBUS device private data +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS ArpDeviceFull ( + IN SMBUS_PRIVATE *Context +) +{ + EFI_SMBUS_DEVICE_MAP DeviceMap; + EFI_STATUS Status; + + Status = PrepareToArp(Context); + if(EFI_ERROR(Status)) + return (Status == EFI_DEVICE_ERROR) ? EFI_SUCCESS : Status; + + do + { + Status = GetUdidGeneral(Context, &DeviceMap); + if(EFI_ERROR(Status)) + break; + + if(DeviceMap.SmbusDeviceAddress.SmbusDeviceAddress == 0x7f) //0xff >> 1 + { + DeviceMap.SmbusDeviceAddress.SmbusDeviceAddress = GetAvailableAddress(Context); + if(DeviceMap.SmbusDeviceAddress.SmbusDeviceAddress == 0xff) + return EFI_OUT_OF_RESOURCES; + } + else + { + if((DeviceMap.SmbusDeviceUdid.DeviceCapabilities & 0xC0) != 0 && + !IsAddressAvailable(Context, (UINT8)DeviceMap.SmbusDeviceAddress.SmbusDeviceAddress)) + { + DeviceMap.SmbusDeviceAddress.SmbusDeviceAddress = GetAvailableAddress(Context); + if(DeviceMap.SmbusDeviceAddress.SmbusDeviceAddress == 0xff) + return EFI_OUT_OF_RESOURCES; + } + } + + Status = AssignAddress(Context, &DeviceMap); + if(EFI_ERROR(Status)) + return Status; + + //save assigned address to our database + Context->ArpDeviceList[Context->ArpDeviceCount] = DeviceMap; + Context->ArpDeviceCount++; + } while(Context->ArpDeviceCount < Context->MaxDevices); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ArpDeviceDirected +// +// Description: This function assign given address to given device +// +// Input: IN SMBUS_PRIVATE *Context - SMBUS device private data +// IN EFI_SMBUS_UDID *SmbusUdid - pointer to device ID +// IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress - pointer to return assigned address +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS ArpDeviceDirected ( + IN SMBUS_PRIVATE *Context, + IN EFI_SMBUS_UDID *SmbusUdid, + IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress +) +{ + UINT8 AssignedAddress; + EFI_SMBUS_DEVICE_MAP DeviceMap; + EFI_STATUS Status; + + if(Context->ArpDeviceCount > Context->MaxDevices) + return EFI_OUT_OF_RESOURCES; + + AssignedAddress = GetAvailableAddress(Context); + if(AssignedAddress == 0xff) + return EFI_OUT_OF_RESOURCES; + + DeviceMap.SmbusDeviceAddress.SmbusDeviceAddress = AssignedAddress; + DeviceMap.SmbusDeviceUdid = *SmbusUdid; + + Status = AssignAddress(Context, &DeviceMap); + if(EFI_ERROR(Status)) + return Status; + +//save assigned address to our database + Context->ArpDeviceList[Context->ArpDeviceCount] = DeviceMap; + Context->ArpDeviceCount++; + + *SlaveAddress = DeviceMap.SmbusDeviceAddress; + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: AssignAddress +// +// Description: This function sends ASSIGN_ADDRESS command via SMBUS +// +// Input: IN SMBUS_PRIVATE *Context - SMBUS device private data +// IN EFI_SMBUS_DEVICE_MAP *DeviceMap - pointer to device Udid/Address pair +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS AssignAddress ( + IN SMBUS_PRIVATE *Context, + IN EFI_SMBUS_DEVICE_MAP *DeviceMap + ) +{ + UINT8 Buffer[GET_UDID_BUFFER_SIZE]; + UINTN Length; + EFI_STATUS Status; + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + + ConvertMapToBuffer(DeviceMap, Buffer); + + Length = GET_UDID_BUFFER_SIZE; + SlaveAddress.SmbusDeviceAddress = SMBUS_ADDRESS_ARP; + + Status = Execute ( + Context, + SlaveAddress, + SMBUS_DATA_ASSIGN_ADDRESS, + EfiSmbusWriteBlock, + TRUE, + &Length, + Buffer ); + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: GetUdidGeneral +// +// Description: This function sends GET_UDID_GENERAL command via SMBUS +// +// Input: IN SMBUS_PRIVATE *Context - SMBUS device private data +// OUT EFI_SMBUS_DEVICE_MAP *DeviceMap - pointer to store device Udid/Address pair +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS GetUdidGeneral ( + IN SMBUS_PRIVATE *Context, + OUT EFI_SMBUS_DEVICE_MAP *DeviceMap +) +{ + UINT8 Buffer[GET_UDID_BUFFER_SIZE]; + UINTN Length; + EFI_STATUS Status; + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + + Length = GET_UDID_BUFFER_SIZE; + SlaveAddress.SmbusDeviceAddress = SMBUS_ADDRESS_ARP; + + Status = Execute ( + Context, + SlaveAddress, + SMBUS_DATA_GET_UDID_GENERAL, + EfiSmbusReadBlock, + TRUE, + &Length, + Buffer ); + + if(EFI_ERROR(Status) || Length != GET_UDID_BUFFER_SIZE) + return EFI_DEVICE_ERROR; + + ConvertBufferToMap(DeviceMap, Buffer); + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ConvertMapToBuffer +// +// Description: This function converts EFI_SMBUS_DEVICE_MAP structure into UINT8[] buffer +// +// Input: IN EFI_SMBUS_DEVICE_MAP *DeviceMap - pointer to structure to convert from +// OUT UINT8 *Buffer - pointer buffer to convert to +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID ConvertMapToBuffer ( + IN EFI_SMBUS_DEVICE_MAP *DeviceMap, + OUT UINT8 *Buffer +) +{ + Buffer[0] = DeviceMap->SmbusDeviceUdid.DeviceCapabilities; + Buffer[1] = DeviceMap->SmbusDeviceUdid.VendorRevision; + Buffer[2] = (UINT8)(DeviceMap->SmbusDeviceUdid.VendorId >> 8); + Buffer[3] = (UINT8)(DeviceMap->SmbusDeviceUdid.VendorId); + Buffer[4] = (UINT8)(DeviceMap->SmbusDeviceUdid.DeviceId >> 8); + Buffer[5] = (UINT8)(DeviceMap->SmbusDeviceUdid.DeviceId); + Buffer[6] = (UINT8)(DeviceMap->SmbusDeviceUdid.Interface >> 8); + Buffer[7] = (UINT8)(DeviceMap->SmbusDeviceUdid.Interface); + Buffer[8] = (UINT8)(DeviceMap->SmbusDeviceUdid.SubsystemVendorId >> 8); + Buffer[9] = (UINT8)(DeviceMap->SmbusDeviceUdid.SubsystemVendorId); + Buffer[10] = (UINT8)(DeviceMap->SmbusDeviceUdid.SubsystemDeviceId >> 8); + Buffer[11] = (UINT8)(DeviceMap->SmbusDeviceUdid.SubsystemDeviceId); + Buffer[12] = (UINT8)(DeviceMap->SmbusDeviceUdid.VendorSpecificId >> 24); + Buffer[13] = (UINT8)(DeviceMap->SmbusDeviceUdid.VendorSpecificId >> 16); + Buffer[14] = (UINT8)(DeviceMap->SmbusDeviceUdid.VendorSpecificId >> 8); + Buffer[15] = (UINT8)(DeviceMap->SmbusDeviceUdid.VendorSpecificId); + Buffer[16] = (UINT8)(DeviceMap->SmbusDeviceAddress.SmbusDeviceAddress << 1); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ConvertBufferToMap +// +// Description: This function converts UINT8[] buffer into EFI_SMBUS_DEVICE_MAP structure +// +// Input: OUT EFI_SMBUS_DEVICE_MAP *DeviceMap - pointer to structure to convert to +// IN UINT8 *Buffer - pointer buffer to convert from +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID ConvertBufferToMap ( + OUT EFI_SMBUS_DEVICE_MAP *DeviceMap, + IN UINT8 *Buffer + ) +{ + DeviceMap->SmbusDeviceUdid.DeviceCapabilities = Buffer[0]; + DeviceMap->SmbusDeviceUdid.VendorRevision = Buffer[1]; + DeviceMap->SmbusDeviceUdid.VendorId = (UINT16)((Buffer[2] << 8) + Buffer[3]); + DeviceMap->SmbusDeviceUdid.DeviceId = (UINT16)((Buffer[4] << 8) + Buffer[5]); + DeviceMap->SmbusDeviceUdid.Interface = (UINT16)((Buffer[6] << 8) + Buffer[7]); + DeviceMap->SmbusDeviceUdid.SubsystemVendorId = (UINT16)((Buffer[8] << 8) + Buffer[9]); + DeviceMap->SmbusDeviceUdid.SubsystemDeviceId = (UINT16)((Buffer[10] << 8) + Buffer[11]); + DeviceMap->SmbusDeviceUdid.VendorSpecificId = (UINT32)((Buffer[12] << 24) + (Buffer[13] << 16) + (Buffer[14] << 8) + Buffer[15]); + DeviceMap->SmbusDeviceAddress.SmbusDeviceAddress = (UINT8)(Buffer[16] >> 1); +} + + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Chipset/SB/SmBus/SmBusCommon.h b/Chipset/SB/SmBus/SmBusCommon.h new file mode 100644 index 0000000..0dda40d --- /dev/null +++ b/Chipset/SB/SmBus/SmBusCommon.h @@ -0,0 +1,226 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusCommon.h 1 6/06/12 8:00a Victortu $ +// +// $Revision: 1 $ +// +// $Date: 6/06/12 8:00a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusCommon.h $ +// +// 1 6/06/12 8:00a Victortu +// Implement EFI_PEI_SMBUS2_PPI Support. +// +// 5 6/27/11 2:26p Artems +// Updated year in file header +// +// 4 6/17/11 5:52p Artems +// EIP 53378: Replaced tabs with spaces, formatted to follow coding +// standard +// +// 3 10/16/09 7:08p Artems +// Updated copyright header +// +// 2 1/28/09 6:52p Artems +// Modified in accordance with coding standard +// +// 1 1/09/09 6:53p Artems +// New implementation of SMBus EIP 16730 +// +// 1 3/18/07 5:23p Felixp +// +//********************************************************************** + +//<AMI_FHDR_START> +//---------------------------------------------------------------------- +// +// Name: SmBusCommon.h +// +// Description: This file contains shared PEI and DXE Smbus functions and +// data structures definitions +// +//---------------------------------------------------------------------- +//<AMI_FHDR_END> +#ifndef __SMBUS_COMMON__H__ +#define __SMBUS_COMMON__H__ +#ifdef __cplusplus +extern "C" { +#endif + +#include <Efi.h> +#include <AmiCspLib.h> +#include <SmBus.h> + +#define SMBUS_ADDRESS_ARP 0x61 // 1100 001 X SMBus Device Default Address + +#define SMBUS_DATA_PREPARE_TO_ARP 0x01 +#define SMBUS_DATA_RESET_DEVICE 0x02 +#define SMBUS_DATA_GET_UDID_GENERAL 0x03 +#define SMBUS_DATA_ASSIGN_ADDRESS 0x04 + +#define SMBUS_SPEC_RESERVED_ADDRESS 21 +#define GET_UDID_BUFFER_SIZE 17 + +#define SMBUS_LOWEST_AVAILABLE_ADDRESS 0x08 +#define SMBUS_HIGHEST_AVAILABLE_ADDRESS 0x77 + +typedef VOID (* SMBUS_WAIT ) ( + IN UINTN Microseconds + ); + +//<AMI_THDR_START> +//---------------------------------------------------------------------------- +// Name: SMBUS_PRIVATE +// +// Description: AMI SMBUS driver private data structure +// +// Fields: Name Type Description +//---------------------------------------------------------------------------- +// SmBusBase UINT16 SMBUS device base IO address +// SmBusWait SMBUS_WAIT Pointer to Wait function +// MaxDevices UINT8 Maximum number of supported devices +// BoardReservedAddressCount UINT8 Number of board reserved addesses +// BoardReservedAddressList UINT8* Pointer to board reserved addresses list +// ArpDeviceCount UINT8 Number of current devices +// ArpDeviceList EFI_SMBUS_DEVICE_MAP* Pointer to list of current devices +// +//---------------------------------------------------------------------------- +//<AMI_THDR_END> +typedef struct _SMBUS_PRIVATE +{ + UINT16 SmBusBase; + SMBUS_WAIT SmBusWait; + UINT8 MaxDevices; + UINT8 BoardReservedAddressCount; + UINT8 *BoardReservedAddressList; + UINT8 ArpDeviceCount; + EFI_SMBUS_DEVICE_MAP *ArpDeviceList; + +} SMBUS_PRIVATE; + + +//******************************************************* +// Shared functions prototypes +//******************************************************* + +VOID SmBusRead ( + IN UINT16 SmBusBase, + IN UINT16 Offset, + IN UINTN ByteCount, + OUT UINT8 *Buffer +); + +VOID SmBusWrite ( + IN UINT16 SmBusBase, + IN UINT16 Offset, + IN UINTN ByteCount, + IN UINT8 *Buffer +); + +EFI_STATUS Execute ( + IN SMBUS_PRIVATE *Context, + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN EFI_SMBUS_DEVICE_COMMAND Command, + IN EFI_SMBUS_OPERATION Operation, + IN BOOLEAN PecCheck, + IN OUT UINTN *Length, + IN OUT VOID *Buffer +); + +EFI_STATUS CheckNotify ( + IN SMBUS_PRIVATE *Context, + OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress, + OUT UINTN *Data +); + +EFI_STATUS ArpDevice ( + IN SMBUS_PRIVATE *Context, + IN BOOLEAN ArpAll, + IN EFI_SMBUS_UDID *SmbusUdid, OPTIONAL + IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress OPTIONAL +); + +EFI_STATUS GetArpMap ( + IN SMBUS_PRIVATE *Context, + IN OUT UINTN *Length, + IN OUT EFI_SMBUS_DEVICE_MAP **SmbusDeviceMap +); + +EFI_STATUS PrepareToArp ( + IN SMBUS_PRIVATE *Context +); + +EFI_STATUS ArpDeviceDirected ( + IN SMBUS_PRIVATE *Context, + IN EFI_SMBUS_UDID *SmbusUdid, + IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress +); + +EFI_STATUS ArpDeviceFull ( + IN SMBUS_PRIVATE *Context +); + +EFI_STATUS AssignAddress ( + IN SMBUS_PRIVATE *Context, + IN EFI_SMBUS_DEVICE_MAP *DeviceMap +); + +EFI_STATUS GetUdidGeneral ( + IN SMBUS_PRIVATE *Context, + OUT EFI_SMBUS_DEVICE_MAP *DeviceMap +); + +BOOLEAN IsAddressAvailable ( + IN SMBUS_PRIVATE *Context, + IN UINT8 Address +); + +UINT8 GetAvailableAddress ( + IN SMBUS_PRIVATE *Context +); + +VOID ConvertMapToBuffer ( + IN EFI_SMBUS_DEVICE_MAP *DeviceMap, + OUT UINT8 *Buffer +); + +VOID ConvertBufferToMap ( + OUT EFI_SMBUS_DEVICE_MAP *DeviceMap, + IN UINT8 *Buffer +); + +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + diff --git a/Chipset/SB/SmBus/SmBusDxe.c b/Chipset/SB/SmBus/SmBusDxe.c new file mode 100644 index 0000000..2aee2ff --- /dev/null +++ b/Chipset/SB/SmBus/SmBusDxe.c @@ -0,0 +1,940 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusDxe.c 1 6/06/12 8:00a Victortu $ +// +// $Revision: 1 $ +// +// $Date: 6/06/12 8:00a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusDxe.c $ +// +// 1 6/06/12 8:00a Victortu +// Implement EFI_PEI_SMBUS2_PPI Support. +// +// 11 7/21/11 7:32a Abelwu +// [TAG] None +// [Category] New Feature +// [Description] Added SMBus SMM protocol support. +// [Files] SmBusDxe.c +// +// 10 7/19/11 8:28a Abelwu +// [TAG] EIP63768 +// [Category] Improvement +// [Description] 1. Supported Core 4.6.5.x PI 1.2 / uEFI 2.3.1 +// compliance +// 2. Added SMBus SMM protocol support. +// +// 9 6/17/11 5:54p Artems +// EIP 53378: Replaced tabs with spaces, formatted to follow coding +// standard +// +// 8 5/18/11 11:51a Artems +// +// 7 1/27/11 9:48p Abelwu +// Supports SMBUS Protocol in early DXE phase. (EIP#40778) +// +// 6 10/13/10 4:16p Artems +// EIP 45184 - fixed pointer size to be same in IA32 and X64 mode +// +// 5 10/16/09 7:32p Artems +// Updated copyright header +// +// 4 3/03/09 4:36p Artems +// EIP 19949 Added support for multiple SM Bus controllers that +// represented by different PCI devices +// +// 3 1/29/09 4:20p Artems +// Change "Note" to "Notes" for HelpBuilder +// +// 2 1/28/09 6:51p Artems +// Modified in accordance with coding standard +// +// 1 1/09/09 6:53p Artems +// New implementation of SMBus EIP 16730 +// +// 1 3/18/07 5:23p Felixp +// +//********************************************************************** + +//<AMI_FHDR_START> +//---------------------------------------------------------------------- +// +// Name: SmBusDxe.c +// +// Description: SMBUS DXE functions implementation +// +//---------------------------------------------------------------------- +//<AMI_FHDR_END> + +#include <AmiHobs.h> +#include "SmBusDxe.h" +#include <Protocol\PciRootBridgeIo.h> + +#define MICROSECOND 10 +#define MILLISECOND (1000 * MICROSECOND) +#define ONESECOND (1000 * MILLISECOND) + +extern EFI_GUID SmBusIdentifierGuid; + +EFI_DRIVER_BINDING_PROTOCOL SmBusDriverBindingProtocol = { + DriverBindingSupported, + DriverBindingStart, + DriverBindingStop, + 0x10, + NULL, + NULL + }; + +SMBUS_DXE_PRIVATE *gPrivate; +EFI_HANDLE gControllerHandle = NULL; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmBusEarlyDxeDriver +// +// Description: This function configures and installs SMBUS protocol before +// SMBus EFI 1.1 drvier is installed. +// +// Input: None +// +// Output: EFI_STATUS +// EFI_SUCCESS - SMBUS protocol has been installed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmBusEarlyDxeDriver ( VOID ) +{ + EFI_STATUS Status; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo = NULL; + EFI_GUID EfiPciRootBridgeIoProtocolGuid = \ + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID; +/* Porting Required + UINT32 IoBase32; + UINT16 Cmd16; +Porting End */ + + Status = pBS->AllocatePool( EfiBootServicesData, \ + sizeof(SMBUS_DXE_PRIVATE), \ + &gPrivate ); + if (EFI_ERROR(Status)) return Status; + + Status = pBS->AllocatePool( \ + EfiBootServicesData, \ + sizeof(EFI_SMBUS_DEVICE_MAP) * MAX_DXE_ARP_DEVICES, \ + &(gPrivate->SmBusContext.ArpDeviceList) ); + if (EFI_ERROR(Status)) { + pBS->FreePool( gPrivate ); + return Status; + } + + gPrivate->SmBusProtocol.Execute = SmBusDxeExecute; + gPrivate->SmBusProtocol.ArpDevice = SmBusDxeArpDevice; + gPrivate->SmBusProtocol.GetArpMap = SmBusDxeGetArpMap; + gPrivate->SmBusProtocol.Notify = SmBusDxeNotify; + + gPrivate->NotifyEvent = NULL; + gPrivate->Identifier = SmBusIdentifierGuid; + + gPrivate->SmBusContext.SmBusWait = SmBusDxeWait; + gPrivate->SmBusContext.MaxDevices = MAX_DXE_ARP_DEVICES; + RetrieveHobData( gPrivate ); + +/* Porting Required + Status = pBS->LocateProtocol( &EfiPciRootBridgeIoProtocolGuid, \ + NULL, \ + &PciRootBridgeIo ); + // Update SMBus I/O Base Address + PciRootBridgeIo->Pci.Read( PciRootBridgeIo, \ + EfiPciWidthUint32, \ + SMBUS_REG(SMBUS_REG_BASE_ADDR), \ + 1, \ + &IoBase32 ); + IoBase32 &= 0xfffffffe; + gPrivate->SmBusContext.SmBusBase = (UINT16)IoBase32; + + // Enable SMBus controller I/O decode. + PciRootBridgeIo->Pci.Read( PciRootBridgeIo, \ + EfiPciWidthUint16, \ + SMBUS_REG(SMBUS_REG_PCICMD), \ + 1, \ + &Cmd16 ); + Cmd16 |= 1; + PciRootBridgeIo->Pci.Write( PciRootBridgeIo, \ + EfiPciWidthUint16, \ + SMBUS_REG(SMBUS_REG_PCICMD), \ + 1, \ + &Cmd16 ); +Porting End */ + + Status = pBS->InstallProtocolInterface( &gControllerHandle, \ + &gEfiSmbusProtocolGuid, \ + EFI_NATIVE_INTERFACE, + &gPrivate->SmBusProtocol ); + + if (EFI_ERROR(Status)) { + TRACE((-1, "SBSmbusDxe: Install Protocol Interface Failed.\n")); + } + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmBusSmmExecute +// +// Description: This Protocol Function can be used to execute SMBus command +// on a particular SMBus controller in SMM. +// +// Input: *This - Pointer to the SMBus Protocol structure +// SlaveAddress - Address of the SMBus device +// Command - Command to be sent to the device +// Operation - SMBus operation to be performed +// PecCheck - Flag indicating the usage of PEC +// *Length - Length of the data in the Buffer (IN or OUT) +// *Buffer - Pointer to the buffer with the data (IN or OUT) +// +// Output: EFI_STATUS +// +// Notes: PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmBusSmmExecute ( + IN EFI_SMBUS_HC_PROTOCOL *This, + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN EFI_SMBUS_DEVICE_COMMAND Command, + IN EFI_SMBUS_OPERATION Operation, + IN BOOLEAN PecCheck, + IN OUT UINTN *Length, + IN OUT VOID *Buffer ) +{ + EFI_STATUS Status = EFI_UNSUPPORTED; +/* + // Porting Required + UINT16 SmBusBase = READ_PCI16_SMBUS(SMBUS_REG_BASE_ADDR) & 0xfff0; + UINT16 SmBusCmd = READ_PCI16_SMBUS(SMBUS_REG_PCICMD); + + if (SmBusBase == 0) { // Assign a new I/O if the original address is 0 + WRITE_PCI16_SMBUS(SMBUS_REG_BASE_ADDR, SMBUS_BASE_ADDRESS); + SmBusBase = SMBUS_BASE_ADDRESS; + } + + gPrivate->SmBusContext.SmBusBase = SmBusBase; + + if ((SmBusCmd & 1) == 0) { // Enable I/O command if needed. + WRITE_PCI16_SMBUS(SMBUS_REG_PCICMD, 1); + } + // Porting End + + Status = Execute( &(((SMBUS_DXE_PRIVATE *)This)->SmBusContext), \ + SlaveAddress, \ + Command, \ + Operation, \ + PecCheck, \ + Length, \ + Buffer ); + + // Porting Required + // Restore the SMBus PCI Command Register + WRITE_PCI16_SMBUS(SMBUS_REG_PCICMD, SmBusCmd); + // Porting End +*/ + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SMBusInSmmInit +// +// Description: This function installs SMBus SMM protocol for the SMBus +// controller present in the SB. +// +// Input: ImageHandle - Image handle for the SB component +// *SystemTable - Pointer to the system table +// +// Output: EFI_STATUS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SMBusInSmmInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status = EFI_SUCCESS; + EFI_HANDLE Handle = NULL; + EFI_GUID SmmSmbusProtocolGuid = \ + AMI_SMBUS_SMM_PROTOCOL_GUID; + static SMBUS_DXE_PRIVATE SmbusSmmPrivate; + + gPrivate = &SmbusSmmPrivate; + gPrivate->SmBusProtocol.Execute = SmBusSmmExecute; + gPrivate->SmBusProtocol.ArpDevice = SmBusDxeArpDevice; + gPrivate->SmBusProtocol.GetArpMap = SmBusDxeGetArpMap; + gPrivate->SmBusProtocol.Notify = SmBusDxeNotify; + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A) + Status = InitAmiSmmLib( ImageHandle, SystemTable ); + if (EFI_ERROR(Status)) return Status; + + return pSmst->SmmInstallProtocolInterface( &Handle, \ + &SmmSmbusProtocolGuid, \ + EFI_NATIVE_INTERFACE, \ + &gPrivate->SmBusProtocol ); +#else + return pBS->InstallProtocolInterface( &Handle, + &SmmSmbusProtocolGuid, + EFI_NATIVE_INTERFACE, + &gPrivate->SmBusProtocol ); +#endif +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SMBusNotInSmmInit +// +// Description: This function installs SMBus DXE protocol for the SMBus +// controller present in the SB. +// +// Input: ImageHandle - Image handle for the SB component +// *SystemTable - Pointer to the system table +// +// Output: EFI_STATUS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SMBusNotInSmmInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status; + + Status = SmBusEarlyDxeDriver(); + +#if SMBUS_BLINDING_PROTOCOL_SUPPORT + SmBusDriverBindingProtocol.ImageHandle = ImageHandle; + SmBusDriverBindingProtocol.DriverBindingHandle = ImageHandle; + Status = pBS->InstallMultipleProtocolInterfaces( \ + &ImageHandle, \ + &gEfiDriverBindingProtocolGuid, \ + &SmBusDriverBindingProtocol, \ + NULL ); +#endif + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmBusDxeEntryPoint +// +// Description: This function installs SMBus DXE/SMM protocols for the SMBus +// controller present in the SB. +// +// Input: ImageHandle - Image handle for the SB component +// *SystemTable - Pointer to the system table +// +// Output: EFI_STATUS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmBusDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + InitAmiLib(ImageHandle, SystemTable); + + return InitSmmHandlerEx( ImageHandle, \ + SystemTable, \ + SMBusInSmmInit, \ + SMBusNotInSmmInit ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: DriverBindingSupported +// +// Description: SMBUS DXE Driver binding protocol Supported function +// +// Input: IN EFI_DRIVER_BINDING_PROTOCOL* This - pointer to EFI_DRIVER_BINDING_PROTOCOL structure +// IN EFI_HANDLE ControllerHandle - handle of controller to serve +// IN EFI_DEVICE_PATH_PROTOCOL* RemainingDevicePath - pointer to EFI_DEVICE_PATH_PROTOCOL structure +// +// Output: EFI_SUCCESS - driver supports given controller +// EFI_UNSUPPORTED - given controller not supported +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS DriverBindingSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath +) +{ + EFI_STATUS Status; + EFI_PCI_IO_PROTOCOL *PciIo; + UINT8 PciData[4]; + + Status = pBS->OpenProtocol ( + ControllerHandle, + &gEfiPciIoProtocolGuid, + (VOID **) &PciIo, + This->DriverBindingHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_BY_DRIVER ); + if (EFI_ERROR (Status)) + return EFI_UNSUPPORTED; + + // + // See if this is a PCI Smbus Controller by looking at the Class Code Register + // + Status = PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint32, + 0x8, + 1, + (VOID *)PciData ); + if (EFI_ERROR (Status)) + return EFI_UNSUPPORTED; + + pBS->CloseProtocol ( + ControllerHandle, + &gEfiPciIoProtocolGuid, + This->DriverBindingHandle, + ControllerHandle ); + + return (PciData[3] == 0x0c && PciData[2] == 0x05) ? EFI_SUCCESS : EFI_UNSUPPORTED; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: DriverBindingStart +// +// Description: SMBUS DXE Driver binding protocol Start function +// +// Input: IN EFI_DRIVER_BINDING_PROTOCOL* This - pointer to EFI_DRIVER_BINDING_PROTOCOL structure +// IN EFI_HANDLE ControllerHandle - handle of controller to serve +// IN EFI_DEVICE_PATH_PROTOCOL* RemainingDevicePath - pointer to EFI_DEVICE_PATH_PROTOCOL structure +// +// Output: EFI_SUCCESS - driver supports given controller +// EFI_UNSUPPORTED - given controller not supported +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS DriverBindingStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath +) +{ + EFI_STATUS Status; + SMBUS_DXE_PRIVATE *Private; + static BOOLEAN EarlyDxeProtocol = TRUE; + + if (EarlyDxeProtocol) { + Status = pBS->UninstallProtocolInterface( gControllerHandle, \ + &gEfiSmbusProtocolGuid, \ + &gPrivate->SmBusProtocol ); + if (Status == EFI_SUCCESS) { + pBS->FreePool( gPrivate->SmBusContext.ArpDeviceList ); + pBS->FreePool( gPrivate ); + } + EarlyDxeProtocol = FALSE; + } + + Status = pBS->AllocatePool(EfiBootServicesData, + sizeof(SMBUS_DXE_PRIVATE), + &Private); + if(EFI_ERROR(Status)) + return Status; + + Status = pBS->AllocatePool(EfiBootServicesData, + sizeof(EFI_SMBUS_DEVICE_MAP) * MAX_DXE_ARP_DEVICES, + &(Private->SmBusContext.ArpDeviceList)); + if(EFI_ERROR(Status)) + return Status; + + Status = pBS->OpenProtocol ( + ControllerHandle, + &gEfiPciIoProtocolGuid, + (VOID **) &(Private->PciIo), + This->DriverBindingHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_BY_DRIVER ); + if (EFI_ERROR (Status)) + { + pBS->FreePool(Private->SmBusContext.ArpDeviceList); + pBS->FreePool(Private); + return Status; + } + + Private->SmBusProtocol.Execute = SmBusDxeExecute; + Private->SmBusProtocol.ArpDevice = SmBusDxeArpDevice; + Private->SmBusProtocol.GetArpMap = SmBusDxeGetArpMap; + Private->SmBusProtocol.Notify = SmBusDxeNotify; + + Private->NotifyEvent = NULL; + Private->Identifier = SmBusIdentifierGuid; + + Private->SmBusContext.SmBusWait = SmBusDxeWait; + Private->SmBusContext.MaxDevices = MAX_DXE_ARP_DEVICES; + RetrieveHobData(Private); + +//TODO Fill Private->SmBusContext.SmBusBase with value read from PCI device + + DListInit(&(Private->NotifyList)); + + Status = pBS->InstallMultipleProtocolInterfaces( + &ControllerHandle, + &gEfiSmbusProtocolGuid, &Private->SmBusProtocol, + NULL); + if (EFI_ERROR (Status)) + { + pBS->CloseProtocol( + ControllerHandle, + &gEfiPciIoProtocolGuid, + This->DriverBindingHandle, + ControllerHandle ); + pBS->FreePool(Private->SmBusContext.ArpDeviceList); + pBS->FreePool(Private); + } + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: DriverBindingStop +// +// Description: SMBUS DXE Driver binding protocol Stop function +// +// Input: IN EFI_DRIVER_BINDING_PROTOCOL* This - pointer to EFI_DRIVER_BINDING_PROTOCOL structure +// IN EFI_HANDLE ControllerHandle - handle of controller to serve +// IN UINTN NumberOfChildren - number of child devices of controller +// IN EFI_HANDLE* ChildHandleBuffer - pointer to child devices handles array +// +// Output: EFI_SUCCESS - driver was successfully uninstalled from controller +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS DriverBindingStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer +) +{ + EFI_STATUS Status; + SMBUS_DXE_PRIVATE *Private; + EFI_SMBUS_HC_PROTOCOL *SmBusProtocol; + + Status = pBS->OpenProtocol ( + ControllerHandle, + &gEfiSmbusProtocolGuid, + &SmBusProtocol, + This->DriverBindingHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_GET_PROTOCOL ); + if (EFI_ERROR (Status)) + return EFI_NOT_STARTED; + + pBS->CloseProtocol ( + ControllerHandle, + &gEfiSmbusProtocolGuid, + This->DriverBindingHandle, + ControllerHandle ); + + Private = (SMBUS_DXE_PRIVATE *) SmBusProtocol; + + // uninstall the protocol + Status = pBS->UninstallMultipleProtocolInterfaces ( + ControllerHandle, + &gEfiSmbusProtocolGuid, &Private->SmBusProtocol, + NULL ); + if (EFI_ERROR (Status)) + return Status; + + if(Private->NotifyEvent != 0) + { + SMBUS_NOTIFY_LINK *NotifyLink = (SMBUS_NOTIFY_LINK *)(Private->NotifyList.pHead); + SMBUS_NOTIFY_LINK *DeleteLink; + + pBS->CloseEvent(Private->NotifyEvent); + while(NotifyLink != 0) + { + DeleteLink = NotifyLink; + NotifyLink = (SMBUS_NOTIFY_LINK *)NotifyLink->Link.pNext; + pBS->FreePool(DeleteLink); + } + } + + pBS->CloseProtocol ( + ControllerHandle, + &gEfiPciIoProtocolGuid, + This->DriverBindingHandle, + ControllerHandle ); + pBS->FreePool(Private->SmBusContext.ArpDeviceList); + pBS->FreePool(Private); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmBusPeiExecute +// +// Description: EFI_SMBUS_HC_PROTOCOL Execute function +// +// Input: IN EFI_SMBUS_HC_PROTOCOL *This - pointer to EFI_SMBUS_HC_PROTOCOL structure +// IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress - slave address +// IN EFI_SMBUS_DEVICE_COMMAND Command - command +// IN EFI_SMBUS_OPERATION Operation - operation +// IN BOOLEAN PecCheck - parity check flag +// IN OUT UINTN *Length - pointer to size of data buffer +// IN OUT VOID *Buffer - pointer to data buffer +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS SmBusDxeExecute ( + IN EFI_SMBUS_HC_PROTOCOL *This, + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN EFI_SMBUS_DEVICE_COMMAND Command, + IN EFI_SMBUS_OPERATION Operation, + IN BOOLEAN PecCheck, + IN OUT UINTN *Length, + IN OUT VOID *Buffer +) +{ + SMBUS_DXE_PRIVATE *Private = (SMBUS_DXE_PRIVATE *)This; + + return Execute( + &(Private->SmBusContext), + SlaveAddress, + Command, + Operation, + PecCheck, + Length, + Buffer); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmBusDxeArpDevice +// +// Description: EFI_SMBUS_HC_PROTOCOL ArpDevice function +// +// Input: IN EFI_SMBUS_HC_PROTOCOL *This - pointer to EFI_SMBUS_HC_PROTOCOL structure +// IN EFI_PEI_SMBUS_PPI *This - pointer to PPI +// IN BOOLEAN ArpAll - Enumerate all devices flag +// IN EFI_SMBUS_UDID *SmbusUdid - pointer to device ID to assign new address +// IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress - pointer to return assigned address +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS SmBusDxeArpDevice ( + IN EFI_SMBUS_HC_PROTOCOL *This, + IN BOOLEAN ArpAll, + IN EFI_SMBUS_UDID *SmbusUdid, OPTIONAL + IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress OPTIONAL +) +{ + SMBUS_DXE_PRIVATE *Private = (SMBUS_DXE_PRIVATE *)This; + + return ArpDevice( + &(Private->SmBusContext), + ArpAll, + SmbusUdid, + SlaveAddress); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmBusDxeGetArpMap +// +// Description: EFI_SMBUS_HC_PROTOCOL GetArpMap function +// +// Input: IN EFI_SMBUS_HC_PROTOCOL *This - pointer to EFI_SMBUS_HC_PROTOCOL structure +// IN OUT UINTN *Length - pointer to store size of address map +// IN OUT EFI_SMBUS_DEVICE_MAP **SmbusDeviceMap - pointer to store pointer to address map +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS SmBusDxeGetArpMap ( + IN EFI_SMBUS_HC_PROTOCOL *This, + IN OUT UINTN *Length, + IN OUT EFI_SMBUS_DEVICE_MAP **SmbusDeviceMap +) +{ + SMBUS_DXE_PRIVATE *Private = (SMBUS_DXE_PRIVATE *)This; + + return GetArpMap( + &(Private->SmBusContext), + Length, + SmbusDeviceMap); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmBusDxeNotify +// +// Description: EFI_SMBUS_HC_PROTOCOL Notify function +// +// Input: IN EFI_SMBUS_HC_PROTOCOL *This - pointer to EFI_SMBUS_HC_PROTOCOL structure +// IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress - address of notification device +// IN UINTN Data - notification data +// IN EFI_SMBUS_NOTIFY_FUNCTION NotifyFunction - pointer to callback function +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS SmBusDxeNotify ( + IN EFI_SMBUS_HC_PROTOCOL *This, + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN UINTN Data, + IN EFI_SMBUS_NOTIFY_FUNCTION NotifyFunction +) +{ + SMBUS_DXE_PRIVATE *Private = (SMBUS_DXE_PRIVATE *)This; + SMBUS_NOTIFY_LINK *NewLink; + EFI_STATUS Status; + + if(NotifyFunction == NULL) + return EFI_INVALID_PARAMETER; + + Status = pBS->AllocatePool(EfiBootServicesData, sizeof(SMBUS_NOTIFY_LINK), &NewLink); + if(EFI_ERROR(Status)) + return Status; + + NewLink->SlaveAddress = SlaveAddress; + NewLink->Data = Data; + NewLink->NotifyFunction = NotifyFunction; + + DListAdd(&(Private->NotifyList), (DLINK *)NewLink); + if(Private->NotifyList.Size == 1) + Status = InitializeNotifyPolling(Private); + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: InitializeNotifyPolling +// +// Description: Function initializes host notify polling periodic event +// +// Input: IN SMBUS_DXE_PRIVATE *Context - pointer to SMBUS device private data +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS InitializeNotifyPolling ( + IN SMBUS_DXE_PRIVATE *Context +) +{ + EFI_STATUS Status; + + Status = pBS->CreateEvent ( + (EFI_EVENT_TIMER | EFI_EVENT_NOTIFY_SIGNAL), + TPL_CALLBACK, + PollSmbusNotify, + Context, + &Context->NotifyEvent ); + if (EFI_ERROR(Status)) + return Status; + + Status = pBS->SetTimer ( + Context->NotifyEvent, + TimerPeriodic, + ONESECOND ); + if (EFI_ERROR(Status)) + return Status; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PollSmbusNotify +// +// Description: Function performs periodic check of host notifications +// +// Input: IN EFI_EVENT Event - periodic check event +// IN VOID *Context - event calling context +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID PollSmbusNotify ( + IN EFI_EVENT Event, + IN VOID *Context +) +{ + EFI_STATUS Status; + EFI_SMBUS_DEVICE_ADDRESS Address; + UINTN Data; + SMBUS_DXE_PRIVATE *Private = (SMBUS_DXE_PRIVATE *)Context; + SMBUS_NOTIFY_LINK *NotifyLink = (SMBUS_NOTIFY_LINK *)(Private->NotifyList.pHead); + + Status = CheckNotify(&(Private->SmBusContext), &Address, &Data); + if (EFI_ERROR(Status)) + return; + + while(NotifyLink != NULL) + { + if(Address.SmbusDeviceAddress == NotifyLink->SlaveAddress.SmbusDeviceAddress && + Data == NotifyLink->Data) + NotifyLink->NotifyFunction(Address, Data); + + NotifyLink = (SMBUS_NOTIFY_LINK *)NotifyLink->Link.pNext; + } +} + +//------------------------------------------------------------------- +// Struct EFI_SMBUS_DEVICE_MAP has one member, that declared as UINTN +// Due to this declaration this struct may have different size if +// compiled in x64 mode - 4 bytes in PEI and 8 bytes in DXE +// So we need mediator structure, to convert from PEI to DXE map, that +// was saved in Hob in PEI phase +//------------------------------------------------------------------- + +#pragma pack(1) +typedef struct { + UINT32 Address; + EFI_SMBUS_UDID Udid; +} PEI_EFI_SMBUS_DEVICE_MAP; +#pragma pack() + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: RetrieveHobData +// +// Description: Function reads device map created in PEI phase +// +// Input: IN OUT SMBUS_DXE_PRIVATE *Context - pointer to device private data +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID RetrieveHobData ( + IN OUT SMBUS_DXE_PRIVATE *Private +) +{ + AMI_SMBUS_HOB *Hob; + EFI_GUID HobListGuid = HOB_LIST_GUID; + EFI_STATUS Status; + SMBUS_PRIVATE *Context = &(Private->SmBusContext); + + PEI_EFI_SMBUS_DEVICE_MAP *PeiMap; + UINT32 i; + + Context->BoardReservedAddressCount = 0; + Context->BoardReservedAddressList = 0; + Context->ArpDeviceCount = 0; + + Hob = (AMI_SMBUS_HOB *)GetEfiConfigurationTable(pST, &HobListGuid); + + if(Hob == NULL) + return; + + Status = FindNextHobByGuid(&(Private->Identifier), &Hob); + if(EFI_ERROR(Status)) + return; + + Context->BoardReservedAddressCount = Hob->BoardReservedAddressCount; + Context->BoardReservedAddressList = (UINT8 *)(UINTN)Hob->BoardReservedAddressList; + Context->ArpDeviceCount = Hob->ArpDeviceCount; + + PeiMap = (PEI_EFI_SMBUS_DEVICE_MAP *)Hob->ArpDeviceList; + for(i = 0; i < Hob->ArpDeviceCount; i++) + { + Context->ArpDeviceList[i].SmbusDeviceAddress.SmbusDeviceAddress = PeiMap[i].Address; + Context->ArpDeviceList[i].SmbusDeviceUdid = PeiMap[i].Udid; + } +/* + MemCpy(Context->ArpDeviceList, + Hob->ArpDeviceList, + Context->ArpDeviceCount * sizeof(EFI_SMBUS_DEVICE_MAP)); +*/ +} + +//********************************************************************** +// Porting functions +//********************************************************************** + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmBusDxeWait +// +// Description: This function waits given number of microseconds +// +// Input: IN UINTN Microseconds - number of microseconds to wait +// +// Output: None +// +// Notes: Porting required +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID SmBusDxeWait( + IN UINTN Microseconds +) +{ +//Porting required - implement wait function for pei phase +} + +/* +VOID SmBusDxeInitialize( + IN SMBUS_PRIVATE *Context + ) +{ +//Porting required - initialize PCI device and fill SmBusBase + +} +*/ + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Chipset/SB/SmBus/SmBusDxe.dxs b/Chipset/SB/SmBus/SmBusDxe.dxs new file mode 100644 index 0000000..7de1921 --- /dev/null +++ b/Chipset/SB/SmBus/SmBusDxe.dxs @@ -0,0 +1,82 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusDxe.dxs 1 6/06/12 8:00a Victortu $ +// +// $Revision: 1 $ +// +// $Date: 6/06/12 8:00a $ +// +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusDxe.dxs $ +// +// 1 6/06/12 8:00a Victortu +// Implement EFI_PEI_SMBUS2_PPI Support. +// +// 4 6/17/11 5:55p Artems +// EIP 53378: Replaced tabs with spaces, formatted to follow coding +// standard +// +// 3 1/27/11 9:48p Abelwu +// Supports SMBUS Protocol in early DXE phase. (EIP#40778) +// +// 2 10/16/09 7:25p Artems +// Updated copyright header +// +// 1 1/09/09 6:53p Artems +// New implementation of SMBus EIP 16730 +// +// 4 7/24/07 12:33p Sivagarn +// Copyright year update +// +// +//********************************************************************** + +//<AMI_FHDR_START> +//---------------------------------------------------------------------------- +// +// Name: SmBusDxe.DXS +// +// Description: This file is the dependency file for the Smbus DXE +// driver +// +//---------------------------------------------------------------------------- +//<AMI_FHDR_END> + + +#include <Protocol\PciRootBridgeIo.h> + +DEPENDENCY_START + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID +DEPENDENCY_END + + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + diff --git a/Chipset/SB/SmBus/SmBusDxe.h b/Chipset/SB/SmBus/SmBusDxe.h new file mode 100644 index 0000000..955ea21 --- /dev/null +++ b/Chipset/SB/SmBus/SmBusDxe.h @@ -0,0 +1,219 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusDxe.h 1 6/06/12 8:00a Victortu $ +// +// $Revision: 1 $ +// +// $Date: 6/06/12 8:00a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusDxe.h $ +// +// 1 6/06/12 8:00a Victortu +// Implement EFI_PEI_SMBUS2_PPI Support. +// +// 9 8/03/11 8:18a Abelwu +// Updated AMI_SMBUS_SMM_PROTOCOL_GUID for following INTEL RC. +// +// 8 7/19/11 8:27a Abelwu +// [TAG] NONE +// [Category] New Feature +// [Description] Added SMBus SMM Protocol support. +// [Files] SmBusDxe.h +// +// 7 6/27/11 2:26p Artems +// Updated year in file header +// +// 6 6/17/11 5:52p Artems +// EIP 53378: Replaced tabs with spaces, formatted to follow coding +// standard +// +// 5 5/18/11 11:50a Artems +// +// 4 10/16/09 7:11p Artems +// Updated copyright header +// +// 3 3/03/09 4:36p Artems +// EIP 19949 Added support for multiple SM Bus controllers that +// represented by different PCI devices +// +// 2 1/28/09 6:52p Artems +// Modified in accordance with coding standard +// +// 1 1/09/09 6:53p Artems +// New implementation of SMBus EIP 16730 +// +// 1 3/18/07 5:23p Felixp +// +//********************************************************************** + +//<AMI_FHDR_START> +//---------------------------------------------------------------------- +// +// Name: SmBusDxe.h +// +// Description: This file contains DXE SMBUS Driver functions and data +// structures definition. +// +//---------------------------------------------------------------------- +//<AMI_FHDR_END> +#ifndef __SMBUS_DXE__H__ +#define __SMBUS_DXE__H__ +#ifdef __cplusplus +extern "C" { +#endif + +#include <AmiDxeLib.h> +#include <Protocol/Smbus.h> +#include <Protocol/DriverBinding.h> +#include <Protocol/PciIo.h> +#include <Protocol/PciRootBridgeIo.h> +#include "SmBusCommon.h" + +#define AMI_SMBUS_SMM_PROTOCOL_GUID \ + {0x72e40094, 0x2ee1, 0x497a, 0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0xc} + +#define MAX_DXE_ARP_DEVICES 0x30 + +#pragma pack(1) + +//<AMI_THDR_START> +//---------------------------------------------------------------------------- +// Name: SMBUS_DXE_PRIVATE +// +// Description: AMI SMBUS driver PEI private data structure +// +// Fields: Name Type Description +//---------------------------------------------------------------------------- +// SmBusProtocol EFI_SMBUS_HC_PROTOCOL SMBUS host controller protocol structure +// Identifier EFI_GUID SMBUS host controller identifier +// SmBusContext SMBUS_PRIVATE SMBUS private data structure +// PciIo EFI_PCI_IO_PROTOCOL* Pointer to PCI IO protocol of SMBUS device +// NotifyList DLIST Linked list of notify callbacks +// NotifyEvent EFI_EVENT EFI_EVENT structure +// +//---------------------------------------------------------------------------- +//<AMI_THDR_END> +typedef struct _SMBUS_DXE_PRIVATE +{ + EFI_SMBUS_HC_PROTOCOL SmBusProtocol; + EFI_GUID Identifier; + SMBUS_PRIVATE SmBusContext; + EFI_PCI_IO_PROTOCOL *PciIo; + DLIST NotifyList; + EFI_EVENT NotifyEvent; +} SMBUS_DXE_PRIVATE; + +#pragma pack() + +typedef struct { + DLINK Link; + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + UINTN Data; + EFI_SMBUS_NOTIFY_FUNCTION NotifyFunction; +} SMBUS_NOTIFY_LINK; + +EFI_STATUS SmBusDxeExecute ( + IN EFI_SMBUS_HC_PROTOCOL *This, + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN EFI_SMBUS_DEVICE_COMMAND Command, + IN EFI_SMBUS_OPERATION Operation, + IN BOOLEAN PecCheck, + IN OUT UINTN *Length, + IN OUT VOID *Buffer +); + +EFI_STATUS SmBusDxeArpDevice ( + IN EFI_SMBUS_HC_PROTOCOL *This, + IN BOOLEAN ArpAll, + IN EFI_SMBUS_UDID *SmbusUdid, OPTIONAL + IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress OPTIONAL +); + +EFI_STATUS SmBusDxeGetArpMap ( + IN EFI_SMBUS_HC_PROTOCOL *This, + IN OUT UINTN *Length, + IN OUT EFI_SMBUS_DEVICE_MAP **SmbusDeviceMap +); + +EFI_STATUS SmBusDxeNotify ( + IN EFI_SMBUS_HC_PROTOCOL *This, + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN UINTN Data, + IN EFI_SMBUS_NOTIFY_FUNCTION NotifyFunction +); + +EFI_STATUS DriverBindingSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath +); + +EFI_STATUS DriverBindingStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath +); + +EFI_STATUS DriverBindingStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer +); + +EFI_STATUS InitializeNotifyPolling ( + IN SMBUS_DXE_PRIVATE *Context +); + +VOID PollSmbusNotify ( + IN EFI_EVENT Event, + IN VOID *Context +); + +VOID RetrieveHobData ( + IN OUT SMBUS_DXE_PRIVATE *Context +); + +VOID SmBusDxeWait( + IN UINTN Microseconds + ); + +/* +VOID SmBusDxeInitialize( + IN SMBUS_PRIVATE *Context + ); +*/ + +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Chipset/SB/SmBus/SmBusPciHooks.c b/Chipset/SB/SmBus/SmBusPciHooks.c new file mode 100644 index 0000000..7362140 --- /dev/null +++ b/Chipset/SB/SmBus/SmBusPciHooks.c @@ -0,0 +1,129 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusPciHooks.c 1 6/06/12 8:00a Victortu $ +// +// $Revision: 1 $ +// +// $Date: 6/06/12 8:00a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusPciHooks.c $ +// +// 1 6/06/12 8:00a Victortu +// Implement EFI_PEI_SMBUS2_PPI Support. +// +// 2 1/27/11 9:44p Abelwu +// Supports SMBUS Protocol in early DXE phase. (EIP#40778) +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SmbusPciHooks.c +// +// Description: This file contains PCI initialized hooks for SMBus porting. +// +// Notes: Porting required if SMBus early DXE supported +// +//<AMI_FHDR_END> +//************************************************************************* + +//--------------------------------------------------------------------------- +// Include(s) +//--------------------------------------------------------------------------- + +#include <Efi.h> +#include <Token.h> +#include <AmiDxeLib.h> +#include <AmiCspLib.h> +#include <PciBus.h> + +//--------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//--------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//--------------------------------------------------------------------------- +// Variable and External Declaration(s) +//--------------------------------------------------------------------------- +// Variable Declaration(s) + +// Local variable + +// GUID Definition(s) + +// Protocol Definition(s) + +// External Declaration(s) + +// Function Definition(s) + +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmBusProtectedPciDevice +// +// Description: This function is called by PCI Bus Driver before configuring +// or disabling any PCI device. This function should examine the +// Vendor/Device ID or PCI Bus, Device and Function numbers to +// make sure it is not a south bridge device or any other device +// which should no be configured by PCI Bus Driver. +// +// Input: *PciDevice - Pointer to PCI Device Info structure. +// +// Output: EFI_STATUS +// EFI_SUCCESS - SKIP this device, do not touch +// PCI Command register. +// EFI_UNSUPPORTED - DON'T SKIP this device do complete +// enumeration as usual. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmBusProtectedPciDevice ( + IN PCI_DEV_INFO *PciDevice ) +{ +/* +if ((PciDevice->Address.Addr.Bus == SMBUS_BUS) && \ + (PciDevice->Address.Addr.Device == SMBUS_DEV) && \ + (PciDevice->Address.Addr.Function == SMBUS_FUN)) { + + return EFI_SUCCESS; +} +*/ + return EFI_UNSUPPORTED; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/SmBus/SmBusPei.c b/Chipset/SB/SmBus/SmBusPei.c new file mode 100644 index 0000000..f9c5665 --- /dev/null +++ b/Chipset/SB/SmBus/SmBusPei.c @@ -0,0 +1,527 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusPei.c 3 3/27/13 10:29p Wesleychen $ +// +// $Revision: 3 $ +// +// $Date: 3/27/13 10:29p $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusPei.c $ +// +// 3 3/27/13 10:29p Wesleychen +// Fix coding error. +// +// 2 11/25/12 10:40p Scottyang +// [TAG] EIP107376 +// [Category] Improvement +// [Description] Add token "PCH_SPD_WRITE_DISABLE" for SMBus reg 40h bit +// 4. +// [Files] SmBus.sdl +// SmBusPei.c +// +// 1 6/06/12 8:00a Victortu +// Implement EFI_PEI_SMBUS2_PPI Support. +// +// 10 7/21/11 7:31a Abelwu +// [TAG] EIP63768 +// [Category] Improvement +// [Description] Supported Core 4.6.5.x PI 1.2 / uEFI 2.3.1 compliance +// [Files] SmBusPei.c +// +// 9 7/19/11 8:03a Abelwu +// [TAG] EIP63768 +// [Category] Improvement +// [Description] Supported Core 4.6.5.x PI 1.2 / uEFI 2.3.1 compliance +// [Files] SmBusPei.c +// +// 8 6/27/11 2:26p Artems +// Updated year in file header +// +// 7 6/17/11 5:53p Artems +// EIP 53378: Replaced tabs with spaces, formatted to follow coding +// standard +// +// 6 10/13/10 4:15p Artems +// EIP 45184 - fixed pointer size to be same in IA32 and X64 mode +// +// 5 10/19/09 12:48p Artems +// Updated copyright header +// +// 4 3/03/09 4:36p Artems +// EIP 19949 Added support for multiple SM Bus controllers that +// represented by different PCI devices +// +// 3 1/29/09 4:20p Artems +// Change "Note" to "Notes" for HelpBuilder +// +// 2 1/28/09 6:51p Artems +// Modified in accordance with coding standard +// +// 1 1/09/09 6:53p Artems +// New implementation of SMBus EIP 16730 +// +// 1 3/18/07 5:23p Felixp +// +//********************************************************************** + +//<AMI_FHDR_START> +//---------------------------------------------------------------------- +// +// Name: SmBusPei.c +// +// Description: SMBUS driver PEI functions implementation +// +//---------------------------------------------------------------------- +//<AMI_FHDR_END> + +#include <AmiLib.h> +#include <AmiHobs.h> +#include "SmBusPei.h" + // [EIP82310]> +#include <Ppi\SmbusPolicy\SmbusPolicy.h> +#include <PchAccess.h> + +static EFI_GUID gEfiPeiEndOfPeiPhasePpiGuid = EFI_PEI_END_OF_PEI_PHASE_PPI_GUID; +EFI_GUID mPeiSmbusPolicyPpiGuid = PEI_SMBUS_POLICY_PPI_GUID; + +extern EFI_GUID SmBusIdentifierGuid; +extern UINT8 SmBusPlatformReservedAddress[]; +extern UINT8 SmBusPlatformReservedAddressSize; + // <[EIP82310] + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmBusPeiEntryPoint +// +// Description: SMBUS driver PEI entry point +// +// Input: EFI_FFS_FILE_HEADER *FfsHeader - pointer to file header +// EFI_PEI_SERVICES **PeiServices - pointer to PEI services table +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS SmBusPeiEntryPoint ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices +) +{ + EFI_STATUS Status; + SMBUS_PEI_PRIVATE *Private; + + Status = (*PeiServices)->AllocatePool( + PeiServices, + sizeof(SMBUS_PEI_PRIVATE), + &Private); + if(EFI_ERROR(Status)) + return Status; + + Status = (*PeiServices)->AllocatePool( + PeiServices, + sizeof(EFI_SMBUS_DEVICE_MAP) * MAX_PEI_ARP_DEVICES, + &(Private->SmBusContext.ArpDeviceList)); + if(EFI_ERROR(Status)) + return Status; + + Private->SmBusPpi.Execute = SmBusPeiExecute; + Private->SmBusPpi.ArpDevice = SmBusPeiArpDevice; + Private->SmBusPpi.GetArpMap = SmBusPeiGetArpMap; + Private->SmBusPpi.Notify = SmBusPeiNotify; + + Private->SmBusPpiDesc.Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + Private->SmBusPpiDesc.Guid = &gEfiPeiSmbus2PpiGuid; + Private->SmBusPpiDesc.Ppi = &Private->SmBusPpi; + + Private->NotifyDesc.Flags = EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + Private->NotifyDesc.Guid = &gEfiPeiEndOfPeiPhasePpiGuid; + Private->NotifyDesc.Notify = SmBusEndOfPeiCallback; + + Private->SmBusContext.ArpDeviceCount = 0; + Private->SmBusContext.MaxDevices = MAX_PEI_ARP_DEVICES; + Private->SmBusContext.SmBusWait = SmBusPeiWait; + + Private->SmBusPpi.Identifier = SmBusIdentifierGuid; + + SmBusPeiInitialize(PeiServices, &Private->SmBusContext); + + Status = (*PeiServices)->NotifyPpi(PeiServices, &Private->NotifyDesc); + if(EFI_ERROR(Status)) + return Status; + + return (*PeiServices)->InstallPpi(PeiServices, &Private->SmBusPpiDesc); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmBusPeiExecute +// +// Description: SMBUS driver PPI Execute function +// +// Input: PI 0.91 +// **PeiServices - Pointer to the PEI services table +// *This - Pointer to the SMBus PPI structure +// +// PI 1.X +// *This - Pointer to the SMBus2 PPI structure +// +// SlaveAddress - Address of the SMBus device to be used to +// send this command +// Command - Command to be sent to the device +// Operation - SMBus operation to be performed +// PecCheck - Flag indicating the usage of PEC +// *Length - Length of the data in the Buffer (IN/OUT) +// *Buffer - Pointer to the buffer with the data (IN/OUT) +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS SmBusPeiExecute ( + IN CONST EFI_PEI_SMBUS2_PPI *This, + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN EFI_SMBUS_DEVICE_COMMAND Command, + IN EFI_SMBUS_OPERATION Operation, + IN BOOLEAN PecCheck, + IN OUT UINTN *Length, + IN OUT VOID *Buffer +) +{ + SMBUS_PEI_PRIVATE *Private = (SMBUS_PEI_PRIVATE *)This; + + return Execute( + &(Private->SmBusContext), + SlaveAddress, + Command, + Operation, + PecCheck, + Length, + Buffer); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmBusPeiArpDevice +// +// Description: SMBUS driver PPI ArpDevice function +// +// Input: PI 0.91 +// **PeiServices - Pointer to the PEI services table +// *This - Pointer to the SMBus PPI structure +// +// PI 1.X +// *This - Pointer to the SMBus2 PPI structure +// +// ArpAll - Flag indicating ARP type - ALL or specific +// *SmbusUdid - SMBus UDID for the device whose Address has +// to be resolved +// *SlaveAddress - Slave address to be assigned to the device +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS SmBusPeiArpDevice ( + IN CONST EFI_PEI_SMBUS2_PPI *This, + IN BOOLEAN ArpAll, + IN EFI_SMBUS_UDID *SmbusUdid, OPTIONAL + IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress OPTIONAL +) +{ + SMBUS_PEI_PRIVATE *Private = (SMBUS_PEI_PRIVATE *)This; + + return ArpDevice( + &(Private->SmBusContext), + ArpAll, + SmbusUdid, + SlaveAddress); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmBusPeiGetArpMap +// +// Description: SMBUS driver PPI GetArpMap function +// +// Input: PI 0.91 +// **PeiServices - Pointer to the PEI services table +// *This - Pointer to the SMBus PPI structure +// +// PI 1.X +// *This - Pointer to the SMBus2 PPI structure +// +// *Length - Length of the Device map structure(IN & OUT) +// *SmBusDeviceMap - Pointer to the buffer where the SMBus +// device map will be filled in +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS SmBusPeiGetArpMap ( + IN CONST EFI_PEI_SMBUS2_PPI *This, + IN OUT UINTN *Length, + IN OUT EFI_SMBUS_DEVICE_MAP **SmbusDeviceMap +) +{ + SMBUS_PEI_PRIVATE *Private = (SMBUS_PEI_PRIVATE *)This; + + return GetArpMap( + &(Private->SmBusContext), + Length, + SmbusDeviceMap); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmBusPeiNotify +// +// Description: SMBUS driver PPI Notify function +// +// Input: EFI_PEI_SERVICES **PeiServices - pointer to PEI services table +// EFI_PEI_SMBUS_PPI *This - pointer to PPI +// EFI_SMBUS_DEVICE_ADDRESS SlaveAddress - address of notification device +// UINTN Data - notification data +// EFI_PEI_SMBUS_NOTIFY_FUNCTION NotifyFunction - pointer to callback function +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS SmBusPeiNotify ( + IN CONST EFI_PEI_SMBUS2_PPI *This, + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN UINTN Data, + IN EFI_PEI_SMBUS_NOTIFY2_FUNCTION NotifyFunction +) +{ + return EFI_UNSUPPORTED; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmBusEndOfPeiCallback +// +// Description: This function creates map of devices connected to SMBUS at the end of PEI phase +// +// Input: EFI_PEI_SERVICES **PeiServices - pointer to PEI services table +// EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor - pointer to notify descriptor +// VOID *Ppi - pointer to notify PPI +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS SmBusEndOfPeiCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi +) +{ + SMBUS_PEI_PRIVATE *Private = OUTTER(NotifyDescriptor, NotifyDesc, SMBUS_PEI_PRIVATE); + UINTN HobSize; + AMI_SMBUS_HOB *Hob; + EFI_STATUS Status; + + HobSize = sizeof(AMI_SMBUS_HOB) + Private->SmBusContext.ArpDeviceCount * sizeof(EFI_SMBUS_DEVICE_MAP); + Status = (*PeiServices)->CreateHob(PeiServices, EFI_HOB_TYPE_GUID_EXTENSION, HobSize, &Hob); + if(!EFI_ERROR(Status)) + { + Hob->Header.Name = Private->SmBusPpi.Identifier; + Hob->BoardReservedAddressCount = Private->SmBusContext.BoardReservedAddressCount; + Hob->BoardReservedAddressList = (UINT32) (Private->SmBusContext.BoardReservedAddressList); + Hob->ArpDeviceCount = Private->SmBusContext.ArpDeviceCount; + MemCpy(Hob->ArpDeviceList, + Private->SmBusContext.ArpDeviceList, + Private->SmBusContext.ArpDeviceCount * sizeof(EFI_SMBUS_DEVICE_MAP)); + } + return Status; +} + +//********************************************************************** +// Porting functions +//********************************************************************** + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmBusPeiWait +// +// Description: This function waits given number of microseconds +// +// Input: UINTN Microseconds - number of microseconds to wait +// +// Output: None +// +// Notes: Porting required +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID SmBusPeiWait( + IN UINTN Microseconds +) +{ + // The following code is to generate delay for specified amount of micro + // seconds using ACPI timer. + UINT16 AcpiTmrReg = PM_BASE_ADDRESS + ACPI_IOREG_PM1_TMR; + UINTN TicksNeeded; + UINT32 TimerValue; + UINT32 NewTimerValue; + UINTN OverFlow = 0; + UINTN TheRest; + UINTN EndValue; + + // There are 3.58 ticks per us, so we have to convert the number of us + // passed in to the number of ticks that need to pass before the timer has + // expired convert us to Ticks, don't loose significant figures or as few + // as possible do integer math in ticks/tens of ns and then divide by 100 + // to get ticks per us + + TicksNeeded = Microseconds * 3; // (Microseconds * 3) + TicksNeeded += (Microseconds) / 2; // (Microseconds * 5)/10 + TicksNeeded += (Microseconds * 2) / 25; // (Microseconds * 8)/100 + TheRest = TicksNeeded; + + // 32 bits corresponds to approz 71 mins no delay should be that long + // otherwise get the number of times the counter will have to overflow + // to delay as long as needed + if (NUM_BITS_IN_ACPI_TIMER < MAX_ACPI_TIMER_BITS) { + OverFlow = TicksNeeded / (1 << NUM_BITS_IN_ACPI_TIMER); + TheRest = TicksNeeded % (1 << NUM_BITS_IN_ACPI_TIMER); + } + + // Read ACPI Timer + TimerValue = IoRead32( AcpiTmrReg ); + + // Need to adjust the values based off of the start time + EndValue = TheRest + TimerValue; + + // Check for overflow on addition. possibly a problem + if (EndValue < TimerValue) { + OverFlow++; + } else { + if (NUM_BITS_IN_ACPI_TIMER < MAX_ACPI_TIMER_BITS) { + // Here make sure that EndValue is less than the max value + // of the counter + OverFlow += EndValue / (1 << NUM_BITS_IN_ACPI_TIMER); + EndValue = EndValue % (1 << NUM_BITS_IN_ACPI_TIMER); + } + } + + // Let the timer wrap around as many times as calculated + while (OverFlow) { + // read timer amd look to see if the new value read is less than + // the current timer value. if this happens the timer overflowed + NewTimerValue = IoRead32( AcpiTmrReg ); + + if (NewTimerValue < TimerValue) OverFlow--; + + TimerValue = NewTimerValue; + } + + // Now wait for the correct number of ticks that need to occur after + // all the needed overflows + while (EndValue > TimerValue) { + NewTimerValue = IoRead32( AcpiTmrReg ); + + // check to see if the timer overflowed. if it did then + // the time has elapsed. Because EndValue should be greater than + // TimerValue + if (NewTimerValue < TimerValue) break; + + TimerValue = NewTimerValue; + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmBusPeiInitialize +// +// Description: This function initializes SMBUS PCI device and fills device context +// +// Input: **PeiServices - Pointer to the PEI Services table +// *Context - Pointer to the SMBus private structure. +// +// Output: None +// +// Notes: Porting required +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID SmBusPeiInitialize( + IN EFI_PEI_SERVICES **PeiServices, + IN OUT SMBUS_PRIVATE *Context ) +{ + // [EIP82310]> + EFI_STATUS Status; + PEI_SMBUS_POLICY_PPI *SmbusPolicy; + UINTN SmbusRegBase; + + Context->BoardReservedAddressCount = SmBusPlatformReservedAddressSize; + Context->BoardReservedAddressList = SmBusPlatformReservedAddress; + + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &mPeiSmbusPolicyPpiGuid, + 0, + NULL, + &SmbusPolicy + ); + if (EFI_ERROR(Status)) return; + + SmbusRegBase = SB_PCIE_CFG_ADDRESS (SMBUS_BUS, SMBUS_DEV, SMBUS_FUN, 0); + + if (MEM_READ16(SmbusRegBase + R_PCH_SMBUS_VENDOR_ID) != 0xFFFF) { + Context->SmBusBase = MEM_READ16(SmbusRegBase + R_PCH_SMBUS_BASE) & (UINT16) B_PCH_SMBUS_BASE_BAR; + if (Context->SmBusBase == SmbusPolicy->BaseAddress) { + return; + } else if (Context->SmBusBase == 0) { + Context->SmBusBase = SmbusPolicy->BaseAddress; + + // Set the BAR & I/O space enable ourselves + MEM_WRITE16(SmbusRegBase + SMBUS_REG_BASE_ADDR, Context->SmBusBase); + MEM_SET8(SmbusRegBase + R_PCH_SMBUS_PCICMD, B_PCH_SMBUS_PCICMD_IOSE); + + // Reset the SMBus host controller + MEM_SET8(SmbusRegBase + R_PCH_SMBUS_HOSTC, (PCH_SPD_WRITE_DISABLE << 4) | B_PCH_SMBUS_HOSTC_SSRESET); + + // Enable the SMBus host controller + MEM_RW8(SmbusRegBase + R_PCH_SMBUS_HOSTC, \ + B_PCH_SMBUS_HOSTC_HST_EN, \ + B_PCH_SMBUS_HOSTC_SMI_EN | B_PCH_SMBUS_HOSTC_I2C_EN); + + // Clear Status Register before anyone uses the interfaces + IoWrite8 (Context->SmBusBase + R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL); + } + } + // <[EIP82310] +} + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + diff --git a/Chipset/SB/SmBus/SmBusPei.dxs b/Chipset/SB/SmBus/SmBusPei.dxs new file mode 100644 index 0000000..79abc58 --- /dev/null +++ b/Chipset/SB/SmBus/SmBusPei.dxs @@ -0,0 +1,73 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusPei.dxs 1 6/06/12 8:00a Victortu $ +// +// $Revision: 1 $ +// +// $Date: 6/06/12 8:00a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusPei.dxs $ +// +// 1 6/06/12 8:00a Victortu +// Implement EFI_PEI_SMBUS2_PPI Support. +// +// 3 6/27/11 2:26p Artems +// Updated year in file header +// +// 2 10/16/09 7:25p Artems +// Updated copyright header +// +// 1 1/09/09 6:53p Artems +// New implementation of SMBus EIP 16730 +// +// 1 7/30/07 6:19p Sivagarn +// Initial check-in for the template +// +//********************************************************************** + +//<AMI_FHDR_START> +//--------------------------------------------------------------------------- +// +// Name: SmBusPei.DXS +// +// Description: Dependency file for the Smbus PEI driver +// +//--------------------------------------------------------------------------- +//<AMI_FHDR_END> + + // [EIP82310]> +#include <Ppi\SmbusPolicy\SmbusPolicy.h> + +DEPENDENCY_START + PEI_SMBUS_POLICY_PPI_GUID +DEPENDENCY_END + // <[EIP82310] + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Chipset/SB/SmBus/SmBusPei.h b/Chipset/SB/SmBus/SmBusPei.h new file mode 100644 index 0000000..6857196 --- /dev/null +++ b/Chipset/SB/SmBus/SmBusPei.h @@ -0,0 +1,182 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusPei.h 1 6/06/12 8:00a Victortu $ +// +// $Revision: 1 $ +// +// $Date: 6/06/12 8:00a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusPei.h $ +// +// 1 6/06/12 8:00a Victortu +// Implement EFI_PEI_SMBUS2_PPI Support. +// +// 8 7/21/11 7:31a Abelwu +// [TAG] EIP63768 +// [Category] Improvement +// [Description] Supported Core 4.6.5.x PI 1.2 / uEFI 2.3.1 compliance +// [Files] SmBusPei.h +// +// 7 7/19/11 8:02a Abelwu +// [TAG] EIP63768 +// [Category] Improvement +// [Description] Supported Core 4.6.5.x PI 1.2 / uEFI 2.3.1 compliance +// [Files] SmBusPei.h +// +// 6 6/27/11 2:26p Artems +// Updated year in file header +// +// 5 6/17/11 5:52p Artems +// EIP 53378: Replaced tabs with spaces, formatted to follow coding +// standard +// +// 4 10/16/09 7:10p Artems +// Updated copyright header +// +// 3 3/03/09 4:36p Artems +// EIP 19949 Added support for multiple SM Bus controllers that +// represented by different PCI devices +// +// 2 1/28/09 6:52p Artems +// Modified in accordance with coding standard +// +// 1 1/09/09 6:53p Artems +// New implementation of SMBus EIP 16730 +// +// 1 3/18/07 5:23p Felixp +// +//********************************************************************** + +//<AMI_FHDR_START> +//---------------------------------------------------------------------- +// +// Name: SmBusPei.h +// +// Description: This file contains PEI SMBUS Driver functions and data structures definition +// +//---------------------------------------------------------------------- +//<AMI_FHDR_END> + +#ifndef __SMBUS_PEI__H__ +#define __SMBUS_PEI__H__ +#ifdef __cplusplus +extern "C" { +#endif + +#include <Ppi/Smbus2.h> + +#include "SmBusCommon.h" + +#define MAX_PEI_ARP_DEVICES 8 + +#pragma pack(1) + +//<AMI_THDR_START> +//---------------------------------------------------------------------------- +// Name: SMBUS_PEI_PRIVATE +// +// Description: AMI SMBUS driver PEI private data structure +// +// Fields: Name Type Description +//---------------------------------------------------------------------------- +// SmBusPpi EFI_PEI_SMBUS/2_PPI SMBUS (2) PPI structure +// Identifier EFI_GUID SMBUS controller identifier +// SmBusContext SMBUS_PRIVATE SMBUS private data structure +// NotifyDesc EFI_PEI_NOTIFY_DESCRIPTOR Notify descriptor structure +// SmBusPpiDesc EFI_PEI_PPI_DESCRIPTOR PPI descriptor structure +// +//---------------------------------------------------------------------------- +//<AMI_THDR_END> +typedef struct _SMBUS_PEI_PRIVATE +{ + EFI_PEI_SMBUS2_PPI SmBusPpi; + SMBUS_PRIVATE SmBusContext; + EFI_PEI_NOTIFY_DESCRIPTOR NotifyDesc; + EFI_PEI_PPI_DESCRIPTOR SmBusPpiDesc; +} SMBUS_PEI_PRIVATE; + +#pragma pack() + +EFI_STATUS SmBusPeiEntryPoint ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices +); + +EFI_STATUS SmBusPeiExecute ( + IN CONST EFI_PEI_SMBUS2_PPI *This, + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN EFI_SMBUS_DEVICE_COMMAND Command, + IN EFI_SMBUS_OPERATION Operation, + IN BOOLEAN PecCheck, + IN OUT UINTN *Length, + IN OUT VOID *Buffer +); + +EFI_STATUS SmBusPeiArpDevice ( + IN CONST EFI_PEI_SMBUS2_PPI *This, + IN BOOLEAN ArpAll, + IN EFI_SMBUS_UDID *SmbusUdid, OPTIONAL + IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress OPTIONAL +); + +EFI_STATUS SmBusPeiGetArpMap ( + IN CONST EFI_PEI_SMBUS2_PPI *This, + IN OUT UINTN *Length, + IN OUT EFI_SMBUS_DEVICE_MAP **SmbusDeviceMap +); + +EFI_STATUS SmBusPeiNotify ( + IN CONST EFI_PEI_SMBUS2_PPI *This, + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN UINTN Data, + IN EFI_PEI_SMBUS_NOTIFY2_FUNCTION NotifyFunction +); + +EFI_STATUS SmBusEndOfPeiCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi +); + +VOID SmBusPeiWait( + IN UINTN Microseconds +); + +VOID SmBusPeiInitialize( + IN EFI_PEI_SERVICES **PeiServices, + IN SMBUS_PRIVATE *Context +); + +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Chipset/SB/SmBus/SmBusPorting.c b/Chipset/SB/SmBus/SmBusPorting.c new file mode 100644 index 0000000..eb4ad69 --- /dev/null +++ b/Chipset/SB/SmBus/SmBusPorting.c @@ -0,0 +1,705 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusPorting.c 1 6/06/12 8:00a Victortu $ +// +// $Revision: 1 $ +// +// $Date: 6/06/12 8:00a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusPorting.c $ +// +// 1 6/06/12 8:00a Victortu +// Implement EFI_PEI_SMBUS2_PPI Support. +// +// 7 6/27/11 2:26p Artems +// Updated year in file header +// +// 6 6/17/11 5:53p Artems +// EIP 53378: Replaced tabs with spaces, formatted to follow coding +// standard +// +// 5 10/16/09 7:24p Artems +// Updated copyright header +// +// 4 3/03/09 4:36p Artems +// EIP 19949 Added support for multiple SM Bus controllers that +// represented by different PCI devices +// +// 3 1/29/09 4:20p Artems +// Change "Note" to "Notes" for HelpBuilder +// +// 2 1/28/09 6:52p Artems +// Modified in accordance with coding standard +// +// 1 1/09/09 6:53p Artems +// New implementation of SMBus EIP 16730 +// +// 1 3/18/07 5:23p Felixp +// +//********************************************************************** + +//<AMI_FHDR_START> +//---------------------------------------------------------------------- +// +// Name: SmBusPorting.c +// +// Description: SMBUS driver porting functions +// +//---------------------------------------------------------------------- +//<AMI_FHDR_END> + +#include "SmBusCommon.h" + +//Porting Required - Put unique GUID for given SMBUS controller +#define SM_BUS_CONTROLLER_IDENTIFIER_GUID \ + {0x882f2546, 0xef1f, 0x4090, 0x9f, 0x9c, 0x93, 0x84, 0x5a, 0xd7, 0x84, 0x1c} + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//--------------------------------------------------------------------------- +// Variable and External Declaration(s) +//--------------------------------------------------------------------------- +// Variable Declaration(s) + + // [EIP82310]> +UINT8 SmBusPlatformReservedAddress[] = { + DIMM1_SMBUS_ADDRESS, + DIMM2_SMBUS_ADDRESS, + DIMM3_SMBUS_ADDRESS, + DIMM4_SMBUS_ADDRESS +}; + // <[EIP82310] + +UINT8 SmBusPlatformReservedAddressSize = \ + sizeof(SmBusPlatformReservedAddress) / sizeof(UINT8); + +// GUID Definition(s) + +EFI_GUID SmBusIdentifierGuid = SM_BUS_CONTROLLER_IDENTIFIER_GUID; + +// Protocol/PPI Definition(s) + +// External Declaration(s) + +// Function Definition(s) + +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: BeforeSMBusTransfer +// +// Description: Set an enviornment for SMBus transfering. +// +// Input: SmBusIoAddr16 - I/O base address of the SMBus Controller +// Protocol8 - SMBus operation to be performed +// +// Output: EFI_STATUS +// EFI_TIMEOUT - The caller can't obtain ownership of SMBus. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS BeforeSMBusTransfer ( + IN UINT16 SmBusIoAddr16, + IN UINT8 Protocol8 ) +{ + UINT16 Timeout = 0xffff; + + // Waiting for other software's usage. + while (IoRead8(SmBusIoAddr16 + SMB_IOREG_HST_STS) & HST_STS_INUSE_STS) { + IoRead8(0xed); // I/O Delay + Timeout--; + if (Timeout == 0) return EFI_TIMEOUT; + } + + // BIOS obtains ownership of SMBus & Waiting for transmission completed. + while (IoRead8(SmBusIoAddr16 + SMB_IOREG_HST_STS) & HST_STS_HOST_BUSY) { + Timeout--; + if (Timeout == 0) break; + } + + // Clears all statues + IoWrite8(SmBusIoAddr16 + SMB_IOREG_HST_STS, HST_STS_ALL); + + if (Protocol8 == SMB_CMD_BLOCK) { +//#### SET_IO8(SmBusIoAddr16 + SMB_IOREG_AUX_CTL, AUX_CTL_E32B); // 0x0D +//#### // Reset Buffer Pointer +//#### IoRead8(SmBusIoAddr16 + SMB_IOREG_HST_CNT); // 0x02 + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteCommand +// +// Description: This support function writes command field to SMBus Controller +// +// Input: SmBusIoAddr16 - I/O base address of the SMBus Controller +// Command8 - SMBus command to be performed +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteCommand ( + IN UINT16 SmBusIoAddr16, + IN UINT8 Command8 ) +{ + IoWrite8(SmBusIoAddr16 + SMB_IOREG_HST_CMD, Command8); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteSlAddr +// +// Description: This support function writes slave address to SMBus Controller +// +// Input: SmBusIoAddr16 - I/O base address of the SMBus Controller +// SlAddr8 - Address of the SMBus device +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteSlAddr ( + IN UINT16 SmBusIoAddr16, + IN UINT8 SlAddr8 ) +{ + IoWrite8(SmBusIoAddr16 + SMB_IOREG_XMIT_SLVA, SlAddr8); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteSMBusData +// +// Description: This support function writes data(s) to SMBus Controller for +// SMBus write operation. +// +// Input: SmBusIoAddr16 - I/O base address of the SMBus Controller +// Protocol8 - SMBus operation to be performed +// Length8 - Size of data buffer in bytes +// *Data8 - Buffer to be written +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteSMBusData ( + IN UINT16 SmBusIoAddr16, + IN UINT8 Protocol8, + IN UINT8 Length8, + IN UINT8 *Data8 ) +{ + UINT8 i; + + for (i = 0; i < Length8; i++) { + if (Protocol8 == SMB_CMD_BLOCK) { + IoWrite8(SmBusIoAddr16 + SMB_IOREG_HST_D0, Length8); + IoWrite8(SmBusIoAddr16 + SMB_IOREG_HOST_BLOCK_DB, *Data8++); + break; + } else { + IoWrite8(SmBusIoAddr16 + SMB_IOREG_HST_D0 + i, *Data8++); + } + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WaitForHostByteDoneStatus +// +// Description: This support function waits the Byte Done bit to be set for +// SMBus Block operation. +// +// Input: SmBusStsReg - 16 Bit I/O address for SMBus status register +// +// Output: EFI_STATUS +// EFI_DEVICE_ERROR - An error on the SMBus device. +// EFI_SUCCESS - The Byte Done bit had been set. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS WaitForHostByteDoneStatus ( + IN UINT16 SmBusStsReg ) +{ + UINT8 HostSts; + + while (1) { + HostSts = IoRead8( SmBusStsReg ); + IoWrite8( IO_DELAY_PORT, HostSts ); + if ( HostSts & HST_STS_ERROR ) return EFI_DEVICE_ERROR; + if ( HostSts & HST_STS_BDS ) return EFI_SUCCESS; + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteSmBusBlockData +// +// Description: This support function writes to SMBus Controller +// +// Input: SmBusIoAddr16 - I/O base address of the SMBus Controller +// Length8 - Size of data buffer in bytes +// *Data8 - Buffer to be written +// +// Output: EFI_STATUS +// EFI_DEVICE_ERROR - An error on the SMBus device. +// EFI_SUCCESS - Write SMBus Block data successfully. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS WriteSmBusBlockData ( + IN UINT16 SmBusIoAddr16, + IN UINT8 Length8, + IN UINT8 *Data8 ) +{ + EFI_STATUS Status; + UINT8 i; + UINT16 StatusReg = SmBusIoAddr16 + SMB_IOREG_HST_STS; + + for (i = 1; i < Length8; i++) { + if (WaitForHostByteDoneStatus(StatusReg)) return EFI_DEVICE_ERROR; + IoWrite8(SmBusIoAddr16 + SMB_IOREG_HOST_BLOCK_DB, *Data8++); + IoWrite8(StatusReg, HST_STS_BDS); + } + Status = WaitForHostByteDoneStatus(StatusReg); + IoWrite8(StatusReg, HST_STS_BDS); + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ReadSmBusData +// +// Description: This support function reads from SMBus Controller +// +// Input: SmBusIoAddr16 - I/O base address of the SMBus Controller +// Protocol8 - SMBus operation to be performed +// Length8 - Size of data buffer in bytes +// *Data8 - Buffer for the read data +// +// Output: EFI_STATUS +// EFI_DEVICE_ERROR - An error on the SMBus device. +// EFI_SUCCESS - Read SMBus data successfully. +// +// Modified: *Data8 - The Pointer will store data(s) read from the SMBus +// device if EFI_SUCCESS is returned. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS ReadSmBusData ( + IN UINT16 SmBusIoAddr16, + IN UINT8 Protocol8, + IN UINT8 Length8, + OUT UINT8 *Data8 ) +{ + UINT8 i; + + if (Protocol8 == SMB_CMD_BLOCK) + Length8 = IoRead8(SmBusIoAddr16 + SMB_IOREG_HST_D0); + + for (i = 0; i < Length8; i++) { + if (Protocol8 == SMB_CMD_BLOCK) { + if (WaitForHostByteDoneStatus(SmBusIoAddr16 + SMB_IOREG_HST_STS)) + return EFI_DEVICE_ERROR; + *Data8++ = IoRead8(SmBusIoAddr16 + SMB_IOREG_HOST_BLOCK_DB); + if (i == (Length8 - 1)) { + IoWrite8(SmBusIoAddr16 + SMB_IOREG_HST_CNT, \ + HST_CNT_LAST_BYTE | SMB_CMD_BLOCK); + } + IoWrite8(SmBusIoAddr16 + SMB_IOREG_HST_STS, HST_STS_BDS); + } else { + *Data8++ = IoRead8(SmBusIoAddr16 + SMB_IOREG_HST_D0 + i); + } + } + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: StartSmBusTransition +// +// Description: This support function starts SMBus operation. +// +// Input: SmBusIoAddr16 - I/O base address of the SMBus Controller +// Protocol8 - SMBus operation to be performed +// PecCheck - TRUE will set PecCheck bit. +// +// Ouput: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID StartSmBusTransition ( + IN UINT16 SmBusIoAddr16, + IN UINT8 Protocol8, + IN BOOLEAN PecCheck ) +{ + UINT8 Buffer8; + + Buffer8 = Protocol8; + if (PecCheck) { + Buffer8 |= HST_CNT_PEC_EN; + SET_IO8(SmBusIoAddr16 + SMB_IOREG_AUX_CTL, AUX_CTL_AAC); // 0x0D + } + IoWrite8(SmBusIoAddr16 + SMB_IOREG_HST_CNT, Buffer8); + + Buffer8 |= HST_CNT_START; + + if (Protocol8 == SMB_CMD_BLOCK) + // Clear SECOND_TO_STS status before SMBus block read/write. + WRITE_IO8_TCO(TCO_IOREG_STS2, 2); // 0x06 + + IoWrite8(SmBusIoAddr16 + SMB_IOREG_HST_CNT, Buffer8); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WaitForSmBusComplete +// +// Description: This support function waits for the operation complete +// +// Input: SmBusIoAddr16 - I/O base address of the SMBus Controller +// +// Output: EFI_STATUS +// EFI_DEVICE_ERROR - An error on the SMBus device. +// EFI_SUCCESS - SMBus transaction is successfully +// completed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS WaitForSmBusComplete ( + IN UINT16 SmBusIoAddr16, + IN UINT8 Protocol8 ) +{ + volatile UINT8 Buffer8; + UINT8 StsChkBit; + UINT16 TimeoutCounter; + + for (TimeoutCounter = 0; TimeoutCounter < 0x6000; TimeoutCounter++) { + Buffer8 = IoRead8(IO_DELAY_PORT); // I/O Delay + Buffer8 = IoRead8(SmBusIoAddr16 + SMB_IOREG_HST_STS); + if (Buffer8 & (HST_STS_BDS | HST_STS_ERROR | HST_STS_INTR)) break; + } + + StsChkBit = (Protocol8 == SMB_CMD_BLOCK) ? HST_STS_BDS : HST_STS_INTR; + if (Buffer8 & StsChkBit) + return (Buffer8 & HST_STS_ERROR) ? EFI_DEVICE_ERROR : EFI_SUCCESS; + return EFI_DEVICE_ERROR; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ClearSmBusStatusAndDelay +// +// Description: This support function clears all statues of the SMBus +// controller +// +// Input: SmBusIoAddr16 - I/O base address of the SMBus Controller +// +// Ouptut: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID ClearSmBusStatusAndDelay ( + IN UINT16 SmBusIoAddr16 ) +{ + UINT16 Timeout = 0x4000; + volatile UINT8 HstSts; + + // Waiting for transmission completed. + do { + Timeout--; + if (Timeout == 0) break; + HstSts = IoRead8(SmBusIoAddr16 + SMB_IOREG_HST_STS); + if (HstSts & HST_STS_HOST_BUSY) continue; + } while ((HstSts & (HST_STS_ERROR | HST_STS_INTR | HST_STS_BDS)) == 0); + + // Clears all statues. + IoWrite8(SmBusIoAddr16 + SMB_IOREG_HST_STS, HST_STS_ALL); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: AfterSMBusTransfer +// +// Description: Restore the enviornment. +// +// Input: SmBusIoAddr16 - I/O base address of the SMBus Controller +// Protocol8 - SMBus operation to be performed +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID AfterSMBusTransfer ( + IN UINT16 SmBusIoAddr16, + IN UINT8 Protocol8 ) +{ +//#### if (Protocol8 == SMB_CMD_BLOCK) +//#### RESET_IO8(SmBusIoAddr16 + SMB_IOREG_AUX_CTL, AUX_CTL_E32B); // 0x0D + RESET_IO8(SmBusIoAddr16 + SMB_IOREG_AUX_CTL, AUX_CTL_AAC); // 0x0D + + // BIOS releases the ownership of SMBus. + IoWrite8(SmBusIoAddr16 + SMB_IOREG_HST_STS, HST_STS_INUSE_STS); + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwSmBusData +// +// Description: This support function reads/writes from/to SMBus Controller. +// +// Input: SmBusIoAddr16 - I/O base address of the SMBus Controller +// SlAddr8 - Address of the SMBus device +// Command8 - SMBus command to be performed +// Protocol8 - SMBus operation to be performed +// PecCheck - TRUE will set PecCheck bit. +// Length8 - Size of data buffer in bytes +// Data8 - Buffer for the read/write data(s) +// +// Output: Return Status based on errors that occurred while SMBus +// transaction. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS RwSmBusData ( + IN UINT16 SmBusIoAddr16, + IN UINT8 SlAddr8, + IN UINT8 Command8, + IN UINT8 Protocol8, + IN BOOLEAN PecCheck, + IN UINT8 Length8, + IN OUT UINT8 *Data8 ) +{ + EFI_STATUS Status; + BOOLEAN IsWriteOperation = (!(SlAddr8 & XMIT_SLVA_RW)); + + Status = BeforeSMBusTransfer(SmBusIoAddr16, Protocol8); + if (Status != EFI_SUCCESS) return Status; + WriteCommand(SmBusIoAddr16, Command8); + WriteSlAddr(SmBusIoAddr16, SlAddr8); + if (IsWriteOperation) + WriteSMBusData(SmBusIoAddr16, Protocol8, Length8, Data8); + StartSmBusTransition(SmBusIoAddr16, Protocol8, PecCheck); + Status = WaitForSmBusComplete(SmBusIoAddr16, Protocol8); + if (Status == EFI_SUCCESS) { + if (IsWriteOperation) { + if (Protocol8 == SMB_CMD_BLOCK) + WriteSmBusBlockData(SmBusIoAddr16, Length8, &Data8[1]); + } else { + Status = ReadSmBusData(SmBusIoAddr16, Protocol8, Length8, Data8); + } + } + + ClearSmBusStatusAndDelay(SmBusIoAddr16); + AfterSMBusTransfer(SmBusIoAddr16, Protocol8); + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: Execute +// +// Description: This function sends commands via SMBUS interface +// +// Input: IN SMBUS_PRIVATE *Context - SMBUS device private data +// IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress - slave address value +// IN EFI_SMBUS_DEVICE_COMMAND Command - command +// IN EFI_SMBUS_OPERATION Operation - operation +// IN BOOLEAN PecCheck - parity check flag +// IN OUT UINTN *Length - pointer to size of data buffer +// IN OUT VOID *Buffer - pointer to data buffer +// +// Output: EFI_STATUS +// +// Notes: Porting required +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS Execute ( + IN SMBUS_PRIVATE *Context, + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN EFI_SMBUS_DEVICE_COMMAND Command, + IN EFI_SMBUS_OPERATION Operation, + IN BOOLEAN PecCheck, + IN OUT UINTN *Length, + IN OUT VOID *Buffer +) +{ + // Porting required - implement internal Smbus protocols here + EFI_STATUS Status = EFI_UNSUPPORTED; + UINT8 *bData = (UINT8 *)Buffer; + UINT8 bSlAddr = (UINT8)(SlaveAddress.SmbusDeviceAddress << 1); + UINT8 bCommand = (UINT8)Command; + UINT8 bLength = (UINT8)(*Length); + + // Wait for SMBus transaction to finish if needed. +//#### while (IoRead8(Context->SmBusBase + SMB_IOREG_CNTL) & 3); + + if (bLength > 32) bLength = 32; + if (bLength == 0) return EFI_INVALID_PARAMETER; + + switch (Operation) { + case EfiSmbusQuickRead: + case EfiSmbusQuickWrite: + break; + + case EfiSmbusReceiveByte: + break; + + case EfiSmbusSendByte: + Status = RwSmBusData( Context->SmBusBase , \ + bSlAddr, \ + bCommand, \ + SMB_CMD_BYTE, \ + PecCheck, \ + 1, \ + bData ); + break; + + case EfiSmbusReadByte: + Status = RwSmBusData( Context->SmBusBase , \ + (bSlAddr | XMIT_SLVA_RW), \ + bCommand, \ + SMB_CMD_BYTE_DATA, \ + PecCheck, \ + 1, \ + bData ); + break; + case EfiSmbusReadWord: + Status = RwSmBusData( Context->SmBusBase , \ + (bSlAddr | XMIT_SLVA_RW), \ + bCommand, \ + SMB_CMD_WORD_DATA, \ + PecCheck, \ + 2, \ + bData ); + break; + + case EfiSmbusWriteByte: + Status = RwSmBusData( Context->SmBusBase , \ + bSlAddr, \ + bCommand, \ + SMB_CMD_BYTE_DATA, \ + PecCheck, \ + 1, \ + bData ); + break; + case EfiSmbusWriteWord: + Status = RwSmBusData( Context->SmBusBase , \ + bSlAddr, \ + bCommand, \ + SMB_CMD_WORD_DATA, \ + PecCheck, \ + 2, \ + bData ); + break; + + case EfiSmbusReadBlock: + Status = RwSmBusData( Context->SmBusBase , \ + (bSlAddr | XMIT_SLVA_RW), \ + bCommand, \ + SMB_CMD_BLOCK, \ + PecCheck, \ + bLength, \ + bData ); + *Length = IoRead8( Context->SmBusBase + SMB_IOREG_HST_D0 ); + break; + + case EfiSmbusWriteBlock: + Status = RwSmBusData( Context->SmBusBase , \ + bSlAddr, \ + bCommand, \ + SMB_CMD_BLOCK, \ + PecCheck, \ + bLength, \ + bData ); + *Length = IoRead8( Context->SmBusBase + SMB_IOREG_HST_D0 ); + break; + + case EfiSmbusProcessCall: + break; + + case EfiSmbusBWBRProcessCall: + break; + + default: + break; + } + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: CheckNotify +// +// Description: This function checks if SMBUS host received any notifications +// +// Input: IN SMBUS_PRIVATE *Context - SMBUS device private data +// OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress - pointer to return address of notificaion device +// OUT UINTN *Data - pointer to notification data +// +// Output: EFI_STATUS +// +// Notes: Porting required +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS CheckNotify ( + IN SMBUS_PRIVATE *Context, + OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress, + OUT UINTN *Data +) +{ +//Porting required + return EFI_UNSUPPORTED; +} + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Chipset/SB/SmBus/SmBusSmm.dxs b/Chipset/SB/SmBus/SmBusSmm.dxs new file mode 100644 index 0000000..dc90908 --- /dev/null +++ b/Chipset/SB/SmBus/SmBusSmm.dxs @@ -0,0 +1,65 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusSmm.dxs 1 6/06/12 8:00a Victortu $ +// +// $Revision: 1 $ +// +// $Date: 6/06/12 8:00a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmBus/SmBusSmm.dxs $ +// +// 1 6/06/12 8:00a Victortu +// Implement EFI_PEI_SMBUS2_PPI Support. +// +// 1 7/19/11 8:09a Abelwu +// [TAG] EIP63768 +// [Category] Improvement +// [Description] Supported Core 4.6.5.x PI 1.2 / uEFI 2.3.1 compliance +// [Files] SmBusSmm.dxs +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SmBusSmm.DXS +// +// Description: This file is the dependency file for the Smbus SMM +// driver +// +//<AMI_FHDR_END> +//************************************************************************* + +#include <Protocol\SmmBase2.h> +#include <Protocol\SmBus.h> +DEPENDENCY_START + EFI_SMM_BASE2_PROTOCOL_GUID AND + EFI_SMBUS_HC_PROTOCOL_GUID +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/SmiHandlerGeneric.c b/Chipset/SB/SmiHandlerGeneric.c new file mode 100644 index 0000000..112cc29 --- /dev/null +++ b/Chipset/SB/SmiHandlerGeneric.c @@ -0,0 +1,1796 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher/SmiHandlerGeneric.c 2 4/25/12 9:35a Victortu $ +// +// $Revision: 2 $ +// +// $Date: 4/25/12 9:35a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher/SmiHandlerGeneric.c $ +// +// 2 4/25/12 9:35a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Reprogram SMM ChildDispatcher drivers. +// [Files] SmiHandlerGeneric.c; SmiHandlerPorting.c; +// SmiHandlerGeneric2.c; SmmChildDispatch2Main.c; SmmChildDispatcher2.mak; +// SmmChildDispatcher2.sdl; SmmChildDispatch.h; SmmChildDispatchMain.c; +// SmmChildDispatchProtocol.c; SmmChildDispatcher.dxs; +// PchSmiDispatcher.sdl +// +// 1 2/08/12 8:27a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SmiHandlerGeneric.c +// +// Description: This file contains implementation of generic SMI handler +// functions +// +//<AMI_FHDR_END> +//************************************************************************* + +//--------------------------------------------------------------------------- +// Include(s) +//--------------------------------------------------------------------------- + +#include <Token.h> +#include <AmiDxeLib.h> +#include <AmiCspLib.h> +#include "SmmChildDispatch.h" +#include <DXE.h> +//--------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//--------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//--------------------------------------------------------------------------- +// Variable and External Declaration(s) +//--------------------------------------------------------------------------- +// Variable Declaration(s) + +static UINT64 gCurrentInterval = 0xffffffffffffffff; +static UINT16 gEnabledUsbSmi = 0; +static UINT16 gActiveUsbSmi = 0; +static UINT32 gEnabledGpiSmi = 0; +static UINT32 gEnabledTcoSmi = 0; +static UINT32 gEnabledIoTrapSmi = 0; +static UINT32 gIoTrapWriteData = 0; + +BOOLEAN gIsLastState = FALSE; + +// GUID Definition(s) +EFI_GUID gDxeGuid = DXE_SERVICES_TABLE_GUID; + +// Protocol Definition(s) + +// External Declaration(s) + +extern EFI_SMM_SYSTEM_TABLE *pSmst; +extern SMM_CHILD_DISPATCHER SmmHandler[]; +extern EFI_SMM_SMI_CONTEXT SmiContext; + +extern UINT64 gSupportedIntervals[]; + +// Function Definition(s) + +//--------------------------------------------------------------------------- + +//--------------------------------------------------------------------------- +// Software SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSwAddHandler +// +// Description: This function adds SW SMI handler +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSwAddHandler ( + IN VOID *Context ) +{ +//#### Use Intel RC if (SmmHandler[EfiSmmSwSmi].RegisteredCallbacks.Size == 1) SwSmiEnable(); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSwRemoveHandler +// +// Description: This function removes SW SMI handler +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSwRemoveHandler ( + IN VOID *Context ) +{ +//#### Use Intel RC if (SmmHandler[EfiSmmSwSmi].RegisteredCallbacks.Size == 1) SwSmiDisable(); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSwVerifyContext +// +// Description: This function verifies SW SMI context +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_STATUS +// EFI_INVALID_PARAMETER - Given context is invalid +// EFI_SUCCESS - Context verified +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSwVerifyContext ( + IN VOID *Context ) +{ +//#### Use Intel RC HANDLER_LINK *Handler = (HANDLER_LINK *)\ +//#### Use Intel RC SmmHandler[EfiSmmSwSmi].RegisteredCallbacks.pHead; +//#### Use Intel RC EFI_SMM_SW_DISPATCH_CONTEXT *SwContext; +//#### Use Intel RC EFI_SMM_SW_DISPATCH_CONTEXT *RegisteredSwContext; + +//#### Use Intel RC SwContext = (EFI_SMM_SW_DISPATCH_CONTEXT *)Context; +//#### Use Intel RC // First check if we already registered handler for this value +//#### Use Intel RC while (Handler != NULL) { +//#### Use Intel RC RegisteredSwContext = (EFI_SMM_SW_DISPATCH_CONTEXT *)Handler->Context; +//#### Use Intel RC if(SwContext->SwSmiInputValue == RegisteredSwContext->SwSmiInputValue) +//#### Use Intel RC // Handler with this value already registered +//#### Use Intel RC return EFI_INVALID_PARAMETER; + +//#### Use Intel RC Handler = (HANDLER_LINK *)Handler->Link.pNext; +//#### Use Intel RC } + +//#### Use Intel RC // Second check if given value is extended SMI value, +//#### Use Intel RC // check the lowest byte +//#### Use Intel RC if ((SwContext->SwSmiInputValue & 0xff) == EXTENDED_SMI) +//#### Use Intel RC return EFI_SUCCESS; // Accept value of UINTN size + +//#### Use Intel RC // Third check if given value is in default range +//#### Use Intel RC return (SwContext->SwSmiInputValue > MAX_SW_SMI_INPUT_VALUE) ? \ +//#### Use Intel RC EFI_INVALID_PARAMETER : EFI_SUCCESS; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSwGetContext +// +// Description: This function verifies SW SMI event and sets SW SMI context +// +// Input: None +// +// Output: BOOLEAN +// TRUE - SW SMI occured, context saved +// FALSE - There was no SW SMI +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SmmSwGetContext (VOID) +{ + UINT16 SwSmiNumber; + BOOLEAN SwSmiDetected; + + // use intel ref code + return FALSE; + + SwSmiDetected = SwSmiDetect( &SwSmiNumber ); + + if (SwSmiDetected) { + if(SwSmiNumber == EXTENDED_SMI) { + // Get the actual number from EAX register + SmiContext.SwContext.SwSmiInputValue = GetEAX(); + } else { + SmiContext.SwContext.SwSmiInputValue = SwSmiNumber; + } + } + + return SwSmiDetected; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSwDispatchSmi +// +// Description: This function dispatches SW SMI event based on context +// +// Input: None +// +// Output: None +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SmmSwDispatchSmi (VOID) +{ +//#### Use Intel RC HANDLER_LINK *Handler; +//#### Use Intel RC EFI_SMM_SW_DISPATCH_CONTEXT *SwContext; + +//#### Use Intel RC Handler = \ +//#### Use Intel RC (HANDLER_LINK *)SmmHandler[EfiSmmSwSmi].RegisteredCallbacks.pHead; +//#### Use Intel RC while (Handler != NULL) { +//#### Use Intel RC SwContext = (EFI_SMM_SW_DISPATCH_CONTEXT *)Handler->Context; +//#### Use Intel RC if(SwContext->SwSmiInputValue == SmiContext.SwContext.SwSmiInputValue) +//#### Use Intel RC Handler->Callback(Handler, SwContext); + +//#### Use Intel RC Handler = (HANDLER_LINK *)Handler->Link.pNext; +//#### Use Intel RC } + +//#### Use Intel RC SwSmiClear(); +} + +//--------------------------------------------------------------------------- +// Sleep SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSxAddHandler +// +// Description: This function adds Sx SMI handler +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSxAddHandler ( + IN VOID *Context ) +{ +//#### Use Intel RC#if SLP_SMI_ENABLE_ON_REGISTER +//#### Use Intel RC if (SmmHandler[EfiSmmSxSmi].RegisteredCallbacks.Size == 1) SxSmiEnable(); +//#### Use Intel RC#endif + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSxRemoveHandler +// +// Description: This function removes Sx SMI handler +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSxRemoveHandler ( + IN VOID *Context ) +{ +//#### Use Intel RC if (SmmHandler[EfiSmmSxSmi].RegisteredCallbacks.Size == 1) SxSmiDisable(); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSxVerifyContext +// +// Description: This function verifies Sx SMI context +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_STATUS +// EFI_SUCCESS - Context verified +// EFI_INVALID_PARAMETER - Given context is invalid +// EFI_UNSUPPORTED - Context is not supported +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSxVerifyContext ( + IN VOID *Context ) +{ + EFI_SMM_SX_DISPATCH_CONTEXT *SxContext; + + SxContext = (EFI_SMM_SX_DISPATCH_CONTEXT *)Context; + if ((SxContext->Type >= EfiMaximumSleepType) || \ + (SxContext->Phase >= EfiMaximumPhase)) + return EFI_INVALID_PARAMETER; + + return ((SxContext->Phase) != SxExit) ? EFI_UNSUPPORTED : EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSxGetContext +// +// Description: This function verifies Sx SMI event and sets SX SMI context +// +// Input: None +// +// Output: BOOLEAN +// TRUE - Sx SMI occured, context saved +// FALSE - There was no SX SMI +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SmmSxGetContext (VOID) +{ + UINT16 SxSleepState; + BOOLEAN SxSmiDetected; + // use intel ref code + return FALSE; + + SxSmiDetected = SxSmiDetect( &SxSleepState ); + + SmiContext.SxContext.Type = SxSleepState; + SmiContext.SxContext.Phase = SxEntry; + + return SxSmiDetected; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSxDispatchSmi +// +// Description: This function dispatches Sx SMI event based on context +// +// Input: None +// +// Output: None +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SmmSxDispatchSmi (VOID) +{ +//#### Use Intel RC HANDLER_LINK *Handler; +//#### Use Intel RC EFI_SMM_SX_DISPATCH_CONTEXT *SxContext; + +//#### Use Intel RC Handler = \ +//#### Use Intel RC (HANDLER_LINK *)SmmHandler[EfiSmmSxSmi].RegisteredCallbacks.pHead; +//#### Use Intel RC while (Handler != NULL) { +//#### Use Intel RC SxContext = (EFI_SMM_SX_DISPATCH_CONTEXT *)Handler->Context; + +//#### Use Intel RC if ((SxContext->Type == SmiContext.SxContext.Type) && \ +//#### Use Intel RC (SxContext->Phase == SmiContext.SxContext.Phase)) +//#### Use Intel RC Handler->Callback(Handler, SxContext); + +//#### Use Intel RC Handler = (HANDLER_LINK *)Handler->Link.pNext; +//#### Use Intel RC } + +//#### Use Intel RC SxSmiClear(); + +//#### Use Intel RC if (SmiContext.SxContext.Type == SxS0) return; + +//#### Use Intel RC PutToSleep( &(SmiContext.SxContext) ); + + // Control returns here on S1. + +//#### Use Intel RC SxSmiClear(); +} + +//--------------------------------------------------------------------------- +// Periodic timer SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmTimerAddHandler +// +// Description: This function adds Periodic timer SMI handler +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmTimerAddHandler ( + IN VOID *Context ) +{ +//#### Use Intel RC EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *TimerContext; + +//#### Use Intel RC TimerContext = (EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *)Context; + +//#### Use Intel RC TimerContext->TimerEnabled = TRUE; + +//#### Use Intel RC if (SmmHandler[EfiSmmPeriodicTimerSmi].RegisteredCallbacks.Size == 1) { +//#### Use Intel RC gCurrentInterval = TimerContext->SmiTickInterval; +//#### Use Intel RC TimerSetInterval( TimerContext->SmiTickInterval ); +//#### Use Intel RC TimerSmiClear(); +//#### Use Intel RC TimerSmiEnable(); +//#### Use Intel RC return EFI_SUCCESS; +//#### Use Intel RC } + +//#### Use Intel RC if (gCurrentInterval > TimerContext->SmiTickInterval) { +//#### Use Intel RC gCurrentInterval = TimerContext->SmiTickInterval; +//#### Use Intel RC TimerSetInterval( TimerContext->SmiTickInterval ); +//#### Use Intel RC } + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmTimerRemoveHandler +// +// Description: This function removes Periodic timer SMI handler +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmTimerRemoveHandler ( + IN VOID *Context ) +{ +//#### Use Intel RC HANDLER_LINK *Handler = (HANDLER_LINK *)\ +//#### Use Intel RC SmmHandler[EfiSmmPeriodicTimerSmi].RegisteredCallbacks.pHead; +//#### Use Intel RC EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *TimerContext; +//#### Use Intel RC EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *CurrentTimerContext; +//#### Use Intel RC UINT64 Interval = 0xffffffffffffffff; + +//#### Use Intel RC UINT16 CurrentIntervalCounter = 0; +//#### Use Intel RC UINT64 *SupportedIntervals = gSupportedIntervals; + +//#### Use Intel RC ((EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *)Context)->TimerEnabled = \ +//#### Use Intel RC FALSE; + +//#### Use Intel RC if (SmmHandler[EfiSmmPeriodicTimerSmi].RegisteredCallbacks.Size == 1) { +//#### Use Intel RC gCurrentInterval = 0xffffffffffffffff; +//#### Use Intel RC TimerSmiDisable(); +//#### Use Intel RC return EFI_SUCCESS; +//#### Use Intel RC } + +//#### Use Intel RC CurrentTimerContext = (EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *)Context; +//#### Use Intel RC while (Handler != NULL) { +//#### Use Intel RC TimerContext = \ +//#### Use Intel RC (EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *)Handler->Context; +//#### Use Intel RC if (Interval > TimerContext->SmiTickInterval) +//#### Use Intel RC Interval = TimerContext->SmiTickInterval; +//#### Use Intel RC if (TimerContext->SmiTickInterval == \ +//#### Use Intel RC CurrentTimerContext->SmiTickInterval) +//#### Use Intel RC CurrentIntervalCounter++; +//#### Use Intel RC Handler = (HANDLER_LINK *)Handler->Link.pNext; +//#### Use Intel RC } + +//#### Use Intel RC if ((Interval == CurrentTimerContext->SmiTickInterval) && \ +//#### Use Intel RC (CurrentIntervalCounter == 1)) { +//#### Use Intel RC Interval = 0xffffffffffffffff; +//#### Use Intel RC while (*SupportedIntervals != 0) { +//#### Use Intel RC if (*SupportedIntervals != CurrentTimerContext->SmiTickInterval) +//#### Use Intel RC if (*SupportedIntervals < Interval) +//#### Use Intel RC Interval = *SupportedIntervals; +//#### Use Intel RC SupportedIntervals++; +//#### Use Intel RC } +//#### Use Intel RC } + +//#### Use Intel RC // This means lowest rate timer no longer active +//#### Use Intel RC if (gCurrentInterval < Interval) { +//#### Use Intel RC gCurrentInterval = Interval; +//#### Use Intel RC TimerSetInterval( Interval ); +//#### Use Intel RC } + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmTimerVerifyContext +// +// Description: This function verifies Periodic timer SMI context +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_STATUS +// EFI_INVALID_PARAMETER - Given context is invalid +// EFI_SUCCESS - Context verified +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmTimerVerifyContext ( + IN VOID *Context ) +{ + EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *TimerContext; + UINT64 *Interval = gSupportedIntervals; + + TimerContext = (EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *)Context; + while (*Interval != 0) { + if (*Interval == TimerContext->SmiTickInterval) return EFI_SUCCESS; + Interval++; + } + + return EFI_INVALID_PARAMETER; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmTimerGetContext +// +// Description: This function verifies Periodic timer SMI event and sets +// Periodic timer SMI context +// +// Input: None +// +// Output: BOOLEAN +// TRUE - Periodic timer SMI occured, context saved +// FALSE - There was no Periodic timer SMI +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SmmTimerGetContext (VOID) +{ + UINT16 TimerType; + BOOLEAN TimerSmiDetected; + + // use intel ref code + return FALSE; + + TimerSmiDetected = TimerSmiDetect( &TimerType ); + SmiContext.TimerContext.SmiTickInterval = gCurrentInterval; + + return TimerSmiDetected; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmTimerDispatchSmi +// +// Description: This function dispatches Periodic timer SMI event based on +// context +// +// Input: None +// +// Output: None +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SmmTimerDispatchSmi (VOID) +{ +//#### Use Intel RC HANDLER_LINK *Handler = (HANDLER_LINK *)\ +//#### Use Intel RC SmmHandler[EfiSmmPeriodicTimerSmi].RegisteredCallbacks.pHead; +//#### Use Intel RC EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *TimerContext; + +//#### Use Intel RC while (Handler != NULL) { +//#### Use Intel RC TimerContext = \ +//#### Use Intel RC (EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *)Handler->Context; + +//#### Use Intel RC if (TimerContext->TimerEnabled) { +//#### Use Intel RC TimerContext->ElapsedTime += \ +//#### Use Intel RC SmiContext.TimerContext.SmiTickInterval; +//#### Use Intel RC if ((TimerContext->ElapsedTime) >= (TimerContext->Period)) { +//#### Use Intel RC Handler->Callback(Handler, TimerContext); +//#### Use Intel RC TimerContext->ElapsedTime = 0; +//#### Use Intel RC } +//#### Use Intel RC } +//#### Use Intel RC Handler = (HANDLER_LINK *)Handler->Link.pNext; +//#### Use Intel RC } + +//#### Use Intel RC TimerSmiClear(); +} + +//--------------------------------------------------------------------------- +// USB SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmUsbAddHandler +// +// Description: This function adds USB SMI handler +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmUsbAddHandler ( + IN VOID *Context +) +{ + EFI_STATUS Status; + EFI_SMM_USB_DISPATCH_CONTEXT *UsbContext; + UINT16 ControllerType; + VOID *NewDp; + UINTN Length; + + UsbContext = (EFI_SMM_USB_DISPATCH_CONTEXT *)Context; + + // Save USB device path protocol into SMM memory + Length = DPLength( UsbContext->Device ); + Status = pSmst->SmmAllocatePool( 0, Length, &NewDp ); + if (EFI_ERROR(Status)) return Status; + MemCpy( NewDp, UsbContext->Device, Length ); + UsbContext->Device = (EFI_DEVICE_PATH_PROTOCOL *)NewDp; + + ControllerType = GetControllerType( UsbContext->Device ); + if((ControllerType & gEnabledUsbSmi) == 0) { + gEnabledUsbSmi |= ControllerType; + UsbSmiSet( gEnabledUsbSmi ); + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmUsbRemoveHandler +// +// Description: This function removes USB SMI handler +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmUsbRemoveHandler ( + IN VOID *Context ) +{ +//#### Use Intel RC HANDLER_LINK *Handler = (HANDLER_LINK *)\ +//#### Use Intel RC SmmHandler[EfiSmmUsbSmi].RegisteredCallbacks.pHead; +//#### Use Intel RC EFI_SMM_USB_DISPATCH_CONTEXT *UsbContext; +//#### Use Intel RC UINT16 ControllerType = 0; + +//#### Use Intel RC UsbContext = (EFI_SMM_USB_DISPATCH_CONTEXT *)Context; + +//#### Use Intel RC pSmst->SmmFreePool( UsbContext->Device ); + +//#### Use Intel RC if (SmmHandler[EfiSmmUsbSmi].RegisteredCallbacks.Size == 1) { +//#### Use Intel RC gEnabledUsbSmi = 0; +//#### Use Intel RC UsbSmiSet( gEnabledUsbSmi ); +//#### Use Intel RC return EFI_SUCCESS; +//#### Use Intel RC } + +//#### Use Intel RC while (Handler != NULL) { +//#### Use Intel RC UsbContext = (EFI_SMM_USB_DISPATCH_CONTEXT *)Handler->Context; +//#### Use Intel RC ControllerType |= GetControllerType( UsbContext->Device ); +//#### Use Intel RC Handler = (HANDLER_LINK *)Handler->Link.pNext; +//#### Use Intel RC } + +//#### Use Intel RC if (ControllerType != gEnabledUsbSmi) { +//#### Use Intel RC gEnabledUsbSmi = ControllerType; +//#### Use Intel RC UsbSmiSet( gEnabledUsbSmi ); +//#### Use Intel RC } + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmUsbVerifyContext +// +// Description: This function verifies USB SMI context +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_STATUS +// EFI_INVALID_PARAMETER - Given context is invalid +// EFI_SUCCESS - Context verified +// EFI_UNSUPPORTED - Context is not supported +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmUsbVerifyContext ( + IN VOID *Context ) +{ + EFI_SMM_USB_DISPATCH_CONTEXT *UsbContext; + UINT16 ControllerType; + + UsbContext = (EFI_SMM_USB_DISPATCH_CONTEXT *)Context; + ControllerType = GetControllerType( UsbContext->Device ); + if (((ControllerType & 3) == 0) || (UsbContext->Type > UsbWake)) + return EFI_INVALID_PARAMETER; + + return ((UsbContext->Type) > UsbLegacy) ? EFI_UNSUPPORTED : EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmUsbGetContext +// +// Description: This function verifies USB SMI event and sets USB SMI context +// +// Input: None +// +// Output: BOOLEAN +// TRUE - USB SMI occured, context saved +// FALSE - There was no USB SMI +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SmmUsbGetContext (VOID) +{ + BOOLEAN UsbSmiDetected; + // use intel ref code + return FALSE; + + UsbSmiDetected = UsbSmiDetect( &gActiveUsbSmi ); + SmiContext.UsbContext.Type = UsbLegacy; + + return UsbSmiDetected; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmUsbDispatchSmi +// +// Description: This function dispatches USB SMI event based on context +// +// Input: None +// +// Output: None +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SmmUsbDispatchSmi (VOID) +{ +//#### Use Intel RC HANDLER_LINK *Handler = (HANDLER_LINK *)\ +//#### Use Intel RC SmmHandler[EfiSmmUsbSmi].RegisteredCallbacks.pHead; +//#### Use Intel RC EFI_SMM_USB_DISPATCH_CONTEXT *UsbContext; +//#### Use Intel RC UINT16 ControllerType; + +//#### Use Intel RC while (Handler != NULL) { +//#### Use Intel RC UsbContext = (EFI_SMM_USB_DISPATCH_CONTEXT *)Handler->Context; +//#### Use Intel RC ControllerType = GetControllerType( UsbContext->Device ); + +//#### Use Intel RC if (((ControllerType & gActiveUsbSmi) != 0) && \ +//#### Use Intel RC (UsbContext->Type == SmiContext.UsbContext.Type)) +//#### Use Intel RC Handler->Callback(Handler, UsbContext); + +//#### Use Intel RC Handler = (HANDLER_LINK *)Handler->Link.pNext; +//#### Use Intel RC } + +//#### Use Intel RC UsbSmiClear( gActiveUsbSmi ); + +//#### Use Intel RC gActiveUsbSmi = 0; +} + +//--------------------------------------------------------------------------- +// GPI SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmGpiAddHandler +// +// Description: This function adds GPI SMI handler +// +// Input: VOID *Context - Pointer to SMI context +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmGpiAddHandler ( + IN VOID *Context ) +{ + EFI_SMM_GPI_DISPATCH_CONTEXT *GpiContext; + + GpiContext = (EFI_SMM_GPI_DISPATCH_CONTEXT *)Context; + if (((UINT32)(GpiContext->GpiNum) & gEnabledGpiSmi) == 0) { + gEnabledGpiSmi |= (UINT32)(GpiContext->GpiNum); + GpiSmiSet( (UINT32)(GpiContext->GpiNum) ); + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmGpiRemoveHandler +// +// Description: This function removes GPI SMI handler +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmGpiRemoveHandler ( + IN VOID *Context ) +{ + UINTN RemoveGpiSmi = ((EFI_SMM_GPI_DISPATCH_CONTEXT *)Context)->GpiNum; + + gEnabledGpiSmi &= ~((UINT32)RemoveGpiSmi); + + GpiSmiReset( (UINT32)RemoveGpiSmi ); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmGpiVerifyContext +// +// Description: This function verifies GPI SMI context +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_STATUS +// EFI_INVALID_PARAMETER - Given context is invalid +// EFI_SUCCESS - Context verified +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmGpiVerifyContext ( + IN VOID *Context ) +{ + EFI_SMM_GPI_DISPATCH_CONTEXT *GpiContext; + + GpiContext = (EFI_SMM_GPI_DISPATCH_CONTEXT *)Context; + if ((GpiContext->GpiNum & (UINT32)SUPPORTED_GPIS) == 0) + return EFI_INVALID_PARAMETER; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmGpiGetContext +// +// Description: This function verifies GPI SMI event and sets GPI SMI context +// +// Input: None +// +// Output: BOOLEAN +// TRUE - GPI SMI occured, context saved +// FALSE - There was no GPI SMI +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SmmGpiGetContext (VOID) +{ +//#### Use Intel RC BOOLEAN GpiSmiDetected; +//#### Use Intel RC UINT32 GpiSmiNum; + + // use intel ref code +//#### Use Intel RC GpiSmiDetected = GpiSmiDetect( &GpiSmiNum ); +//#### Use Intel RC SmiContext.GpiContext.GpiNum = GpiSmiNum; +//#### Use Intel RC return GpiSmiDetected; + return FALSE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmGpiDispatchSmi +// +// Description: This function dispatches GPI SMI event based on context +// +// Input: None +// +// Output: None +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SmmGpiDispatchSmi (VOID) +{ +//#### Use Intel RC HANDLER_LINK *Handler = (HANDLER_LINK *)\ +//#### Use Intel RC SmmHandler[EfiSmmGpiSmi].RegisteredCallbacks.pHead; +//#### Use Intel RC EFI_SMM_GPI_DISPATCH_CONTEXT *GpiContext; + +//#### Use Intel RC while (Handler != NULL) { +//#### Use Intel RC GpiContext = (EFI_SMM_GPI_DISPATCH_CONTEXT *)Handler->Context; + +//#### Use Intel RC if ((SmiContext.GpiContext.GpiNum & GpiContext->GpiNum) != 0) +//#### Use Intel RC Handler->Callback( Handler, GpiContext ); + +//#### Use Intel RC Handler = (HANDLER_LINK *)Handler->Link.pNext; +//#### Use Intel RC } + +//#### Use Intel RC GpiSmiClear( (UINT16)SmiContext.GpiContext.GpiNum ); +} + +//--------------------------------------------------------------------------- +// Standby button SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSButtonAddHandler +// +// Description: This function adds Standby button SMI handler +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSButtonAddHandler ( + IN VOID *Context ) +{ + if (SmmHandler[EfiSmmStandbyButtonSmi].RegisteredCallbacks.Size == 1) + SButtonSmiEnable(); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSButtonRemoveHandler +// +// Description: This function removes Standby button SMI handler +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSButtonRemoveHandler ( + IN VOID *Context ) +{ + if (SmmHandler[EfiSmmStandbyButtonSmi].RegisteredCallbacks.Size == 1) + SButtonSmiDisable(); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSButtonVerifyContext +// +// Description: This function verifies Standby button SMI context +// +// Input: VOID *Context - Pointer to SMI context +// +// Output: EFI_STATUS +// EFI_INVALID_PARAMETER - Given context is invalid +// EFI_SUCCESS - Context verified +// EFI_UNSUPPORTED - Context is not supported +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSButtonVerifyContext ( + IN VOID *Context ) +{ + EFI_SMM_STANDBY_BUTTON_DISPATCH_CONTEXT *SButtonContext; + + SButtonContext = (EFI_SMM_STANDBY_BUTTON_DISPATCH_CONTEXT *)Context; + if (SButtonContext->Phase > Exit) + return EFI_INVALID_PARAMETER; + + return (SButtonContext->Phase > Entry) ? EFI_UNSUPPORTED : EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSButtonGetContext +// +// Description: This function verifies Standby button SMI event and sets +// Standby button SMI context +// +// Input: None +// +// Output: BOOLEAN +// TRUE - Standby button SMI occured, context saved +// FALSE - There was no Standby button SMI +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SmmSButtonGetContext (VOID) +{ + UINT16 Dummy = 0; + BOOLEAN SButtonSmiDetected; + + SButtonSmiDetected = SButtonSmiDetect( &Dummy ); + + SmiContext.SBtnContext.Phase = Entry; + + return SButtonSmiDetected; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSButtonDispatchSmi +// +// Description: This function dispatches Standby button SMI event based on +// context +// +// Input: None +// +// Output: None +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SmmSButtonDispatchSmi (VOID) +{ + HANDLER_LINK *Handler = (HANDLER_LINK *)\ + SmmHandler[EfiSmmStandbyButtonSmi].RegisteredCallbacks.pHead; + EFI_SMM_STANDBY_BUTTON_DISPATCH_CONTEXT *SButtonContext; + + while (Handler != NULL) { + SButtonContext = \ + (EFI_SMM_STANDBY_BUTTON_DISPATCH_CONTEXT *)Handler->Context; + + if (SButtonContext->Phase == SmiContext.SBtnContext.Phase) + Handler->Callback( Handler, SButtonContext ); + + Handler = (HANDLER_LINK *)Handler->Link.pNext; + } + + SButtonSmiClear(); +} + +//--------------------------------------------------------------------------- +// Power button SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmPButtonAddHandler +// +// Description: This function adds Power button SMI handler +// +// Input: *Context - pointer to SMI context +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmPButtonAddHandler ( + IN VOID *Context ) +{ +#if 0 + if (SmmHandler[EfiSmmPowerButtonSmi].RegisteredCallbacks.Size == 1) + PButtonSmiEnable(); +#endif + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmPButtonRemoveHandler +// +// Description: This function removes Power button SMI handler +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_SUCCESS; +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmPButtonRemoveHandler ( + IN VOID *Context ) +{ +#if 0 + if (SmmHandler[EfiSmmPowerButtonSmi].RegisteredCallbacks.Size == 1) + PButtonSmiDisable(); +#endif + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmPButtonVerifyContext +// +// Description: This function verifies Power button SMI context +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_STATUS +// EFI_INVALID_PARAMETER - Given context is invalid +// EFI_SUCCESS - Context verified +// EFI_UNSUPPORTED - Context is not supported +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmPButtonVerifyContext ( + IN VOID *Context ) +{ + EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT *PButtonContext; + + PButtonContext = (EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT *)Context; + if (PButtonContext->Phase > PowerButtonExit) + return EFI_INVALID_PARAMETER; + + return (PButtonContext->Phase > PowerButtonEntry) ? \ + EFI_UNSUPPORTED : EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmPButtonGetContext +// +// Description: This function verifies Power button SMI event and sets Power +// button SMI context +// +// Input: None +// +// Output: BOOLEAN +// TRUE - Power button SMI occured, context saved +// FALSE - There was no Power button SMI +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SmmPButtonGetContext (VOID) +{ + UINT16 Dummy = 0; + BOOLEAN PButtonSmiDetected; + + PButtonSmiDetected = PButtonSmiDetect( &Dummy ); + + SmiContext.PBtnContext.Phase = PowerButtonEntry; + + return PButtonSmiDetected; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmPButtonDispatchSmi +// +// Description: This function dispatches Power button SMI event based on +// context +// +// Input: None +// +// Output: None +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SmmPButtonDispatchSmi (VOID) +{ +#if 0 + HANDLER_LINK *Handler = (HANDLER_LINK *)\ + SmmHandler[EfiSmmPowerButtonSmi].RegisteredCallbacks.pHead; + EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT *PButtonContext; + + while (Handler != NULL) { + PButtonContext = \ + (EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT *)Handler->Context; + + if (PButtonContext->Phase == SmiContext.PBtnContext.Phase) + Handler->Callback( Handler, PButtonContext ); + + Handler = (HANDLER_LINK *)Handler->Link.pNext; + } + + PButtonSmiClear(); + + SBLib_Shutdown(); +#endif +} +//--------------------------------------------------------------------------- +// TCO SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmTcoAddHandler +// +// Description: This function adds TCO SMI handler +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmTcoAddHandler ( + IN VOID *Context ) +{ +//#### Use Intel RC EFI_SMM_TCO_DISPATCH_CONTEXT *TcoContext; + +//#### Use Intel RC TcoContext = (EFI_SMM_TCO_DISPATCH_CONTEXT *)Context; + +//#### Use Intel RC gEnabledTcoSmi |= (1 << (UINT32)(TcoContext->TcoBitOffset)); +//#### Use Intel RC TcoSmiSet( (UINT32)(TcoContext->TcoBitOffset) ); + +//#### Use Intel RC if (SmmHandler[EfiSmmTcoSmi].RegisteredCallbacks.Size == 1) +//#### Use Intel RC TcoSmiEnable(); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmTcoRemoveHandler +// +// Description: This function removes TCO SMI handler +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmTcoRemoveHandler ( + IN VOID *Context ) +{ +//#### Use Intel RC UINT32 RemoveTcoSmiOffset = (UINT32) \ +//#### Use Intel RC (((EFI_SMM_TCO_DISPATCH_CONTEXT *)Context)->TcoBitOffset); + +//#### Use Intel RC TcoSmiReset( RemoveTcoSmiOffset ); + +//#### Use Intel RC gEnabledTcoSmi &= ~(1 << RemoveTcoSmiOffset); + +//#### Use Intel RC if (gEnabledTcoSmi == 0) TcoSmiDisable(); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmTcoVerifyContext +// +// Description: This function verifies TCO SMI context +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_STATUS +// EFI_SUCCESS - Context verified +// EFI_INVALID_PARAMETER - Given context is invalid +// EFI_UNSUPPORTED - Context is not supported +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmTcoVerifyContext ( + IN VOID *Context ) +{ +//#### Use Intel RC EFI_SMM_TCO_DISPATCH_CONTEXT *TcoContext; + +//#### Use Intel RC TcoContext = (EFI_SMM_TCO_DISPATCH_CONTEXT *)Context; + +//#### Use Intel RC if (((1 << TcoContext->TcoBitOffset) & SUPPORTED_TCOS) == 0) +//#### Use Intel RC return EFI_UNSUPPORTED; + +//#### Use Intel RC if ( TcoContext->TcoBitOffset > 32) return EFI_INVALID_PARAMETER; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmTcoGetContext +// +// Description: This function verifies TCO SMI event and sets TCO SMI context +// +// Input: None +// +// Output: BOOLEAN +// TRUE - TCO SMI occured, context saved +// FALSE - There was no TCO SMI +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SmmTcoGetContext (VOID) +{ +//#### Use Intel RC UINT32 TcoStatus; +//#### Use Intel RC BOOLEAN TcoSmiDetected; + +//#### Use Intel RC TcoSmiDetected = TcoSmiDetect( &TcoStatus ); +//#### Use Intel RC SmiContext.TcoContext.TcoBitOffset = (UINTN)(TcoStatus & gEnabledTcoSmi); +//#### Use Intel RC if (SmiContext.TcoContext.TcoBitOffset == 0) TcoSmiDetected = FALSE; + +//#### Use Intel RC return TcoSmiDetected; + return FALSE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmTcoDispatchSmi +// +// Description: This function dispatches TCO SMI event based on context +// +// Input: None +// +// Output: None +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SmmTcoDispatchSmi (VOID) +{ +//#### Use Intel RC HANDLER_LINK *Handler; +//#### Use Intel RC EFI_SMM_TCO_DISPATCH_CONTEXT *TcoContext; + +//#### Use Intel RC Handler = \ +//#### Use Intel RC (HANDLER_LINK *)SmmHandler[EfiSmmTcoSmi].RegisteredCallbacks.pHead; +//#### Use Intel RC while (Handler != NULL) { +//#### Use Intel RC TcoContext = (EFI_SMM_TCO_DISPATCH_CONTEXT *)Handler->Context; + +//#### Use Intel RC if ((Shl64( 1 , (UINT8)TcoContext->TcoBitOffset)) & \ +//#### Use Intel RC SmiContext.TcoContext.TcoBitOffset) +//#### Use Intel RC Handler->Callback(Handler, TcoContext); + +//#### Use Intel RC Handler = (HANDLER_LINK *)Handler->Link.pNext; +//#### Use Intel RC } + +//#### Use Intel RC TcoSmiClear(); +} + +//--------------------------------------------------------------------------- +// I/O Trap SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmIoTrapAddHandler +// +// Description: This function adds I/O Trap SMI handler +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmIoTrapAddHandler ( + IN VOID *Context ) +{ +//#### Use Intel RC HANDLER_LINK *Handler; +//#### Use Intel RC EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *RegedContext; +//#### Use Intel RC EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *IoTrapContext; +//#### Use Intel RC UINTN i = 0; +//#### Use Intel RC UINT32 TrapRegIndex = 0; + +//#### Use Intel RC IoTrapContext = (EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *)Context; + +//#### Use Intel RC Handler = \ +//#### Use Intel RC (HANDLER_LINK *)SmmHandler[EfiSmmIoTrapSmi].RegisteredCallbacks.pHead; + +//#### Use Intel RC while (Handler != NULL) { +//#### Use Intel RC RegedContext = (EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *)Handler->Context; +//#### Use Intel RC if (RegedContext->Address == IoTrapContext->Address) { +//#### Use Intel RC TrapRegIndex = RegedContext->TrapRegIndex; +//#### Use Intel RC i++; +//#### Use Intel RC } +//#### Use Intel RC Handler = (HANDLER_LINK *)Handler->Link.pNext; +//#### Use Intel RC } + +//#### Use Intel RC if (i > 1) { +//#### Use Intel RC IoTrapContext->TrapRegIndex = TrapRegIndex; +//#### Use Intel RC return EFI_SUCCESS; +//#### Use Intel RC } + +//#### Use Intel RC IoTrapSmiSet( IoTrapContext ); + +//#### Use Intel RC gEnabledIoTrapSmi |= (1 << (UINT32)(IoTrapContext->TrapRegIndex)); + +//#### Use Intel RC if (SmmHandler[EfiSmmIoTrapSmi].RegisteredCallbacks.Size == 1) +//#### Use Intel RC IoTrapSmiEnable(); + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmIoTrapRemoveHandler +// +// Description: This function removes I/O Trap SMI handler +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmIoTrapRemoveHandler ( + IN VOID *Context ) +{ +//#### Use Intel RC HANDLER_LINK *Handler; +//#### Use Intel RC EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *RegedContext; +//#### Use Intel RC UINTN i = 0; +//#### Use Intel RC UINTN RemoveIoTrapRegIndex = \ +//#### Use Intel RC (((EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *)Context)->TrapRegIndex); + +//#### Use Intel RC Handler = \ +//#### Use Intel RC (HANDLER_LINK *)SmmHandler[EfiSmmIoTrapSmi].RegisteredCallbacks.pHead; + +//#### Use Intel RC while (Handler != NULL) { +//#### Use Intel RC RegedContext = (EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *)Handler->Context; +//#### Use Intel RC if (RegedContext->TrapRegIndex == RemoveIoTrapRegIndex) i++; +//#### Use Intel RC Handler = (HANDLER_LINK *)Handler->Link.pNext; +//#### Use Intel RC } + +//#### Use Intel RC if (i > 1) return EFI_SUCCESS; + +//#### Use Intel RC IoTrapSmiReset( Context ); + +//#### Use Intel RC gEnabledIoTrapSmi &= ~(1 << RemoveIoTrapRegIndex); + +//#### Use Intel RC if (gEnabledIoTrapSmi == 0) IoTrapSmiDisable(); + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmIoTrapVerifyContext +// +// Description: This function verifies I/O Trap SMI context +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_STATUS +// EFI_SUCCESS - Context verified +// EFI_INVALID_PARAMETER - Given context is invalid +// EFI_UNSUPPORTED - Context is not supported +// EFI_OUT_OF_RESOURCES - There is no I/O Trap register +// available +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmIoTrapVerifyContext ( + IN VOID *Context ) +{ +//#### Use Intel RC HANDLER_LINK *Handler; +//#### Use Intel RC EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *RegedContext; +//#### Use Intel RC EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *IoTrapContext; + +//#### Use Intel RC Handler = \ +//#### Use Intel RC (HANDLER_LINK *)SmmHandler[EfiSmmIoTrapSmi].RegisteredCallbacks.pHead; + +//#### Use Intel RC IoTrapContext = (EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *)Context; + +//#### Use Intel RC while (Handler != NULL) { +//#### Use Intel RC RegedContext = (EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *)Handler->Context; +//#### Use Intel RC if (RegedContext->Address == IoTrapContext->Address) { +//#### Use Intel RC if ( IoTrapContext->Length > MAX_SUPPORTED_IOTRAP_LENGTH) +//#### Use Intel RC return EFI_INVALID_PARAMETER; +//#### Use Intel RC return EFI_SUCCESS; +//#### Use Intel RC } +//#### Use Intel RC Handler = (HANDLER_LINK *)Handler->Link.pNext; +//#### Use Intel RC } + +//#### Use Intel RC if (gEnabledIoTrapSmi >= ((1 << MAX_SUPPORTED_IOTRAP_REGS) - 1)) +//#### Use Intel RC return EFI_OUT_OF_RESOURCES; + +//#### Use Intel RC if ( IoTrapContext->Length > MAX_SUPPORTED_IOTRAP_LENGTH) +//#### Use Intel RC return EFI_INVALID_PARAMETER; + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmIoTrapGetContext +// +// Description: This function verifies I/O Trap SMI event and sets +// I/O Trap SMI context. +// +// Input: None +// +// Output: BOOLEAN +// TRUE - I/O Trap SMI occured, context saved +// FALSE - There was no I/O Trap SMI +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SmmIoTrapGetContext (VOID) +{ + return IoTrapSmiDetect( &SmiContext.IoTrapContext ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmIoTrapDispatchSmi +// +// Description: This function dispatches I/O Trap SMI event based on context. +// +// Input: None +// +// Output: None +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SmmIoTrapDispatchSmi (VOID) +{ +//#### Use Intel RC HANDLER_LINK *Handler; +//#### Use Intel RC EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *IoTrapContext; + +//#### Use Intel RC Handler = \ +//#### Use Intel RC (HANDLER_LINK *)SmmHandler[EfiSmmIoTrapSmi].RegisteredCallbacks.pHead; +//#### Use Intel RC while (Handler != NULL) { +//#### Use Intel RC IoTrapContext = (EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *)Handler->Context; + +//#### Use Intel RC if ( IoTrapContext->TrapRegIndex == \ +//#### Use Intel RC SmiContext.IoTrapContext.TrapRegIndex) +//#### Use Intel RC if ( gEnabledIoTrapSmi & (1 << IoTrapContext->TrapRegIndex)) +//#### Use Intel RC Handler->Callback(Handler, &SmiContext.IoTrapContext); + +//#### Use Intel RC Handler = (HANDLER_LINK *)Handler->Link.pNext; +//#### Use Intel RC } + +//#### Use Intel RC IoTrapSmiClear(); +} + +//--------------------------------------------------------------------------- +// BIOS Write SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmBiosWriteAddHandler +// +// Description: This function adds BIOS Write SMI handler. +// +// Input: *Context - pointer to SMI context +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmBiosWriteAddHandler ( + IN VOID *Context ) +{ +//#### Use Intel RC if (SmmHandler[EfiSmmBiosWriteSmi].RegisteredCallbacks.Size == 1) +//#### Use Intel RC BiosWriteSmiEnable(); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmBiosWriteRemoveHandler +// +// Description: This function removes BIOS Write SMI handler. +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_SUCCESS; +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmBiosWriteRemoveHandler ( + IN VOID *Context ) +{ +//#### Use Intel RC if (SmmHandler[EfiSmmBiosWriteSmi].RegisteredCallbacks.Size == 1) +//#### Use Intel RC BiosWriteSmiDisable(); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmBiosWriteVerifyContext +// +// Description: This function verifies BIOS Write SMI context. +// +// Input: *Context - Pointer to SMI context +// +// Output: EFI_STATUS +// EFI_SUCCESS - Context verified +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmBiosWriteVerifyContext ( + IN VOID *Context ) +{ + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmBiosWriteGetContext +// +// Description: This function verifies BIOS Write SMI event. +// +// Input: None +// +// Output: BOOLEAN +// TRUE - BIOS Write SMI occured. +// FALSE - There was no BIOS Write SMI +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SmmBiosWriteGetContext (VOID) +{ + return BiosWriteSmiDetect(); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmBiosWriteDispatchSmi +// +// Description: This function dispatches BIOW Write SMI event based on +// context. +// +// Input: None +// +// Output: None +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SmmBiosWriteDispatchSmi (VOID) +{ +//#### Use Intel RC HANDLER_LINK *Handler = (HANDLER_LINK *)\ +//#### Use Intel RC SmmHandler[EfiSmmBiosWriteSmi].RegisteredCallbacks.pHead; + +//#### Use Intel RC while (Handler != NULL) { +//#### Use Intel RC Handler->Callback( Handler, NULL ); +//#### Use Intel RC Handler = (HANDLER_LINK *)Handler->Link.pNext; +//#### Use Intel RC } + +//#### Use Intel RC BiosWriteSmiClear(); +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/SmiHandlerPorting.c b/Chipset/SB/SmiHandlerPorting.c new file mode 100644 index 0000000..d0e55e1 --- /dev/null +++ b/Chipset/SB/SmiHandlerPorting.c @@ -0,0 +1,1699 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher/SmiHandlerPorting.c 6 3/19/13 8:21a Scottyang $ +// +// $Revision: 6 $ +// +// $Date: 3/19/13 8:21a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher/SmiHandlerPorting.c $ +// +// 6 3/19/13 8:21a Scottyang +// [TAG] EIP118158 +// [Category] Improvement +// [Description] Correct SBLib_CmosRead () offset. +// [Files] SmiHandlerPorting2.c, SBDxe.c, SBGeneric.c, SBSmm.c, +// SmiHandlerPorting.c +// +// 5 11/06/12 8:10a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Reduce function "GetPchSeries()". +// [Files] SBPEI.c, SBDxe.c, SmiHandlerPorting.c, SmiHandlerPorting2.c +// +// 4 9/26/12 4:00a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update for PCH LP GPIO compatible. +// [Files] SB.sdl, SB.H, AcpiModeEnable.c, AcpiModeEnable.sdl, +// SBDxe.c, SBGeneric.c, SBPEI.c, SBSMI.c, SleepSmi.c, +// SmiHandlerPorting.c, SmiHandlerPorting2.c +// +// 3 7/27/12 6:15a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update to support ULT Platform. +// [Files] SB.H, SB.mak, SB.sdl, SB.sd, SBSetup.c, +// AcpiModeEnable.c, SBDxe.c, SBPEI.c, SBSMI.c, SleepSmi.c, +// SmiHandlerPorting.c, SmiHandlerPorting2.c, SBPPI.h, Pch.sdl +// +// 2 4/25/12 9:33a Victortu +// +// [TAG] None +// [Category] Improvement +// [Description] Reprogram SMM ChildDispatcher drivers. +// [Files] SmiHandlerGeneric.c; SmiHandlerPorting.c; +// SmiHandlerGeneric2.c; SmmChildDispatch2Main.c; SmmChildDispatcher2.mak; +// SmmChildDispatcher2.sdl; SmmChildDispatch.h; SmmChildDispatchMain.c; +// SmmChildDispatchProtocol.c; SmmChildDispatcher.dxs; +// PchSmiDispatcher.sdl +// +// [TAG] EIP73033 +// [Category] Improvement +// [Description] 'PciDevicePath' used in GetControllerType(), +// conditionally not set. +// [Files] SmiHandlerPorting.c; SmiHandlerPorting2.c +// +// 1 2/08/12 8:27a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SmiHandlerPorting.c +// +// Description: This file contains SMM Child Dispatcher porting functions +// +//<AMI_FHDR_END> +//************************************************************************* + +//--------------------------------------------------------------------------- +// Include(s) +//--------------------------------------------------------------------------- + +#include <Token.h> +#include <AmiDxeLib.h> +#include <AmiCspLib.h> +#include <AmiSmm.h> +#include "SmmChildDispatch.h" + +//--------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//--------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//--------------------------------------------------------------------------- +// Variable and External Declaration(s) +//--------------------------------------------------------------------------- +// Variable Declaration(s) + +UINT64 gSupportedIntervals[] = { + // Porting required - put all available intervals here (in Nanoseconds) +#if SWSMI_TIMER_INSTEAD + 15000, // 1.5ms + 160000, // 16 ms + 320000, // 32 ms + 640000, // 64 ms +#else + 600000000, // 60 Seconds + 320000000, // 32 Seconds + 160000000, // 16 Seconds + 80000000, // 8 Seconds +#endif + + // Terminator record + 0 +}; + +// GUID Definition(s) + +// Protocol Definition(s) + +// External Declaration(s) + +extern EFI_SMM_SYSTEM_TABLE *pSmst; + +// Function Definition(s) + +//--------------------------------------------------------------------------- + +//--------------------------------------------------------------------------- +// All purpose SMI Porting hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IsAcpi +// +// Description: This function determines if the system is in ACPI mode. +// +// Input: None +// +// Output: BOOLEAN +// TRUE - It is in ACPI mode +// FALSE - It is not in ACPI mode +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN IsAcpi (VOID) +{ + return (READ_IO16_PM(ACPI_IOREG_PM1_CNTL) & 1) ? TRUE : FALSE; // 0x04 +}; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IsMe +// +// Description: This function checks whether the specific SMI event is raised +// +// Input: CheckBitNo - The bit number for the specific SMI. +// +// Output: BOOLEAN +// TRUE - It is the specific SMI event +// FALSE - It is not the specific SMI event +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN IsMe ( + IN UINT8 CheckBitNo ) +{ + volatile UINT32 Buffer32 = READ_IO32_PM(ACPI_IOREG_SMI_EN); // 0x30 + + Buffer32 &= READ_IO32_PM(ACPI_IOREG_SMI_STS); // 0x34 + return (Buffer32 & (UINT32)(1 << CheckBitNo)) ? TRUE : FALSE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ClearAllSmi +// +// Description: This function clears all SMI's and issues an EOS (End of SMI). +// +// Input: None +// +// Output: None +// +// Notes: If you are porting INTEL chipset and have to support SWSMI +// Timer SMI, you must be unable to clear the SWSMI status in +// this routine. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID ClearAllSmi (VOID) +{ + // Porting Required. Program to clear ALL SMI status bit + if ( !IsAcpi() ) { + if (READ_IO16_PM(ACPI_IOREG_PM1_EN) & 0x400) + if (READ_IO16_PM(ACPI_IOREG_PM1_STS) & 0x400) + SBLib_CmosRead(0x0C); + WRITE_IO16_PM(ACPI_IOREG_PM1_STS, 0xcc31); // 0x00 + if (GetPchSeries() == PchLp) { + WRITE_IO32_PM(ACPI_PCHLP_IOREG_GPE0_STS+0x0c, 0xffffffff); // 0x8C + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_ALTGP_SMI_STS, 0xffffffff); // 0x50 + } else { + WRITE_IO32_PM(ACPI_IOREG_GPE0_STS, 0xffffffff); // 0x20 + WRITE_IO32_PM(ACPI_IOREG_GPE0_STS+4, 0xffffffff); // 0x24 + WRITE_IO16_PM(ACPI_IOREG_ALTGP_SMI_STS, 0xffff); // 0x3A + } + WRITE_IO16_PM(ACPI_IOREG_DEVACT_STS, 0xffff); // 0x44 + WRITE_IO16_TCO(TCO_IOREG_STS1, 0xffff); // 0x04 + WRITE_IO16_TCO(TCO_IOREG_STS2, 0xfffe); // 0x06 (Except Intruder Det) + WRITE_IO32_PM(ACPI_IOREG_SMI_STS, 0xffffffbf); // 0x34 (Except SWSMI) + if ((READ_IO16_TCO(TCO_IOREG_CNT1) & 0x300) == 0x300) { // 0x08 + SET_IO16_TCO(TCO_IOREG_CNT1, 0x100); // Clear NMI_NOW if needed. + } + } + // EOS + SET_IO8_PM(ACPI_IOREG_SMI_EN, 0x02); // 0x30 + if ((READ_IO8_PM(ACPI_IOREG_SMI_EN) & 0x02) == 0) { + // Reset GBL_SMI_EN + RESET_IO8_PM(ACPI_IOREG_SMI_EN, 0x01); // 0x30 + // Set EOS Again + SET_IO8_PM(ACPI_IOREG_SMI_EN, 0x02); // 0x30 + // Set GBL_SMI_EN + SET_IO8_PM(ACPI_IOREG_SMI_EN, 0x01); // 0x30 + } +} + +//--------------------------------------------------------------------------- +// SW SMI Handler Porting hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SwSmiEnable +// +// Description: This function enables SW SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SwSmiEnable (VOID) +{ + // Porting required + SET_IO32_PM(ACPI_IOREG_SMI_EN, 0x20); // 0x30 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SwSmiDisable +// +// Description: This function disables SW SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SwSmiDisable (VOID) +{ + // Porting required + RESET_IO32_PM(ACPI_IOREG_SMI_EN, 0x20); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SwSmiClear +// +// Description: This function clears SW SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SwSmiClear (VOID) +{ + // Porting required + WRITE_IO32_PM(ACPI_IOREG_SMI_STS, 0x20); // 0x34 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SwSmiDetect +// +// Description: This function detects SW SMI event +// +// Input: *Type - Pointer to store SW SMI number +// +// Output: TRUE - SW SMI occured, FALSE otherwise +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SwSmiDetect ( + OUT UINT16 *Type ) +{ + // Porting required + if ( IsMe(5) ) { // SW_SMI + *Type = IoRead8(SW_SMI_IO_ADDRESS); + return TRUE; + } + + return FALSE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetEAX +// +// Description: This function returns EAX saved value from CPU that caused +// SW SMI. +// +// Input: None +// +// Output: EAX saved value +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINTN GetEAX (VOID) +{ + // Porting required for different CPU + EFI_GUID SwSmiCpuTriggerGuid = SW_SMI_CPU_TRIGGER_GUID; + SW_SMI_CPU_TRIGGER *SwSmiCpuTrigger; + UINTN Cpu = pSmst->CurrentlyExecutingCpu - 1; // CPU # + EFI_SMM_CPU_SAVE_STATE *CpuSaveState; + UINT16 i; + + for (i = 0; i < pSmst->NumberOfTableEntries; i++) { + if (guidcmp(&(pSmst->SmmConfigurationTable[i].VendorGuid), \ + &SwSmiCpuTriggerGuid) == 0) + break; + } + + // If found table, check for the CPU that caused the software Smi. + if (i != pSmst->NumberOfTableEntries) + { + SwSmiCpuTrigger = pSmst->SmmConfigurationTable[i].VendorTable; + Cpu = SwSmiCpuTrigger->Cpu; + } + CpuSaveState = pSmst->CpuSaveState; + + return CpuSaveState[Cpu].Ia32SaveState.EAX; +} + +//--------------------------------------------------------------------------- +// SX SMI Handler Porting hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SxSmiEnable +// +// Description: This function enables SX SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SxSmiEnable (VOID) +{ + // Porting required + SET_IO32_PM(ACPI_IOREG_SMI_EN, 0x10); // 0x30 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SxSmiDisable +// +// Description: This function disables SX SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SxSmiDisable (VOID) +{ + // Porting required + RESET_IO32_PM(ACPI_IOREG_SMI_EN, 0x10); // 0x30 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SxSmiClear +// +// Description: This function clears SX SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SxSmiClear (VOID) +{ + // Porting required + WRITE_IO32_PM(ACPI_IOREG_SMI_STS, 0x10); // 0x34 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SxSmiDetect +// +// Description: This function detects SX SMI event +// +// Input: *Type - Pointer to store value of Sleep type +// +// Output: TRUE - SX SMI occured, FALSE otherwise +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SxSmiDetect ( + OUT UINT16 *Type ) +{ + // Porting required + if (IsMe(4)) { // SLP_SMI + switch (READ_IO16_PM(ACPI_IOREG_PM1_CNTL) & (7 << 10)) { // SLP_TYP + case (0 << 10): + *Type = SxS0; + break; + case (1 << 10): + *Type = SxS1; + break; + case (5 << 10): + *Type = SxS3; + break; + case (6 << 10): + *Type = SxS4; + break; + case (7 << 10): + *Type = SxS5; + break; + default: + return FALSE; // Unknown Error. + } + return TRUE; + } + return FALSE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: PutToSleep +// +// Description: Disable Smi sleep and put to sleep. +// +// Input: *Context - Pointer to Sleep SMI context +// +// Output: None +// +// Referrals: SxSmiDisable +// +// Notes: Here is the control flow of this function: +// 1. Disable Smi sleep. +// 2. Set to go to sleep if you want to sleep in SMI. otherwise +// set IORestart to 0xFF in CPU SMM dump area. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PutToSleep ( + IN VOID *SxContext ) +{ + EFI_SMM_CPU_SAVE_STATE *pCpuSaveState = pSmst->CpuSaveState; + UINTN Cpu = pSmst->CurrentlyExecutingCpu - 1; + UINT32 CacheFlush = 0; + + SxSmiDisable(); // Disable sleep SMI. + +//#### if (SxContext->Type == SxS5) +//#### SBLib_BeforeShutdown(); + +#if ACPI_SLEEP_IN_SMM + SET_IO16_PM(ACPI_IOREG_PM1_CNTL, 0x2000); // Set to sleep. +#else + CacheFlush = pCpuSaveState[Cpu].Ia32SaveState.IORestart; + pCpuSaveState[Cpu].Ia32SaveState.IORestart = 0xff; +#endif + +} + +//--------------------------------------------------------------------------- +// Periodic timer SMI Handler Porting hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TimerSmiEnable +// +// Description: This function enables Periodic timer SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID TimerSmiEnable (VOID) +{ + // Porting required +#if SWSMI_TIMER_INSTEAD + SET_IO32_PM(ACPI_IOREG_SMI_EN, 0x40); // 0x30 +#else + SET_IO32_PM(ACPI_IOREG_SMI_EN, 0x4000); // 0x30 +#endif +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TimerSmiDisable +// +// Description: This function disables Periodic timer SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID TimerSmiDisable (VOID) +{ + // Porting required +#if SWSMI_TIMER_INSTEAD + RESET_IO32_PM(ACPI_IOREG_SMI_EN, 0x40); // 0x30 +#else + RESET_IO32_PM(ACPI_IOREG_SMI_EN, 0x4000); // 0x30 +#endif +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TimerSmiClear +// +// Description: This function clears Periodic timer SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID TimerSmiClear (VOID) +{ + // Porting required +#if SWSMI_TIMER_INSTEAD + // SWSMI has to be disabled before clear the status + volatile UINT32 Buffer32 = READ_IO32_PM(ACPI_IOREG_SMI_EN); // 0x30 + WRITE_IO32_PM(ACPI_IOREG_SMI_EN, Buffer32 & (UINT32)(~0x40)); // 0x30 + WRITE_IO32_PM(ACPI_IOREG_SMI_STS, 0x40); // 0x34 + WRITE_IO32_PM(ACPI_IOREG_SMI_EN, Buffer32); // 0x30 +#else + WRITE_IO32_PM(ACPI_IOREG_SMI_STS, 0x4000); // 0x34 +#endif +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TimerSmiDetect +// +// Description: This function detects Periodic timer SMI event +// +// Input: *Type - Added for compatibility, not used +// +// Output: TRUE - Periodic timer SMI occured, FALSE otherwise +// +// Notes: Return TRUE if Timer SMI detected, Type ignored +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN TimerSmiDetect ( + OUT UINT16 *Type ) +{ + // Porting required + *Type = 0; +#if SWSMI_TIMER_INSTEAD + return (IsMe(6)) ? TRUE : FALSE; +#else + return (IsMe(14)) ? TRUE : FALSE; +#endif +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TimerSetInterval +// +// Description: This function programs Periodic timer to given interval +// +// Input: Interval - Interval to program +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID TimerSetInterval ( + IN UINT64 Interval ) +{ + // Porting required + UINT16 RateIndex; + UINT16 AvailTimer = sizeof(gSupportedIntervals) / sizeof(UINT64) - 1; + + TimerSmiDisable(); + TimerSmiClear(); + + for (RateIndex = 0; RateIndex < AvailTimer ; RateIndex++) + if (Interval == gSupportedIntervals[RateIndex]) break; +#if SWSMI_TIMER_INSTEAD + RW_PCI16_SB(SB_REG_GEN_PMCON_3, RateIndex << 6, 0xc0); // 0xA4 +#else + RW_PCI16_SB(SB_REG_GEN_PMCON_1, RateIndex, 3); // 0xA0 +#endif + + TimerSmiEnable(); +} + +//--------------------------------------------------------------------------- +// Usb SMI Handler Porting hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: UsbSmiSet +// +// Description: This function enables/disables USB SMI based on given +// Controller type +// +// Input: ControllerType - USB controller type variable +// +// Output: None +// +// Notes: This function implements logic as follows: +// Two lowest bits of ControllerType: +// 00 - both USB controllers smi are disabled +// 01 - UHCI/OHCI enabled, EHCI - disabled +// 10 - UHCI/OHCI disabled, EHCI - enabled +// 11 - both USB controllers smi are enabled +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID UsbSmiSet( + IN UINT16 ControllerType ) +{ + // Porting required + switch (ControllerType & 3) { + case 0 : + RESET_PCI32_EHCI(EHCI_REG_SPECIAL_SMI, 1); + RESET_PCI32_EHCI2(EHCI_REG_SPECIAL_SMI, 1); + RESET_IO32_PM(ACPI_IOREG_SMI_EN, 0x60008); // 0x30 + break; + case 1 : + RESET_PCI32_EHCI(EHCI_REG_SPECIAL_SMI, 1); + RESET_PCI32_EHCI2(EHCI_REG_SPECIAL_SMI, 1); + RW_IO32_PM(ACPI_IOREG_SMI_EN, 0x08, 0x60008); // 0x30 + break; + case 2 : + RW_IO32_PM(ACPI_IOREG_SMI_EN, 0x60000, 0x60008); // 0x30 + SET_PCI32_EHCI(EHCI_REG_SPECIAL_SMI, 1); + SET_PCI32_EHCI2(EHCI_REG_SPECIAL_SMI, 1); + break; + default: + SET_IO32_PM(ACPI_IOREG_SMI_EN, 0x60008); // 0x30 + SET_PCI32_EHCI(EHCI_REG_SPECIAL_SMI, 1); + SET_PCI32_EHCI2(EHCI_REG_SPECIAL_SMI, 1); + break; + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: UsbSmiClear +// +// Description: This function clears USB SMI based on given Controller type +// +// Input: UINT16 ControllerType - USB controller type variable +// +// Output: None +// +// Notes: This function implements logic as follows: +// Two lowest bits of ControllerType: +// 00 - Nothing to do +// 01 - Clear UHCI/OHCI USB SMI status +// 10 - Clear EHCI USB SMI status +// 11 - Clear UHCI/OHCI & EHCI USB SMI statuses +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID UsbSmiClear ( + IN UINT16 ControllerType ) +{ + // Porting required + switch (ControllerType & 3) { + case 0 : + break; + case 1 : + WRITE_IO32_PM(ACPI_IOREG_SMI_STS, 0x08); // 0x34 + break; + case 2 : + WRITE_IO32_PM(ACPI_IOREG_SMI_STS, 0x20000); // 0x34 + break; + default: + WRITE_IO32_PM(ACPI_IOREG_SMI_STS, 0x20008); // 0x34 + break; + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: UsbSmiDetect +// +// Description: This function detects USB SMI event +// +// Input: *Type - Pointer to store USB controller type, source of event +// +// Output: TRUE - USB SMI occured, FALSE otherwise +// +// Notes: This function implements logic as follows: +// *Type will be set to +// 01 - If UHCI/OHCI USB SMI is occured +// 02 - If EHCI USB SMI is occured +// 03 - If UHCI/OHCI & EHCI USB SMI is occured +// 00 - Nothing is occured and return FALSE +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN UsbSmiDetect ( + OUT UINT16 *Type ) +{ + // Porting required + *Type = 0; + if (IsMe(3)) *Type |= 1; // USB_SMI (USB 1.1) + if (IsMe(17)) *Type |= 2; // USB_SMI (USB 2.0) + + return (*Type) ? TRUE : FALSE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetControllerType +// +// Description: This function returns USB controller type, based on given +// device path +// +// Input: *Device - Pointer USB device path protocol +// +// Output: UINT16 - USB controller type +// +// Notes: The USB controller type will be retuened by the follow value: +// 0 - If there is no matche. +// 1 - It is an UHCI/OHCI (USB 1.1) controller +// 2 - It is an EHCI (USB 2.0) controller +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT16 GetControllerType ( + IN EFI_DEVICE_PATH_PROTOCOL *Device) +{ + + // Porting required + EFI_DEVICE_PATH_PROTOCOL *DevicePath = Device; + PCI_DEVICE_PATH *PciDevicePath = NULL; // [EIP73033] + UINT16 ControllerType = 0; + + while (!isEndNode( DevicePath )) { + if ((DevicePath->Type == HARDWARE_DEVICE_PATH) && \ + (DevicePath->SubType == HW_PCI_DP)) { + PciDevicePath = (PCI_DEVICE_PATH *) DevicePath; + break; + } + DevicePath = NEXT_NODE (DevicePath); + } + + if ((PciDevicePath->Device == EHCI_DEV) || \ + (PciDevicePath->Device == EHCI2_DEV)) { + if ((READ_MEM32_RCRB(0x3598) & 1) == 0) return 2; // RMH Enabled + ControllerType = 1; + if (PciDevicePath->Function == 0x07) ControllerType = 2; + } + + return ControllerType; +} + +//--------------------------------------------------------------------------- +// GPI SMI Handler Porting hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GpiSmiSet +// +// Description: This function enables GPI SMI based on given bit field. +// +// Input: GpiEnableBit - GPI enabled bit field +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID GpiSmiSet ( + IN UINT32 GpiEnableBit ) +{ + // Porting required + + UINT8 GpiNum = 0; + PCH_SERIES PchSeries = GetPchSeries(); + + if (PchSeries == PchLp) { + SET_IO32(GPIO_BASE_ADDRESS + GP_IOREG_ALTGP_SMI_EN, GpiEnableBit); + } else { + SET_IO16_PM(ACPI_IOREG_ALTGP_SMI_EN, (UINT16)GpiEnableBit); + } + + while ((GpiEnableBit % 2) == 0) { + GpiEnableBit /= 2; + GpiNum++; + } + + if (PchSeries == PchLp) { + //Only GPI[47:32] are capable of SMI# generation. + SET_IO16(GPIO_BASE_ADDRESS+GP_IOREG_GPI_ROUT2, (UINT16)GpiEnableBit); + } else { + RW_PCI32_SB(SB_REG_GPI_ROUT, 1 << (GpiNum * 2), 3 << (GpiNum * 2)); // 0xB8, + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GpiSmiReset +// +// Description: This function disables GPI SMI based on given bit field. +// +// Input: GpiDisableBit - GPI disabled bit field +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID GpiSmiReset ( + IN UINT32 GpiDisableBit ) +{ + // Porting required + + UINT8 GpiNum = 0; + PCH_SERIES PchSeries = GetPchSeries(); + + if (PchSeries == PchLp) { + RESET_IO32(GPIO_BASE_ADDRESS + GP_IOREG_ALTGP_SMI_EN, GpiDisableBit); + } else { + RESET_IO16_PM(ACPI_IOREG_ALTGP_SMI_EN, (UINT16)GpiDisableBit); + } + + while ((GpiDisableBit % 2) == 0) { + GpiDisableBit /= 2; + GpiNum++; + } + + if (PchSeries == PchLp) { + //Only GPI[47:32] are capable of SMI# generation. + RESET_IO16(GPIO_BASE_ADDRESS+GP_IOREG_GPI_ROUT2, (UINT16)GpiDisableBit); + } else { + RESET_PCI32_SB(SB_REG_GPI_ROUT, 3 << (GpiNum * 2)); // 0xB8, + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: GpiSmiClear +// +// Description: This function clears GPI SMI status based on given bit field +// +// Input: Type - GPI Disabled bit field +// +// Output: None +// +// Notes: All GPIs which correspondent bit in Type set to 1 should +// be cleared +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID GpiSmiClear ( + IN UINT32 GpiClearBit ) +{ + // Porting required + if (GetPchSeries() == PchLp) { + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_ALTGP_SMI_EN, GpiClearBit); + } else { + WRITE_IO16_PM(ACPI_IOREG_ALTGP_SMI_STS, (UINT16)GpiClearBit); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GpiSmiDetect +// +// Description: This function detects GPI SMI event +// +// Input: *Gpi - Pointer to store source of GPI SMI +// +// Output: TRUE - GPI SMI occured, FALSE otherwise +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN GpiSmiDetect ( + OUT UINT32 *Gpi ) +{ + // Porting required + if (GetPchSeries() == PchLp) { + *Gpi = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_ALTGP_SMI_EN) & READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_ALTGP_SMI_STS); + } else { + *Gpi = READ_IO16_PM(ACPI_IOREG_ALTGP_SMI_EN) & READ_IO16_PM(ACPI_IOREG_ALTGP_SMI_STS); + } + + return (*Gpi) ? TRUE : FALSE; +} + +//--------------------------------------------------------------------------- +// Standby button SMI Handler Porting hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SButtonSmiEnable +// +// Description: This function enables Standby button SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SButtonSmiEnable (VOID) +{ + // Porting required +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SButtonSmiDisable +// +// Description: This function disables Standby button SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SButtonSmiDisable (VOID) +{ + // Porting required +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SButtonSmiClear +// +// Description: This function clears Standby button SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SButtonSmiClear (VOID) +{ + // Porting required +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SButtonSmiDetect +// +// Description: This function detects Standby button SMI event +// +// Input: *Type - Pointer to store value of Standby button phase, +// not used. +// +// Output: TRUE - Standby button SMI occured, FALSE otherwise +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SButtonSmiDetect ( + OUT UINT16 *Type ) +{ + // Porting required + return FALSE; +} + +//--------------------------------------------------------------------------- +// Power button SMI Handler Porting hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: PButtonSmiEnable +// +// Description: This function enables Power button SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PButtonSmiEnable (VOID) +{ + // Porting required + SET_IO16_PM(ACPI_IOREG_PM1_EN, 0x100); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: PButtonSmiDisable +// +// Description: This function disables Power button SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PButtonSmiDisable (VOID) +{ + // Porting required + RESET_IO16_PM(ACPI_IOREG_PM1_EN, 0x100); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: PButtonSmiClear +// +// Description: This function clears Power button SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PButtonSmiClear (VOID) +{ + // Porting required + WRITE_IO16_PM(ACPI_IOREG_PM1_STS, 0x100); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: PButtonSmiDetect +// +// Description: This function detects Power button SMI event +// +// Input: *Type - pointer to store value of Power button phase +// not used. +// +// Output: TRUE - Power button SMI occured, FALSE - otherwise +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN PButtonSmiDetect ( + OUT UINT16 *Type ) +{ + // Porting Required + UINT16 Buffer16; + + if ( IsAcpi() ) { + return FALSE; + } else { + Buffer16 = READ_IO16_PM(ACPI_IOREG_PM1_STS) & \ + READ_IO16_PM(ACPI_IOREG_PM1_EN) & 0x100; + return (Buffer16) ? TRUE : FALSE; + } +} + +//--------------------------------------------------------------------------- +// TCO SMI Handler Porting hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TcoSmiSet +// +// Description: This function sets TCO functon based on given bit field . +// +// Input: TcoBitOffset - The offset of TCO bit will be set. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID TcoSmiSet ( + IN UINT32 TcoBitOffset ) +{ + UINT32 PchRcba = READ_PCI32_SB(SB_REG_RCBA); + + // NMI2SMI_STS (TCOBASE+04h[0]) + if (TcoBitOffset == 0) { + // Enable NMI by set Port 70h[7] = '0b' + SwitchAlternateAccessMode (TRUE); + RESET_IO8(CMOS_ADDR_PORT, BIT07); + SwitchAlternateAccessMode (FALSE); + + // GBL_SMI_EN = 1 + SET_IO8_PM(ACPI_IOREG_SMI_EN, BIT00); + // Set NMI2SMI_EN = '1b', TCO_BASE + 08h[9] + SET_IO16_TCO(TCO_IOREG_CNT1, BIT09); + } + + // INTRD_DET (TCOBASE+06h[0]) + if (TcoBitOffset == 16) { + // INTRD_SEL + RW_IO16_TCO(TCO_IOREG_STS2, BIT02, (BIT01 | BIT02)); + } + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TcoSmiReset +// +// Description: This function resets TCO functon based on given bit field . +// +// Input: TcoBitOffset - The offset of TCO bit will be reset. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID TcoSmiReset ( + IN UINT32 TcoBitOffset ) +{ + // NMI2SMI_STS (TCOBASE+04h[0]) + if (TcoBitOffset & BIT00) { + // Set NMI2SMI_EN = 0 + RESET_IO16_TCO(TCO_IOREG_CNT1, BIT09); + } + + // INTRD_DET (TCOBASE+06h[0]) + if (TcoBitOffset & BIT16) { + // INTRD_SEL + RESET_IO16_TCO(TCO_IOREG_CNT2, (BIT01 | BIT02)); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TcoSmiEnable +// +// Description: This function enables TCO SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID TcoSmiEnable (VOID) +{ + // Porting required + SET_IO32_PM(ACPI_IOREG_SMI_EN, 0x2000); // 0x30 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TcoSmiDisable +// +// Description: This function disables TCO SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID TcoSmiDisable (VOID) +{ + // Porting required + RESET_IO32_PM(ACPI_IOREG_SMI_EN, 0x2000); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TcoSmiClear +// +// Description: This function clears TCO SMI and TCO statuses +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID TcoSmiClear (VOID) +{ + // Porting required + WRITE_IO32_TCO(TCO_IOREG_STS1, (UINT32)SUPPORTED_TCOS); // 0x04 + WRITE_IO32_PM(ACPI_IOREG_SMI_STS, 0x2000); // 0x34 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TcoSmiDetect +// +// Description: This function detects TCO SMI event +// +// Input: *TcoStatus - Pointer to store TCO SMI status +// +// Output: TRUE - TCO SMI occured, FALSE otherwise +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN TcoSmiDetect ( + OUT UINT32 *TcoStatus ) +{ + // Porting required + if ( (IsMe(13)) || (READ_IO8_TCO(TCO_IOREG_STS1) & BIT00)) { // TCO_SMI + *TcoStatus = READ_IO32_TCO(TCO_IOREG_STS1); // 0x04 + return TRUE; + } + + return FALSE; +} + +//--------------------------------------------------------------------------- +// I/O Trap SMI Handler Porting hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IoTrapSmiSet +// +// Description: This function sets I/O Trap functon based on given the +// context +// +// Input: IoTrapContext - Pointer to the context that I/O trap register +// will be enabled. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID IoTrapSmiSet ( + IN EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *IoTrapContext ) +{ + // Porting required if needed. + UINT32 IoTrapAddr = RCRB_MMIO_IO_TRAP_0; // 0x1E80 + UINT32 i; + UINT32 Buffer32 = 0; + + // Find an available I/O trap register + for (i = 0; i < MAX_SUPPORTED_IOTRAP_REGS; i++) { + if ((READ_MEM32_RCRB(IoTrapAddr) & 1) == 0) break; + IoTrapAddr += 8; + } + + IoTrapContext->TrapRegIndex = i; + + if (IoTrapContext->Length < 4) IoTrapContext->Length = 4; + Buffer32 = IoTrapContext->Length; + for (i = 0; Buffer32 != 1; Buffer32 >>= 1, i++); + if (IoTrapContext->Length > (1 << i)) i++; + + IoTrapContext->Length = 1 << i; // Length is always 2^n + + Buffer32 = IoTrapContext->Address & 0xfffc; + Buffer32 |= ((IoTrapContext->Length - 1) & 0xfffc) << 16; + WRITE_MEM32_RCRB(IoTrapAddr, Buffer32); + + Buffer32 = 0xf0; + if (IoTrapContext->TrapWidth == AccessWord) Buffer32 = 0x03; + if (IoTrapContext->TrapWidth == AccessDWord) Buffer32 = 0x0f; + + if (IoTrapContext->TrapOpType == ReadWriteIoCycle) { + Buffer32 |= (1 << 17); // Both Read/Write Cycles. + } else { + if (IoTrapContext->TrapOpType == ReadIoCycle) + Buffer32 |= (1 << 16); // Read Cycle Only + } + + WRITE_MEM32_RCRB(IoTrapAddr + 4, Buffer32); + SET_MEM32_RCRB(IoTrapAddr, 1); // Enable Trap and SMI. +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IoTrapSmiReset +// +// Description: This function resets I/O Trap functon based on given the +// context +// +// Input: IoTrapContext - Pointer to the context that I/O trap register +// will be disabled. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID IoTrapSmiReset ( + IN EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *IoTrapContext ) +{ + // Porting required if needed. + UINT32 IoTrapAddr = RCRB_MMIO_IO_TRAP_0 + IoTrapContext->TrapRegIndex * 8; + + WRITE_MEM32_RCRB(IoTrapAddr, 0); + WRITE_MEM32_RCRB(IoTrapAddr + 4, 0); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IoTrapSmiEnable +// +// Description: This function enables I/O Trap SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID IoTrapSmiEnable (VOID) +{ + // Porting required if needed. +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IoTrapSmiDisable +// +// Description: This function disables I/O Trap SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID IoTrapSmiDisable (VOID) +{ + // Porting required if needed. +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IoTrapSmiClear +// +// Description: This function clears all I/O Trap SMI status. +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID IoTrapSmiClear (VOID) +{ + // Porting required + SET_MEM32_RCRB(RCRB_MMIO_TRSR, 0); // 0x1E00 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IoTrapSmiDetect +// +// Description: This function detects I/O Trap SMI event. +// +// Input: *IoTrapContext - Pointer to EFI_SMM_IO_TRAP_DISPATCH_CONTEXT +// +// Output: TRUE - I/O Trap SMI occured, the SMI context IoTrapContext +// should be updated according to the traped H/W +// information. +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN IoTrapSmiDetect ( + OUT EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *IoTrapContext ) +{ + UINT32 IoTrapStatus; + UINT32 Buffer32; + + // Porting required + IoTrapStatus = READ_MEM32_RCRB(RCRB_MMIO_TRSR) & 15; // 0x1E00 + + if (IoTrapStatus) { + + IoTrapContext->TrapRegIndex = 0; + + while (IoTrapStatus != 1) { + IoTrapStatus >>= 1; + IoTrapContext->TrapRegIndex++; + } + + Buffer32 = READ_MEM32_RCRB(RCRB_MMIO_TRCR); // 0x1E10 + IoTrapContext->TrapAddress = Buffer32 & 0xfffc; + IoTrapContext->TrapOpType = (Buffer32 & 0x1000000) ? WriteIoCycle : + ReadIoCycle; + if (IoTrapContext->TrapOpType == WriteIoCycle) + IoTrapContext->TrapData = READ_MEM32_RCRB(RCRB_MMIO_TWDR); + + return TRUE; + } + + return FALSE; +} + +//--------------------------------------------------------------------------- +// BIOS Write SMI Handler Porting hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: BiosWriteSmiEnable +// +// Description: This function enables BIOS write SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID BiosWriteSmiEnable (VOID) +{ + // Enable BIOSWE SMI if needed +//#### SET_PCI8_SB(SB_REG_BIOS_CNTL, 2); // 0xDC +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: BiosWriteSmiDisable +// +// Description: This function disables BIOS write SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID BiosWriteSmiDisable (VOID) +{ + // Disable BIOSWE SMI if possible. +//#### RESET_PCI8_SB(SB_REG_BIOS_CNTL, 2); // 0xDC +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: BiosWriteSmiClear +// +// Description: This function clears BIOS write SMI status and disables +// BIOS write function. +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID BiosWriteSmiClear (VOID) +{ + // Only clear BIOSWR_STS + WRITE_IO16_TCO(TCO_IOREG_STS1, 0x100); // 0x04 + // Disable BIOS Write + RESET_PCI8_SB(SB_REG_BIOS_CNTL, 1); // 0xDC +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: BiosWriteSmiDetect +// +// Description: This function detects BIOS write SMI event +// +// Input: None +// +// Output: TRUE - BIOS Write SMI occured, FALSE otherwise +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN BiosWriteSmiDetect (VOID) +{ + // Check BIOS Lock Enable first. + if ((READ_PCI8_SB(SB_REG_BIOS_CNTL) & 2) == 0) return FALSE; // 0xDC + + return (READ_IO16_TCO(TCO_IOREG_STS1) & 0x100) ? TRUE : FALSE; // 0x04 +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbSmiWorkaround +// +// Description: This hook is used for all south bridge workaround in SMI. +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SbSmiWorkaround (VOID) +{ + UINT8 DevNum8 = 0; + UINT32 BaseAddress; + UINT8 Offset; + UINT8 EndPort; + + // Sighting #3306438 + if ((READ_IO32_PM(ACPI_IOREG_SMI_EN) & 0x40000) == 0) return; + if ((READ_IO32_PM(ACPI_IOREG_SMI_STS) & 0x40000) == 0) return; + + // Clear the SMI status + WRITE_IO32_PM(ACPI_IOREG_SMI_STS, 0x40000); + + if (READ_PCI32_EHCI(EHCI_REG_VID) != 0xffffffff) + if ((READ_PCI32_EHCI(EHCI_REG_SPECIAL_SMI) & 0x10001) == 0x10001) + DevNum8 = EHCI_DEV; + + if (READ_PCI32_EHCI2(EHCI_REG_VID) != 0xffffffff) + if ((READ_PCI32_EHCI2(EHCI_REG_SPECIAL_SMI) & 0x10001) == 0x10001) + DevNum8 = EHCI2_DEV; + + if (DevNum8) { + // Clear HCReset SMI status + WRITE_PCI16(0, DevNum8, 0, EHCI_REG_SPECIAL_SMI + 2, 1); + + BaseAddress = READ_PCI32(0, DevNum8, 0, EHCI_REG_MBASE_ADDR); + BaseAddress &= 0xfffffff0; + EndPort = (DevNum8 == EHCI2_DEV) ? 0x78 : 0x80; + + for (Offset = 0x68; Offset <= EndPort; Offset += 4) { + // Ensure port ownerchip is not been claimed. + // Clear "Port Owner" bit, Port N Status and Control(PORTSC) [13], + // if it was set. + RESET_MEM8(BaseAddress + Offset + 1, 0x20); + + // Set "Port Test Control" bit, PORTSC[19:16], to '1h'. + RW_MEM8(BaseAddress + Offset + 2, 0x01, 0x0f); + + // Clear "Port Test Control" bit, PORTSC[19:16], to '0h'. + RESET_MEM8(BaseAddress + Offset + 2, 0x0f); + } + // Clear FC[5]; + RESET_PCI16(0, DevNum8, 0, EHCI_REG_IR2, 0x20); + } +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/Smm2/SmiHandlerGeneric2.c b/Chipset/SB/Smm2/SmiHandlerGeneric2.c new file mode 100644 index 0000000..d476784 --- /dev/null +++ b/Chipset/SB/Smm2/SmiHandlerGeneric2.c @@ -0,0 +1,1644 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher2/SmiHandlerGeneric2.c 7 8/17/14 11:55p Mirayang $ +// +// $Revision: 7 $ +// +// $Date: 8/17/14 11:55p $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher2/SmiHandlerGeneric2.c $ +// +// 7 8/17/14 11:55p Mirayang +// Fix Build Error when token "PI_0_9_CHILD_DISPATCHER_SUPPORT" = 0 +// +// 6 3/25/13 4:59a Wesleychen +// [TAG] None +// [Category] Improvement +// [Description] Refine GPI SMM2 related routines. +// [Files] SmiHandlerGeneric2.c; SmiHandlerPorting2.c; +// SmmChildDispatch2.h +// +// 5 3/15/13 2:25a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Support ULT GPISMI. +// [Files] SmiHandlerGeneric2.c +// +// 4 1/03/13 7:00a Scottyang +// [TAG] None +// [Category] Bug Fix +// [Severity] Important +// [Symptom] GPISMI cannot use. +// [RootCause] GPISMI2 will clear status before GPISMI. +// [Solution] GPISMI2 do not clear status when GPISMI has register. +// [Files] SmmChildDispatcher2.sdl; SmiHandlerGeneric2.c +// +// 3 8/30/12 9:50a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Implement EIP#73211 and EIP#79156 for OA 3.0 function. +// [Files] SmiHandlerGeneric2.c, SmmChildDispatch2Main.c +// +// 2 4/25/12 9:32a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Reprogram SMM ChildDispatcher drivers. +// [Files] SmiHandlerGeneric.c; SmiHandlerPorting.c; +// SmiHandlerGeneric2.c; SmmChildDispatch2Main.c; SmmChildDispatcher2.mak; +// SmmChildDispatcher2.sdl; SmmChildDispatch.h; SmmChildDispatchMain.c; +// SmmChildDispatchProtocol.c; SmmChildDispatcher.dxs; +// PchSmiDispatcher.sdl +// +// 1 2/08/12 8:28a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SmiHandlerGeneric2.c +// +// Description: This file contains implementation of generic SMI handler II +// functions +// +//<AMI_FHDR_END> +//************************************************************************* + +//--------------------------------------------------------------------------- +// Include(s) +//--------------------------------------------------------------------------- + +#include <Token.h> +#include <AmiDxeLib.h> +#include <AmiCspLib.h> +#include "SmmChildDispatch2.h" +#include <AmiSmm.h> + +//--------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//--------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//--------------------------------------------------------------------------- +// Variable and External Declaration(s) +//--------------------------------------------------------------------------- +// Variable Declaration(s) + +static UINT64 gCurrentInterval = 0xffffffffffffffff; +static UINT16 gEnabledUsbSmi = 0; +static UINT16 gActiveUsbSmi = 0; +static UINT32 gEnabledGpiSmi = 0; +static UINT32 gEnabledTcoSmi = 0; +static UINT32 gEnabledIoTrapSmi = 0; +static UINT32 gIoTrapWriteData = 0; + +BOOLEAN gIsLastState = FALSE; + +// GUID Definition(s) + +// Protocol Definition(s) + +// External Declaration(s) + +extern EFI_SMM_SYSTEM_TABLE2 *gSmst2; +extern SMM_CHILD_DISPATCHER2 Smm2Handler[]; +extern EFI_SMM_SMI_CONTEXT2 SmiContext; + +extern UINT64 gSupportedIntervals[]; + +// Function Definition(s) + +//--------------------------------------------------------------------------- + +//--------------------------------------------------------------------------- +// Software SMI II Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSwAddHandler2 +// +// Description: This function adds SW SMI II handler +// +// Input: *Context - Pointer to EFI_SMM_SW_REGISTER_CONTEXT +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSwAddHandler2 ( + IN VOID *Context ) +{ + if (Smm2Handler[EfiSmmSwSmi2].RegisteredCallbacks.Size == 1) SwSmiEnable(); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSwRemoveHandler2 +// +// Description: This function removes SW SMI II handler +// +// Input: *Context - Pointer to EFI_SMM_SW_REGISTER_CONTEXT +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSwRemoveHandler2 ( + IN VOID *Context ) +{ +#if (PI_0_9_CHILD_DISPATCHER_SUPPORT == 0) + if (Smm2Handler[EfiSmmSwSmi2].RegisteredCallbacks.Size == 1) SwSmiDisable(); +#endif + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSwVerifyContext2 +// +// Description: This function verifies SW SMI II context +// +// Input: *Context - Pointer to SMI II context +// +// Output: EFI_STATUS +// EFI_INVALID_PARAMETER - Given context is invalid +// EFI_SUCCESS - Context verified +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSwVerifyContext2 ( + IN VOID *Context ) +{ + HANDLER_LINK2 *Handler = (HANDLER_LINK2 *)\ + Smm2Handler[EfiSmmSwSmi2].RegisteredCallbacks.pHead; + EFI_SMM_SW_REGISTER_CONTEXT *SwContext; + EFI_SMM_SW_REGISTER_CONTEXT *RegisteredSwContext; + + SwContext = (EFI_SMM_SW_REGISTER_CONTEXT *)Context; + // First check if we already registered handler for this value + while (Handler != NULL) { + RegisteredSwContext = (EFI_SMM_SW_REGISTER_CONTEXT *)Handler->Context; + if(SwContext->SwSmiInputValue == RegisteredSwContext->SwSmiInputValue) + // Handler with this value already registered + return EFI_INVALID_PARAMETER; + + Handler = (HANDLER_LINK2 *)Handler->Link.pNext; + } + + // Second check if given value is extended SMI value, + // check the lowest byte + if ((SwContext->SwSmiInputValue & 0xff) == EXTENDED_SMI) + return EFI_SUCCESS; // Accept value of UINTN size + + // Third check if given value is in default range + return (SwContext->SwSmiInputValue > MAX_SW_SMI_INPUT_VALUE) ? \ + EFI_INVALID_PARAMETER : EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSwGetContext2 +// +// Description: This function verifies SW SMI II event and sets SW SMI II +// context +// +// Input: None +// +// Output: BOOLEAN +// TRUE - SW SMI occured, context saved +// FALSE - There was no SW SMI II +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SmmSwGetContext2 (VOID) +{ + UINT16 SwSmiNumber; + BOOLEAN SwSmiDetected; + + SwSmiDetected = SwSmiDetect( &SwSmiNumber ); + + if (SwSmiDetected) { + if(SwSmiNumber == EXTENDED_SMI) { + // Get the actual number from EAX register + SmiContext.SwContext.SwSmiInputValue = GetEAX(); + } else { + SmiContext.SwContext.SwSmiInputValue = SwSmiNumber; + } + } + + return SwSmiDetected; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSwDispatchSmi2 +// +// Description: This function dispatches SW SMI II event based on context +// +// Input: None +// +// Output: EFI_STATUS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSwDispatchSmi2 ( VOID ) +{ + EFI_STATUS Status = EFI_WARN_INTERRUPT_SOURCE_QUIESCED; + HANDLER_LINK2 *Handler; + EFI_SMM_SW_REGISTER_CONTEXT *SwRegisterContext; + + EFI_SMM_SW_CONTEXT SwContext; + UINTN SwContextSize; + UINT16 i; + EFI_GUID SwSmiCpuTriggerGuid = SW_SMI_CPU_TRIGGER_GUID; + SW_SMI_CPU_TRIGGER *SwSmiCpuTrigger; + UINTN Cpu = pSmst->CurrentlyExecutingCpu - 1; //default cpu # + + for (i = 0; i < pSmst->NumberOfTableEntries; i++) + { + if (guidcmp(&(pSmst->SmmConfigurationTable[i].VendorGuid), &SwSmiCpuTriggerGuid) == 0) + break; + } + + //If found table, check for the CPU that caused the software Smi. + if (i != pSmst->NumberOfTableEntries) + { + SwSmiCpuTrigger = pSmst->SmmConfigurationTable[i].VendorTable; + Cpu = SwSmiCpuTrigger->Cpu; + } + + SwContext.SwSmiCpuIndex = Cpu; + SwContext.CommandPort = IoRead8(SW_SMI_IO_ADDRESS); + SwContext.DataPort = IoRead8(SW_SMI_IO_ADDRESS + 1); + SwContextSize = sizeof(SwContext); + + Handler = \ + (HANDLER_LINK2 *)Smm2Handler[EfiSmmSwSmi2].RegisteredCallbacks.pHead; + while (Handler != NULL) { + SwRegisterContext = (EFI_SMM_SW_REGISTER_CONTEXT *)Handler->Context; + if(SwRegisterContext->SwSmiInputValue == SmiContext.SwContext.SwSmiInputValue) + Status = Handler->Callback(Handler, SwRegisterContext, &SwContext, &SwContextSize); + + Handler = (HANDLER_LINK2 *)Handler->Link.pNext; + } + +/*#if (CHILD_DISPATCHER_SUPPORT != 0) + if (!EFI_ERROR(Status)) +#endif*/ +if (Status != EFI_WARN_INTERRUPT_SOURCE_QUIESCED) + SwSmiClear(); + + return EFI_WARN_INTERRUPT_SOURCE_QUIESCED; +} + +//--------------------------------------------------------------------------- +// Sleep SMI II Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSxAddHandler2 +// +// Description: This function adds Sx SMI II handler +// +// Input: *Context - Pointer to EFI_SMM_SX_REGISTER_CONTEXT +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSxAddHandler2 ( + IN VOID *Context ) +{ +#if SLP_SMI_ENABLE_ON_REGISTER + if (Smm2Handler[EfiSmmSxSmi2].RegisteredCallbacks.Size == 1) SxSmiEnable(); +#endif + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSxRemoveHandler2 +// +// Description: This function removes Sx SMI II handler +// +// Input: *Context - Pointer to EFI_SMM_SX_REGISTER_CONTEXT +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSxRemoveHandler2 ( + IN VOID *Context ) +{ +#if SLP_SMI_ENABLE_ON_REGISTER && (PI_0_9_CHILD_DISPATCHER_SUPPORT == 0) + if (Smm2Handler[EfiSmmSxSmi2].RegisteredCallbacks.Size == 1) SxSmiDisable(); +#endif + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSxVerifyContext2 +// +// Description: This function verifies Sx SMI II context +// +// Input: *Context - Pointer to SMI II context +// +// Output: EFI_STATUS +// EFI_SUCCESS - Context verified +// EFI_INVALID_PARAMETER - Given context is invalid +// EFI_UNSUPPORTED - Context is not supported +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSxVerifyContext2 ( + IN VOID *Context ) +{ + EFI_SMM_SX_REGISTER_CONTEXT *SxContext; + + SxContext = (EFI_SMM_SX_REGISTER_CONTEXT *)Context; + if ((SxContext->Type >= EfiMaximumSleepType) || \ + (SxContext->Phase >= EfiMaximumPhase)) + return EFI_INVALID_PARAMETER; + + return ((SxContext->Phase) != SxEntry) ? EFI_UNSUPPORTED : EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSxGetContext2 +// +// Description: This function verifies Sx SMI II event and sets SX SMI II +// context +// +// Input: None +// +// Output: BOOLEAN +// TRUE - Sx SMI occured, context saved +// FALSE - There was no SX SMI II +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SmmSxGetContext2 (VOID) +{ + UINT16 SxSleepState; + BOOLEAN SxSmiDetected; + + SxSmiDetected = SxSmiDetect( &SxSleepState ); + + SmiContext.SxContext.Type = SxSleepState; + SmiContext.SxContext.Phase = SxEntry; + + return SxSmiDetected; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSxDispatchSmi2 +// +// Description: This function dispatches Sx SMI II event based on context +// +// Input: None +// +// Output: EFI_STATUS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSxDispatchSmi2 (VOID) +{ + EFI_STATUS Status = EFI_WARN_INTERRUPT_SOURCE_QUIESCED; + HANDLER_LINK2 *Handler; + EFI_SMM_SX_REGISTER_CONTEXT *SxContext; + + Handler = \ + (HANDLER_LINK2 *)Smm2Handler[EfiSmmSxSmi2].RegisteredCallbacks.pHead; + while (Handler != NULL) { + SxContext = (EFI_SMM_SX_REGISTER_CONTEXT *)Handler->Context; + + if ((SxContext->Type == SmiContext.SxContext.Type) && \ + (SxContext->Phase == SmiContext.SxContext.Phase)) + Status = Handler->Callback(Handler, SxContext, NULL, NULL); + + Handler = (HANDLER_LINK2 *)Handler->Link.pNext; + } + +#if (PI_0_9_CHILD_DISPATCHER_SUPPORT == 0) + SxSmiClear(); + + if (SmiContext.SxContext.Type == SxS0) return Status; + + PutToSleep( &(SmiContext.SxContext) ); + + // Control returns here on S1. + + SxSmiClear(); + + return Status; +#else + return EFI_WARN_INTERRUPT_SOURCE_QUIESCED; +#endif +} + +//--------------------------------------------------------------------------- +// Periodic timer SMI II Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmTimerAddHandler2 +// +// Description: This function adds Periodic timer SMI II handler +// +// Input: *Context - Pointer to EFI_SMM_PERIODIC_TIMER_REGISTER_CONTEXT +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmTimerAddHandler2 ( + IN VOID *Context ) +{ + EFI_SMM_PERIODIC_TIMER_EXT_REGISTER_CONTEXT *TimerContext; + + TimerContext = (EFI_SMM_PERIODIC_TIMER_EXT_REGISTER_CONTEXT *)Context; + + if (Smm2Handler[EfiSmmPeriodicTimerSmi2].RegisteredCallbacks.Size == 1) { + gCurrentInterval = TimerContext->OrgContext.SmiTickInterval; + TimerSetInterval2( TimerContext->OrgContext.SmiTickInterval ); + TimerSmiClear2(); + TimerSmiEnable2(); + return EFI_SUCCESS; + } + + if (gCurrentInterval > TimerContext->OrgContext.SmiTickInterval) { + gCurrentInterval = TimerContext->OrgContext.SmiTickInterval; + TimerSetInterval2( TimerContext->OrgContext.SmiTickInterval ); + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmTimerRemoveHandler2 +// +// Description: This function removes Periodic timer SMI II handler +// +// Input: *Context - Pointer to EFI_SMM_PERIODIC_TIMER_REGISTER_CONTEXT +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmTimerRemoveHandler2 ( + IN VOID *Context ) +{ + HANDLER_LINK2 *Handler = (HANDLER_LINK2 *)\ + Smm2Handler[EfiSmmPeriodicTimerSmi2].RegisteredCallbacks.pHead; + EFI_SMM_PERIODIC_TIMER_EXT_REGISTER_CONTEXT *TimerContext; + EFI_SMM_PERIODIC_TIMER_EXT_REGISTER_CONTEXT *CurrentTimerContext; + UINT64 Interval = 0xffffffffffffffff; + + UINT16 CurrentIntervalCounter = 0; + UINT64 *SupportedIntervals = gSupportedIntervals; + + if (Smm2Handler[EfiSmmPeriodicTimerSmi2].RegisteredCallbacks.Size == 1) { + gCurrentInterval = 0xffffffffffffffff; + TimerSmiDisable2(); + return EFI_SUCCESS; + } + + CurrentTimerContext = \ + (EFI_SMM_PERIODIC_TIMER_EXT_REGISTER_CONTEXT *)Context; + while (Handler != NULL) { + TimerContext = \ + (EFI_SMM_PERIODIC_TIMER_EXT_REGISTER_CONTEXT *)Handler->Context; + if (Interval > TimerContext->OrgContext.SmiTickInterval) + Interval = TimerContext->OrgContext.SmiTickInterval; + if (TimerContext->OrgContext.SmiTickInterval == \ + CurrentTimerContext->OrgContext.SmiTickInterval) + CurrentIntervalCounter++; + Handler = (HANDLER_LINK2 *)Handler->Link.pNext; + } + + if ((Interval == CurrentTimerContext->OrgContext.SmiTickInterval) && \ + (CurrentIntervalCounter == 1)) { + Interval = 0xffffffffffffffff; + while (*SupportedIntervals != 0) { + if (*SupportedIntervals != \ + CurrentTimerContext->OrgContext.SmiTickInterval) + if (*SupportedIntervals < Interval) + Interval = *SupportedIntervals; + SupportedIntervals++; + } + } + + // This means lowest rate timer no longer active + if (gCurrentInterval < Interval) { + gCurrentInterval = Interval; + TimerSetInterval2( Interval ); + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmTimerVerifyContext2 +// +// Description: This function verifies Periodic timer SMI II context +// +// Input: *Context - Pointer to SMI II context +// +// Output: EFI_STATUS +// EFI_INVALID_PARAMETER - Given context is invalid +// EFI_SUCCESS - Context verified +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmTimerVerifyContext2 ( + IN VOID *Context ) +{ + EFI_SMM_PERIODIC_TIMER_EXT_REGISTER_CONTEXT *TimerContext; + UINT64 *Interval = gSupportedIntervals; + + TimerContext = (EFI_SMM_PERIODIC_TIMER_EXT_REGISTER_CONTEXT *)Context; + while (*Interval != 0) { + if (*Interval == TimerContext->OrgContext.SmiTickInterval) + return EFI_SUCCESS; + Interval++; + } + + return EFI_INVALID_PARAMETER; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmTimerGetContext2 +// +// Description: This function verifies Periodic timer SMI II event and sets +// Periodic timer SMI II context +// +// Input: None +// +// Output: BOOLEAN +// TRUE - Periodic timer SMI occured, context saved +// FALSE - There was no Periodic timer SMI +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SmmTimerGetContext2 (VOID) +{ + UINT16 TimerType; + BOOLEAN TimerSmiDetected; + + TimerSmiDetected = TimerSmiDetect2( &TimerType ); + SmiContext.TimerContext.OrgContext.SmiTickInterval = gCurrentInterval; + + return TimerSmiDetected; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmTimerDispatchSmi2 +// +// Description: This function dispatches Periodic timer SMI event based on +// context +// +// Input: None +// +// Output: EFI_STATUS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmTimerDispatchSmi2 (VOID) +{ + EFI_STATUS Status = EFI_WARN_INTERRUPT_SOURCE_QUIESCED; + HANDLER_LINK2 *Handler = (HANDLER_LINK2 *)\ + Smm2Handler[EfiSmmPeriodicTimerSmi2].RegisteredCallbacks.pHead; + EFI_SMM_PERIODIC_TIMER_EXT_REGISTER_CONTEXT *TimerContext; + + while (Handler != NULL) { + TimerContext = \ + (EFI_SMM_PERIODIC_TIMER_EXT_REGISTER_CONTEXT *)Handler->Context; + + TimerContext->ElapsedTime += \ + SmiContext.TimerContext.OrgContext.SmiTickInterval; + if (TimerContext->ElapsedTime >= TimerContext->OrgContext.Period){ + Status = Handler->Callback(Handler, TimerContext, NULL, NULL); + TimerContext->ElapsedTime = 0; + } + Handler = (HANDLER_LINK2 *)Handler->Link.pNext; + } + +#if (PI_0_9_CHILD_DISPATCHER_SUPPORT == 0) + TimerSmiClear2(); + return Status; +#else + return EFI_WARN_INTERRUPT_SOURCE_QUIESCED; +#endif + +} + +//--------------------------------------------------------------------------- +// USB SMI II Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmUsbAddHandler2 +// +// Description: This function adds USB SMI II handler +// +// Input: *Context - Pointer to EFI_SMM_USB_REGISTER_CONTEXT +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmUsbAddHandler2 ( + IN VOID *Context +) +{ + EFI_STATUS Status; + EFI_SMM_USB_REGISTER_CONTEXT *UsbContext; + UINT16 ControllerType; + VOID *NewDp; + UINTN Length; + + UsbContext = (EFI_SMM_USB_REGISTER_CONTEXT *)Context; + + // Save USB device path protocol into SMM memory + Length = DPLength( UsbContext->Device ); + Status = gSmst2->SmmAllocatePool( 0, Length, &NewDp ); + if (EFI_ERROR(Status)) return Status; + MemCpy( NewDp, UsbContext->Device, Length ); + UsbContext->Device = (EFI_DEVICE_PATH_PROTOCOL *)NewDp; + + ControllerType = GetControllerType( UsbContext->Device ); + if((ControllerType & gEnabledUsbSmi) == 0) { + gEnabledUsbSmi |= ControllerType; + UsbSmiSet( gEnabledUsbSmi ); + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmUsbRemoveHandler2 +// +// Description: This function removes USB SMI II handler +// +// Input: *Context - Pointer to EFI_SMM_USB_REGISTER_CONTEXT +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmUsbRemoveHandler2 ( + IN VOID *Context ) +{ + HANDLER_LINK2 *Handler = (HANDLER_LINK2 *)\ + Smm2Handler[EfiSmmUsbSmi2].RegisteredCallbacks.pHead; + EFI_SMM_USB_REGISTER_CONTEXT *UsbContext; + UINT16 ControllerType = 0; + + UsbContext = (EFI_SMM_USB_REGISTER_CONTEXT *)Context; + + gSmst2->SmmFreePool( UsbContext->Device ); + + if (Smm2Handler[EfiSmmUsbSmi2].RegisteredCallbacks.Size == 1) { + gEnabledUsbSmi = 0; + UsbSmiSet( gEnabledUsbSmi ); + return EFI_SUCCESS; + } + + while (Handler != NULL) { + UsbContext = (EFI_SMM_USB_REGISTER_CONTEXT *)Handler->Context; + ControllerType |= GetControllerType( UsbContext->Device ); + Handler = (HANDLER_LINK2 *)Handler->Link.pNext; + } + + if (ControllerType != gEnabledUsbSmi) { + gEnabledUsbSmi = ControllerType; + UsbSmiSet( gEnabledUsbSmi ); + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmUsbVerifyContext2 +// +// Description: This function verifies USB SMI II context +// +// Input: *Context - Pointer to SMI II context +// +// Output: EFI_STATUS +// EFI_INVALID_PARAMETER - Given context is invalid +// EFI_SUCCESS - Context verified +// EFI_UNSUPPORTED - Context is not supported +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmUsbVerifyContext2 ( + IN VOID *Context ) +{ + EFI_SMM_USB_REGISTER_CONTEXT *UsbContext; + UINT16 ControllerType; + + UsbContext = (EFI_SMM_USB_REGISTER_CONTEXT *)Context; + ControllerType = GetControllerType( UsbContext->Device ); + if (((ControllerType & 7) == 0) || (UsbContext->Type > UsbWake)) + return EFI_INVALID_PARAMETER; + + return ((UsbContext->Type) > UsbLegacy) ? EFI_UNSUPPORTED : EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmUsbGetContext2 +// +// Description: This function verifies USB SMI II event and sets USB SMI II +// context +// +// Input: None +// +// Output: BOOLEAN +// TRUE - USB SMI occured, context saved +// FALSE - There was no USB SMI +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SmmUsbGetContext2 (VOID) +{ + BOOLEAN UsbSmiDetected; + + UsbSmiDetected = UsbSmiDetect( &gActiveUsbSmi ); + SmiContext.UsbContext.Type = UsbLegacy; + + return UsbSmiDetected; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmUsbDispatchSmi2 +// +// Description: This function dispatches USB SMI II event based on context +// +// Input: None +// +// Output: EFI_STATUS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmUsbDispatchSmi2 (VOID) +{ + EFI_STATUS Status = EFI_WARN_INTERRUPT_SOURCE_QUIESCED; + HANDLER_LINK2 *Handler = (HANDLER_LINK2 *)\ + Smm2Handler[EfiSmmUsbSmi2].RegisteredCallbacks.pHead; + EFI_SMM_USB_REGISTER_CONTEXT *UsbContext; + UINT16 ControllerType; + + while (Handler != NULL) { + UsbContext = (EFI_SMM_USB_REGISTER_CONTEXT *)Handler->Context; + ControllerType = GetControllerType( UsbContext->Device ); + + if (((ControllerType & gActiveUsbSmi) != 0) && \ + (UsbContext->Type == SmiContext.UsbContext.Type)) + Status = Handler->Callback(Handler, UsbContext, NULL, NULL); + + Handler = (HANDLER_LINK2 *)Handler->Link.pNext; + } + +#if (PI_0_9_CHILD_DISPATCHER_SUPPORT == 0) + UsbSmiClear( gActiveUsbSmi ); + gActiveUsbSmi = 0; + return Status; +#else + gActiveUsbSmi = 0; + return EFI_WARN_INTERRUPT_SOURCE_QUIESCED; +#endif + +} + +//--------------------------------------------------------------------------- +// GPI SMI II Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmGpiAddHandler2 +// +// Description: This function adds GPI SMI II handler +// +// Input: VOID *Context - Pointer to EFI_SMM_GPI_REGISTER_CONTEXT +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmGpiAddHandler2 ( + IN VOID *Context ) +{ + EFI_SMM_GPI_REGISTER_CONTEXT *GpiContext; + UINT32 GpiBitMap = 0; + + GpiContext = (EFI_SMM_GPI_REGISTER_CONTEXT *)Context; + + GpiBitMap = ConvertGpi (GpiContext->GpiNum); + + if ((GpiBitMap & gEnabledGpiSmi) == 0) { + gEnabledGpiSmi |= GpiBitMap; + GpiSmiSet( GpiBitMap ); + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmGpiRemoveHandler2 +// +// Description: This function removes GPI SMI II handler +// +// Input: *Context - Pointer to EFI_SMM_GPI_REGISTER_CONTEXT +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmGpiRemoveHandler2 ( + IN VOID *Context ) +{ + EFI_SMM_GPI_REGISTER_CONTEXT *GpiContext; + UINT32 GpiBitMap = 0; + + GpiContext = (EFI_SMM_GPI_REGISTER_CONTEXT *)Context; + + GpiBitMap = ConvertGpi (GpiContext->GpiNum); + + gEnabledGpiSmi &= ~(GpiBitMap); + + GpiSmiReset( GpiBitMap ); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmGpiVerifyContext2 +// +// Description: This function verifies GPI SMI II context +// +// Input: *Context - Pointer to SMI II context +// +// Output: EFI_STATUS +// EFI_INVALID_PARAMETER - Given context is invalid +// EFI_SUCCESS - Context verified +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmGpiVerifyContext2 ( + IN VOID *Context ) +{ + EFI_SMM_GPI_REGISTER_CONTEXT *GpiContext; + UINT32 GpiBitMap = 0; + + GpiContext = (EFI_SMM_GPI_REGISTER_CONTEXT *)Context; + + GpiBitMap = ConvertGpi (GpiContext->GpiNum); + + if ((GpiBitMap & SUPPORTED_GPIS2) == 0) + return EFI_INVALID_PARAMETER; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmGpiGetContext2 +// +// Description: This function verifies GPI SMI II event and sets GPI SMI II +// context +// +// Input: None +// +// Output: BOOLEAN +// TRUE - GPI SMI occured, context saved +// FALSE - There was no GPI SMI +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SmmGpiGetContext2 (VOID) +{ + BOOLEAN GpiSmiDetected; + UINT32 GpiSmiNum; + + GpiSmiDetected = GpiSmiDetect( &GpiSmiNum ); + SmiContext.GpiContext.GpiNum = GpiSmiNum; + + return GpiSmiDetected; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmGpiDispatchSmi2 +// +// Description: This function dispatches GPI SMI event based on context +// +// Input: None +// +// Output: EFI_STATUS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmGpiDispatchSmi2 (VOID) +{ + EFI_STATUS Status = EFI_WARN_INTERRUPT_SOURCE_QUIESCED; + HANDLER_LINK2 *Handler = (HANDLER_LINK2 *)\ + Smm2Handler[EfiSmmGpiSmi2].RegisteredCallbacks.pHead; + EFI_SMM_GPI_REGISTER_CONTEXT *GpiContext; + UINT32 GpiBitMap = 0; + BOOLEAN GpiSmiServiced = FALSE; + + while (Handler != NULL) { + GpiContext = (EFI_SMM_GPI_REGISTER_CONTEXT *)Handler->Context; + + GpiBitMap = ConvertGpi (GpiContext->GpiNum); + + GpiSmiServiced = FALSE; + if ((SmiContext.GpiContext.GpiNum & GpiBitMap) != 0) { + Status = Handler->Callback( Handler, GpiContext, NULL, NULL ); + GpiSmiServiced = TRUE; + } + + Handler = (HANDLER_LINK2 *)Handler->Link.pNext; + } + + if (GpiSmiServiced) + GpiSmiClear( (UINT16)SmiContext.GpiContext.GpiNum ); + +#if (PI_0_9_CHILD_DISPATCHER_SUPPORT == 0) + return Status; +#else + return EFI_WARN_INTERRUPT_SOURCE_QUIESCED; +#endif + +} + +//--------------------------------------------------------------------------- +// Standby button SMI II Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSButtonAddHandler2 +// +// Description: This function adds Standby button SMI II handler +// +// Input: *Context - Pointer to EFI_SMM_STANDBY_BUTTON_REGISTER_CONTEXT +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSButtonAddHandler2 ( + IN VOID *Context ) +{ + if (Smm2Handler[EfiSmmStandbyButtonSmi2].RegisteredCallbacks.Size == 1) + SButtonSmiEnable(); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSButtonRemoveHandler2 +// +// Description: This function removes Standby button SMI II handler +// +// Input: *Context - Pointer to EFI_SMM_STANDBY_BUTTON_REGISTER_CONTEXT +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSButtonRemoveHandler2 ( + IN VOID *Context ) +{ + if (Smm2Handler[EfiSmmStandbyButtonSmi2].RegisteredCallbacks.Size == 1) + SButtonSmiDisable(); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSButtonVerifyContext2 +// +// Description: This function verifies Standby button SMI II context +// +// Input: VOID *Context - Pointer to SMI II context +// +// Output: EFI_STATUS +// EFI_INVALID_PARAMETER - Given context is invalid +// EFI_SUCCESS - Context verified +// EFI_UNSUPPORTED - Context is not supported +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSButtonVerifyContext2 ( + IN VOID *Context ) +{ + EFI_SMM_STANDBY_BUTTON_REGISTER_CONTEXT *SButtonContext; + + SButtonContext = (EFI_SMM_STANDBY_BUTTON_REGISTER_CONTEXT *)Context; + if (SButtonContext->Phase >= EfiStandbyButtonMax) + return EFI_INVALID_PARAMETER; + + return (SButtonContext->Phase > EfiStandbyButtonEntry) \ + ? EFI_UNSUPPORTED : EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSButtonGetContext2 +// +// Description: This function verifies Standby button SMI II event and sets +// Standby button SMI II context +// +// Input: None +// +// Output: BOOLEAN +// TRUE - Standby button SMI occured, context saved +// FALSE - There was no Standby button SMI +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SmmSButtonGetContext2 (VOID) +{ + UINT16 Dummy = 0; + BOOLEAN SButtonSmiDetected; + + SButtonSmiDetected = SButtonSmiDetect( &Dummy ); + + SmiContext.SBtnContext.Phase = EfiStandbyButtonEntry; + + return SButtonSmiDetected; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmSButtonDispatchSmi2 +// +// Description: This function dispatches Standby button SMI II event based on +// context +// +// Input: None +// +// Output: EFI_STATUS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmSButtonDispatchSmi2 (VOID) +{ + EFI_STATUS Status = EFI_WARN_INTERRUPT_SOURCE_QUIESCED; + HANDLER_LINK2 *Handler = (HANDLER_LINK2 *)\ + Smm2Handler[EfiSmmStandbyButtonSmi2].RegisteredCallbacks.pHead; + EFI_SMM_STANDBY_BUTTON_REGISTER_CONTEXT *SButtonContext; + + while (Handler != NULL) { + SButtonContext = \ + (EFI_SMM_STANDBY_BUTTON_REGISTER_CONTEXT *)Handler->Context; + + if (SButtonContext->Phase == SmiContext.SBtnContext.Phase) + Status = Handler->Callback( Handler, SButtonContext, NULL, NULL ); + + Handler = (HANDLER_LINK2 *)Handler->Link.pNext; + } + +#if (PI_0_9_CHILD_DISPATCHER_SUPPORT == 0) + SButtonSmiClear(); + + return Status; +#else + return EFI_WARN_INTERRUPT_SOURCE_QUIESCED; +#endif +} + +//--------------------------------------------------------------------------- +// Power button SMI II Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmPButtonAddHandler2 +// +// Description: This function adds Power button SMI II handler +// +// Input: *Context - pointer to EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmPButtonAddHandler2 ( + IN VOID *Context ) +{ + if (Smm2Handler[EfiSmmPowerButtonSmi2].RegisteredCallbacks.Size == 1) + PButtonSmiEnable(); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmPButtonRemoveHandler2 +// +// Description: This function removes Power button SMI II handler +// +// Input: *Context - Pointer to EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT +// +// Output: EFI_SUCCESS; +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmPButtonRemoveHandler2 ( + IN VOID *Context ) +{ + if (Smm2Handler[EfiSmmPowerButtonSmi2].RegisteredCallbacks.Size == 1) + PButtonSmiDisable(); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmPButtonVerifyContext2 +// +// Description: This function verifies Power button SMI II context +// +// Input: *Context - Pointer to SMI II context +// +// Output: EFI_STATUS +// EFI_INVALID_PARAMETER - Given context is invalid +// EFI_SUCCESS - Context verified +// EFI_UNSUPPORTED - Context is not supported +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmPButtonVerifyContext2 ( + IN VOID *Context ) +{ + EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT *PButtonContext; + + PButtonContext = (EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT *)Context; + if (PButtonContext->Phase >= EfiPowerButtonMax) + return EFI_INVALID_PARAMETER; + + return (PButtonContext->Phase > EfiPowerButtonEntry) ? \ + EFI_UNSUPPORTED : EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmPButtonGetContext2 +// +// Description: This function verifies Power button SMI II event and sets +// Power button SMI II context +// +// Input: None +// +// Output: BOOLEAN +// TRUE - Power button SMI occured, context saved +// FALSE - There was no Power button SMI +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SmmPButtonGetContext2 (VOID) +{ + UINT16 Dummy = 0; + BOOLEAN PButtonSmiDetected; + + PButtonSmiDetected = PButtonSmiDetect( &Dummy ); + + SmiContext.PBtnContext.Phase = EfiPowerButtonEntry; + + return PButtonSmiDetected; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmPButtonDispatchSmi2 +// +// Description: This function dispatches Power button SMI II event based on +// context +// +// Input: None +// +// Output: EFI_STATUS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmPButtonDispatchSmi2 (VOID) +{ + EFI_STATUS Status = EFI_WARN_INTERRUPT_SOURCE_QUIESCED; + HANDLER_LINK2 *Handler = (HANDLER_LINK2 *)\ + Smm2Handler[EfiSmmPowerButtonSmi2].RegisteredCallbacks.pHead; + EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT *PButtonContext; + + while (Handler != NULL) { + PButtonContext = \ + (EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT *)Handler->Context; + + if (PButtonContext->Phase == SmiContext.PBtnContext.Phase) + Status = Handler->Callback( Handler, PButtonContext, NULL, NULL ); + + Handler = (HANDLER_LINK2 *)Handler->Link.pNext; + } + +#if (PI_0_9_CHILD_DISPATCHER_SUPPORT == 0) + PButtonSmiClear(); + SBLib_Shutdown(); + + return Status; +#else + return EFI_WARN_INTERRUPT_SOURCE_QUIESCED; +#endif +} + +//--------------------------------------------------------------------------- +// I/O Trap SMI II Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmIoTrapAddHandler2 +// +// Description: This function adds I/O Trap SMI II handler +// +// Input: *Context - Pointer to EFI_SMM_IO_TRAP_REGISTER_CONTEXT +// +// Output: EFI_SUCCESS - The context has been registerd successfully. +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmIoTrapAddHandler2 ( + IN VOID *Context ) +{ + HANDLER_LINK2 *Handler; + EFI_SMM_IO_TRAP_REGISTER_CONTEXT *RegedContext; + EFI_SMM_IO_TRAP_REGISTER_CONTEXT *IoTrapContext; + UINT32 TrapRegIndex = 0; + UINT32 i = 0; + + IoTrapContext = (EFI_SMM_IO_TRAP_REGISTER_CONTEXT *)Context; + + Handler = \ + (HANDLER_LINK2 *)Smm2Handler[EfiSmmIoTrapSmi2].RegisteredCallbacks.pHead; + + while (Handler != NULL) { + RegedContext = (EFI_SMM_IO_TRAP_REGISTER_CONTEXT *)Handler->Context; + if ((RegedContext->Address == IoTrapContext->Address) && \ + (RegedContext->Type == IoTrapContext->Type) && \ + (RegedContext->Length == IoTrapContext->Length)) { + i++; + } + Handler = (HANDLER_LINK2 *)Handler->Link.pNext; + } + + if (i > 1) return EFI_SUCCESS; + + IoTrapSmiSet2( IoTrapContext, &TrapRegIndex ); + + gEnabledIoTrapSmi |= (UINT32)(1 << TrapRegIndex); + + if (Smm2Handler[EfiSmmIoTrapSmi2].RegisteredCallbacks.Size == 1) + IoTrapSmiEnable2(); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmIoTrapRemoveHandler2 +// +// Description: This function removes I/O Trap SMI II handler +// +// Input: *Context - Pointer to EFI_SMM_IO_TRAP_REGISTER_CONTEXT +// +// Output: EFI_SUCCESS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmIoTrapRemoveHandler2 ( + IN VOID *Context ) +{ + HANDLER_LINK2 *Handler; + EFI_SMM_IO_TRAP_REGISTER_CONTEXT *RegedContext; + EFI_SMM_IO_TRAP_REGISTER_CONTEXT *RemoveContext; + UINT32 i = 0; + UINT32 TrapRegIndex = 0; + + RemoveContext = (EFI_SMM_IO_TRAP_REGISTER_CONTEXT *)Context; + + Handler = \ + (HANDLER_LINK2 *)Smm2Handler[EfiSmmIoTrapSmi2].RegisteredCallbacks.pHead; + + while (Handler != NULL) { + RegedContext = (EFI_SMM_IO_TRAP_REGISTER_CONTEXT *)Handler->Context; + if ((RegedContext->Address == RemoveContext->Address) && \ + (RegedContext->Type == RemoveContext->Type) && \ + (RegedContext->Length == RemoveContext->Length)) i++; + Handler = (HANDLER_LINK2 *)Handler->Link.pNext; + } + + if (i > 1) return EFI_SUCCESS; + + IoTrapSmiReset2( Context, &TrapRegIndex ); + + gEnabledIoTrapSmi &= ~(1 << TrapRegIndex); + + if (gEnabledIoTrapSmi == 0) IoTrapSmiDisable2(); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmIoTrapVerifyContext2 +// +// Description: This function verifies I/O Trap SMI II context +// +// Input: *Context - Pointer to SMI II context +// +// Output: EFI_STATUS +// EFI_SUCCESS - Context verified +// EFI_INVALID_PARAMETER - Given context is invalid +// EFI_UNSUPPORTED - Context is not supported +// EFI_OUT_OF_RESOURCES - There is no I/O Trap register +// available +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmIoTrapVerifyContext2 ( + IN VOID *Context ) +{ + HANDLER_LINK2 *Handler; + EFI_SMM_IO_TRAP_REGISTER_CONTEXT *RegedContext; + EFI_SMM_IO_TRAP_REGISTER_CONTEXT *IoTrapContext; + + Handler = \ + (HANDLER_LINK2 *)Smm2Handler[EfiSmmIoTrapSmi2].RegisteredCallbacks.pHead; + + IoTrapContext = (EFI_SMM_IO_TRAP_REGISTER_CONTEXT *)Context; + + while (Handler != NULL) { + RegedContext = (EFI_SMM_IO_TRAP_REGISTER_CONTEXT *)Handler->Context; + if ((RegedContext->Address == IoTrapContext->Address) && \ + (RegedContext->Type == IoTrapContext->Type)) { + if ( IoTrapContext->Length > MAX_SUPPORTED_IOTRAP_LENGTH) + return EFI_INVALID_PARAMETER; + return EFI_SUCCESS; + } + Handler = (HANDLER_LINK2 *)Handler->Link.pNext; + } + + if (gEnabledIoTrapSmi >= ((1 << MAX_SUPPORTED_IOTRAP_REGS) - 1)) + return EFI_OUT_OF_RESOURCES; + + if (IoTrapContext->Length > MAX_SUPPORTED_IOTRAP_LENGTH) + return EFI_INVALID_PARAMETER; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmIoTrapGetContext2 +// +// Description: This function verifies I/O Trap SMI II event and sets +// I/O Trap SMI II context. +// +// Input: None +// +// Output: BOOLEAN +// TRUE - I/O Trap SMI occured, context saved +// FALSE - There was no I/O Trap SMI +// The global variable gIoTrapWriteData will save the data from +// I/O write cycle. +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SmmIoTrapGetContext2 (VOID) +{ + return IoTrapSmiDetect2( &SmiContext.IoTrapContext, &gIoTrapWriteData ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmIoTrapDispatchSmi2 +// +// Description: This function dispatches I/O Trap SMI II event based on +// context. +// +// Input: None +// +// Output: EFI_STATUS +// +// Notes: GENERALLY NO PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmIoTrapDispatchSmi2 (VOID) +{ + EFI_STATUS Status = EFI_WARN_INTERRUPT_SOURCE_QUIESCED; + HANDLER_LINK2 *Handler; + EFI_SMM_IO_TRAP_REGISTER_CONTEXT *IoTrapContext; + volatile UINT16 MaxAddress; + + Handler = \ + (HANDLER_LINK2 *)Smm2Handler[EfiSmmIoTrapSmi2].RegisteredCallbacks.pHead; + while (Handler != NULL) { + IoTrapContext = (EFI_SMM_IO_TRAP_REGISTER_CONTEXT *)Handler->Context; + MaxAddress = IoTrapContext->Address + IoTrapContext->Length; + if ((IoTrapContext->Address <= SmiContext.IoTrapContext.Address) && \ + (MaxAddress > SmiContext.IoTrapContext.Address)) { + if ((IoTrapContext->Type == ReadWriteTrap) || \ + (IoTrapContext->Type == SmiContext.IoTrapContext.Type)) { + Status = Handler->Callback( \ + Handler, \ + (EFI_SMM_IO_TRAP_CONTEXT*)&gIoTrapWriteData, \ + NULL, \ + NULL ); + } + } + Handler = (HANDLER_LINK2 *)Handler->Link.pNext; + } +#if (PI_0_9_CHILD_DISPATCHER_SUPPORT == 0) + if (Status != EFI_WARN_INTERRUPT_SOURCE_QUIESCED) IoTrapSmiClear2(); + return Status; +#else + return EFI_WARN_INTERRUPT_SOURCE_QUIESCED; +#endif +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/Smm2/SmiHandlerPorting2.c b/Chipset/SB/Smm2/SmiHandlerPorting2.c new file mode 100644 index 0000000..12fb095 --- /dev/null +++ b/Chipset/SB/Smm2/SmiHandlerPorting2.c @@ -0,0 +1,1565 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher2/SmiHandlerPorting2.c 9 5/22/15 9:13a Dennisliu $ +// +// $Revision: 9 $ +// +// $Date: 5/22/15 9:13a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher2/SmiHandlerPorting2.c $ +// +// 9 5/22/15 9:13a Dennisliu +// [TAG] EIP215945 +// [Category] Improvement +// [Description] [SharkBay][PCH] Executing code outside TSEG check in +// SMM +// +// 8 3/25/13 5:00a Wesleychen +// [TAG] None +// [Category] Improvement +// [Description] Refine GPI SMM2 related routines. +// [Files] SmiHandlerGeneric2.c; SmiHandlerPorting2.c; +// SmmChildDispatch2.h +// +// 7 3/19/13 8:21a Scottyang +// [TAG] EIP118158 +// [Category] Improvement +// [Description] Correct SBLib_CmosRead () offset. +// [Files] SmiHandlerPorting2.c, SBDxe.c, SBGeneric.c, SBSmm.c, +// SmiHandlerPorting.c +// +// 6 11/06/12 8:11a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Reduce function "GetPchSeries()". +// [Files] SBPEI.c, SBDxe.c, SmiHandlerPorting.c, SmiHandlerPorting2.c +// +// 5 10/19/12 2:52a Scottyang +// [TAG] EIP93461 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] System halt when AFUDOS is running with /N /ME command. +// [RootCause] An unexpected BIOSWR_STS is set, it causes BIOS stuck +// at SMM dispatcher. +// [Solution] Clear BIOSWR_STS if BIOS Lock Enable is not set. +// [Files] SmiHandlerPorting2.c; SmmChildDispatch2Main.c +// SmmChildDispatcher2.sdl; SmmChildDispatch2.h +// SB\SBGeneric.c +// +// 4 9/26/12 3:56a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update for PCH LP GPIO compatible. +// [Files] SB.sdl, SB.H, AcpiModeEnable.c, AcpiModeEnable.sdl, +// SBDxe.c, SBGeneric.c, SBPEI.c, SBSMI.c, SleepSmi.c, +// SmiHandlerPorting.c, SmiHandlerPorting2.c +// +// 3 7/27/12 6:16a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update to support ULT Platform. +// [Files] SB.H, SB.mak, SB.sdl, SB.sd, SBSetup.c, +// AcpiModeEnable.c, SBDxe.c, SBPEI.c, SBSMI.c, SleepSmi.c, +// SmiHandlerPorting.c, SmiHandlerPorting2.c, SBPPI.h, Pch.sdl +// +// 2 4/25/12 9:30a Victortu +// [TAG] EIP73033 +// [Category] Improvement +// [Description] 'PciDevicePath' used in GetControllerType(), +// conditionally not set. +// [Files] SmiHandlerPorting.c; SmiHandlerPorting2.c +// +// 1 2/08/12 8:28a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SmiHandlerPorting2.c +// +// Description: This file contains SMM Child Dispatcher II porting +// functions +// +//<AMI_FHDR_END> +//************************************************************************* + +//--------------------------------------------------------------------------- +// Include(s) +//--------------------------------------------------------------------------- + +#include <Token.h> +#include <AmiDxeLib.h> +#include <AmiCspLib.h> +#include <AmiSmm.h> +#include <Protocol\SmmCpu.h> +#include "SmmChildDispatch2.h" + +//--------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//--------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//--------------------------------------------------------------------------- +// Variable and External Declaration(s) +//--------------------------------------------------------------------------- +// Variable Declaration(s) + +UINT64 gSupportedIntervals[] = { + // Porting required - put all available intervals here (in 100Nanoseconds) +#if SWSMI_TIMER_INSTEAD +// [ EIP215677 ] +// 15000, // 1.5ms +// 160000, // 16 ms +// 320000, // 32 ms +// 640000, // 64 ms + 640000, // 64 ms + 320000, // 32 ms + 160000, // 16 ms + 15000, // 1.5ms +#else + 600000000, // 60 Seconds + 320000000, // 32 Seconds + 160000000, // 16 Seconds + 80000000, // 8 Seconds +#endif + + // Terminator record + 0 +}; + +// GUID Definition(s) + +// Protocol Definition(s) + +// External Declaration(s) + +extern EFI_SMM_SYSTEM_TABLE2 *gSmst2; +extern EFI_SMM_CPU_PROTOCOL *gEfiSmmCpuProtocol; + +// Function Definition(s) + +//--------------------------------------------------------------------------- + +//--------------------------------------------------------------------------- +// All purpose SMI Porting hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IsAcpi +// +// Description: This function determines if the system is in ACPI mode. +// +// Input: None +// +// Output: BOOLEAN +// TRUE - It is in ACPI mode +// FALSE - It is not in ACPI mode +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN IsAcpi (VOID) +{ + return (READ_IO16_PM(ACPI_IOREG_PM1_CNTL) & 1) ? TRUE : FALSE; // 0x04 +}; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IsMe +// +// Description: This function checks whether the specific SMI event is raised +// +// Input: CheckBitNo - The bit number for the specific SMI. +// +// Output: BOOLEAN +// TRUE - It is the specific SMI event +// FALSE - It is not the specific SMI event +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN IsMe ( + IN UINT8 CheckBitNo ) +{ + volatile UINT32 Buffer32 = READ_IO32_PM(ACPI_IOREG_SMI_EN); // 0x30 + + Buffer32 &= READ_IO32_PM(ACPI_IOREG_SMI_STS); // 0x34 + return (Buffer32 & (UINT32)(1 << CheckBitNo)) ? TRUE : FALSE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ClearAllSmi +// +// Description: This function clears all SMI's and issues an EOS (End of SMI). +// +// Input: None +// +// Output: None +// +// Notes: If you are porting INTEL chipset and have to support SWSMI +// Timer SMI, you must be unable to clear the SWSMI status in +// this routine. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID ClearAllSmi (VOID) +{ + // Porting Required. Program to clear ALL SMI status bit + if ( !IsAcpi() ) { + if (READ_IO16_PM(ACPI_IOREG_PM1_EN) & 0x400) + if (READ_IO16_PM(ACPI_IOREG_PM1_STS) & 0x400) + SBLib_CmosRead(0x0C); + WRITE_IO16_PM(ACPI_IOREG_PM1_STS, 0xcc31); // 0x00 + if (GetPchSeries() == PchLp) { + WRITE_IO32_PM(ACPI_PCHLP_IOREG_GPE0_STS+0x0c, 0xffffffff); // 0x8C + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_ALTGP_SMI_STS, 0xffffffff); // 0x50 + } else { + WRITE_IO32_PM(ACPI_IOREG_GPE0_STS, 0xffffffff); // 0x20 + WRITE_IO32_PM(ACPI_IOREG_GPE0_STS+4, 0xffffffff); // 0x24 + WRITE_IO16_PM(ACPI_IOREG_ALTGP_SMI_STS, 0xffff); // 0x3A + } + WRITE_IO16_PM(ACPI_IOREG_DEVACT_STS, 0xffff); // 0x44 + WRITE_IO16_TCO(TCO_IOREG_STS1, 0xffff); // 0x04 + WRITE_IO16_TCO(TCO_IOREG_STS2, 0xfffe); // 0x06 (Except Intruder Det) + WRITE_IO32_PM(ACPI_IOREG_SMI_STS, 0xffffffbf); // 0x34 (Except SWSMI) + if ((READ_IO16_TCO(TCO_IOREG_CNT1) & 0x300) == 0x300) { // 0x08 + SET_IO16_TCO(TCO_IOREG_CNT1, 0x100); // Clear NMI_NOW if needed. + } + } + // EOS + SET_IO8_PM(ACPI_IOREG_SMI_EN, 0x02); // 0x30 + if ((READ_IO8_PM(ACPI_IOREG_SMI_EN) & 0x02) == 0) { + // Reset GBL_SMI_EN + RESET_IO8_PM(ACPI_IOREG_SMI_EN, 0x01); // 0x30 + // Set EOS Again + SET_IO8_PM(ACPI_IOREG_SMI_EN, 0x02); // 0x30 + // Set GBL_SMI_EN + SET_IO8_PM(ACPI_IOREG_SMI_EN, 0x01); // 0x30 + } +} + +//--------------------------------------------------------------------------- +// SW SMI Handler Porting hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SwSmiEnable +// +// Description: This function enables SW SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SwSmiEnable (VOID) +{ + // Porting required + SET_IO32_PM(ACPI_IOREG_SMI_EN, 0x20); // 0x30 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SwSmiDisable +// +// Description: This function disables SW SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SwSmiDisable (VOID) +{ + // Porting required + RESET_IO32_PM(ACPI_IOREG_SMI_EN, 0x20); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SwSmiClear +// +// Description: This function clears SW SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SwSmiClear (VOID) +{ + // Porting required + WRITE_IO32_PM(ACPI_IOREG_SMI_STS, 0x20); // 0x34 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SwSmiDetect +// +// Description: This function detects SW SMI event +// +// Input: *Type - Pointer to store SW SMI number +// +// Output: TRUE - SW SMI occured, FALSE otherwise +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SwSmiDetect ( + OUT UINT16 *Type ) +{ + // Porting required + if ( IsMe(5) ) { // SW_SMI + *Type = IoRead8(SW_SMI_IO_ADDRESS); + return TRUE; + } + + return FALSE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetEAX +// +// Description: This function returns EAX saved value from CPU that caused +// SW SMI. +// +// Input: None +// +// Output: EAX saved value +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINTN GetEAX (VOID) +{ + // Porting required for different CPU + EFI_STATUS Status; + EFI_GUID SwSmiCpuTriggerGuid = SW_SMI_CPU_TRIGGER_GUID; + SW_SMI_CPU_TRIGGER *SwSmiCpuTrigger; + UINTN Cpu = gSmst2->CurrentlyExecutingCpu - 1; // CPU # + UINT16 i; + UINT32 RegEAX; + + for (i = 0; i < gSmst2->NumberOfTableEntries; i++) { + if (guidcmp(&(gSmst2->SmmConfigurationTable[i].VendorGuid), \ + &SwSmiCpuTriggerGuid) == 0) + break; + } + + // If found table, check for the CPU that caused the software Smi. + if (i != gSmst2->NumberOfTableEntries) { + SwSmiCpuTrigger = gSmst2->SmmConfigurationTable[i].VendorTable; + Cpu = SwSmiCpuTrigger->Cpu; + } + + Status = gEfiSmmCpuProtocol->ReadSaveState ( \ + gEfiSmmCpuProtocol, \ + 4, \ + EFI_SMM_SAVE_STATE_REGISTER_RAX, \ + Cpu, \ + &RegEAX ); + return RegEAX; +} + +//--------------------------------------------------------------------------- +// SX SMI Handler Porting hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SxSmiEnable +// +// Description: This function enables SX SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SxSmiEnable (VOID) +{ + // Porting required + SET_IO32_PM(ACPI_IOREG_SMI_EN, 0x10); // 0x30 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SxSmiDisable +// +// Description: This function disables SX SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SxSmiDisable (VOID) +{ + // Porting required + RESET_IO32_PM(ACPI_IOREG_SMI_EN, 0x10); // 0x30 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SxSmiClear +// +// Description: This function clears SX SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SxSmiClear (VOID) +{ + // Porting required + WRITE_IO32_PM(ACPI_IOREG_SMI_STS, 0x10); // 0x34 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SxSmiDetect +// +// Description: This function detects SX SMI event +// +// Input: *Type - Pointer to store value of Sleep type +// +// Output: TRUE - SX SMI occured, FALSE otherwise +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SxSmiDetect ( + OUT UINT16 *Type ) +{ + // Porting required + if (IsMe(4)) { // SLP_SMI + switch (READ_IO16_PM(ACPI_IOREG_PM1_CNTL) & (7 << 10)) { // SLP_TYP + case (0 << 10): + *Type = SxS0; + break; + case (1 << 10): + *Type = SxS1; + break; + case (5 << 10): + *Type = SxS3; + break; + case (6 << 10): + *Type = SxS4; + break; + case (7 << 10): + *Type = SxS5; + break; + default: + return FALSE; // Unknown Error. + } + return TRUE; + } + return FALSE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: PutToSleep +// +// Description: Disable Smi sleep and put to sleep. +// +// Input: *Context - Pointer to Sleep SMI context +// +// Output: None +// +// Referrals: SxSmiDisable +// +// Notes: Here is the control flow of this function: +// 1. Disable Smi sleep. +// 2. Set to go to sleep if you want to sleep in SMI. otherwise +// set IORestart to 0xFF in CPU SMM dump area. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PutToSleep ( + IN EFI_SMM_SX_REGISTER_CONTEXT *SxContext ) +{ +// TODO YODO TODO +//#### EFI_SMM_CPU_SAVE_STATE *pCpuSaveState = gSmst2->CpuSaveState; +//#### UINTN Cpu = gSmst2->CurrentlyExecutingCpu - 1; +//#### UINT32 CacheFlush = 0; + + SxSmiDisable(); // Disable sleep SMI. + +//#### if (SxContext->Type == SxS5) +//#### SBLib_BeforeShutdown(); + +//#####if ACPI_SLEEP_IN_SMM + SET_IO16_PM(ACPI_IOREG_PM1_CNTL, 0x2000); // Set to sleep. +//#####else +//#### CacheFlush = pCpuSaveState[Cpu].Ia32SaveState.IORestart; +//#### pCpuSaveState[Cpu].Ia32SaveState.IORestart = 0xff; +//#####endif + +} + +//--------------------------------------------------------------------------- +// Periodic timer SMI Handler Porting hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TimerSmiEnable2 +// +// Description: This function enables Periodic timer SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID TimerSmiEnable2 (VOID) +{ + // Porting required +#if SWSMI_TIMER_INSTEAD + SET_IO32_PM(ACPI_IOREG_SMI_EN, 0x40); // 0x30 +#else + SET_IO32_PM(ACPI_IOREG_SMI_EN, 0x4000); // 0x30 +#endif +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TimerSmiDisable2 +// +// Description: This function disables Periodic timer SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID TimerSmiDisable2 (VOID) +{ + // Porting required +#if SWSMI_TIMER_INSTEAD + RESET_IO32_PM(ACPI_IOREG_SMI_EN, 0x40); // 0x30 +#else + RESET_IO32_PM(ACPI_IOREG_SMI_EN, 0x4000); // 0x30 +#endif +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TimerSmiClear2 +// +// Description: This function clears Periodic timer SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID TimerSmiClear2 (VOID) +{ + + // Porting required +#if SWSMI_TIMER_INSTEAD + // SWSMI has to be disabled before clear the status + volatile UINT32 Buffer32 = READ_IO32_PM(ACPI_IOREG_SMI_EN); // 0x30 + WRITE_IO32_PM(ACPI_IOREG_SMI_EN, Buffer32 & (UINT32)(~0x40)); // 0x30 + WRITE_IO32_PM(ACPI_IOREG_SMI_STS, 0x40); // 0x34 + WRITE_IO32_PM(ACPI_IOREG_SMI_EN, Buffer32); // 0x30 +#else + WRITE_IO32_PM(ACPI_IOREG_SMI_STS, 0x4000); // 0x34 +#endif +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TimerSmiDetect2 +// +// Description: This function detects Periodic timer SMI event +// +// Input: *Type - Added for compatibility, not used +// +// Output: TRUE - Periodic timer SMI occured, FALSE otherwise +// +// Notes: Return TRUE if Timer SMI detected, Type ignored +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN TimerSmiDetect2 ( + OUT UINT16 *Type ) +{ + // Porting required + *Type = 0; +#if SWSMI_TIMER_INSTEAD + return (IsMe(6)) ? TRUE : FALSE; +#else + return (IsMe(14)) ? TRUE : FALSE; +#endif +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TimerSetInterval2 +// +// Description: This function programs Periodic timer to given interval +// +// Input: Interval - Interval to program +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID TimerSetInterval2 ( + IN UINT64 Interval ) +{ + + // Porting required + UINT16 RateIndex; + UINT16 AvailTimer = sizeof(gSupportedIntervals) / sizeof(UINT64) - 1; + + TimerSmiDisable2(); + TimerSmiClear2(); + + for (RateIndex = 0; RateIndex < AvailTimer ; RateIndex++) + if (Interval == gSupportedIntervals[RateIndex]) break; +#if SWSMI_TIMER_INSTEAD + RW_PCI16_SB(SB_REG_GEN_PMCON_3, RateIndex << 6, 0xc0); // 0xA4 +#else + RW_PCI16_SB(SB_REG_GEN_PMCON_1, RateIndex, 3); // 0xA0 +#endif + + TimerSmiEnable2(); +} + +//--------------------------------------------------------------------------- +// Usb SMI Handler Porting hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: UsbSmiSet +// +// Description: This function enables/disables USB SMI based on given +// Controller type +// +// Input: ControllerType - USB controller type variable +// +// Output: None +// +// Notes: This function implements logic as follows: +// Three lowest bits of ControllerType: +// 000 - All USB controllers SMI are disabled +// 001 - UHCI/OHCI enabled, EHCI/XHCI - disabled +// 010 - EHCI enabled, UHCI/OHCI/XHCI - disabled +// 011 - UHCI/OHCI/EHCI enabled, XHCI - disabled +// 100 - XHCI enabled, UHCI/OHCI/EHCI - disabled +// 101 - UHCI/OHCI/XHCI enabled, EHCI - disabled +// 110 - EHCI/XHCI enabled, UHCI/OHCI - disabled +// 111 - All USB controllers SMI are enabled +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID UsbSmiSet( + IN UINT16 ControllerType ) +{ + // Porting required + switch (ControllerType & 7) { + + case 0 : // All USB controllers SMI are disabled + RESET_PCI32_EHCI(EHCI_REG_SPECIAL_SMI, 1); + RESET_PCI32_EHCI2(EHCI_REG_SPECIAL_SMI, 1); + RESET_IO32_PM(ACPI_IOREG_SMI_EN, 0x80060008); // 0x30 + break; + + case 1 : // UHCI/OHCI enabled, EHCI/XHCI - disabled + RESET_PCI32_EHCI(EHCI_REG_SPECIAL_SMI, 1); + RESET_PCI32_EHCI2(EHCI_REG_SPECIAL_SMI, 1); + RW_IO32_PM(ACPI_IOREG_SMI_EN, 0x08, 0x80060008); // 0x30 + break; + + case 2 : // EHCI enabled, UHCI/OHCI/XHCI - disabled + RW_IO32_PM(ACPI_IOREG_SMI_EN, 0x60000, 0x80060008); // 0x30 + SET_PCI32_EHCI(EHCI_REG_SPECIAL_SMI, 1); + SET_PCI32_EHCI2(EHCI_REG_SPECIAL_SMI, 1); + break; + + case 3 : // UHCI/OHCI/EHCI enabled, XHCI - disabled + RW_IO32_PM(ACPI_IOREG_SMI_EN, 0x60008, 0x80060008); // 0x30 + SET_PCI32_EHCI(EHCI_REG_SPECIAL_SMI, 1); + SET_PCI32_EHCI2(EHCI_REG_SPECIAL_SMI, 1); + break; + + case 4 : // XHCI enabled, UHCI/OHCI/EHCI - disabled + RESET_PCI32_EHCI(EHCI_REG_SPECIAL_SMI, 1); + RESET_PCI32_EHCI2(EHCI_REG_SPECIAL_SMI, 1); + RW_IO32_PM(ACPI_IOREG_SMI_EN, 0x80000000, 0x80060008); // 0x30 + break; + + case 5 : // UHCI/OHCI/XHCI enabled, EHCI - disabled + RESET_PCI32_EHCI(EHCI_REG_SPECIAL_SMI, 1); + RESET_PCI32_EHCI2(EHCI_REG_SPECIAL_SMI, 1); + RW_IO32_PM(ACPI_IOREG_SMI_EN, 0x80000008, 0x80060008); // 0x30 + break; + + case 6 : // EHCI/XHCI enabled, UHCI/OHCI - disabled + RW_IO32_PM(ACPI_IOREG_SMI_EN, 0x80060000, 0x80060008); // 0x30 + SET_PCI32_EHCI(EHCI_REG_SPECIAL_SMI, 1); + SET_PCI32_EHCI2(EHCI_REG_SPECIAL_SMI, 1); + break; + + default: // All USB controllers SMI are enabled + SET_IO32_PM(ACPI_IOREG_SMI_EN, 0x80060008); // 0x30 + SET_PCI32_EHCI(EHCI_REG_SPECIAL_SMI, 1); + SET_PCI32_EHCI2(EHCI_REG_SPECIAL_SMI, 1); + break; + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: UsbSmiClear +// +// Description: This function clears USB SMI status based on given Controller +// type. +// +// Input: UINT16 ControllerType - USB controller type variable +// +// Output: None +// +// Notes: This function implements logic as follows: +// Three lowest bits of ControllerType: +// Bit 0 - Clear UHCI/OHCI USB SMI status +// Bit 1 - Clear EHCI USB SMI status +// Bit 2 - Clear XHCI USB SMI status +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID UsbSmiClear ( + IN UINT16 ControllerType ) +{ + // Porting required + + if (ControllerType & 1) // Clear UHCI/OHCI USB SMI status + WRITE_IO32_PM(ACPI_IOREG_SMI_STS, 0x08); // 0x34 + + if (ControllerType & 2) // Clear EHCI USB SMI status + WRITE_IO32_PM(ACPI_IOREG_SMI_STS, 0x20000); // 0x34 + if (ControllerType & 4) // Clear XHCI USB SMI status + WRITE_IO32_PM(ACPI_IOREG_SMI_STS, 0x80000000); // 0x34 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: UsbSmiDetect +// +// Description: This function detects USB SMI event +// +// Input: *Type - Pointer to store USB controller type, source of event +// +// Output: TRUE - USB SMI occured, FALSE otherwise +// +// Notes: This function implements logic as follows: +// *Type will be set to +// 000 - There is no SMI occured +// Bit 0 - If UHCI/OHCI USB SMI is occured +// Bit 1 - If EHCI USB SMI is occured +// Bit 2 - If XHCI USB SMI is occured +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN UsbSmiDetect ( + OUT UINT16 *Type ) +{ + // Porting required + *Type = 0; + if (IsMe(03)) *Type |= 1; // USB_SMI (USB 1.1) + if (IsMe(17)) *Type |= 2; // USB_SMI (USB 2.0) + if (IsMe(31)) *Type |= 4; // USB_SMI (USB 3.0) + + return (*Type) ? TRUE : FALSE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetControllerType +// +// Description: This function returns USB controller type, based on given +// device path +// +// Input: *Device - Pointer USB device path protocol +// +// Output: UINT16 - USB controller type +// +// Notes: The USB controller type will be retuened by the follow value: +// 0 - If there is no matche. +// 1 - It is an UHCI/OHCI (USB 1.1) controller +// 2 - It is an EHCI (USB 2.0) controller +// 4 - It is a XHCI (USB 3.0) controller +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT16 GetControllerType ( + IN EFI_DEVICE_PATH_PROTOCOL *Device) +{ + // Porting required + EFI_DEVICE_PATH_PROTOCOL *DevicePath = Device; + PCI_DEVICE_PATH *PciDevicePath = NULL; // [EIP73033] + UINT16 ControllerType = 0; + + while (!isEndNode( DevicePath )) { + if ((DevicePath->Type == HARDWARE_DEVICE_PATH) && \ + (DevicePath->SubType == HW_PCI_DP)) { + PciDevicePath = (PCI_DEVICE_PATH *) DevicePath; + break; + } + DevicePath = NEXT_NODE (DevicePath); + } + +// [ EIP215945 ] +// if (PciDevicePath->Device == EHCI_DEV) { +// ControllerType = 1; +// if (PciDevicePath->Function == 0x07) ControllerType = 2; +// + if ((PciDevicePath->Device == EHCI_DEV) || (PciDevicePath->Device == EHCI2_DEV)) + { + ControllerType = 2; + } else { + if (PciDevicePath->Device == XHCI_DEV) + if (PciDevicePath->Function == XHCI_FUN) ControllerType = 4; + } + + return ControllerType; +} + +//--------------------------------------------------------------------------- +// GPI SMI Handler Porting hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GpiSmiSet +// +// Description: This function enables GPI SMI based on given bit field. +// +// Input: GpiEnableBit - GPI enabled bit field +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID GpiSmiSet ( + IN UINT32 GpiEnableBit ) +{ + // Porting required + + UINT8 GpiNum = 0; + PCH_SERIES PchSeries = GetPchSeries(); + + if (PchSeries == PchLp) { + SET_IO16(GPIO_BASE_ADDRESS + GP_IOREG_ALTGP_SMI_EN, (UINT16)GpiEnableBit); + } else { + SET_IO16_PM(ACPI_IOREG_ALTGP_SMI_EN, (UINT16)GpiEnableBit); + } + + while ((GpiEnableBit % 2) == 0) { + GpiEnableBit /= 2; + GpiNum++; + } + GpiNum *= 2; + + if (PchSeries == PchLp) { + //Only GPI[47:32] are capable of SMI# generation. + SET_IO16(GPIO_BASE_ADDRESS + GP_IOREG_GPI_ROUT2, (UINT16)GpiEnableBit); + } else { + RW_PCI32_SB(SB_REG_GPI_ROUT, 1 << GpiNum, 3 << GpiNum); // 0xB8 + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GpiSmiReset +// +// Description: This function disables GPI SMI based on given bit field. +// +// Input: GpiDisableBit - GPI disabled bit field +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID GpiSmiReset ( + IN UINT32 GpiDisableBit ) +{ + // Porting required + + UINT8 GpiNum = 0; + PCH_SERIES PchSeries = GetPchSeries(); + + if (PchSeries == PchLp) { + RESET_IO16(GPIO_BASE_ADDRESS + GP_IOREG_ALTGP_SMI_EN, (UINT16)GpiDisableBit); + } else { + RESET_IO16_PM(ACPI_IOREG_ALTGP_SMI_EN, (UINT16)GpiDisableBit); + } + + while ((GpiDisableBit % 2) == 0) { + GpiDisableBit /= 2; + GpiNum++; + } + GpiNum *= 2; + + if (PchSeries == PchLp) { + //Only GPI[47:32] are capable of SMI# generation. + RESET_IO16(GPIO_BASE_ADDRESS+GP_IOREG_GPI_ROUT2, (UINT16)GpiDisableBit); + } else { + RESET_PCI32_SB(SB_REG_GPI_ROUT, 3 << GpiNum); // 0xB8 + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: GpiSmiClear +// +// Description: This function clears GPI SMI status based on given bit field +// +// Input: Type - GPI Disabled bit field +// +// Output: None +// +// Notes: All GPIs which correspondent bit in Type set to 1 should +// be cleared +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID GpiSmiClear ( + IN UINT32 GpiClearBit ) +{ + // Porting required + if (GetPchSeries() == PchLp) { + WRITE_IO32(GPIO_BASE_ADDRESS + GP_IOREG_ALTGP_SMI_EN, GpiClearBit); + } else { + WRITE_IO16_PM(ACPI_IOREG_ALTGP_SMI_STS, (UINT16)GpiClearBit); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GpiSmiDetect +// +// Description: This function detects GPI SMI event +// +// Input: *Gpi - Pointer to store source of GPI SMI +// +// Output: TRUE - GPI SMI occured, FALSE otherwise +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN GpiSmiDetect ( + OUT UINT32 *Gpi ) +{ + // Porting required + if (GetPchSeries() == PchLp) { + *Gpi = READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_ALTGP_SMI_EN) & READ_IO32(GPIO_BASE_ADDRESS + GP_IOREG_ALTGP_SMI_STS); + } else { + *Gpi = READ_IO16_PM(ACPI_IOREG_ALTGP_SMI_EN) & READ_IO16_PM(ACPI_IOREG_ALTGP_SMI_STS); + } + + return (*Gpi) ? TRUE : FALSE; +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ConvertGpi +// +// Description: This function converts GPI to bitmap in 32 bit. +// +// Input: Gpi - GPI Pin number or bitmap +// +// Output: Converted GPI bitmap in 32 bit. +// GpiBitMap[16:0] = ALT_GPI_SMI_EN[15:0] = LPT-H GPI[15:0] +// GpiBitMap[16:0] = ALT_GPI_SMI_EN[15:0] = LPT-LP GPI[47:32] +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT32 ConvertGpi ( + IN UINTN Gpi +) +{ + UINT32 GpiBitMap = 0; + PCH_SERIES PchSeries = GetPchSeries(); + + if (GPI_DISPATCH2_BY_BITMAP) { + if (PchSeries == PchLp) + GpiBitMap = (UINT32)(Shr64((UINT64)Gpi, 32)); + else + GpiBitMap = (UINT32)Gpi; + } else { + if (PchSeries == PchLp) + GpiBitMap |= Shl64(1, (UINT8)(Gpi - 32)); + else + GpiBitMap |= Shl64(1, (UINT8)Gpi); + } + return GpiBitMap; +} + +//--------------------------------------------------------------------------- +// Standby button SMI Handler Porting hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SButtonSmiEnable +// +// Description: This function enables Standby button SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SButtonSmiEnable (VOID) +{ + // Porting required +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SButtonSmiDisable +// +// Description: This function disables Standby button SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SButtonSmiDisable (VOID) +{ + // Porting required +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SButtonSmiClear +// +// Description: This function clears Standby button SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SButtonSmiClear (VOID) +{ + // Porting required +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SButtonSmiDetect +// +// Description: This function detects Standby button SMI event +// +// Input: *Type - Pointer to store value of Standby button phase, +// not used. +// +// Output: TRUE - Standby button SMI occured, FALSE otherwise +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN SButtonSmiDetect ( + OUT UINT16 *Type ) +{ + // Porting required + return FALSE; +} + +//--------------------------------------------------------------------------- +// Power button SMI Handler Porting hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: PButtonSmiEnable +// +// Description: This function enables Power button SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PButtonSmiEnable (VOID) +{ + // Porting required + SET_IO16_PM(ACPI_IOREG_PM1_EN, 0x100); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: PButtonSmiDisable +// +// Description: This function disables Power button SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PButtonSmiDisable (VOID) +{ + // Porting required + RESET_IO16_PM(ACPI_IOREG_PM1_EN, 0x100); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: PButtonSmiClear +// +// Description: This function clears Power button SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PButtonSmiClear (VOID) +{ + // Porting required + WRITE_IO16_PM(ACPI_IOREG_PM1_STS, 0x100); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: PButtonSmiDetect +// +// Description: This function detects Power button SMI event +// +// Input: *Type - pointer to store value of Power button phase +// not used. +// +// Output: TRUE - Power button SMI occured, FALSE - otherwise +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN PButtonSmiDetect ( + OUT UINT16 *Type ) +{ + // Porting Required + UINT16 Buffer16; + + if ( IsAcpi() ) { + return FALSE; + } else { + Buffer16 = READ_IO16_PM(ACPI_IOREG_PM1_STS) & \ + READ_IO16_PM(ACPI_IOREG_PM1_EN) & 0x100; + return (Buffer16) ? TRUE : FALSE; + } +} + +//--------------------------------------------------------------------------- +// I/O Trap SMI Handler Porting hooks +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IoTrapSmiSet +// +// Description: This function sets I/O Trap functon based on given the +// context +// +// Input: IoTrapContext - Pointer to the context +// EFI_SMM_IO_TRAP_REGISTER_CONTEXT +// +// Output: TrapRegIndex - Pointer to the index of I/O Trap register +// that I/O Trap register will be enabled. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID IoTrapSmiSet2 ( + IN EFI_SMM_IO_TRAP_REGISTER_CONTEXT *IoTrapContext, + OUT UINT32 *TrapRegIndex ) +{ + // Porting required if needed. + UINT32 IoTrapAddr = RCRB_MMIO_IO_TRAP_0; // 0x1E80 + UINT32 i; + UINT32 Buffer32 = 0; + UINT16 Length = IoTrapContext->Length; + + // Find an available I/O trap register + for (i = 0; i < MAX_SUPPORTED_IOTRAP_REGS; i++) { + if ((READ_MEM32_RCRB(IoTrapAddr) & 1) == 0) break; + IoTrapAddr += 8; + } + + *TrapRegIndex = i; + + if (*TrapRegIndex == MAX_SUPPORTED_IOTRAP_REGS) return; + + if (Length < 4) Length = 4; + Buffer32 = Length; + for (i = 0; Buffer32 != 1; Buffer32 >>= 1, i++); + if (Length > (1 << i)) i++; + + Length = 1 << i; // Length is always 2^n + + Buffer32 = IoTrapContext->Address & 0xfffc; + Buffer32 |= ((Length - 1) & 0xfffc) << 16; + WRITE_MEM32_RCRB(IoTrapAddr, Buffer32); + + Buffer32 = 0xf0; // Byte Access +// if (IoTrapContext->TrapWidth == AccessWord) Buffer32 = 0x03; +// if (IoTrapContext->TrapWidth == AccessDWord) Buffer32 = 0x0f; + + if (IoTrapContext->Type == ReadWriteTrap) { + Buffer32 |= (1 << 17); // Both Read/Write Cycles. + } else { + if (IoTrapContext->Type == ReadTrap) + Buffer32 |= (1 << 16); // Read Cycle Only + } + + WRITE_MEM32_RCRB(IoTrapAddr + 4, Buffer32); + SET_MEM32_RCRB(IoTrapAddr, 1); // Enable Trap and SMI. +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IoTrapSmiReset +// +// Description: This function resets I/O Trap functon based on given the +// context +// +// Input: IoTrapContext - Pointer to the context that I/O trap register +// will be disabled. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID IoTrapSmiReset2 ( + IN EFI_SMM_IO_TRAP_REGISTER_CONTEXT *IoTrapContext, + OUT UINT32 *TrapRegIndex ) +{ + // Porting required if needed. + + UINT32 IoTrapAddr = RCRB_MMIO_IO_TRAP_0; // 0x1E80 + UINT32 i; + UINT32 TrapContext32 = 0; + + for (i = 0; i < MAX_SUPPORTED_IOTRAP_REGS; i++) { + TrapContext32 = READ_MEM32_RCRB(IoTrapAddr); + if (TrapContext32 & 1) + if ((UINT16)(TrapContext32 & 0xfffc) == IoTrapContext->Address) { + TrapContext32 = READ_MEM32_RCRB(IoTrapAddr + 4); + if (TrapContext32 & 0x20000) { + if (IoTrapContext->Type == ReadWriteTrap) break; + } else { + if (TrapContext32 & 0x10000) { + if (IoTrapContext->Type == ReadTrap) break; + } else { + if (IoTrapContext->Type == WriteTrap) break; + } + } + } + IoTrapAddr += 8; + } + + WRITE_MEM32_RCRB(IoTrapAddr, 0); + WRITE_MEM32_RCRB(IoTrapAddr + 4, 0); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IoTrapSmiEnable +// +// Description: This function enables I/O Trap SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID IoTrapSmiEnable2 (VOID) +{ + // Porting required if needed. +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IoTrapSmiDisable +// +// Description: This function disables I/O Trap SMI +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID IoTrapSmiDisable2 (VOID) +{ + // Porting required if needed. +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IoTrapSmiClear +// +// Description: This function clears all I/O Trap SMI status. +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID IoTrapSmiClear2 (VOID) +{ + // Porting required + SET_MEM32_RCRB(RCRB_MMIO_TRSR, 0); // 0x1E00 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: IoTrapSmiDetect2 +// +// Description: This function detects I/O Trap SMI event. +// +// Input: *IoTrapContext - Pointer to EFI_SMM_IO_TRAP_REGISTER_CONTEXT +// +// Output: TRUE - I/O Trap SMI occured, the SMI context IoTrapContext +// should be updated according to the traped H/W +// information. +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN IoTrapSmiDetect2 ( + OUT EFI_SMM_IO_TRAP_REGISTER_CONTEXT *IoTrapContext, + OUT UINT32 *IoTrapWriteData ) +{ + // Porting required + + UINT32 Buffer32; + UINT16 Offset = 0; + UINT16 i; + + if (READ_MEM32_RCRB(RCRB_MMIO_TRSR) & 15) { // 0x1E00 + + Buffer32 = READ_MEM32_RCRB(RCRB_MMIO_TRCR); // 0x1E10 + IoTrapContext->Address = Buffer32 & 0xfffc; + for (i = 0; i < 4; i++) { + if (Buffer32 & (1 << (16 + i))) break; + Offset++; + } + IoTrapContext->Address += Offset; + if (Buffer32 & (1 << 24)) { + IoTrapContext->Type = ReadTrap; + } else { + IoTrapContext->Type = WriteTrap; + *IoTrapWriteData = READ_MEM32_RCRB(RCRB_MMIO_TWDR); // 0x1E18 + } + return TRUE; + } + + return FALSE; +} + // [EIP93461]> +#if BIOS_WRITE_SMI_PATCH_ENABLE +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: PchBiosWritePatch +// +// Description: This function clears unexpected BIOSWR_STS. +// +// Input: None +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID BiosWriteSmiPatch ( VOID ) +{ + // Clear BIOSWR_STS(TCO_BASE + 04h[8]) if BIOS Lock Enable + // (B0:D31:F0 Reg#DCh[1]) is not set. + if (((READ_PCI8_SB(SB_REG_BIOS_CNTL) & BIT01) == 0) && \ + (READ_IO16_TCO(TCO_IOREG_STS1) & BIT08)) { + + // Clear BIOSWR_STS + WRITE_IO16_TCO(TCO_IOREG_STS1, BIT08); + // Clear TCO_STS + WRITE_IO16_PM(ACPI_IOREG_SMI_STS, BIT13); + + } +} +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbSmiWorkaround2 +// +// Description: This hook is used for all south bridge workaround in SMI. +// +// Input: None +// +// Output: None +// +// Notes: Porting required +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SbSmiWorkaround2 (VOID) +{ + +#if BIOS_WRITE_SMI_PATCH_ENABLE + BiosWriteSmiPatch(); +#endif + +} + // <[EIP93461] +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/Smm2/SmmChildDispatch2.h b/Chipset/SB/Smm2/SmmChildDispatch2.h new file mode 100644 index 0000000..7e557f2 --- /dev/null +++ b/Chipset/SB/Smm2/SmmChildDispatch2.h @@ -0,0 +1,333 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher2/SmmChildDispatch2.h 3 3/25/13 5:00a Wesleychen $ +// +// $Revision: 3 $ +// +// $Date: 3/25/13 5:00a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher2/SmmChildDispatch2.h $ +// +// 3 3/25/13 5:00a Wesleychen +// [TAG] None +// [Category] Improvement +// [Description] Refine GPI SMM2 related routines. +// [Files] SmiHandlerGeneric2.c; SmiHandlerPorting2.c; +// SmmChildDispatch2.h +// +// 2 10/19/12 2:52a Scottyang +// [TAG] EIP93461 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] System halt when AFUDOS is running with /N /ME command. +// [RootCause] An unexpected BIOSWR_STS is set, it causes BIOS stuck +// at SMM dispatcher. +// [Solution] Clear BIOSWR_STS if BIOS Lock Enable is not set. +// [Files] SmiHandlerPorting2.c; SmmChildDispatch2Main.c +// SmmChildDispatcher2.sdl; SmmChildDispatch2.h +// SB\SBGeneric.c +// +// 1 2/08/12 8:28a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SmmChildDispatch2.h +// +// Description: SMM Child dispatcher II functions and data structures +// definition. +// +//<AMI_FHDR_END> +//************************************************************************* + +#ifndef __SMM_CHILD_DISPATCH2__H__ +#define __SMM_CHILD_DISPATCH2__H__ +#ifdef __cplusplus +extern "C" { +#endif + +#include <AmiDxeLib.h> + +#include <Protocol\SmmSwDispatch2.h> +#include <Protocol\SmmSxDispatch2.h> +#include <Protocol\SmmPeriodicTimerDispatch2.h> +#include <Protocol\SmmUsbDispatch2.h> +#include <Protocol\SmmGpiDispatch2.h> +#include <Protocol\SmmStandbyButtonDispatch2.h> +#include <Protocol\SmmPowerButtonDispatch2.h> +#include <Protocol\SmmIoTrapDispatch2.h> + +#define SMM_CHILD_DISPATCHER2_GUID \ + {0x950c3a26, 0xe0c2, 0x491c, 0xb6, 0xb2, 0x3, 0x74, 0xf5, 0xc7, 0x3b, 0x96} + +#pragma pack(push, 1) + +typedef enum { + EfiSmmSwSmi2, + EfiSmmSxSmi2, + EfiSmmPeriodicTimerSmi2, + EfiSmmUsbSmi2, + EfiSmmGpiSmi2, + EfiSmmStandbyButtonSmi2, + EfiSmmPowerButtonSmi2, + EfiSmmIoTrapSmi2, + EfiSmmMaxSmi2 +} EFI_SMM_SMI2; + +typedef struct { + EFI_SMM_PERIODIC_TIMER_REGISTER_CONTEXT OrgContext; + UINT64 ElapsedTime; +} EFI_SMM_PERIODIC_TIMER_EXT_REGISTER_CONTEXT; + +typedef union { + EFI_SMM_SW_REGISTER_CONTEXT SwContext; + EFI_SMM_SX_REGISTER_CONTEXT SxContext; + EFI_SMM_PERIODIC_TIMER_EXT_REGISTER_CONTEXT TimerContext; + EFI_SMM_USB_REGISTER_CONTEXT UsbContext; + EFI_SMM_GPI_REGISTER_CONTEXT GpiContext; + EFI_SMM_STANDBY_BUTTON_REGISTER_CONTEXT SBtnContext; + EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT PBtnContext; + EFI_SMM_IO_TRAP_REGISTER_CONTEXT IoTrapContext; +} EFI_SMM_SMI_CONTEXT2; + +typedef EFI_STATUS ( *SMI_GENERIC_CALLBACK2 ) ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *DispatchContext OPTIONAL, + IN OUT VOID *CommBuffer OPTIONAL, + IN OUT UINTN *CommBufferSize OPTIONAL +); + +typedef struct { + DLINK Link; + UINT32 Signature; + SMI_GENERIC_CALLBACK2 Callback; + UINT8 Context[1]; +} HANDLER_LINK2; + +//--------------------------------------------------------------------------- +// SMI Handler protocol functions prototypes +//--------------------------------------------------------------------------- + +typedef EFI_STATUS ( *ADD_HANDLER2 ) ( + IN VOID *Context +); + +typedef EFI_STATUS ( *REMOVE_HANDLER2 ) ( + IN VOID *Context +); + +typedef EFI_STATUS ( *VERIFY_CONTEXT2) ( + IN VOID *Context +); + +typedef BOOLEAN ( *GET_CONTEXT2 ) ( + VOID +); + +typedef EFI_STATUS ( *DISPATCH_SMI2 ) ( + VOID +); + +typedef struct { + ADD_HANDLER2 AddHandler; + REMOVE_HANDLER2 RemoveHandler; + VERIFY_CONTEXT2 VerifyContext; + GET_CONTEXT2 GetContext; + DISPATCH_SMI2 DispatchSmi; +} SMI_HANDLER_PROTOCOL2; + +typedef struct { + EFI_SMM_SMI2 SmiType; + SMI_HANDLER_PROTOCOL2 HandlerProtocol; + DLIST RegisteredCallbacks; +} SMM_CHILD_DISPATCHER2; + +#pragma pack(pop) + +//--------------------------------------------------------------------------- +// SW SMI Handler functions +//--------------------------------------------------------------------------- + +EFI_STATUS SmmSwAddHandler2( IN VOID *Context ); +EFI_STATUS SmmSwRemoveHandler2( IN VOID *Context ); +EFI_STATUS SmmSwVerifyContext2( IN VOID *Context ); +BOOLEAN SmmSwGetContext2( VOID ); +EFI_STATUS SmmSwDispatchSmi2( VOID ); + +//---------------------- SW SMI Handler Porting hooks ----------------------- + +VOID SwSmiEnable( VOID ); +VOID SwSmiDisable( VOID ); +VOID SwSmiClear( VOID ); +BOOLEAN SwSmiDetect( OUT UINT16 *Type ); +UINTN GetEAX( VOID ); + +//--------------------------------------------------------------------------- +// SX SMI Handler functions +//--------------------------------------------------------------------------- + +EFI_STATUS SmmSxAddHandler2( IN VOID *Context ); +EFI_STATUS SmmSxRemoveHandler2( IN VOID *Context ); +EFI_STATUS SmmSxVerifyContext2( IN VOID *Context ); +BOOLEAN SmmSxGetContext2( VOID ); +EFI_STATUS SmmSxDispatchSmi2( VOID ); + +//---------------------- SX SMI Handler Porting hooks ----------------------- + +VOID SxSmiEnable( VOID ); +VOID SxSmiDisable( VOID ); +VOID SxSmiClear( VOID ); +VOID PutToSleep( IN VOID *Context ); +BOOLEAN SxSmiDetect( OUT UINT16 *Type ); + +//--------------------------------------------------------------------------- +// Periodic timer SMI Handler functions +//--------------------------------------------------------------------------- + +EFI_STATUS SmmTimerAddHandler2( IN VOID *Context ); +EFI_STATUS SmmTimerRemoveHandler2( IN VOID *Context ); +EFI_STATUS SmmTimerVerifyContext2( IN VOID *Context ); +BOOLEAN SmmTimerGetContext2( VOID ); +EFI_STATUS SmmTimerDispatchSmi2( VOID ); + +//---------------- Periodic timer SMI Handler Porting hooks ----------------- + +VOID TimerSmiEnable2( VOID ); +VOID TimerSmiDisable2( VOID ); +VOID TimerSmiClear2( VOID ); +BOOLEAN TimerSmiDetect2( OUT UINT16 *Type ); +VOID TimerSetInterval2( IN UINT64 Interval); + +//--------------------------------------------------------------------------- +// USB SMI Handler functions +//--------------------------------------------------------------------------- + +EFI_STATUS SmmUsbAddHandler2( IN VOID *Context ); +EFI_STATUS SmmUsbRemoveHandler2( IN VOID *Context ); +EFI_STATUS SmmUsbVerifyContext2( IN VOID *Context ); +BOOLEAN SmmUsbGetContext2( VOID ); +EFI_STATUS SmmUsbDispatchSmi2( VOID ); + +//---------------------- USB SMI Handler Porting hooks ---------------------- + +VOID UsbSmiSet( IN UINT16 ControllerType ); +VOID UsbSmiClear( IN UINT16 ControllerType ); +BOOLEAN UsbSmiDetect( OUT UINT16 *Type ); +UINT16 GetControllerType( OUT EFI_DEVICE_PATH_PROTOCOL *Device ); + +//--------------------------------------------------------------------------- +// GPI SMI Handler functions +//--------------------------------------------------------------------------- + +EFI_STATUS SmmGpiAddHandler2( IN VOID *Context ); +EFI_STATUS SmmGpiRemoveHandler2( IN VOID *Context ); +EFI_STATUS SmmGpiVerifyContext2( IN VOID *Context ); +BOOLEAN SmmGpiGetContext2( VOID ); +EFI_STATUS SmmGpiDispatchSmi2( VOID ); + +//---------------------- GPI SMI Handler Porting hooks ---------------------- + +VOID GpiSmiSet( IN UINT32 GpiEnableBit ); +VOID GpiSmiReset( IN UINT32 GpiDisableBit ); +VOID GpiSmiClear( IN UINT32 GpiClearBit ); +BOOLEAN GpiSmiDetect( OUT UINT32 *Gpi ); +UINT32 ConvertGpi ( IN UINTN Gpi ); + +//--------------------------------------------------------------------------- +// Standby button SMI Handler functions +//--------------------------------------------------------------------------- + +EFI_STATUS SmmSButtonAddHandler2( IN VOID *Context ); +EFI_STATUS SmmSButtonRemoveHandler2( IN VOID *Context ); +EFI_STATUS SmmSButtonVerifyContext2( IN VOID *Context ); +BOOLEAN SmmSButtonGetContext2( VOID ); +EFI_STATUS SmmSButtonDispatchSmi2( VOID ); + +//---------------- Standby button SMI Handler Porting hooks ----------------- + +VOID SButtonSmiEnable( VOID ); +VOID SButtonSmiDisable( VOID ); +VOID SButtonSmiClear( VOID ); +BOOLEAN SButtonSmiDetect( OUT UINT16 *Type ); + +//--------------------------------------------------------------------------- +// Power button SMI Handler functions +//--------------------------------------------------------------------------- + +EFI_STATUS SmmPButtonAddHandler2( IN VOID *Context ); +EFI_STATUS SmmPButtonRemoveHandler2( IN VOID *Context ); +EFI_STATUS SmmPButtonVerifyContext2( IN VOID *Context ); +BOOLEAN SmmPButtonGetContext2( VOID ); +EFI_STATUS SmmPButtonDispatchSmi2( VOID ); + +//---------------- Power button SMI Handler Porting hooks ------------------- + +VOID PButtonSmiEnable( VOID ); +VOID PButtonSmiDisable( VOID ); +VOID PButtonSmiClear( VOID ); +BOOLEAN PButtonSmiDetect( OUT UINT16 *Type ); + +//--------------------------------------------------------------------------- +// I/O Trap SMI Handler functions +//--------------------------------------------------------------------------- + +EFI_STATUS SmmIoTrapAddHandler2( IN VOID *Context ); +EFI_STATUS SmmIoTrapRemoveHandler2( IN VOID *Context ); +EFI_STATUS SmmIoTrapVerifyContext2( IN VOID *Context ); +BOOLEAN SmmIoTrapGetContext2( VOID ); +EFI_STATUS SmmIoTrapDispatchSmi2( VOID ); + +//------------------ I/O Trap SMI Handler Porting hooks --------------------- + +VOID IoTrapSmiSet2( IN EFI_SMM_IO_TRAP_REGISTER_CONTEXT *Context, \ + OUT UINT32 *TrapRegIndex ); +VOID IoTrapSmiReset2( IN EFI_SMM_IO_TRAP_REGISTER_CONTEXT *Context, \ + OUT UINT32 *TrapRegIndex ); +VOID IoTrapSmiEnable2( VOID ); +VOID IoTrapSmiDisable2( VOID ); +VOID IoTrapSmiClear2( VOID ); +BOOLEAN IoTrapSmiDetect2( OUT EFI_SMM_IO_TRAP_REGISTER_CONTEXT *Context, \ + OUT UINT32 *IoTrapWriteDara ); + +//--------------------------------------------------------------------------- +// All purpose SMI Porting hooks +//--------------------------------------------------------------------------- +VOID ClearAllSmi( VOID ); + // [EIP93461]> +VOID SbSmiWorkaround2( VOID ); + // <[EIP93461] +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/Smm2/SmmChildDispatch2Main.c b/Chipset/SB/Smm2/SmmChildDispatch2Main.c new file mode 100644 index 0000000..bae5efc --- /dev/null +++ b/Chipset/SB/Smm2/SmmChildDispatch2Main.c @@ -0,0 +1,510 @@ +#pragma optimize ("", off) +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher2/SmmChildDispatch2Main.c 4 10/19/12 2:52a Scottyang $ +// +// $Revision: 4 $ +// +// $Date: 10/19/12 2:52a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher2/SmmChildDispatch2Main.c $ +// +// 4 10/19/12 2:52a Scottyang +// [TAG] EIP93461 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] System halt when AFUDOS is running with /N /ME command. +// [RootCause] An unexpected BIOSWR_STS is set, it causes BIOS stuck +// at SMM dispatcher. +// [Solution] Clear BIOSWR_STS if BIOS Lock Enable is not set. +// [Files] SmiHandlerPorting2.c; SmmChildDispatch2Main.c +// SmmChildDispatcher2.sdl; SmmChildDispatch2.h +// SB\SBGeneric.c +// +// 3 8/30/12 9:50a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Implement EIP#73211 and EIP#79156 for OA 3.0 function. +// [Files] SmiHandlerGeneric2.c, SmmChildDispatch2Main.c +// +// 2 4/25/12 9:32a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Reprogram SMM ChildDispatcher drivers. +// [Files] SmiHandlerGeneric.c; SmiHandlerPorting.c; +// SmiHandlerGeneric2.c; SmmChildDispatch2Main.c; SmmChildDispatcher2.mak; +// SmmChildDispatcher2.sdl; SmmChildDispatch.h; SmmChildDispatchMain.c; +// SmmChildDispatchProtocol.c; SmmChildDispatcher.dxs; +// PchSmiDispatcher.sdl +// +// 1 2/08/12 8:28a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SmmChildDispatch2Main.c +// +// Description: This file contains implementation of module entry point, +// generic RegisterHandler and UnregisterHandler routines +// and main dispatcher loop. +// +//<AMI_FHDR_END> +//************************************************************************* + +//--------------------------------------------------------------------------- +// Include(s) +//--------------------------------------------------------------------------- + +#include <AmiCspLib.h> +#include <Smm.h> +#include <Protocol\SmmBase2.h> +#include <Protocol\SmmCpu.h> +#include "SmmChildDispatch2.h" +#include "SmmChildDispatch2Protocol.h" + +//--------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//--------------------------------------------------------------------------- +// Constant Definition(s) + +#define SMI_HANDLER_SIGNATURE 0x48494d53 //SMIH + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//--------------------------------------------------------------------------- +// Variable and External Declaration(s) +//--------------------------------------------------------------------------- +// Variable Declaration(s) + +EFI_SMM_SMI_CONTEXT2 SmiContext; +EFI_SMM_BASE2_PROTOCOL *gSmmBase2; +EFI_SMM_SYSTEM_TABLE2 *gSmst2; +EFI_SMM_CPU_PROTOCOL *gEfiSmmCpuProtocol; + +// GUID Definition(s) + +EFI_GUID gEfiSmmChildDispatcher2Guid = SMM_CHILD_DISPATCHER2_GUID; + +// Protocol Definition(s) + +// External Declaration(s) + +extern SMM_CHILD_DISPATCHER2 Smm2Handler[]; + +extern EFI_SMM_SW_DISPATCH2_PROTOCOL gEfiSmmSwDispatch2Protocol; +extern EFI_SMM_SX_DISPATCH2_PROTOCOL gEfiSmmSxDispatch2Protocol; +extern EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL gEfiSmmPeriodicTimerDispatch2Protocol; +extern EFI_SMM_USB_DISPATCH2_PROTOCOL gEfiSmmUsbDispatch2Protocol; +extern EFI_SMM_GPI_DISPATCH2_PROTOCOL gEfiSmmGpiDispatch2Protocol; +extern EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL gEfiSmmStandbyButtonDispatch2Protocol; +extern EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL gEfiSmmPowerButonDispatch2Protocol; +extern EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL gEfiSmmIoTrapDispatch2Protocol; + +// Function Definition(s) + +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RegisterHandler2 +// +// Description: This function registers SMI II handler and returns registered +// handle +// +// Input: Type - Type of SMI handler +// Function - Pointer to callback function +// *Context - Pointer to callback context +// ContextSize - Callback context size +// *Handle - Pointer to store registered handle +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS RegisterHandler2 ( + IN EFI_SMM_SMI2 Type, + IN SMI_GENERIC_CALLBACK2 Function, + IN VOID *Context, + IN UINTN ContextSize, + OUT EFI_HANDLE *Handle ) +{ + EFI_STATUS Status; + HANDLER_LINK2 *HandlerLink; + + Status = Smm2Handler[Type].HandlerProtocol.VerifyContext( Context ); + if(EFI_ERROR(Status)) return Status; + + Status = gSmst2->SmmAllocatePool( 0, + sizeof(HANDLER_LINK2) + ContextSize - 1, + &HandlerLink ); + if(EFI_ERROR(Status)) return Status; + + HandlerLink->Callback = Function; + HandlerLink->Signature = SMI_HANDLER_SIGNATURE; + MemCpy( HandlerLink->Context, Context, ContextSize ); + + DListAdd(&(Smm2Handler[Type].RegisteredCallbacks), (DLINK *)HandlerLink); + + Smm2Handler[Type].HandlerProtocol.AddHandler( HandlerLink->Context ); + *Handle = HandlerLink; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: FindHandler +// +// Description: This function find the handle in the Type of SMI hander list. +// +// Input: Type - Type of SMI handler +// Handle - Handle of found handler +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS FindHandler( + IN EFI_SMM_SMI2 Type, + IN EFI_HANDLE Handle) +{ + HANDLER_LINK2 *HandlerLink = (HANDLER_LINK2 *)Handle; + HANDLER_LINK2 *NodeLink = NULL; + + if (HandlerLink->Signature != SMI_HANDLER_SIGNATURE) + return EFI_INVALID_PARAMETER; + + if (Smm2Handler[Type].RegisteredCallbacks.Size <= 0) + return EFI_UNSUPPORTED; + + NodeLink = (HANDLER_LINK2 *)Smm2Handler[Type].RegisteredCallbacks.pHead; + for (; NodeLink != NULL; NodeLink = (HANDLER_LINK2 *)NodeLink->Link.pNext) + { + if (NodeLink == HandlerLink) + return EFI_SUCCESS; + } + + return EFI_UNSUPPORTED; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: UnregisterHandler2 +// +// Description: This function unregisters SMI II handler with given handle +// +// Input: Type - Type of SMI handler +// Handle - Handle of registered handler +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS UnregisterHandler2 ( + IN EFI_SMM_SMI2 Type, + IN EFI_HANDLE Handle ) +{ + EFI_STATUS Status; + HANDLER_LINK2 *HandlerLink = (HANDLER_LINK2 *)Handle; + + Status = FindHandler(Type, Handle); + if (Status == EFI_SUCCESS) + { + Smm2Handler[Type].HandlerProtocol.RemoveHandler( HandlerLink->Context ); + DListDelete( &(Smm2Handler[Type].RegisteredCallbacks), (DLINK *)HandlerLink ); + gSmst2->SmmFreePool( HandlerLink ); + } + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ChildDispatcher2 +// +// Description: This function implements main SMI II dispatcher. +// +// Input: DispatchHandle - SMM dispatch handle +// *Context - Pointer to the dispatched context +// CommBuffer - Pointer to a collection of data in memory +// that will be conveyed from a non-SMM +// environment into an SMM environment. +// CommBufferSize - Pointer to the size of the CommBuffer +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS ChildDispatcher2 ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *Context OPTIONAL, + IN OUT VOID *CommBuffer OPTIONAL, + IN OUT UINTN *CommBufferSize OPTIONAL ) +{ + EFI_STATUS Status = EFI_UNSUPPORTED; + UINT32 Index; + BOOLEAN HandledSmi; + + do + { + HandledSmi = FALSE; + for (Index = EfiSmmSwSmi2; Index < EfiSmmMaxSmi2; Index++) + { + if (Smm2Handler[Index].HandlerProtocol.GetContext != 0 && + Smm2Handler[Index].HandlerProtocol.GetContext()) + { + Status = Smm2Handler[Index].HandlerProtocol.DispatchSmi(); + if (Status != EFI_WARN_INTERRUPT_SOURCE_QUIESCED) + { + HandledSmi = TRUE; + } + } + } + } while (HandledSmi); + // [EIP93461]> + SbSmiWorkaround2(); + // <[EIP93461] + return EFI_HANDLER_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InSmmFunction +// +// Description: This function initializes Child dispatcher in SMM mode +// +// Input: ImageHandle - Image handle +// *SystemTable - Pointer to system table +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS InSmmFunction ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle = NULL; + EFI_HANDLE BsHandle = NULL; + EFI_HANDLE RootHandle; + +#if (CHILD_DISPATCHER_SUPPORT == 0) + ClearAllSmi(); +#endif + + // Locate SMM CPU Protocols + Status = gSmst2->SmmLocateProtocol( &gEfiCpuProtocolGuid, + NULL, + &gEfiSmmCpuProtocol); + + // Install Protocols + Status = gSmst2->SmmInstallProtocolInterface( + &Handle, + &gEfiSmmSwDispatch2ProtocolGuid, + EFI_NATIVE_INTERFACE, + &gEfiSmmSwDispatch2Protocol); + ASSERT_EFI_ERROR(Status); + + Status = pBS->InstallProtocolInterface( + &BsHandle, + &gEfiSmmSwDispatch2ProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL); + ASSERT_EFI_ERROR(Status); + + Status = gSmst2->SmmInstallProtocolInterface( + &Handle, + &gEfiSmmSxDispatch2ProtocolGuid, + EFI_NATIVE_INTERFACE, + &gEfiSmmSxDispatch2Protocol); + ASSERT_EFI_ERROR(Status); + + Status = pBS->InstallProtocolInterface( + &BsHandle, + &gEfiSmmSxDispatch2ProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL); + ASSERT_EFI_ERROR(Status); + + Status = gSmst2->SmmInstallProtocolInterface( + &Handle, + &gEfiSmmPeriodicTimerDispatch2ProtocolGuid, + EFI_NATIVE_INTERFACE, + &gEfiSmmPeriodicTimerDispatch2Protocol); + ASSERT_EFI_ERROR(Status); + + Status = pBS->InstallProtocolInterface( + &BsHandle, + &gEfiSmmPeriodicTimerDispatch2ProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL); + ASSERT_EFI_ERROR(Status); + + Status = gSmst2->SmmInstallProtocolInterface( + &Handle, + &gEfiSmmUsbDispatch2ProtocolGuid, + EFI_NATIVE_INTERFACE, + &gEfiSmmUsbDispatch2Protocol); + ASSERT_EFI_ERROR(Status); + + Status = pBS->InstallProtocolInterface( + &BsHandle, + &gEfiSmmUsbDispatch2ProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL); + ASSERT_EFI_ERROR(Status); + + Status = gSmst2->SmmInstallProtocolInterface( + &Handle, + &gEfiSmmGpiDispatch2ProtocolGuid, + EFI_NATIVE_INTERFACE, + &gEfiSmmGpiDispatch2Protocol); + ASSERT_EFI_ERROR(Status); + + Status = pBS->InstallProtocolInterface( + &BsHandle, + &gEfiSmmGpiDispatch2ProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL); + ASSERT_EFI_ERROR(Status); + + Status = gSmst2->SmmInstallProtocolInterface( + &Handle, + &gEfiSmmStandbyButtonDispatch2ProtocolGuid, + EFI_NATIVE_INTERFACE, + &gEfiSmmStandbyButtonDispatch2Protocol); + ASSERT_EFI_ERROR(Status); + + Status = pBS->InstallProtocolInterface( + &BsHandle, + &gEfiSmmStandbyButtonDispatch2ProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL); + ASSERT_EFI_ERROR(Status); + + Status = gSmst2->SmmInstallProtocolInterface( + &Handle, + &gEfiSmmPowerButtonDispatch2ProtocolGuid, + EFI_NATIVE_INTERFACE, + &gEfiSmmPowerButonDispatch2Protocol); + ASSERT_EFI_ERROR(Status); + + Status = pBS->InstallProtocolInterface( + &BsHandle, + &gEfiSmmPowerButtonDispatch2ProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL); + ASSERT_EFI_ERROR(Status); + + Status = gSmst2->SmmInstallProtocolInterface( + &Handle, + &gEfiSmmIoTrapDispatch2ProtocolGuid, + EFI_NATIVE_INTERFACE, + &gEfiSmmIoTrapDispatch2Protocol); + ASSERT_EFI_ERROR(Status); + + Status = pBS->InstallProtocolInterface( + &BsHandle, + &gEfiSmmIoTrapDispatch2ProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL); + ASSERT_EFI_ERROR(Status); + + Status = gSmst2->SmiHandlerRegister(ChildDispatcher2, NULL, &RootHandle); + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmChildDispatch2EntryPoint +// +// Description: SMM Child Dispatcher II module entry point +// +// Input: ImageHandle - Image handle +// *SystemTable - Pointer to system table +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmChildDispatch2EntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status; + BOOLEAN InSmram = FALSE; + + InitAmiLib( ImageHandle, SystemTable ); + + Status = pBS->LocateProtocol(&gEfiSmmBase2ProtocolGuid, NULL, &gSmmBase2); + if (!EFI_ERROR(Status)) + { + Status = gSmmBase2->InSmm(gSmmBase2, &InSmram); + if ((!EFI_ERROR(Status)) && + (InSmram)) + { + Status = InitAmiSmmLib( ImageHandle, SystemTable ); + if (EFI_ERROR(Status)) + return Status; + + Status = gSmmBase2->GetSmstLocation(gSmmBase2, &gSmst2); + if (!EFI_ERROR(Status)) + { + Status = InSmmFunction(ImageHandle, SystemTable); + return Status; + } + else + { + gSmst2 = NULL; + } + } + else + { + // DXE initialize. + } + } + + return EFI_SUCCESS; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/Smm2/SmmChildDispatch2Protocol.c b/Chipset/SB/Smm2/SmmChildDispatch2Protocol.c new file mode 100644 index 0000000..2fc7edc --- /dev/null +++ b/Chipset/SB/Smm2/SmmChildDispatch2Protocol.c @@ -0,0 +1,679 @@ +#pragma optimize ("", off) +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher2/SmmChildDispatch2Protocol.c 1 2/08/12 8:28a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:28a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher2/SmmChildDispatch2Protocol.c $ +// +// 1 2/08/12 8:28a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SmmChildDispatch2Protocol.c +// +// Description: This file contains SMM Child dispatcher II Protocols +// +//<AMI_FHDR_END> +//************************************************************************* + +//--------------------------------------------------------------------------- +// Include(s) +//--------------------------------------------------------------------------- + +#include <Token.h> +#include <AmiDxeLib.h> +#include "SmmChildDispatch2.h" +#include "SmmChildDispatch2Protocol.h" + +//--------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//--------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//--------------------------------------------------------------------------- +// Variable and External Declaration(s) +//--------------------------------------------------------------------------- +// Variable Declaration(s) + +SMM_CHILD_DISPATCHER2 Smm2Handler[] = { + // SwSmmHandler + EfiSmmSwSmi2, + { SmmSwAddHandler2, \ + SmmSwRemoveHandler2, \ + SmmSwVerifyContext2, \ + SmmSwGetContext2, \ + SmmSwDispatchSmi2 }, + { 0, NULL, NULL }, + + // SxSmmHandler + EfiSmmSxSmi2, + { SmmSxAddHandler2, \ + SmmSxRemoveHandler2, \ + SmmSxVerifyContext2, \ + SmmSxGetContext2, \ + SmmSxDispatchSmi2 }, + { 0, NULL, NULL }, + + // PeriodicTimerSmmHandler + EfiSmmPeriodicTimerSmi2, + { SmmTimerAddHandler2, \ + SmmTimerRemoveHandler2, \ + SmmTimerVerifyContext2, \ + SmmTimerGetContext2, \ + SmmTimerDispatchSmi2 }, + { 0, NULL, NULL }, + + // UsbSmmHandler + EfiSmmUsbSmi2, + { SmmUsbAddHandler2, \ + SmmUsbRemoveHandler2, \ + SmmUsbVerifyContext2, \ + SmmUsbGetContext2, \ + SmmUsbDispatchSmi2 }, + { 0, NULL, NULL }, + + // GpiSmmHandler + EfiSmmGpiSmi2, + { SmmGpiAddHandler2, \ + SmmGpiRemoveHandler2, \ + SmmGpiVerifyContext2, \ + SmmGpiGetContext2, \ + SmmGpiDispatchSmi2 }, + { 0, NULL, NULL }, + + // SButtonSmmHandler + EfiSmmStandbyButtonSmi2, + { SmmSButtonAddHandler2, \ + SmmSButtonRemoveHandler2, \ + SmmSButtonVerifyContext2, \ + SmmSButtonGetContext2, \ + SmmSButtonDispatchSmi2 }, + { 0, NULL, NULL }, + + // PButtonSmmHandler + EfiSmmPowerButtonSmi2, + { SmmPButtonAddHandler2, \ + SmmPButtonRemoveHandler2, \ + SmmPButtonVerifyContext2, \ + SmmPButtonGetContext2, \ + SmmPButtonDispatchSmi2 }, + { 0, NULL, NULL }, + + // IoTrapSmmHandler + EfiSmmIoTrapSmi2, + { SmmIoTrapAddHandler2, \ + SmmIoTrapRemoveHandler2, \ + SmmIoTrapVerifyContext2, \ + SmmIoTrapGetContext2, \ + SmmIoTrapDispatchSmi2 }, + { 0, NULL, NULL }, + +//********************** PUT ADDITIONAL HANDLERS HERE *********************** +//********************** PUT ADDITIONAL HANDLERS HERE *********************** +//********************** PUT ADDITIONAL HANDLERS HERE *********************** + + // Terminator record + EfiSmmMaxSmi2, + { NULL, NULL, NULL, NULL, NULL }, + { 0, NULL, NULL } +}; + +EFI_SMM_SW_DISPATCH2_PROTOCOL gEfiSmmSwDispatch2Protocol = \ + { EfiSmmSwRegister2, \ + EfiSmmSwUnregister2, \ + MAX_SW_SMI_INPUT_VALUE }; + +EFI_SMM_SX_DISPATCH2_PROTOCOL gEfiSmmSxDispatch2Protocol = \ + { EfiSmmSxRegister2, EfiSmmSxUnregister2 }; + +EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL \ + gEfiSmmPeriodicTimerDispatch2Protocol = \ + { EfiSmmTimerRegister2, \ + EfiSmmTimerUnregister2, \ + EfiSmmTimerGetNextShorterInterval2 }; + +EFI_SMM_USB_DISPATCH2_PROTOCOL gEfiSmmUsbDispatch2Protocol = \ + { EfiSmmUsbRegister2, EfiSmmUsbUnregister2 }; + +EFI_SMM_GPI_DISPATCH2_PROTOCOL gEfiSmmGpiDispatch2Protocol = \ + { EfiSmmGpiRegister2, \ + EfiSmmGpiUnregister2, \ + SUPPORTED_GPIS }; + +EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL \ + gEfiSmmStandbyButtonDispatch2Protocol = \ + { EfiSmmSButtonRegister2, EfiSmmSButtonUnregister2 }; + +EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL gEfiSmmPowerButonDispatch2Protocol = \ + { EfiSmmPButtonRegister2, EfiSmmPButtonUnregister2 }; + + +EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL gEfiSmmIoTrapDispatch2Protocol = \ + { EfiSmmIoTrapRegister2, EfiSmmIoTrapUnregister2 }; + + +// GUID Definition(s) + +// Protocol Definition(s) + +// External Declaration(s) + +extern UINT64 gSupportedIntervals[]; + +// Function Definition(s) + +//--------------------------------------------------------------------------- +// S/W SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmSwRegister2 +// +// Description: EFI_SMM_SW_DISPATCH2_PROTOCOL Register function. +// +// Input: *This - Pointer to EFI_SMM_SW_DISPATCH2_PROTOCOL +// Function - Pointer to callback function +// *Context - Pointer to callback context +// *Handle - Pointer to store registered handle +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmSwRegister2 ( + IN CONST EFI_SMM_SW_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 Function, + IN CONST EFI_SMM_SW_REGISTER_CONTEXT *Context, + OUT EFI_HANDLE *Handle ) +{ + return RegisterHandler2( EfiSmmSwSmi2, \ + Function, \ + Context, \ + sizeof(EFI_SMM_SW_REGISTER_CONTEXT), \ + Handle ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmSwUnregister2 +// +// Description: EFI_SMM_SW_DISPATCH2_PROTOCOL Unregister function. +// +// Input: *This - Pointer to the EFI_SMM_SW_DISPATCH2_PROTOCOL +// Handle - Handle to unregister +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmSwUnregister2 ( + IN CONST EFI_SMM_SW_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ + return UnregisterHandler2( EfiSmmSwSmi2, Handle ); +} + +//--------------------------------------------------------------------------- +// Sleep SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmSxRegister2 +// +// Description: EFI_SMM_SX_DISPATCH2_PROTOCOL Register function. +// +// Input: *This - Pointer to EFI_SMM_SX_DISPATCH2_PROTOCOL +// Function - Pointer to callback function +// *Context - Pointer to callback context +// *Handle - Pointer to store registered handle +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmSxRegister2 ( + IN CONST EFI_SMM_SX_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 Function, + IN CONST EFI_SMM_SX_REGISTER_CONTEXT *Context, + OUT EFI_HANDLE *Handle ) +{ + return RegisterHandler2( EfiSmmSxSmi2, \ + Function, \ + Context, \ + sizeof(EFI_SMM_SX_REGISTER_CONTEXT), \ + Handle ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmSxUnregister2 +// +// Description: EFI_SMM_SW_DISPATCH2_PROTOCOL Unregister function. +// +// Input: *This - Pointer to the EFI_SMM_SX_DISPATCH2_PROTOCOL +// Handle - Handle to unregister +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmSxUnregister2 ( + IN CONST EFI_SMM_SX_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ + return UnregisterHandler2( EfiSmmSxSmi2, Handle ); +} + +//--------------------------------------------------------------------------- +// Periodic timer SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmTimerRegister2 +// +// Description: EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL Register function. +// +// Input: *This - Pointer to +// EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL +// Function - Pointer to callback function +// *Context - Pointer to callback context +// *Handle - Pointer to store registered handle +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmTimerRegister2 ( + IN CONST EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 Function, + IN CONST EFI_SMM_PERIODIC_TIMER_REGISTER_CONTEXT *Context, + OUT EFI_HANDLE *Handle ) +{ + EFI_SMM_PERIODIC_TIMER_EXT_REGISTER_CONTEXT ExContext; + TRACE ((TRACE_ALWAYS, "EfiSmmTimerRegister2 \n")); + ExContext.OrgContext = *Context; + ExContext.ElapsedTime = 0; + + return RegisterHandler2( EfiSmmPeriodicTimerSmi2, \ + Function, \ + &ExContext, \ + sizeof(EFI_SMM_PERIODIC_TIMER_EXT_REGISTER_CONTEXT), \ + Handle ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmTimerUnregister2 +// +// Description: EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL Unregister function. +// +// Input: *This - Pointer to the +// EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL +// Handle - Handle to unregister +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmTimerUnregister2 ( + IN CONST EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ + TRACE ((TRACE_ALWAYS, "EfiSmmTimerUnregister2 \n")); + return UnregisterHandler2( EfiSmmPeriodicTimerSmi2, Handle ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmTimerGetNextShorterInterval2 +// +// Description: EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL +// GetNextShorterInterval function. +// +// Input: *This - Pointer to the +// EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL +// **SmiTickInterval - Pointer to store pointer to next interval +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmTimerGetNextShorterInterval2 ( + IN CONST EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL *This, + IN OUT UINT64 **SmiTickInterval ) +{ + UINT64 *Result = *SmiTickInterval; + TRACE ((TRACE_ALWAYS, "EfiSmmTimerGetNextShorterInterval2 \n")); + if (Result == NULL) { + Result = gSupportedIntervals; + } else { + Result++; + } + *SmiTickInterval = (*Result == 0) ? NULL : Result; + + return EFI_SUCCESS; +} + +//--------------------------------------------------------------------------- +// USB SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmUsbRegister2 +// +// Description: EFI_SMM_USB_DISPATCH2_PROTOCOL Register function. +// +// Input: *This - Pointer to EFI_SMM_USB_DISPATCH2_PROTOCOL +// Function - Pointer to callback function +// *Context - Pointer to callback context +// *Handle - Pointer to store registered handle +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmUsbRegister2 ( + IN CONST EFI_SMM_USB_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 Function, + IN CONST EFI_SMM_USB_REGISTER_CONTEXT *Context, + OUT EFI_HANDLE *Handle ) +{ + return RegisterHandler2( EfiSmmUsbSmi2, \ + Function, \ + Context, \ + sizeof(EFI_SMM_USB_REGISTER_CONTEXT), \ + Handle ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmUsbUnregister2 +// +// Description: EFI_SMM_USB_DISPATCH2_PROTOCOL Unregister function. +// +// Input: *This - Pointer to the EFI_SMM_USB_DISPATCH2_PROTOCOL +// Handle - Handle to unregister +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmUsbUnregister2 ( + IN CONST EFI_SMM_USB_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ + return UnregisterHandler2( EfiSmmUsbSmi2, Handle ); +} + +//--------------------------------------------------------------------------- +// GPI SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmGpiRegister2 +// +// Description: EFI_SMM_GPI_DISPATCH2_PROTOCOL Register function. +// +// Input: *This - Pointer to EFI_SMM_GPI_DISPATCH2_PROTOCOL +// Function - Pointer to callback function +// *Context - Pointer to callback context +// *Handle - Pointer to store registered handle +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmGpiRegister2 ( + IN CONST EFI_SMM_GPI_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 Function, + IN CONST EFI_SMM_GPI_REGISTER_CONTEXT *Context, + OUT EFI_HANDLE *Handle ) +{ + return RegisterHandler2( EfiSmmGpiSmi2, \ + Function, \ + Context, \ + sizeof(EFI_SMM_GPI_REGISTER_CONTEXT), \ + Handle ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmGpiUnregister2 +// +// Description: EFI_SMM_GPI_DISPATCH2_PROTOCOL Unregister function. +// +// Input: *This - Pointer to the EFI_SMM_GPI_DISPATCH2_PROTOCOL +// Handle - Handle to unregister +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmGpiUnregister2 ( + IN CONST EFI_SMM_GPI_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ + return UnregisterHandler2( EfiSmmGpiSmi2, Handle ); +} + +//--------------------------------------------------------------------------- +// Standby button SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmSButtonRegister2 +// +// Description: EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL Register function. +// +// Input: *This - Pointer to +// EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL +// Function - Pointer to callback function +// *Context - Pointer to callback context +// *Handle - Pointer to store registered handle +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmSButtonRegister2 ( + IN CONST EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 Function, + IN CONST EFI_SMM_STANDBY_BUTTON_REGISTER_CONTEXT *Context, + OUT EFI_HANDLE *Handle ) +{ + return RegisterHandler2( EfiSmmStandbyButtonSmi2, \ + Function, \ + Context, \ + sizeof(EFI_SMM_STANDBY_BUTTON_REGISTER_CONTEXT),\ + Handle ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmSButtonUnregister2 +// +// Description: EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL Unregister function. +// +// Input: *This - Pointer to the +// EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL +// Handle - Handle to unregister +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmSButtonUnregister2 ( + IN CONST EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ + return UnregisterHandler2( EfiSmmStandbyButtonSmi2, Handle ); +} + +//--------------------------------------------------------------------------- +// Power button SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmPButtonRegister2 +// +// Description: EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL Register function. +// +// Input: *This - Pointer to EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL +// Function - Pointer to callback function +// *Context - Pointer to callback context +// *Handle - Pointer to store registered handle +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmPButtonRegister2 ( + IN CONST EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 Function, + IN CONST EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT *Context, + OUT EFI_HANDLE *Handle ) +{ + return RegisterHandler2( EfiSmmPowerButtonSmi2, \ + Function, \ + Context, \ + sizeof(EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT), \ + Handle ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmPButtonUnregister2 +// +// Description: EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL Unregister function. +// +// Input: *This - Pointer to the +// EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL +// Handle - Handle to unregister +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmPButtonUnregister2 ( + IN CONST EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ + return UnregisterHandler2( EfiSmmPowerButtonSmi2, Handle ); +} + +//--------------------------------------------------------------------------- +// I/O Trap SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmIoTrapRegister2 +// +// Description: EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL Register function. +// +// Input: *This - Pointer to EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL +// Function - Pointer to callback function +// *Context - Pointer to register context +// *Handle - Pointer to store registered handle +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmIoTrapRegister2 ( + IN CONST EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 Function, + IN OUT EFI_SMM_IO_TRAP_REGISTER_CONTEXT *Context, + OUT EFI_HANDLE *Handle) +{ + return RegisterHandler2( EfiSmmIoTrapSmi2, \ + Function, \ + Context, \ + sizeof(EFI_SMM_IO_TRAP_REGISTER_CONTEXT), \ + Handle ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmIoTrapUnregister2 +// +// Description: EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL Unregister function. +// +// Input: *This - Pointer to the EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL +// Handle - Handle to unregister +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmIoTrapUnregister2 ( + IN CONST EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ + return UnregisterHandler2( EfiSmmIoTrapSmi2, Handle ); +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/Smm2/SmmChildDispatch2Protocol.h b/Chipset/SB/Smm2/SmmChildDispatch2Protocol.h new file mode 100644 index 0000000..39d7bd4 --- /dev/null +++ b/Chipset/SB/Smm2/SmmChildDispatch2Protocol.h @@ -0,0 +1,204 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher2/SmmChildDispatch2Protocol.h 1 2/08/12 8:28a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:28a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher2/SmmChildDispatch2Protocol.h $ +// +// 1 2/08/12 8:28a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SmmChildDispatch2Protocol.h +// +// Description: SMM Child dispatcher II protocols functions definition +// +//<AMI_FHDR_END> +//************************************************************************* + +#ifndef __SMM_CHILD_DISPATCH2_PROTOCOL__H__ +#define __SMM_CHILD_DISPATCH2_PROTOCOL__H__ +#ifdef __cplusplus +extern "C" { +#endif + +#include <Protocol\SmmSwDispatch2.h> +#include <Protocol\SmmSxDispatch2.h> +#include <Protocol\SmmPeriodicTimerDispatch2.h> +#include <Protocol\SmmUsbDispatch2.h> +#include <Protocol\SmmGpiDispatch2.h> +#include <Protocol\SmmStandbyButtonDispatch2.h> +#include <Protocol\SmmPowerButtonDispatch2.h> +#include <Protocol\SmmIoTrapDispatch2.h> + +//-------------- Generic register/unregister handler functions -------------- + +EFI_STATUS RegisterHandler2( + IN EFI_SMM_SMI2 Type, + IN SMI_GENERIC_CALLBACK2 Function, + IN CONST VOID *Context, + IN UINTN ContextSize, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS UnregisterHandler2 ( + IN EFI_SMM_SMI2 Type, + IN EFI_HANDLE Handle +); + +//------------------------ Sw SMI protocol functions ------------------------ + +EFI_STATUS EfiSmmSwRegister2 ( + IN CONST EFI_SMM_SW_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 Function, + IN CONST EFI_SMM_SW_REGISTER_CONTEXT *Context, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS EfiSmmSwUnregister2 ( + IN CONST EFI_SMM_SW_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +//------------------------ Sx SMI protocol functions ------------------------ + +EFI_STATUS EfiSmmSxRegister2 ( + IN CONST EFI_SMM_SX_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 Function, + IN CONST EFI_SMM_SX_REGISTER_CONTEXT *Context, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS EfiSmmSxUnregister2 ( + IN CONST EFI_SMM_SX_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +//------------------ Periodic timer SMI protocol functions ------------------ + +EFI_STATUS EfiSmmTimerRegister2 ( + IN CONST EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 Function, + IN CONST EFI_SMM_PERIODIC_TIMER_REGISTER_CONTEXT *Context, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS EfiSmmTimerUnregister2 ( + IN CONST EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +EFI_STATUS EfiSmmTimerGetNextShorterInterval2 ( + IN CONST EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL *This, + IN OUT UINT64 **SmiTickInterval +); + +//----------------------- Usb SMI protocol functions ------------------------ + +EFI_STATUS EfiSmmUsbRegister2 ( + IN CONST EFI_SMM_USB_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 Function, + IN CONST EFI_SMM_USB_REGISTER_CONTEXT *Context, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS EfiSmmUsbUnregister2 ( + IN CONST EFI_SMM_USB_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +//----------------------- Gpi SMI protocol functions ------------------------ + +EFI_STATUS EfiSmmGpiRegister2 ( + IN CONST EFI_SMM_GPI_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 Function, + IN CONST EFI_SMM_GPI_REGISTER_CONTEXT *Context, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS EfiSmmGpiUnregister2 ( + IN CONST EFI_SMM_GPI_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +//------------------ Standby button SMI protocol functions ------------------ + +EFI_STATUS EfiSmmSButtonRegister2 ( + IN CONST EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 Function, + IN CONST EFI_SMM_STANDBY_BUTTON_REGISTER_CONTEXT *Context, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS EfiSmmSButtonUnregister2 ( + IN CONST EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +//------------------- Power button SMI protocol functions ------------------- + +EFI_STATUS EfiSmmPButtonRegister2 ( + IN CONST EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 Function, + IN CONST EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT *Context, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS EfiSmmPButtonUnregister2 ( + IN CONST EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +//--------------------- I/O Trap SMI protocol functions --------------------- + +EFI_STATUS EfiSmmIoTrapRegister2 ( + IN CONST EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 Function, + IN OUT EFI_SMM_IO_TRAP_REGISTER_CONTEXT *Context, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS EfiSmmIoTrapUnregister2 ( + IN CONST EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/Smm2/SmmChildDispatcher2.cif b/Chipset/SB/Smm2/SmmChildDispatcher2.cif new file mode 100644 index 0000000..c02d46b --- /dev/null +++ b/Chipset/SB/Smm2/SmmChildDispatcher2.cif @@ -0,0 +1,16 @@ +<component> + name = "SmmChildDispatcher2" + category = ModulePart + LocalRoot = "Chipset\SB\Smm2" + RefName = "SmmChildDispatcher2" +[files] +"SmmChildDispatcher2.mak" +"SmmChildDispatcher2.sdl" +"SmmChildDispatcher2.dxs" +"SmiHandlerGeneric2.c" +"SmiHandlerPorting2.c" +"SmmChildDispatch2.h" +"SmmChildDispatch2Main.c" +"SmmChildDispatch2Protocol.c" +"SmmChildDispatch2Protocol.h" +<endComponent> diff --git a/Chipset/SB/Smm2/SmmChildDispatcher2.dxs b/Chipset/SB/Smm2/SmmChildDispatcher2.dxs new file mode 100644 index 0000000..2d6cd56 --- /dev/null +++ b/Chipset/SB/Smm2/SmmChildDispatcher2.dxs @@ -0,0 +1,58 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher2/SmmChildDispatcher2.dxs 1 2/08/12 8:28a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:28a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher2/SmmChildDispatcher2.dxs $ +// +// 1 2/08/12 8:28a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SmmChildDispatcher2.DXS +// +// Description: This file contains the dependency expression for the SMM +// Child Dispatcher II driver +// +//<AMI_FHDR_END> +//************************************************************************* + +#include <Protocol\SmmBase2.h> + +DEPENDENCY_START + EFI_SMM_BASE2_PROTOCOL_GUID +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/Smm2/SmmChildDispatcher2.mak b/Chipset/SB/Smm2/SmmChildDispatcher2.mak new file mode 100644 index 0000000..18e5cd7 --- /dev/null +++ b/Chipset/SB/Smm2/SmmChildDispatcher2.mak @@ -0,0 +1,85 @@ +# MAK file for the ModulePart:SmmChildDispatcher II +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher2/SmmChildDispatcher2.mak 2 4/25/12 9:32a Victortu $ +# +# $Revision: 2 $ +# +# $Date: 4/25/12 9:32a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher2/SmmChildDispatcher2.mak $ +# +# 2 4/25/12 9:32a Victortu +# [TAG] None +# [Category] Improvement +# [Description] Reprogram SMM ChildDispatcher drivers. +# [Files] SmiHandlerGeneric.c; SmiHandlerPorting.c; +# SmiHandlerGeneric2.c; SmmChildDispatch2Main.c; SmmChildDispatcher2.mak; +# SmmChildDispatcher2.sdl; SmmChildDispatch.h; SmmChildDispatchMain.c; +# SmmChildDispatchProtocol.c; SmmChildDispatcher.dxs; +# PchSmiDispatcher.sdl +# +# 1 2/08/12 8:28a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: SmmChildDispatcher2.mak +# +# Description: Make file for the SMM Child Dispatcher II driver. +# +#<AMI_FHDR_END> +#************************************************************************* +!IFNDEF BACKWARD_COMPATIBLE_MODE +BACKWARD_COMPATIBLE_MODE = 1 +!ENDIF + +all : SmmChildDispatcher2 + +SmmChildDispatcher2 : $(BUILD_DIR)\SmmChildDispatcher2.mak SmmChildDispatcher2Bin + +$(BUILD_DIR)\SmmChildDispatcher2.mak : $(SMM_CHILD_DISP2_DIR)\SmmChildDispatcher2.cif $(SMM_CHILD_DISP2_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(SMM_CHILD_DISP2_DIR)\SmmChildDispatcher2.cif $(CIF2MAK_DEFAULTS) + +SmmChildDispatcher2Bin : $(AMICSPLib) $(AMIDXELIB) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\SmmChildDispatcher2.mak all\ + "CFLAGS=$(CFLAGS) /I$(SB_BOARD_DIR)"\ + GUID=E53734A3-E594-4c25-B1A2-081445650F7F\ + ENTRY_POINT=SmmChildDispatch2EntryPoint\ + TYPE=DXESMM_DRIVER \ + DEPEX1=$(SMM_CHILD_DISP2_DIR)\SmmChildDispatcher2.dxs \ + DEPEX1_TYPE=EFI_SECTION_SMM_DEPEX \ + DEPEX2=$(SMM_CHILD_DISP2_DIR)\SmmChildDispatcher2.dxs \ + DEPEX2_TYPE=EFI_SECTION_DXE_DEPEX \ + COMPRESS=1 + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/SB/Smm2/SmmChildDispatcher2.sdl b/Chipset/SB/Smm2/SmmChildDispatcher2.sdl new file mode 100644 index 0000000..5540394 --- /dev/null +++ b/Chipset/SB/Smm2/SmmChildDispatcher2.sdl @@ -0,0 +1,135 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher2/SmmChildDispatcher2.sdl 4 1/03/13 7:00a Scottyang $ +# +# $Revision: 4 $ +# +# $Date: 1/03/13 7:00a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher2/SmmChildDispatcher2.sdl $ +# +# 4 1/03/13 7:00a Scottyang +# [TAG] None +# [Category] Bug Fix +# [Severity] Important +# [Symptom] GPISMI cannot use. +# [RootCause] GPISMI2 will clear status before GPISMI. +# [Solution] GPISMI2 do not clear status when GPISMI has register. +# [Files] SmmChildDispatcher2.sdl +# SmiHandlerGeneric2.c +# +# 3 10/19/12 2:52a Scottyang +# [TAG] EIP93461 +# [Category] Bug Fix +# [Severity] Normal +# [Symptom] System halt when AFUDOS is running with /N /ME command. +# [RootCause] An unexpected BIOSWR_STS is set, it causes BIOS stuck +# at SMM dispatcher. +# [Solution] Clear BIOSWR_STS if BIOS Lock Enable is not set. +# [Files] SmiHandlerPorting2.c; SmmChildDispatch2Main.c +# SmmChildDispatcher2.sdl; SmmChildDispatch2.h +# SB\SBGeneric.c +# +# 2 4/25/12 9:32a Victortu +# [TAG] None +# [Category] Improvement +# [Description] Reprogram SMM ChildDispatcher drivers. +# [Files] SmiHandlerGeneric.c; SmiHandlerPorting.c; +# SmiHandlerGeneric2.c; SmmChildDispatch2Main.c; SmmChildDispatcher2.mak; +# SmmChildDispatcher2.sdl; SmmChildDispatch.h; SmmChildDispatchMain.c; +# SmmChildDispatchProtocol.c; SmmChildDispatcher.dxs; +# PchSmiDispatcher.sdl +# +# 1 2/08/12 8:28a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "SmmChildDispatcher2_SUPPORT" + Value = "1" + Help = "Main switch to enable SmmChildDispatcher II support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Token = "PI_SPECIFICATION_VERSION" ">" "0x10000" +End + +TOKEN + Name = "PI_0_9_CHILD_DISPATCHER_SUPPORT" + Value = "1" + Help = "Enable SmmChildDispatcher I support" + TokenType = Boolean + TargetH = Yes +End + + # [EIP93461]> +TOKEN + Name = "BIOS_WRITE_SMI_PATCH_ENABLE" + Value = "1" + Help = "Clear unexpected BIOSWR_STS." + TokenType = Boolean + TargetH = Yes +End + # <[EIP93461] + +TOKEN + Name = "GPI_DISPATCH2_BY_BITMAP" + Value = "0" + Help = "ON = The registered parameter of SMM GPI dispatcher II is using bitmapped.\OFF = The registered parameter of SMM GPI disatcher is using index based" + TokenType = Boolean + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "SUPPORTED_GPIS2" + Value = "0xFFFF" + Help = "This is a supported GPI SMI mask, 1 = supported, 16 bits maximum" + TokenType = Integer + TargetH = Yes +End + +PATH + Name = "SMM_CHILD_DISP2_DIR" +End + +MODULE + Help = "Includes SmmChildDispatcher2.mak to Project" + File = "SmmChildDispatcher2.mak" +End + +ELINK + Name = "$(BUILD_DIR)\SmmChildDispatcher2.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Chipset/SB/SmmChildDispatch.h b/Chipset/SB/SmmChildDispatch.h new file mode 100644 index 0000000..01458d0 --- /dev/null +++ b/Chipset/SB/SmmChildDispatch.h @@ -0,0 +1,369 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher/SmmChildDispatch.h 2 4/25/12 9:35a Victortu $ +// +// $Revision: 2 $ +// +// $Date: 4/25/12 9:35a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher/SmmChildDispatch.h $ +// +// 2 4/25/12 9:35a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Reprogram SMM ChildDispatcher drivers. +// [Files] SmiHandlerGeneric.c; SmiHandlerPorting.c; +// SmiHandlerGeneric2.c; SmmChildDispatch2Main.c; SmmChildDispatcher2.mak; +// SmmChildDispatcher2.sdl; SmmChildDispatch.h; SmmChildDispatchMain.c; +// SmmChildDispatchProtocol.c; SmmChildDispatcher.dxs; +// PchSmiDispatcher.sdl +// +// 1 2/08/12 8:27a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SmmChildDispatch.h +// +// Description: SMM Child dispatcher functions and data structures +// definition. +// +//<AMI_FHDR_END> +//************************************************************************* + +#ifndef __SMM_CHILD_DISPATCH__H__ +#define __SMM_CHILD_DISPATCH__H__ +#ifdef __cplusplus +extern "C" { +#endif + +#include <AmiDxeLib.h> +#include <Protocol\SmmSwDispatch.h> +#include <Protocol\SmmSxDispatch.h> +#include <Protocol\SmmPeriodicTimerDispatch.h> +#include <Protocol\SmmUsbDispatch.h> +#include <Protocol\SmmGpiDispatch.h> +#include <Protocol\SmmStandbyButtonDispatch.h> +#include <Protocol\SmmPowerButtonDispatch.h> +#include <Protocol\SmmTcoDispatch.h> +#include <Protocol\SmmIoTrapDispatch.h> + +#include <Protocol\SmmBiosWriteDispatch.h> + +#ifndef INTEL_RC_SMI_DISPATCHER_SUPPORT +#define INTEL_RC_SMI_DISPATCHER_SUPPORT 0 +#endif + +#pragma pack(push, 1) + +typedef enum { + EfiSmmSwSmi, + EfiSmmSxSmi, + EfiSmmPeriodicTimerSmi, + EfiSmmUsbSmi, + EfiSmmGpiSmi, + EfiSmmStandbyButtonSmi, + EfiSmmPowerButtonSmi, + EfiSmmTcoSmi, + EfiSmmIoTrapSmi, + EfiSmmMaxSmi +} EFI_SMM_SMI; + +typedef union { + EFI_SMM_SW_DISPATCH_CONTEXT SwContext; + EFI_SMM_SX_DISPATCH_CONTEXT SxContext; + EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT TimerContext; + EFI_SMM_USB_DISPATCH_CONTEXT UsbContext; + EFI_SMM_GPI_DISPATCH_CONTEXT GpiContext; + EFI_SMM_STANDBY_BUTTON_DISPATCH_CONTEXT SBtnContext; + EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT PBtnContext; + EFI_SMM_TCO_DISPATCH_CONTEXT TcoContext; + EFI_SMM_IO_TRAP_DISPATCH_CONTEXT IoTrapContext; +} EFI_SMM_SMI_CONTEXT; + +typedef VOID ( *SMI_GENERIC_CALLBACK ) ( + IN EFI_HANDLE DispatchHandle, + IN VOID *DispatchContext +); + +typedef struct { + DLINK Link; + UINT32 Signature; + SMI_GENERIC_CALLBACK Callback; + UINT8 Context[1]; +} HANDLER_LINK; + +typedef VOID ( *SMI_GENERIC_NEW_CALLBACK ) ( + IN EFI_HANDLE DispatchHandle, + IN VOID *DispatchContext, + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommBufferSize +); + + +typedef struct { + DLINK Link; + UINT32 Signature; + SMI_GENERIC_NEW_CALLBACK Callback; + UINT8 Context[1]; +} HANDLER_NEW_LINK; + +//--------------------------------------------------------------------------- +// SMI Handler protocol functions prototypes +//--------------------------------------------------------------------------- + +typedef EFI_STATUS ( *ADD_HANDLER ) ( + IN VOID *Context +); + +typedef EFI_STATUS ( *REMOVE_HANDLER ) ( + IN VOID *Context +); + +typedef EFI_STATUS ( *VERIFY_CONTEXT) ( + IN VOID *Context +); + +typedef BOOLEAN ( *GET_CONTEXT ) ( + VOID +); + +typedef VOID ( *DISPATCH_SMI ) ( + VOID +); + +typedef struct { + ADD_HANDLER AddHandler; + REMOVE_HANDLER RemoveHandler; + VERIFY_CONTEXT VerifyContext; + GET_CONTEXT GetContext; + DISPATCH_SMI DispatchSmi; +} SMI_HANDLER_PROTOCOL; + +typedef struct { + EFI_SMM_SMI SmiType; + SMI_HANDLER_PROTOCOL HandlerProtocol; + DLIST RegisteredCallbacks; +} SMM_CHILD_DISPATCHER; + +#pragma pack(pop) + +//--------------------------------------------------------------------------- +// SW SMI Handler functions +//--------------------------------------------------------------------------- + +EFI_STATUS SmmSwAddHandler( IN VOID *Context ); +EFI_STATUS SmmSwRemoveHandler( IN VOID *Context ); +EFI_STATUS SmmSwVerifyContext( IN VOID *Context ); +BOOLEAN SmmSwGetContext( VOID ); +VOID SmmSwDispatchSmi( VOID ); + +//---------------------- SW SMI Handler Porting hooks ----------------------- + +VOID SwSmiEnable( VOID ); +VOID SwSmiDisable( VOID ); +VOID SwSmiClear( VOID ); +BOOLEAN SwSmiDetect( OUT UINT16 *Type ); +UINTN GetEAX( VOID ); + +//--------------------------------------------------------------------------- +// SX SMI Handler functions +//--------------------------------------------------------------------------- + +EFI_STATUS SmmSxAddHandler( IN VOID *Context ); +EFI_STATUS SmmSxRemoveHandler( IN VOID *Context ); +EFI_STATUS SmmSxVerifyContext( IN VOID *Context ); +BOOLEAN SmmSxGetContext( VOID ); +VOID SmmSxDispatchSmi( VOID ); + +//---------------------- SX SMI Handler Porting hooks ----------------------- + +VOID SxSmiEnable( VOID ); +VOID SxSmiDisable( VOID ); +VOID SxSmiClear( VOID ); +VOID PutToSleep( IN VOID *Context ); +BOOLEAN SxSmiDetect( OUT UINT16 *Type ); + +//--------------------------------------------------------------------------- +// Periodic timer SMI Handler functions +//--------------------------------------------------------------------------- + +EFI_STATUS SmmTimerAddHandler( IN VOID *Context ); +EFI_STATUS SmmTimerRemoveHandler( IN VOID *Context ); +EFI_STATUS SmmTimerVerifyContext( IN VOID *Context ); +BOOLEAN SmmTimerGetContext( VOID ); +VOID SmmTimerDispatchSmi( VOID ); + +//---------------- Periodic timer SMI Handler Porting hooks ----------------- + +VOID TimerSmiEnable( VOID ); +VOID TimerSmiDisable( VOID ); +VOID TimerSmiClear( VOID ); +BOOLEAN TimerSmiDetect( OUT UINT16 *Type ); +VOID TimerSetInterval( IN UINT64 Interval); + +//--------------------------------------------------------------------------- +// USB SMI Handler functions +//--------------------------------------------------------------------------- + +EFI_STATUS SmmUsbAddHandler( IN VOID *Context ); +EFI_STATUS SmmUsbRemoveHandler( IN VOID *Context ); +EFI_STATUS SmmUsbVerifyContext( IN VOID *Context ); +BOOLEAN SmmUsbGetContext( VOID ); +VOID SmmUsbDispatchSmi( VOID ); + +//---------------------- USB SMI Handler Porting hooks ---------------------- + +VOID UsbSmiSet( IN UINT16 ControllerType ); +VOID UsbSmiClear( IN UINT16 ControllerType ); +BOOLEAN UsbSmiDetect( OUT UINT16 *Type ); +UINT16 GetControllerType( OUT EFI_DEVICE_PATH_PROTOCOL *Device ); + +//--------------------------------------------------------------------------- +// GPI SMI Handler functions +//--------------------------------------------------------------------------- + +EFI_STATUS SmmGpiAddHandler( IN VOID *Context ); +EFI_STATUS SmmGpiRemoveHandler( IN VOID *Context ); +EFI_STATUS SmmGpiVerifyContext( IN VOID *Context ); +BOOLEAN SmmGpiGetContext( VOID ); +VOID SmmGpiDispatchSmi( VOID ); + +//---------------------- GPI SMI Handler Porting hooks ---------------------- + +VOID GpiSmiSet( IN UINT32 GpiEnableBit ); +VOID GpiSmiReset( IN UINT32 GpiDisableBit ); +VOID GpiSmiClear( IN UINT32 GpiClearBit ); +BOOLEAN GpiSmiDetect( OUT UINT32 *Gpi ); + +//--------------------------------------------------------------------------- +// Standby button SMI Handler functions +//--------------------------------------------------------------------------- + +EFI_STATUS SmmSButtonAddHandler( IN VOID *Context ); +EFI_STATUS SmmSButtonRemoveHandler( IN VOID *Context ); +EFI_STATUS SmmSButtonVerifyContext( IN VOID *Context ); +BOOLEAN SmmSButtonGetContext( VOID ); +VOID SmmSButtonDispatchSmi( VOID ); + +//---------------- Standby button SMI Handler Porting hooks ----------------- + +VOID SButtonSmiEnable( VOID ); +VOID SButtonSmiDisable( VOID ); +VOID SButtonSmiClear( VOID ); +BOOLEAN SButtonSmiDetect( OUT UINT16 *Type ); + +//--------------------------------------------------------------------------- +// Power button SMI Handler functions +//--------------------------------------------------------------------------- + +EFI_STATUS SmmPButtonAddHandler( IN VOID *Context ); +EFI_STATUS SmmPButtonRemoveHandler( IN VOID *Context ); +EFI_STATUS SmmPButtonVerifyContext( IN VOID *Context ); +BOOLEAN SmmPButtonGetContext( VOID ); +VOID SmmPButtonDispatchSmi( VOID ); + +//---------------- Power button SMI Handler Porting hooks ------------------- + +VOID PButtonSmiEnable( VOID ); +VOID PButtonSmiDisable( VOID ); +VOID PButtonSmiClear( VOID ); +BOOLEAN PButtonSmiDetect( OUT UINT16 *Type ); + +//--------------------------------------------------------------------------- +// TCO SMI Handler functions +//--------------------------------------------------------------------------- + +EFI_STATUS SmmTcoAddHandler( IN VOID *Context ); +EFI_STATUS SmmTcoRemoveHandler( IN VOID *Context ); +EFI_STATUS SmmTcoVerifyContext( IN VOID *Context ); +BOOLEAN SmmTcoGetContext( VOID ); +VOID SmmTcoDispatchSmi( VOID ); + +//--------------------- TCO SMI Handler Porting hooks ----------------------- + +VOID TcoSmiSet( IN UINT32 TcoBitOffset ); +VOID TcoSmiReset( IN UINT32 TcoBitOffset ); +VOID TcoSmiEnable( VOID ); +VOID TcoSmiDisable( VOID ); +VOID TcoSmiClear( VOID ); +BOOLEAN TcoSmiDetect( OUT UINT32 *TcoStatus ); + +//--------------------------------------------------------------------------- +// I/O Trap SMI Handler functions +//--------------------------------------------------------------------------- + +EFI_STATUS SmmIoTrapAddHandler( IN VOID *Context ); +EFI_STATUS SmmIoTrapRemoveHandler( IN VOID *Context ); +EFI_STATUS SmmIoTrapVerifyContext( IN VOID *Context ); +BOOLEAN SmmIoTrapGetContext( VOID ); +VOID SmmIoTrapDispatchSmi( VOID ); + +//------------------ I/O Trap SMI Handler Porting hooks --------------------- + +VOID IoTrapSmiSet( IN EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *Context ); +VOID IoTrapSmiReset( IN EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *Context ); +VOID IoTrapSmiEnable( VOID ); +VOID IoTrapSmiDisable( VOID ); +VOID IoTrapSmiClear( VOID ); +BOOLEAN IoTrapSmiDetect( OUT EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *Context ); + +//--------------------------------------------------------------------------- +// BIOS Write SMI Handler functions +//--------------------------------------------------------------------------- + +EFI_STATUS SmmBiosWriteAddHandler( IN VOID *Context ); +EFI_STATUS SmmBiosWriteRemoveHandler( IN VOID *Context ); +EFI_STATUS SmmBiosWriteVerifyContext( IN VOID *Context ); +BOOLEAN SmmBiosWriteGetContext( VOID ); +VOID SmmBiosWriteDispatchSmi( VOID ); + +//----------------- BIOS Write SMI Handler Porting hooks -------------------- + +VOID BiosWriteSmiEnable( VOID ); +VOID BiosWriteSmiDisable( VOID ); +VOID BiosWriteSmiClear( VOID ); +BOOLEAN BiosWriteSmiDetect( VOID ); + +//--------------------------------------------------------------------------- +// All purpose SMI Porting hooks +//--------------------------------------------------------------------------- +VOID ClearAllSmi( VOID ); + +VOID SbSmiWorkaround( VOID ); + +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/SmmChildDispatchMain.c b/Chipset/SB/SmmChildDispatchMain.c new file mode 100644 index 0000000..650c5fa --- /dev/null +++ b/Chipset/SB/SmmChildDispatchMain.c @@ -0,0 +1,437 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher/SmmChildDispatchMain.c 2 4/25/12 9:35a Victortu $ +// +// $Revision: 2 $ +// +// $Date: 4/25/12 9:35a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher/SmmChildDispatchMain.c $ +// +// 2 4/25/12 9:35a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Reprogram SMM ChildDispatcher drivers. +// [Files] SmiHandlerGeneric.c; SmiHandlerPorting.c; +// SmiHandlerGeneric2.c; SmmChildDispatch2Main.c; SmmChildDispatcher2.mak; +// SmmChildDispatcher2.sdl; SmmChildDispatch.h; SmmChildDispatchMain.c; +// SmmChildDispatchProtocol.c; SmmChildDispatcher.dxs; +// PchSmiDispatcher.sdl +// +// 1 2/08/12 8:27a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SmmChildDispatchMain.c +// +// Description: This file contains implementation of module entry point, +// generic RegisterHandler and UnregisterHandler routines +// and main dispatcher loop. +// +//<AMI_FHDR_END> +//************************************************************************* + +//--------------------------------------------------------------------------- +// Include(s) +//--------------------------------------------------------------------------- + +#include <AmiCspLib.h> +#include <Smm.h> +#include "SmmChildDispatch.h" +#include "SmmChildDispatchProtocol.h" + +//--------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//--------------------------------------------------------------------------- +// Constant Definition(s) +#define SMI_HANDLER_SIGNATURE 0x48494d53 //SMIH + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//--------------------------------------------------------------------------- +// Variable and External Declaration(s) +//--------------------------------------------------------------------------- +// Variable Declaration(s) + +EFI_SMM_SMI_CONTEXT SmiContext; +SB_ASL_BUFFER *gSbAslBufPtr = NULL; + +// GUID Definition(s) + +// Protocol Definition(s) + +// External Declaration(s) + +extern EFI_SMM_SYSTEM_TABLE *pSmst; +extern SMM_CHILD_DISPATCHER SmmHandler[]; + +#if INTEL_RC_SMI_DISPATCHER_SUPPORT == 0 +extern EFI_SMM_SW_DISPATCH_PROTOCOL gEfiSmmSwDispatchProtocol; +extern EFI_SMM_SX_DISPATCH_PROTOCOL gEfiSmmSxDispatchProtocol; +extern EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL gEfiSmmPeriodicTimerDispatchProtocol; +extern EFI_SMM_USB_DISPATCH_PROTOCOL gEfiSmmUsbDispatchProtocol; +extern EFI_SMM_GPI_DISPATCH_PROTOCOL gEfiSmmGpiDispatchProtocol; +#endif +extern EFI_SMM_STANDBY_BUTTON_DISPATCH_PROTOCOL gEfiSmmStandbyButtonDispatchProtocol; +#if INTEL_RC_SMI_DISPATCHER_SUPPORT == 0 +extern EFI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL gEfiSmmPowerButonDispatchProtocol; +extern EFI_SMM_TCO_DISPATCH_PROTOCOL gEfiSmmTcoDispatchProtocol; +extern EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL gEfiSmmIoTrapDispatchProtocol; +#endif + +// Function Definition(s) + +#if (INTEL_RC_SMI_DISPATCHER_SUPPORT == 1) && (PI_0_9_CHILD_DISPATCHER_SUPPORT == 1) +static BOOLEAN PowerBtnSmi = FALSE; + +VOID PowerButtonActivated( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT *DispatchContext + ) +{ + PowerBtnSmi = TRUE; +} + +VOID AfterChildDispatcher(VOID) +{ + if (PowerBtnSmi) + { + PButtonSmiClear(); + SBLib_Shutdown(); + PowerBtnSmi = FALSE; + } +} + +VOID InstallAfterChildDispatcher(VOID) +{ + EFI_STATUS Status; + EFI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL *PowerButton; + EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT DispatchContext = {PowerButtonEntry}; + EFI_HANDLE hPowerButton; + + Status = pBS->LocateProtocol( + &gEfiSmmPowerButtonDispatchProtocolGuid, + NULL, + &PowerButton); + if (!EFI_ERROR(Status)) + { + Status = PowerButton->Register( + PowerButton, + PowerButtonActivated, + &DispatchContext, + &hPowerButton); + ASSERT_EFI_ERROR(Status); + } +} +#endif + +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RegisterHandler +// +// Description: This function registers SMI handler and returns registered +// handle +// +// Input: Type - Type of SMI handler +// Function - Pointer to callback function +// *Context - Pointer to callback context +// ContextSize - Callback context size +// *Handle - Pointer to store registered handle +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS RegisterHandler ( + IN EFI_SMM_SMI Type, + IN VOID *Function, + IN VOID *Context, + IN UINTN ContextSize, + OUT EFI_HANDLE *Handle ) +{ + EFI_STATUS Status; + HANDLER_LINK *HandlerLink; + Status = SmmHandler[Type].HandlerProtocol.VerifyContext( Context ); + if(EFI_ERROR(Status)) return Status; + + Status = pSmst->SmmAllocatePool( 0, + sizeof(HANDLER_LINK) + ContextSize - 1, + &HandlerLink ); + if(EFI_ERROR(Status)) return Status; + + HandlerLink->Callback = Function; + HandlerLink->Signature = SMI_HANDLER_SIGNATURE; + MemCpy( HandlerLink->Context, Context, ContextSize ); + + DListAdd(&(SmmHandler[Type].RegisteredCallbacks), (DLINK *)HandlerLink); + SmmHandler[Type].HandlerProtocol.AddHandler( HandlerLink->Context ); + *Handle = HandlerLink; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: FindHandler +// +// Description: This function find the handle in the Type of SMI hander list. +// +// Input: Type - Type of SMI handler +// Handle - Handle of found handler +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS FindHandler( + IN EFI_SMM_SMI Type, + IN EFI_HANDLE Handle) +{ + HANDLER_LINK *HandlerLink = (HANDLER_LINK *)Handle; + HANDLER_LINK *NodeLink = NULL; + + if (HandlerLink->Signature != SMI_HANDLER_SIGNATURE) + return EFI_INVALID_PARAMETER; + + if (SmmHandler[Type].RegisteredCallbacks.Size <= 0) + return EFI_UNSUPPORTED; + + NodeLink = (HANDLER_LINK *)SmmHandler[Type].RegisteredCallbacks.pHead; + for (; NodeLink != NULL; NodeLink = (HANDLER_LINK *)NodeLink->Link.pNext) + { + if (NodeLink == HandlerLink) + return EFI_SUCCESS; + } + + return EFI_UNSUPPORTED; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: UnregisterHandler +// +// Description: This function unregisters SMI handler with given handle +// +// Input: Type - Type of SMI handler +// Handle - Handle of registered handler +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS UnregisterHandler ( + IN EFI_SMM_SMI Type, + IN EFI_HANDLE Handle ) +{ + EFI_STATUS Status; + HANDLER_LINK *HandlerLink = (HANDLER_LINK *)Handle; + + Status = FindHandler(Type, Handle); + if (Status == EFI_SUCCESS) + { + SmmHandler[Type].HandlerProtocol.RemoveHandler( HandlerLink->Context ); + DListDelete( &(SmmHandler[Type].RegisteredCallbacks), (DLINK *)HandlerLink ); + pSmst->SmmFreePool( HandlerLink ); + } + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ChildDispatcher +// +// Description: This function implements main SMI dispatcher loop +// +// Input: SmmImageHandle - SMM Image handle +// *CommunicationBuffer - Pointer to optional communication +// buffer +// *SourceSize - Pointer to size of communication +// buffer +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS ChildDispatcher ( + IN EFI_HANDLE SmmImageHandle, + IN OUT VOID *CommunicationBuffer OPTIONAL, + IN OUT UINTN *SourceSize OPTIONAL ) +{ + UINT32 Index; + BOOLEAN HandledSmi; + + do { + HandledSmi = FALSE; + for (Index = EfiSmmStandbyButtonSmi; Index < EfiSmmMaxSmi; Index++) + { + if (SmmHandler[Index].HandlerProtocol.GetContext != NULL && + SmmHandler[Index].HandlerProtocol.GetContext()) + { + SmmHandler[Index].HandlerProtocol.DispatchSmi(); + HandledSmi = TRUE; + } + } + } while (HandledSmi); + + SbSmiWorkaround(); + +#if (INTEL_RC_SMI_DISPATCHER_SUPPORT == 1) && (PI_0_9_CHILD_DISPATCHER_SUPPORT == 1) + AfterChildDispatcher(); +#endif + + return EFI_HANDLER_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InSmmFunction +// +// Description: This function initializes Child dispatcher in SMM mode +// +// Input: ImageHandle - Image handle +// *SystemTable - Pointer to system table +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS InSmmFunction( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status; + EFI_GUID SbAslBufPtrGuid = SB_ASL_BUFFER_PTR_GUID; + CHAR16 SbAslBufPtrVar[] = SB_ASL_BUFFER_PTR_VARIABLE; + EFI_HANDLE Handle = NULL; + UINTN VarSize = sizeof(UINT32); + UINT32 SbAslBufPtr; + + ClearAllSmi(); + + Status = pRS->GetVariable( SbAslBufPtrVar, + &SbAslBufPtrGuid, + NULL, + &VarSize, + &SbAslBufPtr ); + if (!EFI_ERROR(Status)) gSbAslBufPtr = (SB_ASL_BUFFER *)SbAslBufPtr; + + // Install Protocols + Status = pBS->InstallMultipleProtocolInterfaces( + &Handle, + +#if INTEL_RC_SMI_DISPATCHER_SUPPORT == 0 + &gEfiSmmSwDispatchProtocolGuid, + &gEfiSmmSwDispatchProtocol, + + &gEfiSmmSxDispatchProtocolGuid, + &gEfiSmmSxDispatchProtocol, + + &gEfiSmmPeriodicTimerDispatchProtocolGuid, + &gEfiSmmPeriodicTimerDispatchProtocol, + + &gEfiSmmUsbDispatchProtocolGuid, + &gEfiSmmUsbDispatchProtocol, + + &gEfiSmmGpiDispatchProtocolGuid, + &gEfiSmmGpiDispatchProtocol, +#endif + + &gEfiSmmStandbyButtonDispatchProtocolGuid, + &gEfiSmmStandbyButtonDispatchProtocol, + +#if INTEL_RC_SMI_DISPATCHER_SUPPORT == 0 + &gEfiSmmPowerButtonDispatchProtocolGuid, + &gEfiSmmPowerButonDispatchProtocol, + + &gEfiSmmTcoDispatchProtocolGuid, + &gEfiSmmTcoDispatchProtocol, + + &gEfiSmmIoTrapDispatchProtocolGuid, + &gEfiSmmIoTrapDispatchProtocol, + + &gEfiSmmBiosWriteDispatchProtocolGuid, + &gEfiSmmBiosWriteDispatchProtocol, +#endif + + NULL ); + ASSERT_EFI_ERROR(Status); + + Status = pSmmBase->RegisterCallback( pSmmBase, + ImageHandle, + ChildDispatcher, + TRUE, + FALSE ); + ASSERT_EFI_ERROR(Status); + +#if (INTEL_RC_SMI_DISPATCHER_SUPPORT == 1) && (PI_0_9_CHILD_DISPATCHER_SUPPORT == 1) + InstallAfterChildDispatcher(); +#endif + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SmmChildDispatchEntryPoint +// +// Description: SMM Child Dispatcher module entry point +// +// Input: ImageHandle - Image handle +// *SystemTable - Pointer to system table +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SmmChildDispatchEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + InitAmiLib( ImageHandle,SystemTable ); + + return InitSmmHandler( ImageHandle, SystemTable, InSmmFunction, NULL ); +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/SmmChildDispatchProtocol.c b/Chipset/SB/SmmChildDispatchProtocol.c new file mode 100644 index 0000000..b56d925 --- /dev/null +++ b/Chipset/SB/SmmChildDispatchProtocol.c @@ -0,0 +1,961 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher/SmmChildDispatchProtocol.c 2 4/25/12 9:35a Victortu $ +// +// $Revision: 2 $ +// +// $Date: 4/25/12 9:35a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher/SmmChildDispatchProtocol.c $ +// +// 2 4/25/12 9:35a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Reprogram SMM ChildDispatcher drivers. +// [Files] SmiHandlerGeneric.c; SmiHandlerPorting.c; +// SmiHandlerGeneric2.c; SmmChildDispatch2Main.c; SmmChildDispatcher2.mak; +// SmmChildDispatcher2.sdl; SmmChildDispatch.h; SmmChildDispatchMain.c; +// SmmChildDispatchProtocol.c; SmmChildDispatcher.dxs; +// PchSmiDispatcher.sdl +// +// 1 2/08/12 8:27a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SmmChildDispatchProtocol.c +// +// Description: This file contains SMM Child dispatcher Protocols +// +//<AMI_FHDR_END> +//************************************************************************* + +//--------------------------------------------------------------------------- +// Include(s) +//--------------------------------------------------------------------------- + +#include <Token.h> +#include <AmiDxeLib.h> +#include "SmmChildDispatch.h" +#include "SmmChildDispatchProtocol.h" + +//--------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//--------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//--------------------------------------------------------------------------- +// Variable and External Declaration(s) +//--------------------------------------------------------------------------- +// Variable Declaration(s) + +#if INTEL_RC_SMI_DISPATCHER_SUPPORT == 0 +SMM_CHILD_DISPATCHER SmmHandler[] = { + // SwSmmHandler + EfiSmmSwSmi, + { SmmSwAddHandler, + SmmSwRemoveHandler, + SmmSwVerifyContext, + SmmSwGetContext, + SmmSwDispatchSmi }, + { 0, NULL, NULL }, + + // SxSmmHandler + EfiSmmSxSmi, + { SmmSxAddHandler, + SmmSxRemoveHandler, + SmmSxVerifyContext, + SmmSxGetContext, + SmmSxDispatchSmi }, + { 0, NULL, NULL }, + + // PeriodicTimerSmmHandler + EfiSmmPeriodicTimerSmi, + { SmmTimerAddHandler, + SmmTimerRemoveHandler, + SmmTimerVerifyContext, + SmmTimerGetContext, + SmmTimerDispatchSmi }, + { 0, NULL, NULL }, + + // UsbSmmHandler + EfiSmmUsbSmi, + { SmmUsbAddHandler, + SmmUsbRemoveHandler, + SmmUsbVerifyContext, + SmmUsbGetContext, + SmmUsbDispatchSmi }, + { 0, NULL, NULL }, + + // GpiSmmHandler + EfiSmmGpiSmi, + { SmmGpiAddHandler, + SmmGpiRemoveHandler, + SmmGpiVerifyContext, + SmmGpiGetContext, + SmmGpiDispatchSmi }, + { 0, NULL, NULL }, + + // SButtonSmmHandler + EfiSmmStandbyButtonSmi, + { SmmSButtonAddHandler, + SmmSButtonRemoveHandler, + SmmSButtonVerifyContext, + SmmSButtonGetContext, + SmmSButtonDispatchSmi }, + { 0, NULL, NULL }, + + // PButtonSmmHandler + EfiSmmPowerButtonSmi, + { SmmPButtonAddHandler, + SmmPButtonRemoveHandler, + SmmPButtonVerifyContext, + SmmPButtonGetContext, + SmmPButtonDispatchSmi }, + { 0, NULL, NULL }, + + // TcoSmmHandler + EfiSmmTcoSmi, + { SmmTcoAddHandler, + SmmTcoRemoveHandler, + SmmTcoVerifyContext, + SmmTcoGetContext, + SmmTcoDispatchSmi }, + { 0, NULL, NULL }, + + // IoTrapSmmHandler + EfiSmmIoTrapSmi, + { SmmIoTrapAddHandler, + SmmIoTrapRemoveHandler, + SmmIoTrapVerifyContext, + SmmIoTrapGetContext, + SmmIoTrapDispatchSmi }, + { 0, NULL, NULL }, + +//********************** PUT ADDITIONAL HANDLERS HERE *********************** +//********************** PUT ADDITIONAL HANDLERS HERE *********************** +//********************** PUT ADDITIONAL HANDLERS HERE *********************** + + // Terminator record + EfiSmmMaxSmi, + { NULL, NULL, NULL, NULL, NULL }, + { 0, NULL, NULL } +}; +#else +SMM_CHILD_DISPATCHER SmmHandler[] = { + // SwSmmHandler + (EfiSmmMaxSmi + 1), + { NULL, + NULL, + NULL, + NULL, + NULL }, + { 0, NULL, NULL }, + + // SxSmmHandler + (EfiSmmMaxSmi + 1), + { NULL, + NULL, + NULL, + NULL, + NULL }, + { 0, NULL, NULL }, + + // PeriodicTimerSmmHandler + (EfiSmmMaxSmi + 1), + { NULL, + NULL, + NULL, + NULL, + NULL }, + { 0, NULL, NULL }, + + // UsbSmmHandler + (EfiSmmMaxSmi + 1), + { NULL, + NULL, + NULL, + NULL, + NULL }, + { 0, NULL, NULL }, + + // GpiSmmHandler + (EfiSmmMaxSmi + 1), + { NULL, + NULL, + NULL, + NULL, + NULL }, + { 0, NULL, NULL }, + + // SButtonSmmHandler + EfiSmmStandbyButtonSmi, + { SmmSButtonAddHandler, + SmmSButtonRemoveHandler, + SmmSButtonVerifyContext, + SmmSButtonGetContext, + SmmSButtonDispatchSmi }, + { 0, NULL, NULL }, + + // PButtonSmmHandler + (EfiSmmMaxSmi + 1), + { NULL, + NULL, + NULL, + NULL, + NULL }, + { 0, NULL, NULL }, + + // TcoSmmHandler + (EfiSmmMaxSmi + 1), + { NULL, + NULL, + NULL, + NULL, + NULL }, + { 0, NULL, NULL }, + + // IoTrapSmmHandler + (EfiSmmMaxSmi + 1), + { NULL, + NULL, + NULL, + NULL, + NULL }, + { 0, NULL, NULL }, + +//********************** PUT ADDITIONAL HANDLERS HERE *********************** +//********************** PUT ADDITIONAL HANDLERS HERE *********************** +//********************** PUT ADDITIONAL HANDLERS HERE *********************** + + // Terminator record + EfiSmmMaxSmi, + { NULL, NULL, NULL, NULL, NULL }, + { 0, NULL, NULL } +}; +#endif + +EFI_SMM_SW_DISPATCH_PROTOCOL gEfiSmmSwDispatchProtocol = \ + { EfiSmmSwRegister, \ + EfiSmmSwUnregister, \ + MAX_SW_SMI_INPUT_VALUE }; + +EFI_SMM_SX_DISPATCH_PROTOCOL gEfiSmmSxDispatchProtocol = \ + { EfiSmmSxRegister, EfiSmmSxUnregister }; + +EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL gEfiSmmPeriodicTimerDispatchProtocol= + { EfiSmmTimerRegister, \ + EfiSmmTimerUnregister, \ + EfiSmmTimerGetNextShorterInterval }; + +EFI_SMM_USB_DISPATCH_PROTOCOL gEfiSmmUsbDispatchProtocol = \ + { EfiSmmUsbRegister, EfiSmmUsbUnregister }; + +EFI_SMM_GPI_DISPATCH_PROTOCOL gEfiSmmGpiDispatchProtocol = \ + { EfiSmmGpiRegister, \ + EfiSmmGpiUnregister, \ + SUPPORTED_GPIS }; + +EFI_SMM_STANDBY_BUTTON_DISPATCH_PROTOCOL gEfiSmmStandbyButtonDispatchProtocol= + { EfiSmmSButtonRegister, EfiSmmSButtonUnregister }; + +EFI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL gEfiSmmPowerButonDispatchProtocol = \ + { EfiSmmPButtonRegister, EfiSmmPButtonUnregister }; + +EFI_SMM_TCO_DISPATCH_PROTOCOL gEfiSmmTcoDispatchProtocol = \ + { EfiSmmTcoRegister, EfiSmmTcoUnregister }; + +EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL gEfiSmmIoTrapDispatchProtocol = \ + { EfiSmmIoTrapRegister, EfiSmmIoTrapUnregister }; + +// GUID Definition(s) + +// Protocol Definition(s) + +// External Declaration(s) + +extern UINT64 gSupportedIntervals[]; + +// Function Definition(s) + +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmSwRegister +// +// Description: EFI_SMM_SW_DISPATCH_PROTOCOL Register function. +// +// Input: *This - Pointer to EFI_SMM_SW_DISPATCH_PROTOCOL +// Function - Pointer to callback function +// *Context - Pointer to callback context +// *Handle - Pointer to store registered handle +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmSwRegister ( + IN EFI_SMM_SW_DISPATCH_PROTOCOL *This, + IN EFI_SMM_SW_DISPATCH Function, + IN EFI_SMM_SW_DISPATCH_CONTEXT *Context, + OUT EFI_HANDLE *Handle ) +{ +//#### Use Intel RC return RegisterHandler( EfiSmmSwSmi, \ +//#### Use Intel RC Function, \ +//#### Use Intel RC Context, \ +//#### Use Intel RC sizeof(EFI_SMM_SW_DISPATCH_CONTEXT), \ +//#### Use Intel RC Handle ); + return EFI_NOT_FOUND; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmSwUnregister +// +// Description: EFI_SMM_SW_DISPATCH_PROTOCOL Unregister function. +// +// Input: *This - Pointer to the EFI_SMM_SW_DISPATCH_PROTOCOL +// Handle - Handle to unregister +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmSwUnregister ( + IN EFI_SMM_SW_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ +//#### Use Intel RC return UnregisterHandler( EfiSmmSwSmi, Handle ); + return EFI_NOT_FOUND; +} + +//--------------------------------------------------------------------------- +// Sleep SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmSxRegister +// +// Description: EFI_SMM_SX_DISPATCH_PROTOCOL Register function. +// +// Input: *This - Pointer to EFI_SMM_SX_DISPATCH_PROTOCOL +// Function - Pointer to callback function +// *Context - Pointer to callback context +// *Handle - Pointer to store registered handle +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmSxRegister ( + IN EFI_SMM_SX_DISPATCH_PROTOCOL *This, + IN EFI_SMM_SX_DISPATCH Function, + IN EFI_SMM_SX_DISPATCH_CONTEXT *Context, + OUT EFI_HANDLE *Handle ) +{ +//#### Use Intel RC return RegisterHandler( EfiSmmSxSmi, \ +//#### Use Intel RC Function, \ +//#### Use Intel RC Context, \ +//#### Use Intel RC sizeof(EFI_SMM_SX_DISPATCH_CONTEXT), \ +//#### Use Intel RC Handle ); + return EFI_NOT_FOUND; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmSxUnregister +// +// Description: EFI_SMM_SW_DISPATCH_PROTOCOL Unregister function. +// +// Input: *This - Pointer to the EFI_SMM_SX_DISPATCH_PROTOCOL +// Handle - Handle to unregister +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmSxUnregister ( + IN EFI_SMM_SX_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ +//#### Use Intel RC return UnregisterHandler( EfiSmmSxSmi, Handle ); + return EFI_NOT_FOUND; +} + +//--------------------------------------------------------------------------- +// Periodic timer SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmTimerRegister +// +// Description: EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL Register function. +// +// Input: *This - Pointer to EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL +// Function - Pointer to callback function +// *Context - Pointer to callback context +// *Handle - Pointer to store registered handle +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmTimerRegister ( + IN EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL *This, + IN EFI_SMM_PERIODIC_TIMER_DISPATCH Function, + IN EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *Context, + OUT EFI_HANDLE *Handle ) +{ +//#### Use Intel RC return RegisterHandler( EfiSmmPeriodicTimerSmi, \ +//#### Use Intel RC Function, \ +//#### Use Intel RC Context, \ +//#### Use Intel RC sizeof(EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT), \ +//#### Use Intel RC Handle ); + return EFI_NOT_FOUND; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmTimerUnregister +// +// Description: EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL Unregister function. +// +// Input: *This - Pointer to the +// EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL +// Handle - Handle to unregister +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmTimerUnregister ( + IN EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ +//#### Use Intel RC return UnregisterHandler( EfiSmmPeriodicTimerSmi, Handle ); + return EFI_NOT_FOUND;; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmTimerGetNextShorterInterval +// +// Description: EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL +// GetNextShorterInterval function. +// +// Input: *This - Pointer to the +// EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL +// **SmiTickInterval - Pointer to store pointer to next interval +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmTimerGetNextShorterInterval ( + IN EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL *This, + IN OUT UINT64 **SmiTickInterval ) +{ + UINT64 *Result = *SmiTickInterval; + + if (Result == NULL) { + Result = gSupportedIntervals; + } else { + Result++; + } + *SmiTickInterval = (*Result == 0) ? NULL : Result; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmGetPeriodicTimerSourcesStatus +// +// Description: Gets Periodic Timer sources status. +// +// Input: None +// +// Output: BOOLEAN +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN EfiSmmGetPeriodicTimerSourcesStatus (VOID) +{ +//#### Use Intel RC HANDLER_LINK *Handler = (HANDLER_LINK *)\ +//#### Use Intel RC SmmHandler[EfiSmmPeriodicTimerSmi].RegisteredCallbacks.pHead; +//#### Use Intel RC EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *TimerContext; + +//#### Use Intel RC while (Handler != NULL) { +//#### Use Intel RC TimerContext = \ +//#### Use Intel RC (EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *)Handler->Context; +//#### Use Intel RC if (TimerContext->TimerEnabled) return TRUE; + +//#### Use Intel RC Handler = (HANDLER_LINK *)Handler->Link.pNext; +//#### Use Intel RC } + return FALSE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmPeriodicTimerEnable +// +// Description: Enables Periodic Timer SMI. +// +// Input: *This - Pointer to the +// EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL +// Handle - Handle to enable +// +// Output: EFI_STATUS +// EFI_NOT_FOUND - The specific handle is not found. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmPeriodicTimerEnable ( + IN EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ +//#### Use Intel RC HANDLER_LINK *Handler = (HANDLER_LINK *)\ +//#### Use Intel RC SmmHandler[EfiSmmPeriodicTimerSmi].RegisteredCallbacks.pHead; +//#### Use Intel RC EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *TimerContext; + +//#### Use Intel RC while (Handler != NULL) { +//#### Use Intel RC if (Handler == Handle) { +//#### Use Intel RC TimerContext = \ +//#### Use Intel RC (EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *)Handler->Context; +//#### Use Intel RC TimerContext->TimerEnabled = TRUE; +//#### Use Intel RC TimerSmiClear(); +//#### Use Intel RC TimerSmiEnable(); +//#### Use Intel RC return EFI_SUCCESS; +//#### Use Intel RC } + +//#### Use Intel RC Handler = (HANDLER_LINK *)Handler->Link.pNext; +//#### Use Intel RC } + return EFI_NOT_FOUND; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmPeriodicTimerDisable +// +// Description: Disables Periodic Timer SMI. +// +// Input: *This - Pointer to the +// EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL +// Handle - Handle to disable +// +// Output: EFI_STATUS +// EFI_NOT_FOUND - The specific handle is not found. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmPeriodicTimerDisable ( + IN EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ +//#### Use Intel RC HANDLER_LINK *Handler = (HANDLER_LINK *)\ +//#### Use Intel RC SmmHandler[EfiSmmPeriodicTimerSmi].RegisteredCallbacks.pHead; +//#### Use Intel RC EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *TimerContext; + +//#### Use Intel RC while (Handler != NULL) { +//#### Use Intel RC if (Handler == Handle) { +//#### Use Intel RC TimerContext = \ +//#### Use Intel RC (EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *)Handler->Context; +//#### Use Intel RC TimerContext->TimerEnabled = FALSE; +//#### Use Intel RC if (!EfiSmmGetPeriodicTimerSourcesStatus()) +//#### Use Intel RC TimerSmiDisable(); +//#### Use Intel RC return EFI_SUCCESS; +//#### Use Intel RC } + +//#### Use Intel RC Handler = (HANDLER_LINK *)Handler->Link.pNext; +//#### Use Intel RC } + return EFI_NOT_FOUND; +} + +//--------------------------------------------------------------------------- +// USB SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmUsbRegister +// +// Description: EFI_SMM_USB_DISPATCH_PROTOCOL Register function. +// +// Input: *This - Pointer to EFI_SMM_USB_DISPATCH_PROTOCOL +// Function - Pointer to callback function +// *Context - Pointer to callback context +// *Handle - Pointer to store registered handle +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmUsbRegister ( + IN EFI_SMM_USB_DISPATCH_PROTOCOL *This, + IN EFI_SMM_USB_DISPATCH Function, + IN EFI_SMM_USB_DISPATCH_CONTEXT *Context, + OUT EFI_HANDLE *Handle ) +{ +//#### Use Intel RC return RegisterHandler( EfiSmmUsbSmi, \ +//#### Use Intel RC Function, \ +//#### Use Intel RC Context, \ +//#### Use Intel RC sizeof(EFI_SMM_USB_DISPATCH_CONTEXT), \ +//#### Use Intel RC Handle ); + return EFI_NOT_FOUND; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmUsbUnregister +// +// Description: EFI_SMM_USB_DISPATCH_PROTOCOL Unregister function. +// +// Input: *This - Pointer to the EFI_SMM_USB_DISPATCH_PROTOCOL +// Handle - Handle to unregister +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmUsbUnregister ( + IN EFI_SMM_USB_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ +//#### Use Intel RC return UnregisterHandler( EfiSmmUsbSmi, Handle ); + return EFI_SUCCESS; +} + +//--------------------------------------------------------------------------- +// GPI SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmGpiRegister +// +// Description: EFI_SMM_GPI_DISPATCH_PROTOCOL Register function. +// +// Input: *This - Pointer to EFI_SMM_GPI_DISPATCH_PROTOCOL +// Function - Pointer to callback function +// *Context - Pointer to callback context +// *Handle - Pointer to store registered handle +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmGpiRegister ( + IN EFI_SMM_GPI_DISPATCH_PROTOCOL *This, + IN EFI_SMM_GPI_DISPATCH Function, + IN EFI_SMM_GPI_DISPATCH_CONTEXT *Context, + OUT EFI_HANDLE *Handle ) +{ +//#### Use Intel RC return RegisterHandler( EfiSmmGpiSmi, \ +//#### Use Intel RC Function, \ +//#### Use Intel RC Context, \ +//#### Use Intel RC sizeof(EFI_SMM_GPI_DISPATCH_CONTEXT), \ +//#### Use Intel RC Handle ); + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmGpiUnregister +// +// Description: EFI_SMM_GPI_DISPATCH_PROTOCOL Unregister function. +// +// Input: *This - Pointer to the EFI_SMM_GPI_DISPATCH_PROTOCOL +// Handle - Handle to unregister +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmGpiUnregister ( + IN EFI_SMM_GPI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ +//#### Use Intel RC return UnregisterHandler( EfiSmmGpiSmi, Handle ); + return EFI_SUCCESS; +} + +//--------------------------------------------------------------------------- +// Standby button SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmSButtonRegister +// +// Description: EFI_SMM_STANDBY_BUTTON_DISPATCH_PROTOCOL Register function. +// +// Input: *This - Pointer to EFI_SMM_STANDBY_BUTTON_DISPATCH_PROTOCOL +// Function - Pointer to callback function +// *Context - Pointer to callback context +// *Handle - Pointer to store registered handle +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmSButtonRegister ( + IN EFI_SMM_STANDBY_BUTTON_DISPATCH_PROTOCOL *This, + IN EFI_SMM_STANDBY_BUTTON_DISPATCH Function, + IN EFI_SMM_STANDBY_BUTTON_DISPATCH_CONTEXT *Context, + OUT EFI_HANDLE *Handle ) +{ + return RegisterHandler( EfiSmmStandbyButtonSmi, \ + Function, \ + Context, \ + sizeof(EFI_SMM_STANDBY_BUTTON_DISPATCH_CONTEXT), \ + Handle ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmSButtonUnregister +// +// Description: EFI_SMM_STANDBY_BUTTON_DISPATCH_PROTOCOL Unregister function. +// +// Input: *This - Pointer to the +// EFI_SMM_STANDBY_BUTTON_DISPATCH_PROTOCOL +// Handle - Handle to unregister +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmSButtonUnregister ( + IN EFI_SMM_STANDBY_BUTTON_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ + return UnregisterHandler( EfiSmmStandbyButtonSmi, Handle ); +} + +//--------------------------------------------------------------------------- +// Power button SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmPButtonRegister +// +// Description: EFI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL Register function. +// +// Input: *This - Pointer to EFI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL +// Function - Pointer to callback function +// *Context - Pointer to callback context +// *Handle - Pointer to store registered handle +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmPButtonRegister ( + IN EFI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL *This, + IN EFI_SMM_POWER_BUTTON_DISPATCH Function, + IN EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT *Context, + OUT EFI_HANDLE *Handle ) +{ +#if INTEL_RC_SMI_DISPATCHER_SUPPORT == 0 + return RegisterHandler( EfiSmmPowerButtonSmi, + Function, + Context, + sizeof(EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT), + Handle ); +#else + return EFI_UNSUPPORTED; +#endif +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmPButtonUnregister +// +// Description: EFI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL Unregister function. +// +// Input: *This - Pointer to the EFI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL +// Handle - Handle to unregister +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmPButtonUnregister ( + IN EFI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ +#if INTEL_RC_SMI_DISPATCHER_SUPPORT == 0 + return UnregisterHandler( EfiSmmPowerButtonSmi, Handle ); +#else + return EFI_UNSUPPORTED; +#endif +} + +//--------------------------------------------------------------------------- +// TCO SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmTcoRegister +// +// Description: EFI_SMM_TCO_DISPATCH_PROTOCOL Register function. +// +// Input: *This - Pointer to EFI_SMM_TCO_DISPATCH_PROTOCOL +// Function - Pointer to callback function +// *Context - Pointer to callback context +// *Handle - Pointer to store registered handle +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmTcoRegister ( + IN EFI_SMM_TCO_DISPATCH_PROTOCOL *This, + IN EFI_SMM_TCO_DISPATCH Function, + IN EFI_SMM_TCO_DISPATCH_CONTEXT *Context, + OUT EFI_HANDLE *Handle ) +{ +//#### Use Intel RC return RegisterHandler( EfiSmmTcoSmi, \ +//#### Use Intel RC Function, \ +//#### Use Intel RC Context, \ +//#### Use Intel RC sizeof(EFI_SMM_TCO_DISPATCH_CONTEXT), \ +//#### Use Intel RC Handle ); + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmTcoUnregister +// +// Description: EFI_SMM_TCO_DISPATCH_PROTOCOL Unregister function. +// +// Input: *This - Pointer to the EFI_SMM_TCO_DISPATCH_PROTOCOL +// Handle - Handle to unregister +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmTcoUnregister ( + IN EFI_SMM_TCO_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ +//#### Use Intel RC return UnregisterHandler( EfiSmmTcoSmi, Handle ); + return EFI_SUCCESS; +} + +//--------------------------------------------------------------------------- +// I/O Trap SMI Handler functions +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmIoTrapRegister +// +// Description: EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL Register function. +// +// Input: *This - Pointer to EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL +// Function - Pointer to callback function +// *Context - Pointer to callback context +// *Handle - Pointer to store registered handle +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmIoTrapRegister ( + IN EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL *This, + IN EFI_SMM_IO_TRAP_DISPATCH Function, + IN EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *Context, + OUT EFI_HANDLE *Handle ) +{ +//#### Use Intel RC return RegisterHandler( EfiSmmIoTrapSmi, \ +//#### Use Intel RC Function, \ +//#### Use Intel RC Context, \ +//#### Use Intel RC sizeof(EFI_SMM_IO_TRAP_DISPATCH_CONTEXT), \ +//#### Use Intel RC Handle ); + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiSmmIoTrapUnregister +// +// Description: EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL Unregister function. +// +// Input: *This - Pointer to the EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL +// Handle - Handle to unregister +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EfiSmmIoTrapUnregister ( + IN EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ +//#### Use Intel RC return UnregisterHandler( EfiSmmIoTrapSmi, Handle ); + return EFI_SUCCESS; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/SmmChildDispatchProtocol.h b/Chipset/SB/SmmChildDispatchProtocol.h new file mode 100644 index 0000000..39bca9a --- /dev/null +++ b/Chipset/SB/SmmChildDispatchProtocol.h @@ -0,0 +1,279 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher/SmmChildDispatchProtocol.h 1 2/08/12 8:27a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:27a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher/SmmChildDispatchProtocol.h $ +// +// 1 2/08/12 8:27a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SmmChildDispatchProtocol.h +// +// Description: SMM Child dispatcher protocols functions definition +// +//<AMI_FHDR_END> +//************************************************************************* + +#ifndef __SMM_CHILD_DISPATCH_PROTOCOL__H__ +#define __SMM_CHILD_DISPATCH_PROTOCOL__H__ +#ifdef __cplusplus +extern "C" { +#endif + +#include <Protocol\SmmSwDispatch.h> +#include <Protocol\SmmSxDispatch.h> +#include <Protocol\SmmPeriodicTimerDispatch.h> +#include <Protocol\SmmUsbDispatch.h> +#include <Protocol\SmmGpiDispatch.h> +#include <Protocol\SmmStandbyButtonDispatch.h> +#include <Protocol\SmmPowerButtonDispatch.h> +#include <Protocol\SmmTcoDispatch.h> +#include <Protocol\SmmIoTrapDispatch.h> +#if defined PI_SPECIFICATION_VERSION && (PI_SPECIFICATION_VERSION >= 0x0001000A) +#include <Protocol\SmmIoTrapDispatch2.h> +#else +#include <Protocol\SmmPchIoTrapDispatch2.h> +#endif + +#include <Protocol\SmmBiosWriteDispatch.h> +#include <Token.h> +//-------------- Generic register/unregister handler functions -------------- + +EFI_STATUS RegisterHandler( + IN EFI_SMM_SMI Type, + IN VOID *Function, + IN VOID *Context, + IN UINTN ContextSize, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS UnregisterHandler ( + IN EFI_SMM_SMI Type, + IN EFI_HANDLE Handle +); + +//------------------------ Sw SMI protocol functions ------------------------ + +EFI_STATUS EfiSmmSwRegister ( + IN EFI_SMM_SW_DISPATCH_PROTOCOL *This, + IN EFI_SMM_SW_DISPATCH Function, + IN EFI_SMM_SW_DISPATCH_CONTEXT *Context, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS EfiSmmSwUnregister ( + IN EFI_SMM_SW_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +//------------------------ Sx SMI protocol functions ------------------------ + +EFI_STATUS EfiSmmSxRegister ( + IN EFI_SMM_SX_DISPATCH_PROTOCOL *This, + IN EFI_SMM_SX_DISPATCH Function, + IN EFI_SMM_SX_DISPATCH_CONTEXT *Context, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS EfiSmmSxUnregister ( + IN EFI_SMM_SX_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +//------------------ Periodic timer SMI protocol functions ------------------ + +EFI_STATUS EfiSmmTimerRegister ( + IN EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL *This, + IN EFI_SMM_PERIODIC_TIMER_DISPATCH Function, + IN EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *Context, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS EfiSmmTimerUnregister ( + IN EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +EFI_STATUS EfiSmmTimerGetNextShorterInterval ( + IN EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL *This, + IN OUT UINT64 **SmiTickInterval +); + +EFI_STATUS EfiSmmPeriodicTimerEnable ( + IN EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +EFI_STATUS EfiSmmPeriodicTimerDisable ( + IN EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +//----------------------- Usb SMI protocol functions ------------------------ + +EFI_STATUS EfiSmmUsbRegister ( + IN EFI_SMM_USB_DISPATCH_PROTOCOL *This, + IN EFI_SMM_USB_DISPATCH Function, + IN EFI_SMM_USB_DISPATCH_CONTEXT *Context, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS EfiSmmUsbUnregister ( + IN EFI_SMM_USB_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +//----------------------- Gpi SMI protocol functions ------------------------ + +EFI_STATUS EfiSmmGpiRegister ( + IN EFI_SMM_GPI_DISPATCH_PROTOCOL *This, + IN EFI_SMM_GPI_DISPATCH Function, + IN EFI_SMM_GPI_DISPATCH_CONTEXT *Context, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS EfiSmmGpiUnregister ( + IN EFI_SMM_GPI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +//------------------ Standby button SMI protocol functions ------------------ + +EFI_STATUS EfiSmmSButtonRegister ( + IN EFI_SMM_STANDBY_BUTTON_DISPATCH_PROTOCOL *This, + IN EFI_SMM_STANDBY_BUTTON_DISPATCH Function, + IN EFI_SMM_STANDBY_BUTTON_DISPATCH_CONTEXT *Context, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS EfiSmmSButtonUnregister ( + IN EFI_SMM_STANDBY_BUTTON_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +//------------------- Power button SMI protocol functions ------------------- + +EFI_STATUS EfiSmmPButtonRegister ( + IN EFI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL *This, + IN EFI_SMM_POWER_BUTTON_DISPATCH Function, + IN EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT *Context, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS EfiSmmPButtonUnregister ( + IN EFI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +//----------- Total Cost of Ownership (TCO) SMI protocol functions ---------- + +EFI_STATUS EfiSmmTcoRegister ( + IN EFI_SMM_TCO_DISPATCH_PROTOCOL *This, + IN EFI_SMM_TCO_DISPATCH Function, + IN EFI_SMM_TCO_DISPATCH_CONTEXT *Context, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS EfiSmmTcoUnregister ( + IN EFI_SMM_TCO_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +//--------------------- I/O Trap SMI protocol functions --------------------- + +EFI_STATUS EfiSmmIoTrapRegister ( + IN EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL *This, + IN EFI_SMM_IO_TRAP_DISPATCH Function, + IN EFI_SMM_IO_TRAP_DISPATCH_CONTEXT *Context, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS EfiSmmIoTrapUnregister ( + IN EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +//------------------- I/O Trap #2 SMI protocol functions ------------------- + +#if defined PI_SPECIFICATION_VERSION && (PI_SPECIFICATION_VERSION >= 0x0001000A) +EFI_STATUS EfiSmmIoTrap2Register ( + IN CONST EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 Function, + IN EFI_SMM_IO_TRAP_REGISTER_CONTEXT *Context, + OUT EFI_HANDLE *Handle +); +#else +EFI_STATUS EfiSmmIoTrap2Register ( + IN EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_IO_TRAP_DISPATCH2 Function, + IN EFI_SMM_IO_TRAP_REGISTER_CONTEXT *Context, + OUT EFI_HANDLE *Handle +); +#endif + +#if defined PI_SPECIFICATION_VERSION && (PI_SPECIFICATION_VERSION >= 0x0001000A) +EFI_STATUS EfiSmmIoTrap2Unregister ( + IN CONST EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE Handle +); +#else +EFI_STATUS EfiSmmIoTrap2Unregister ( + IN EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE Handle +); +#endif + +//-------------------- BIOS Write SMI protocol functions -------------------- + +EFI_STATUS EfiSmmBiosWriteRegister ( + IN EFI_SMM_BIOS_WRITE_DISPATCH_PROTOCOL *This, + IN EFI_SMM_BIOS_WRITE_DISPATCH Function, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS EfiSmmBiosWriteUnregister ( + IN EFI_SMM_BIOS_WRITE_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/SmmChildDispatcher.cif b/Chipset/SB/SmmChildDispatcher.cif new file mode 100644 index 0000000..9649c65 --- /dev/null +++ b/Chipset/SB/SmmChildDispatcher.cif @@ -0,0 +1,16 @@ +<component> + name = "SmmChildDispatcher" + category = ModulePart + LocalRoot = "Chipset\SB" + RefName = "SmmChildDispatcher" +[files] +"SmmChildDispatcher.mak" +"SmmChildDispatcher.sdl" +"SmmChildDispatcher.dxs" +"SmiHandlerGeneric.c" +"SmiHandlerPorting.c" +"SmmChildDispatch.h" +"SmmChildDispatchMain.c" +"SmmChildDispatchProtocol.c" +"SmmChildDispatchProtocol.h" +<endComponent> diff --git a/Chipset/SB/SmmChildDispatcher.dxs b/Chipset/SB/SmmChildDispatcher.dxs new file mode 100644 index 0000000..aa66571 --- /dev/null +++ b/Chipset/SB/SmmChildDispatcher.dxs @@ -0,0 +1,76 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher/SmmChildDispatcher.dxs 2 4/25/12 9:35a Victortu $ +// +// $Revision: 2 $ +// +// $Date: 4/25/12 9:35a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher/SmmChildDispatcher.dxs $ +// +// 2 4/25/12 9:35a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Reprogram SMM ChildDispatcher drivers. +// [Files] SmiHandlerGeneric.c; SmiHandlerPorting.c; +// SmiHandlerGeneric2.c; SmmChildDispatch2Main.c; SmmChildDispatcher2.mak; +// SmmChildDispatcher2.sdl; SmmChildDispatch.h; SmmChildDispatchMain.c; +// SmmChildDispatchProtocol.c; SmmChildDispatcher.dxs; +// PchSmiDispatcher.sdl +// +// 1 2/08/12 8:27a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SmmChildDispatcher.DXS +// +// Description: This file contains the dependency expression for the SMM +// Child Dispatcher driver +// +//<AMI_FHDR_END> +//************************************************************************* + +#include <token.h> + +#include <Protocol\SmmBase.h> +#if INTEL_RC_SMI_DISPATCHER_SUPPORT +#include <Protocol\SmmSwDispatch.h> +#endif + +DEPENDENCY_START +#if INTEL_RC_SMI_DISPATCHER_SUPPORT + EFI_SMM_SW_DISPATCH_PROTOCOL_GUID AND +#endif + EFI_SMM_BASE_PROTOCOL_GUID +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/SB/SmmChildDispatcher.mak b/Chipset/SB/SmmChildDispatcher.mak new file mode 100644 index 0000000..5825886 --- /dev/null +++ b/Chipset/SB/SmmChildDispatcher.mak @@ -0,0 +1,78 @@ +# MAK file for the ModulePart:SmmChildDispatcher +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher/SmmChildDispatcher.mak 1 2/08/12 8:27a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 8:27a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher/SmmChildDispatcher.mak $ +# +# 1 2/08/12 8:27a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: SmmChildDispatcher.mak +# +# Description: Make file for the SMM Child Dispatcher driver. +# +#<AMI_FHDR_END> +#************************************************************************* +!IFNDEF BACKWARD_COMPATIBLE_MODE +BACKWARD_COMPATIBLE_MODE = 1 +!ENDIF + +all : SmmChildDispatcher + +SmmChildDispatcher : $(BUILD_DIR)\SmmChildDispatcher.mak SmmChildDispatcherBin + +$(BUILD_DIR)\SmmChildDispatcher.mak : $(SMM_CHILD_DISP_DIR)\SmmChildDispatcher.cif $(SMM_CHILD_DISP_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(SMM_CHILD_DISP_DIR)\SmmChildDispatcher.cif $(CIF2MAK_DEFAULTS) + +SmmChildDispatcherBin : $(AMICSPLib) $(AMIDXELIB) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\SmmChildDispatcher.mak all\ + "CFLAGS=$(CFLAGS) /I$(SB_BOARD_DIR)"\ + GUID=753630C9-FAE5-47a9-BBBF-88D621CD7282\ + ENTRY_POINT=SmmChildDispatchEntryPoint\ +!IF $(BACKWARD_COMPATIBLE_MODE) + TYPE=BS_DRIVER \ + DEPEX1=$(SMM_CHILD_DISP_DIR)\SmmChildDispatcher.DXS \ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ +!ELSE + TYPE=RT_DRIVER \ + DEPEX1=$(SMM_CHILD_DISP_DIR)\SmmChildDispatcher.DXS \ +!ENDIF + COMPRESS=1 + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/SB/SmmChildDispatcher.sdl b/Chipset/SB/SmmChildDispatcher.sdl new file mode 100644 index 0000000..6630274 --- /dev/null +++ b/Chipset/SB/SmmChildDispatcher.sdl @@ -0,0 +1,141 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher/SmmChildDispatcher.sdl 1 2/08/12 8:27a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 8:27a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Chipset/SmmChildDispatcher/SmmChildDispatcher.sdl $ +# +# 1 2/08/12 8:27a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "SmmChildDispatcher_SUPPORT" + Value = "1" + Help = "Main switch to enable SmmChildDispatcher support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes +End + +TOKEN + Name = "EXTENDED_SMI" + Value = "0xF0" + Help = "SMI number for DWORD SMI value handlers" + TokenType = Integer + TargetH = Yes + Range = "00-FF" +End + +TOKEN + Name = "MAX_SW_SMI_INPUT_VALUE" + Value = "0xEF" + Help = "This is the maximum value supported by the SW SMI child dispatcher" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "SUPPORTED_GPIS" + Value = "0xFFFF" + Help = "This is a supported GPI SMI mask, 1 = supported, 32 bits maximum" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "GPI_DISPATCH_BY_BITMAP" + Value = "0" + Help = "ON = The registered parameter of SMM GPI dispatcher is using bitmapped.\OFF = The registered parameter of SMM GPI disatcher is using index based" + TokenType = Boolean + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "SUPPORTED_TCOS" + Value = "0x168F" + Help = "This is a supported TCO SMI status mask, 1 = supported, 32 bits maximum\This value should not include BIOSWE bit, because it had been supported by another SMM dispatch" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "MAX_SUPPORTED_IOTRAP_REGS" + Value = "0x04" + Help = "This is the maximum register number in SB can be used for I/O Trap" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "MAX_SUPPORTED_IOTRAP_LENGTH" + Value = "0x100" + Help = "This is the maximum length (BYTE) supported by I/O Trap register" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "ACPI_SLEEP_IN_SMM" + Value = "1" + Help = "If ON = The function of ACPI Sleep will enable in SMM by BIOS.\If OFF = The function of ACPI Sleep will enable by OS." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "SWSMI_TIMER_INSTEAD" + Value = "1" + Help = "ON = Select the SWSMI Timer for SMI Periodic Timer event.\OFF = Select the Periodic Timer for SMI Periodic Timer event." + TokenType = Boolean + TargetH = Yes +End + +PATH + Name = "SMM_CHILD_DISP_DIR" +End + +MODULE + Help = "Includes SmmChildDispatcher.mak to Project" + File = "SmmChildDispatcher.mak" +End + +ELINK + Name = "$(BUILD_DIR)\SmmChildDispatcher.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + diff --git a/Chipset/SB/sb.cif b/Chipset/SB/sb.cif new file mode 100644 index 0000000..3bc20aa --- /dev/null +++ b/Chipset/SB/sb.cif @@ -0,0 +1,12 @@ +<component> + name = "Intel PCH" + category = eChipset + LocalRoot = "Chipset\SB\" + RefName = "Intel Pch" +[files] +"ReleaseNotes.chm" +[parts] +"Intel Pch SB Board" +"Intel Pch SB Chipset" +"Intel Pch SB Refcode" +<endComponent> diff --git a/Chipset/SB/sbCSP.CIF b/Chipset/SB/sbCSP.CIF new file mode 100644 index 0000000..0031bf6 --- /dev/null +++ b/Chipset/SB/sbCSP.CIF @@ -0,0 +1,31 @@ +<component> + name = "Intel Pch SB Chipset" + category = ModulePart + LocalRoot = "Chipset\SB\" + RefName = "Intel Pch SB Chipset" +[files] +"SBGeneric.c" +"SBPEI.c" +"SBDxe.c" +"SBCspLib.h" +"RTC.h" +"SBRun.c" +"SBSmm.c" +"RRIORDMA.asl" +"GbE_OR.BIN" +"SB.ASL" +"IDE.ASL" +"SATA.ASL" +"SataOrom125.bin" +[parts] +"SB PPI" +"SB Protocols" +"SmBus" +"SmmChildDispatcher" +"SmmChildDispatcher2" +"AcpiModeEnable" +"SleepSmi" +"SBSMI" +"PchWrap" +"SataDriver" +<endComponent> diff --git a/Chipset/SB/usb/usbsb.c b/Chipset/SB/usb/usbsb.c new file mode 100644 index 0000000..2d0a21f --- /dev/null +++ b/Chipset/SB/usb/usbsb.c @@ -0,0 +1,891 @@ +//**************************************************************************** +//**************************************************************************** +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone (770)-246-8600 ** +//** ** +//**************************************************************************** +//**************************************************************************** + +//**************************************************************************** +// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/chipset/sb/usb/usbsb.c 2 2/10/17 1:48a Chienhsieh $ +// +// $Revision: 2 $ +// +// $Date: 2/10/17 1:48a $ +// +//**************************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/chipset/sb/usb/usbsb.c $ +// +// 2 2/10/17 1:48a Chienhsieh +// [TAG] EIP316430 +// [Description] [Haswell Series] Modules Update/Function +// implementation/Bug fixed on 'SharkBay DT' CRB049 project label. +// Sync with 4.6.5.1_USB_08.10.36 +// +// 1 8/08/16 4:02a Chienhsieh +// Sync with 4.6.3_USB_08.10.35. +// +// 29 6/11/14 2:26a Littleyan +// Update USBSB Template to 4.6.3_USB_08.10.30. +// +// 28 1/17/14 4:20a Littleyan +// Update USBSB Template to 4.6.3_USB_08.10.29. +// +// 27 12/10/13 6:04a Littleyan +// Add WPT Sku +// +// 26 5/13/13 12:17a Wesleychen +// Update address of GPE0_STS and GPE0_EN for Intel PCH LPT-LP. +// +// 25 4/02/13 5:31a Wesleychen +// Update USBSB Template to 4.6.3_USB_08.10.26. +// +// 23 1/22/13 5:00a Wesleychen +// Fix USB keyboard cannot work in DOS if LPT xHCI Mode = Enabled. +// +// 22 1/14/13 10:05p Wesleychen +// Improve IsAllEhciDisabled(). +// +// 21 1/11/13 5:47a Wesleychen +// Fixed coding error. +// +// 19 1/06/13 9:55p Wesleychen +// Update for Intel LPT RC 0.8.1. Turen on the SWSMI Timer when all EHCI +// controllers are disabled. +// +// 18 12/20/12 8:11a Wesleychen +// [TAG] EIP108635 +// [Category] Bug Fix +// [Severity] Important +// [Symptom] Lynx Point USB ports have no function in DOS when +// all EHCIs are disabled and only xHCI exists. +// [RootCause] Legacy keyboard support is rely on EHCI H/W SMI to +// trigger it, that is why the USB KB couldn't working +// under DOS if you issue a warm boot from Windows 8 or +// set "xHCI Mode" = "Enabled". +// [Solution] Use SW Timer SMI to instead of EHCI H/W SMI. +// [Files] usbsb.c +// +// 15 10/31/12 2:11a Wesleychen +// Update for Intel PCH Lynx Point-LP support. +// +// 13 6/05/12 2:13a Wesleychen +// Update USBSB Template to 4.6.3_USB_08.10.22. +// +// 30 5/22/12 10:02a Ryanchou +// [TAG] EIP90154 +// [Category] Improvement +// [Description] Remove the USBSB_EnableSmmPeriodicSmi and +// USBSB_DisableSmmPeriodicSmi hooks. +// [Files] amidef.h, amiusb.c, usb.c, usbsb.c +// +// 29 5/04/12 6:36a Ryanchou +// [TAG] EIP82875 +// [Category] Improvement +// [Description] Support start/stop individual USB host to avoid +// reconnect issues. +// [Files] usbport.c, usbsb.c, amiusb.c, amiusb.h, ehci.c, ohci.c, +// uhci.c, uhci.h, usb.c, usbdef.h, xhci.c, amiusbhc.c, uhcd.c, uhcd.h, +// usbbus.c, usbmisc.c +// +// 28 5/03/12 6:31a Roberthsu +// [TAG] EIP84455 +// [Category] Improvement +// [Description] Implement usb hid device gencric. +// [Files] amiusb.c,amiusbhc.c,efiusbhid.c,efiusbkb.c,ehci.c,ohci.c,uhc +// d.c,uhci.c,usbdef.h,usbhid.c,usbhub.c,usbkbd.c,usbkbd.h,usbms.c,usbsb.c +// ,usbsrc.sdl +// +// 27 1/16/12 6:02a Ryanchou +// [TAG] EIP81132 +// [Description] Add core version check for EIP80609 solution. +// [Files] amiusb.c, usbrt.mak, usbsb.c +// +// 26 1/14/12 4:11a Ryanchou +// [TAG] EIP80609 +// [Category] Bug Fix +// [Severity] Important +// [Symptom] If to enable debug mode and set launch CSM is "Never" in +// setup, system will hang at 0xB1 +// [RootCause] The pointer AmiUsb is invalid if CSM is not launched, +// that may cause CPU exception. +// [Solution] Added USB smm protocol, and use SmmLocateProtocol to get +// the pointer. +// [Files] amiusb.c, AmiUsbController.h, usbrt.mak, usbsb.c +// +// 25 11/08/11 2:02a Ryanchou +// [TAG] EIP63188 +// [Category] Improvement +// [Description] External USB controller support. +// [Files] amidef.h, amiusb.c, ehci.c, ohci.c, uhcd.c, uhcd.h, uhci.c, +// usbdef.h, usbmisc.c, usbsb.c, xhci.c +// +// 24 10/17/11 2:25a Ryanchou +// [TAG] EIP69136 +// [Category] Improvement +// [Description] Remove the dependency of EBDA in USB module for CSM +// disabling. +// [Files] amiusb.c, uhcd.c, usbport.c, usbsb.c +// +// 23 8/08/11 7:03a Ryanchou +// [TAG] EIP54018 +// [Category] New Feature +// [Description] Added USB S5 wake up support. +// [Files] amiusb.c, ehci.c, ohci.c, uhci.c, usb.c, usb.sdl, usbdef.h, +// usbsb.c xhci.c +// +// 22 7/15/11 6:33a Ryanchou +// [TAG] EIP38434 +// [Category] New Feature +// [Description] Added USB HID report protocol support. +// [Files] amiusb.c, AmiUsbController.h, amiusbhc.c, efiusbkb.c, +// efiusbkb.h, efiusbpoint.c, ehci.c, ohci.c, uhcd.c uhcd.cif, uhci.c, +// usb.c, usbdef.h, usbhid.c, usbkbd.c, usbkbd.h, usbms.c, usbpoint.c, +// usbrt.cif, usbsb.c, usbsetup.c, usbsrc.sdl, xhci.c +// +// 21 6/22/11 4:48a Ryanchou +// [TAG] EIP61556 +// [Category] Improvement +// [Description] Add both bitmapped and index based GPI number for +// better compatibility. +// [Files] usbsb.c +// +// 20 4/06/11 3:29a Ryanchou +// [TAG] EIP55275 +// [Category] Bug Fix +// [Severity] Important +// [Symptom] EBDA:108 conflict +// [RootCause] The EIP48064 save EFI_USB_PROTOCOL pointer in EBDA:108, +// but Keymon filter driver used the same location. +// [Solution] Use the EBDA:32 to save EFI_USB_PROTOCOL pointer and add a +// signature in EFI_USB_PROTOCOL. +// [Files] amidef.h, AmiUsbController.h, uhcd.c, usbsb.c +// +// 19 3/29/11 10:23a Ryanchou +// [TAG] EIP53518 +// [Category] Improvement +// [Description] Added chipset xHCI chip support. +// [Files] amiusb.c, amiusb.h, ehci.c, ohci.c, uhcd.c, uhci.c, usb.c, +// usb.sdl, usbdef.h, usbport, usbsb.c, xhci.c +// +// 18 12/29/10 1:51a Ryanchou +// [TAG] EIP50358 +// [Category] Bug Fix +// [Severity] Important +// [Symptom] System hang at "Starting Windows". +// [RootCause] The EIP48064 modification save EFI_USB_PROTOCOL pointer +// to EBDA, if disable USB Support, the pointer will be 0. +// [Solution] Check the pointer in EBDA before use it. +// [Files] usbsb.c +// +// 17 12/29/10 1:29a Ryanchou +// [TAG] EIP50943 +// [Category] Bug Fix +// [Severity] Minor +// [Symptom] USB Keyboard abnormal +// [RootCause] We only check the aUSBKBDeviceTable entry 0, if the value +// is 0, we will not send the characters to KBC. +// [Solution] The solution is search all the aUSBKBDeviceTable. +// [Files] usbsb.c +// +// 16 11/22/10 8:48a Ryanchou +// [TAG] EIP48064 +// [Category] Improvement +// [Description] The SB template implemented elink +// AcpiEnableCallbackList, the XHCI/EHCI hand off function should be +// invoked via the elink AcpiEnableCallbackList. +// [Files] amidef.h, amiusb.c, amiusb.dxs, amiusb.h, +// AmiUsbController.h, usb.sdl, usbrt.mak, usbsb.c +// +// 15 11/02/10 12:04a Tonylo +// EIP45564 - System hang when resume from S3. +// +// 13 10/21/10 8:58a Ryanchou +// EIP44570: Added multiple xHCI SMI pin support. +// +// 12 10/07/10 10:12a Ryanchou +// EIP41379: Move the code that install xHCI hardware SMI handler in +// XHCI_Start function. +// +// 11 8/31/10 11:32p Tonylo +// EIP43380 - BIOS build failed with WDK 7600.16385.1. +// +// 10 7/13/10 7:09a Ryanchou +// EIP38356: Implement shutdown USB legacy support in ACPI enable call. +// +// 9 7/13/10 5:32a Ryanchou +// EIP40732: Implement xHCI periodic timer handler to replace the XHCI HW +// SMI functionality. +// +// 8 6/15/10 1:23a Ryanchou +// Implement xHCI USB Legacy Capability. +// +// 7 4/29/10 10:07a Olegi +// +// 6 4/14/10 5:42p Olegi +// Unnecessary code commented out, left for reference only. +// +// 4 1/29/10 4:55p Olegi +// +// 3 11/20/09 6:17p Olegi +// Sample implementation added. +// +// 2 11/18/09 4:25p Olegi +// Copyright message update. +// +// 1 2/19/08 2:32p Olegi +// +//**************************************************************************** +// +//<AMI_FHDR_START> +//----------------------------------------------------------------------------- +// +// Name: USBSB.C +// +// Description: USB South Bridge Porting Hooks +// +//----------------------------------------------------------------------------- +//<AMI_FHDR_END> + +//**************************************************************************** + +#include "Efi.h" +#include "token.h" +#include "amidef.h" +#include "usbdef.h" +#include "amiusb.h" +#include "usbkbd.h" +#include "AmiCspLib.h" +#include <Setup.h> + +#ifndef USB_ACPI_ENABLE_CALLBACK + +#include <Edk\Foundation\Framework\Protocol\SmmPeriodicTimerDispatch\SmmPeriodicTimerDispatch.h> +#include <Protocol\SmmGpiDispatch.h> + +#ifdef USB_ACPI_ENABLE_DISPATCH +#include <Chipset\SB\AcpiModeEnable.h> + +EFI_GUID gEfiAcpiEnDispatchProtocolGuid = EFI_ACPI_EN_DISPATCH_PROTOCOL_GUID; +#endif + +#include <AmiBufferValidationLib.h> +#include <AmiUsbSmmGlobalDataValidationLib.h> + +// Timer service +EFI_GUID gEfiSmmPeriodicTimerDispatchProtocolGuid = EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL_GUID; +EFI_SMM_PERIODIC_TIMER_DISPATCH_PROTOCOL *gPeriodicTimerDispatch = NULL; +EFI_HANDLE gPeriodicTimerHandle = NULL; +EFI_HANDLE gUsbIntTimerHandle = NULL; + +EFI_STATUS USBPort_PeriodicTimerCallBack ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *DispatchContext + ); + +extern USB_GLOBAL_DATA *gUsbData; +extern BOOLEAN gLockSmiHandler; +extern BOOLEAN gLockHwSmiHandler; + +UINT8 ByteReadIO (UINT16); +VOID ByteWriteIO (UINT16, UINT8); +UINT32 ReadPCIConfig(UINT16, UINT8); + +extern UINT32 DwordReadMem(UINT32, UINT16); +extern void DwordWriteMem(UINT32, UINT16, UINT32); + +#ifndef GP_IOREG_GPI_ROUT2 +#define GP_IOREG_GPI_ROUT2 0x34 +#endif + +#ifndef ICH_LP_IOREG_GPE0_STS +#define ICH_LP_IOREG_GPE0_STS ACPI_PCHLP_IOREG_GPE0_STS + 0x0c +#endif + +#ifndef ICH_LP_IOREG_GPE0_EN +#define ICH_LP_IOREG_GPE0_EN ACPI_PCHLP_IOREG_GPE0_EN + 0x0c +#endif + +#define PCH_NON_LPT 0x00 // Non Lynx Point Series +#define PCH_LPT_H 0x01 // Lynx Point 2 Chip +#define PCH_LPT_LP 0x02 // Lynx Point LP + +UINT8 IsLynxPoint ( VOID ) +{ + UINT32 LpcId; + UINT16 LpcBusDevFunc = (0 << 8) + (0x1F << 3) + 0; + + LpcId = ReadPCIConfig(LpcBusDevFunc, 0); + + if (((UINT16)(LpcId >> 16) & 0xFF00) == 0x8C00) + return PCH_LPT_H; + + if (((UINT16)(LpcId >> 16) & 0xFF00) == 0x9C00) + return PCH_LPT_LP; + + return PCH_NON_LPT; +} + +//<AMI_PHDR_START> +//--------------------------------------------------------------------------- +// +// Function: USBSB_PeriodicTimerCallBack +// +// Description: +// This function is registers periodic timer callbacks. +// +// Input: +// Pointer to the EFI System Table +// +// Output: +// - EFI_SUCCESS if timers are initialized or function is not implemented +// - timer initialization error +// +// Note: +// If function is not implemented (timers are not needed for this chipset), +// function must return EFI_SUCCESS +// +//--------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +USBSB_PeriodicTimerCallBack ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *DispatchContext + ) +{ + DEV_INFO* fpDevInfo; + int i; + DEV_INFO* pDev = gUsbData->aDevInfoTable; + EFI_STATUS Status = EFI_SUCCESS; + + if (gLockSmiHandler == TRUE) { + return EFI_SUCCESS; + } +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) + Status = AmiUsbSmmGlobalDataValidation(gUsbData); + + ASSERT_EFI_ERROR(Status); + + if (EFI_ERROR(Status)) { + gLockHwSmiHandler = TRUE; + gLockSmiHandler = TRUE; + return EFI_SUCCESS; + } +#endif + + for (i = 0; i < USB_DEV_HID_COUNT; i++) { + fpDevInfo = gUsbData->aUSBKBDeviceTable[i]; + if (fpDevInfo != NULL) break; + } + if(fpDevInfo == NULL){ + for (i = 1; i < MAX_DEVICES; ++i, ++pDev ){ +#if USB_DRIVER_BUILD_VER > 29 + if ( (pDev->Flag & DEV_INFO_VALID_STRUC) != 0 && +#else + if ( (pDev->bFlag & DEV_INFO_VALID_STRUC) != 0 && +#endif + pDev->bDeviceType == BIOS_DEV_TYPE_HID && +#if USB_DRIVER_BUILD_VER > 28 + (pDev->HidDevType & HID_DEV_TYPE_MOUSE) ) { //(EIP84455) +#else + (pDev->bSubDeviceType & SUB_DEV_TYPE_MOUSE) ) { //(EIP84455) +#endif + fpDevInfo= pDev; + break; + } + } + } + + if (fpDevInfo != NULL){ + USBKBDPeriodicInterruptHandler(gUsbData->HcTable[fpDevInfo->bHCNumber - 1]); + } + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//--------------------------------------------------------------------------- +// +// Name: USBSB_InstallXhciHwSmiHandler +// +// Description: +// This function registers XHCI hardware SMI callback function. +// +// Note: +// Currently EHCI, UHCI and OHCI drivers install their SMI handlers in the +// corresponding Start functions. In the future all code related to SMI +// registration can be moved here. +// +//--------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +USBSB_InstallXhciHwSmiHandler() +{ + EFI_STATUS Status = EFI_SUCCESS; + EFI_HANDLE Handle = NULL; + +#if XHCI_SUPPORT +#if XHCI_EVENT_SERVICE_MODE != 0 +//GPI service + EFI_SMM_GPI_DISPATCH_PROTOCOL *GpiDispatch = NULL; + EFI_SMM_GPI_DISPATCH_CONTEXT Context; + + UINT8 HwSmiPinTable[] = {USB_XHCI_EXT_HW_SMI_PINS}; + UINT8 i; + UINT32 Buffer32; + + Status = pBS->LocateProtocol (&gEfiSmmGpiDispatchProtocolGuid, NULL, &GpiDispatch); + ASSERT_EFI_ERROR(Status); // driver dependencies? + + if (!EFI_ERROR(Status)) { + for (i = 0; i < sizeof(HwSmiPinTable)/sizeof(UINT8); i++) { + if(HwSmiPinTable[i] == 0xFF) continue; + //(EIP61556)> + Context.GpiNum = HwSmiPinTable[i]; + //<(EIP61556) + GpiDispatch->Register(GpiDispatch, XhciHwSmiHandler, &Context, &Handle); + if (IsLynxPoint() == PCH_LPT_LP) { + Buffer32 = IoRead32(GPIO_BASE_ADDRESS + GP_IOREG_GPI_ROUT2); + Buffer32 &= ~(3 << (Context.GpiNum * 2)); + Buffer32 |= (1 << (Context.GpiNum * 2)); + IoWrite32(GPIO_BASE_ADDRESS + GP_IOREG_GPI_ROUT2, Buffer32); + } else { + // Set GPIO_ROUTx = SMI# (B0:D31:F0 B8h[31:0]) + Buffer32 = DwordReadMem(SB_PCIE_CFG_ADDRESS(SB_BUS, SB_DEV, SB_FUN, 0), SB_REG_GPI_ROUT); + Buffer32 &= ~(3 << (Context.GpiNum * 2)); + Buffer32 |= (1 << (Context.GpiNum * 2)); + DwordWriteMem(SB_PCIE_CFG_ADDRESS(SB_BUS, SB_DEV, SB_FUN, 0), SB_REG_GPI_ROUT, Buffer32); + } + } + } +#endif + +#if XHCI_EVENT_SERVICE_MODE != 1 + Status = USBSB_InstallUsbIntTimerHandler(); +#endif +#endif + + return Status; +} + +//<AMI_PHDR_START> +//--------------------------------------------------------------------------- +// +// Name: UsbIntTimerCallBack +// +// Description: +// +//--------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID +UsbIntTimerCallBack ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT *DispatchContext +) +{ + HC_STRUC* HcStruc; + UINT8 i; + EFI_STATUS Status; + + if (gLockSmiHandler == TRUE) { + return; + } +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B) + Status = AmiUsbSmmGlobalDataValidation(gUsbData); + + ASSERT_EFI_ERROR(Status); + + if (EFI_ERROR(Status)) { + gLockHwSmiHandler = TRUE; + gLockSmiHandler = TRUE; + return; + } +#endif + + for (i = 0; i < gUsbData->HcTableCount; i++) { + HcStruc = gUsbData->HcTable[i]; + if (HcStruc == NULL) { + continue; + } + if((HcStruc->dHCFlag & (HC_STATE_EXTERNAL | HC_STATE_RUNNING)) == + (HC_STATE_EXTERNAL | HC_STATE_RUNNING)) { + (*gUsbData->aHCDriverTable[ + GET_HCD_INDEX(HcStruc->bHCType)].pfnHCDProcessInterrupt)(HcStruc); + } + } +} + +//<AMI_PHDR_START> +//--------------------------------------------------------------------------- +// +// Name: USBSB_InstallUsbIntTimerHandler +// +// Description: +// +//--------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +USBSB_InstallUsbIntTimerHandler() +{ + EFI_STATUS Status; + EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT TimerContext; + UINT64 *SmiTickInterval; + + if (gUsbIntTimerHandle != NULL) { + return EFI_SUCCESS; + } + + Status = pBS->LocateProtocol ( + &gEfiSmmPeriodicTimerDispatchProtocolGuid, + NULL, + &gPeriodicTimerDispatch); + ASSERT_EFI_ERROR(Status); // driver dependencies? + + if (!EFI_ERROR(Status)) { + TimerContext.Period = 160000; //16ms + TimerContext.SmiTickInterval = 160000; + TimerContext.ElapsedTime = 0; + SmiTickInterval = NULL; + //Check SmiTickInterval that are supported by the chipset. + do { + Status = gPeriodicTimerDispatch->GetNextShorterInterval( + gPeriodicTimerDispatch, + &SmiTickInterval + ); + if (EFI_ERROR(Status)) { + break; + } + if (SmiTickInterval != NULL) { + if (*SmiTickInterval <= TimerContext.SmiTickInterval) { + TimerContext.SmiTickInterval = *SmiTickInterval; + break; + } + } + } while (SmiTickInterval != NULL); + + Status = gPeriodicTimerDispatch->Register ( + gPeriodicTimerDispatch, + UsbIntTimerCallBack, + &TimerContext, + &gUsbIntTimerHandle); + ASSERT_EFI_ERROR(Status); + } + + return Status; +} + +//<AMI_PHDR_START> +//--------------------------------------------------------------------------- +// +// Name: USBSB_UninstallTimerHandlers +// +// Description: This function unregisters all the periodic timer handles. +// +//--------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +USBSB_UninstallTimerHandlers() +{ + EFI_STATUS Status = EFI_SUCCESS; + + if (gPeriodicTimerDispatch == NULL) { + return Status; + } + + if (gUsbIntTimerHandle) { + Status = gPeriodicTimerDispatch->UnRegister ( + gPeriodicTimerDispatch, + gUsbIntTimerHandle); + ASSERT_EFI_ERROR(Status); + + gUsbIntTimerHandle = NULL; + } + + if (gPeriodicTimerHandle) { + Status = gPeriodicTimerDispatch->UnRegister ( + gPeriodicTimerDispatch, + gPeriodicTimerHandle); + ASSERT_EFI_ERROR(Status); + + gPeriodicTimerHandle = NULL; + } + + return Status; +} + +#ifdef USB_ACPI_ENABLE_DISPATCH +//<AMI_PHDR_START> +//--------------------------------------------------------------------------- +// +// Name: AcpiEnableCallBack +// +// Description: +// This is ACPI mode enable callback function. It is a workaround for non +// XHCI/EHCI aware OSes. +// +//--------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID +AcpiEnableCallBack( + IN EFI_HANDLE DispatchHandle +) +{ + USB_StopUnsupportedHc(); + gUsbData->dUSBStateFlag |= USB_FLAG_RUNNING_UNDER_OS; + gLockSmiHandler = TRUE; +} + +//<AMI_PHDR_START> +//--------------------------------------------------------------------------- +// +// Name: RegisterAcpiEnableCallBack +// +// Description: +// This function registers ACPI enable callback function. +// +//--------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +RegisterAcpiEnableCallBack( + IN EFI_EVENT Event, + IN VOID *Context +) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + EFI_ACPI_DISPATCH_PROTOCOL *AcpiEnDispatch; + + Status = pBS->LocateProtocol(&gEfiAcpiEnDispatchProtocolGuid, NULL, &AcpiEnDispatch); + if (EFI_ERROR(Status)) return Status; + + Status = AcpiEnDispatch->Register(AcpiEnDispatch, AcpiEnableCallBack, &Handle); + ASSERT_EFI_ERROR(Status); + + return Status; +} +#endif + +BOOLEAN IsAllEhciDisabled ( VOID ) +{ + UINT32 XhciDID; + UINT16 XhciBusDevFunc = (0 << 8) + (0x14 << 3) + 0; + EFI_STATUS Status; + SETUP_DATA SetupData; + EFI_GUID SetupGuid = SETUP_GUID; + UINTN VarSize; + + XhciDID = ReadPCIConfig(XhciBusDevFunc, 0); + + if (((UINT16)(XhciDID >> 16) == 0x8C31) || \ + ((UINT16)(XhciDID >> 16) == 0x8CB1) || \ + ((UINT16)(XhciDID >> 16) == 0x9CB1) || \ + ((UINT16)(XhciDID >> 16) == 0x9C31)) { + + VarSize = sizeof(SETUP_DATA); + Status = pRS->GetVariable( + L"Setup", + &SetupGuid, + NULL, + &VarSize, + &SetupData ); + if (!EFI_ERROR(Status)) { + if ((SetupData.PchUsb30Mode == 1) || \ + ((SetupData.PchUsb20[0] == 0) && \ + (SetupData.PchUsb20[1] == 0))) + return TRUE; + } + } + + return FALSE; +} + +//<AMI_PHDR_START> +//--------------------------------------------------------------------------- +// +// Name: USBSB_InstallSmiEventHandlers +// +// Description: +// This function is called from USBRT entry point inside SMM. Any SMI handlers +// registration related to USB driver can be done here. +// +//--------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +USBSB_InstallSmiEventHandlers(VOID) +{ + EFI_STATUS Status = EFI_SUCCESS; + + +#if USB_HID_KEYREPEAT_USE_SETIDLE == 0 + EFI_SMM_PERIODIC_TIMER_DISPATCH_CONTEXT PeriodicTimerContext; + + if (IsLynxPoint() != PCH_NON_LPT) { + + // [Lynx point] Register Timer SMI if all EHCI controllers are disabled. + if (!IsAllEhciDisabled()) return Status; + + Status = pBS->LocateProtocol ( + &gEfiSmmPeriodicTimerDispatchProtocolGuid, + NULL, + &gPeriodicTimerDispatch); + ASSERT_EFI_ERROR(Status); // driver dependencies? + + if (!EFI_ERROR(Status)) { + PeriodicTimerContext.Period = 160000; //16ms + PeriodicTimerContext.SmiTickInterval = 160000; + PeriodicTimerContext.ElapsedTime = 0; + + Status = gPeriodicTimerDispatch->Register ( + gPeriodicTimerDispatch, + USBSB_PeriodicTimerCallBack, + &PeriodicTimerContext, + &gPeriodicTimerHandle); + ASSERT_EFI_ERROR(Status); + } + if (EFI_ERROR(Status)) { + gPeriodicTimerDispatch = NULL; + } + } + +#endif + +#ifdef USB_ACPI_ENABLE_DISPATCH + { + EFI_ACPI_DISPATCH_PROTOCOL *AcpiEnDispatch; + EFI_EVENT Event; + VOID *Reg; + + Status = pBS->LocateProtocol(&gEfiAcpiEnDispatchProtocolGuid, NULL, &AcpiEnDispatch); + if(!EFI_ERROR(Status)) { + RegisterAcpiEnableCallBack(NULL, NULL); + } else { + Status = RegisterProtocolCallback( + &gEfiAcpiEnDispatchProtocolGuid, + RegisterAcpiEnableCallBack, + NULL, + &Event, + &Reg); + ASSERT_EFI_ERROR(Status); + } + } +#endif + return Status; +} + //(EIP54018+)> +#if USB_S5_WAKEUP_SUPPORT +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Name: UsbSbEnablePme +// +// Description: +// The funciton enable usb PME +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID +UsbSbEnablePme(VOID) +{ + // Disable USB Wake on Device Connect/Disconnect + *(UINT32*)(SB_RCBA + RCRB_MMIO_RMHWKCTL)= 0x33; + + // Clear PM1_STS + IoWrite16(PM_BASE_ADDRESS, IoRead16(PM_BASE_ADDRESS)); + if (IsLynxPoint() == PCH_LPT_LP) { + // Clear GPE0_STS + IoWrite32(PM_BASE_ADDRESS + ICH_LP_IOREG_GPE0_STS, 0xFFFFFFFF); // PMBASE + 8Ch + IoWrite32(PM_BASE_ADDRESS + ICH_LP_IOREG_GPE0_STS - 0x04, 0xFFFFFFFF); // PMBASE + 88h + IoWrite32(PM_BASE_ADDRESS + ICH_LP_IOREG_GPE0_STS - 0x08, 0xFFFFFFFF); // PMBASE + 84h + IoWrite32(PM_BASE_ADDRESS + ICH_LP_IOREG_GPE0_STS - 0x0C, 0xFFFFFFFF); // PMBASE + 80h + // Set PME_B0_EN and PME_EN + IoWrite16(PM_BASE_ADDRESS + ICH_LP_IOREG_GPE0_EN, BIT13 + BIT11); // PMBASE + 9Ch + } else { + // Clear GPE0_STS + IoWrite32(PM_BASE_ADDRESS + ICH_IOREG_GPE0_STS, 0xFFFFFFFF); // PMBASE + 20h + IoWrite32(PM_BASE_ADDRESS + ICH_IOREG_GPE0_STS + 0x04, 0xFFFFFFFF); // PMBASE + 24h + // Set PME_B0_EN and PME_EN (PMBASE + 28h) + IoWrite16(PM_BASE_ADDRESS + ICH_IOREG_GPE0_EN, BIT13 + BIT11); // PMBASE + 28h + } + // Clear PCI Express Wake Disable + IoWrite16(PM_BASE_ADDRESS + ACPI_IOREG_PM1_EN, + IoRead16(PM_BASE_ADDRESS + ACPI_IOREG_PM1_EN & ~BIT14)); +} + +#endif + //<(EIP54018+) +#else + +//<AMI_PHDR_START> +//--------------------------------------------------------------------------- +// +// Name: UsbAcpiEnableCallBack +// +// Description: +// This is ACPI mode enable callback function. It is a workaround for non +// XHCI/EHCI aware OSes. +// +//--------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID +UsbAcpiEnableCallBack( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext +) +{ +#if (defined(PI_SPECIFICATION_VERSION) && (PI_SPECIFICATION_VERSION>=0x0001000A)) && defined(SMM_BUILD) + EFI_STATUS Status; + AMI_USB_SMM_PROTOCOL *UsbSmmProtocol = NULL; + + Status = pSmst->SmmLocateProtocol(&gAmiUsbSmmProtocolGuid, NULL, &UsbSmmProtocol); + if (EFI_ERROR(Status)) { + return; + } + + UsbSmmProtocol->UsbStopUnsupportedHc(); + +#else + EFI_USB_PROTOCOL *AmiUsb = NULL; + UINT16 EbdaSeg = *((UINT16*)0x40E); + + AmiUsb = *(EFI_USB_PROTOCOL **)(UINTN)(((UINT32)EbdaSeg << 4) + USB_PROTOCOL_EBDA_OFFSET); + //(EIP50358)> + if (AmiUsb && AmiUsb->Signature == 0x50425355) { //USBP //(EIP55275) + AmiUsb->UsbStopUnsupportedHc(); + } + //<(EIP50358) +#endif +} + +#endif + +//**************************************************************************** +//**************************************************************************** +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone (770)-246-8600 ** +//** ** +//**************************************************************************** +//**************************************************************************** diff --git a/Chipset/SB/usb/usbsb.cif b/Chipset/SB/usb/usbsb.cif new file mode 100644 index 0000000..9134fda --- /dev/null +++ b/Chipset/SB/usb/usbsb.cif @@ -0,0 +1,8 @@ +<component> + name = "SouthBridge - Intel PCH" + category = ModulePart + LocalRoot = "chipset\sb\usb\" + RefName = "USB_SB" +[files] +"usbsb.c" +<endComponent> diff --git a/Chipset/eM/Ahci/AHCI.EQU b/Chipset/eM/Ahci/AHCI.EQU new file mode 100644 index 0000000..3bfe5a4 --- /dev/null +++ b/Chipset/eM/Ahci/AHCI.EQU @@ -0,0 +1,583 @@ +; TITLE AHCI.EQU - Equates and structures +;**************************************************************************** +;**************************************************************************** +;** ** +;** (C)Copyright 1985-2011, American Megatrends, Inc. ** +;** ** +;** All Rights Reserved. ** +;** ** +;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +;** ** +;** Phone (770)-246-8600 ** +;** ** +;**************************************************************************** +;**************************************************************************** + +;**************************************************************************** +; $Header: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AHCI.EQU 3 2/10/11 10:52a Rameshr $ +; +; $Revision: 3 $ +; +; $Date: 2/10/11 10:52a $ +; +;**************************************************************************** +; Revision History +; ---------------- +; $Log: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AHCI.EQU $ +; +; 3 2/10/11 10:52a Rameshr +; [TAG] EIP53704 +; [Category] Improvement +; [Description] AMI headers update for Alaska Ahci Driver +; [Files] AHCIACC.ASM +; HACCESS.EQU +; AHCI.EQU +; AINT13.EQU +; AInt13Csp.c +; +; 2 5/28/08 9:44a Rameshraju +; Updated the AMI Address. +; +; 1 12/07/07 11:17a Olegi +; +; 6 1/29/07 1:25a Iminglin +; +; 5 11/09/06 3:55a Iminglin +; Make code generic. +; +; 4 10/24/06 11:25p Iminglin +; Stylization. +; +; 3 9/13/06 1:58a Iminglin +; Issue Freeze Lock Command. +; +; 2 9/28/05 5:40a Iminglin +; Update for CDROM. +; +; 1 6/09/05 11:29p Iminglin +; Initialized version +; +; 1 5/20/05 2:37a Iminglin +; Intel AHCI source +; +;**************************************************************************** +; +;************************************************************************; +;* *; +;* Intel(r) Restricted Secret *; +;* *; +;* Support for and Booting from SATA devices in AHCI mode *; +;* *; +;* Enterprise Software Technology *; +;* *; +;* Copyright (c) 2003-2005 Intel Corporation *; +;* *; +;* Version iSrc03x *; +;* *; +;* This information is provided in connection with Intel products. *; +;* No license, express or implied, by estoppel or otherwise, to *; +;* any intellectual property rights is granted by this information *; +;* or by the sale of Intel products. Except as provided in Intel's *; +;* Terms and Conditions of Sale for such products, Intel assumes *; +;* no liability whatsoever, and Intel disclaims any express or *; +;* implied warranty, relating to sale and/or use of Intel products *; +;* including liability or warranties relating to fitness for a *; +;* particular purpose, merchantability, or infringement of any *; +;* patent, copyright or other intellectual property right. Intel *; +;* products are not intended for use in medical, life saving, or *; +;* life sustaining applications. *; +;* Intel retains the right to make changes to specifications and *; +;* product descriptions at any time, without notice and may choose *; +;* to develop product based on these designs. *; +;* *; +;* *Third-party brands and names are the property of their *; +;* respective owners. *; +;* *; +;************************************************************************; +;* *; +;* REFERENCES *; +;* *; +;* Revision Title *; +;* ==================================================================== *; +;* 1.0 Serial ATA Advanced Host Controller Interface (AHCI) *; +;* *; +;************************************************************************; +; +;;;;;;;;;;;; Specification related equates and structures ;;;;;;;;;;;;;;;; +;------------------------------------------------------------------------- +; Maximum #of ports supported by each SATA controller +; +MAX_PORT_NUM equ 20h ; Max #of SATA Ports per SATA Controller +; +;------------------------------------------------------------------------- +; SATA Controller Information Table +; 1. Contains the AHCI related data for the device +; 2. Built during POST +; 3. Each device has its own table +; +INFO_CONTROLLER_STRUC struc + wBusDevFunc dw ? ; Bus#, Dev#, Func# + dHbaBaseAddr dd ? ; HBA Base Address + bIrq db ? ; IRQ used + dHbaCap dd ? ; HBA Capabilities (dCAP field) + dBitPortImp dd ? ; Bit-mapped info of port implemented (dPI field) +INFO_CONTROLLER_STRUC ends +; +;------------------------------------------------------------------------- +; Generic Host Control registers +; +GENERAL_HOST_OFFSET equ 0000h ; Offset of start of Generic Host Control Registers from AHCI Base +; +GENERAL_HOST_STRUC struc + dCAP dd ? ; HBA Capabilities (see below for details) + dGHC dd ? ; Global HBA Control (see below for details) + dIS dd ? ; Interrupt Status Register (see below for details) + dPI dd ? ; Ports Implemented (see below for details) + dVS dd ? ; AHCI Version (see below for details) +GENERAL_HOST_STRUC ends +; +; Details of dCAP field +; +dCAP_NP_MASK equ 1Fh shl 0 ; Bit4-0 = max #of ports (0-based) supported +dCAP_NCS_MASK equ 1Fh shl 8 ; Bit12-8 = #of command slots (0-based) supported +dCAP_PSC equ 1 shl 13 ; Bit-13 = Partial State Capable +dCAP_SSC equ 1 shl 14 ; Bit-14 = Slumber State Capable +dCAP_PMD equ 1 shl 15 ; Bit-15 = PIO Multiple DRQ Block +dCAP_SPM equ 1 shl 17 ; Bit-17 = Supports Port Multiplier +dCAP_SAM equ 1 shl 18 ; Bit-18 = Supports AHCI Mode only +dCAP_SNZO equ 1 shl 19 ; Bit-19 = Supports Non-Zero DMA offsets +dCAP_ISS_MASK equ 0Fh shl 20; Bit23-20 = Interface Speed Support + ISS_1P5_GBPS equ 0001b ; 1.5 Gbps + ISS_1P5_3_GBPS equ 0010b ; 1.5 Gbps and 3 Gbps +dCAP_SCLO equ 1 shl 24 ; Bit-24 = Supports Command List Override +dCAP_SAL equ 1 shl 25 ; Bit-25 = Supports Activity LED +dCAP_SALP equ 1 shl 26 ; Bit-26 = Supports Aggresive Link Power Management +dCAP_SSS equ 1 shl 27 ; Bit-27 = Supports Staggered Spin-Up +dCAP_SIS equ 1 shl 28 ; Bit-28 = Supports Interlock Switch +dCAP_SNCQ equ 1 shl 30 ; Bit-30 = Supports Native Command Queuing +dCAP_S64A equ 1 shl 31 ; Bit-31 = Supports 64-bit Addressing +; +; Details of dGHC field +; +dGHC_HR equ 1 shl 0 ; Bit-0 = HBA Reset +dGHC_IE equ 1 shl 1 ; Bit-1 = Interrupt Enable +dGHC_AE equ 1 shl 31 ; Bit-31 = AHCI Enable +; +; Details of dIS field +; A particular bit, if set to 1, indicates that the corresponding port has an +; interrupt pending. Only ports, that are implemented, have a corresponding +; valid bit; all other bits are reserved. +; +; Details of dPI field +; A particular bit, if set to 1, indicates that the corresponding port is +; available for use. If set to 0, the corresponding port is not available. +; The maximum number of bits that are set to 1, shall not exceed the value +; of (dCap_NP_MASK + 1). At least one bit must be set to 1. +; +; Details of dVS field +; +dVS_MINOR equ 0FFFFh shl 0 ; Bit15-0 = Minor Version +dVS_MAJOR equ 0FFFFh shl 16 ; Bit31-16 = Major Version +; +;------------------------------------------------------------------------- +; Port registers +; +PORT_REGISTER_START equ 100h ; Port registers start at offset 100h from AHCI base +PORT_REGISTER_SET_SIZE equ 80h ; Each port registers set is 128bytes +PORT_REGISTER_SET_SIZE_N equ 07h ; #of bits to be shifted left +; +; Thus Port-N registers set starts at following offset from AHCI base +; PORT_REGISTER_START + (N * 80h) +; i.e. PORT_REGISTER_START + (N << 07h) +; +PORT_REG_STRUC struc + dPCLB dd ? ; Port Command List Base Address (lower 32bit) + dPCLBU dd ? ; Port Command List Base Address (upper 32bit) + dPFB dd ? ; Port FIS Base Address (lower 32bit) + dPFBU dd ? ; Port FIS Base Address (upper 32bit) + dPIS dd ? ; Port Interrupt Status (see below for details) + dPIE dd ? ; Port Interrupt Enable (see below for details) + dPCMD dd ? ; Port Command (see below for details) + dReserved dd ? ; Reserved + dPTFD dd ? ; Port Task File Data (see below for details) + dPSIG dd ? ; Port Signature (see below for details) + dPSSTS dd ? ; Port Serial ATA Status (see below for details) + dPSCTL dd ? ; Port Serial ATA Control (see below for details) + dPSERR dd ? ; Port Serial ATA Error (see below for details) + dPSACT dd ? ; Port Serial ATA Active + dPCI dd ? ; Port Command Issue +PORT_REG_STRUC ends +; +; Details of dPIS field +; +dPIS_DHRS equ 1 shl 0 ; Bit-0 = Device to Host Register FIS Interrupt +dPIS_PSS equ 1 shl 1 ; Bit-1 = PIO Setup FIS Interrupt +dPIS_DSS equ 1 shl 2 ; Bit-2 = DMA Setup FIS Interrupt +dPIS_SDBS equ 1 shl 3 ; Bit-3 = Set Device Bits Interrupt +dPIS_UFS equ 1 shl 4 ; Bit-4 = Unknown FIS Interrupt +dPIS_DPS equ 1 shl 5 ; Bit-5 = Descriptor Processed +dPIS_PCS equ 1 shl 6 ; Bit-6 = Port Connect Change Status +dPIS_DIS equ 1 shl 7 ; Bit-7 = Device Interlock Status + ; Bit21-8..Reserved +dPIS_PRCS equ 1 shl 22; Bit-22 = PhyRdy Change Status +dPIS_IPMS equ 1 shl 23; Bit-23 = Incorrect Port Multiplier Status +dPIS_OFS equ 1 shl 24; Bit-24 = Overflow Status +dPIS_INFS equ 1 shl 26; Bit-26 = Interface Non-Fatal Error Status +dPIS_IFS equ 1 shl 27; Bit-27 = Interface Fatal Error Status +dPIS_HBDS equ 1 shl 28; Bit-28 = Host Bus Data Error Status +dPIS_HBFS equ 1 shl 29; Bit-29 = Host Bus Fatal Error Status +dPIS_TFES equ 1 shl 30; Bit-30 = Task File Error Status +dPIS_CPDS equ 1 shl 31; Bit-31 = Cold Port Detect Status +; +; Details of dPIE field +; +dPIE_DHRE equ 1 shl 0 ; Bit-0 = Device to Host Register FIS Interrupt Enable +dPIE_PSE equ 1 shl 1 ; Bit-1 = PIO Setup FIS Interrupt Enable +dPIE_DSE equ 1 shl 2 ; Bit-2 = DMA Setup FIS Interrupt Enable +dPIE_SDBE equ 1 shl 3 ; Bit-3 = Set Device Bits Interrupt Enable +dPIE_UFE equ 1 shl 4 ; Bit-4 = Unknown FIS Interrupt Enable +dPIE_DPE equ 1 shl 5 ; Bit-5 = Descriptor Processed Interrupt Enable +dPIE_PCE equ 1 shl 6 ; Bit-6 = Port Connect Change Interrupt Enable +dPIE_DIE equ 1 shl 7 ; Bit-7 = Device Interlock Interrupt Enable + ; Bit21-8..Reserved +dPIE_PRCE equ 1 shl 22; Bit-22 = PhyRdy Change Interrupt Enable +dPIE_IPME equ 1 shl 23; Bit-23 = Incorrect Port Multiplier Interrupt Enable +dPIE_OFE equ 1 shl 24; Bit-24 = Overflow Interrupt Enable +dPIE_INFE equ 1 shl 26; Bit-26 = Interface Non-Fatal Error Interrupt Enable +dPIE_IFE equ 1 shl 27; Bit-27 = Interface Fatal Error Interrupt Enable +dPIE_HBDE equ 1 shl 28; Bit-28 = Host Bus Data Error Interrupt Enable +dPIE_HBFE equ 1 shl 29; Bit-29 = Host Bus Fatal Error Interrupt Enable +dPIE_TFEE equ 1 shl 30; Bit-30 = Task File Error Interrupt Enable +dPIE_CPDE equ 1 shl 31; Bit-31 = Cold Port Detect Interrupt Enable +; +; Details of dPCMD field +; +dPCMD_ST equ 1 shl 0 ; Bit-0 = Start process command list + PxCMD_ST0_AND_MASK equ 0FFFFFFFEh; AND Mask to set PxCMD.ST = 0 + PxCMD_ST0_OR_MASK equ 000000000h; OR Mask to set PxCMD.ST = 0 +dPCMD_SUD equ 1 shl 1 ; Bit-1 = Spin-Up Device +dPCMD_POD equ 1 shl 2 ; Bit-2 = Power On Device +dPCMD_CLO equ 1 shl 3 ; Bit-3 = Command List Override +dPCMD_FRE equ 1 shl 4 ; Bit-4 = FIS Receive Enable +; ; Bit7-5....Reserved +dPCMD_CCS_MASK equ 1Fh shl 8 ; Bit12-8 = Current Command Slot +dPCMD_ISS equ 1 shl 13; Bit-13 = Interlock Switch State +dPCMD_FR equ 1 shl 14; Bit-14 = FIS Receive Running +dPCMD_CR equ 1 shl 15; Bit-15 = Command List Running +dPCMD_CPS equ 1 shl 16; Bit-16 = Cold Presence State +dPCMD_PMA equ 1 shl 17; Bit-17 = Port Multiplier Attached +dPCMD_HPCP equ 1 shl 18; Bit-18 = Hot Plug Capable Port +dPCMD_ISP equ 1 shl 19; Bit-19 = Interlock Switch Attached to Port +dPCMD_CPD equ 1 shl 20; Bit-20 = Cold Presence Detect + ; Bit23-21..Reserved +dPCMD_ATAPI equ 1 shl 24; Bit-24 = Device is ATAPI +dPCMD_DLAE equ 1 shl 25; Bit-25 = Drive LED on ATAPI Enable +dPCMD_ALPE equ 1 shl 26; Bit-26 = Aggressive Link Power Management Enable +dPCMD_ASP equ 1 shl 27; Bit-27 = Aggressive Slumber/Partial +dPCMD_ICC_MASK equ 0Fh shl 28; Bit31-28= Interface Communication Control +dPCMD_ICC_MASK_ALIGN equ 28 ; #of bits to be shifted for Interface Communication Control alignment + ICC_NOP_IDLE equ 00h ; HBA ready to accept new interface control command + ICC_ACTIVE equ 01h ; Active + ICC_PARTIAL equ 02h ; Partial + ICC_SLUMBER equ 06h ; Slumber State +; +; +; Details of dPTFD field +; +dPTFD_STS_MASK equ 0FFh shl 0 ; Bit7-0 = Copy of Task File Status Register + dPTFD_STS_ERR equ 1 shl 0 ; Bit-0 = Error + ; Bit2-1...Not applicable + dPTFD_STS_DRQ equ 1 shl 3 ; Bit-3 = Data Xfer Requested + ; Bit5-4...Not applicable + dPTFD_STS_DRDY equ 1 shl 6 ; Bit-6 = Device is ready + dPTFD_STS_BSY equ 1 shl 7 ; Bit-7 = Interface is busy +dPTFD_ERR_MASK equ 0FFh shl 8 ; Bit15-8= Copy of Task File Error Register +; +; Details of dPSIG field +; Contains the signature received from the device on first D2H register FIS. It +; is updated once after a reset sequence. +; Bit7-0 = Sector Count Register +; Bit15-8 = LBA Low Register +; Bit23-16 = LBA Mid Register +; Bit31-24 = LBA High Register +; +; Details of dPSSTS field +; +dPSSTS_DET_MASK equ 0Fh shl 0 ; Bit3-0 = Device Detection + dPSSTS_DET_DEVICE_MASK equ 01h ; Bit-0 = 1, Device Detected + DET_NO_DEVICE_AND_NO_PHY_COMM equ 00h ; No device detected and no Phy communication + DET_DEVICE_BUT_NO_PHY_COMM equ 01h ; Device detected but no Phy communication + DET_DEVICE_AND_PHY_COMM equ 03h ; Device detected and Phy communication + DET_PHY_OFF_LINE equ 04h ; Phy in offline mode +dPSSTS_SPD_MASK equ 0Fh shl 4 ; Bit7-4 = Current Interface Speed + SPD_NO_DEVICE_OR_NO_COMM equ 00h ; No device present or no communication + SPD_GEN_1_COMM equ 01h ; Generation 1 communication rate + SPD_GEN_2_COMM equ 02h ; Generation 2 communication rate +dPSSTS_IPM_MASK equ 0Fh shl 8 ; Bit11-8 = Current Interface State + IPM_NO_DEVICE_OR_NO_COMM equ 00h ; No device present or no communication + IPM_ACTIVE equ 03h ; Interface in Active state(v1.07) + IPM_PARTIAL equ 02h ; Interface in Partial power management state + IPM_SLUMBER equ 01h ; Interface in Slumber power management state(v1.07) +; +; Details of dPSCTL field +; +dPSCTL_DET_MASK equ 0Fh shl 0 ; Bit3-0 = Device Detection Initialization + DET_NO_DET_AND_NO_INIT equ 00h ; No detection or initialization requested + DET_COMM_INIT equ 01h ; Perform Interface communication initialization + DET_DISABLE_SATA equ 04h ; Disable SATA interface and put Phy in offline mode +dPSCTL_SPD_MASK equ 0Fh shl 4 ; Bit7-4 = Speed Allowed + SPD_NO_RESTRICTION equ 00h ; No speed negotiation restriction + SPD_LIMIT_TO_GEN1 equ 01h ; Limit speed negotiation to Gen 1 rate + SPD_LIMIT_TO_GEN2 equ 02h ; Limit speed negotiation to a rate + ; not greater than Gen 2 rate +dPSCTL_IPM_MASK equ 0Fh shl 8 ; Bit11-8 = Interface Power Management Transition Allowed +dPSCTL_IPM_MASK_ALIGN equ 8 ; #of bits to be shifted for Interface Power Management Transition alignment + IPM_NO_RESTRICTION equ 00h ; No interface restriction + IPM_PARTIAL_DISABLED equ 01h ; Transition to Partial state disabled + IPM_SLUMBER_DISABLED equ 02h ; Transition to Slumber state disabled + IPM_PARTIAL_SLUMBER_DISABLED equ 03h ; Transition to both Partial and Slumber states disabled + +dPSCTL_SPM_MASK equ 0Fh shl 12; Bit15-12 = The Select Power Management +dPSCTL_SPM_MASK_ALIGN equ 12 ; #of bits to be shifted for Select Power Management alignment + SPM_NO_TRANSITION equ 00h ; No power management state transition + SPM_PARTIAL_INITIATED equ 01h ; Transition to Partial state initiated + SPM_SLUMBER_INITIATED equ 02h ; Transition to Slumber state initiated + SPM_ACTIVE_INITIATED equ 04h ; Transition to the active power management states initiated + +dPSCTL_PMP_MASK equ 0Fh shl 16; Bit19-16 = The Port Multiplier field +dPSCTL_PMP_MASK_ALIGN equ 16 ; #of bits to be shifted for Port Multiplier alignment + PMP_CONTROL_PORT equ 0Fh ; Control port # of Port Multiplier +; +; Details of dPSERR field +; +dPSERR_ERR_MASK equ 0FFFFh shl 0; Bit15-0= Error + dPSERR_ERR_I equ 1 shl 0 ; Bit-0 = Recovered Data Integrity Error + dPSERR_ERR_M equ 1 shl 1 ; Bit-1 = Recovered Communications Error + ; Bit7-2.......Reserved + dPSERR_ERR_T equ 1 shl 8 ; Bit-8 = Transient Data Integrity Error + dPSERR_ERR_C equ 1 shl 9 ; Bit-9 = Persistent Communication or Data Integrity Error + dPSERR_ERR_P equ 1 shl 10; Bit-10 = Protocol Error + dPSERR_ERR_E equ 1 shl 11; Bit-11 = Master or Target Abort + ; Bit15-12.....Reserved +dPSERR_DIAG_MASK equ 0FFFFh shl 16; Bit31-16 = Diagnostics + dPSERR_DIAG_N equ 1 shl 16; Bit-16 = PhyRdy Change + dPSERR_DIAG_I equ 1 shl 17; Bit-17 = Phy Internal Error + dPSERR_DIAG_W equ 1 shl 18; Bit-18 = Comm Wake + dPSERR_DIAG_B equ 1 shl 19; Bit-19 = 10B to 8B Decode Error + dPSERR_DIAG_D equ 1 shl 20; Bit-20 = Disparity Error + dPSERR_DIAG_C equ 1 shl 21; Bit-21 = CRC Error + dPSERR_DIAG_H equ 1 shl 22; Bit-22 = Handshake Error + dPSERR_DIAG_S equ 1 shl 23; Bit-23 = Link Sequence Error + dPSERR_DIAG_T equ 1 shl 24; Bit-24 = Transport State Transition Error + dPSERR_DIAG_F equ 1 shl 25; Bit-25 = Unknown FIS Type + dPSERR_DIAG_X equ 1 shl 26; Bit-26 = Exchanged + ; Bit31-27.....Reserved +; +;------------------------------------------------------------------------- +; +; Command List Structure +; +COMMAND_LIST_STRUC struc + dDW0 dd ? ; Description Information (details below) + dPRDBC dd ? ; Physical Region Descriptor Byte Count + dCTBA dd ? ; Command Table Base Address (lower 32bit) + dCTBAU dd ? ; Command Table Base Address (upper 32bit) + dReserved1 dd ? ; Reserved dword + dReserved2 dd ? ; Reserved dword + dReserved3 dd ? ; Reserved dword + dReserved4 dd ? ; Reserved dword +COMMAND_LIST_STRUC ends +; +; Details of dDW0 field +; +dDW0_CFL_MASK equ 1Fh shl 0 ; Bit4-0 = Command FIS Length (1-based) in #of DWords +dDW0_ATAPI equ 1 shl 5 ; Bit-5 = ATAPI +dDW0_WRITE equ 1 shl 6 ; Bit-6 = Direction of data transfer + ; 0 = Device Read (data from device to host) + ; 1 = Device Write (data from host to device) +dDW0_PREFETCHABLE equ 1 shl 7 ; Bit-7 = Prefetchable +dDW0_RESET equ 1 shl 8 ; Bit-8 = Device Reset +dDW0_BIST equ 1 shl 9 ; Bit-9 = BIST +dDW0_CLEAR_BSY equ 1 shl 10; Bit-10 = Clear Busy after xmitting FIS and receiving R_OK + ; Bit-11....Reserved +dDW0_PMP_MASK equ 0Fh shl 12; Bit15-12= Port multiplier number to be used + +dDW0_PRDTL_N equ 16 ; Bit-16 = Start bit of PRDTL +dDW0_PRDTL_MASK equ 0FFFFh shl 16;Bit31-16= Physical Region Descriptor Table Length + ; in #of entries, each entry is 4 DWords +;------------------------------------------------------------------------- +; Command Table +; +COMMAND_TABLE_STRUC struc + aCFIS db 40h dup (?) ; Area for command FIS + aACMD db 10h dup (?) ; Area for ATAPI command + aReserved db 30h dup (?) ; Reserbed area + aPRDT db ? ; Start of Physical Region Descriptor Tables +COMMAND_TABLE_STRUC ends +; +;------------------------------------------------------------------------- +; PRDT: Physical Region Descriptor Table +; +PRDT_STRUC struc + dDBA dd ? ; Data Base Address (lower 32bit) + dDBAU dd ? ; Data Base Address (upper 32bit) + dReserved dd ? ; Reserved + dDW3 dd ? ; Description Information (details below) +PRDT_STRUC ends +; +; Details of dDW3 field +; +dDW3_DBC_MASK equ 3FFFFFh shl 0; Bit21-0 = Data Byte Count (0-based) + ; Bit30-22...Reserved +dDW3_INTERRUPT equ 1 shl 31; Bit-31 = Generate interrupt when data is xferred +; +;------------------------------------------------------------------------- +; FIS: Frame Information Structure +; +; FIS Types and size in #of dwords +H2D_REGISTER_FIS_TYPE equ 27h + H2D_REGISTER_FIS_LENGTH_DWORD equ 05h +D2H_REGISTER_FIS_TYPE equ 34h + D2H_REGISTER_FIS_LENGTH_DWORD equ 05h +DMA_SETUP_FIS_TYPE equ 41h + DMA_SETUP_FIS_LENGTH_DWORD equ 07h +BIST_ACTIVATE_FIS_TYPE equ 58h + BIST_ACTIVATE_FIS_LENGTH_DWORD equ 03h +PIO_SETUP_FIS_TYPE equ 5Fh + PIO_SETUP_FIS_LENGTH_DWORD equ 05h +SET_DEVICE_BITS_FIS_TYPE equ 0A1h + SET_DEVICE_BITS_FIS_LENGTH_DWORD equ 02h +ACMD_FIELD_LENGTH_DWORD equ 03h ;(V1.07+) +; +H2D_REGISTER_FIS_STRUC struc + bFisType db ? ; FIS Type + bXferReason db ? ; Cause of transfer + COMMAND_REGISTER_UPDATE equ 80h; Bit-7 = 1, xfer is due to an update of command register + ; Bit6-0=....Reserved + bCommand db ? ; Command + bFeatures db ? ; Features + bSectorNumber db ? ; Sector Number + bCylinderLow db ? ; Cylinder Low + bCylinderHigh db ? ; Cylinder High + bDeviceHead db ? ; Device Head + bSectorNumberExp db ? ; Sector Number Exp + bCylinderLowExp db ? ; Cylinder Low Exp + bCylinderHighExp db ? ; Cylinder High Exp + bFeaturesExp db ? ; Features Exp + bSectorCount db ? ; Sector Count + bSectorCountExp db ? ; Sector Count Exp + bReserved1 db ? ; Reserved + bControl db ? ; Control + bReserved2 db ? ; Reserved + bReserved3 db ? ; Reserved + bReserved4 db ? ; Reserved + bReserved5 db ? ; Reserved +H2D_REGISTER_FIS_STRUC ends +; +D2H_REGISTER_FIS_STRUC struc + bFisType db ? ; FIS Type + bDeviceInterruptLine db ? ; Interrupt line of device + INTERRUPT_BIT equ 40h ; Bit-6 = it reflects interrupt bit line of the device + bStatus db ? ; Status + bError db ? ; Error + bSectorNumber db ? ; Sector Number + bCylinderLow db ? ; Cylinder Low + bCylinderHigh db ? ; Cylinder High + bDeviceHead db ? ; Device Head + bSectorNumberExp db ? ; Sector Number Exp + bCylinderLowExp db ? ; Cylinder Low Exp + bCylinderHighExp db ? ; Cylinder High Exp + bReserved1 db ? ; Features Exp + bSectorCount db ? ; Sector Count + bSectorCountExp db ? ; Sector Count Exp + bReserved2 db ? ; Reserved + bReserved3 db ? ; Control + bReserved4 db ? ; Reserved + bReserved5 db ? ; Reserved + bReserved6 db ? ; Reserved + bReserved7 db ? ; Reserved +D2H_REGISTER_FIS_STRUC ends +; +DMA_SETUP_FIS_STRUC struc + bFisType db ? ; FIS Type + bXferDirnAndInt db ? ; Xfer direction and interrupt + XFER_D2H equ 20h ; Bit-5 = 1, D2H xfer + XFER_H2D equ 00h ; 0, H2D xfer + INTERRUPT_PENDING equ 40h ; Bit-6 = interrupt pending + bReserved1 db ? ; Reserved + bReserved2 db ? ; Reserved + dDmaBufferIdentifierLow dd ? ; DMA Buffer Identifier Low + dDmaBufferIdentifierHigh dd ? ; DMA Buffer Identifier High + dReserved3 dd ? ; Reserved + dDmaBufferOffset dd ? ; DMA Buffer offset + dDmaXferCount dd ? ; DMA Transfer Count in bytes + dReserved4 dd ? ; Reserved +DMA_SETUP_FIS_STRUC ends +; +BIST_ACTIVATE_FIS_STRUC struc + bFisType db ? ; FIS Type + bReserved1 db ? ; Reserved + bPattern db ? ; Pattern Definition + bReserved2 db ? ; Reserved + dData1 dd ? ; Data1 + dData2 dd ? ; Data2 +BIST_ACTIVATE_FIS_STRUC ends +; +PIO_SETUP_FIS_STRUC struc + bFisType db ? ; FIS Type + bXferDirnAndInt db ? ; Xfer direction and interrupt + ; (bit defintions same as DMA_SETUP_FIS) + bStatus db ? ; Status + bError db ? ; Error + bSectorNumber db ? ; Sector Number + bCylinderLow db ? ; Cylinder Low + bCylinderHigh db ? ; Cylinder High + bDeviceHead db ? ; Device Head + bSectorNumberExp db ? ; Sector Number Exp + bCylinderLowExp db ? ; Cylinder Low Exp + bCylinderHighExp db ? ; Cylinder High Exp + bReserved1 db ? ; Reserved + bSectorCount db ? ; Sector Count + bSectorCountExp db ? ; Sector Count Exp + bReserved2 db ? ; Reserved + bE_Status db ? ; Status + wXferCount dw ? ; Xfer count in bytes + wReserved dw ? ; Reserved +PIO_SETUP_FIS_STRUC ends +; +SET_DEVICE_BITS_FIS_STRUC struc + bFisType db ? ; FIS Type + bFlags db ? ; Information flags + bStatus db ? ; Status + bError db ? ; Error + dReserved dd ? ; Reserved +SET_DEVICE_BITS_FIS_STRUC ends +; +; Receive FIS structure +FIS_RECEIVE_STRUC struc + aDSFIS DMA_SETUP_FIS_STRUC {?} ; DMA Setup FIS + bReserved1 db 04h dup (?) ; Reserved + aPSFIS PIO_SETUP_FIS_STRUC {?} ; PIO Setup FIS + bReserved2 db 0Ch dup (?) ; Reserved + aRFIS D2H_REGISTER_FIS_STRUC {?} ; D2H Register FIS + bReserved3 db 04h dup (?) ; Reserved + aSDBFIS SET_DEVICE_BITS_FIS_STRUC {?} ; Set Device Bits FIS + aUFIS db 40h dup (?) ; Unknown FIS + bReserved4 db 60h dup (?) ; Reserved +FIS_RECEIVE_STRUC ends +; +;------------------------------------------------------------------------- +;**************************************************************************** +;**************************************************************************** +;** ** +;** (C)Copyright 1985-2011, American Megatrends, Inc. ** +;** ** +;** All Rights Reserved. ** +;** ** +;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +;** ** +;** Phone (770)-246-8600 ** +;** ** +;**************************************************************************** +;**************************************************************************** + diff --git a/Chipset/eM/Ahci/AHCIACC.ASM b/Chipset/eM/Ahci/AHCIACC.ASM new file mode 100644 index 0000000..1f93536 --- /dev/null +++ b/Chipset/eM/Ahci/AHCIACC.ASM @@ -0,0 +1,1181 @@ + + TITLE AHCIACC.ASM - AHCI Register/Memory Acccess Routines + +;**************************************************************************** +;**************************************************************************** +;** ** +;** (C)Copyright 1985-2014, American Megatrends, Inc. ** +;** ** +;** All Rights Reserved. ** +;** ** +;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +;** ** +;** Phone (770)-246-8600 ** +;** ** +;**************************************************************************** +;**************************************************************************** + +;**************************************************************************** +; $Header: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AHCIACC.ASM 14 12/08/14 5:58a Anbuprakashp $ +; +; $Revision: 14 $ +; +; $Date: 12/08/14 5:58a $ +;**************************************************************************** +; Revision History +; ---------------- +; $Log: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AHCIACC.ASM $ +; +; 14 12/08/14 5:58a Anbuprakashp +; [TAG] EIP192297 +; [Category] Improvement +; [Description] Replacing SmmGetMemoryType usage in AHCI driver with +; AmiBufferValidationLib +; [Files] AhciInt13Smm.c, AhciInt13Smm.mak, AHCIACC.ASM +; +; 13 11/24/14 11:54p Kapilporwal +; [TAG] EIP191939 +; [Category] Improvement +; [Description] Issue about BIG_REAL_MODE_MMIO_ACCESS of AHCI module +; [Files] AI13.bin +; AHCIACC.ASM +; AhciInt13Dxe.c +; AhciInt13Dxe.dxs +; AhciInt13Smm.c +; AhciInt13Smm.cif +; AhciInt13Smm.dxs +; AhciInt13Smm.h +; AhciInt13Smm.mak +; AhciInt13Smm.sdl +; AInt13.c +; Aint13.cif +; AInt13.h +; AhciSmm.c +; AhciSmm.h +; AhciSmmProtocol.h +; +; 12 7/01/14 2:23a Nagadineshk +; [TAG] EIP172162 +; [Category] Bug Fix +; [Severity] Important +; [Symptom] Can't install legacy windows if achiacc.obj is not first +; one of CSM_OEM16_OBJS elink +; [RootCause] Wrong offset of Newly Hooked Interrupt(CPU Exception +; Interrupt) address loaded in Interrupt vector table. +; [Solution] Stored Correct Offset value in IVT +; [Files] AHCIACC.ASM +; +; 11 6/20/14 6:54a Nimishsv +; Recheck-in +; +; 10 12/17/13 7:06a Nimishsv +; [TAG] EIP131322 +; [Category] Improvement +; [Description] Improve S4 resume time with PCIE SSD +; under Win7, reported that if enable AHCIMMIOSMM_SUPPORT, +; and then S4 resume time is very long(about 50s) with win 7. +; (Add support for accessing MMIO region using BIG real mode) +; [Files] AhciMmioSmm.sdl, AHCIACC.asm +; +; 9 8/02/12 8:14a Deepthins +; [TAG] EIP93480 +; [Category] Bug Fix +; [Symptom] AHCI legacy support module is corrupting the memory. +; [RootCause] AHCI legacy support module is corrupting the memory as it +; was using wrong offset for storing the base address. +; [Solution] Properly calculating offset for storing the base address. +; [Files] AINT13.EQU, AInt13.c, AInt13.h and AHCIACC.ASM +; +; 8 1/13/12 12:20a Deepthins +; [TAG] EIP78099 +; [Category] Improvement +; [Description] Handle multiple AHCI controller in legacy. +; [Files] Aint13.sdl , AInt13.c , AInt13.h , AHCIACC.ASM , AHCI.EQU , +; AINT13.bin (AHCIACC.ASM , AINT13.EQU) +; +; 7 2/10/11 10:52a Rameshr +; [TAG] EIP53704 +; [Category] Improvement +; [Description] AMI headers update for Alaska Ahci Driver +; [Files] AHCIACC.ASM +; HACCESS.EQU +; AHCI.EQU +; AINT13.EQU +; AInt13Csp.c +; +; 6 6/21/10 5:34a Rameshr +; AHCI Legacy booting through MMIO reg. +; EIP 38444 +; +; 5 5/28/08 9:43a Rameshraju +; Updated the AMI Address. +; +; 4 3/28/08 10:03a Olegi +; +; 3 3/27/08 5:33p Olegi +; +; 2 19/12/07 4:28p Anandakrishnanl +; Modified the relative offsets to be absolute. +; +; 1 12/07/07 11:17a Olegi +; +;**************************************************************************** + +;---------------------------------------------------------------------------- +; INCLUDE FILES +;---------------------------------------------------------------------------- + include ahci.equ + include haccess.equ + include aint13.equ + include token.equ + + FLAT_MODE_INDEX equ 08h + REAL_MODE_INDEX equ 10h +;---------------------------------------------------------------------------- +; EXTERNS USED +;---------------------------------------------------------------------------- +.586p +OEM16_CSEG SEGMENT PARA PUBLIC 'CODE' USE16 + ASSUME cs:OEM16_CSEG, ds:OEM16_CSEG +;------------------------------------------------------------------------- + PUBLIC AhciApiModuleStart +AhciApiModuleStart LABEL BYTE + jmp SHORT AhciCsm16Api + dw AhciDataStart - AhciApiModuleStart + + +;---------------------------------------------------------------------------- +; IMPORTANT: Do not put any OEM/CHIPSET code above this, the above code and +; and data are at fixed locations. +;---------------------------------------------------------------------------- + +;------------------------------------------------------------------------- +; AHCI_CSM16_API_Start +;---------------------------------------------------------------------------- +; This routine is implementation of the CSM16 API #7. +; Input: CX 80h - ReadRegisterDword call +; 00h - WriteRegisterDword call +; 01h - WaitForFisRecRun call +; For read/write functions: +; SS:SP+3Eh (originally ESI) HBA Base Address +; SS:SP+42h (originally EBX) Port#, Register Offset +; Bit31-16 = Port# (0-based) +; FFFF for Generic Host Control Register +; Bit15-0 = Register offset +; SS:SP+46h (originally EAX) Data to be written +; For WaitForFisRecRun function: +; No input +; Output: NC Successful +; EAX Data read +; CY Error +; Register Usage: Do not destroy any register except EAX +; +;---------------------------------------------------------------------------- +; +AhciCsm16Api PROC FAR PUBLIC +; Adjust current IP so that the data offsets are valid + call $+3 ; Push curent IP + pop bx ; Get current IP in BX + shr bx, 4 + mov ax, cs ; Always x000h + add ax, bx ; New CS + push ax + push newOffset-AhciApiModuleStart + retf ; Execute from new CS:IP + +newOffset: + push bp + mov bp, sp + mov eax, ss:[bp+48h] ; Data to be written (ignored for Read function) + mov ebx, ss:[bp+44h] ; Port# + mov esi, ss:[bp+40h] ; HBA Base Address + + cmp cx, 0 + jz aca_WriteCall + cmp cx, 80h + jnz aca_WaitForFisRecRun + call ReadRegisterDword + jmp SHORT aca_Exit +aca_WaitForFisRecRun: + call WaitForFisRecRun + jmp SHORT aca_Exit +aca_WriteCall: + call WriteRegisterDword + +aca_Exit: + pop bp + +; Adjust sp as if we returned to csm16_func_ret + add sp, 4 ; cs:ip of F000:csm16_func_ret + +; Save EAX, restore it after popad + push eax + pop ds + pop gs +;csm16_func_ret: + popad + push gs + push ds + pop eax + + pop gs + pop fs + pop es + pop ds + +;csm16_exit: + popf + pop ds + pop si + + add sp, 2 ; Do not "pop ax", preserving return code + +; Prepare for FAR return - fetch the CS and patch the segment for RETF + mov cx, WORD PTR ss:[bp+1ah] + mov WORD PTR ss:[bp+06h], cx +; Restore CX + mov cx, WORD PTR ss:[bp+18h] + mov dx, WORD PTR ss:[bp+16h] ;Restore Dx + + pop bp + add sp, 4 + clc + retf 18 + +AhciCsm16Api ENDP + +; +;------------------------------------------------------------------------- +; ReadRegisterDword +;---------------------------------------------------------------------------- +; This routine reads the register. +; Input: ESI HBA Base Address +; EBX Port#, Register Offset +; Bit31-16 = Port# (0-based) +; FFFF for Generic Host Control Register +; Bit15-0 = Register offset +; Output: NC Successful +; EAX Data read +; CY Error +; Register Usage: Do not destroy any register except EAX +; +;---------------------------------------------------------------------------- +; +ReadRegisterDword_FAR PROC FAR PUBLIC + call ReadRegisterDword ; EAX = data read if read + ret +ReadRegisterDword_FAR ENDP + +ReadRegisterDword PROC NEAR PUBLIC + push esi + call CalculateRegisterOffset ; ESI = register offset from base + + push dx ; Dx has the controller number + cli + push bx ; Save bx value in stack + push ax ; Save ax value in stack + mov ax, 0 + mov al, dl ; Move the controller no into al + mov bl, 8 + mul bl ; Multiply it with 8 as AHCI_ACCESS\ + ; structure size is 8 + mov bx, ax ; Move the offset into bx + pop ax ; Restore ax +IF (MKF_AHCI_INT13_SMM_SUPPORT) + push ebx + push ecx + mov ebx, dword ptr cs:[AhciDataStart - AhciApiModuleStart +4+bx] ;ebx=Data + add esi,ebx +IF (MKF_BIG_REAL_MODE_MMIO_ACCESS) + call ReadDWORD +ELSE + mov cx,1 ;Read Function + call AhciGenerateSwSMI + cmp ecx, 0 ; if ECX == 0, MMIO read is Success + jz Read_Success + stc + jmp Read_Return +Read_Success: + clc +Read_Return: +ENDIF + pop ecx + pop ebx + jmp Read_done +ENDIF + mov dx, cs:[AhciDataStart - AhciApiModuleStart +bx] ; DX = Index Port + push eax + mov eax, esi ; EAX = register address + out dx, eax ; Write Address + pop eax + + mov dx, cs:[AhciDataStart - AhciApiModuleStart +2+bx] ; DX = Data Port + in eax, dx ; EAX = adat + + clc ; NC, Successful +Read_done: + pop bx + pop dx + + pop esi + ret +ReadRegisterDword ENDP +; +;---------------------------------------------------------------------------- +; WriteRegisterDword +;---------------------------------------------------------------------------- +; This routine writes the register. +; Input: ESI HBA Base Address +; EBX Port#, Register Offset +; Bit31-16 = Port# (0-based) +; FFFF for Generic Host Control Register +; Bit15-0 = Register offset +; EAX Data to be written +; Output: NC Successful +; CY Error +; Register Usage: Do not destroy any register +; +;---------------------------------------------------------------------------- +; +WriteRegisterDword_FAR PROC FAR PUBLIC + call WriteRegisterDword + ret +WriteRegisterDword_FAR ENDP + +WriteRegisterDword PROC NEAR PUBLIC + push esi + call CalculateRegisterOffset ; ESI = register offset from base + + push dx ; Dx has the controller number + cli + push bx ; Save bx value in stack + push ax ; Save ax value in stack + mov ax, 0 + mov al, dl ; Move the controller no into al + mov bl, 8 + mul bl ; Multiply it with 8 as AHCI_ACCESS\ + ; structure size is 8 + mov bx, ax ; Move the offset into bx + pop ax ; Restore ax + +IF (MKF_AHCI_INT13_SMM_SUPPORT) + push ebx + push ecx + mov ebx, dword ptr cs:[AhciDataStart - AhciApiModuleStart +4+bx] + add esi,ebx +IF (MKF_BIG_REAL_MODE_MMIO_ACCESS) + call WriteDWORD +ELSE + mov ebx,eax ;Write Value + mov cx,2 ;Write Function + call AhciGenerateSwSMI + cmp ecx, 0 ; if ECX == 0, MMIO write is Success + jz Write_Success + stc + jmp Write_Return +Write_Success: + clc +Write_Return: +ENDIF + pop ecx + pop ebx + jmp Write_done +ENDIF + mov dx, cs:[AhciDataStart - AhciApiModuleStart +bx] ; DX = Index Port + push eax + mov eax, esi ; EAX = register address + out dx, eax ; Write Address + pop eax + + mov dx, cs:[AhciDataStart - AhciApiModuleStart +2+bx] ; DX = Data Port + out dx, eax ; Write dword data + clc ; NC, Successful +Write_done: + pop bx + pop dx + + pop esi + ret +WriteRegisterDword ENDP +; +;---------------------------------------------------------------------------- +; CalculateRegisterOffset +;---------------------------------------------------------------------------- +; This routine calculates the register offset from HBA Base. +; Input: EBX Port#, Register Offset within Port +; Bit31-16 = Port# (0-based) +; FFFF for Generic Host Control Register +; Bit15-0 = Register offset +; Output: ESI Register Offset from HBA Base +; Register Usage: Do not destroy any register except ESI +; +;---------------------------------------------------------------------------- +; +CalculateRegisterOffset PROC NEAR PRIVATE + push cx + push ebx + mov cx, bx ; CX = register offset + shr ebx, 16 ; BX = Port# (0-based) + inc bx ; Port# valid? + jz short cro_00 ; No + dec bx ; BX = Port# (0-based) + shl bx, PORT_REGISTER_SET_SIZE_N + add bx, PORT_REGISTER_START +cro_00: + add bx, cx ; BX = Port register offset from HBA base address + movzx esi, bx ; ESI = Port register offset from HBA base address + pop ebx + pop cx + ret +CalculateRegisterOffset ENDP + +; +;---------------------------------------------------------------------------- +; WaitForFisRecRun +;---------------------------------------------------------------------------- +; This routine executes HBA wait for FIS rec run code. If not +; implemented (just ret), AHCI INT13 code will execute the default routine. +; Implement this routine for different OEM/Chipset vendor and return 0 in AL +; to override the default routine execution. +; +; Output: AH 0 if implemented +; +;---------------------------------------------------------------------------- +; +WaitForFisRecRun PROC NEAR PUBLIC + ret +WaitForFisRecRun ENDP + +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: AhciGenerateSwSMI +; +; Description: Generate the Sw SMI to read the MMIO space. +; if the system is in big real mode, read/write the MMIO space without +; SwSMI +; +; Input: Cx = 1 - Read MMIO +; Cx= 2 - Write MMIO +; Eax= Value to write in MMIO for write MMIO +; +; Output: Eax- for Read MMIO +; +; Modified: Ds +; +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> +IF (MKF_AHCI_INT13_SMM_SUPPORT) +AhciGenerateSwSMI PROC NEAR PUBLIC + call Check_Big_Real_mode + jc NotBigReadMode + push es + push 0 + pop es + + cmp cx,1 + je ReadMmio + mov dword ptr es:[esi],eax ;Write MMIO + pop es + ret +ReadMmio: + mov eax,dword ptr es:[esi] ;Read MMIO + pop es + ret +NotBigReadMode: + + mov dx,MKF_SW_SMI_IO_ADDRESS + mov al,MKF_AHCI_INT13_SMM_SWSMI_VALUE + out dx,al ;Generate Sw SMI to Read/Write MMIO + jmp $+2 + ret +AhciGenerateSwSMI ENDP + +;------------------------------------------------------------------------- +; ReadDWORD +;------------------------------------------------------------------------- +; This routine reads DWORD from MMIO. +; Input: ESI HBA Base Address +; +; Output: NC Successful +; EAX Data read +; CY Error +; Register Usage: Do not destroy any register except EAX +; +;------------------------------------------------------------------------- +ReadDWORD PROC NEAR PUBLIC + + push ds + + push 0 + pop ds + + push esi + +; Save original values of registers in stack + push ebx + push es + push di + +; Save a dword from 5000h + mov bx, 5000h + mov es, bx + mov di, 00h + mov ebx, dword ptr es:[di] + + push ebx + + mov byte ptr es:[di], 00h +; Switching to Big Real Mode + call Switch_Big_Real_Mode + +; Reading DWORD from Hba_base_address and store in EAX + mov eax, dword ptr ds:[esi] + + push eax + movzx eax, byte ptr es:[di] + and eax, 01h + jz rdw_done +; Switch back from Big Real mode + call Switch_Original_Mode + +rdw_done: + pop eax + + push eax + movzx eax, byte ptr es:[di] + and eax, 10b + jz org_g20 + call DisblGateA20 +org_g20: + pop eax + + pop ebx +; Restore the original values stored in stack + mov dword ptr es:[di], ebx + + pop di + pop es + pop ebx + + pop esi + + pop ds + clc + + ret +ReadDWORD ENDP + +;------------------------------------------------------------------------- +; WriteDWORD +;------------------------------------------------------------------------- +; This routine writes DWORD in MMIO space. +; Input: EAX Data to be written +; +; Output: ESI HBA Base Address +; NC Successful +; CY Error +; +; Register Usage: Do not destroy any register except EAX +; +;------------------------------------------------------------------------- +WriteDWORD PROC NEAR PUBLIC + push ds + + push 0 + pop ds + + push esi + +; Save original values of registers in stack + push ebx + push es + push di + +; Save a dword from 5000h + mov bx, 5000h + mov es, bx + mov di, 00h + mov ebx, dword ptr es:[di] + + push ebx + + mov byte ptr es:[di], 00h +; Switching to Big Real Mode + call Switch_Big_Real_Mode + +; Writing DWORD stored in EAX into Hba_base_address + mov dword ptr ds:[esi],eax + + push eax + movzx eax, byte ptr es:[di] + and eax, 01h + jz wdw_done + +; Switch back from Big Real mode + call Switch_Original_Mode + +wdw_done: + pop eax + + push eax + movzx eax, byte ptr es:[di] + and eax, 10b + jz org_g201 + call DisblGateA20 +org_g201: + pop eax + pop ebx + +; Restore the original values stored in stack + mov dword ptr es:[di], ebx + + pop di + pop es + pop ebx + + pop esi + + pop ds + clc + + ret +WriteDWORD ENDP + +;---------------------------------------------------------------------------- +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: Switch_Big_Real_Mode +; +; Description: Switch to Big real Mode. +; +; Input: None +; +; Output: +; +; Modified: DS, ES +; +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> +;---------------------------------------------------------------------------- +Switch_Big_Real_Mode PROC NEAR PUBLIC + + push di + call Check_Big_Real_mode + jnc InBigRealMode + mov byte ptr es:[di], 01h + +InBigRealMode: + + mov di, FLAT_MODE_INDEX ;Index for flat mode + call GotoProtectedMode + + pop di + ret + +Switch_Big_Real_Mode ENDP + +;---------------------------------------------------------------------------- +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: Switch_Original_Mode +; +; Description: Switch to Original Mode. +; +; Input: None +; +; Output: +; +; Modified: DS, ES +; +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> +;---------------------------------------------------------------------------- +Switch_Original_Mode PROC NEAR PUBLIC + + push di + mov di, REAL_MODE_INDEX ;Real mode index + call GotoProtectedMode + pop di + + ret + +Switch_Original_Mode ENDP + +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: GotoProtectedMode +; +; Description: This function jumps to protected mode for 4GB limit access +; +; Input: None +; +; Output: None +; +; Modified: None +; +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> + +GotoProtectedMode PROC NEAR PUBLIC + push es + pusha + cli ; Disable interrupts. +; Check the GA20 status.. +; Compare 256bytes at 0:0 with FFFF:10 +; If match, GA20 is disabled else GA20 is enabled. + push di + push es + push ds + push 0000h + pop ds ; DS = 0000. + push 0FFFFh + pop es ; ES = FFFF. + mov cx, 100h / 4 ; Number of Dwords in 256bytes. + xor si, si + mov di, 0010h + repz cmpsd + pop ds + pop es + pop di ;Descriptor table index in di + + pushf ; Save GA20 status + ; ZR/NZ = disabled/enabled. + jnz short gtbrm_00 ; GA20 is already enabled. + + push di + mov di, 00h + or byte ptr es:[di], 10b + pop di + call EnblGateA20 ; Enable GateA20. + +gtbrm_00: + call go_big_mode ; Go to protected mode and comeback + ; to real mode. + popf ; ZR/NZ = GA20 status. + stc ; Routine went to big real mode. + +gtbrm_01: + popa + pop es + ret ; Return to caller. +GotoProtectedMode ENDP + +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: EnblGateA20 +; +; Description: This function enables GateA20 +; +; Input: None +; +; Output: None +; +; Modified: None +; +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> + +EnblGateA20 PROC NEAR PUBLIC + + push ax + mov al,02h + out 92h, al + +; Check the GA20 status.. +; Compare 256bytes at 0:0 with FFFF:10 +; If match, GA20 is disabled else GA20 is enabled. + push di + push es + push ds + push 0000h + pop ds ; DS = 0000. + push 0FFFFh + pop es ; ES = FFFF. + mov cx, 100h / 4 ; Number of Dwords in 256bytes. + xor si, si + mov di, 0010h + repz cmpsd + pop ds + pop es + pop di ;Descriptor table index in di + + jnz eg20_end + + mov al, 0DFh ; Data for output port to enable A20. + out 60h, al + mov al, 0D1h + out 64h, al + +eg20_end: + pop ax + + ret +EnblGateA20 ENDP + +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: go_big_mode +; +; Description: This routine goes to protected mode, sets the DS, ES to the +; given selector, comes back to real mode and sets DS, ES to 0000. +; +; Input: DX - Selector. +; +; Output: Selector 00 can be used to access 4GB. +; +; Modified: EAX. +; +; Referrals: big_gdt. +; +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> + +go_big_mode PROC NEAR PRIVATE + + jmp Executable_code + +;<AMI_SHDR_START> +;---------------------------------------------------------------------------- +; Name: big_gdt +; +; Type: BYTE Array +; +; Description: Global Descriptor Table to switch the system to/from FLAT Mode. +; Since these routines will be called from non-shadowed system +; ROM, the GDT must be on a QWORD boundary or else the bytes +; will get CORRUPTED! +; +;---------------------------------------------------------------------------- +;<AMI_SHDR_END> + +ALIGN 8 +big_gdt LABEL WORD + db 8 dup (0) ;00 - Null descriptor + db 0FFh,0FFh,000h,000h,000h,093h,08Fh,000h ; 08h - DS descriptor for flat mode +big_gdt_end LABEL WORD + +big_gdt_real LABEL WORD + db 8 dup (0) ;00 - Null descriptor + db 0FFh,0FFh,000h,000h,000h,093h,000h,000h ; 08h - DS descriptor for real mode +big_gdt_real_end LABEL WORD + +GDT_DESC LABEL BYTE + dw 010h ; Length of GDT + db 00,00h ; ptr to GDT + db 05h,00h +GDT_DESC_END LABEL BYTE + +Executable_code: + + push ds + push es + push eax + push ebx + push ecx + push edx + push si + push di + +; Changed for CSM - need to save SS, reload SS Limit to 64K selector and restore it + push bp + mov bp, ss + + mov al, 8Dh ; Disable NMI + out 70h, al + +;;; Copy contents from 5000:00(16 bytes) into registers + mov ax, 5000h + mov es, ax + mov si, 00h + mov eax, dword ptr es:[si] + add si, 4 + mov ebx, dword ptr es:[si] + add si, 4 + mov ecx, dword ptr es:[si] + add si, 4 + mov edx, dword ptr es:[si] + push eax + push ebx + push ecx + push edx + +;;; Copy GDT to 5000h:00h + mov ax, cs + mov ds, ax + cmp di, 08h + jne gbm_real + mov si, offset cs:big_gdt + jmp gbm_flat +gbm_real: + mov si, offset cs:big_gdt_real +gbm_flat: + mov ax, 5000h + mov es, ax + mov di, 00h + xor cx, cx + mov cx, 08h + rep movsw + + lgdt fword ptr cs:GDT_DESC + mov eax, cr0 + or al, 01h + mov cr0, eax ; In protected mode. + jmp gbm_00 ; Flush instruction queue - JMP (NEAR) + ; to next instruction. + +gbm_00: + mov ax, 08h ; Selector + mov ds, ax ; DS = selector. + mov es, ax ; ES = selector. + + mov eax, cr0 ; Come back into real mode with DS,ES + and al, 0FEh + mov cr0, eax + jmp gbm_01 ; Flush instruction queue - JMP (NEAR) + ; to next instruction. +gbm_01: + + xor ax, ax + mov ds, ax + mov es, ax + + pop edx + pop ecx + pop ebx +;;; Restore contents of 5000:00h(16 bytes) from registers + mov ax, 5000h + mov es, ax + mov si, 00h + pop eax + mov dword ptr es:[si], eax + add si, 4 + mov dword ptr es:[si], ebx + add si, 4 + mov dword ptr es:[si], ecx + add si, 4 + mov dword ptr es:[si], edx + + pop bp + pop di + pop si + pop edx + pop ecx + pop ebx + pop eax + pop es + pop ds + ret +go_big_mode ENDP + +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: DisblGateA20 +; +; Description: This function disables GateA20 +; +; Input: None +; +; Output: None +; +; Modified: None +; +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> + +DisblGateA20 PROC NEAR PUBLIC + + push ax + mov al,00h + out 92h, al + +; Check the GA20 status.. +; Compare 256bytes at 0:0 with FFFF:10 +; If match, GA20 is disabled else GA20 is enabled. + push di + push es + push ds + push 0000h + pop ds ; DS = 0000. + push 0FFFFh + pop es ; ES = FFFF. + mov cx, 100h / 4 ; Number of Dwords in 256bytes. + xor si, si + mov di, 0010h + repz cmpsd + pop ds + pop es + pop di ;Descriptor table index in di + + jz dg20_end + + mov al, 0DDh ; Data for output port to disables A20. + out 60h, al + mov al, 0D1h + out 64h, al + +dg20_end: + pop ax + + ret + +DisblGateA20 ENDP + +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: Get_EBDA +; +; Description: Get the EBDA Segment Address +; +; Input: None +; +; Output: DS: Ebda Segment +; +; Modified: Ds +; +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> +Get_EBDA PROC NEAR PUBLIC + + push 40h + pop ds + mov ds, ds:[0Eh] ; DS - EBDA segment. + ret + +get_EBDA ENDP + +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: Int0DHandler +; +; Description: Exception 0D handler +; +; Input: None +; +; Output: Exception_flag Set +; +; Modified: None +; +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> +Int0DHandler PROC NEAR PUBLIC + push ds + call Get_EBDA + mov byte ptr ds:[102h],1 ;Set the Flag in Ebda:102 + pop ds + pop ax + add ax, 5 ; Go to Next instruction that doesn't + ; cause Exception + push ax + iret +Int0DHandler ENDP + +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: Check_Big_Real_mode +; +; Description: This function checks wheather system is in Big real mode +; +; Input: None +; +; Output: Carry Set - Not in Big Real mode +; Carry Not Set- System is in Big Real mode +; +; Modified: None +; +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> +Check_Big_Real_mode PROC NEAR PUBLIC + push eax + push edi + push ebx + push es + push ds + pushf + cli + + call Get_EBDA + + mov byte ptr ds:[102h],0 ;EBDA:102 + + push 0 + pop es + + mov eax, dword ptr es:[0Dh*4] + push eax + + push cs ; Runtime segment + push offset cs:Int0DHandler-AhciApiModuleStart + pop eax + mov dword ptr es:[0Dh*4], eax + + + mov edi,0100000h + mov eax,dword ptr es:[edi] + cmp byte ptr ds:[102h],1 ;Check the exception + je Real_mode + + mov edi,0 + mov ebx,dword ptr es:[edi] + cmp eax,ebx + je Real_mode + + ;Read ,Write test for above 1Mb area + mov edi,0100000h + mov ebx,dword ptr es:[edi] + mov eax,055AA55AAh + mov dword ptr es:[edi],eax + mov eax,dword ptr es:[edi] + mov dword ptr es:[edi],ebx + cmp eax,055AA55AAh + jne Real_mode + pop eax + mov dword ptr es:[0Dh*4], eax + popf + clc ;System is in Big Real Mode + jmp Exit_Ret + +Real_mode: + pop eax + mov dword ptr es:[0Dh*4], eax + popf + stc ;System is in Real Mode +Exit_Ret: + pop ds + pop es + pop ebx + pop edi + pop eax + ret +Check_Big_Real_mode ENDP + +ENDIF + +AhciDataStart label word +AhciAccess AHCI_ACCESS (MKF_AHCI_CONTROLLER_COUNT) dup (<>) + +OEM16_CSEG ENDS + +END +;**************************************************************************** +;**************************************************************************** +;** ** +;** (C)Copyright 1985-2014, American Megatrends, Inc. ** +;** ** +;** All Rights Reserved. ** +;** ** +;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +;** ** +;** Phone (770)-246-8600 ** +;** ** +;**************************************************************************** +;**************************************************************************** diff --git a/Chipset/eM/Ahci/AINT13.EQU b/Chipset/eM/Ahci/AINT13.EQU new file mode 100644 index 0000000..f51aaf8 --- /dev/null +++ b/Chipset/eM/Ahci/AINT13.EQU @@ -0,0 +1,748 @@ +; TITLE aint13.equ - Equates and structures for AHCI INT13 +;**************************************************************************** +;**************************************************************************** +;** ** +;** (C)Copyright 1985-2011, American Megatrends, Inc. ** +;** ** +;** All Rights Reserved. ** +;** ** +;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +;** ** +;** Phone (770)-246-8600 ** +;** ** +;**************************************************************************** +;**************************************************************************** + +;**************************************************************************** +; $Header: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AINT13.EQU 5 8/02/12 8:17a Deepthins $ +; +; $Revision: 5 $ +; +; $Date: 8/02/12 8:17a $ +; +;**************************************************************************** +; Revision History +; ---------------- +; $Log: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AINT13.EQU $ +; +; 5 8/02/12 8:17a Deepthins +; [TAG] EIP93480 +; [Category] Bug Fix +; [Severity] Normal +; [Symptom] AHCI legacy support module is corrupting the memory. +; [RootCause] AHCI legacy support module is corrupting the memory as it +; was using wrong offset for storing the base address. +; [Solution] Properly calculating offset for storing the base address. +; [Files] AINT13.EQU, AInt13.c, AInt13.h and AHCIACC.ASM +; +; 4 1/13/12 12:21a Deepthins +; [TAG] EIP78099 +; [Category] Improvement +; [Description] Handle multiple AHCI controller in legacy. +; [Files] Aint13.sdl , AInt13.c , AInt13.h , AHCIACC.ASM , AHCI.EQU , +; AINT13.bin (AHCIACC.ASM , AINT13.EQU) +; +; 3 2/10/11 10:52a Rameshr +; [TAG] EIP53704 +; [Category] Improvement +; [Description] AMI headers update for Alaska Ahci Driver +; [Files] AHCIACC.ASM +; HACCESS.EQU +; AHCI.EQU +; AINT13.EQU +; AInt13Csp.c +; +; 2 5/28/08 9:44a Rameshraju +; Updated the AMI Address. +; +; 1 12/07/07 11:17a Olegi +; +; 7 9/20/07 1:41a Davidhsieh +; +; 6 9/11/07 6:54a Chung +; 1. Add Security Function. +; 2. Modify AHCI Code. +; +; 5 6/06/07 2:06a Chung +; Add AHCI HD Mode Information +; +; 4 5/03/07 4:02a Chung +; EIP9321 - Add SMART function for self test. +; +; 2 1/29/07 1:25a Iminglin +; +; 1 1/25/07 1:21a Iminglin +; Changed by James. +; +; 15 12/20/06 2:26a Iminglin +; 1. Prepare Port Multiplier support. +; 2. Display SMART status. +; +; 14 12/05/06 3:15a Iminglin +; Remove useless equates. +; +; 13 11/09/06 3:47a Iminglin +; Make code generic. +; +; 12 10/27/06 4:28a Iminglin +; Rename Int13 function 48 structure. +; +; 11 10/24/06 11:25p Iminglin +; Stylization. +; +; 10 9/13/06 1:58a Iminglin +; Issue Freeze Lock Command. +; +; 9 7/14/06 4:28a Iminglin +; Clearificatoin. +; +; 8 6/01/06 11:25p Iminglin +; Enable SMART function. +; +; 7 5/19/06 2:09a Iminglin +; Intel source v1.00 change. +; +; 6 3/27/06 12:49a Iminglin +; Change Device Path length. +; +; 5 11/10/05 10:32p Iminglin +; Add smart handle. +; +; 4 10/25/05 2:25a Iminglin +; Remove CD structure. +; +; 3 10/20/05 4:35a Iminglin +; Give a solution for byte alignment. +; +; 2 10/05/05 6:57a Iminglin +; CDROM data structure +; +; 1 6/09/05 11:29p Iminglin +; Initialized version +; +; 1 5/20/05 2:37a Iminglin +; Intel AHCI source +; +;**************************************************************************** +; +;************************************************************************; +;* *; +;* Intel(r) Restricted Secret *; +;* *; +;* Support for and Booting from SATA devices in AHCI mode *; +;* *; +;* Enterprise Software Technology *; +;* *; +;* Copyright (c) 2003-2005 Intel Corporation *; +;* *; +;* Version iSrc03x *; +;* *; +;* This information is provided in connection with Intel products. *; +;* No license, express or implied, by estoppel or otherwise, to *; +;* any intellectual property rights is granted by this information *; +;* or by the sale of Intel products. Except as provided in Intel's *; +;* Terms and Conditions of Sale for such products, Intel assumes *; +;* no liability whatsoever, and Intel disclaims any express or *; +;* implied warranty, relating to sale and/or use of Intel products *; +;* including liability or warranties relating to fitness for a *; +;* particular purpose, merchantability, or infringement of any *; +;* patent, copyright or other intellectual property right. Intel *; +;* products are not intended for use in medical, life saving, or *; +;* life sustaining applications. *; +;* Intel retains the right to make changes to specifications and *; +;* product descriptions at any time, without notice and may choose *; +;* to develop product based on these designs. *; +;* *; +;* *Third-party brands and names are the property of their *; +;* respective owners. *; +;* *; +;************************************************************************; +;* *; +;* REFERENCES *; +;* *; +;* Revision Title *; +;* ==================================================================== *; +;* 1.0 Serial ATA Advanced Host Controller Interface (AHCI) *; +;* *; +;************************************************************************; +; +;------------------------------------------------------------------------- +; IMPLEMENTATION RELATED EQUATES AND STRUCTURES +;------------------------------------------------------------------------- +; SATA Device Information Table +; 1. Contains the AHCI related data for the device +; 2. Built during POST +; 3. Each device has its own table +DEV_INFO_STRUC STRUC + bDetectType db ? ;Detected Device Type (Details Below) + bInstalledType db ? ;Device Installed Type (See Below) + wStatus dw ? ;Bit-mapped device Init Status (Details Below) + bInt13Num db ? ;Device# for INT13 (8xh) + bPMNum db ? ;Port Multipier Port # + bPortNum db ? ;SATA Port# (0-Based) where device is present + wBusDevFunc dw ? ;Bus#, Dev#, Func# of Controller + bControllerNo db ? ;Ahci Controller number + dHbaBase dd ? ;HBA Base Address of Generic Host Control Registers + dHbaCap dd ? ;HBA Capabilities + dPortBase dd ? ;Base Address of SATA port where device is present + bSelector db ? ;Device selector value + bIrq db ? ;IRQ used by this device + bInfoFlag db ? ;Information Flag (details below) + bSectorSizeN db ? ;N value of Sector size 2^N + ;For 512bytes sector, N = 9 + wSmartInfo dw ? ;SMART info (details below) + qTotalSectors dq ? ;Total #of sectors in device (1-based) + wXferCount dw ? ;Device transfer count. Used for ATAPI packer size + bBlockInfo db ? + b32BitInfo db ? + bUDMAInfo db ? + bPIOInfo db ? +DEV_INFO_STRUC ENDS + +; Details of bDetectType +DETECT_NO EQU 00h ;Not detected +DETECT_ATA EQU 01h ;device detected is ATA +DETECT_ATAPI_CD EQU 02h ;device detected is ATAPI CDROM +DETECT_ATAPI_ARMD EQU 03h ;device detected is ATAPI ARMD + +; Details of bInstalledType +INSTALLED_NO EQU 00h ;Not installed +INSTALLED_HDD EQU 01h ;device installed as ATA HDD +INSTALLED_CDROM EQU 02h ;device installed as ATAPI CDROM +INSTALLED_ARMD_FDD EQU 03h ;device installed as ATAPI ARMD FDD +INSTALLED_ARMD_HDD EQU 04h ;device installed as ATAPI ARMD HDD + +; Details of wStatus +ST_SUCCESS EQU 0001h ;Bit 0 = 1, successful (device is installed in this case) +ST_ID_DEV_ERR EQU 0002h ;Bit 1 = 1, Identify Device Failed +ST_DEV_GEOMETRY_ERR EQU 0004h ;Bit 2 = 1, Invalid Device Geometry +ST_INIT_DEV_PARAM_ERR EQU 0008h ;Bit 3 = 1, Init device parameter failed +ST_RECALI_ERR EQU 0010h ;Bit 4 = 1, Recalibrate failed +ST_SMART_ERR EQU 0020h ;Bit 5 = 1, SMART failed +ST_VERIFY_ERR EQU 0040h ;Bit 6 = 1, Verify failed +ST_FREEZE_LOCK_ERR EQU 0080h ;Bit 7 = 1, Security Freeze Lock failed +ST_PORT_RESET_ERR EQU 0100h ;Bit 8 = 1, Port Reset failed +ST_SMART_EVENT EQU 0200h ;Bit 9 = 1, SMART Event was found +ST_RAID_SUPPORT_ERR EQU 0400h ;Bit 10 = 1, Device will be supported by RIAD OROM, not AHCI OROM (ex. HDD) + ;Bit 14-11, Reserved for future use +ST_NOT_SUPPORT_ERR EQU 8000h ;Bit 15 = 1, Device not supported + +; Details of bInfoFlag, a bit-mapped field +INFO_REMOVABLE EQU 01h ;Bit 0 = 1, Device supports removable media +INFO_LBA_48 EQU 02h ;Bit 1 = 1, 48bit LBA enabled +INFO_IRQ EQU 04h ;Bit 2 = 1, Device uses IRQ + ; 0, Device uses DRQ + ;Bit 6-2, Reserved +INFO_ATAPI EQU 80h ;Bit 7 = 1, ATAPI Device + ; 0, ATA Device + +; Details wSmartInfo +AHCI_SMART_SUPPORT EQU 1 shl 0 ;Bit 0 = 0/1, SMART (Not Supported/Supported) +AHCI_SMART_ENABLE EQU 1 shl 1 ;Bit 1 = 0/1, SMART (Disabled/Enabled) +AHCI_SMART_EN EQU 1 shl 1 ;Bit 1 = 0/1, SMART (Disabled/Enabled) +AHCI_SMART_STATUS EQU 1 shl 2 ;Bit 2 = 0/1, Device Status Good/Bad +AHCI_SMART_COMMAND_STATUS EQU 1 shl 7 ;Bit 7 = 0/1, SMART Execution Successful/Error + ;Bit 15-8, Reserved + +; Details qTotalSectors +; This contains the total #of sectors (1-based) in the device. + +;------------------------------------------------------------------------- +; Table containing the pointers to different tables +; 1. Initialized during POST +DEV_PTR_STRUC struc + bInt13Num db ? ; INT13 Drive# for this Port + bPMnum db ? ; Port Multipier port # + bPortNum db ? ; Port# (0-based) on Controller + dParamTablePtr dd ? ; Ptr to device parameter table + dInfoTablePtr dd ? ; Ptr to device info table +DEV_PTR_STRUC ends + +;------------------------------------------------------------------------- + ;(amiahcix-)> +;;;;; INIT_DEV_FUNC_STRUC: Used in INIT_DEVICE_TABLE while initializing device. +;;;;INIT_DEV_FUNC_STRUC struc +;;;; wFunction dw ? ; Routine to be executed +;;;; wStatus dw ? ; Bit-mapped status if error +;;;; bAttrib db ? ; Attribute (details below) +;;;;INIT_DEV_FUNC_STRUC ends +;;;; +;;;;; Details of bAttribute field +;;;;ATTRIB_ERROR equ 01h ;Bit-0 = 0/1, Non-Fatal/Fatal Error +;;;;; ;Bit7-1.....Reserved for future use + ;<(amiahcix-) +;------------------------------------------------------------------------- +; Device parameter table: Same to hdparam.equ +DEV_PARAM_STRUC struc + wMAXCYL dw ? ; maximum no. of cylinders..INT13 interface. (logical) + bMAXHN db ? ; maximum no. of heads..INT13 interface. (logical) + bLBASIG db ? ; LBA signature + bLBASPT db ? ; #of sectors per track drive is configured for. (physical) + wWPCYL dw ? ; start write precomp cyl no. + bReserved db ? ; reserved + bCBYTE db ? ; bit 3 for more than 8 heads + wLBACYL dw ? ; #of cylinders drive is configured for. (physical) + bLBAHD db ? ; #of heads drive is configured for. (physical) + wLANDZ dw ? ; Landing zone + bMAXSN db ? ; no. of sectors per track..INT13 interface. (logical) + bLBACHK db ? ; checksum..LBA +DEV_PARAM_STRUC ends + +; Details of bSignature field: A signature Axh indicates that the table is translated. +DPTBL_SIG_MASK equ 0F0h +lba_signature equ 0A0h ;A0h signature indicating LBA translation + +;------------------------------------------------------------------------- +; Return codes from INT13 +R_SUCCESS EQU 00h ;No error (i.e. Successful) +R_INVALID EQU 01h ;Invalid function request +R_MARK_NOT_FOUND EQU 02h ;Address mark not found +R_WRITE_PROTECT_ERR EQU 03h ;Write protect error +R_SECTOR_NOT_FOUND EQU 04h ;Sector not found +R_RESET_FAIL EQU 05h ;Reset failed +R_MEDIA_CHANGED EQU 06h ;Media changed +R_DRV_PARAM_ACT_FAIL EQU 07h ;Drive parameter activity failed +R_DMA_OVERRUN EQU 08h ;DMA overrun on operation +R_DATA_BOUNDARY_ERR EQU 09h ;Data boundary error +R_BAD_SECTOR EQU 0Ah ;Bad sector flag detected +R_BAD_CYL EQU 0Bh ;Bad cylinder detected +R_INVALID_NUM_OF_SECTOR EQU 0Dh ;Invalid #of sectors on format +R_CTRL_DATA_ADDR_MARK EQU 0Eh ;Control data address mark detected +R_DMA_ARBIT_LEVEL EQU 0Fh ;DMA arbitration level out of range +R_UNCORRECTABLE_ERR EQU 10h ;Uncorrectable ECC/CRC error +R_CORRECTED_DATA_ERR EQU 11h ;ECC corrected data error +R_GENERAL_CTRLER_FAIL EQU 20h ;General controller failure +R_SEEK_FAIL EQU 40h ;Seek operation failed +R_TIME_OUT EQU 80h ;Time out +R_DRV_NOT_READY EQU 0AAh ;Drive not ready +R_UNDEFINED_ERR EQU 0BBh ;Undefined error occurred +R_WRITE_FAULT EQU 0CCh ;Write fault on selected drive +R_STATUS_ERR EQU 0E0h ;Error Register = 0 +R_SENSE_FAIL EQU 0FFh ;Sense Operation failed + +;---------------------------------------------------------------------------- +; Timeout for different operations +SEC_TIMES EQU 00h ;Count for 1sec using refresh signal +MAX_TIMES EQU 05h ;Max time out in seconds + +;---------------------------------------------------------------------------- +IDENTIFY_BUFFER_LENGTH EQU 200h ;512 bytes for Identify device command +SECTOR_LENGTH EQU 200h ;512 bytes sector size +SECTOR_LENGTH_N EQU 9 ;2^n bytes sector size +SELECTOR_NON_LBA EQU 0A0h ;Master without LBA +SELECTOR_LBA EQU 0E0h ;Master with LBA +MAX_STND_XFER_SECTOR EQU 080h ;#of sectors that can be xferred in stnd INT13 func +MAX_EXTD_XFER_SECTOR EQU 07Fh ;#of sectors that can be xferred in extd INT13 func +BLOCK_SIZE EQU 800h ;#of bytes of each transefer from CDROM +BLOCK_SIZE_N EQU 00Bh ;N, block size 2^N + +;------------------------------------------------------------------------- +; Different data area relevant to Hard Disk in BIOS DATA SEGMENT (0040h) +;WINCH_STATUS EQU 74h ;40:74h = DB..Last operation status +;WINCH_NUMBER EQU 75h ;40:75h = DB..#of HDD installed by BIOS +;WINCH_STAT_REG EQU 8Ch ;40:8Ch = DB..Content of status register +;WINCH_ERROR_REG EQU 8Dh ;40:8Dh = DB..Content of error register +;WINCH_INT_FLAG EQU 8Eh ;40:8Eh = DB..Used for interrupt occurrence + +;------------------------------------------------------------------------- +; ATA/ATAPI commands +DEVICE_DIAG_CMD EQU 090h ;Execute device diagnostics command +IDENTIFY_DEVICE_COMMAND EQU 0ECh +ATAPI_IDENTIFY_DEV_CMD EQU 0A1h ;ATAPI identify device command +ATAPI_SIGNATURE EQU 0EB14h ;ATAPI Signature +MULTIPLIER_SIGNATURE EQU 9669h ;Port Multiplier Signature +ATA_SIGNATURE EQU 0000h ;ATA Signature +IDLE_IMMEDIATE EQU 0E2h ;IDLE IMMEDIATE Non-data + +READ_DMA_CMD EQU 0C8h ;Read DMA command +READ_DMA_EXT_CMD EQU 025h ;Read DMA Ext command +READ_MULTIPLE_CMD EQU 0C4h ;Read Multiple command +READ_MULTIPLE_EXT_CMD EQU 029h ;Read Multiple Ext command +READ_SECTORS_CMD EQU 020h ;Read Sector(s) command +READ_EXT_CMD EQU 024h ;Read Sector(s) Ext command + +WRITE_DMA_CMD EQU 0CAh ;Write DMA command +WRITE_DMA_EXT_CMD EQU 035h ;Write DMA Ext command +WRITE_MULTIPLE_CMD EQU 0C5h ;Write Multiple command +WRITE_MULTIPLE_EXT_CMD EQU 039h ;Write Multiple Ext command +WRITE_SECTORS_CMD EQU 030h ;Write Sector(s) command +WRITE_EXT_CMD EQU 034h ;Write Sector(s) Ext command + +READ_VERIFY_CMD EQU 040h ;Verify Sector(s) command +EXTD_READ_VERIFY_CMD EQU 042h ;Verify Sector(s) Ext command + +SET_MULTIPLE_CMD EQU 0C6h ;Set multiple mode command + +ATAPI_RESET_COMMAND EQU 008h ;ATAPI reset command + +SMART_COMMAND EQU 0B0h ;SMART Enable Operations command + SMART_READ_DATA EQU 0D0h + SMART_ATTRIBUTE_AUTOSAVE EQU 0D2h + SMART_SAVE_ATTRIBUTE_VALUES EQU 0D3h + SMART_EXECUTE_OFFLINE_IMMEDIATE EQU 0D4h + SMART_READ_LOG EQU 0D5h + SMART_WRITE_LOG EQU 0D6h +; SMART_ENABLE EQU 0D8h + SMART_DISABLE EQU 0D9h + SMART_RETURN_STATUS EQU 0DAh +;AHCI_HDS --> +SECURITY_SET_CMD equ 0F1h +SECURITY_UNLOCK_CMD equ 0F2h +SECURITY_DISABLE_CMD equ 0F6h +;AHCI_HDS <-- + +SECURITY_FREEZE_LOCK EQU 0F5h + +ATAPI_SOFT_PACKET_CMD EQU 0A0h ;ATAPI command packet value +; Available Packet commands +ATAPI_READ_10_CMD EQU 028h ;ATAPI read command packet value +ATAPI_REQUEST_SENSE_CMD EQU 03h ;ATAPI Request sense +ATAPI_NOP_CMD EQU 00h ;ATAPI Request sense +; Size of "Request Sense Packet" buffer +ATAPI_REQ_SENSE_DATA_SIZE EQU 18 ;ATAPI controller request sense data + +;------------------------------------------------------------------------- +; Input packet structure used in Extended INT13 functions +DISK_ADDRESS_PACKET_STRUC struc + bSize db ? ; Packet size in bytes + bReserved1 db ? ; Reserved (set to 0) + bBlockCount db ? ; #of blocks to be transferred + bReserved2 db ? ; Reserved (set to 0) + dPtrXferBuffer dd ? ; Segment:Offset of transfer buffer + qLBA dq ? ; Selected LBA +DISK_ADDRESS_PACKET_STRUC ends + +DISK_ADDRESS_PACKET_SIZE equ size DISK_ADDRESS_PACKET_STRUC + +; Details of bSize +; It contains size of the packet in bytes including this field. The size is +; 16bytes. If size is less than 16bytes, the function should return error +; with AH = 01h, and CF = 1. If packet size is greater than 16bytes, the +; function ignores the additional information and executes. +; +; Details of bXferCount +; On input, it contains #of sectors to be transferred. On output, it returns +; #of sectors actually transferred. If the input value is 0, the function +; returns successful without any data being transferred. +; +; Details dPtrXferBuffer +; It contains address of the data xfer buffer in segment:offset format. +; +; Details qStartLba +; It contains the absolute LBA of the device. The value can be from 0 to +; (total #of sectors - 1). +;------------------------------------------------------------------------- +; Result Buffer in INT13 Function 48h +;ExtI13DriveInfo STRUC +; wBufferSize DW ? ;Input buffer size in bytes +; wInfoFlags DW ? ;Information flags +; dNumCyls DD ? ;#of cylinders (1-based) +; dNumHeads DD ? ;#of heads (1-based) +; dNumSecs DD ? ;#of sectors per track (1-based) +; qTotalSecs DQ ? ;#of sectors on disk (1-based) +; wSectorSize DW ? ;Sector size in bytes +; pExtTable DD ? ;Ptr to extd parameter table +; wDevPathID DW ? ;Key for Device Path Extension +; bDevPathLength DB ? ;Device path info length (including key) in bytes +; bReserved DB ? ;Reserved (set to 00h) +; wReserved DW ? ;Reserved (set to 0000h) +; dHostBus DD ? ;Host Bus Type in ASCII +; aInterfaceType DB 8 DUP (?) ;Interface Type in ASCII +; aInterfacePath DB 8 DUP (?) ;Interface Path +; aDevPath DB 8 DUP (?) ;Device Path +; bReserved1 DB ? ;Reserved (set to 00h) +; bDevPathChksum DB ? ;Checksum of device path info including wKey field +;ExtI13DriveInfo ENDS + +; Details of wSize field +; It contains the maximum size of the supplied buffer in bytes. +; If buffer size < 1E, function does not return dPtrDpte field. +; If buffer size >= 1E, it should be set to 1E on exit. +; If 1A <= buffer size <= 1D, it should be set to 1A on exit. +; If buffer size < 1A, function returns error. +; Details of wInfoFlag field +; Bit-0 = 1, DMA boundary errors handled transparently +; Bit-1 = 1, Device geometry (in dCylinder, dHead, dSpt fields) is valid +; Bit-2 = 1, Removable Media (Bit6-4 are NOT valid if this Bit-2 = 0) +; Bit-3 = 1, Device supports write with verify on +; Bit-4 = 1, Device supports media change notification +; Bit-5 = 1, Media can be locked +; Bit-6 = 1, Device geometry is set to maximum and no media is present when +; this Bit-6 is set to 1 +; Bit-7 = 1, INT13 Function 50h supported +; Bit15-8....Reserved +; Details of dCylinder field +; It contains physical #of cylinders (1-based). INT13 Function 08h returns +; logical #of cylinders. +; Details of dHead field +; It contains physical #of heads (1-based). INT13 Function 08h returns +; logical #of heads. +; Details of dSpt field +; It contains physical #of sectors/track (1-based). INT13 Function 08h returns +; logical #of sectors/track. +; Details of qTotalSector field +; It contains the total #of sectors (1-based) in the device. If total #of +; sectors > 15482880 (decimal), then bit-1 of wInfoFlag should be set to 0 +; indicating device geometry is not valid. +; Details dPtrDpte field +; This field is present only when INT13 Function 41h returns a 1 in bit-2 of +; output CX. +; Details of wKey field +; It contains BEDDh signature indicating presence of device path information. +; Details of bDevicePathInfoLength +; It contains the length of device path information. The length includes the +; wKey field. +; Details of bHostBusType field +; It contains ASCII string identifying Host Bus. +; 'PCI ' PCI Local Bus 50 43 49 20 +; 'ISA ' Legacy 16bit fixed bus 49 53 41 20 +; 'PCIX' PCI-X Bus 50 43 49 58 +; 'XPRS' PCI Express 58 50 52 53 +; Details of bInterfaceType field +; It contains ASCII string identifying Interface +; 'ATA ' Device using ATA command 41 54 41 20 20 20 20 20 +; 'ATAPI ' Device using ATAPI commands 41 54 41 50 49 20 20 20 +; 'USB ' USB Mass Storage device 55 53 42 20 20 20 20 20 +; 'SATA ' Serial ATA 53 41 54 41 20 20 20 20 +; Details of qInterfacePath field (offset 30h to 37h) +; The content depends on Host Bus Type (bHostBusType field) +; Host Bus Offset Type Content +; ISA 30h Word 16bit base address +; 32h Word Should be 0000h +; 34h Dword Should be 00000000h +; PCI 30h Byte PCI Bus Number +; 31h Byte PCI Slot Number +; 32h Byte PCI Function Number +; 33h Byte Channel Number (FF if not used) +; 34h Dword Should be 00000000h +; Details of bDevicePath field (offset 38h to 47h) +; The content depends on Interface Type (bInterfaceType field) +; Interface Offset Type Content +; SATA 38h Byte SATA Port# (0-based) +; 39h-57h 15byte Set to 0 +; Details of bChecksum field (offset 49h) +; It contains the checksum of device path information including wKey field. +; The byte addition of all bytes in device path information including the +; checksum (offset 1Eh-49h) is 00. +;------------------------------------------------------------------------- +; Extra Functions that are called using interface similar to INT13 +API_DEV_RESET_FUNC equ 00h ; Reset Device +API_PORT_RESET_FUNC equ 01h ; Reset Port +API_DEVICE_ID_FUNC equ 02h ; Identify device data +API_ATAPI_READ_FUNC equ 03h ; Read ATAPI device +API_SMART_ENABLE_FUNC equ 04h ; Enable SMART feature +API_SMART_PROMPT_FUNC equ 05h ; Prop SMART events for errors +API_FREEZE_LOCK_FUNC equ 06h +API_SMART_DISABLE_FUNC equ 07h ;Disable SMART feature ;(EIP9252+) + ;(EIP9321+)>>> Add SMART Function +API_RETURN_SMART_STATUS_FUNC equ 08h ;Return SMART status +API_SMART_READ_DATA_FUNC equ 09h ;Read SMART Data +API_SMART_SHORT_SELFTEST_FUNC equ 0Ah ;SMART Execute Off-Line Immediate +API_SMART_EXTENDED_SELFTEST_FUNC equ 0Bh ;SMART Execute Off-Line Immediate + ;<<<(EIP9321+) + +;------------------------------------------------------------------------- +; Runtime Attribute: bit-mapped information +A_EBDA_USED equ 01h ; Bit-0 = 1, Use EBDA memory for CLCTFIS area + ; Bit-1...Reserved for internal use + ; Bit7-2..Reserved for future use + +;------------------------------------------------------------------------- +; Equates and structures of Virtual DMA Services (VDS) +;------------------------------------------------------------------------- +; DDS (DMA Descriptor structure): Used to Lock/Unlock DMA region. The fields +; namely, dRegionSize, dRegionOffset, wRegionSegment need to be +; initialized with proper values before calling Lock function. The Lock +; function fills wBufferId and dRegionPhysicalAddress fields. The same +; DDS, as returned by Lock function, needs to be used while calling +; UnLock function. +DDS_STRUC struc + dRegionSize dd ? ; Region Size in bytes (filled by caller) + dRegionOffset dd ? ; Region Offset (filled by caller) + wRegionSegment dw ? ; Region Segment (filled by caller) + wBufferId dw ? ; Buffer ID (filled by VDS function) + dRegionPhysicalAddress dd ? ; Physical address of region (filled by VDS function) +DDS_STRUC ends + +; EDDS (Extended DMA Descriptor structure): EDDS contains EDDS Header followed +; by one or more EDDS entry. The maximum #of entries that EDDS can +; accommodate is limited by the space available for EDDS. In this +; implementation, space for maximum 16 entries are available in EDDS. +MAX_NO_OF_EDDS_ENTRY equ 16 ; Max #of entries EDDS can accommodate + +EDDS_HEADER_STRUC struc + dRegionSize dd ? ; Region Size in bytes (filled by caller) + dRegionOffset dd ? ; Region Offset (filled by caller) + wRegionSegment dw ? ; Region Segment (filled by caller) + wReserved dw ? ; Reserved (filled by caller) + wNoOfAvailableEntry dw ? ; #of entries available in EDDS (filled by caller) + wNoOfUsedEntry dw ? ; #of entries used in EDDS (filled by VDS function) +EDDS_HEADER_STRUC ends + +EDDS_ENTRY_STRUC struc + dRegionPhysicalAddress dd ? ; Physical address of region (filled by VDS function) + dRegionSize dd ? ; Region size in bytes (filled by VDS function) +EDDS_ENTRY_STRUC ends + +;------------------------------------------------------------------------- +; EQUATES FOR COMMAND LIST, COMMAND TABLE, FIS, DDS, EDDS +; CLCTFIS area is in EBDA, both DDS and EDDS are in EBDA. +;------------------------------------------------------------------------- +SIZE_CMD_LIST equ 1024 ; 1kbytes for command list +SIZE_FIS equ 0256 ; 256bytes for FIS +SIZE_CMD_TABLE equ 0384 ; 384bytes for command table +; +SIZE_DDS equ size DDS_STRUC ; 16bytes for DDS +SIZE_EDDS equ size EDDS_HEADER_STRUC + \ + (MAX_NO_OF_EDDS_ENTRY * (size EDDS_ENTRY_STRUC)); 272bytes for EDDS + +SIZE_ALIGN_BUFFER equ BLOCK_SIZE+2 ;(v1.07) + +SIZE_CLCTFIS_AREA_K equ 4 ; CLCTFIS area in unit of 1k in system memory/EBDA +SIZE_CLCTFIS_AREA_B equ SIZE_CLCTFIS_AREA_K*1024 ; CLCTFIS area in bytes in system memory/EBDA + +; Equates for start offset of different areas +; Command List at offset 0000h, FIS at offset 0400h, Command Table at +; offset 0500h. +START_CMD_LIST equ 0000h ; Command List must be 1kbyte aligned +START_FIS equ START_CMD_LIST+SIZE_CMD_LIST ; FIS must be 256byte aligned +START_CMD_TABLE equ START_FIS+SIZE_FIS ; Command table must be 128byte aligned +START_DDS equ START_CMD_TABLE+SIZE_CMD_TABLE ; Start of DDS +START_EDDS equ START_DDS+SIZE_DDS ; Start of EDDS +START_ALIGN_BUFFER equ START_EDDS+SIZE_EDDS ; Start of DMA Alignment Buffer +START_LOCAL_BUFFER equ START_ALIGN_BUFFER+SIZE_ALIGN_BUFFER ; Start of Local Buffer(v1.07) + +;------------------------------------------------------------------------- +; INT13 FUNCTION TABLE STRUCTURE +;------------------------------------------------------------------------- +AI13_FUNC_STRUC struc + bFuncNum db ? ; Function# + wFuncProc dw ? ; Offset of Execution routine +AI13_FUNC_STRUC ends + +;------------------------------------------------------------------------- +; EQUATES OF DIFFERENT PARAMETERS IN STACK +;------------------------------------------------------------------------- +; +; Stack equates for PUSH GS/PUSH FS/PUSH ES/PUSH DS/PUSHAD +; after allocating N bytes in stack +; +; GS, FS, ES, DS positions in stack PUSH GS +; PUSH FS +; PUSH ES +; PUSH DS +; PUSHAD +; sub sp, SIZE_AHCI_INT13_MISC_STACK +; +TASKF_STRUC STRUC + CmdListBase dd ? ;32bit Command List base address + CmdTableBase dd ? ;32bit Command Table base address + FisRecBase dd ? ;32bit FIS Receive base address + HbaBase dd ? ;32bit HBA Base address + CmdListPtr dd ? ;Ptr (Seg:Off) to Command List + CmdTablePtr dd ? ;Ptr (Seg:Off) to Command Table + FisRecPtr dd ? ;Ptr (Seg:Off) to FIS Receive + DdsPtr dd ? ;Ptr (Seg:off) to DDS + EddsPtr dd ? ;Ptr (Seg:off) to EDDS + DevInfoTablePtr dd ? ;Ptr (Seg:off) to Device Info Table + PortNum db ? ;Port# (0-based) on Controller + bControllerNo db ? + Selector db ? ;Device Selector + InfoFlag db ? ;Device Info Flag + RequestedSectorCount db ? ;#of sector(s) access requested + AccessedSectorCount db ? ;#of sector(s) actually accessed + CmdSlotMask db ? ;Bit-mask of slot(s) used in command list + CmdSlotNum db ? ;Slot# (0-based) used in command list + Attribute db ? ;Bit-mapped attribute of misc information + Port21 db ? ;Content of Port21 + PortA1 db ? ;Content of PortA1 + ReservedDD1 dd ? ;Reserved + ReservedDD2 dd ? ;Reserved + ModUserBufferOfs dw ? ;Offset of modified user buffer + ModUserBufferSeg dw ? ;Segment of modified user buffer + ModUserBufferSize dw ? ;Size in Dwords (1-based) of modified user buffer + OrgUserBufferOfs dw ? ;Original segment of user buffer, to overcome unaligned user buffer + OrgUserBufferSeg dw ? ;Original Offset of user buffer, to overcome unaligned user buffer + AlignBufferOfs dw ? ;Offset to Alignment buffer, to be used for temp DMA alignment buffer + AlignBufferSeg dw ? ;Segment to Alignment buffer, to be used for temp DMA alignment buffer +TASKF_STRUC ENDS + +PUSHAD_STRUC STRUC + + StackFS dw ? + StackDS dw ? + StackES dw ? + StackGS dw ? + + StackEDI dd ? + StackESI dd ? + StackEBP dd ? + StackESP dd ? + StackEBX dd ? + StackEDX dd ? + StackECX dd ? + StackEAX dd ? + +PUSHAD_STRUC ENDS + +;SIZE_AHCI_INT13_MISC_STACK equ AI13_STACK_BUFFER_STRUC.StackEDI ; EDI is the last in PUSHAD + + +S_AHCI_STACK struc +TaskFile TASKF_STRUC <> +Stack PUSHAD_STRUC <> +S_AHCI_STACK ends + + ;(amiahcix+)> +;---------------------------------------------------------------------------- +; AHCI error equates +;---------------------------------------------------------------------------- + +; 000h-03Fh : CIDs for CORE compnents. +; Used for stBIOSError.wErrorCode[15:8] +CID_AHCI EQU 004h + +;---------------------------------------; +; AHCI_x_ERR +;---------------------------------------; +EQU_AHCI_ERR macro COUNT + AHCI_&COUNT&_ERR EQU (CID_AHCI SHL 8) + COUNT +endm + +AHCI_ACCESS STRUCT + Index dw ? + Data dw ? + BaseAddress dd ? +AHCI_ACCESS ENDS + +; builds 64 AHCI_x_ERR: + +; AHCI_0_ERR EQU (CID_AHCI SHL 8) + 0 +; AHCI_1_ERR EQU (CID_AHCI SHL 8) + 1 +; AHCI_2_ERR EQU (CID_AHCI SHL 8) + 2 +; AHCI_3_ERR EQU (CID_AHCI SHL 8) + 3 +; . +; . +ATA_COUNT = 0 ; starts from AHCI_0_err +REPEAT 64 ; Max 64 AHCI errors + EQU_AHCI_ERR %ATA_COUNT + ATA_COUNT = ATA_COUNT+1 +ENDM +;---------------------------------------; + ;<(amiahcix+) + + +;------------------------------------------------------------------------- +;**************************************************************************** +;**************************************************************************** +;** ** +;** (C)Copyright 1985-2011, American Megatrends, Inc. ** +;** ** +;** All Rights Reserved. ** +;** ** +;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +;** ** +;** Phone (770)-246-8600 ** +;** ** +;**************************************************************************** +;**************************************************************************** diff --git a/Chipset/eM/Ahci/AInt13Csp.c b/Chipset/eM/Ahci/AInt13Csp.c new file mode 100644 index 0000000..44365ba --- /dev/null +++ b/Chipset/eM/Ahci/AInt13Csp.c @@ -0,0 +1,111 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//**************************************************************************** +// $Header: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AInt13Csp.c 3 2/10/11 10:52a Rameshr $ +// +// $Revision: 3 $ +// +// $Date: 2/10/11 10:52a $ +// +//**************************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AInt13Csp.c $ +// +// 3 2/10/11 10:52a Rameshr +// [TAG] EIP53704 +// [Category] Improvement +// [Description] AMI headers update for Alaska Ahci Driver +// [Files] AHCIACC.ASM +// HACCESS.EQU +// AHCI.EQU +// AINT13.EQU +// AInt13Csp.c +// +// 2 5/28/08 9:44a Rameshraju +// Updated the AMI Address. +// +// 1 12/07/07 11:17a Olegi +// +//**************************************************************************** + +//<AMI_FHDR_START> +//---------------------------------------------------------------------------- +// +// Name: AINT13CSP.C +// Description: AHCI INT13 Support Chipset Configuration File +// +//---------------------------------------------------------------------------- +//<AMI_FHDR_END> + +#define LBAR_REGISTER 0x20 +#define LBAR_ADDRESS_MASK 0xFFFFFFE0 +#define INDEX_OFFSET_FROM_LBAR 0x10 +#define DATA_OFFSET_FROM_LBAR 0x14 + +#include "AmiDxeLib.h" +#include "Protocol\PciIo.h" + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Name: GetAccessInfo +// +// Description: This is chipset porting routine that returns index/data ports +// to access memory-mapped registers. +// +// Input: PciIo +// +// Output: EFI_SUCCESS - Access information is collected +// EFI_ACCESS_DENIED - No Access information avaliable +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +GetAccessInfo ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + OUT UINT16 *AccessIndexPort, + OUT UINT16 *AccessDataPort +) +{ + EFI_STATUS Status; + UINT32 lbar; + + Status = PciIo->Pci.Read(PciIo, EfiPciIoWidthUint32, LBAR_REGISTER, 1, &lbar); + ASSERT_EFI_ERROR(Status); + + lbar &= LBAR_ADDRESS_MASK; // Legacy Bus Master Base Address + + *AccessIndexPort = (UINT16)lbar + INDEX_OFFSET_FROM_LBAR; + *AccessDataPort = (UINT16)lbar + DATA_OFFSET_FROM_LBAR; + + return EFI_SUCCESS; + +} + + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Chipset/eM/Ahci/AhciAccess.c b/Chipset/eM/Ahci/AhciAccess.c new file mode 100644 index 0000000..36ea264 --- /dev/null +++ b/Chipset/eM/Ahci/AhciAccess.c @@ -0,0 +1,252 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/AHCI/AhciAccess.c 3 2/11/11 4:09a Rameshr $ +// +// $Revision: 3 $ +// +// $Date: 2/11/11 4:09a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/AHCI/AhciAccess.c $ +// +// 3 2/11/11 4:09a Rameshr +// [TAG] EIP53704 +// [Category] Improvement +// [Description] AMI headers update for Alaska Ahci Driver +// [Files] AhciAccess.c +// +// 2 5/07/10 11:51a Krishnakumarg +// Update for coding standard. +// +// 1 5/28/08 9:49a Rameshraju +// Initial Check-in for Index/Data access method. +// +//********************************************************************** +//<AMI_FHDR_START> +// +// Name: AhciAccess.c +// +// Description: Provides Index Data Port Access to AHCI Controller +// +//<AMI_FHDR_END> +//********************************************************************** +//#include <AmiDxeLib.h> + +#define LBAR_REGISTER 0x20 +#define LBAR_ADDRESS_MASK 0xFFFFFFE0 +#define INDEX_OFFSET_FROM_LBAR 0x10 +#define DATA_OFFSET_FROM_LBAR 0x14 + +#include "AmiDxeLib.h" +#include "Protocol\PciIo.h" + +UINT16 IndexPort, DataPort; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Name: InitilizeIndexDataPortAddress +// +// Description: This is chipset porting routine that returns index/data ports +// to access memory-mapped registers. +// +// Input: PciIo +// +// Output: EFI_SUCCESS - Access information is collected +// EFI_ACCESS_DENIED - No Access information avaliable +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +InitilizeIndexDataPortAddress ( + IN EFI_PCI_IO_PROTOCOL *PciIo +) +{ + EFI_STATUS Status; + UINT32 lbar; + + Status = PciIo->Pci.Read(PciIo, EfiPciIoWidthUint32, LBAR_REGISTER, 1, &lbar); + ASSERT_EFI_ERROR(Status); + + lbar &= LBAR_ADDRESS_MASK; // Legacy Bus Master Base Address + + IndexPort = (UINT16)lbar + INDEX_OFFSET_FROM_LBAR; + DataPort = (UINT16)lbar + DATA_OFFSET_FROM_LBAR; + + return EFI_SUCCESS; + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Name: ReadDataDword +// +// Description: Read the Dword Data using Index/Data access method +// +// Input: BaseAddress - BaseAddress of AHCI Controller +// Index - Index address to read +// +// Output: Value Read +// +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT32 +ReadDataDword( + IN UINTN BaseAddr, + IN UINTN Index +) +{ + IoWrite32(IndexPort, (UINT32)Index); + return IoRead32(DataPort); +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Name: WriteDataDword +// +// Description: WriteRead the Dword Data using Index/Data access method +// +// Input: BaseAddress - BaseAddress of AHCI Controller +// Index - Index address to Write +// Data - Data to be written +// +// Output: Nothing +// +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +WriteDataDword( + IN UINTN BaseAddr, + IN UINTN Index, + IN UINTN Data +) +{ + IoWrite32(IndexPort, (UINT32)Index); + IoWrite32(DataPort, (UINT32)Data); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Name: ReadDataDword +// +// Description: Read the Word Data using Index/Data access method +// +// Input: BaseAddress - BaseAddress of AHCI Controller +// Index - Index address to read +// +// Output: Value Read +// +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT16 +ReadDataWord( + IN UINTN BaseAddr, + IN UINTN Index +) +{ + IoWrite32(IndexPort, (UINT32)Index); + return (UINT16)IoRead32(DataPort); +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Name: WriteDataDword +// +// Description: WriteRead the word Data using Index/Data access method +// +// Input: BaseAddress - BaseAddress of AHCI Controller +// Index - Index address to Write +// Data - Data to be written +// +// Output: Nothing +// +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +WriteDataWord( + IN UINTN BaseAddr, + IN UINTN Index, + IN UINTN Data +) +{ + IoWrite32(IndexPort, (UINT32)Index); + IoWrite32(DataPort, (UINT16)Data); +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Name: ReadDataDword +// +// Description: Read the Byte Data using Index/Data access method +// +// Input: BaseAddress - BaseAddress of AHCI Controller +// Index - Index address to read +// +// Output: Value Read +// +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8 +ReadDataByte( + IN UINTN BaseAddr, + IN UINTN Index +) +{ + IoWrite32(IndexPort, (UINT32)Index); + return (UINT8)IoRead32(DataPort); +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Name: WriteDataByte +// +// Description: WriteRead the Dword Data using Index/Data access method +// +// Input: BaseAddress - BaseAddress of AHCI Controller +// Index - Index address to Write +// Data - Data to be written +// +// Output: Nothing +// +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +WriteDataByte( + IN UINTN BaseAddr, + IN UINTN Index, + IN UINTN Data +) +{ + IoWrite32(IndexPort, (UINT32)Index); + IoWrite8(DataPort, (UINT8)Data); +} + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//**********************************************************************
\ No newline at end of file diff --git a/Chipset/eM/Ahci/AhciAccess.cif b/Chipset/eM/Ahci/AhciAccess.cif new file mode 100644 index 0000000..d5a2046 --- /dev/null +++ b/Chipset/eM/Ahci/AhciAccess.cif @@ -0,0 +1,8 @@ +<component> + name = "AHCI CSP-Template" + category = ModulePart + LocalRoot = "Chipset\eM\Ahci" + RefName = "ACSP" +[files] +"AhciAccess.c" +<endComponent> diff --git a/Chipset/eM/Ahci/AhciCsp.cif b/Chipset/eM/Ahci/AhciCsp.cif new file mode 100644 index 0000000..1c12363 --- /dev/null +++ b/Chipset/eM/Ahci/AhciCsp.cif @@ -0,0 +1,12 @@ +<component> + name = "AHCI Int13 CSP-Template" + category = ModulePart + LocalRoot = "Chipset\eM\Ahci" + RefName = "AHCI_INT13_CSP" +[files] +"AHCIACC.ASM" +"HACCESS.EQU" +"AHCI.EQU" +"AINT13.EQU" +"AInt13Csp.c" +<endComponent> diff --git a/Chipset/eM/Ahci/HACCESS.EQU b/Chipset/eM/Ahci/HACCESS.EQU new file mode 100644 index 0000000..53c2292 --- /dev/null +++ b/Chipset/eM/Ahci/HACCESS.EQU @@ -0,0 +1,108 @@ +; TITLE HACCESS.EQU - Accessing HBA memory-mapped register +;**************************************************************************** +;**************************************************************************** +;** ** +;** (C)Copyright 1985-2011, American Megatrends, Inc. ** +;** ** +;** All Rights Reserved. ** +;** ** +;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +;** ** +;** Phone (770)-246-8600 ** +;** ** +;**************************************************************************** +;**************************************************************************** + +;**************************************************************************** +; $Header: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/HACCESS.EQU 3 2/10/11 10:52a Rameshr $ +; +; $Revision: 3 $ +; +; $Date: 2/10/11 10:52a $ +; +;**************************************************************************** +; Revision History +; ---------------- +; $Log: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/HACCESS.EQU $ +; +; 3 2/10/11 10:52a Rameshr +; [TAG] EIP53704 +; [Category] Improvement +; [Description] AMI headers update for Alaska Ahci Driver +; [Files] AHCIACC.ASM +; HACCESS.EQU +; AHCI.EQU +; AINT13.EQU +; AInt13Csp.c +; +; 2 5/28/08 9:43a Rameshraju +; Updated the AMI Address. +; +; 1 12/07/07 11:17a Olegi +; +; 4 12/05/06 3:16a Iminglin +; Remove useless. +; +; 3 11/29/06 3:18a Iminglin +; CSP modification. +; +; 2 11/23/06 10:12p Iminglin +; Default is for ICH7. +; +; 1 6/09/05 11:29p Iminglin +; Initialized version +; +; 1 5/20/05 2:37a Iminglin +; Intel AHCI source +; +;**************************************************************************** + +;------------------------------------------------------------------------- +; +; Input parameter in register CH to read/write memory-mapped registers. +; +;ACCESS_DATA equ 0ADh +; +; Output parameter in register CH from read/write memory-mapped registers. +; This data is checked for determining whether access is successful. +; +;DATA_ACCESSED equ 0DAh ; Access is Successful + ; Any other value -> error +; +;------------------------------------------------------------------------- +; Function number used for common control routine to access memory-mapped +; registers using any access method +; +;READ_BYTE equ 00h ; Func# 00h for Read Byte Data +;READ_WORD equ 01h ; Func# 01h for Read Word Data +;READ_DWORD equ 02h ; Func# 02h for Read Dword Data +; +;WRITE_BYTE equ 10h ; Func# 10h for Write Byte Data +;WRITE_WORD equ 11h ; Func# 11h for Write Word Data +;WRITE_DWORD equ 12h ; Func# 12h for Write Dword Data +; +;INIT_BYTE_ARRAY equ 20h ; Func# 20h for Init Byte Array +;INIT_WORD_ARRAY equ 21h ; Func# 21h for Init Word Array +;INIT_DWORD_ARRAY equ 22h ; Func# 22h for Init Dword Array +; +;------------------------------------------------------------------------- +; +;RW_FUNC_STRUC struc +; bFunction db ? ; Function# +; wPtrToRoutine dw ? ; Offset of execution routine +;RW_FUNC_STRUC ends +;------------------------------------------------------------------------- +;**************************************************************************** +;**************************************************************************** +;** ** +;** (C)Copyright 1985-2011, American Megatrends, Inc. ** +;** ** +;** All Rights Reserved. ** +;** ** +;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +;** ** +;** Phone (770)-246-8600 ** +;** ** +;**************************************************************************** +;**************************************************************************** + diff --git a/Chipset/eM/ME/MEUD/CSP_MEUD.c b/Chipset/eM/ME/MEUD/CSP_MEUD.c new file mode 100644 index 0000000..2036dee --- /dev/null +++ b/Chipset/eM/ME/MEUD/CSP_MEUD.c @@ -0,0 +1,1196 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2009, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* +//************************************************************************* +// $Header: /Alaska/SOURCE/Modules/OFBD Intel ME Update/CSP_MEUD/ME80/CSP_MEUD.c 14 5/14/15 4:33a Tristinchou $ +// +// $Revision: 14 $ +// +// $Date: 5/14/15 4:33a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/OFBD Intel ME Update/CSP_MEUD/ME80/CSP_MEUD.c $ +// +// 14 5/14/15 4:33a Tristinchou +// [TAG] EIP215437 +// [Category] New Feature +// [Description] ME capsule update support on SharkBay +// +// 13 3/05/14 2:51a Tristinchou +// [TAG] EIP147099 +// [Category] New Feature +// [Description] Support ME FWUpdate API +// +// 12 10/01/13 1:40a Klzhan +// [TAG] EIPNone +// [Category] Improvement +// [Description] backward compatible +// +// 11 9/30/13 6:05a Klzhan +// [TAG] EIPNone +// [Category] Improvement +// [Description] Support PI 1.2 +// +// 10 8/23/13 4:14a Tristinchou +// [TAG] EIPNone +// [Category] Improvement +// [Description] Fix build error with CrescentBay project. +// +// 9 5/16/13 6:24a Klzhan +// [TAG] EIPNone +// [Category] Improvement +// [Description] 1. Pre-allocate Memory while ME is disable(Avoid +// allocate memory error message). +// 2. Support PDR reiong is on top of SPI(AFU 3.05 and +// 4.6.3_Flash_Combined_2_36) +// +// 8 3/15/13 5:18a Klzhan +// [TAG] EIPNone +// [Category] Improvement +// [Description] Add new token BITS_OF_SPI_DENSITY +// [Files] CSP_MEUD.c +// CSP_MEUD.h +// CSP_MEUD.sdl +// CSP_MEUD.mak +// CSP_MEUD.cif +// +// 7 11/29/12 4:42a Klzhan +// BugFix : Can't update ME when 2 SPI installed. A token is added +// (Lynx Point spec updated, BIT define chaged). +// +// 6 11/29/12 2:24a Klzhan +// BugFix : Mac address restored to wrong address. +// +// 5 11/28/12 4:03a Klzhan +// Getting wrong Flash capacity when 2 flash component. +// +// 4 9/07/12 4:46a Klzhan +// Support ME 9. +// +// 1 12/12/11 2:38a Wesleychen +// Update to rev.2 for FD region length correction. +// +// 2 5/09/11 3:25a Klzhan +// Correct FD region length. +// +// 1 4/22/11 2:47a Klzhan +// Initial check - in +// +// +// +//********************************************************************** +//<AMI_FHDR_START> +// +// Name: CSP_MEUD.c +// +// Description: +// +//<AMI_FHDR_END> +//********************************************************************** +#include "Efi.h" +#include "token.h" +#include <AmiLib.h> +#include <AmiDxeLib.h> +#include <SB.h> +#include "CoreBiosMsg.h" +#include "ReferenceCode\ME\Protocol\Heci\Heci.h" +#include "MeChipset.h" +#include "PchRegs\PchRegsRcrb.h" +#include "CSP_MEUD.h" +#include <MEUD\MEUD.h> +#include "Flash.h" +#include "MEFwUpdLcl\MeFwUpdLclProtocol.h" + +#if defined SecSMIFlash_SUPPORT && SecSMIFlash_SUPPORT == 1 +#include <Protocol\SecSmiFlash.h> +#endif + +#if PI_SPECIFICATION_VERSION >= 0x1000A +#include <Protocol\SmmBase2.h> +#define RETURN(status) {return status;} + +extern EFI_GUID gEfiSmmBase2ProtocolGuid; +EFI_SMM_BASE2_PROTOCOL *gSmmBase2; +EFI_SMM_SYSTEM_TABLE2 *gSmst; +#endif +#if defined SecSMIFlash_SUPPORT && SecSMIFlash_SUPPORT == 1 +static EFI_GUID gEfiSecSmiFlashProtocolGuid = SEC_SMI_FLASH_GUID; +UINT32 *gFwCapsuleAddress = NULL; +#endif + +EFI_GUID gEfiHeciProtocolGuid = HECI_PROTOCOL_GUID; + +BOOLEAN IsIgnition; +BOOLEAN Is_SECOVR_JMPR; +BOOLEAN Is_MEFW; + +EFI_PHYSICAL_ADDRESS Phy_Address; +OFBD_TC_55_ME_PROCESS_STRUCT *StructPtr; +UINT8 MacAddr[6]; +UINT8 Nounce[8]; +UINT32 Factory_Base; +UINT32 Factory_Limit; +#ifdef _HECI_PROTOCOL_H +HECI_PROTOCOL *mHeci = NULL; +#else +EFI_HECI_PROTOCOL *mHeci = NULL; +#endif +EFI_PHYSICAL_ADDRESS RomBuffer = NULL; +EFI_PHYSICAL_ADDRESS BlockBuffer = NULL; + +EFI_GUID mMeFwUpdLclProtocolGuid = ME_FW_UPD_LOCAL_PROTOCOL_GUID; +ME_FW_UPDATE_LOCAL_PROTOCOL *mMeFwUpdateLocalProtocol = NULL; +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: GET_FW_VERSION +// +// Description: Get ME FW Version. +// +// Input: NONE +// +// Output: EFI_STATUS +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS GET_FW_VERSION( + IN UINT16 *MeFwVersionData +) +{ + EFI_STATUS Status; + UINT32 Length; + GEN_GET_FW_VER *MsgGenGetFwVersion; + GEN_GET_FW_VER GenGetFwVersion; + UINT32 MeMode; + GEN_GET_FW_VER_ACK MsgGenGetFwVersionAck; + + Status = mHeci->GetMeMode (&MeMode); + if (EFI_ERROR (Status) || (MeMode != ME_MODE_NORMAL)) { + return EFI_UNSUPPORTED; + } + + // + // Allocate MsgGenGetFwVersion data structure + // + MsgGenGetFwVersion = &GenGetFwVersion; + MsgGenGetFwVersion->MKHIHeader.Data = 0; + MsgGenGetFwVersion->MKHIHeader.Fields.GroupId = MKHI_GEN_GROUP_ID; + MsgGenGetFwVersion->MKHIHeader.Fields.Command = GEN_GET_FW_VERSION_CMD; + MsgGenGetFwVersion->MKHIHeader.Fields.IsResponse = 0; + Length = sizeof (GEN_GET_FW_VER); + // + // Send Get Firmware Version Request to ME + Status = mHeci->SendMsg ( + (UINT32 *) MsgGenGetFwVersion, + Length, + BIOS_FIXED_HOST_ADDR, + HECI_CORE_MESSAGE_ADDR + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Length = sizeof (GEN_GET_FW_VER_ACK); + Status = mHeci->ReadMsg ( + BLOCKING, + (UINT32 *) &MsgGenGetFwVersionAck, + &Length + ); + if (EFI_ERROR (Status)) { + return Status; + } + + MeFwVersionData[0] = MsgGenGetFwVersionAck.Data.CodeMajor; + MeFwVersionData[1] = MsgGenGetFwVersionAck.Data.CodeMinor; + MeFwVersionData[2] = MsgGenGetFwVersionAck.Data.CodeHotFix; + MeFwVersionData[3] = MsgGenGetFwVersionAck.Data.CodeBuildNo; + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: GetHFS +// +// Description: Get Host Firmware Status pass to MEUD +// +// Input: NONE +// +// Output: Host Firmware Status +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT32 GetHFS(VOID) +{ + UINT32 R_HFS; + EFI_STATUS Status; + if(mHeci == NULL) + { + R_HFS = 0; + return R_HFS; + } + Status = mHeci->GetMeStatus(&R_HFS); + if (EFI_ERROR (Status)) { + R_HFS = 0; + } + return R_HFS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: HMRFPO_ENABLE_MSG +// +// Description: Send Enable HECI message to enable Ignition Firmwate update. +// +// Input: NONE +// +// Output: NONE +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS HMRFPO_ENABLE_MSG(VOID) +{ + EFI_STATUS Status = EFI_SUCCESS; + MKHI_HMRFPO_ENABLE HmrfpoEnableRequest; + MKHI_HMRFPO_ENABLE_RESPONSE HmrfpoEnableResponse; + UINT32 HeciLength; + + // Function 1 and 4 will call this function, check is ME or Ignition. + if(Is_MEFW) + { + // If ME FW check GPIO33 assert or not + if(Is_SECOVR_JMPR) + return EFI_SUCCESS; + else + return EFI_UNSUPPORTED; + } + if(mHeci == NULL) + return EFI_NOT_READY; + + HmrfpoEnableRequest.MkhiHeader.Fields.GroupId = MKHI_SPI_GROUP_ID; + HmrfpoEnableRequest.MkhiHeader.Fields.Command = HMRFPO_ENABLE_CMD_ID; + HmrfpoEnableRequest.MkhiHeader.Fields.IsResponse = 1; + + MemSet( &HmrfpoEnableRequest.Nonce ,8,0); + + HeciLength = sizeof (MKHI_HMRFPO_ENABLE); + + Status = mHeci->SendMsg ( + (UINT32 *) &HmrfpoEnableRequest, + HeciLength, + BIOS_FIXED_HOST_ADDR, + HECI_CORE_MESSAGE_ADDR + ); + if (EFI_ERROR (Status)) { + IoWrite8(0x80, 0xA0); + return Status; + } + + HeciLength = sizeof (MKHI_HMRFPO_ENABLE_RESPONSE); + + Status = mHeci->ReadMsg ( + BLOCKING, + (UINT32 *) &HmrfpoEnableResponse, + &HeciLength + ); + if (EFI_ERROR (Status)) { + IoWrite8(0x80, 0xA1); + return Status; + } + + return Status; + +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: HMRFPO_LOCK_MSG +// +// Description: Send LOCK HECI message and lock ME. +// +// Input: NONE +// +// Output: NONE +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS HMRFPO_LOCK_MSG(VOID) +{ + EFI_STATUS Status; + MKHI_HMRFPO_LOCK HmrfpoLockRequest; + MKHI_HMRFPO_LOCK_RESPONSE HmrfpoLockResponse; + UINT32 HeciLength; + // Function 1 and 4 will call this function, check is ME or Ignition. + if(Is_MEFW) + { + // If ME FW check GPIO33 assert or not + if(Is_SECOVR_JMPR) + return EFI_SUCCESS; + else + return EFI_UNSUPPORTED; + } + if(mHeci == NULL) + return EFI_NOT_READY; + HmrfpoLockRequest.MkhiHeader.Fields.GroupId = MKHI_SPI_GROUP_ID; + HmrfpoLockRequest.MkhiHeader.Fields.Command = HMRFPO_LOCK_CMD_ID; + HmrfpoLockRequest.MkhiHeader.Fields.IsResponse = 1; + + HeciLength = sizeof (MKHI_HMRFPO_LOCK); + Status = mHeci->SendMsg ( + (UINT32 *) &HmrfpoLockRequest, + HeciLength, + BIOS_FIXED_HOST_ADDR, + HECI_CORE_MESSAGE_ADDR + ); + if (EFI_ERROR (Status)) { + IoWrite8(0x80, 0xA0); + return Status; + } + + HeciLength = sizeof (MKHI_HMRFPO_LOCK_RESPONSE); + Status = mHeci->ReadMsg ( + BLOCKING, + (UINT32 *) &HmrfpoLockResponse, + &HeciLength + ); + if (EFI_ERROR (Status)) { + IoWrite8(0x80, 0xA1); + return Status; + } else { + Factory_Base = HmrfpoLockResponse.FactoryDefaultBase; + Factory_Limit = HmrfpoLockResponse.FactoryDefaultLimit; + } + + return Status; + +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: GetRegionOffset +// +// Description: Get GBE Region Offet of whole FlashPart +// +// Input: +// VOID +// Output: +// UINT32 The offset of GBE Region +// +// Returns: +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +GetRegionOffset( + UINT8 Region, + UINT32* Offset, + UINT32* Length +) +{ + volatile UINT32 *FDOC; + volatile UINT32 *FDOD; + UINT32 FlashDescriptorSig = 0x0FF0A55A; + UINT32 Buffer32, RegionStart, RegionEnd; + + + FDOC = (UINT32*)(pSPIBASE + 0xB0); + FDOD = (UINT32*)(pSPIBASE + 0xB4); + *FDOC = 0; + + if (*FDOD != FlashDescriptorSig) + return EFI_UNSUPPORTED; + + switch(Region) + { + // Flash Descriptor + case 0: + *FDOC = 0x2000; + break; + + // BIOS + case 1: + *FDOC = 0x2004; + break; + + // ME + case 2: + *FDOC = 0x2008; + break; + + // GBE + case 3: + *FDOC = 0x200C; + break; + + // Platform Data + case 4: + *FDOC = 0x2010; + break; + + default: + return EFI_UNSUPPORTED; + break; + } + Buffer32 = *FDOD; + RegionEnd = Buffer32 >> 16; + RegionStart = Buffer32 & 0xFFFF; + + *Offset = RegionStart << 12; + *Length = (RegionEnd - RegionStart + 1) << 12; + if((Region == 0) && (RegionEnd == 0)) + { + *Length = 0x1000; + return EFI_SUCCESS; + } + if(RegionEnd == 0) + { + *Length = 0; + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: GetFlashCapacity +// +// Description: Send a HECI message to lock ME. +// +// Input: NONE +// +// Output: FlashDensity - Real Flash Size +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT32 GetFlashCapacity(VOID) +{ + volatile UINT32 *FDOC; + volatile UINT32 *FDOD; + UINT32 FlashDescriptorSig = 0x0FF0A55A; + UINT16 Components; + UINT8 i,j; + static UINT32 FlashDensity = 0; + + if(FlashDensity) + return FlashDensity; + + FDOC = (UINT32*)(pSPIBASE + 0xB0); + FDOD = (UINT32*)(pSPIBASE + 0xB4); + *FDOC = 0; + + if (*FDOD != FlashDescriptorSig) + return 0; + + *FDOC = 0x04; + Components = (*FDOD >> 8) & 0x03; + + *FDOC = 0x1000; + j = *FDOD; + + + for (i=0; i<(Components + 1); i++) + { + switch (j & 0x07) + { + case 0: + FlashDensity += 0x80000; + break; + case 1: + FlashDensity += 0x100000; + break; + case 2: + FlashDensity += 0x200000; + break; + case 3: + FlashDensity += 0x400000; + break; + case 4: + FlashDensity += 0x800000; + break; + case 5: + FlashDensity += 0x1000000; + break; + default: + break; + } +#if BITS_OF_SPI_DENSITY + j = j >> 4; +#else + j = j >> 3; +#endif + } + return FlashDensity; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: CSP_ReportMEInfo +// +// Description: Report ME Base address and Length to AFU +// +// Input: BASE_Address - address of ME region to be updated +// Length - Length of ME region to be updated +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS CSP_ReportMEInfo +( + IN UINT8 Func_Num, + IN OUT UINT32* BASE_Address, + IN OUT UINT32* Length +) +{ + switch (Func_Num) + { + case 0: + + *BASE_Address = 0; + *Length = GetFlashCapacity() - FLASH_SIZE; + return EFI_UNSUPPORTED; + + break; + case 3: + // Flash the whole SPI but BIOS region + *BASE_Address = 0; + *Length = GetFlashCapacity() - FLASH_SIZE; + if (Is_SECOVR_JMPR && Is_MEFW) + return EFI_SUCCESS; + else + return EFI_UNSUPPORTED; + break; + default: + return EFI_UNSUPPORTED; + break; + } + return EFI_SUCCESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: HeciCallback +// +// Description: Locate Heci protocol callback +// +// Input: +// IN EFI_EVENT Event +// IN VOID *Context +// +// Output: +// VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID HeciCallback( + IN EFI_EVENT Event, + IN VOID *Context +) +{ + EFI_STATUS Status; + + Status = pBS->LocateProtocol ( + &gEfiHeciProtocolGuid, + NULL, + &mHeci + ); + + if(EFI_ERROR(Status)) + mHeci = NULL; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: MeFwUpdLclCallback +// +// Description: Locate ME Firmware update local protocol callback +// +// Input: +// IN CONST EFI_GUID *Protocol +// IN VOID *Interface +// IN EFI_HANDLE Handle +// +// Output: +// VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS MeFwUpdLclCallback ( + IN CONST EFI_GUID *Protocol, + IN VOID *Interface, + IN EFI_HANDLE Handle +) +{ + EFI_STATUS Status; + + Status = gSmst->SmmLocateProtocol( + &mMeFwUpdLclProtocolGuid , NULL, + &mMeFwUpdateLocalProtocol ); + if( EFI_ERROR(Status) ) + mMeFwUpdateLocalProtocol = NULL; + + return Status; +} +#if defined SecSMIFlash_SUPPORT && SecSMIFlash_SUPPORT == 1 +/** + * Callback funciotn on Secure SmiFlash Protocol for saving FW Capsule Buffer address. + * @param Protocol OPTIONAL + * @param Interface OPTIONAL + * @param Handle OPTIONAL + * @retval EFI_SUCCESS Secure SmiFlash Protocol installed. + * @retval EFI_NOT_FOUND Secure SmiFlash Protocol not install yet. +**/ +static +EFI_STATUS +SecSmiFlashProtocolCallback ( + IN const EFI_GUID *Protocol, + IN VOID *Interface, + IN EFI_HANDLE Handle +) +{ + EFI_SEC_SMI_FLASH_PROTOCOL *SecSmiFlash = NULL; + if (EFI_ERROR(pBS->LocateProtocol( \ + &gEfiSecSmiFlashProtocolGuid, NULL, &SecSmiFlash))) + return EFI_NOT_FOUND; + gFwCapsuleAddress = SecSmiFlash->pFwCapsule; + return EFI_SUCCESS; +} +#endif +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: CSP_MEUDInSmm +// +// Description: Get Host Firmware Status. +// If needed, Send LOCK if needed in SMM. +// +// Input: NONE +// +// Output: NONE +// +// Returns: NONE +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID CSP_MEUDInSmm(VOID) +{ + UINT32 Buffer32; + EFI_STATUS Status; + VOID *MeFwUpdLclReg = NULL; + +#if PI_SPECIFICATION_VERSION >= 0x1000A + + Status = pBS->LocateProtocol(&gEfiSmmBase2ProtocolGuid, NULL, &gSmmBase2); + if (EFI_ERROR(Status)) return; + + Status = gSmmBase2->GetSmstLocation (gSmmBase2, &gSmst); + if (EFI_ERROR(Status)) return; + +#endif + + Buffer32 = *(volatile UINT32 *)((UINTN)PCIEX_BASE_ADDRESS + \ + (UINTN)(HECI_BUS << 20) + (UINTN)(HECI_DEV << 15) + \ + (UINTN)(HECI_FUN << 12) + (UINTN)(0x40)); + + if(Buffer32 == 0xFFFFFFFF) + { + UINT8* pRCBA_DIS2 = (UINT8*)(SB_RCRB_BASE_ADDRESS + R_PCH_RCRB_FD2); + // Enable HECI Device + *pRCBA_DIS2 &= 0xFD; + // Read Again + pBS->Stall (1000);//1ms + Buffer32 = *(volatile UINT32 *)((UINTN)PCIEX_BASE_ADDRESS + \ + (UINTN)(HECI_BUS << 20) + (UINTN)(HECI_DEV << 15) + \ + (UINTN)(HECI_FUN << 12) + (UINTN)(0x40)); + // Follow Spec ,Disable HECI Device + *pRCBA_DIS2 |= 0x02; + } + // Check If Ignition FW + // ME 8.0 is no more Ignition FW, It should alway be FALSE + if (((Buffer32 >> 16) & 0x0F) == 1) + IsIgnition = TRUE; + else + IsIgnition = FALSE; + + // Check If GPIO33 Assert + if ( (((Buffer32 >> 16) & 0x0F) == 4) || (((Buffer32 >> 16) & 0x0F) == 5)) + { + Is_SECOVR_JMPR = TRUE; + Status = pBS->AllocatePages(AllocateAnyPages, + EfiReservedMemoryType, + EFI_SIZE_TO_PAGES (GetFlashCapacity()), + &RomBuffer); + if(EFI_ERROR(Status)) + RomBuffer = NULL; + + Status = pBS->AllocatePages(AllocateAnyPages, + EfiReservedMemoryType, + EFI_SIZE_TO_PAGES (FLASH_BLOCK_SIZE), + &BlockBuffer); + if(EFI_ERROR(Status)) + BlockBuffer = NULL; + }else + Is_SECOVR_JMPR = FALSE; + + // Check If ME FW + if ((((Buffer32 >> 16) & 0x0F) == 0) || + (((Buffer32 >> 16) & 0x0F) == 3) || + (((Buffer32 >> 16) & 0x0F) == 4) || + (((Buffer32 >> 16) & 0x0F) == 5)) + Is_MEFW = TRUE; + else + Is_MEFW = FALSE; + + //ME Firmware update local + Status = gSmst->SmmLocateProtocol( &mMeFwUpdLclProtocolGuid , NULL, + &mMeFwUpdateLocalProtocol ); + if( EFI_ERROR(Status) ) + { + gSmst->SmmRegisterProtocolNotify( &mMeFwUpdLclProtocolGuid, + MeFwUpdLclCallback, + &MeFwUpdLclReg ); + } + +#if defined SecSMIFlash_SUPPORT && SecSMIFlash_SUPPORT == 1 + { + //VOID *Registration; + // Create SecSmiFlash Protocol Callback to get and save the FwCapsule + // Address, because of the address could be cleared after calling the + // functions of Secure SMI Flash protocol. + //pSmst->SmmRegisterProtocolNotify(&gEfiSecSmiFlashProtocolGuid, \ + // SecSmiFlashProtocolCallback, &Registration); + SecSmiFlashProtocolCallback(NULL, NULL, NULL); + } +#endif +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: MEProcessHandleResult +// +// Description: Handle ME Process +// +// Input: +// UpdateResult +// Message +// Output: +// VOID +// +// Returns: +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +MEProcessHandleResult( + IN UINT16 Result, + IN CHAR8* Message +) +{ + StructPtr->UpdateResult = Result; + MemCpy((UINT8*)(StructPtr->ddMessageBuffer), + Message, Strlen(Message)); + + *(CHAR8*)(StructPtr->ddMessageBuffer + Strlen(Message)) = 0; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: HandleBuffer +// +// Description: Init the Length and Offset need to be updated +// If needed, send ENABLE MESSAGE +// +// Input: +// UpdateResult +// Message +// Output: +// VOID +// +// Returns: +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +HandleBuffer( + IN OUT UINT32* ProgramOffset, + IN OUT UINT32* ProgramLength, + IN OUT UINT8* Step, + IN BOOLEAN InSmm +) +{ + EFI_STATUS Status; + UINT32 Offset, Length; + UINT32 HFS = GetHFS(); + + switch(StructPtr->bBlockType) + { + case FDT_BLK: + Status = GetRegionOffset(0, &Offset, &Length); + *Step = 0; + break; + + case PDR_BLK: + Status = GetRegionOffset(4, &Offset, &Length); + if(Status == EFI_NOT_FOUND) + return EFI_UNSUPPORTED; + *Step = 0; + break; + + case GBE_BLK: + Status = GetRegionOffset(3, &Offset, &Length); + if(Status == EFI_NOT_FOUND) + return EFI_UNSUPPORTED; + // Store Mac address + if(Length) + { + UINT8* Address = (UINT8*)FLASH_BASE_ADDRESS(Offset); + FlashRead(Address, MacAddr, 6); + } + *Step = 0; + break; + + case ME_BLK: + Status = GetRegionOffset(2, &Offset, &Length); + if((HFS & BIT05) || (HFS & BIT10)) + *Step = 2; + else + *Step = 1; + + break; + default: + *Step = 0; + return EFI_UNSUPPORTED; + break; + } + *ProgramOffset = Offset; + *ProgramLength = Length; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: UpdateRegions +// +// Description: UpdateRegions +// +// Input: +// Buffer +// +// Output: +// VOID +// +// Returns: +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +UpdateRegions( + IN UINT8* Buffer, + IN BOOLEAN InSmm +) +{ + static UINT32 Offset, Length; + UINT8* Address; + EFI_STATUS Status; + BOOLEAN FlashStatus = TRUE, NeedToVerify = FALSE; + static UINT8 Step = 0; + static BOOLEAN NewRegion; + UINTN Counter = 0; + static UINT8* ProgramBuffer; + UINT8* BufferForVerify = (UINT8*)BlockBuffer; + UINT32 i; + // Prepare Offset and Length to be updated + // If BIT02 , update buffer + if((StructPtr->bHandleRequest & BIT02)) + { + Status = HandleBuffer(&Offset, &Length, &Step, InSmm); + if(EFI_ERROR(Status)) + { + MEProcessHandleResult(BIT03, + "UN SUPPORT TYPE"); + return Status; + } + // Frist In + NewRegion = TRUE; + ProgramBuffer = (UINT8*)(Phy_Address + Offset); + } + + // Set MAC address to buffer + if(((StructPtr->bBlockType) == GBE_BLK) && NewRegion) + MemCpy((Buffer + Offset),MacAddr,6); + + if(NewRegion) + { + NewRegion = FALSE; + } + + Address = (UINT8*)FLASH_BASE_ADDRESS(Offset); + FlashBlockWriteEnable(Address); + + FlashEraseCommand(Address); + + // System hangs when using physical address. + // So, verify erase complete or not. + FlashStatus = TRUE; + FlashReadCommand(Address, BufferForVerify, FLASH_BLOCK_SIZE); + + for(i = 0 ; (i < FLASH_BLOCK_SIZE) && (*(BufferForVerify + i) == 0xFF) ; i++); + if(i != FLASH_BLOCK_SIZE) + FlashStatus = FALSE; + if(FlashStatus) + { + FlashProgramCommand(Address, ProgramBuffer, FLASH_BLOCK_SIZE); + FlashReadCommand(Address, BufferForVerify, FLASH_BLOCK_SIZE); + for(i = 0 ; (i < FLASH_BLOCK_SIZE) && (*(BufferForVerify + i) == *(BufferForVerify + i)) ; i++); + if(i != FLASH_BLOCK_SIZE) + FlashStatus = FALSE; + if(FlashStatus) + Status = EFI_SUCCESS; + else + Status = EFI_DEVICE_ERROR; + }else + Status = EFI_DEVICE_ERROR; + FlashBlockWriteDisable(Address); + ProgramBuffer = ProgramBuffer + FLASH_BLOCK_SIZE; + Length -= FLASH_BLOCK_SIZE; + Offset += FLASH_BLOCK_SIZE; + + // End of Region Update + if(Length == 0) + { + NewRegion = TRUE; + } + // TODO : + // OEM can output message here in every block updated. + // Remember to Set BIT02 + else + { + MEProcessHandleResult((BIT01), + " "); + return EFI_SUCCESS; + } + // Show Strings + if(!EFI_ERROR(Status)) + { + + switch(StructPtr->bBlockType) + { + case FDT_BLK: + MEProcessHandleResult((BIT03 | BIT02), + "Update success for /FDT!!"); + break; + case PDR_BLK: + MEProcessHandleResult((BIT03 | BIT02), + "Update success for /PDR!!"); + break; + case GBE_BLK: + MEProcessHandleResult((BIT03 | BIT02), + "Update success for /GBE!!"); + break; + + case ME_OPR_BLK: + MEProcessHandleResult((BIT03 | BIT02), + "Update success for /OPR!!"); + break; + + default: + MEProcessHandleResult((BIT03 | BIT02), + "Update success for /MER!!"); + break; + } + }else + { + switch(StructPtr->bBlockType) + { + case FDT_BLK: + MEProcessHandleResult((BIT03 | BIT02), + "/FDT is Locked !!"); + break; + + default: + MEProcessHandleResult((BIT00 | BIT02), + "Update Fail !!"); + break; + } + } + + return EFI_SUCCESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: MEProcessHandler +// +// Description: Handle ME Process +// +// Input: +// VOID +// Output: +// OFBD_TC_55_ME_PROCESS_STRUCT +// +// Returns: +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +MEProcessHandler +( + IN OUT OFBD_TC_55_ME_PROCESS_STRUCT **MEProcessStructPtr +) +{ + EFI_STATUS Status; + static UINTN NumberOfPages; + static UINT32 SizeCopied; + static BOOLEAN UseSmmMem = FALSE; + static EFI_PHYSICAL_ADDRESS SMM_Address; + static UINT8 HeciIsHide = 0; + static BOOLEAN UseMeFwUpdLcl = FALSE; + static UINTN BufferLength = 0; + + StructPtr = *MEProcessStructPtr; + switch(StructPtr->bHandleRequest) + { + // Allocate Buffer + case 1: +/* + if ((Mmio32(SB_RCBA, 0x3428) & BIT01) != 0) + { + MmioRW32((SB_RCBA+0x3428), 0, BIT01); + HeciIsHide = 1; + } +*/ + NumberOfPages = StructPtr->TotalBlocks; +#if PI_SPECIFICATION_VERSION >= 0x1000A + Status = gSmst->SmmAllocatePages(AllocateAnyPages, +#else + Status = pSmst->SmmAllocatePages(AllocateAnyPages, +#endif + EfiRuntimeServicesData, NumberOfPages, &SMM_Address); + if(!EFI_ERROR(Status)) + { + UseSmmMem = TRUE; + Phy_Address = SMM_Address; + }else + Phy_Address = RomBuffer; + // No memory allocated + if(!Phy_Address) + { + if( ( mMeFwUpdateLocalProtocol != NULL ) && + ( mMeFwUpdateLocalProtocol->FwUpdBufferAddress != NULL ) ) + { + UseMeFwUpdLcl = TRUE; + Phy_Address = mMeFwUpdateLocalProtocol->FwUpdBufferAddress; + BufferLength = mMeFwUpdateLocalProtocol->FwUpdBufferLength; + SizeCopied = 0; + break; + } + MEProcessHandleResult((BIT00 | BIT02), + "Error : No Memory Allocated!!"); + } + SizeCopied = 0; + break; + + // Recieve Data from AFU + case 2: + if( UseMeFwUpdLcl && + ( SizeCopied + StructPtr->ddMeDataSize > BufferLength ) ) + { + MEProcessHandleResult((BIT00 | BIT02), + "Error : No Memory Allocated!!"); + SizeCopied = 0; + break; + } + MemCpy((UINT8*)(Phy_Address + SizeCopied), + (UINT8*)StructPtr->ddMeDataBuffer,StructPtr->ddMeDataSize); + SizeCopied += StructPtr->ddMeDataSize; + + break; + + // Update + case 4: +#if (OFBD_VERSION >= 0x0220) + DoNotConvert = TRUE; +#endif + UpdateRegions((UINT8*)Phy_Address, TRUE); + break; + + // Continue.... + case 8: + UpdateRegions((UINT8*)Phy_Address, TRUE); + break; + + // Free Buffer + case 0x10: +#if (OFBD_VERSION >= 0x0220) + DoNotConvert = FALSE; +#endif + if(UseSmmMem) +#if PI_SPECIFICATION_VERSION >= 0x1000A + gSmst->SmmFreePages(Phy_Address, NumberOfPages); +#else + pSmst->SmmFreePages(Phy_Address, NumberOfPages); +#endif + + +// if (HeciIsHide) +// MmioRW32((SB_RCBA+0x3428), BIT01, 0); + break; + + case 0x20: + if( UseMeFwUpdLcl ) + mMeFwUpdateLocalProtocol->FwUpdLcl( mMeFwUpdateLocalProtocol, (UINT8*)Phy_Address, SizeCopied ); + break; + +#if defined SecSMIFlash_SUPPORT && SecSMIFlash_SUPPORT == 1 + // ME FW Capsule Update functions. + case 3: // ME FW Capsule Update. (ME FW only) + case 5: // ME FW Capsule Update. (BIOS + ME FW) + if (!gFwCapsuleAddress) { + MEProcessHandleResult((BIT00 | BIT02), "Error : Functon Not Supported!!"); + break; + } + Phy_Address = 0; + if ((StructPtr->bHandleRequest == 3) && \ + (StructPtr->TotalBlocks <= EFI_SIZE_TO_PAGES(FWCAPSULE_IMAGE_SIZE))) { + // Function#3 : ME FW Update only, upload ME FW capsule from the beggining. + Phy_Address = (EFI_PHYSICAL_ADDRESS)gFwCapsuleAddress; + } + if ((StructPtr->bHandleRequest == 5) && \ + (StructPtr->TotalBlocks <= \ + EFI_SIZE_TO_PAGES(FWCAPSULE_IMAGE_SIZE - FLASH_SIZE))) { + // Function#5 : BIOS + ME FW Update, upload capsule from the end of BIOS. + Phy_Address = (EFI_PHYSICAL_ADDRESS)gFwCapsuleAddress + FLASH_SIZE; + } + if (!Phy_Address) MEProcessHandleResult((BIT00 | BIT02), "Error : Buffer Too Small!!"); + break; +#endif // #if SecSMIFlash_SUPPORT == 1 + } +} +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2005, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 6145-F Northbelt Pkwy, Norcross, GA 30071 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Chipset/eM/ME/MEUD/CSP_MEUD.cif b/Chipset/eM/ME/MEUD/CSP_MEUD.cif new file mode 100644 index 0000000..be0b236 --- /dev/null +++ b/Chipset/eM/ME/MEUD/CSP_MEUD.cif @@ -0,0 +1,14 @@ +<component> + name = "CSP : ME 8.0 Firmware Update" + category = ModulePart + LocalRoot = "\Chipset\eM\ME\MEUD" + RefName = "CSP_MEUD" +[files] +"CSP_MEUD.c" +"CSP_MEUD.h" +"CSP_MEUD.sdl" +"CSP_MEUD.mak" +[parts] +"MEFwUpdLcl" +"MeFwCapsule" +<endComponent> diff --git a/Chipset/eM/ME/MEUD/CSP_MEUD.h b/Chipset/eM/ME/MEUD/CSP_MEUD.h new file mode 100644 index 0000000..85b511c --- /dev/null +++ b/Chipset/eM/ME/MEUD/CSP_MEUD.h @@ -0,0 +1,86 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2009, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* +//************************************************************************* +// $Header: /Alaska/SOURCE/Modules/OFBD Intel ME Update/CSP_MEUD/ME80/CSP_MEUD.h 2 5/16/13 6:30a Klzhan $ +// +// $Revision: 2 $ +// +// $Date: 5/16/13 6:30a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/OFBD Intel ME Update/CSP_MEUD/ME80/CSP_MEUD.h $ +// +// 2 5/16/13 6:30a Klzhan +// [TAG] EIPNone +// [Category] Improvement +// [Description] Add define for flash commands. +// +// 1 4/22/11 2:47a Klzhan +// Initial check - in +// +// +//********************************************************************** +//<AMI_FHDR_START> +// +// Name: CSP_MEUD.h +// +// Description: +// +//<AMI_FHDR_END> +//********************************************************************** +#ifndef _EFI_CSP_MEUD_H_ +#define _EFI_CSP_MEUD_H_ +#ifdef __cplusplus +extern "C" { +#endif + +VOID +FlashReadCommand ( + IN volatile UINT8* pByteAddress, + OUT UINT8 *Byte, + IN UINT32 Length +); + +VOID +FlashProgramCommand ( + IN volatile UINT8* pByteAddress, + IN UINT8 *Byte, + IN UINT32 Length +); + +VOID +FlashEraseCommand ( + IN volatile UINT8* pBlockAddress +); + +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2009, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/eM/ME/MEUD/CSP_MEUD.mak b/Chipset/eM/ME/MEUD/CSP_MEUD.mak new file mode 100644 index 0000000..bc4e861 --- /dev/null +++ b/Chipset/eM/ME/MEUD/CSP_MEUD.mak @@ -0,0 +1,133 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2009, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* +#************************************************************************* +# $Header: /Alaska/SOURCE/Modules/OFBD Intel ME Update/CSP_MEUD/ME80/CSP_MEUD.mak 5 5/14/15 4:33a Tristinchou $ +# +# $Revision: 5 $ +# +# $Date: 5/14/15 4:33a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/OFBD Intel ME Update/CSP_MEUD/ME80/CSP_MEUD.mak $ +# +# 5 5/14/15 4:33a Tristinchou +# [TAG] EIP215437 +# [Category] New Feature +# [Description] ME capsule update support on SharkBay +# +# 4 8/23/13 4:14a Tristinchou +# [TAG] EIPNone +# [Category] Improvement +# [Description] Fix build error with CrescentBay project. +# +# 3 9/07/12 4:46a Klzhan +# Support ME 9. +# +# 2 3/08/12 6:00a Klzhan +# Support AFU new command +# +# 1 4/22/11 2:47a Klzhan +# Initial check - in +# +# +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: CSP_MEUD.mak +# +# Description: +# +#<AMI_FHDR_END> +#********************************************************************** +#--------------------------------------------------------------------------- +# Create CSP ME FW Update Component +#--------------------------------------------------------------------------- +all : CSP_MEUD + +CSP_MEUD : $(BUILD_DIR)\CSP_MEUD.mak CSP_MEUDBin + +$(BUILD_DIR)\CSP_MEUD.mak : $(MEUD_CSP_DIR)\CSP_MEUD.cif $(MEUD_CSP_DIR)\CSP_MEUD.mak $(BUILD_RULES) + $(CIF2MAK) $(MEUD_CSP_DIR)\CSP_MEUD.cif $(CIF2MAK_DEFAULTS) + +CSP_MEUD_DEFINES=\ + $(MY_DEFINES) /D __EDKII_GLUE_BASE_MEMORY_LIB__\ + /D __EDKII_GLUE_EDK_DXE_RUNTIME_DRIVER_LIB__\ + /D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__\ + +CSP_MEUD_INCLUDES = \ + $(EdkIIGlueLib_INCLUDES)\ + $(ME_INCLUDES) \ + $(EdkIIGlueLib_INCLUDES) \ + $(ME_INCLUDES) \ + $(MeLibSmm_DIR) \ + $(MeProtocolLib_DIR) \ + $(MeProtocolLib_DIR)\SmmHeci \ + /I$(PROJECT_DIR)\Core\EM\OFBD\ +!IFDEF INTEL_COUGAR_POINT_INCLUDE_DIR + /I$(INTEL_COUGAR_POINT_INCLUDE_DIR) +!ELSE + /I$(INTEL_PCH_INCLUDE_DIR) +!ENDIF + + +CSP_MEUD_LIBS=\ + $(MeLibSmm_LIB)\ + $(EfiScriptLib_LIB)\ + $(EdkIIGlueBaseLib_LIB)\ + $(EDKFRAMEWORKPROTOCOLLIB)\ + $(EFIPROTOCOLLIB)\ +!IF "$(x64_BUILD)"=="1" + $(EdkIIGlueBaseLibX64_LIB)\ +!ELSE + $(EdkIIGlueBaseLibIA32_LIB)\ +!ENDIF + $(EdkIIGlueDxeReportStatusCodeLib_LIB)\ + $(EdkIIGluePeiDxeDebugLibReportStatusCode_LIB)\ + $(EdkIIGlueUefiBootServicesTableLib_LIB)\ + $(EdkIIGlueUefiDevicePathLib_LIB)\ + $(EdkIIGlueBasePciLibPciExpress_LIB)\ + $(EdkIIGlueBasePciExpressLib_LIB)\ + $(EdkIIGlueDxeMemoryAllocationLib_LIB)\ + $(EFIGUIDLIB)\ + $(EDKPROTOCOLLIB)\ + $(EdkIIGlueBaseIoLibIntrinsic_LIB)\ + $(EdkIIGlueBaseMemoryLib_LIB)\ + $(EdkIIGlueEdkDxeRuntimeDriverLib_LIB)\ + $(EdkIIGlueUefiLib_LIB)\ + $(EdkIIGlueDxeHobLib_LIB)\ + +CSP_MEUDBin : $(CSP_MEUD_LIBS) + @set INCLUDE=%%INCLUDE%% + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\CSP_MEUD.mak all\ + "MY_INCLUDES=$(CSP_MEUD_INCLUDES)" \ + "MY_DEFINES=$(CSP_MEUD_DEFINES)"\ + NAME=CSP_MEUD \ + TYPE=LIBRARY LIBRARY_NAME=$(CSP_MEUDLIB) + +$(CSP_MEUDLIB) : CSP_MEUD +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2009, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/CSP_MEUD.sdl b/Chipset/eM/ME/MEUD/CSP_MEUD.sdl new file mode 100644 index 0000000..458562c --- /dev/null +++ b/Chipset/eM/ME/MEUD/CSP_MEUD.sdl @@ -0,0 +1,47 @@ +TOKEN + Name = CSP_MEUD_SUPPORT + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable ME Firmware Update Chipset function in Project" +End + +TOKEN + Name = "CSP_MEUDLIB" + Value = "$(BUILD_DIR)\CSP_MEUD.lib" + TokenType = Expression + TargetMAK = Yes +End + +MODULE + Help = "Includes MEUD.mak to Project" + File = "CSP_MEUD.mak" +End + +PATH + Name = "MEUD_CSP_DIR" +End + +ELINK + Name = "$(BUILD_DIR)\CSP_MEUD.lib" + Parent = "OFBDLISTLIB" + InvokeOrder = AfterParent +End + +TOKEN + Name = "pSPIBASE" + Value = "$(SB_RCBA) + $(SPI_BASE_ADDRESS)" + TokenType = Integer + TargetH = Yes + Help = "Fill SPI_BASE." +End + +TOKEN + Name = "BITS_OF_SPI_DENSITY" + Value = "1" + TokenType = Integer + TargetH = Yes + Help = "Please check Flash Descriptor Component Section in SPI Programming Guid, 0 = 3 BITs for Density , 1 = 4 BITs for Density" +End
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/IntelLib/FWUpdateLib.h b/Chipset/eM/ME/MEUD/MEFwUpdLcl/IntelLib/FWUpdateLib.h new file mode 100644 index 0000000..062fe89 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/IntelLib/FWUpdateLib.h @@ -0,0 +1,566 @@ +/*++ + +This file contains a 'Sample Driver' and is licensed as such +under the terms of your license agreement with Intel or your +vendor. This file may be modified by the user, subject to +the additional terms of the license agreement + +--*/ + +/*++ + +Copyright (c) 2009-13 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + + +Module Name: + + FwUpdateLib.h + +Abstract: + + FW Update Local Sample Code Header file + +--*/ + +#define INVALID_DATA_FORMAT_VERSION 0 +#define INVALID_MANIFEST_DATA 1 +#define NO_FPT_IMAGE 2 +#define MANIFEST_BUFFER 0x1000 +#define FPT_PARTITION_NAME_FPT 0x54504624 + +//===== +#define bool BOOLEAN + +extern +InitializeLib( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +); + +void _fltused(); + +typedef UINT32 STATUS; + +typedef struct { + UINT16 Major; + UINT16 Minor; + UINT16 Hotfix; + UINT16 Build; +} FWVersion; + +typedef struct { + FWVersion code; + FWVersion rcvy; +} FlashVersion; + +typedef struct +{ + unsigned long Data1; + unsigned short Data2; + unsigned short Data3; + unsigned char Data4[8]; +} _UUID; + +typedef enum +{ + FWU_ENV_MANUFACTURING = 0, // Manufacturing update + FWU_ENV_IFU, // Independent Firmware update +}FWU_ENVIRONMENT; + +enum errorValues { + FWU_ERROR_SUCCESS, + FWU_IME_NO_DEVICE = 8193, + FWU_UPD_VER_MIS = 8199, + FWU_VER_GET_ERR = 8204, + FWU_CERT_ERR = 8213, + FWU_REBOOT_NEEDED = 8703, + FWU_SKU_MISMATCH, + FWU_VER_MISMATCH, + FWU_SGN_MISMATCH, + FWU_GENERAL, + FWU_UPD_PROCESS, + FWU_NO_MEMORY = 8710, + FWU_AUTH = 8712, + FWU_IMG_HEADER, + FWU_FILE_OPEN, + FWU_HTTP_ERROR, + FWU_USAGE_ERROR, + FWU_HOSTNAME, + FWU_UPDATE_TIMEOUT, + FWU_LOCAL_DIS, + FWU_SECURE_DIS, + FWU_IME_UN_SUP_MESS = 8722, + FWU_NO_UPDATE, + FWU_IME_NOT_READY, + FWU_LAST_STATUS, + FWU_GET_VER_ERR = 8727, + FWU_IME_SMALL_BUFF, + FWU_WSMAN_NO = 8734, + FWU_UNSUPPRT_OS = 8740, + FWU_ERROR_FW, + FWU_HECI, + FWU_UNSUPPRT_PLAT, + FWU_VERIFY_OEM_ID_ERR, + FWU_INVALID_OEM_ID = 8745, + FWU_INVALID_IMG_LENGTH, + FWU_GLBL_BUFF_UNAVAILABLE, + FWU_INVALID_FW_PARAMS, + FWU_AMT_STATUS_INTERNAL_ERROR, + FWU_AMT_STATUS_NOT_READY = 8750, + FWU_AMT_STATUS_INVALID_AMT_MODE, + FWU_AMT_STATUS_INVALID_MESSAGE_LENGTH, + FWU_SAVE_RESTORE_POINT_ERROR, + FWU_FILE_WRITE, + FWU_GET_BLIST_ERROR = 8755, + FWU_CHECK_VERSION_ERROR, + FWU_DISPLAY_FW_VERSION, + FWU_IMAGE_UNDER_VCN, + FWU_IMAGE_VER_HIST_CHK_FAIL, + FWU_DOWNGRADE_VETOED = 8760, + FWU_FW_WRITE_FILE_FAIL, + FWU_FW_READ_FILE_FAIL, + FWU_FW_DELETE_FILE_FAIL, + FWU_PARTITION_LAYOUT_NOT_COMP, + FWU_DOWNGRADE_NOT_ALLOWED_DATA_MISMATCH = 8765, + FWU_UPDATE_PASSWORD_NOT_MATCHED, + FWU_UPDATE_PASSWORD_EXCEED_MAXIMUM_RETRY, + FWU_UPDATE_PASSWORD_NOT_PROVIDED, + FWU_UPDATE_POLLING_FAILED, + FWU_FILE_ALREADY_EXISTS = 8770, + FWU_FILE_INVALID, + FWU_USAGE_ERROR_B, + FWU_AUDIT_POLICY_FAILURE, + FWU_ERROR_CREATING_FT, + FWU_SAL_NOTIFICATION_ERROR = 8775, + FWU_GET_PATTRIB_ERROR, + FWU_GET_UPD_INFO_STATUS, + FWU_PID_NOT_EXPECTED, + FWU_UPDATE_INRECOVERY_MODE_RESTRICT_UPDATE_TO_ATTEMPTED_VERSION, + FWU_BUFFER_COPY_FAILED, + FWU_GET_ME_FWU_INFO, + FWU_APP_REGISTER_OS_FAILURE, + FWU_APP_UNREGISTER_OS_FAILURE, + FWU_INVALID_PARTID, + FWU_LIVE_PING_FAILURE, + FWU_SERVICE_CONNECT_FAILURE, + FWU_SERVICE_NOT_AVAILABLE, + FWU_SERVICE_BUSY, + FWU_USER_NOT_ADMIN, + FWU_WMI_FAIL, + FWU_CHK_BIT_LOCKER_FAIL, + FWU_REG_CMD_FAIL, + FWU_UPDATE_IMAGE_BLACKLISTED, + FWU_DOWNGRADE_NOT_ALLOWED_SVN_RESTRICTION +}; +//===== + + +// below structure is defiend by the fw team +// in fwucommon.h file +typedef struct _UPDATE_FLAGS_LIB +{ + unsigned int RestorePoint:1; // If set indicate restore point + unsigned int RestartOperation:1; // If set indicate restart operation, like lost hard drive etc... + unsigned int UserRollback:1; // indicates user has initiated a rollback + unsigned int Reserve:29; // +}UPDATE_FLAGS_LIB; + +// Used by the tool to perform FULL FW update +typedef enum _UPDATE_TYPE +{ + DOWNGRADE_SUCCESS = 0, + DOWNGRADE_FAILURE, + SAMEVERSION_SUCCESS, + SAMEVERSION_FAILURE, + UPGRADE_SUCCESS, + UPGRADE_PROMPT +}UPDATE_TYPE; + +//Image type to validate the binary sent to update +//For Full Update - only FULL image type is valid +//For Partial Update - only FULL and PARTIAL image type is valid +//FULL Image => Image with Flash Partition Table, FTPR, and NFTPR +//PARTIAL Image => Image with no Flash Partition Table or FTPR or NFTPR, +// only WCOD or LOCL +typedef enum _IMAGE_TYPE +{ + FULL = 0, + PARTIAL, + RESTORE, + INVALID +}IMAGE_TYPE; + +typedef enum _SKU_TYPE { + SKU_1_5_MB = 0, + SKU_5_MB, + SKU_INVALID +}SKU_TYPE; + +//Used by the tool to retrieve FW version information +typedef struct { + unsigned short Major; + unsigned short Minor; + unsigned short Hotfix; + unsigned short Build; +} VersionLib; + +//Should be used by both tool and UNS to retrieve the Updated UPV version +typedef struct _IPU_UPDATED_INFO +{ + unsigned int UpdatedUpvVer;//Version from the update image file that is for updating IPU + unsigned int Reserved[4]; +}IPU_UPDATED_INFO; + +// disable the "zero-sized array" warning +#pragma warning(disable:4200) +typedef enum _FWU_STATUS { + FWU_STATUS_SUCCESS = 0, + FWU_STATUS_NO_MEMORY = 1, + FWU_STATUS_NOT_READY = 2, + FWU_STATUS_ILLEGAL_LENGTH = 3, + FWU_STATUS_AUTHENTICATION_FAILED = 4, + FWU_STATUS_INTERNAL_ERROR = 5, + FWU_STATUS_SKU_FAILURE = 6, + FWU_STATUS_VERSION_FAILURE = 7 +}FWU_STATUS; + +// From FWU_if.h + +#pragma pack(1) + +/** + * FWU_GET_INFO_MESSAGE - get version + * + * @MessageType: FWU_MESSAGE_TYPE_GET_INFO + */ +typedef struct { + UINT32 MessageType; +} FWU_GET_INFO_MESSAGE; + +/** + * FWU_DATA_MESSAGE - data fragment of the image + * + * @MessageType: FWU_MESSAGE_TYPE_DATA + * @Length: The length of the data field, in Little Endian + * @Reserved: Reserved, must be 0 + * @Data: The data of the image fragment + */ +typedef struct { + UINT32 MessageType; + UINT32 Length; + UINT8 Reserved[3]; +#ifndef _DOS + UINT8 Data[0]; +#endif +} FWU_DATA_MESSAGE; + +#pragma pack() + +bool +IsUpdateStatusPending ( + IN UINT32 status +) +/*++ + +Routine Description: + + Checks if ME FW Update client is ready to accept an update + +Arguments: + + +Returns: + + true if ready + +--*/ +; + +unsigned int +CheckPolicyBuffer ( + IN char* buffer, + IN int bufferLength, + IN int AllowSV, + IN UPDATE_TYPE *Upd_Type, + IN VersionLib *ver +) +/*++ + +Routine Description: + + This routine determines if the update is allowed given the ME Upgrade/downgrade/same version policy + +Arguments: + +Returns: + + FWU_ERROR_SUCCESS if operation allowed + +--*/ +; + +unsigned int +FwUpdateFullBuffer ( + IN char *buffer, + IN unsigned int bufferLength, + IN char *_pwd, + IN int _forceResetLib, + IN unsigned int UpdateEnvironment, + IN _UUID OemID, + IN UPDATE_FLAGS_LIB update_flags, + IN void(*func)(float, float) +) +/*++ + +Routine Description: + + This routine sends the buffer to the ME FW Update Client + +Arguments: + +Returns: + + FWU_ERROR_SUCCESS if operation allowed + +--*/ +; + +unsigned int +FWUpdate_QueryStatus_Get_Response ( + IN unsigned int *UpdateStatus, + IN unsigned int *TotalStages, + IN unsigned int *PercentWritten, + IN unsigned int *LastUpdateStatus, + IN unsigned int *LastResetType +) +/*++ + +Routine Description: + + This routine queries the ME Kernel for the update status + +Arguments: + +Returns: + + FWU_ERROR_SUCCESS if operation allowed + +--*/ +; + +bool +VerifyOemId( + IN _UUID id +) +/*++ + +Routine Description: + + The ME FW when created has an OEM ID embedded in it. For security + reasons, we need to verify that the OEM ID of the application (mOemID) + matches the OEM ID of the ME FW. + + NOTE: A connection to the client is required before this routine is + executed. + +Arguments: + + UUID to check + + +Returns: + + true or false indicating if the match was succesfull + +--*/ +; + +EFI_STATUS +GetLastStatus( + OUT UINT32 *LastFwUpdateStatus +) +/*++ + +Routine Description: + + Get the last status of the FW Update Client - this is used to determine if a previous update + requires a reboot + +Arguments: + + UINT32 pointer for results of previous update. + + +Returns: + + EFI Error code + +--*/ +; + +EFI_STATUS +GetLastUpdateResetType ( + OUT UINT32 *LastResetType +)/*++ + +Routine Description: + + Get the last status of the FW Update Client - this is used to determine if a previous update + requires a reboot + +Arguments: + + UINT32 pointer for results of previous update. + + +Returns: + + EFI Error code + +--*/ +; + +EFI_STATUS +GetInterfaces ( + OUT UINT16 *interfaces +) +; + +EFI_STATUS +CheckVersion( + IN UINT8 *FileBuffer, + IN BOOLEAN AllowSV, + OUT FlashVersion *FlashVersion, + OUT UINT32 *LastFwUpdateStatus +) +/*++ + +Routine Description: + + Policy routine to verify if the current FW version is older + than the version in the image. + + The routine will return the result of a previous ME FW Update. If a reset is required + before an update can occur, the return value will indicate it + + NOTE: A connection to the client is required before this routine is + executed. + +Arguments: + + UINT8 pointer to update image + BOOLEAN indicating TRUE for same version update + FlashVersion pointer for return version numbers of FW Update image + UINT32 pointer for results of previous update. + + +Returns: + + EFI_UNSUPPORTED if version is of update image is not supported + +--*/ +; + +EFI_STATUS +StartUpdate( + IN UINT8 *FileBuffer, + IN UINT32 FileLength, + IN CHAR8 *Password, + IN VOID (*DataProgressProc)(), + IN UINT32 DataProgessSteps, + OUT STATUS *FWU_Status +) +/*++ + +Routine Description: + + Start the update process by asking the ME FW Update client + to allocate a buffer for the image. Note that the ME does not update the flash until + the FWU_END message is received. + + If the current ME Flash image is password protected, then that password is required to unlock + the update process + + Because the process of downloading the image is time consuming, a callback is provided for each + chunk of data sent to the ME FW Update client. If desired, the caller can specify the number of steps + that the total data send will have (e.g. 100 means a total of 100 callbacks for the entire duration). The + number of steps supplied will be divided by the total result of (FileLength / Chunksize) + 1. + +Arguments: + + UINT8 pointer to FW Update Image + UINT32 FW Update image length + CHAR16 pointer to password (if no password then NULL) + VOID pointer to callback function (if no callback then NULL) + UINT32 callback steps (1 means each packet sent will trigger a callback) + UINT32 pointer to ME FW Update Client return status + +Returns: + + EFI_STATUS + +--*/ +; + +EFI_STATUS +EndUpdate ( + IN VOID (*EndProgressProc)(), + IN UINT32 EndProgressSteps, + OUT STATUS *FWU_Status +) +/*++ + +Routine Description: + + Send the FWU_END message to the ME after a successful data download. + This operation will request the ME to validate the image and update the + flash. Depending on flash speed, the operation may take serveral minutes + to finish. Be patient... + + Because the process of updating the image is time consuming, a callback is provided each delay (5 seconds) + that occurs waiting for the ME FW Update client to respond. If desired, the caller can specify a number of timeouts before + a callback (e.g. 1 means send wait 5 seconds then invoke the callback routine). + +Arguments: + + VOID pointer to callback function (if no callback then NULL) + UINT32 callback ratio (1 means wait 5 seconds and then trigger a callback) + UINT32 pointer to ME FW Update Client return status + +Returns: + + EFI_STATUS + +--*/ +; + +EFI_STATUS +GetFwFlashVersion( + IN FWVersion *fwVersion +) +/*++ + +Routine Description: + + Get the FW version of the currently running ME FW + + NOTE: A connection to the client is required before this routine is + executed. + +Arguments: + + FWVersion pointer to FW Flash version + +Returns: + + EFI_STATUS + +--*/ +;
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/IntelLib/FWUpdateLib.lib b/Chipset/eM/ME/MEUD/MEFwUpdLcl/IntelLib/FWUpdateLib.lib Binary files differnew file mode 100644 index 0000000..267f5a6 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/IntelLib/FWUpdateLib.lib diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/IntelLib/me_status.h b/Chipset/eM/ME/MEUD/MEFwUpdLcl/IntelLib/me_status.h new file mode 100644 index 0000000..5a66448 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/IntelLib/me_status.h @@ -0,0 +1,986 @@ +/*++ + +INTEL CONFIDENTIAL +Copyright 2005-2013 Intel Corporation All Rights Reserved. + +The source code contained or described herein and all documents +related to the source code ("Material") are owned by Intel Corporation +or its suppliers or licensors. Title to the Material remains with +Intel Corporation or its suppliers and licensors. The Material +contains trade secrets and proprietary and confidential information of +Intel or its suppliers and licensors. The Material is protected by +worldwide copyright and trade secret laws and treaty provisions. No +part of the Material may be used, copied, reproduced, modified, +published, uploaded, posted, transmitted, distributed, or disclosed in +any way without Intel's prior express written permission. + +No license under any patent, copyright, trade secret or other +intellectual property right is granted to or conferred upon you by +disclosure or delivery of the Materials, either expressly, by +implication, inducement, estoppel or otherwise. Any license under such +intellectual property rights must be express and approved by Intel in +writing. + +File Name: + + me_status.h + +Abstract: + + Defines the ME Status codes + +Authors: + + Hemaprabhu Jayanna + +--*/ + +#ifndef _ME_STATUS_H_ +#define _ME_STATUS_H_ + +/////////////////////////////////////////////////////////////////////////////// +// ERROR & STATUS CODE RANGES // +/////////////////////////////////////////////////////////////////////////////// +// RANGE // DESCRIPTION // +/////////////////////////////////////////////////////////////////////////////// +// 0x0000FFFF - 0x00000000 // Pre-defined standard error values used by all // +// // ME Components and interfaces // +/////////////////////////////////////////////////////////////////////////////// +// 0x0001FFFF - 0x00010000 // Capability Module specific error codes // +/////////////////////////////////////////////////////////////////////////////// +// 0xFFFFFFFF - 0x00020000 // Reserved for future use. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// KERNEL STATUS AND ERROR CODES // +//The following are the status and error codes returned by the ME Kernel. // +//ThreadX Codes range from (0x00 to 0x7F) // +//Other Kernel codes range from (0x80 to 0xFF) // +/////////////////////////////////////////////////////////////////////////////// + + + + +// +//STATUS_SUCCESS +// The operation completed successfully. +// + +/** + * @brief The operation completed successfully. + */ +#define STATUS_SUCCESS 0x0 + +// +//STATUS_DELETED +// The requested object has been deleted. +// +#define STATUS_DELETED 0x1 + +// +//STATUS_POOL_ERROR +// An invalid memory pool pointer (NULL) was given or the pool is +// already created. +// +#define STATUS_POOL_ERROR 0x2 + +// +//STATUS_PTR_ERROR +// An invalid pointer was provided. +// +#define STATUS_PTR_ERROR 0x3 + +// +//STATUS_WAIT_ERROR +// The specified wait option is invalid. +// +#define STATUS_WAIT_ERROR 0x4 + +// +//STATUS_SIZE_ERROR +// The size of the specified object (memory pool, stack, message queue, +// etc.) is invalid. +// +#define STATUS_SIZE_ERROR 0x5 + +// +//STATUS_GROUP_ERROR +// An invalid group pointer was provided. The pointer is NULL or points +// to an already created group. +// +#define STATUS_GROUP_ERROR 0x6 + +// +//STATUS_NO_EVENTS +// The requested event could not be found. +// +#define STATUS_NO_EVENTS 0x7 + +// +//STATUS_OPTION_ERROR +// Invalid event flag set option (AND, OR). +// +#define STATUS_OPTION_ERROR 0x8 + +// +//STATUS_QUEUE_ERROR +// An invalid queue pointer passed or the queue is already created. +// +#define STATUS_QUEUE_ERROR 0x9 + +// +//STATUS_QUEUE_EMPTY +// The requested queue is empty. +// +#define STATUS_QUEUE_EMPTY 0xA + +// +//STATUS_QUEUE_FULL +// The requested queue is full. +// +#define STATUS_QUEUE_FULL 0xB + +// +//STATUS_SEMAPHORE_ERROR +// An invalid semaphore pointer provided or the semaphore is already created. +// +#define STATUS_SEMAPHORE_ERROR 0xC + +// +//STATUS_NO_INSTANCE +// The requested instance was not found (semaphore count is 0x0). +// +#define STATUS_NO_INSTANCE 0xD + +// +//STATUS_THREAD_ERROR +// An invalid thread control pointer provided or the thread is already created. +// +#define STATUS_THREAD_ERROR 0xE + +// +//STATUS_PRIORITY_ERROR +// An invalid thread priority level has been given. +// +#define STATUS_PRIORITY_ERROR 0xF + +// +//STATUS_START_ERROR +// An invalid auto-start selection was given during thread creation. +// NOTE: This value is the same a as STATUS_NO_MEMORY. +// +#define STATUS_START_ERROR 0x10 + +// +//STATUS_DELETE_ERROR +// The requested object can not be deleted. This can occur if an attempt is +// made to delete a thread that is not in a terminated or completed state. +// +#define STATUS_DELETE_ERROR 0x11 + +// +//STATUS_RESUME_ERROR +// The thread can not be resumed (e.g. the specified thread is not in a +// suspended state or was suspended by a driver other than the RTOS protocol). +// +#define STATUS_RESUME_ERROR 0x12 + +// +//STATUS_CALLER_ERROR +// Invalid caller of this service. +// +#define STATUS_CALLER_ERROR 0x13 + +// +//STATUS_SUSPEND_ERROR +// The thead can not be suspended (e.g. the specified thread is in a +// terminated or completed state). +// +#define STATUS_SUSPEND_ERROR 0x14 + +// +//STATUS_TIMER_ERROR +// An invalid timer object pointer was given. +// +#define STATUS_TIMER_ERROR 0x15 + +// +//STATUS_TICK_ERROR +// An invalid value (0x0) supplied for the initial tick count. +// +#define STATUS_TICK_ERROR 0x16 + +// +//STATUS_ACTIVATE_ERROR +// The object is already active. +// +#define STATUS_ACTIVATE_ERROR 0x17 + +// +//STATUS_THRESH_ERROR +// An invalid preemption threashold was specified. +// +#define STATUS_THRESH_ERROR 0x18 + +// +//STATUS_SUSPEND_LIFTED +// An attempt to resume a thread marked for delayed suspension has +// occurred. +// +#define STATUS_SUSPEND_LIFTED 0x19 + +// +//STATUS_WAIT_ABORTED +// The wait condition on which the thread is waiting has been aborted. +// +#define STATUS_WAIT_ABORTED 0x1A + +// +//STATUS_WAIT_ABORT_ERROR +// An attempt to abort a waiting thread was attempted on a thread that is +// not in a waiting condition (terminated, ready, completed, etc.). +// +#define STATUS_WAIT_ABORT_ERROR 0x1B + +// +//STATUS_MUTEX_ERROR +// An invalid mutex pointer was provided. +// +#define STATUS_MUTEX_ERROR 0x1C + +// +//STATUS_NOT_AVAILABLE +// An attempt to remove a mutex on which a thread is suspended has been +// attempted. +// +#define STATUS_NOT_AVAILABLE 0x1D + +// +//STATUS_NOT_OWNED +// An attempt to access a mutex not owned by the caller was made. +// +#define STATUS_NOT_OWNED 0x1E + +// +//STATUS_INHERIT_ERROR +// An invalid inherit option was given when trying to create a mutex. +// +#define STATUS_INHERIT_ERROR 0x1F + +// +//STATUS_TIMER_RUNNING +// An attempt to set an alarm was made while alarm is already enabled. +// +#define STATUS_TIMER_RUNNING 0x20 + +// +//STATUS_INVALID_FUNCTION +// The requested function was not found. +// +#define STATUS_INVALID_FUNCTION 0x80 + +// +//STATUS_NOT_FOUND +// The requested item could not be found. +// +#define STATUS_NOT_FOUND 0x81 + +// +//STATUS_ACCESS_DENIED +// Access to the requested object could not be granted. +// +#define STATUS_ACCESS_DENIED 0x82 + +// +//STATUS_INVALID_HANDLE +// The provided handle does not exist. +// +#define STATUS_INVALID_HANDLE 0x83 + +// +//STATUS_INVALID_ACCESS +// An attempt was made to access an inaccessible or unavailable object. +// +#define STATUS_INVALID_ACCESS 0x84 + +// +//STATUS_INVALID_PARAMS +// One or more parameters are invalid. +// +#define STATUS_INVALID_PARAMS 0x85 + +// +//STATUS_INVALID_PARAMS +// Request could not be processed because a Power Management event is already +// in progress. +// +#define STATUS_PM_EVENT_IN_PROGRESS 0x86 + +// +//STATUS_WRITE_PROTECTED +// The media is write protected. When writing to flash, this means +// the flash block is write protected. +// +#define STATUS_WRITE_PROTECTED 0x87 + +// +//STATUS_NOT_READY +// The h/w device is not ready. +// +#define STATUS_NOT_READY 0x88 + +// +//STATUS_NOT_SUPPORTED +// The function, message or request is not recognized or supported. +// +#define STATUS_NOT_SUPPORTED 0x89 + +// +//STATUS_NETWORK_BUSY +// The network device is busy. +// +#define STATUS_NETWORK_BUSY 0x8A + +// +//STATUS_DEVICE_ERROR +// The h/w device reported an error while attempting the operation. +// +#define STATUS_DEVICE_ERROR 0x8B + +// +//STATUS_INVALID_ADDRESS +// The address provided in invalid. +// +#define STATUS_INVALID_ADDRESS 0x8C + +// +//STATUS_INVALID_COMMAND +// The requested command is unrecognized or invalid. +// +#define STATUS_INVALID_COMMAND 0x8D + +// +//STATUS_STACK_OVERFLOW +// The request caused a stack overflow. +// +#define STATUS_STACK_OVER_FLOW 0x8E + +// +//STATUS_BUFFER_TOO_SMALL +// The provided buffer is too small to hold the requested data. +// +#define STATUS_BUFFER_TOO_SMALL 0x8F + +// +//STATUS_LOAD_ERROR +// The image failed to load. +// +#define STATUS_LOAD_ERROR 0x90 + +// +//STATUS_INVALID_BUFFER +// The buffer was not the proper size for the request. +// +#define STATUS_INVALID_BUFFER 0x91 + +// +//STATUS_NO_RESPONSE +// No response was received from the requested target. +// +#define STATUS_NO_RESPONSE 0x92 + +// +//STATUS_TIMED_OUT +// The device or object timed out and was unable to complete the request. +// +#define STATUS_TIMED_OUT 0x93 + +// +//STATUS_NOT_STARTED +// The requested operation could not be started. For protocols, this +// error indicates the protocol has not been started. +// +#define STATUS_NOT_STARTED 0x94 + +// +//STATUS_ALREADY_STARTED +// The requested operation has already been started. +// - For protocols, this error +// indicates the protocol has already been started. +// - For Policy Manager this error means +// that the MKHI group ID is already registered. +// For FW update, we only allow one process to do the update at a time, this means error +// case where FW update is already in progress, the current process will have to try later. +// +#define STATUS_ALREADY_STARTED 0x95 + +// +//STATUS_PROTOCOL_ERROR +// The protocol in use has generated an error. For network traffic this error +// means the networking protocol returned and error. When returned from a +// protocol this means the protocol itself generated an error. +// +#define STATUS_PROTOCOL_ERROR 0x96 + +// +//STATUS_INCOMPATIBLE_VERSION +// The version of the object is incompatible with the request. For protocols, +// this indicates that the protocol version number is not supported. +// +#define STATUS_INCOMPATIBLE_VERSION 0x97 + +// +//STATUS_SECURITY_VIOLATION +// A security violation has occurred. +// +#define STATUS_SECURITY_VIOLATION 0x98 + +// +//STATUS_AUTHENTICATION_FAIL +// The authentication of an object has failed. +// +#define STATUS_AUTHENTICATION_FAIL 0x99 + +// +//STATUS_INVALID_MEM_TYPE +// The target memory is invalid for the requested operation (e.g. DMA to +// ROM or cypto DMA from system memory). +// +#define STATUS_INVALID_MEM_TYPE 0x9A + +// +//STATUS_MODE_NOT_SUPPORTED +// The type of blocking mode is not supported. Refer to the documentation on +// the specific interface. +// +#define STATUS_MODE_NOT_SUPPORTED 0x9B + +// +//STATUS_RESOURCE_BUSY +// The requested resource is busy or can not be acquired. +// +#define STATUS_RESOURCE_BUSY 0x9C + +// +//STATUS_OUT_OF_RESOURCES +// Insufficient resources to perform the request. Used by components operating +// in non-blocking mode. A caller will be returned this error when a component +// does not have enough resources like command buffers, PRDs etc... to entertain +// a new request. +// +#define STATUS_OUT_OF_RESOURCES 0x9D + +// +//STATUS_FAILURE +// A unknown error encountered while performing a requested transaction. +// +#define STATUS_FAILURE 0x9E + +// +//STATUS_QUEUED +// A requested has been successfully placed in a command queue. This status +// is returned by non-blocking components after successfully queuing a request +// in their command queue. +// +#define STATUS_QUEUED 0x9F + +// +//STATUS_WEAR_OUT_VIOLATION +// The partition manager returns this error code when it can not perform a +// requested erase operation due to flash wear out constraints. +#define STATUS_WEAR_OUT_VIOLATION 0xA0 + +// +//STATUS_GENERAL_ERROR +// This is a general error code used for errors that do not require a specific +// code. +#define STATUS_GENERAL_ERROR 0xA1 + +// +//STATUS_SMB_EMPTY +// The smbus slave circular buffer does not contain any smbus transactions data. +#define STATUS_SMB_EMPTY 0xA2 + +// +//STATUS_SMB_NO_MORE_ENTRIES +// The smbus slave has reached its maximal number of registered transactions. +// New transactions can not be added until the removal of one of the current +// registered ones. +#define STATUS_SMB_NO_MORE_ENTRIES 0xA3 + +// +//STATUS_BUS_ERROR +// Generic error code for bus errors. Common cause could be losing arbitration +// on a multi-mastered bus. +#define STATUS_BUS_ERROR 0xA4 + +// +//STATUS_IMAGE_INVALID +// The FW Update image content is invalid. +#define STATUS_IMAGE_INVALID 0xA5 + +// +//STATUS_UPDATE_AUTH_FAILED +// The FW Update image authentication failed. +#define STATUS_UPDATE_AUTH_FAILED 0xA6 + +// +//STATUS_UPDATE_ALLOWED +// Used in the policy manager to indicate whether a policy can be updated at +// the time of this request. +#define STATUS_UPDATE_ALLOWED 0xA7 + +// +//STATUS_UPDATE_NOT_ALLOWED +// Used in the policy manager to indicate that a policy cannot be updated at +// the time of this request. +#define STATUS_UPDATE_NOT_ALLOWED 0xA8 + +// +//STATUS_LOCKED +// Indicates policy element has been already locked and cannot be updated. +#define STATUS_LOCKED 0xA9 + +// +//STATUS_NOT_INITIALIZED +// Indicates that SDM core is not initialized +#define STATUS_NOT_INITIALIZED 0xAA //REQUIRES COORDINATION!!! + +// +//STATUS_END_OF_FILE +// Indicates that EOF is reached while accessing a file +#define STATUS_END_OF_FILE 0xAB //REQUIRES COORDINATION!!! + +// +//STATUS_NO_STORAGE_AVAILABLE +// Indicates policy element could not be stored in the NVAR. +#define STATUS_NO_STORAGE_AVAILABLE 0xB0 + +// +//STATUS_LOCKING_NOT_ALLOWED +// Indicates policy element cannot be locked. +#define STATUS_LOCKING_NOT_ALLOWED 0xB1 + +// +//STATUS_UNKNOWN_LAN_FUSE_CAPS +// Indicates a unknown capability of the LAN device is being set. +#define STATUS_UNKNOWN_LAN_FUSE_CAPS 0xB2 + +// +//STATUS_INVALID_FEATURE_ID +// Indicates an invalid feature ID. +#define STATUS_INVALID_FEATURE_ID 0xB3 + +// +//STATUS_PET_TRANSMIT_DISABLED +// The transmission of pet packets is disabled. +#define STATUS_PET_TRANSMIT_DISABLED 0xB4 + +// STATUS_MAX_KERB_DOMAIN_REACHED +// indicates that in the kerberos ACL there are users from MAX DOMAINS (4). +#define STATUS_MAX_KERB_DOMAIN_REACHED 0xB5 + +// STATUS_UPDATE_MISMATCH_HW_SKU +// Indicates that there is a mismatch between the current HW SKU and the +// one in the new image. +#define STATUS_UPDATE_MISMATCH_HW_SKU 0xB6 + +// STATUS_UPDATE_MISMATCH_FW_SKU +// Indicates that there is a mismatch between the current FW SKU and the +// one in the new image. +#define STATUS_UPDATE_MISMATCH_FW_SKU 0xB7 + +// STATUS_UPDATE_MISMATCH_VERSION +// Indicates that there is a mismatch between the current FW version and the +// one in the new image. +#define STATUS_UPDATE_MISMATCH_VERSION 0xB8 + +// STATUS_EVENT_DISABLED_CONFIG +// This wake event is configured to be disabled (via MEBx setup or remote +// configuration). +#define STATUS_EVENT_DISABLED_CONFIG 0xB9 + +// STATUS_NOT_REGISTERED +// Caller is trying to use an interface that requires registration, but the +// registration process has not been completed. +#define STATUS_NOT_REGISTERED 0xBA + + +// STATUS_INVALID_EVENT +// Caller is trying to use a wake event code which is invalid +#define STATUS_INVALID_EVENT 0xBB + +// STATUS_INVALID_EVENT +// Caller is trying to use an event context which is invalid +#define STATUS_BAD_CONTEXT 0xBC + + +// +//STATUS_NET_RESTART_NEEDED +// The network stack need restart to continue working. +#define STATUS_NET_RESTART_NEEDED 0xBD + +// +//STATUS_OUT_OF_MEMORY +// This error can be returned for the following reasons: +// 1.Attempt to allocate memory and no memory is available +// 2.Attempt to free a memory block on which a thread is suspended +// NOTE: This value is the same a as STATUS_START_ERROR. +// +#define STATUS_OUT_OF_MEMORY 0xBE + + +// +//STATUS_COUNTER_ROLLOVER +// This error can be returned by MC_PROTOCOL IncrementCounter() +// if given monotonic counter reaches maximum value. +// Along with error, counter will be initialized with value "1" +// +// The value will also be returned by TIME_PROTOCOL GetPRTC() +// if the PRTC rolls over +#define STATUS_COUNTER_ROLLOVER 0xBF + + +// +// BLOB SERVICE SPECIFIC FAILURES +// +// STATUS_BLOB_INTEGRITY_FAILED +// STATUS_BLOB_CONFIDENTIALITY_FAILED +// STATUS_BLOB_AR_FAILED +#define STATUS_BLOB_INTEGRITY_FAILED 0xC0 +#define STATUS_BLOB_CONFIDENTIALITY_FAILED 0xC1 +#define STATUS_BLOB_AR_FAILED 0xC2 + + + +//STATUS_PROCESSING +// Caller is asking for process result that is not already finished +#define STATUS_PROCESSING 0xC3 + +//STATUS_REGISTERED +// Caller registered for something that itself or others already did +#define STATUS_REGISTERED 0xC4 +// +//STATUS_EAC_NOT_PERMITTED +// This error can be returned for the following reasons: +// 1.Attempt to enable EAC when sign certificate is not set + +// +#define STATUS_EAC_NOT_PERMITTED 0xC5 + +// +//STATUS_EAC_NO_ASSOCIATION +// This error can be returned for the following reasons: +// 1.Attempt to receive a posture or posture hash sign certificate is not set + +// +#define STATUS_EAC_NO_ASSOCIATION 0xC6 + +// +//STATUS_AUDIT_FAIL +// This error can be returned when these conditions are met: +// 1. The action should be logged to the Audit Log +// 2. The event was defined as critical +// 3. The Audit Log is enabled +// 4. Either: +// a. The Audit Log is currently Locked +// b. The storage for the Audit Log is full + +// +#define STATUS_AUDIT_FAIL 0xC7 + +#define STATUS_DUPLICATED 0xC8 + +// +//STATUS_IPP_INTERNAL_ERROR +// This error can bb returned in case of internal IPP function failed. +#define STATUS_IPP_INTERNAL_ERROR 0xC9 + +// +//STATUS_IPP_CORRUPTED_KEY +// This error can be returned when trying to load or validate corrupted RSA key +// using the IPP stack. +// Can be returned RsaEncryptDecrypt and RsaValidateKey functions. +#define STATUS_IPP_CORRUPTED_KEY 0xCA + +// +//STATUS_IPP_DATA_NOT_ALIGNED +// This error can be returned when trying to load, create or validate RSA key using the +// IPP stack, and the data is not aligned. +// Can be returned RsaGenerateKey, RsaEncryptDecrypt and RsaValidateKey functions. +#define STATUS_IPP_DATA_NOT_ALIGNED 0xCB + +// +//STATUS_IPP_OPERATION_ABORTED +// This error will be returned if the IPP aborted key generation before completion. +#define STATUS_IPP_OPERATION_ABORTED 0xCC + +// +//STATUS_IPP_CACHE_CONVERTION_FAILED +// This error can be returned if the TRAMD-Cache conversion failed. +#define STATUS_IPP_CACHE_CONVERTION_FAILED 0xCD + +// +//STATUS_IPP_EXPONENT_CHANGED +// This error will be returned if the IPP decided to use differnt exponent (E) +// than the one the caller supplied. +#define STATUS_IPP_EXPONENT_CHANGED 0xCE + +// STATUS_PERMIT_EXPIRED +// iCLS Permit has expired +#define STATUS_PERMIT_EXPIRED 0xCF + +// STATUS_PERMIT_RESET_REQUIRED +// iCLS permit is invalid in some way (for example expired) +// and HW fuses are overided by permit still +#define STATUS_PERMIT_RESET_REQUIRED 0xD0 + +// STATUS_CLOSED_BY_HOST +// HECI will return this in the event that AddBuffer call is failing because +// the connection is in a close pending status. +// This will indicate that freeing the SendBufferQ and BufferQ is not permitted at +// this time and the client should wait for a HIE_CLOSED message to cleanup HECI_CONNECTION. +#define STATUS_CLOSED_BY_HOST 0xD1 + + +// STATUS_DISABLED_BY_POLICY +// This error will be returned if the call is blocked by previous defined policy +#define STATUS_DISABLED_BY_POLICY 0xD2 + +//STATUS_INVALID_COMP_HANDLE +// The provided component handle does not exist. +// +#define STATUS_INVALID_COMP_HANDLE 0xD3 + +// +//Status Codes used by state manager to indicate ME Database status +//and general Client/Daemon registration problems in state manager +//that prohibit the Daemon from returning more exact status. +// + +// +//STATUS_ALREADY_REGISTERED +// This error is used to indicate if a Daemon is already +// registered with state manager. +#define STATUS_ALREADY_REGISTERED 0xD4 + +// +//STATUS_DATABASE_IN_USE +// This error is used to indicate if a ME Database is currently in +// use when a delete is called on it. +#define STATUS_DATABASE_IN_USE 0xD5 + +// +//STATUS_ENTRY_IN_USE +// This error is used to indicate if an entry in a ME Database is +// currently in use when a release is called on it. +#define STATUS_ENTRY_IN_USE 0xD6 + +// +//STATUS_UNABLE_TO_REGISTER +// This error is used to indicate that a Daemon cannot register +// with state manager. +#define STATUS_UNABLE_TO_REGISTER 0xD7 + +// +// STATUS_TLB_ENTRY_NOT_FOUND +// This error indicates that a free TLB entry or the specified TLB entry +// could not be found. +// +#define STATUS_TLB_ENTRY_NOT_FOUND 0xD8 + +// +//STATUS_UNABLE_TO_UNREGISTER +// This error code is used to indicate that a Daemon cannot +// unregister with the state manager. +#define STATUS_UNABLE_TO_UNREGISTER 0xD9 + +// +//STATUS_TIMER_VALUE_NOT_SET +// Error used by PRTC to indicate the alarm value +// has not been set prior to enabling the alarm. +#define STATUS_TIMER_VALUE_NOT_SET 0xDA + +// +//STATUS_ICV_CHECK_ERROR +// HW reported an ICV check failure +#define STATUS_ICV_CHECK_ERROR 0xDB + +// STATUS_SUCCESS_WITH_ERRORS +// This error will be returned if the opration completed but had some errors (e,eg Transfer AHCI for DT) +// It is shared between Danbury components +#define STATUS_SUCCESS_WITH_ERRORS 0xDC + +// STATUS_SUCCESS_HOST_RESET_REQUIRED +// This status will be returned by FwUpdateMgr after successfully updating FW +// if Danbury is enabled +#define STATUS_SUCCESS_HOST_RESET_REQUIRED 0xDD + +// STATUS_FIPS_FAILURE +// This status will be returned by when FIPS self-tests fail +#define STATUS_FIPS_FAILURE 0xDE + +//STATUS_PRIVILEGE_CHECK +// Privileged component access +#define STATUS_PRIVILEGE_CHECK 0xDF + +// STATUS_INCOMPLETE +// This error indicates that the operation is incomplete +#define STATUS_INCOMPLETE 0xE0 + +// STATUS_RETRY +// This error indicates that the operation is being retried or needs to be retried +#define STATUS_RETRY 0xE1 + +#define STATUS_NOT_RUN 0xE2 + +#define STATUS_NOT_IMPLEMENTED 0xE3 + + +#define STATUS_INVALID_INDEX 0xE4 +#define STATUS_SLOT_IN_USE 0xE5 +#define STATUS_SLOT_EMPTY 0xE6 + +// STATUS_OVERRIDDEN +// This error indicates that the operation can't be performed because +// it was overridden by some other logic/request +#define STATUS_OVERRIDDEN 0xE7 + +//STATUS_PERMIT_IS_DEACTIVE +// iCLS Permit has been deactivated +#define STATUS_PERMIT_IS_DEACTIVE 0xF0 + +//Return this if it is a Patsburg chipset +#define STATUS_UNKNOWN_CPUID 0xF1 + +#define STATUS_CRC_ERROR 0xF2 + +#if 1 +//STATUS for task isolation +#define STATUS_HECI_CONNECTION_ACCEPT 0xF3 +#define STATUS_HECI_CONNECTION_REJECT 0xF4 +#define STATUS_RETURN_NOT_AVAILABLE 0xF5 +#endif +//STATUS for PG +#define STATUS_PG_ENTRY_IN_PROGRESS 0xF6 + +// Intel Secret Key Unavailable +// RCR CCG0100111613 +#define STATUS_BLOB_UNAVAILABLE 0xF6 + +#define STATUS_FPF_READ_MISMATCH 0xF7 +#define STATUS_FPF_ARRAY_FULL 0xF8 +#define STATUS_FPF_WRITE_FAILED 0xF9 +#define STATUS_FPF_FILE_INVALID 0xFA +#define STATUS_FPF_FILE_FULL 0xFB +#define STATUS_FPF_FILE_LOCKED 0xFC +#define STATUS_FPF_NOT_AVAILABLE 0xFD +#define STATUS_FPF_BUSY 0xFE // FPF write currently in progress +#define STATUS_FPF_FATAL_ERROR 0xFF // Fatal error, fuses are no longer valid (bad PCH) +#define STATUS_FPF_FILE_EMPTY 0x100 // File has not been written to +#define STATUS_FPF_ALREADY_COMMITTED 0x101 +#define STATUS_FPF_COMMIT_FAILED_EOM_NOT_SET 0x102 +#define STATUS_FPF_INVALID_SB_VALUES 0x103 +#define STATUS_FPF_NOT_COMMITTED 0x104 +#define STATUS_FPF_NVAR_MISMATCH 0x105 +#define STATUS_FPF_FILE_UNLOCKED 0x106 +#define STATUS_FPF_COMMIT_NOT_ALLOWED 0x107 +#define STATUS_FPF_CANARY_FAILURE 0x108 +#define STATUS_FPF_SENSE_FAILED 0x109 +#if 1 +// STATUS for FWU kernel between 0x200 to 0x2FF +#define FW_UPDATE_STATUS UINT32 + +#define NO_UPDATE 0 +#define STATUS_UPDATE_SUCCESS 0x0 // Zero for sucess anything else is consider failures +#define STATUS_UPDATE_IMAGE_INVALID 0x201 +#define STATUS_UPDATE_INTEGRITY_FAILURE 0x202 +#define STATUS_UPDATE_SKU_MISMATCH 0x203 +#define STATUS_UPDATE_FW_VERSION_MISMATCH 0x204 +#define STATUS_UPDATE_GENERAL_FAILURE 0x205 +#define STATUS_UPDATE_OUT_OF_RESOURCES 0x206 +#define STATUS_UPDATE_AUDIT_POLICY_FAILURE 0x207 +#define STATUS_UPDATE_ERROR_CREATING_FT 0x208 +#define STATUS_UPDATE_SAL_NOTIFICATION_ERROR 0x209 +#define STATUS_UPDATE_IMG_LOADING 0x20A +#define STATUS_UPDATE_IMG_AUTHENTICATING 0x20B +#define STATUS_UPDATE_IMG_PROCESSING 0x20C +#define STATUS_UPDATE_CREATING_FT 0x20D +#define STATUS_UPDATE_UPDATING_CODE 0x20E +#define STATUS_UPDATE_UPDATING_NFT 0x20F +#define STATUS_UPDATE_FLASH_CODE_PARTITION_INVALID 0x210 +#define STATUS_UPDATE_FLASH_NFT_PARTITION_INVALID 0x211 +#define STATUS_UPDATE_ILLEGAL_IMAGE_LENGTH 0x212 +#define STATUS_UPDATE_NOT_READY 0x213 + +#define STATUS_UPDATE_HOST_RESET_REQUIRED 0x214 +#define STATUS_INVALID_GLUT 0x215 +#define STATUS_INVALID_OEM_ID 0x216 + +// New for CPT add below here +#define STATUS_UPDATE_IMAGE_BLACKLISTED 0x217 +#define STATUS_UPDATE_IMAGE_VERSION_HISTORY_CHECK_FAILURE 0x218 +#define STATUS_UPDATE_DOWNGRADE_VETOED 0x219 +#define STATUS_UPDATE_WRITE_FILE_FAILURE 0x22A +#define STATUS_UPDATE_READ_FILE_FAILURE 0x22B +#define STATUS_UPDATE_DELETE_FILE_FAILURE 0x22C +#define STATUS_UPDATE_PARTITION_LAYOUT_NOT_COMPATIBLE 0x22D // FW Update is not possible due to partition move +#define STATUS_DOWNGRADE_NOT_ALLOWED_DATA_MISMATCHED 0x22E +#define STATUS_UPDATE_FW_UPDATE_IS_DISABLED 0x22F +#define STATUS_UPDATE_PASSWORD_NOT_MATCHED 0x230 +#define STATUS_UPDATE_PASSWORD_EXCEED_MAXIMUM_RETRY 0x231 +#define STATUS_UPDATE_INRECOVERY_MODE_RESTRICT_UPDATE_TO_ATTEMPTED_VERSION 0x232 // They have to update with the same image that they started with. + + +// New for Partial FW update +#define STATUS_UPDATE_UPV_VERSION_MISMATCHED 0x233 // UPV version mismatched update is not allow +#define STATUS_UPDATE_INSTID_IS_NOT_EXPECTED_ID 0x234 // Reject update, instance ID sent is not one of expected ID +#define STATUS_UPDATE_INFO_NOT_AVAILABLE 0x235 // While in the middle of update IPU attrib info will bot be available +#define STATUS_UPDATE_REJ_IPU_FULL_UPDATE_NEEDED 0x236 // Can't do IPU update while we are in Full recovery mode. +#define STATUS_UPDATE_IPU_NAMEID_NOT_FOUND 0x237 // IPU name not found when compare with UPV extension + +#define STATUS_UPDATE_RESTORE_POINT_INVALID 0x238 +#define STATUS_UPDATE_RESTORE_POINT_VALID_BUT_NOT_LATEST 0x239 +#define STATUS_UPDATE_RESTORE_POINT_OPERATION_NOT_ALLOWED 0x23A +#define STATUS_DOWNGRADE_NOT_ALLOWED_SVN_RESTRICTION 0x23B +#define STATUS_DOWNGRADE_NOT_ALLOWED_VCN_RESTRICTION 0x23C +#define STATUS_INVALID_SVN 0x23D +#define STATUS_UPDATE_OUT_OF_SVN_RESOURCES 0x23E +#define STATUS_UPDATE_REJECT_RESTORE_POINT_REQUEST_FLASH_IN_RECOVERY 0x23F +#define STATUS_UPDATE_REJECTED_BY_UPDATE_POLICY 0x240 +#define STATUS_UPDATE_REJECTED_INCOMPATIBLE_TOOL_USAGE 0x241 +#define STATUS_UPDATE_REJECTED_CROSSPOINT_UPDATE_NOT_ALLOWED 0x242 +#define STATUS_UPDATE_REJECTED_CROSSHOTFIX_UPDATE_NOT_ALLOWED 0x243 +#define STATUS_UPDATE_REJECTED_CURRENT_FW_NOT_ELIGIBLE_FOR_UPDATE 0x244 +#define STATUS_UPDATE_REJECTED_WRONG_UPDATE_OPERATION 0x245 +#define STATUS_UPDATE_REJECTED_WRONG_UPDATE_IMAGE_FOUND 0x246 +#define STATUS_UPDATE_REJECTED_IFR_UPDATE_NOT_ALLOWED 0x247 +#define STATUS_UPDATE_FAILURE_OCCURRED_DURING_ROLLBACK 0x248 + +//......................................................................... +//......................................................................... // Reserve for FWU usage +#define STATUS_UPDATE_LAST_STATUS_CODE 0x2FF + +// Hotham-specific error codes +#define STATUS_HTM_HOST_NOT_RDY 0x300 +#define STATUS_HTM_INTERNAL_ERROR 0x301 +#define STATUS_HTM_REQ_IN_PROGRESS 0x302 +#define STATUS_HTM_RESP_IN_PROGRESS 0x303 +#define STATUS_HTM_INVALID_FRAGMENT 0x304 +#define STATUS_HTM_RESP_NONE_ACTIVE 0x305 +#define STATUS_HTM_NOT_CONNECTED 0x306 +//... +//... Reserved for future use +#define STATUS_HTM_LAST_STATUS_CODE 0x31F + + + + +// means internal FW operation errors +//#define STATUS_UPDATE_UNKNOWN = 0xFFFFFFFF + + +#endif + + +#endif // _ME_STATUS_H_ diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.c b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.c new file mode 100644 index 0000000..d5caea8 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.c @@ -0,0 +1,701 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2015, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** +#include <Token.h> +#include <AmiDxeLib.h> +#include <Protocol\Heci\Heci.h> +#include <Protocol\PchPlatformPolicy\PchPlatformPolicy.h> +#include <Protocol\PchReset\PchReset.h> +#include <Protocol\MeBiosPayloadData\MeBiosPayloadData.h> +#include <Protocol\Decompress.h> +#include <Protocol\GuidedSectionExtraction.h> +#include <Protocol\ConsoleControl.h> +#include <Protocol\AMIPostMgr.h> + +#ifdef _HECI_PROTOCOL_H +//Broadwell RC +#include <Library\MeDxeLib.h> +#include <Library\MeChipsetLib.h> +#else +//Haswell RC +#undef EFI_PROTOCOL_DEFINITION +#define EFI_STRINGIZE(a) #a +#define EFI_PROTOCOL_DEFINITION(a) EFI_STRINGIZE (Protocol/a/a.h) +#include "HeciMsgLib.h" +#include "MeChipsetLib.h" +#endif + +#include <Guid\FirmwareFileSystem2.h> + + +#include "IntelLib\FWUpdateLib.h" +#include "IntelLib\me_status.h" +#include "MeFwUpdLclProtocol.h" +#include "EdkIICommon.h" + +_UUID mOemId = {0x00000000, 0x0000, 0x0000, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + +// Last Reset Types +#define NORESET 0 +#define HOSTRESET 1 +#define MERESET 2 +#define GLOBALRESET 3 + +// Get Interface +#define FW_UPDATE_DISABLED 0 +#define FW_UPDATE_ENABLED 1 +#define FW_UPDATE_PASSWORD_PROTECTED 2 + +#ifdef _HECI_PROTOCOL_H +//Broadwell RC +typedef struct _PCH_PLATFORM_POLICY PRIVATE_PCH_PLATFORM_POLICY_PROTOCOL; +#else +//Haswell RC +typedef struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL PRIVATE_PCH_PLATFORM_POLICY_PROTOCOL; +#define HECI_PROTOCOL EFI_HECI_PROTOCOL +#define MBP_DATA_PROTOCOL DXE_MBP_DATA_PROTOCOL +#define PCH_PLATFORM_POLICY_PROTOCOL_GUID DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID +#endif + +#ifndef MAX_ADDRESS +#define MAX_ADDRESS 0xFFFFFFFF +#endif +#define ME_UPD_LCL_SIGNATURE SIGNATURE_32 ('_', 'M', 'U', 'L') + +EFI_GUID mAmiGlobalVariableGuid = AMI_GLOBAL_VARIABLE_GUID; + +EFI_GUID mEfiHeciProtocolGuid = HECI_PROTOCOL_GUID; +EFI_GUID mMeFwUpdLclProtocolGuid = ME_FW_UPD_LOCAL_PROTOCOL_GUID; +EFI_GUID mPchPlatformPolicyProtocolGuid = PCH_PLATFORM_POLICY_PROTOCOL_GUID; +EFI_GUID mPchResetProtocolGuid = PCH_RESET_PROTOCOL_GUID; +EFI_GUID mMeBiosPayloadDataProtocolGuid = ME_BIOS_PAYLOAD_DATA_PROTOCOL_GUID; +EFI_GUID mConOutStartedProtocolGuid = CONSOLE_OUT_DEVICES_STARTED_PROTOCOL_GUID; + +EFI_GUID mMeRegionFfsGuid = \ +{0xDE90FFA8, 0xB985, 0x4575, 0xAB, 0x8D, 0xAD, 0xE5, 0x2C, 0x36, 0x2C, 0xA3}; + +ME_FW_UPDATE_LOCAL_PROTOCOL *mMeFwUpdateLclProtocol = NULL; +PRIVATE_PCH_PLATFORM_POLICY_PROTOCOL *mPchPlatformPolicy = NULL; + +EFI_BOOT_SERVICES *BS = NULL; +EFI_RESET_SYSTEM mSavedResetSystem = NULL; + +ME_FW_UPD_VERSION mMeFwImgVersion[] = ME_FW_IMAGE_VERSION; + +void _fltused() +{ +} + +VOID * +SetMem ( + OUT VOID *Buffer, + IN UINTN Length, + IN UINT8 Value +) +{ + MemSet( Buffer, Length, Value); + return Buffer; +} + +INTN +EFIAPI +CompareMem ( + IN VOID *DestinationBuffer, + IN VOID *SourceBuffer, + IN UINTN Length + ) +{ + return MemCmp( DestinationBuffer, SourceBuffer, Length ); +} + +VOID* AllocatePool( + IN UINTN AllocationSize) +{ + VOID *p; + EFI_STATUS Status; + + Status = BS->AllocatePool(EfiBootServicesData, AllocationSize, &p); + return (EFI_ERROR(Status)) ? NULL : p; +} + +VOID FreePool( + IN VOID *Buffer) +{ + BS->FreePool(Buffer); +} + +VOID * +EFIAPI +CopyMem ( + OUT VOID *Destination, + IN VOID *Source, + IN UINTN Length + ) +{ + MemCpy( Destination, Source, Length); + return Destination; +} + +VOID * +EFIAPI +ZeroMem ( + OUT VOID *Buffer, + IN UINTN Length + ) +{ + ASSERT (!(Buffer == NULL && Length > 0)); + ASSERT (Length <= (MAX_ADDRESS - (UINTN)Buffer + 1)); + return SetMem (Buffer, Length, 0); +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MeUpdPlatformUnlock +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MeUpdPlatformUnlock ( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This, + IN UINT32 UnlockType +) +{ + if( mPchPlatformPolicy != NULL ) +#ifdef _HECI_PROTOCOL_H + //Broadwell RC + mPchPlatformPolicy->LockDownConfig.BiosLock = 0; +#else + //Haswell RC + mPchPlatformPolicy->LockDownConfig->BiosLock = 0; +#endif + + // Patch disabling IDE_R if ME is Disabled for system assert if DEBUG_MODE is ON. + // The IDE-R device will be disabled if ME is in Normal state (HeciInit.c), + // Here ME is in ME_MODE_SECOVER, the IDE-R is active and could cause assert error + // in IdeBus.Start proceduce. + MeDeviceControl( IDER, Disabled ); + + return EFI_SUCCESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MeUpdPlatformReset +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MeUpdPlatformReset ( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This, + IN EFI_RESET_TYPE ResetType +) +{ + EFI_STATUS Status; + PCH_RESET_PROTOCOL *PchReset; + // Reset system to re-start ME FW.. + Status = pBS->LocateProtocol( + &mPchResetProtocolGuid, + NULL, + (VOID**)&PchReset); + if( !EFI_ERROR(Status) ) + PchReset->Reset(PchReset, EfiResetCold); + + return EFI_SUCCESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MeCheckFwState +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MeCheckFwState( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This, + IN ME_FW_STATE MeFwState +) +{ + EFI_STATUS Status; + UINT32 MeMode; + HECI_PROTOCOL *Heci = NULL; + + Status = pBS->LocateProtocol( + &mEfiHeciProtocolGuid, NULL, (VOID**)&Heci); + if (EFI_ERROR(Status)) return EFI_UNSUPPORTED; + Status = Heci->GetMeMode (&MeMode); + if (EFI_ERROR(Status)) return EFI_UNSUPPORTED; + if (((MeFwState == MeModeNormal) && (MeMode == ME_MODE_NORMAL)) || \ + ((MeFwState == MeModeDebug) && (MeMode == ME_MODE_DEBUG)) || \ + ((MeFwState == MeModeTempDisabled) && (MeMode == ME_MODE_TEMP_DISABLED)) || \ + ((MeFwState == MeModeSecOver) && (MeMode == ME_MODE_SECOVER)) || \ + ((MeFwState == MeModeFailed) && (MeMode == ME_MODE_FAILED))) return EFI_SUCCESS; + return EFI_UNSUPPORTED; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MeGetFwVersion +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MeGetFwVersion ( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This, + IN OUT ME_FW_UPD_VERSION *MeFwVersion +) +{ + EFI_STATUS Status; + MBP_DATA_PROTOCOL *MbpData; + + // Get ME Firmware Version from MBP, then save for future used. + Status = pBS->LocateProtocol ( \ + &mMeBiosPayloadDataProtocolGuid, NULL, (VOID **)&MbpData); + if (!EFI_ERROR (Status)) { + MemCpy(MeFwVersion, \ + &MbpData->MeBiosPayload.FwVersionName, sizeof(ME_FW_UPD_VERSION)); + } + return Status; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MeUpdHmrfpoEnable +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MeUpdHmrfpoEnable ( + ME_FW_UPDATE_LOCAL_PROTOCOL *This +) +{ + EFI_STATUS Status; + UINT8 HeciHmrfpoEnableResult; + HeciHmrfpoEnableResult = HMRFPO_ENABLE_UNKNOWN_FAILURE; + Status = HeciHmrfpoEnable (0, &HeciHmrfpoEnableResult); + if ((Status == EFI_SUCCESS) && (HeciHmrfpoEnableResult == HMRFPO_ENABLE_SUCCESS)) { + /// (A6) The BIOS sends the GLOBAL RESET MEI message + HeciSendCbmResetRequest (CBM_RR_REQ_ORIGIN_BIOS_POST, CBM_HRR_GLOBAL_RESET); + MeUpdPlatformReset(This, EfiResetCold); + //CpuDeadLoop(); + while(1); + } + return Status; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: DisplaySendStatus +// +// Description: +// +// Input: +// float BytesSent +// float BytestobeSent +// Output: +// None +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +void +DisplaySendStatus ( + float BytesSent, + float BytestobeSent + ) +{ +// float value = (BytesSent / BytestobeSent) * 100; +// UINT32 pValue = (UINT32)value; +// +// if (pValue != 100) +// { +// DEBUG ((D_ERROR, "Sending the update image to FW for verification: [ %d%% ]\r", pValue)); +// } +// else +// { +// DEBUG ((D_ERROR, "Sending the update image to FW for verification: [ COMPLETE ] \n")); +// } +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: FwUpdLclFunc +// +// Description: The main function to update ME firmware. +// It will call Intel's API to update ME firmware. +// +// Input: +// IN ME_FW_UPDATE_LOCAL_PROTOCOL *This +// IN UINT8 *FileBuffer +// IN UINTN FileLength +// Output: +// None +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +FwUpdLclFunc ( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This, + IN UINT8 *FileBuffer, + IN UINTN FileLength +) +{ + EFI_STATUS Status; + UINTN ImageLength = 0; + UINT8 *ImageBuffer = NULL; + UPDATE_FLAGS_LIB update_flags; + CHAR8 Password[9]; + UINT32 FWUpdateStatus; + UINT32 QueryStatus; + UINT32 UpdateStatus = 0; + UINT32 TotalStages = 0; + UINT32 PercentWritten = 0; + UINT32 LastStatus; + UINT32 LastResetType; + UINT16 Interfaces; + UINT8 Symbol; + UINT32 Index; + UINT32 CheckPolicyStatus = 0; + BOOLEAN AllowSV = FALSE; + UPDATE_TYPE UpdType; + VersionLib Ver; + VOID *DisplayHandle; + AMI_POST_MGR_KEY OutKey; + + BS = pBS; + + ImageBuffer = FileBuffer; + ImageLength = FileLength; + + ZeroMem( &update_flags, sizeof(UPDATE_FLAGS_LIB) ); + + Status = GetLastStatus( &LastStatus ); + if( EFI_ERROR(Status) ) + { + return Status; + } + + if( LastStatus == STATUS_UPDATE_HOST_RESET_REQUIRED ) + { + //DEBUG ((D_ERROR, "PLEASE REBOOT YOUR SYSTEM. ")); + //DEBUG ((D_ERROR, "Firmware update cannot be initiated without a reboot.\n")); + return EFI_SUCCESS; + } + + if( IsUpdateStatusPending(LastStatus) ) + { + //DEBUG ((D_ERROR, "Firmware Update operation not initiated ")); + //DEBUG ((D_ERROR, "because a firmware update is already in progress\n")); + return EFI_SUCCESS; + } + + Status = GetLastUpdateResetType( &LastResetType ); + if( EFI_ERROR(Status) ) return Status; + switch( LastResetType ) + { + case HOSTRESET: + case GLOBALRESET: + //DEBUG ((D_ERROR, "PLEASE REBOOT YOUR SYSTEM. ")); + //DEBUG ((D_ERROR, "Firmware update cannot be initiated without a reboot.\n")); + return EFI_SUCCESS; + break; + default: + break; + } + + Status = GetInterfaces( &Interfaces ); + if( EFI_ERROR(Status) ) return Status; + switch( Interfaces ) + { + case FW_UPDATE_DISABLED: + //DEBUG ((D_ERROR, "Local FWUpdate is Disabled\n")); + return EFI_SUCCESS; + case FW_UPDATE_PASSWORD_PROTECTED: + //DEBUG ((D_ERROR, "Local FWUpdate is Password Protected\n")); + break; + case FW_UPDATE_ENABLED: + break; + default: + break; + } + + //DEBUG ((D_ERROR, "Checking firmware parameters...\n")); + + CheckPolicyStatus = CheckPolicyBuffer( (char *)ImageBuffer, + (INT32)ImageLength, + (INT32)AllowSV, + &UpdType, + &Ver ); + switch( UpdType ) + { + case DOWNGRADE_SUCCESS: + case SAMEVERSION_SUCCESS: + case UPGRADE_SUCCESS: + break; + + case DOWNGRADE_FAILURE: + //DEBUG ((D_ERROR, "FW Update downgrade not allowed\n")); + return EFI_SUCCESS; + break; + + case SAMEVERSION_FAILURE: + //DEBUG ((D_ERROR, "FW Update same version not allowed, specify /s on command line\n")); + return EFI_SUCCESS; + + default: + break; + } + + ZeroMem( &Password, sizeof(Password) ); + + if( This->AmiPostMgr != NULL ) + { + This->AmiPostMgr->DisplayProgress( + AMI_PROGRESS_BOX_INIT, + L"ME FW update", + L"Flash New ME Firmware", + NULL, + 0, + &DisplayHandle, + &OutKey ); + } + + FWUpdateStatus = FwUpdateFullBuffer( + (char*)ImageBuffer, + (unsigned int)ImageLength, + Password, + 0, + FWU_ENV_MANUFACTURING, + mOemId, + update_flags, + &DisplaySendStatus ); + if( FWUpdateStatus != FWU_ERROR_SUCCESS ) + { + //DEBUG ((D_ERROR, "FWUpdateStatus: %x\n", FWUpdateStatus)); + //if( ImageBuffer ) + // FreePool( ImageBuffer ); + return EFI_SUCCESS; + } + + //if( ImageBuffer ) + //{ + // Status = FreePool( ImageBuffer ); + //} + + Index = 0; + do + { + Symbol = (++Index % 2 == 0) ? '|':'-'; + + QueryStatus = FWUpdate_QueryStatus_Get_Response( + &UpdateStatus, + &TotalStages, + &PercentWritten, + &LastStatus, + &LastResetType ); + if( QueryStatus == FWU_ERROR_SUCCESS ) + { + //DEBUG ((D_ERROR, "FW Update: [ %d%% (Stage: %d of %d) (%c)]\r", PercentWritten, UpdateStatus, TotalStages, Symbol)); + if( This->AmiPostMgr != NULL ) + { + This->AmiPostMgr->DisplayProgress( + AMI_PROGRESS_BOX_UPDATE, + L"ME FW update", + L"Flash New ME Firmware", + NULL, + PercentWritten, + &DisplayHandle, + &OutKey ); + } + } + else if ( LastStatus != STATUS_UPDATE_NOT_READY ) + { + //DEBUG ((D_ERROR, "\nLastStatus: %x\n", LastStatus)); + break; + } + BS->Stall(100000); + } while( (PercentWritten != 100) && (QueryStatus == FWU_ERROR_SUCCESS) ); + + if( This->AmiPostMgr != NULL ) + { + This->AmiPostMgr->DisplayProgress( + AMI_PROGRESS_BOX_CLOSE, + L"ME FW update", + L"Flash New ME Firmware", + NULL, + 0, + &DisplayHandle, + &OutKey ); + } + + return EFI_SUCCESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MeFwUpdateProtocolEvent +// +// Description: The driver entry +// +// Input: +// +// Output: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MeFwUpdateProtocolEvent ( + IN EFI_EVENT Event, + IN EFI_HANDLE ImageHandle + ) +{ + UINT32 Dummy = 0; + UINTN VariableSize = sizeof(UINT8); + EFI_STATUS Status; + ME_FW_UPD_VERSION MeFwVersion; + + if (mMeFwImgVersion->MajorVersion != 0) { + Status = MeGetFwVersion(mMeFwUpdateLclProtocol, &MeFwVersion); + if (!EFI_ERROR (Status)) { + VariableSize = sizeof(ME_FW_UPD_VERSION); + // Set MbpMeFwVersion to "NV+BS", because MBP could be not available if + // Capsule Update mode. + pRS->SetVariable(L"MbpMeFwVersion", \ + &mAmiGlobalVariableGuid, \ + EFI_VARIABLE_NON_VOLATILE | \ + EFI_VARIABLE_BOOTSERVICE_ACCESS, \ + sizeof(ME_FW_UPD_VERSION), \ + &MeFwVersion); + } + } + // Check "MeAutoUpdateReq" variable if ME Auto Update is requested. + VariableSize = sizeof(UINT32); + Status = pRS->GetVariable(L"MeAutoUpdateReq", \ + &mAmiGlobalVariableGuid, NULL, &VariableSize, &Dummy); + if (EFI_ERROR(Status)) return EFI_SUCCESS; + + return EFI_SUCCESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MEFwUpdLclEntry +// +// Description: The driver entry +// +// Input: +// IN EFI_HANDLE ImageHandle +// OUT EFI_SYSTEM_TABLE *SystemTable +// Output: +// None +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MEFwUpdLclEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINT32 Dummy; + UINTN VariableSize = sizeof(UINT32); + EFI_HANDLE pHandle = NULL; + EFI_STATUS Status; + + InitAmiLib( ImageHandle, SystemTable ); + + Status = pBS->LocateProtocol( + &mPchPlatformPolicyProtocolGuid, + NULL, + &mPchPlatformPolicy ); + if( EFI_ERROR(Status) ) return EFI_SUCCESS; + + //Prepare ME firmware update local protocol + Status = pBS->AllocatePool( + EfiBootServicesData, + sizeof(ME_FW_UPDATE_LOCAL_PROTOCOL), + (VOID**)&mMeFwUpdateLclProtocol ); + if( EFI_ERROR(Status) ) + return Status; + + mMeFwUpdateLclProtocol->FwUpdBufferAddress = 0; + mMeFwUpdateLclProtocol->FwUpdBufferLength = 0; + mMeFwUpdateLclProtocol->FwUpdLcl = FwUpdLclFunc; + mMeFwUpdateLclProtocol->MeFwCheckMode = MeCheckFwState; + mMeFwUpdateLclProtocol->MeFwGetVersion = MeGetFwVersion; + mMeFwUpdateLclProtocol->HmrfpoEnable = MeUpdHmrfpoEnable; + mMeFwUpdateLclProtocol->PlatformReset = MeUpdPlatformReset; + mMeFwUpdateLclProtocol->PlatformUnlock = MeUpdPlatformUnlock; + mMeFwUpdateLclProtocol->AmiPostMgr = NULL; + + Status = pBS->InstallProtocolInterface( + &pHandle, + &mMeFwUpdLclProtocolGuid, + EFI_NATIVE_INTERFACE, + mMeFwUpdateLclProtocol ); + + MeFwUpdateProtocolEvent( NULL, NULL ); + + Status = pRS->GetVariable( + L"MeAutoUpdateReq", + &mAmiGlobalVariableGuid, + NULL, + &VariableSize, + &Dummy ); + if( EFI_ERROR(Status) || (Dummy == ME_UPD_LCL_SIGNATURE) ) + return EFI_SUCCESS; + + return EFI_SUCCESS; +} +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2015, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.cif b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.cif new file mode 100644 index 0000000..675fb33 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.cif @@ -0,0 +1,17 @@ +<component> + name = "ME Firmware Update Local" + category = ModulePart + LocalRoot = "\Chipset\eM\ME\MEUD\MEFwUpdLcl\" + RefName = "MEFwUpdLcl" +[files] +"MEFwUpdLcl.c" +"MeFwUpdLclProtocol.h" +"MEFwUpdLcl.sdl" +"MEFwUpdLcl.dxs" +"MEFwUpdLcl_SBY.dxs" +"MEFwUpdLcl.mak" +"MEFwUpdLclUpdateHooks.c" +"IntelLib\FWUpdateLib.h" +"IntelLib\me_status.h" +"IntelLib\FWUpdateLib.lib" +<endComponent> diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.dxs b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.dxs new file mode 100644 index 0000000..077fe27 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.dxs @@ -0,0 +1,9 @@ +#include <Protocol\HeciProtocol.h> +#include <Protocol\MeBiosPayloadData.h> +#include <Protocol\PchPlatformPolicy.h> +#include "MeFwUpdLclProtocol.h" + +DEPENDENCY_START + HECI_PROTOCOL_GUID AND + PCH_PLATFORM_POLICY_PROTOCOL_GUID +DEPENDENCY_END
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.mak b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.mak new file mode 100644 index 0000000..3eb64c2 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.mak @@ -0,0 +1,118 @@ +#********************************************************************** +#********************************************************************** +#** ** +#** (C)Copyright 1985-2010, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#********************************************************************** +#********************************************************************** + +#********************************************************************** +# $Header: /Alaska/SOURCE/Modules/OFBD Intel ME Update/CSP_MEUD/ME80/MEFwUpdLcl/MEFwUpdLcl.mak 2 5/14/15 4:28a Tristinchou $ +# +# $Revision: 2 $ +# +# $Date: 5/14/15 4:28a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/OFBD Intel ME Update/CSP_MEUD/ME80/MEFwUpdLcl/MEFwUpdLcl.mak $ +# +# 2 5/14/15 4:28a Tristinchou +# [TAG] EIP215437 +# [Category] New Feature +# [Description] ME capsule update support on SharkBay +# [Files] MEFwUpdLcl.c +# MeFwUpdLclProtocol.h +# MEFwUpdLcl.sdl +# MEFwUpdLcl.dxs +# MEFwUpdLcl.mak +# MEFwUpdLcl.cif +# +# 1 3/05/14 3:16a Tristinchou +# [TAG] EIP147099 +# [Category] Improvement +# [Description] Support ME FWUpdate API +# [Files] MEFwUpdLcl.cif +# MEFwUpdLcl.c +# MeFwUpdLclProtocol.h +# MEFwUpdLcl.sdl +# MEFwUpdLcl.dxs +# MEFwUpdLcl.mak +# IntelLib\FWUpdateLib.h +# IntelLib\me_status.h +# IntelLib\FWUpdateLib.lib +# +# 6 1/13/10 2:13p Felixp +# +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: <ComponentName>.mak +# +# Description: +# +#<AMI_FHDR_END> +#********************************************************************** +all : MEFwUpdLcl + +MEFwUpdLcl_LIBS=\ + $(EFIPROTOCOLLIB)\ + $(INTEL_FWUPDATE_LIB)\ + $(AMIDXELIB)\ + $(MeChipsetDxeLib_LIB)\ + $(MeLibDxe_LIB)\ + $(PchPlatformLib_LIB)\ + $(PchPlatformDxeLib_LIB)\ + $(EdkIIGlueBaseDebugLibNull_LIB) + +MEFwUpdLcl_INCLUDES=\ + $(ME_INCLUDES)\ + /I Core\ + +MEFwUpdLcl_OBJ = \ + $(BUILD_DIR)\$(MEFwUpdLcl_DIR)\MEFwUpdLcl.obj + +MEFwUpdLcl : $(BUILD_DIR)\MEFwUpdLcl.mak MEFwUpdLclBin + +$(BUILD_DIR)\MEFwUpdLcl.mak : $(MEFwUpdLcl_DIR)\$(@B).cif $(MEFwUpdLcl_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(MEFwUpdLcl_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +MEFwUpdLclBin : $(MEFwUpdLcl_LIBS) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\MEFwUpdLcl.mak all\ + "MY_INCLUDES=$(MEFwUpdLcl_INCLUDES)"\ + GUID=a11585b7-8fa2-4f1c-aa6f-dd6309469613\ + OBJECTS="$(MEFwUpdLcl_OBJ)" \ + ENTRY_POINT=MEFwUpdLclEntry\ + TYPE=BS_DRIVER \ +!IF "$(MEFWUPDLCL_ON_SHARKBAY_PLATFORM)"=="0" + DEPEX1=$(MEFwUpdLcl_DIR)\MEFwUpdLcl.dxs \ +!ELSE + DEPEX1=$(MEFwUpdLcl_DIR)\MEFwUpdLcl_SBY.dxs \ +!ENDIF + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + COMPRESS=1\ + +ReFlashBin : $(BUILD_DIR)\MEFwUpdLclUpdateHooks.obj + +$(BUILD_DIR)\MEFwUpdLclUpdateHooks.obj : $(MEFwUpdLcl_DIR)\MEFwUpdLclUpdateHooks.c + $(CC) /Fo$(BUILD_DIR)\MEFwUpdLclUpdateHooks.obj $(CFLAGS) $(MEFwUpdLcl_DIR)\MEFwUpdLclUpdateHooks.c +#********************************************************************** +#********************************************************************** +#** ** +#** (C)Copyright 1985-2010, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#********************************************************************** +#**********************************************************************
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.sdl b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.sdl new file mode 100644 index 0000000..6844616 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl.sdl @@ -0,0 +1,51 @@ +TOKEN + Name = MEFwUpdLcl_SUPPORT + Value = 0 + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable MEFwUpdLcl support in Project" +End + +TOKEN + Name = "MEFWUPDLCL_ON_SHARKBAY_PLATFORM" + Value = "0" + TokenType = Boolean + TargetMAK = Yes +End + +MODULE + Help = "Includes MEFwUpdLcl.mak to Project" + File = "MEFwUpdLcl.mak" +End + +PATH + Name = "MEFwUpdLcl_DIR" +End + +TOKEN + Name = "INTEL_FWUPDATE_LIB" + Value = "$(MEFwUpdLcl_DIR)\IntelLib\FWUpdateLib.lib" + TokenType = Expression + TargetMAK = Yes +End + +ELINK + Name = "$(BUILD_DIR)\MEFwUpdLcl.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + +ELINK + Name = "AutoMeudBeforeReflashHook," + Parent = "OemBeforeFlashUpdateList" + InvokeOrder = AfterParent +End + +ELINK + Name = "AutoMeudAfterReflashHook," + Parent = "OemAfterFlashUpdateList" + InvokeOrder = AfterParent + Priority = -100 +End
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLclUpdateHooks.c b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLclUpdateHooks.c new file mode 100644 index 0000000..0ec4b8e --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLclUpdateHooks.c @@ -0,0 +1,596 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2015, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* +#include <AmiDxeLib.h> +#include <AmiHobs.h> +#include <Capsule.h> +#include <Token.h> +#include <Protocol/Decompress.h> +#include <Protocol/GuidedSectionExtraction.h> +#include <Protocol/AmiPostMgr.h> + +#include "MeFwUpdLclProtocol.h" + +#define SECTION_SIZE(SectionHeaderPtr) \ + ((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) SectionHeaderPtr)->Size) & 0x00ffffff)) +#define SIGNATURE_16(A, B) ((A) | (B << 8)) +#define SIGNATURE_32(A, B, C, D) (SIGNATURE_16 (A, B) | (SIGNATURE_16 (C, D) << 16)) + +#define EFI_CUSTOMIZED_DECOMPRESS_PROTOCOL_GUID \ + { 0x9a44198e, 0xa4a2, 0x44e6, 0x8a, 0x1f, 0x39, 0xbe, 0xfd, 0xac, 0x89, 0x6f } +#define ME_UPD_LCL_SIGNATURE SIGNATURE_32 ('_', 'M', 'U', 'L') +#define FV_GUID_OFFSET 0x60 + +extern EFI_GUID gAmiGlobalVariableGuid; +EFI_GUID mMeRegionFfsGuid = \ + { 0xDE90FFA8, 0xB985, 0x4575, 0xAB, 0x8D, 0xAD, 0xE5, 0x2C, 0x36, 0x2C, 0xA3 }; +EFI_GUID mMeVersionFfsFileGuid = \ + { 0x0B4AE6BE, 0x6DA6, 0x4908, 0x8A, 0x71, 0x7E, 0x6A, 0x8A, 0x33, 0xB1, 0x1C }; +EFI_GUID mMeVersionFfsSectionGuid = \ + { 0x6A6D576A, 0x8F38, 0x45E7, 0x97, 0xC0, 0x8A, 0xCD, 0x9E, 0x99, 0x26, 0x74 }; +EFI_GUID mEfiCustomizedDecompressProtocolGuid = \ + { 0X9A44198E, 0XA4A2, 0X44E6, 0X8A, 0X1F, 0X39, 0XBE, 0XFD, 0XAC, 0X89, 0X6F }; +static EFI_GUID mAmiPostManagerProtocolGuid = AMI_POST_MANAGER_PROTOCOL_GUID; +static AMI_POST_MANAGER_PROTOCOL *mAmiPostMgr = NULL; +ME_FW_UPD_VERSION mMeFwImgVersion[] = ME_FW_IMAGE_VERSION; +ME_FW_UPD_VERSION MbpMeFwVer; + +extern UINT8 *RecoveryBuffer; + +UINT8* +FvFindFfsFileByGuid ( + UINT8 *FvAddress, + EFI_GUID *pGuid +); + +VOID +AutoMeudBeforeReflashHook( + VOID +); + +VOID +AutoMeudAfterReflashHook( + VOID +); + +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: DecompressBinary +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +DecompressBinary( + IN UINTN *BinaryBuffer, + IN UINTN BinaryBufferSize, + OUT UINTN **DecompressBuffer, + OUT UINTN *DecompressBufferSize + ) +{ + EFI_STATUS Status; + EFI_FFS_FILE_HEADER *FfsFileHeader = NULL; + EFI_COMMON_SECTION_HEADER *SectionHeader = NULL; + UINTN NvarSize = 0; + VOID *NvarBuffer = NULL; + EFI_COMPRESSION_SECTION *CompressSection = NULL; + EFI_GUID_DEFINED_SECTION *GuidedSection = NULL; + EFI_DECOMPRESS_PROTOCOL *Decompress = NULL; + EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL *GuidedExtraction = NULL; + VOID *CompressionSource = NULL; + UINT32 CompressionSourceSize = 0; + UINT32 UncompressedLength = 0; + UINT8 CompressionType; + VOID *ScratchBuffer = NULL; + UINT32 ScratchSize = 0; + VOID *NewBuffer = NULL; + UINTN NewBufferSize = 0; + UINT32 AuthenticationStatus = 0; + + FfsFileHeader = (EFI_FFS_FILE_HEADER*)BinaryBuffer; + SectionHeader = (EFI_COMMON_SECTION_HEADER*)((UINT8*)FfsFileHeader + sizeof(EFI_FFS_FILE_HEADER)); + + if( FfsFileHeader->Type == EFI_FV_FILETYPE_RAW ) { + //The binary is the NVRAM ffs without any section, + //allocate the memory and copy it. + + NvarSize = BinaryBufferSize - sizeof(EFI_FFS_FILE_HEADER); + + Status = pBS->AllocatePool( EfiBootServicesData, + NvarSize, + &NvarBuffer ); + if( EFI_ERROR(Status) ) + return Status; + + MemCpy( NvarBuffer, (VOID*)SectionHeader, NvarSize ); + + *DecompressBuffer = NvarBuffer; + *DecompressBufferSize = NvarSize; + + return EFI_SUCCESS; + } + //The binary is the NVRAM ffs with section, + //determine the section type. + + switch( SectionHeader->Type ) + { + case EFI_SECTION_COMPRESSION: + //The section is compressed by PI_STD + CompressSection = (EFI_COMPRESSION_SECTION*)SectionHeader; + + CompressionSource = (VOID*)((UINT8*)CompressSection + sizeof(EFI_COMPRESSION_SECTION)); + CompressionSourceSize = (UINT32)(SECTION_SIZE(CompressSection) - sizeof(EFI_COMPRESSION_SECTION)); + UncompressedLength = CompressSection->UncompressedLength; + CompressionType = CompressSection->CompressionType; + + if( UncompressedLength > 0 ) + { + NewBufferSize = UncompressedLength; + + Status = pBS->AllocatePool( EfiBootServicesData, + NewBufferSize, + &NewBuffer ); + if( EFI_ERROR(Status) ) + return Status; + + if( CompressionType == EFI_NOT_COMPRESSED ) + { + MemCpy( NewBuffer, (VOID*)CompressionSource, NewBufferSize ); + } + else if ( CompressionType == EFI_STANDARD_COMPRESSION || + CompressionType == EFI_CUSTOMIZED_COMPRESSION ) + { + + if( CompressionType == EFI_STANDARD_COMPRESSION ) + { + Status = pBS->LocateProtocol( + &gEfiDecompressProtocolGuid, + NULL, + &Decompress ); + } + else + { + Status = pBS->LocateProtocol( + &mEfiCustomizedDecompressProtocolGuid, + NULL, + &Decompress ); + } + if( EFI_ERROR(Status) ) + { + pBS->FreePool( NewBuffer ); + return Status; + } + + Status = Decompress->GetInfo( Decompress, + CompressionSource, + CompressionSourceSize, + (UINT32 *)&NewBufferSize, + &ScratchSize ); + if( EFI_ERROR(Status) || (NewBufferSize != UncompressedLength)) + { + pBS->FreePool( NewBuffer ); + if(!EFI_ERROR (Status)) + Status = EFI_BAD_BUFFER_SIZE; + return Status; + } + + Status = pBS->AllocatePool( EfiBootServicesData, + ScratchSize, + &ScratchBuffer ); + if( EFI_ERROR(Status) ) + { + pBS->FreePool( NewBuffer ); + return Status; + } + + Status = Decompress->Decompress( Decompress, + CompressionSource, + CompressionSourceSize, + NewBuffer, + (UINT32)NewBufferSize, + ScratchBuffer, + ScratchSize ); + pBS->FreePool( ScratchBuffer ); + if( EFI_ERROR(Status) ) + { + pBS->FreePool( NvarBuffer ); + return Status; + } + + //The decompressed data is the EFI_SECTION_RAW + //Add the section header length to get data + SectionHeader = (EFI_COMMON_SECTION_HEADER*)NewBuffer; + + NvarSize = SECTION_SIZE(SectionHeader) - sizeof(EFI_COMMON_SECTION_HEADER); + NvarBuffer = (VOID*)((UINT8*)NewBuffer + sizeof(EFI_COMMON_SECTION_HEADER)); + } + } + + break; + + case EFI_SECTION_GUID_DEFINED: + + //The section is compressed by LZMA + GuidedSection = (EFI_GUID_DEFINED_SECTION*)SectionHeader; + + Status = pBS->LocateProtocol( &(GuidedSection->SectionDefinitionGuid), + NULL, + &GuidedExtraction ); + if( EFI_ERROR(Status) ) + return Status; + + Status = GuidedExtraction->ExtractSection( + GuidedExtraction, + GuidedSection, + &NewBuffer, + &NewBufferSize, + &AuthenticationStatus ); + if( EFI_ERROR(Status) ) + return Status; + + //The decompressed data is the EFI_SECTION_RAW + //Add the section header length to get data + SectionHeader = (EFI_COMMON_SECTION_HEADER*)NewBuffer; + + NvarSize = SECTION_SIZE(SectionHeader) - sizeof(EFI_COMMON_SECTION_HEADER); + NvarBuffer = (VOID*)((UINT8*)NewBuffer + sizeof(EFI_COMMON_SECTION_HEADER)); + + break; + + case EFI_SECTION_RAW: + + //The section is not compressed. + NvarSize = BinaryBufferSize - (sizeof(EFI_FFS_FILE_HEADER) + sizeof(EFI_COMMON_SECTION_HEADER)); + + Status = pBS->AllocatePool( EfiBootServicesData, + NvarSize, + &NvarBuffer ); + if( EFI_ERROR(Status) ) + return Status; + + MemCpy( NvarBuffer, (VOID*)((UINT8*)SectionHeader + sizeof(EFI_COMMON_SECTION_HEADER)), NvarSize ); + + break; + + default: + + NvarBuffer = NULL; + NvarSize = 0; + + break; + } + + *DecompressBuffer = NvarBuffer; + *DecompressBufferSize = NvarSize; + + return Status; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MeFwUpdateViaIntelLib +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MeFwUpdateViaIntelLib( + IN UINT8 *pBuffer, + IN AMI_POST_MANAGER_PROTOCOL *AmiPostMgr + ) +{ + EFI_STATUS Status; + UINTN *pMeRegionFile, *UcMeBuffer, UcMeBufferSize; + EFI_GUID mMeFwUpdLclProtocolGuid = ME_FW_UPD_LOCAL_PROTOCOL_GUID; + ME_FW_UPDATE_LOCAL_PROTOCOL *mMeFwUpdateLclProtocol = NULL; + EFI_FFS_FILE_HEADER *pHdr; + + // Locate ME FW Update Local Protocol. + Status = pBS->LocateProtocol (&mMeFwUpdLclProtocolGuid, \ + NULL, (VOID**)&mMeFwUpdateLclProtocol); + if(EFI_ERROR(Status) || (pBuffer == NULL)) return Status; + + // Check ME is in Normal mode. + Status = mMeFwUpdateLclProtocol->MeFwCheckMode(mMeFwUpdateLclProtocol, MeModeNormal); + if(EFI_ERROR(Status)) return Status; + + // Search the ME FW file from buffer. + if (((UINT8*)pMeRegionFile = FvFindFfsFileByGuid( \ + pBuffer, &mMeRegionFfsGuid)) == NULL) return Status; + + // Decompress the ME FW file.. + pHdr = (EFI_FFS_FILE_HEADER*)pMeRegionFile; + Status = DecompressBinary ( pMeRegionFile, \ + (UINTN)(*(UINT32*)pHdr->Size & 0xffffff), \ + &UcMeBuffer, &UcMeBufferSize); + if (EFI_ERROR(Status)) return Status; + + // Update reflash progress bar only if Secure flash capsule update. + // Do not display any messages if Windwos Firmware Update Capsule. + mMeFwUpdateLclProtocol->AmiPostMgr = NULL; + if (AmiPostMgr != NULL) mMeFwUpdateLclProtocol->AmiPostMgr = AmiPostMgr; + Status = mMeFwUpdateLclProtocol->FwUpdLcl(mMeFwUpdateLclProtocol, \ + (UINT8*)UcMeBuffer, UcMeBufferSize); + return Status; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: GetFvMeFwRegionAddress +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8* +GetFvMeFwRegionAddress( + UINT8 *StartAddress + ) +{ + EFI_GUID mMeFwCapsuleFirmwareVolumeGuid = ME_FW_CAPSULE_FIRMWARE_VOLUME_GUID; + if (!guidcmp((UINT8*)StartAddress + FV_GUID_OFFSET, \ + &mMeFwCapsuleFirmwareVolumeGuid)) return StartAddress; + if (!guidcmp((UINT8*)StartAddress + FLASH_SIZE + FV_GUID_OFFSET, \ + &mMeFwCapsuleFirmwareVolumeGuid)) return StartAddress + FLASH_SIZE; + return NULL; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: FvFindFfsFileByGuid +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8* +FvFindFfsFileByGuid( + UINT8 *FvAddress, + EFI_GUID *pGuid + ) +{ + EFI_FFS_FILE_HEADER *pFfsFile; + UINT32 i, FvLength = FLASH_SIZE, FileSize; + UINT8 *p = (UINT8*)NULL; + EFI_GUID EfiFirmwareFileSystem2Guid = EFI_FIRMWARE_FILE_SYSTEM2_GUID; + + if ((p = GetFvMeFwRegionAddress(FvAddress)) == NULL) return NULL; + FvLength = (UINT32)((EFI_FIRMWARE_VOLUME_HEADER*)p)->FvLength; + for (i = 0; (i + 16) < FvLength; i += 16) { + if (guidcmp (&((EFI_FIRMWARE_VOLUME_HEADER*)(p + i))->FileSystemGuid, \ + &EfiFirmwareFileSystem2Guid)) continue; + FileSize = ((EFI_FIRMWARE_VOLUME_HEADER*)(p + i))->HeaderLength; + pFfsFile = (EFI_FFS_FILE_HEADER*)(p + i + FileSize); + do { + if (!guidcmp (&((EFI_FFS_FILE_HEADER*)pFfsFile)->Name, pGuid)) { + return ((UINT8*)pFfsFile); + } + FileSize = *(UINT32 *)pFfsFile->Size & 0x00FFFFFF; + pFfsFile = (EFI_FFS_FILE_HEADER*)((UINT32)pFfsFile + FileSize); + pFfsFile = (EFI_FFS_FILE_HEADER*)(((UINT32)pFfsFile + 7) & 0xfffffff8); + } while(((*(UINT32 *)pFfsFile->Size & 0x00FFFFFF) != 0xFFFFFF) && \ + ((*(UINT32 *)pFfsFile->Size & 0x00FFFFFF) != 0)); + i += (UINT32)(((EFI_FIRMWARE_VOLUME_HEADER*)(p + i))->FvLength - 16); + } + return ((UINT8*)NULL); +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: CheckMeFirmwareVersion +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +BOOLEAN +CheckMeFirmwareVersion( + UINT8 *pFileSection + ) +{ + UINT8 *p = pFileSection + sizeof(EFI_COMMON_SECTION_HEADER); + ME_FW_UPD_VERSION *NewMeFwVer; + + if (guidcmp (p, &mMeVersionFfsSectionGuid)) return FALSE; + NewMeFwVer = (ME_FW_UPD_VERSION*)(p + sizeof (EFI_GUID)); + + // ??? PORTING REQUEST ??? [TO DO] if can't get ME FW version from MBP ?? + // ==== PORTING REQUEST ==== >> + if (MbpMeFwVer.MajorVersion != NewMeFwVer->MajorVersion) return FALSE; + if (MbpMeFwVer.MinorVersion < NewMeFwVer->MinorVersion) return FALSE; + if ((UINT32)((NewMeFwVer->HotfixVersion << 16) + NewMeFwVer->BuildVersion) > + (UINT32)((MbpMeFwVer.HotfixVersion << 16) + MbpMeFwVer.BuildVersion)) { + return TRUE; + } + // << ==== PORTING REQUEST ==== + return FALSE; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: IsMeFirmawareUpgraded +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +BOOLEAN +IsMeFirmawareUpgraded( + EFI_GUID *pGuid + ) +{ + UINT8 *pFfsFile; + if ((pFfsFile = FvFindFfsFileByGuid(RecoveryBuffer, pGuid)) == NULL) return FALSE; + return CheckMeFirmwareVersion (pFfsFile + sizeof(EFI_FFS_FILE_HEADER)); +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: IsWindowsFwUpdate +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +BOOLEAN +IsWindowsFwUpdate( + VOID + ) +{ + EFI_STATUS Status; + EFI_CAPSULE_HEADER *Capsule; + EFI_HOB_UEFI_CAPSULE *Hob; + static EFI_GUID ImageCapsuleGuid = W8_SCREEN_IMAGE_CAPSULE_GUID; + static EFI_GUID HobListGuid = HOB_LIST_GUID; + + if ((Hob = GetEfiConfigurationTable(pST, &HobListGuid)) == NULL) return FALSE; + do { + Status = FindNextHobByType(EFI_HOB_TYPE_UEFI_CAPSULE, &Hob); + if(!EFI_ERROR(Status)) { + Capsule = (EFI_CAPSULE_HEADER *)(VOID *)(UINTN)Hob->BaseAddress; + if(!guidcmp(&(Capsule->CapsuleGuid), &ImageCapsuleGuid)) return TRUE; + } + } while(!EFI_ERROR(Status)); + return FALSE; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: AutoMeudBeforeReflashHook +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +AutoMeudBeforeReflashHook( + VOID + ) +{ + UINTN Length = sizeof(ME_FW_UPD_VERSION); + EFI_STATUS Status; + + // Save "MeAutoUpdateReq" variable here for avoiding NVRAM could be updated later. + Status = pRS->GetVariable (L"MbpMeFwVersion", \ + &gAmiGlobalVariableGuid, NULL, &Length, &MbpMeFwVer); + if (EFI_ERROR(Status)) MemSet(&MbpMeFwVer, sizeof(ME_FW_UPD_VERSION), 0); + + // Start ME FW update process here if ME FW Capsule only. + if (RecoveryBuffer == GetFvMeFwRegionAddress(RecoveryBuffer)) { + EFI_EVENT event; + AutoMeudAfterReflashHook(); + if (mAmiPostMgr != NULL) + mAmiPostMgr->DisplayInfoBox(L"ME FW update", L"ME FW update completed, Press any key to reset the system", 5, &event); + pRS->ResetSystem(EfiResetCold, EFI_SUCCESS, 0, NULL); + } + + return; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: AutoMeudAfterReflashHook +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +AutoMeudAfterReflashHook( + VOID + ) +{ + EFI_STATUS Status = EFI_VOLUME_CORRUPTED; + UINT32 MeMode; + + if ((mMeFwImgVersion->MajorVersion != 0) && \ + (!IsMeFirmawareUpgraded(&mMeVersionFfsFileGuid))) return ; + if (!IsWindowsFwUpdate()) + Status = pBS->LocateProtocol(&mAmiPostManagerProtocolGuid, NULL, &mAmiPostMgr); + // ME FW Update API could returns error "EFI_VOLUME_CORRUPTED" if capsule mode + // in S3 resume path, so, we set the MeAutoUpdateReq variable to "_MUL" for + // trying update ME FW again if error. + MeMode = ME_UPD_LCL_SIGNATURE; + Status = MeFwUpdateViaIntelLib (RecoveryBuffer, mAmiPostMgr); + if (EFI_ERROR(Status)) + { + pRS->SetVariable (L"MeAutoUpdateReq", + &gAmiGlobalVariableGuid, + EFI_VARIABLE_NON_VOLATILE | \ + EFI_VARIABLE_BOOTSERVICE_ACCESS, \ + sizeof(UINT32), \ + &MeMode); + } + return; +} +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2015, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//*************************************************************************
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl_SBY.dxs b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl_SBY.dxs new file mode 100644 index 0000000..5728a1c --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MEFwUpdLcl_SBY.dxs @@ -0,0 +1,14 @@ +#define HECI_PROTOCOL_GUID \ + { \ + 0xcfb33810, 0x6e87, 0x4284, 0xb2, 0x3, 0xa6, 0x6a, 0xbe, 0x7, 0xf6, 0xe8 \ + } + +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID \ + { \ + 0x9797aaf8, 0xe49b, 0x4f02, 0xa3, 0x68, 0xc8, 0x14, 0x8d, 0x2b, 0xc9, 0xe7 \ + } + +DEPENDENCY_START + HECI_PROTOCOL_GUID AND + DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID +DEPENDENCY_END
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MEFwUpdLcl/MeFwUpdLclProtocol.h b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MeFwUpdLclProtocol.h new file mode 100644 index 0000000..66c805e --- /dev/null +++ b/Chipset/eM/ME/MEUD/MEFwUpdLcl/MeFwUpdLclProtocol.h @@ -0,0 +1,109 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2014, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** +#include <Protocol/AmiPostMgr.h> + +#define SEC_SMI_FLASH_GUID \ + { 0x3bf4af16, 0xab7c, 0x4b43, 0x89, 0x8d, 0xab, 0x26, 0xac, 0x5d, 0xdc, 0x6c } + +//{ DCA334AB-56E3-4EDE-B9B3-8EAE2ACF5E78 } +#define ME_FW_UPD_LOCAL_PROTOCOL_GUID \ + { 0xDCA334AB, 0x56E3, 0x4EDE, 0xB9, 0xB3, 0x8E, 0xAE, 0x2A, 0xCF, 0x5E, 0x78 } + +//{ 9F8B1DEF-B62B-45F3-8282-BFD7EA19801B } +#define ME_FW_CAPSULE_FIRMWARE_VOLUME_GUID \ + { 0x9F8B1DEF, 0xB62B, 0x45F3, 0x82, 0x82, 0xBF, 0xD7, 0xEA, 0x19, 0x80, 0x1B } + +typedef struct _ME_FW_UPD_VERSION { + UINT32 MajorVersion : 16; + UINT32 MinorVersion : 16; + UINT32 HotfixVersion : 16; + UINT32 BuildVersion : 16; +} ME_FW_UPD_VERSION; + +typedef enum { + MeModeNormal, + MeModeDebug, + MeModeTempDisabled, + MeModeSecOver, + MeModeFailed +} ME_FW_STATE; + +typedef struct _ME_FW_UPDATE_LOCAL_PROTOCOL ME_FW_UPDATE_LOCAL_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *ME_FW_UPD_LOCAL_FUNC) ( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This, + IN UINT8 *FileBuffer, + IN UINTN FileLength +); + +typedef +EFI_STATUS +(EFIAPI *ME_FW_CHECK_MODE) ( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This, + IN ME_FW_STATE MeFwState +); + +typedef +EFI_STATUS +(EFIAPI *ME_FW_CHECK_VERSION) ( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This, + IN ME_FW_UPD_VERSION *MeFwVerion +); + +typedef +EFI_STATUS +(EFIAPI *ME_MEI_HMRFPO_ENABLE) ( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This +); + +typedef +EFI_STATUS +(EFIAPI *PLATFORM_RESET) ( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This, + IN EFI_RESET_TYPE ResetType +); + +typedef +EFI_STATUS +(EFIAPI *PLATFORM_UNLOCK) ( + IN ME_FW_UPDATE_LOCAL_PROTOCOL *This, + IN UINT32 UnlockType OPTIONAL +); + +typedef struct _ME_FW_UPDATE_LOCAL_PROTOCOL { + EFI_PHYSICAL_ADDRESS FwUpdBufferAddress; + UINTN FwUpdBufferLength; + ME_FW_UPD_LOCAL_FUNC FwUpdLcl; + ME_FW_CHECK_MODE MeFwCheckMode; + ME_FW_CHECK_VERSION MeFwGetVersion; + ME_MEI_HMRFPO_ENABLE HmrfpoEnable; + PLATFORM_RESET PlatformReset; + PLATFORM_UNLOCK PlatformUnlock; + AMI_POST_MANAGER_PROTOCOL *AmiPostMgr; +}; +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2014, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//**********************************************************************
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsule.cif b/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsule.cif new file mode 100644 index 0000000..1858b65 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsule.cif @@ -0,0 +1,11 @@ +<component> + name = "MeFwCapsule" + category = ModulePart + LocalRoot = "\Chipset\eM\ME\MEUD\MeFwCapsule\" + RefName = "MeFwCapsule" +[files] +"MeFwCapsule.sdl" +"MeFwCapsule.mak" +"MeFwCapsulePei.c" +"MeFwCapsulePei.dxs" +<endComponent>
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsule.mak b/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsule.mak new file mode 100644 index 0000000..f605eda --- /dev/null +++ b/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsule.mak @@ -0,0 +1,348 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2014, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#********************************************************************** +# $Header: /Alaska/SOURCE/Modules/OFBD Intel ME Update/CSP_MEUD/ME80/MeFwCapsule/MeFwCapsule.mak 3 6/03/15 7:22a Tristinchou $ +# +# $Revision: 3 $ +# +# $Date: 6/03/15 7:22a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/OFBD Intel ME Update/CSP_MEUD/ME80/MeFwCapsule/MeFwCapsule.mak $(BUILD_DIR)\MeFwCapsulePei.mak MeFwCapsulePeiBin +# +# 3 6/03/15 7:22a Tristinchou +# [TAG] EIPNone +# [Category] Improvement +# [Description] Fix ME update capsule can't be generated. +# +# 2 5/14/15 5:08a Tristinchou +# +# 1 5/14/15 4:24a Tristinchou +# [TAG] EIP215437 +# [Category] New Feature +# [Description] ME capsule update support +# [Files] MeFwCapsule.cif +# MeFwCapsule.sdl +# MeFwCapsule.mak +# MeFwCapsulePei.c +# MeFwCapsulePei.dxs +# +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: +# +# Description: +# +#<AMI_FHDR_END> +#********************************************************************** +all : MeFwCapsulePei MeFwCapsule + +MeFwCapsulePei : $(BUILD_DIR)\MeFwCapsulePei.mak MeFwCapsulePeiBin + +MeFwCapsulePei_OBJ = \ + $(BUILD_DIR)\$(MeFwCapsule_DIR)\MeFwCapsulePei.obj + +$(BUILD_DIR)\MeFwCapsulePei.mak : $(MeFwCapsule_DIR)\MeFwCapsule.mak $(MeFwCapsule_DIR)\MeFwCapsule.cif $(BUILD_RULES) + $(CIF2MAK) $(MeFwCapsule_DIR)\MeFwCapsule.cif $(CIF2MAK_DEFAULTS) + +MeFwCapsulePeiBin : $(AMIPEILIB) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS) \ + /f $(BUILD_DIR)\MeFwCapsulePei.mak all \ + NAME=MeFwCapsulePei \ + MAKEFILE=$(BUILD_DIR)\MeFwCapsulePei.mak \ + GUID=FD27652D-F758-4EFC-B1A9-283EFE51F4E9 \ + ENTRY_POINT=MeFwCapsulePeiEntry \ + OBJECTS="$(MeFwCapsulePei_OBJ)" \ + DEPEX1="$(MeFwCapsule_DIR)\MeFwCapsulePei.dxs" DEPEX1_TYPE=EFI_SECTION_PEI_DEPEX \ + TYPE=PEIM \ + COMPRESS=0\ + +MeFwCapsule : MeFwExt MeFwCapsuleHdr MeFwCapFid MeFwVer MeFwLayout MeFwRegion MeFwFv + +MeFwExt : $(BUILD_DIR)\MeFwExt.ffs + +$(BUILD_DIR)\MeFwExt.obj: $(BUILD_DIR)\MeFwCapsule.mak + $(SILENT)copy << $(BUILD_DIR)\MeFwExt.c > NUL +#include <EFI.h> + +#define ME_CAPSULE_GUID \ + { 0x9F8B1DEF, 0xB62B, 0x45F3, 0x82, 0x82, 0xBF, 0xD7, 0xEA, 0x19, 0x80, 0x1B} + +static EFI_GUID MeCapsuleGuid = ME_CAPSULE_GUID; +static UINT32 Length = 0x14; +static UINT32 Pad = 0xFFFFFFFF; +<<KEEP + $(CC) /Fo$@ $(CFLAGS) $(BUILD_DIR)\MeFwExt.c + +$(BUILD_DIR)\MeFwExt.ffs : $(BUILD_DIR)\MeFwExt.obj + $(MAKE) /$(MAKEFLAGS) EXT_OBJS= $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\MeFwCapsule.mak bin\ + NAME=MeFwExt OBJECTS=$(BUILD_DIR)\MeFwExt.obj\ + MAKEFILE=$(BUILD_DIR)\MeFwCapsule.mak \ + TYPE=BINARY + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=FFFFFFFF-FFFF-FFFF-FFFF-FFFFFFFFFFFF \ + TYPE=EFI_FV_FILETYPE_RAW FFS_CHECKSUM=0\ + RAWFILE=$(BUILD_DIR)\MeFwExt.bin\ + FFSFILE=$@ COMPRESS=0 NAME=$(@B) + +#--------------------------------------------------------------------------- +# Generic MAK dependencies +#--------------------------------------------------------------------------- +$(BUILD_DIR)\MeFwCapsule.mak : $(MeFwCapsule_DIR)\MeFwCapsule.mak $(MeFwCapsule_DIR)\MeFwCapsule.cif $(BUILD_RULES) + $(CIF2MAK) $(MeFwCapsule_DIR)\MeFwCapsule.cif $(CIF2MAK_DEFAULTS) + +#--------------------------------------------------------------------------- +# Generic GUID defines. Aptio Tools must support these GUIDs +#--------------------------------------------------------------------------- +#GUID used to identify FW Capsule Hdr FFS file within the Firmware Volume. +FWCAPSULE_FFS_GUID = 414D94AD-998D-47D2-BFCD-4E882241DE32 +#Section GUID used to identify FW Capsule Hdr section within FwCap FFS file. +FWCAPSULE_FFS_SECTION_GUID = 5A88641B-BBB9-4AA6-80F7-498AE407C31F + +MeFwCapsuleHdr : $(BUILD_DIR)\MeFwCapsule.mak $(BUILD_DIR)\MeFwCapsuleHdr.ffs + +$(BUILD_DIR)\MeFwCapsuleHdr.obj: $(BUILD_DIR)\MeFwCapsule.mak + $(SILENT)copy << $(BUILD_DIR)\MeFwCapsuleHdr.c > NUL +#include <AmiCertificate.h> +#pragma pack(1) +APTIO_FW_CAPSULE_HEADER dummyHdr = + { { APTIO_FW_CAPSULE_GUID, + $(FWCAPSULE_MAX_HDR_SIZE), + CAPSULE_FLAGS_PERSIST_ACROSS_RESET | + CAPSULE_FLAGS_FWCERTBLOCK_VALID, // 1 - sig is invalid + $(FWCAPSULE_MAX_HDR_SIZE)}, + $(FWCAPSULE_MAX_HDR_SIZE), // Rom Offs + sizeof(APTIO_FW_CAPSULE_HEADER) // RomLayout Offs + }; +char pad[$(FWCAPSULE_MAX_HDR_SIZE)-sizeof(APTIO_FW_CAPSULE_HEADER)] = {0x55, 0xAA}; +<<KEEP + $(CC) /Fo$@ $(CFLAGS) $(BUILD_DIR)\MeFwCapsuleHdr.c + +$(BUILD_DIR)\MeFwCapsuleHdr.ffs : $(BUILD_DIR)\MeFwCapsuleHdr.obj $(BUILD_DIR)\MeFwCapsule.mak + $(MAKE) /$(MAKEFLAGS) EXT_OBJS= $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\MeFwCapsule.mak bin\ + NAME=MeFwCapsuleHdr OBJECTS=$(BUILD_DIR)\MeFwCapsuleHdr.obj\ + MAKEFILE=$(BUILD_DIR)\MeFwCapsule.mak \ + TYPE=BINARY + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=$(FWCAPSULE_FFS_GUID) \ + TYPE=EFI_FV_FILETYPE_FREEFORM FFS_CHECKSUM=0\ + SECTION_GUID=$(FWCAPSULE_FFS_SECTION_GUID) \ + RESOURCE=$(BUILD_DIR)\MeFwCapsuleHdr.bin \ + FFSFILE=$@ COMPRESS=0 NAME=$(@B) + +CSP_LIB_DIR = Core\CspLib + +MeFwCapFid : $(BUILD_DIR)\MeFwCapsule.mak $(BUILD_DIR)\MeFwCapFid.ffs + +$(BUILD_DIR)\MeFwCapFid.ffs : $(BUILD_DIR)\AMICspLib.mak + $(MAKE) /$(MAKEFLAGS) EXT_OBJS= $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\AMICspLib.mak bin\ + NAME=MeFwCapFid OBJECTS=$(BUILD_DIR)\$(CSP_LIB_DIR)\Fid.obj\ + MAKEFILE=$(BUILD_DIR)\AMICspLib.mak \ + TYPE=BINARY + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=3FD1D3A2-99F7-420b-BC69-8BB1D492A332 \ + TYPE=EFI_FV_FILETYPE_FREEFORM \ + FFSFILE=$@ COMPRESS=0 NAME=$(@B)\ + RESOURCE=$(BUILD_DIR)\Fid.bin \ + SECTION_GUID=2EBE0275-6458-4AF9-91ED-D3F4EDB100AA \ + +MeFwVer : $(BUILD_DIR)\MeFwCapsule.mak $(BUILD_DIR)\MeFwVer.ffs + +$(BUILD_DIR)\MeFwVer.obj: $(BUILD_DIR)\MeFwCapsule.mak + $(SILENT)copy << $(BUILD_DIR)\MeFwVer.c > NUL +#include <EFI.h> +#include <Token.h> + +typedef struct _FW_VERSION_NAME { + UINT32 MajorVersion : 16; + UINT32 MinorVersion : 16; + UINT32 HotfixVersion : 16; + UINT32 BuildVersion : 16; +} ME_FW_UPD_VERSION; + +const ME_FW_UPD_VERSION MeFwVersion[] = ME_FW_IMAGE_VERSION; +<<KEEP + $(CC) /Fo$@ $(CFLAGS) $(BUILD_DIR)\MeFwVer.c + +$(BUILD_DIR)\MeFwVer.ffs : $(BUILD_DIR)\MeFwVer.obj + $(MAKE) /$(MAKEFLAGS) EXT_OBJS= $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\MeFwCapsule.mak bin\ + NAME=MeFwVer OBJECTS=$(BUILD_DIR)\MeFwVer.obj\ + MAKEFILE=$(BUILD_DIR)\MeFwCapsule.mak \ + TYPE=BINARY + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=0B4AE6BE-6DA6-4908-8A71-7E6A8A33B11C \ + TYPE=EFI_FV_FILETYPE_FREEFORM FFS_CHECKSUM=0\ + SECTION_GUID=6A6D576A-8F38-45E7-97C0-8ACD9E992674 \ + RESOURCE=$(BUILD_DIR)\MeFwVer.bin \ + FFSFILE=$@ COMPRESS=0 NAME=$(@B) + +MeFwLayout : $(BUILD_DIR)\MeFwCapsule.mak $(BUILD_DIR)\MeFwLayout.ffs + +$(BUILD_DIR)\MeFwLayout.obj: $(BUILD_DIR)\MeFwCapsule.mak + $(SILENT)copy << $(BUILD_DIR)\MeFwLayout.c > NUL +#include <Token.h> +#include <RomLayout.h> + +ROM_AREA MeLayout[2] = {\ + { 0, 0, FV_MEFWCAP_SIZE, 0, 0x20A}, + { 0, 0, 0, 0, 0} +}; +<<KEEP + $(CC) /Fo$@ $(CFLAGS) $(BUILD_DIR)\MeFwLayout.c + +$(BUILD_DIR)\MeFwLayout.ffs : $(BUILD_DIR)\MeFwLayout.obj + $(MAKE) /$(MAKEFLAGS) EXT_OBJS= $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\MeFwCapsule.mak bin\ + NAME=MeFwLayout OBJECTS=$(BUILD_DIR)\MeFwLayout.obj\ + MAKEFILE=$(BUILD_DIR)\MeFwCapsule.mak \ + TYPE=BINARY + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=0DCA793A-EA96-42d8-BD7B-DC7F684E38C1 \ + TYPE=EFI_FV_FILETYPE_FREEFORM FFS_CHECKSUM=0\ + SECTION_GUID=88A15A4F-977D-4682-B17C-DA1F316C1F32 \ + RESOURCE=$(BUILD_DIR)\MeFwLayout.bin \ + FFSFILE=$@ COMPRESS=0 NAME=$(@B) + +MeFwRegion : $(BUILD_DIR)\MeFwRegion.ffs + +$(BUILD_DIR)\MeFwRegion.ffs : $(ME_BIN_FILE) + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=DE90FFA8-B985-4575-AB8D-ADE52C362CA3 \ + TYPE=EFI_FV_FILETYPE_FREEFORM \ + BINFILE=$** FFSFILE=$@ COMPRESS=1 NAME=$(**B) + +MeFwFv : MeFwExt MeFwCapsuleHdr MeFwCapFid MeFwVer MeFwLayout MeFwRegion $(BUILD_DIR)\FWkey.ffs +!IF EXIST ($(BUILD_DIR)\FV_MEFWCAP_VOL.inf ) + del $(BUILD_DIR)\FV_MEFWCAP_VOL.inf +!ENDIF + echo [options] >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf +# This is a dummy base address to store logos in ROMHOLE.This address has no effect in ROMHOLE. + echo EFI_BASE_ADDRESS = $(FV_MEFWCAP_BASE) >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_FILE_NAME = $(BUILD_DIR)\FV_MEFWCAP_VOL.FV >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_NUM_BLOCKS = $(FV_MEFWCAP_NUMBER_OF_BLOCK) >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_BLOCK_SIZE = $(FV_MEFWCAP_BLOCK_SIZE) >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo IGNORE_COMPRESSION = FALSE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo [attributes] >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_READ_DISABLED_CAP = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_READ_ENABLED_CAP = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_READ_STATUS = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_WRITE_DISABLED_CAP = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_WRITE_ENABLED_CAP = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_WRITE_STATUS = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_LOCK_CAP = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_LOCK_STATUS = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_STICKY_WRITE = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_MEMORY_MAPPED = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ERASE_POLARITY = 1 >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_CAP = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_2 = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_4 = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_8 = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_16 = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_32 = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_64 = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_128 = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_256 = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_512 = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_1K = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_2K = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_4K = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_8K = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_16K = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_32K = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_ALIGNMENT_64K = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_READ_LOCK_CAP = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_READ_LOCK_STATUS = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_WRITE_LOCK_CAP = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_WRITE_LOCK_STATUS = TRUE >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_FVB2_ALIGNMENT = 8 >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo [files] >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_FILE_NAME = $(BUILD_DIR)\MeFwExt__.pkg >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_FILE_NAME = $(BUILD_DIR)\MeFwCapsuleHdr__.pkg >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_FILE_NAME = $(BUILD_DIR)\MeFwCapFid__.pkg >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_FILE_NAME = $(BUILD_DIR)\MeFwVer__.pkg >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf + echo EFI_FILE_NAME = $(BUILD_DIR)\MeFwLayout__.pkg >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf +!IF $(CREATE_FWCAPSULE) == 1 + echo EFI_FILE_NAME = $(BUILD_DIR)\FWkey__.pkg >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf +!ENDIF + echo EFI_FILE_NAME = $(BUILD_DIR)\MeFwRegion__.pkg >> $(BUILD_DIR)\FV_MEFWCAP_VOL.inf +!IF $(PI_SPECIFICATION_VERSION) >= 0x00010000 + $(FWBUILD) $(UNSIGNED_MEFW_CAPSULE) /f $(BUILD_DIR)\FV_MEFWCAP_VOL.inf /p 1.0 +!ELSE + $(FWBUILD) $(UNSIGNED_MEFW_CAPSULE) /f $(BUILD_DIR)\FV_MEFWCAP_VOL.inf +!ENDIF + if exist $(BIOS_MEFW_CAPSULE_FILE) @del $(BIOS_MEFW_CAPSULE_FILE) + if exist $(MEFW_CAPSULE_FILE) @del $(MEFW_CAPSULE_FILE) + +End : CombineFwCapsule +BUILD_ME : SignMeFwCapsule + +ME_FW_LAYOUT_EX = $(BUILD_DIR)\MeFwLayoutEx.bin + +CombineFwCapsule : + $(SILENT)copy /b $(UNSIGNED_BIOS_ROM)+$(UNSIGNED_MEFW_CAPSULE) $(UNSIGNED_MEFW_CAPSULE)2 + +$(ME_FW_LAYOUT_EX) : $(UNSIGNED_MEFW_CAPSULE) + @if not exist $@ $(FWBUILD) $(UNSIGNED_MEFW_CAPSULE) /s /m $(ME_FW_LAYOUT_EX) + +!IF "$(MEFWUPDLCL_ON_SHARKBAY_PLATFORM)"=="0" +SignMeFwCapsule : $(UNSIGNED_BIOS_ROM) $(ROM_LAYOUT_EX) MeFwFv $(ME_FW_LAYOUT_EX) +!ELSE +SignMeFwCapsule : $(UNSIGNED_BIOS_ROM) $(ROM_LAYOUT_EX) MeFwFv $(ME_FW_LAYOUT_EX) CombineFwCapsule +!ENDIF + @echo ---------------------------------------------------------------- + @echo ----- create Signed BIOS + ME FW Capsule : "$(BIOS_MEFW_CAPSULE_FILE)" ------ + @echo ---------------------------------------------------------------- +!IF !EXIST($(FWpriv)) || ("$(FWCAPSULE_CERT_FORMAT)"=="0" && !EXIST($(FWrootKey))) + @echo ----- WARNING!!! Missing RSA private key FWpriv=$(FWpriv) to sign BIOS + ME FW Capsule image. +!ELSE + $(CRYPTCON) -c2 -y -r$(ROM_LAYOUT_EX) -l$(FWCAPSULE_MAX_HDR_SIZE) -f $(UNSIGNED_MEFW_CAPSULE)2 -o $(UNSIGNED_MEFW_CAPSULE)2 + $(CRYPTCON) $(CRYPTOCON_CMDLINE_MEFWCAP) -f $(UNSIGNED_MEFW_CAPSULE)2 -o $(BIOS_MEFW_CAPSULE_FILE) +!ENDIF + @echo ---------------------------------------------------------------- + @echo ----- create Signed ME FW Capsule : "$(MEFW_CAPSULE_FILE)" ------------- + @echo ---------------------------------------------------------------- +!IF !EXIST($(FWpriv)) || ("$(FWCAPSULE_CERT_FORMAT)"=="0" && !EXIST($(FWrootKey))) + @echo ----- WARNING!!! Missing RSA private key FWpriv=$(FWpriv) to sign ME FW Capsule image. +!ELSE + $(CRYPTCON) -c2 -y -r$(ME_FW_LAYOUT_EX) -l$(FWCAPSULE_MAX_HDR_SIZE) -f $(UNSIGNED_MEFW_CAPSULE) -o $(UNSIGNED_MEFW_CAPSULE).Sig + $(CRYPTCON) $(CRYPTOCON_CMDLINE_MEFWCAP) -f $(UNSIGNED_MEFW_CAPSULE).Sig -o $(MEFW_CAPSULE_FILE) +!ENDIF + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2014, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsule.sdl b/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsule.sdl new file mode 100644 index 0000000..7ee2650 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsule.sdl @@ -0,0 +1,115 @@ +TOKEN + Name = MeFwCapsule_SUPPORT + Value = 1 + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Help = "Main switch to enable MeFwCapsule support in Project" + Master = Yes + Token = "MEFwUpdLcl_SUPPORT" "=" "1" +End + +TOKEN + Name = "ME_BIN_FILE" + Value = "$(ROM_IMAGE_DIR)\ME\ME9.1_5M_Production.BIN" + TokenType = Expression + TargetH = Yes + TargetMAK = Yes +End + +TOKEN + Name = "ME_FW_IMAGE_VERSION" + Value = "{9, 1, 25, 1005}" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "FV_MEFWCAP_SIZE" + Value = "0x400000" + TokenType = Integer + TargetH = Yes + TargetMAK = Yes +End + +TOKEN + Name = "BIOS_MEFW_CAPSULE_FILE" + Value = "BIOSMEFW.CAP" + Help = "File name of the BIOS + ME FW image to be signed." + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "MEFW_CAPSULE_FILE" + Value = "MEFW.CAP" + Help = "File name of the ME FW image to be signed." + TokenType = Expression + TargetMAK = Yes +End + +MODULE + Help = "Includes MeFwCapsule.mak to Project" + File = "MeFwCapsule.mak" +End + +PATH + Name = "MeFwCapsule_DIR" +End + +TOKEN + Name = "UNSIGNED_MEFW_CAPSULE" + Value = "$(BUILD_DIR)\FV_MEFWCAP.fv" + Help = "File name of the BIOS image to be signed." + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "CRYPTOCON_CMDLINE_MEFWCAP" + Value = "-c $(FWrootKey) -k $(FWpriv) -n -y -l $(FWCAPSULE_MAX_HDR_SIZE) -q -r2" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "FV_MEFWCAP_BASE" + Value = "0xFFFFFFFF-$(FV_MEFWCAP_SIZE)+1" + Help = "Number of Block used for ROMHOLE" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes +End + +TOKEN + Name = "FV_MEFWCAP_BLOCK_SIZE" + Value = "0x1000" + Help = "Size of Block used for ROMHOLE" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes +End + +TOKEN + Name = "FV_MEFWCAP_NUMBER_OF_BLOCK" + Value = "$(FV_MEFWCAP_SIZE) / $(FV_MEFWCAP_BLOCK_SIZE)" + Help = "Number of Block used for ROMHOLE" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes +End + +TOKEN + Name = "FWCAPSULE_IMAGE_SIZE" + Value = "$(FLASH_SIZE)+$(FWCAPSULE_MAX_HDR_SIZE)+$(FV_MEFWCAP_SIZE)" + TokenType = Integer + TargetH = Yes + Token = "MeFwCapsule_SUPPORT" "=" "1" +End + +ELINK + Name = "$(BUILD_DIR)\MeFwCapsulePei.ffs" + Parent = "FV_BB" + #Priority = 10 + InvokeOrder = AfterParent +End
\ No newline at end of file diff --git a/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsulePei.c b/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsulePei.c new file mode 100644 index 0000000..db54c27 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsulePei.c @@ -0,0 +1,185 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2015, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* +/** @file MeFwCapsulePei.c + ME FW Capsule Update Pei driver. +**/ +//********************************************************************** +//---------------------------------------------------------------------------- +// Includes +// Statements that include other files +#include <PEI.h> +#include <AmiPeiLib.h> +#include <FlashUpd.h> +#include <Token.h> +#include <PPI\NBPPI.h> +#include <FlashUpd.h> +#include <AmiHobs.h> +//---------------------------------------------------------------------------- +// Function Externs +EFI_GUID mFlashUpdBootModePpiGuid = EFI_PEI_BOOT_IN_FLASH_UPDATE_MODE_PEIM_PPI; +EFI_GUID mAmiPeiBeforeMrcGuid = AMI_PEI_BEFORE_MRC_GUID; +EFI_GUID mAmiCapsuleHobGuid = AMI_CAPSULE_HOB_GUID; +//---------------------------------------------------------------------------- +// Local prototypes +EFI_STATUS +MeFwBootOnFlashUpdateNotify ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *NullPpi +); +EFI_STATUS +MeFwBeforeMrcNotify ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *NullPpi +); + +// PPI to be installed +static +EFI_PEI_NOTIFY_DESCRIPTOR +MeFwBootOnFlashUpdateNotifyList[] = { + { EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | \ + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, \ + &mFlashUpdBootModePpiGuid, MeFwBootOnFlashUpdateNotify }, +}; + +static +EFI_PEI_NOTIFY_DESCRIPTOR +MeFwBeforeMrcNotifyList[] = { + { EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | \ + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &mAmiPeiBeforeMrcGuid, MeFwBeforeMrcNotify } +}; + +//---------------------------------------------------------------------------- +// Local Variables + +//---------------------------------------------------------------------------- +// Function Definitions +#define R_PCH_ACPI_PM1_STS 0x00 +#define B_PCH_ACPI_PM1_STS_WAK 0x8000 +#define R_PCH_ACPI_PM1_CNT 0x04 +#define B_PCH_ACPI_PM1_CNT_SLP_TYP 0x00001C00 +#define R_PCH_RST_CNT 0xCF9 +#define V_PCH_RST_CNT_SOFTRESET 0x04 +#define V_PCH_RST_CNT_SOFTSTARTSTATE 0x00 + +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MeFwBootOnFlashUpdateNotify +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MeFwBootOnFlashUpdateNotify ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *NullPpi +) +{ + VOID *p; + + for ((*PeiServices)->GetHobList(PeiServices,&p); \ + !(FindNextHobByGuid(&mAmiCapsuleHobGuid, &p)); ) { + // When the gFlashUpdBootModePpi is installed, bios identify the Capsule Guid + // either APTIO FW or Windows FW Capsule, so, we just check the Capsule Length + // for determine whether contains the ME FW. + if ((((AMI_CAPSULE_HOB*)p)->CapsuleLength != FWCAPSULE_IMAGE_SIZE) && \ + (((AMI_CAPSULE_HOB*)p)->CapsuleLength != \ + (FV_MEFWCAP_SIZE + FWCAPSULE_MAX_HDR_SIZE))) continue; + // Clear Wake Status (WAK_STS) and Sleep Type (SLP_TYP) + IoWrite16(PM_BASE_ADDRESS + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_WAK); + IoWrite16(PM_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, \ + IoRead16(PM_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT) & ~B_PCH_ACPI_PM1_CNT_SLP_TYP); + // Since, HECI interface not work if S3 resume path, to generate a Soft Reset + // to re-activate HECI. + IoWrite8(R_PCH_RST_CNT, V_PCH_RST_CNT_SOFTSTARTSTATE); + IoWrite8(R_PCH_RST_CNT, V_PCH_RST_CNT_SOFTRESET); + EFI_DEADLOOP() + } + return EFI_SUCCESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MeFwBeforeMrcNotify +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MeFwBeforeMrcNotify ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *NullPpi +) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + + Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode); + if (EFI_ERROR(Status) || (BootMode != BOOT_ON_S3_RESUME)) return EFI_SUCCESS; + (*PeiServices)->NotifyPpi (PeiServices, MeFwBootOnFlashUpdateNotifyList); + return EFI_SUCCESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Procedure: MeFwCapsulePeiEntry +// +// Description: +// +// Input: +// +// Output: +// +// Returns: +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MeFwCapsulePeiEntry ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices +) +{ + (*PeiServices)->NotifyPpi (PeiServices, MeFwBeforeMrcNotifyList); + return EFI_SUCCESS; +} +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2015, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsulePei.dxs b/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsulePei.dxs new file mode 100644 index 0000000..16c6253 --- /dev/null +++ b/Chipset/eM/ME/MEUD/MeFwCapsule/MeFwCapsulePei.dxs @@ -0,0 +1,3 @@ +DEPENDENCY_START + TRUE +DEPENDENCY_END
\ No newline at end of file |