diff options
| author | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
|---|---|---|
| committer | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
| commit | b7c51c9cf4864df6aabb99a1ae843becd577237c (patch) | |
| tree | eebe9b0d0ca03062955223097e57da84dd618b9a /ReferenceCode/AcpiTables | |
| download | zprj-master.tar.xz | |
Diffstat (limited to 'ReferenceCode/AcpiTables')
169 files changed, 35701 insertions, 0 deletions
diff --git a/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.c b/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.c new file mode 100644 index 0000000..94d2a90 --- /dev/null +++ b/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.c @@ -0,0 +1,67 @@ +/** @file + ACPI RC FVI DXE driver + +@copyright + Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +/// +/// External include files do NOT need to be explicitly specified in real EDKII +/// environment +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "AcpiFvi.h" +#endif /// EDK_RELEASE_VERSION + +FVI_ELEMENT_AND_FUNCTION mAcpiFviElementsData[] = { + { + DEFAULT_FVI_ELEMENT_DATA (ACPI), + NULL + } +}; + +FVI_DATA_HUB_CALLBACK_CONTEXT mAcpiFviVersionData = { + MISC_SUBCLASS_FVI_HEADER_ENTRY (ACPI), + mAcpiFviElementsData, +}; + +UINTN mAcpiFviElements = sizeof (mAcpiFviElementsData) / sizeof (FVI_ELEMENT_AND_FUNCTION); + +EFI_STATUS +AcpiFviEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +/** +@brief + The entry-point of ACPI RC FVI DXE driver + + @param[in] ImageHandle - Standard entry point parameter. + @param[in] SystemTable - Standard entry point parameter. + + @retval EFI_STATUS +**/ +{ + + InitFviDataHubCbContext ( + ACPI_FVI_SMBIOS_TYPE, + (UINT8) mAcpiFviElements, + &mAcpiFviVersionData + ); + + CreateRcFviDatahub (&mAcpiFviVersionData); + + return EFI_SUCCESS; +} diff --git a/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.cif b/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.cif new file mode 100644 index 0000000..54efa3d --- /dev/null +++ b/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.cif @@ -0,0 +1,13 @@ +<component> + name = "AcpiFvi" + category = ModulePart + LocalRoot = "ReferenceCode\AcpiTables\AcpiFvi\" + RefName = "AcpiFvi" +[files] +"AcpiFvi.sdl" +"AcpiFvi.mak" +"AcpiFvi.c" +"AcpiFvi.dxs" +"AcpiFvi.h" +"AcpiFvi.inf" +<endComponent> diff --git a/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.dxs b/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.dxs new file mode 100644 index 0000000..3b352ff --- /dev/null +++ b/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.dxs @@ -0,0 +1,41 @@ +/** @file + Dependency expression source file. + +@copyright + Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ + + +// +// Common for R8 and R9 codebase +// +#include "AutoGen.h" +#include "DxeDepex.h" + +// +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase; +// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase. +// +#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB) +#include "EfiDepex.h" +#include EFI_PROTOCOL_DEFINITION (DataHub) +#endif + +DEPENDENCY_START + EFI_DATA_HUB_PROTOCOL_GUID +DEPENDENCY_END + diff --git a/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.h b/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.h new file mode 100644 index 0000000..09e38e6 --- /dev/null +++ b/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.h @@ -0,0 +1,28 @@ +/** @file + Definitions for ACPI RC FVI DXE driver + +@copyright + Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _ACPI_RC_FVI_H_ +#define _ACPI_RC_FVI_H_ +#include "EdkIIGlueDxe.h" +#include "RcFviDxeLib.h" +#include EFI_PROTOCOL_PRODUCER (AcpiInfo) + +#define ACPI_FVI_STRING "Reference Code - ACPI" +#define ACPI_FVI_SMBIOS_TYPE 0xDD ///< Default value +#define ACPI_FVI_SMBIOS_INSTANCE 0x01 +#endif diff --git a/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.inf b/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.inf new file mode 100644 index 0000000..21873da --- /dev/null +++ b/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.inf @@ -0,0 +1,80 @@ +## @file +# Component description file for ACPI RC FVI DXE driver +# +#@copyright +# Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +[defines] +BASE_NAME = AcpiFvi +FILE_GUID = D7E31ECB-0A17-4529-9B84-C529DE8E1C0E +COMPONENT_TYPE = BS_DRIVER + +[sources.common] + AcpiFvi.c + AcpiFvi.h +# +# Edk II Glue Driver Entry Point +# + EdkIIGlueDxeDriverEntryPoint.c + +[includes.common] +# +# EDK II Glue Library utilizes some standard headers from EDK +# + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Framework/Include + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include/Library + $(EFI_SOURCE)/$(PROJECT_ACPI_ROOT) + +[libraries.common] + EfiProtocolLib + EdkProtocolLib + EdkFrameworkProtocolLib + EdkIIGlueBaseIoLibIntrinsic + EdkIIGlueDxeReportStatusCodeLib + EdkIIGlueDxeDebugLibReportStatusCode + EdkIIGlueUefiBootServicesTableLib + EdkIIGlueUefiRuntimeServicesTableLib + EdkIIGlueUefiLib + EdkIIGlueBasePciLibPciExpress + EdkIIGlueBasePciExpressLib + EdkIIGlueDxeServicesTableLib + RcFviDxeLib + AcpiProtocolLib + +[nmake.common] + IMAGE_ENTRY_POINT=_ModuleEntryPoint + DPX_SOURCE=AcpiFvi.dxs +# +# Module Entry Point +# + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=AcpiFviEntryPoint + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \ + -D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \ + -D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \ + -D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \ + -D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \ + -D __EDKII_GLUE_UEFI_LIB__ \ + -D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \ + -D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ diff --git a/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.mak b/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.mak new file mode 100644 index 0000000..ce67b84 --- /dev/null +++ b/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.mak @@ -0,0 +1,56 @@ +#--------------------------------------------------------------------------- +# Create AcpiFvi Driver +#--------------------------------------------------------------------------- +EDK : AcpiFvi + +AcpiFvi: $(BUILD_DIR)\AcpiFvi.mak AcpiFviBin + +$(BUILD_DIR)\AcpiFvi.mak : $(AcpiFvi_DIR)\$(@B).cif $(AcpiFvi_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(AcpiFvi_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + + +AcpiFvi_DEFINES =$(MY_DEFINES)\ + /D "__EDKII_GLUE_MODULE_ENTRY_POINT__=AcpiFviEntryPoint" \ + /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \ + /D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \ + /D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \ + /D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__\ + /D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \ + /D __EDKII_GLUE_UEFI_LIB__\ + /D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \ + /D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ \ + + +AcpiFvi_LIB_LINKS =\ + $(EFIPROTOCOLLIB)\ + $(EDKFRAMEWORKPROTOCOLLIB)\ + $(EdkIIGlueBaseIoLibIntrinsic_LIB)\ + $(EdkIIGlueDxeReportStatusCodeLib_LIB)\ + $(EdkIIGlueDxeDebugLibReportStatusCode_LIB)\ + $(EdkIIGlueUefiBootServicesTableLib_LIB)\ + $(EdkIIGlueUefiRuntimeServicesTableLib_LIB)\ + $(EdkIIGlueDxeServicesTableLib_LIB)\ + $(EdkIIGlueUefiLib_LIB)\ + $(EdkIIGlueBasePciLibPciExpress_LIB)\ + $(EdkIIGlueBasePciExpressLib_LIB)\ + $(RcFviDxeLib_LIB)\ + $(EDKPROTOCOLLIB)\ + $(AcpiProtocolLib_LIB)\ + +AcpiFvi_INCLUDES=\ + /I ReferenceCode\AcpiTables\ + $(EdkIIGlueLib_INCLUDES)\ + $(INTEL_PCH_INCLUDES)\ + +AcpiFviBin: $(AcpiFvi_LIB_LINKS) + $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\ + /f $(BUILD_DIR)\AcpiFvi.mak all \ + "MY_INCLUDES=$(AcpiFvi_INCLUDES)"\ + "MY_DEFINES=$(AcpiFvi_DEFINES)"\ + GUID=D7E31ECB-0A17-4529-9B84-C529DE8E1C0E\ + ENTRY_POINT=_ModuleEntryPoint \ + TYPE=BS_DRIVER\ + EDKIIModule=DXEDRIVER\ + DEPEX1=$(AcpiFvi_DIR)\AcpiFvi.dxs\ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\ + COMPRESS=1 diff --git a/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.sdl b/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.sdl new file mode 100644 index 0000000..2fd8ad0 --- /dev/null +++ b/ReferenceCode/AcpiTables/AcpiFvi/AcpiFvi.sdl @@ -0,0 +1,24 @@ +TOKEN + Name = "AcpiFvi_SUPPORT" + Value = "1" + Help = "Main switch to enable AcpiFvi support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes +End + +PATH + Name = "AcpiFvi_DIR" +End + +MODULE + File = "AcpiFvi.mak" + Help = "Includes AcpiFvi.mak to Project" +End + +ELINK + Name = "$(BUILD_DIR)\AcpiFvi.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/Cppc/AcpiTables/Cpc.asl b/ReferenceCode/AcpiTables/Cppc/AcpiTables/Cpc.asl new file mode 100644 index 0000000..2099515 --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/AcpiTables/Cpc.asl @@ -0,0 +1,298 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + Cpc.asl + +Abstract: + + Intel ACPI Reference Code for ACPI 5.0 Collaborative Processor Performance Control (CPPC) + +--*/ + +DefinitionBlock ( + "Cpc.aml", + "SSDT", + 1, + "Cpc_Tabl", + "Cpc_Tabl", + 0x1000 ) +{ + +External(\_PR.CPU0, ProcessorObj) +External(\_PR.CPU1, ProcessorObj) +External(\_PR.CPU2, ProcessorObj) +External(\_PR.CPU3, ProcessorObj) +External(\_PR.CPU4, ProcessorObj) +External(\_PR.CPU5, ProcessorObj) +External(\_PR.CPU6, ProcessorObj) +External(\_PR.CPU7, ProcessorObj) + +// _CPC (Continuous Performance Control) +// _CPC is a per-processor ACPI object that declares an interface for OSPM to +// transition the processor into a performance state based on a continuous range +// of allowable values. Each CPPC register is described in a Generic Register +// Descriptor format and maps to an unique PCC shared memory +// location. For a complete description of _CPC object, refer to ACPI 5.0 +// specification, section 8.4.5.1. +// Arguments: (0) +// None +// Return Value: +// A Package of elements in the following format +// +// Package +// { +// NumEntries, // Integer +// Revision, // Integer +// HighestPerformance, // Generic Register Descriptor +// NominalPerformance, // Generic Register Descriptor +// LowestNonlinearPerformance, // Generic Register Descriptor +// LowestPerformance, // Generic Register Descriptor +// GuaranteedPerformanceRegister, // Generic Register Descriptor +// DesiredPerformanceRegister, // Generic Register Descriptor +// MinimumPerformanceRegister, // Generic Register Descriptor +// MaximumPerformanceRegister, // Generic Register Descriptor +// PerformanceReductionToleranceRegister,// Generic Register Descriptor +// TimeWindowRegister, // Generic Register Descriptor +// CounterWraparoundTime, // Generic Register Descriptor +// NominalCounterRegister, // Generic Register Descriptor +// DeliveredCounterRegister, // Generic Register Descriptor +// PerformanceLimitedRegister, // Generic Register Descriptor +// EnableRegister // Generic Register Descriptor +// } + +Scope(\_PR.CPU0) +{ + Name(_CPC, Package() + { + 17, // Number of entries + 1, // Revision + // + // Describe processor capabilities + // + ResourceTemplate() {Register(PCC, 32, 0, 0x0000, 0)}, // HighestPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x0004, 0)}, // NominalPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x0008, 0)}, // LowestNonlinearPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x000C, 0)}, // LowestPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x0010, 0)}, // GuaranteedPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0014, 0)}, // DesiredPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0018, 0)}, // MinimumPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x001C, 0)}, // MaximumPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0020, 0)}, // PerformanceReductionToleranceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0024, 0)}, // TimeWindowRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0028, 0)}, // CounterWraparoundTime + ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // NominalCounterRegister + ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // DeliveredCounterRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x003C, 0)}, // PerformanceLimitedRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0040, 0)} // EnableRegister + }) +}// end Scope(\_PR.CPU0) + +Scope(\_PR.CPU1) +{ + Name(_CPC, Package() + { + 17, // Number of entries + 1, // Revision + // + // Describe processor capabilities + // + ResourceTemplate() {Register(PCC, 32, 0, 0x0064, 0)}, // HighestPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x0068, 0)}, // NominalPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x006C, 0)}, // LowestNonlinearPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x0070, 0)}, // LowestPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x0074, 0)}, // GuaranteedPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0078, 0)}, // DesiredPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x007C, 0)}, // MinimumPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0080, 0)}, // MaximumPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0084, 0)}, // PerformanceReductionToleranceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0088, 0)}, // TimeWindowRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x008C, 0)}, // CounterWraparoundTime + ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // NominalCounterRegister + ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // DeliveredCounterRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x00A0, 0)}, // PerformanceLimitedRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x00A4, 0)} // EnableRegister + }) +}// end Scope(\_PR.CPU1) + +Scope(\_PR.CPU2) +{ + Name(_CPC, Package() + { + 17, // Number of entries + 1, // Revision + // + // Describe processor capabilities + // + ResourceTemplate() {Register(PCC, 32, 0, 0x00C8, 0)}, // HighestPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x00CC, 0)}, // NominalPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x00D0, 0)}, // LowestNonlinearPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x00D4, 0)}, // LowestPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x00D8, 0)}, // GuaranteedPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x00DC, 0)}, // DesiredPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x00E0, 0)}, // MinimumPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x00E4, 0)}, // MaximumPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x00E8, 0)}, // PerformanceReductionToleranceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x00EC, 0)}, // TimeWindowRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x00F0, 0)}, // CounterWraparoundTime + ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // NominalCounterRegister + ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // DeliveredCounterRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0104, 0)}, // PerformanceLimitedRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0108, 0)} // EnableRegister + }) +}// end Scope(\_PR.CPU2) + +Scope(\_PR.CPU3) +{ + Name(_CPC, Package() + { + 17, // Number of entries + 1, // Revision + // + // Describe processor capabilities + // + ResourceTemplate() {Register(PCC, 32, 0, 0x012C, 0)}, // HighestPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x0130, 0)}, // NominalPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x0134, 0)}, // LowestNonlinearPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x0138, 0)}, // LowestPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x013C, 0)}, // GuaranteedPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0140, 0)}, // DesiredPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0144, 0)}, // MinimumPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0148, 0)}, // MaximumPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x014C, 0)}, // PerformanceReductionToleranceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0150, 0)}, // TimeWindowRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0154, 0)}, // CounterWraparoundTime + ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // NominalCounterRegister + ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // DeliveredCounterRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0168, 0)}, // PerformanceLimitedRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x016C, 0)} // EnableRegister + }) +}// end Scope(\_PR.CPU3) + +Scope(\_PR.CPU4) +{ + Name(_CPC, Package() + { + 17, // Number of entries + 1, // Revision + // + // Describe processor capabilities + // + ResourceTemplate() {Register(PCC, 32, 0, 0x0190, 0)}, // HighestPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x0194, 0)}, // NominalPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x0198, 0)}, // LowestNonlinearPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x019C, 0)}, // LowestPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x01A0, 0)}, // GuaranteedPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x01A4, 0)}, // DesiredPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x01A8, 0)}, // MinimumPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x01AC, 0)}, // MaximumPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x01B0, 0)}, // PerformanceReductionToleranceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x01B4, 0)}, // TimeWindowRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x01B8, 0)}, // CounterWraparoundTime + ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // NominalCounterRegister + ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // DeliveredCounterRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x01CC, 0)}, // PerformanceLimitedRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x01D0, 0)} // EnableRegister + }) +}// end Scope(\_PR.CPU4) + +Scope(\_PR.CPU5) +{ + Name(_CPC, Package() + { + 17, // Number of entries + 1, // Revision + // + // Describe processor capabilities + // + ResourceTemplate() {Register(PCC, 32, 0, 0x01F4, 0)}, // HighestPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x01F8, 0)}, // NominalPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x01FC, 0)}, // LowestNonlinearPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x0200, 0)}, // LowestPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x0204, 0)}, // GuaranteedPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0208, 0)}, // DesiredPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x020C, 0)}, // MinimumPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0210, 0)}, // MaximumPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0214, 0)}, // PerformanceReductionToleranceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0218, 0)}, // TimeWindowRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x021C, 0)}, // CounterWraparoundTime + ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // NominalCounterRegister + ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // DeliveredCounterRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0230, 0)}, // PerformanceLimitedRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0234, 0)} // EnableRegister + }) +}// end Scope(\_PR.CPU5) + +Scope(\_PR.CPU6) +{ + Name(_CPC, Package() + { + 17, // Number of entries + 1, // Revision + // + // Describe processor capabilities + // + ResourceTemplate() {Register(PCC, 32, 0, 0x0258, 0)}, // HighestPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x025C, 0)}, // NominalPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x0260, 0)}, // LowestNonlinearPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x0264, 0)}, // LowestPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x0268, 0)}, // GuaranteedPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x026C, 0)}, // DesiredPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0270, 0)}, // MinimumPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0274, 0)}, // MaximumPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0278, 0)}, // PerformanceReductionToleranceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x027C, 0)}, // TimeWindowRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0280, 0)}, // CounterWraparoundTime + ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // NominalCounterRegister + ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // DeliveredCounterRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0294, 0)}, // PerformanceLimitedRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x0298, 0)} // EnableRegister + }) +}// end Scope(\_PR.CPU6) + +Scope(\_PR.CPU7) +{ + Name(_CPC, Package() + { + 17, // Number of entries + 1, // Revision + // + // Describe processor capabilities + // + ResourceTemplate() {Register(PCC, 32, 0, 0x02BC, 0)}, // HighestPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x02C0, 0)}, // NominalPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x02C4, 0)}, // LowestNonlinearPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x02C8, 0)}, // LowestPerformance + ResourceTemplate() {Register(PCC, 32, 0, 0x02CC, 0)}, // GuaranteedPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x02D0, 0)}, // DesiredPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x02D4, 0)}, // MinimumPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x02D8, 0)}, // MaximumPerformanceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x02DC, 0)}, // PerformanceReductionToleranceRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x02E0, 0)}, // TimeWindowRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x02E4, 0)}, // CounterWraparoundTime + ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // NominalCounterRegister + ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // DeliveredCounterRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x02F8, 0)}, // PerformanceLimitedRegister + ResourceTemplate() {Register(PCC, 32, 0, 0x02FC, 0)} // EnableRegister + }) +}// end Scope(\_PR.CPU7) + +}// end of definition block diff --git a/ReferenceCode/AcpiTables/Cppc/AcpiTables/Cppc.asl b/ReferenceCode/AcpiTables/Cppc/AcpiTables/Cppc.asl new file mode 100644 index 0000000..ce2bc49 --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/AcpiTables/Cppc.asl @@ -0,0 +1,319 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + Cppc.asl + +Abstract: + + Intel ACPI Reference Code for ACPI 5.0 Collaborative Processor Performance Control (CPPC) + +--*/ + +#include "PowerMgmtDefinitions.h" + +DefinitionBlock ( + "Cppc.aml", + "SSDT", + 1, + "CppcTabl", + "CppcTabl", + 0x1000 ) +{ + +External(TCNT, IntObj) +External(OSYS, IntObj) +External(\PDC0, IntObj) +External(\_PR.CPU0, ProcessorObj) +External(\_PR.CPU0._PSS, MethodObj) +External(\_PR.CPU0._PPC, IntObj) +External(\_PR.CPU0._CPC, MethodObj) +External(\_PR.CPU0._TSS, MethodObj) +External(\_PR.CPU1, ProcessorObj) +External(\_PR.CPU2, ProcessorObj) +External(\_PR.CPU3, ProcessorObj) +External(\_PR.CPU4, ProcessorObj) +External(\_PR.CPU5, ProcessorObj) +External(\_PR.CPU6, ProcessorObj) +External(\_PR.CPU7, ProcessorObj) + +Scope(\_SB) +{ +// Define PCCD device so that we can load CPPC driver against this +// device. This driver will process PCC commands from OSPM in +// PCC Shared memory region. +Device(PCCD) +{ + +// +// These objects are patched during POST. +// +Name(PCCA, 0x80000000) // Address of PCC shared memory buffer, fixed up during POST +Name(PCCS, 0x80000000) // PCCA buffer size +Name(PENB, 0x80000000) // REQUIRED object. CPCC Enable/Disable. 1 = Enable, 0 = Disable. Also used by _OSC evaluation of CPPC support. + +Name(_HID, EISAID("INT340F")) +Name(_STR, Unicode ("Collaborative Processor Performance Control (CPPC)")) + + // _STA (Status) + // + // This object returns the current status of a device. + // Checks if Win8 or later is present. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If(LGreaterEqual(OSYS,2012)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + Name (TMPP, Package (){0x80000000,0x80000000}) + + // PADR (Pcc shared memory ADRess) + // + // This ACPI object evaluates to a package, containing the PCC Shared Memory 32-bit address and its size in bytes. + // This object will be evaluated by the Intel CPPC driver during its initialization. This object is REQUIRED. + // + // Arguments: (0) + // None + // Return Value: + // A package of 2 Integer (DWORD) elements: PCC Shared Memory Address and PCC Shared Memory Length. + // + Method(PADR) + { + Store(PCCA,Index (TMPP, 0)) + Store(PCCS,Index (TMPP, 1)) + Return(TMPP) + } + + // GPRN (Guaranteed Performance Register Notification) + // + // The purpose of this object is to notify OSPM on changes to CPPC Guaranteed Performance register. This object is REQUIRED. + // This object is evaluated by the CPPC driver dynamically whenever the CPPC driver changes the CPPC Guaranteed Performance register value. + // Upon evaluation, GPRN control method issues an ACPI notification on each processor device with notify code = 0x83 and + // OSPM processes the ACPI notification. + // + // Arguments: (0) + // None + // Return Value: + // None + // + Method(GPRN,0,Serialized) + { + Switch(ToInteger(TCNT)){ + Case(8){ + Notify(\_PR.CPU0, 0x83) + Notify(\_PR.CPU1, 0x83) + Notify(\_PR.CPU2, 0x83) + Notify(\_PR.CPU3, 0x83) + Notify(\_PR.CPU4, 0x83) + Notify(\_PR.CPU5, 0x83) + Notify(\_PR.CPU6, 0x83) + Notify(\_PR.CPU7, 0x83) + } + Case(4){ + Notify(\_PR.CPU0, 0x83) + Notify(\_PR.CPU1, 0x83) + Notify(\_PR.CPU2, 0x83) + Notify(\_PR.CPU3, 0x83) + } + Case(2){ + Notify(\_PR.CPU0, 0x83) + Notify(\_PR.CPU1, 0x83) + } + Default{ + Notify(\_PR.CPU0, 0x83) + } + } + } + + // PCFG (Platform Configuration) + // + // The purpose of this object is for platform to enable or disable EE P-States selection of frequency below P1. + // This method is REQUIRED if platform issues ACPI notification code 0x81 on CPPC device. + // This object is evaluated by the CPPC driver once during boot (to get boot-time selection) and dynamically + // whenever platform issues an ACPI notification (notify code = 0x81) to change optimization selection. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing CPPC optimization enables bitmap: + // Bit Value Description + // [0] 0 CPPC driver determines (based on OS power plan settings) when to enable EE P-States selection of frequency below P1. + // [0] 1 Disable EE P-States selection of frequency below P1. + // [31:1] 0 Reserved for future use + // + Name(PCFG,0) + + // _PTC (Processor Throttling Control) + // + // _PTC defines the processor throttling control interface. + // + // PDC0[2] = ACPI object indicating if OSPM is capable of direct access to On Demand throttling MSR + // + // Arguments: (0) + // None + // Return Value: + // A Package as described below + // + // Return Value Information + // Package { + // ControlRegister // Buffer (Resource Descriptor) + // StatusRegister // Buffer (Resource Descriptor) + // } + // + Method(_PTC,,,,PkgObj) + { + If(LAnd(CondRefOf(\PDC0),LNotEqual(\PDC0,0x80000000))) // is object present and initialized? + { + If(And(\PDC0, 0x0004)) { // does OS support MSR interface? + Return(Package() { + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} }) // if OS supports MSR interface + } Else { + Return(Package() { + ResourceTemplate(){Register(SystemIO, 5, 0, PCH_ACPI_PBLK)}, + ResourceTemplate(){Register(SystemIO, 5, 0, PCH_ACPI_PBLK)} }) // if OS support IO based interface + } + } Else { + Return(Package() { + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} }) // if object is not present or not initialized then return MSR interface + } + } + + // _PSS (Performance Supported States) + // + // This optional object indicates to OSPM the number of supported processor performance states that any given system can support. + // + // Arguments: (1) + // None + // Return Value: + // A variable-length Package containing a list of Pstate sub-packages as described below + // + // Return Value Information + // Package { + // PState [0] // Package - Performance state 0 + // .... + // PState [n] // Package - Performance state n + // } + // + // Each Pstate sub-Package contains the elements described below: + // Package { + // CoreFrequency // Integer (DWORD) + // Power // Integer (DWORD) + // Latency // Integer (DWORD) + // BusMasterLatency // Integer (DWORD) + // Control // Integer (DWORD) + // Status // Integer (DWORD) + // } + // + // Stub for the Actual CPU _PSS method. + // + Method(_PSS,,,,PkgObj) + { + If(CondRefOf(\_PR.CPU0._PSS)) + { // Ensure _PSS is present + Return(\_PR.CPU0._PSS()) + } Else { + Return(Package(){ + Package(){0,0,0,0,0,0}, + Package(){0,0,0,0,0,0}}) + } + } + + // _PPC (Performance Present Capabilities) + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the range of states supported + // 0 - States 0 through nth state are available (all states available) + // 1 - States 1 through nth state are available + // 2 - States 2 through nth state are available + // ... + // n - State n is available only + // + Method(_PPC) + { + If(CondRefOf(\_PR.CPU0._PPC)) + { // Ensure _PPC is present + Return(\_PR.CPU0._PPC) + } Else { + Return(0) + } + } + + // _TSS (Throttling Supported States) + // + // Arguments: (0) + // None + // Return Value: + // A variable-length Package containing a list of Tstate sub-packages as described below + // + // Return Value Information + // Package { + // TState [0] // Package - Throttling state 0 + // .... + // TState [n] // Package - Throttling state n + // } + // + // Each Tstate sub-Package contains the elements described below: + // Package { + // Percent // Integer (DWORD) + // Power // Integer (DWORD) + // Latency // Integer (DWORD) + // Control // Integer (DWORD) + // Status // Integer (DWORD) + // } + // + // Stub for the Actual CPU _TSS method. + // + Method(_TSS,,,,PkgObj) + { + If(CondRefOf(\_PR.CPU0._TSS)) + { // Ensure _TSS is present + Return(\_PR.CPU0._TSS()) + } Else { + Return(Package(){ + Package(){0,0,0,0,0}, + Package(){0,0,0,0,0}}) + } + } + + +} // End Device(PCCD) +} // End Scope(_SB) + +} diff --git a/ReferenceCode/AcpiTables/Cppc/AcpiTables/CppcAcpiTables.cif b/ReferenceCode/AcpiTables/Cppc/AcpiTables/CppcAcpiTables.cif new file mode 100644 index 0000000..54ee1aa --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/AcpiTables/CppcAcpiTables.cif @@ -0,0 +1,13 @@ +<component> + name = "CppcAcpiTables" + category = ModulePart + LocalRoot = "ReferenceCode\AcpiTables\Cppc\AcpiTables\" + RefName = "CppcAcpiTables" +[files] +"CppcAcpiTables.sdl" +"CppcAcpiTables.mak" +"Cppc.asl" +"CppcAcpiTables.inf" +"Pcct.asl" +"Cpc.asl" +<endComponent> diff --git a/ReferenceCode/AcpiTables/Cppc/AcpiTables/CppcAcpiTables.inf b/ReferenceCode/AcpiTables/Cppc/AcpiTables/CppcAcpiTables.inf new file mode 100644 index 0000000..f0333c7 --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/AcpiTables/CppcAcpiTables.inf @@ -0,0 +1,69 @@ +## @file +# Component description file for the ACPI tables +# +#@copyright +# Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# + + +[defines] +BASE_NAME = CppcAcpiTables +# +# If the value of this GUID is changed then make sure to change the corresponding GUID (CPPC_ACPI_TABLE_STORAGE_GUID) +# in CppcAcpiTableStorage.h. +# +FILE_GUID = 60E31DE1-03EC-492a-9598-65A3C50E0F6B +COMPONENT_TYPE = ACPITABLE +FFS_EXT = .ffs + +[sources.common] + Cppc.ASL + Pcct.ASL + Cpc.ASL + +[libraries.common] + +[includes.common] + . + $(EFI_SOURCE) + $(EFI_SOURCE)/Include + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EFI_SOURCE)/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include + +# +# Edk II Glue Library, some header are not included by R9 header so have to include +# + $(EFI_SOURCE) + $(EFI_SOURCE)/Framework + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Library + +[nmake.common] diff --git a/ReferenceCode/AcpiTables/Cppc/AcpiTables/CppcAcpiTables.mak b/ReferenceCode/AcpiTables/Cppc/AcpiTables/CppcAcpiTables.mak new file mode 100644 index 0000000..53c14cc --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/AcpiTables/CppcAcpiTables.mak @@ -0,0 +1,92 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2012, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: CppcAcpiTables.mak +# +# Description: MAke file to build Intel CPPC ACPI ASL components +# +#<AMI_FHDR_END> +#********************************************************************** +#----------------------------------------------------------------------- +# ASL compiler definition +#----------------------------------------------------------------------- +!IF "$(ACPIPLATFORM_ASL_COMPILER)"=="" +!ERROR It is an invalid path, please check your ASL compiler path. +!ENDIF + +IASL = $(ACPIPLATFORM_ASL_COMPILER) +#----------------------------------------------------------------------- +EDK : CPPCACPI + +ALLCPPCSEC = $(BUILD_DIR)\Cpc.sec\ + $(BUILD_DIR)\Cppc.sec\ + $(BUILD_DIR)\Pcct.sec + +CPPCACPI : $(BUILD_DIR)\CppcAcpiTables.ffs + +$(BUILD_DIR)\Cpc.aml : $(INTEL_CPC_ASL_FILE) + @cl /C /EP $(INTEL_CPC_ASL_FILE) > $(BUILD_DIR)\Cpc.asl + $(IASL) -p $(BUILD_DIR)\Cpc.aml $(BUILD_DIR)\Cpc.asl + +$(BUILD_DIR)\Cppc.aml : $(INTEL_CPPC_ASL_FILE) + @cl /C /EP $(PROJECT_CPU_INCLUDES) $(INTEL_CPPC_ASL_FILE) > $(BUILD_DIR)\Cppc.asl + $(IASL) -p $(BUILD_DIR)\Cppc.aml $(BUILD_DIR)\Cppc.asl + +$(BUILD_DIR)\Pcct.aml : $(INTEL_PCCT_ASL_FILE) + @cl /C /EP $(INTEL_PCCT_ASL_FILE) > $(BUILD_DIR)\Pcct.asl + $(IASL) -p $(BUILD_DIR)\Pcct.aml $(BUILD_DIR)\Pcct.asl + +$(BUILD_DIR)\Cpc.sec: $(BUILD_DIR)\Cpc.aml + $(GENSECTION) -I $** -O $@ -S EFI_SECTION_RAW + +$(BUILD_DIR)\Cppc.sec: $(BUILD_DIR)\Cppc.aml + $(GENSECTION) -I $** -O $@ -S EFI_SECTION_RAW + +$(BUILD_DIR)\Pcct.sec: $(BUILD_DIR)\Pcct.aml + $(GENSECTION) -I $** -O $@ -S EFI_SECTION_RAW + +$(BUILD_DIR)\CppcAcpiTables.ffs: $(ALLCPPCSEC) $(INTEL_CPPC_ACPI_TABLE_DIR)\CppcAcpiTables.mak + $(GENFFSFILE) -B $(BUILD_DIR) -V -o $@ -P1 <<$(BUILD_DIR)\CppcAcpiTables.pkg +PACKAGE.INF +[.] +BASE_NAME = CppcAcpiTables +FFS_FILEGUID = 60E31DE1-03EC-492a-9598-65A3C50E0F6B +FFS_FILETYPE = EFI_FV_FILETYPE_FREEFORM +FFS_ATTRIB_CHECKSUM = TRUE + +IMAGE_SCRIPT = +{ + Compress (dummy) { + $(PROJECT_DIR)\$(BUILD_DIR)\Cpc.sec + $(PROJECT_DIR)\$(BUILD_DIR)\Cppc.sec + $(PROJECT_DIR)\$(BUILD_DIR)\Pcct.sec + } +} +<<KEEP +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2012, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/AcpiTables/Cppc/AcpiTables/CppcAcpiTables.sdl b/ReferenceCode/AcpiTables/Cppc/AcpiTables/CppcAcpiTables.sdl new file mode 100644 index 0000000..a67daec --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/AcpiTables/CppcAcpiTables.sdl @@ -0,0 +1,53 @@ +TOKEN + Name = "CppcAcpiTables_SUPPORT" + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable CppcAcpiTables support in Project" +End + +MODULE + Help = "Includes CppcAcpiTables.mak to Project" + File = "CppcAcpiTables.mak" +End + +PATH + Name = "INTEL_CPPC_ACPI_TABLE_DIR" +End + +TOKEN + Name = "INTEL_CPC_ASL_FILE" + Value = "$(INTEL_CPPC_ACPI_TABLE_DIR)\Cpc.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_CPPC_ASL_FILE" + Value = "$(INTEL_CPPC_ACPI_TABLE_DIR)\Cppc.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_PCCT_ASL_FILE" + Value = "$(INTEL_CPPC_ACPI_TABLE_DIR)\Pcct.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "CPPC_ASL_COMPILER" + Value = "$(INTEL_CPPC_DIR)\iasl.exe" + Help = "ASL Optimizing Compiler version 20120711-32 [Jul 11 2012]" + TokenType = Expression + TargetMAK = Yes +End + +ELINK + Name = "$(BUILD_DIR)\CppcAcpiTables.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/Cppc/AcpiTables/Pcct.asl b/ReferenceCode/AcpiTables/Cppc/AcpiTables/Pcct.asl new file mode 100644 index 0000000..d7ea368 --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/AcpiTables/Pcct.asl @@ -0,0 +1,54 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + Pcct.asl + +Abstract: + + Intel ACPI Reference Code for ACPI 5.0 Platform Communications Channel Table (PCCT) + +--*/ + +DefinitionBlock ( + "Pcct.aml", + "PCCT", + 5, + "PcctTa", + "PcctTabl", + 0x1000 ) +{ + +/// The 12 byte EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER structure is patched during POST. +/// The 62 byte EFI_ACPI_5_0_PCCT_SUBSPACE_GENERIC structure is patched during POST. +/// Allocate a buffer of 64 bytes plus the size of the 10 byte Name structure for a total of 74 bytes. +/// +Name(PCCT,Buffer() { +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 10 +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 20 +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 30 +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 40 +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 50 +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 60 +0x00, 0x00, 0x00, 0x00 // 64 +}) + +}// end DefinitionBlock diff --git a/ReferenceCode/AcpiTables/Cppc/Cppc.cif b/ReferenceCode/AcpiTables/Cppc/Cppc.cif new file mode 100644 index 0000000..846f7ed --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/Cppc.cif @@ -0,0 +1,14 @@ +<component> + name = "Intel CPPC" + category = eModule + LocalRoot = "ReferenceCode\AcpiTables\Cppc\" + RefName = "Intel CPPC" +[files] +"Cppc.sdl" +"ReleaseNotes.chm" +"iasl.exe" +[parts] +"CppcDxe" +"CppcAcpiTables" +"CppcGuidLib" +<endComponent> diff --git a/ReferenceCode/AcpiTables/Cppc/Cppc.sdl b/ReferenceCode/AcpiTables/Cppc/Cppc.sdl new file mode 100644 index 0000000..f9413eb --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/Cppc.sdl @@ -0,0 +1,26 @@ +TOKEN + Name = "CPPC_SUPPORT" + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Master = Yes + Help = "Main switch to enable CPPC supppory in Project" +End + +PATH + Name = "INTEL_CPPC_DIR" + Help = "Intel DPTF source directory" +End + +ELINK + Name = "CPPC_INCLUDES" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "/I$(INTEL_CPPC_DIR)" + Parent = "CPPC_INCLUDES" + InvokeOrder = AfterParent +End
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/Cppc/Dxe/Cppc.c b/ReferenceCode/AcpiTables/Cppc/Dxe/Cppc.c new file mode 100644 index 0000000..9da9b1a --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/Dxe/Cppc.c @@ -0,0 +1,863 @@ +/** @file + This DXE driver configures and supports Collaborative Processor Performance Control (CPPC). + +@copyright + Copyright (c) 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement + +**/ +#include "Cppc.h" + +ACPI_PLATFORM_POLICY_PROTOCOL *mAcpiPlatformPolicyProtocol; + +extern EFI_RUNTIME_SERVICES *gRT; +extern EFI_BOOT_SERVICES *gBS; + +EFI_PHYSICAL_ADDRESS mCppcBaseAddressMem = 0; + +/// +/// Driver entry point +/// +EFI_DRIVER_ENTRY_POINT (InitializeCppc) + +EFI_STATUS +InitializeCppc ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +/** +@brief + Cppc DXE support. + + @param[in] ImageHandle - Pointer to the loaded image protocol for this driver + @param[in] SystemTable - Pointer to the EFI System Table + + @retval EFI_SUCCESS - The driver installed/initialized correctly. +**/ +{ + EFI_STATUS Status; + VOID *MemoryPointer; + UINT64 MsrValue; + + gRT = SystemTable->RuntimeServices; + gBS = SystemTable->BootServices; + + /// + /// Initialize the EFI Runtime Library + /// + DxeInitializeDriverLib (ImageHandle, SystemTable); + + /// + /// S3 boot script + /// + INITIALIZE_SCRIPT (ImageHandle, SystemTable); + + /// + /// Locate platform configuration information and copy it to a global variable. + /// + Status = gBS->LocateProtocol ( + &gAcpiPlatformPolicyProtocolGuid, + NULL, + (VOID **) &mAcpiPlatformPolicyProtocol + ); + if (EFI_ERROR(Status)) { + DEBUG ((EFI_D_ERROR, "CPPC: No Platform Policy Protocol available.\n")); + ASSERT_EFI_ERROR(Status); + return Status; + } else { + DEBUG ((EFI_D_ERROR, "CPPC: Platform Policy Protocol is loaded.\n")); + } + + /// + /// Enable or disable CPPC depending on platform policy. + /// + if (mAcpiPlatformPolicyProtocol->EnableCppc == 0) { + DEBUG ((EFI_D_ERROR, "CPPC is disabled by platform policy. \n")); + return EFI_SUCCESS; + } + + /// + /// Check if Haswell traditional, Haswell ULT or Crystal Well CPU. + /// + if(!(IsCpuSupported())){ + DEBUG ((EFI_D_ERROR, "CPPC not supported in this CPU. \n")); + return EFI_SUCCESS; + } + + /// + /// Check if Mobile CPU. + /// + if(!(IS_SA_DEVICE_ID_MOBILE (McD0PciCfg16 (R_SA_MC_DEVICE_ID)))) { + DEBUG ((EFI_D_ERROR, "CPPC not supported in this CPU. (not mobile) \n")); + return EFI_SUCCESS; + } + + /// + /// Check if processor supports EE Policy capability. + /// + MsrValue = EfiReadMsr (EFI_MSR_POWER_CTL); + if (((UINT32)MsrValue & BIT18) != BIT18) { + DEBUG ((EFI_D_ERROR, "CPPC not supported in this CPU. (no Energy Efficient Policy capability) \n")); + return EFI_SUCCESS; + } + + gST = SystemTable; + gDS = NULL; + Status = EfiGetSystemConfigurationTable (&gEfiDxeServicesTableGuid, (VOID**) &gDS); + + /// + /// Allocate 4kb of runtime memory. + /// + Status = (gBS->AllocatePool) (EfiACPIMemoryNVS, CPPC_SIZE, &MemoryPointer); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "CPPC: No Memory Buffer available.\n")); + ASSERT_EFI_ERROR(Status); + return Status; + } else { + mCppcBaseAddressMem = (EFI_PHYSICAL_ADDRESS) MemoryPointer; + ZeroMem ((VOID *)(UINTN)mCppcBaseAddressMem, CPPC_SIZE); + DEBUG((EFI_D_ERROR, "CPPC: PCCA memory buffer address: %x\n", mCppcBaseAddressMem)); + } + + /// + /// Add the Platform Communications Channel Table signature. + /// + CopyMem ((VOID *)(UINTN)mCppcBaseAddressMem, "PCC" , 3); + + /// + /// Load the SSDT Table for the CPPC ACPI objects. + /// + LoadAcpiTables (); + + /// + /// Load the ACPI 5.0 PCC Table. + /// + LoadAcpiTablesPcct (); + + /// + /// Load the ACPI 5.0 _CPC objects. + /// + LoadAcpiTablesCpc (); + + return EFI_SUCCESS; +} + +VOID +LoadAcpiTables( + VOID + ) +/** +@brief + This procedure loads the CPPC SSDT table. + + @param[in] None + + @retval None + +**/ +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + UINTN Index; + EFI_FIRMWARE_VOLUME_PROTOCOL *FwVol; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + INTN Instance; + EFI_ACPI_COMMON_HEADER *Table; + UINTN Size; + EFI_FV_FILETYPE FileType; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINT32 FvStatus; + EFI_ACPI_DESCRIPTION_HEADER *TableHeader; + UINTN TableHandle; + EFI_ACPI_TABLE_VERSION Version; + BOOLEAN LoadTable; + NAME_LAYOUT *NamePtr; + UINT8 *CurrPtr; + UINT32 *Signature; + UINT8 UpdateCounter; + + FwVol = NULL; + Table = NULL; + + /// + /// Locate FV protocol. + /// + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolumeProtocolGuid, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Look for FV with ACPI storage file + /// + for (Index = 0; Index < NumberOfHandles; Index++) { + + /// + /// Get the protocol on this handle + /// This should not fail because of LocateHandleBuffer + /// + Status = gBS->HandleProtocol ( + HandleBuffer[Index], + &gEfiFirmwareVolumeProtocolGuid, + (VOID **) &FwVol + ); + ASSERT_EFI_ERROR (Status); + + if ((Status == EFI_SUCCESS) && (FwVol != NULL)) { + /// + /// See if it has the ACPI storage file + /// + Size = 0; + FvStatus = 0; + Status = FwVol->ReadFile ( + FwVol, + &gCppcAcpiTableStorageGuid, + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + /// + /// If we found it, then we are done + /// + if (Status == EFI_SUCCESS) { + break; + } + } + } + + /// + /// Our exit status is determined by the success of the previous operations + /// If the protocol was found, Instance already points to it. + /// + /// Free any allocated buffers + /// + FreePool (HandleBuffer); + + /// + /// Sanity check that we found our data file + /// + ASSERT (FwVol); + if (FwVol == NULL) { + return; + } + + /// + /// By default, a table belongs in all ACPI table versions published. + /// + Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0; + + /// + /// Find the Table protocol + /// + Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable); + + /// + /// Read tables from the storage file. + /// + Instance = 0; + + while (Status == EFI_SUCCESS) { + /// + /// Read the ACPI tables + /// + Status = FwVol->ReadSection ( + FwVol, + &gCppcAcpiTableStorageGuid, + EFI_SECTION_RAW, + Instance, + (VOID **) &Table, + &Size, + &FvStatus + ); + + if (!EFI_ERROR (Status)) { + + LoadTable = FALSE; + TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table; + + switch (((EFI_ACPI_DESCRIPTION_HEADER*) TableHeader)->OemTableId) { + + case EFI_SIGNATURE_64 ('C', 'p', 'p', 'c', 'T', 'a', 'b', 'l'): + /// + /// This is Cppc SSDT. Cppc should be enabled if we reach here so load the table. + /// + LoadTable = TRUE; + DEBUG ((EFI_D_ERROR, "CPPC: Found Cppc SSDT signature.\n")); + + UpdateCounter = 3; // Number of objects to initialize. + for (CurrPtr = (UINT8 *) TableHeader; ((CurrPtr <= ((UINT8 *) TableHeader + TableHeader->Length))) && UpdateCounter !=0; CurrPtr++) { + Signature = (UINT32 *) (CurrPtr + 1); + /// + /// Patch PCCA with the address of the CPPC shared memory buffer. + /// + if ((*CurrPtr == AML_NAME_OP) && (*Signature == EFI_SIGNATURE_32 ('P', 'C', 'C', 'A'))) { + NamePtr = (NAME_LAYOUT *) CurrPtr; + if (mCppcBaseAddressMem != 0){ + NamePtr->Value = (UINT32) mCppcBaseAddressMem; + } + UpdateCounter--; + DEBUG((EFI_D_ERROR, "CPPC: PCCA pointer updated in SSDT: %x\n", mCppcBaseAddressMem)); + } + /// + /// Patch PCCS with the size of the CPPC shared memory buffer. + /// + if ((*CurrPtr == AML_NAME_OP) && (*Signature == EFI_SIGNATURE_32 ('P', 'C', 'C', 'S'))) { + NamePtr = (NAME_LAYOUT *) CurrPtr; + NamePtr->Value = (UINT32) CPPC_SIZE; + UpdateCounter--; + DEBUG((EFI_D_ERROR, "CPPC: PCCS length updated in SSDT: %x\n", CPPC_SIZE)); + } + /// + /// Patch PENB with the CPPC Enable/Disable Flag. + /// + if ((*CurrPtr == AML_NAME_OP) && (*Signature == EFI_SIGNATURE_32 ('P', 'E', 'N', 'B'))) { + NamePtr = (NAME_LAYOUT *) CurrPtr; + NamePtr->Value = (UINT32) mAcpiPlatformPolicyProtocol->EnableCppc; + UpdateCounter--; + DEBUG((EFI_D_ERROR, "CPPC: PENB updated in SSDT: %x\n", (UINT32) mAcpiPlatformPolicyProtocol->EnableCppc)); + } + } + break; + + default: + break; + } + + /// + /// Add the table + /// + if (LoadTable) { + TableHandle = 0; + Status = AcpiTable->InstallAcpiTable ( + AcpiTable, + Table, + Table->Length, + &TableHandle + ); + } + + /// + /// Increment the instance + /// + Instance++; + Table = NULL; + } + } +} + +VOID +LoadAcpiTablesPcct( + VOID + ) +/** +@brief + This procedure loads the ACPI 5.0 PCCT table. + + @param[in] None + + @retval None + +**/ +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + UINTN Index; + EFI_FIRMWARE_VOLUME_PROTOCOL *FwVol; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + INTN Instance; + EFI_ACPI_COMMON_HEADER *Table; + UINTN Size; + EFI_FV_FILETYPE FileType; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINT32 FvStatus; + EFI_ACPI_DESCRIPTION_HEADER *TableHeader; + UINTN TableHandle; + EFI_ACPI_TABLE_VERSION Version; + BOOLEAN LoadTable; + EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER *PcctHeaderPtr; + EFI_ACPI_5_0_PCCT_SUBSPACE_GENERIC *PcctPtr; + UINT8 *CurrPtr; + UINT32 *Signature; + UINT8 UpdateCounter; + + FwVol = NULL; + Table = NULL; + + /// + /// Locate FV protocol. + /// + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolumeProtocolGuid, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Look for FV with ACPI storage file + /// + for (Index = 0; Index < NumberOfHandles; Index++) { + + /// + /// Get the protocol on this handle + /// This should not fail because of LocateHandleBuffer + /// + Status = gBS->HandleProtocol ( + HandleBuffer[Index], + &gEfiFirmwareVolumeProtocolGuid, + (VOID **) &FwVol + ); + ASSERT_EFI_ERROR (Status); + + if ((Status == EFI_SUCCESS) && (FwVol != NULL)) { + /// + /// See if it has the ACPI storage file + /// + Size = 0; + FvStatus = 0; + Status = FwVol->ReadFile ( + FwVol, + &gCppcAcpiTableStorageGuid, + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + /// + /// If we found it, then we are done + /// + if (Status == EFI_SUCCESS) { + break; + } + } + } + + /// + /// Our exit status is determined by the success of the previous operations + /// If the protocol was found, Instance already points to it. + /// + /// Free any allocated buffers + /// + FreePool (HandleBuffer); + + /// + /// Sanity check that we found our data file + /// + ASSERT (FwVol); + if (FwVol == NULL) { + return; + } + + /// + /// By default, a table belongs in all ACPI table versions published. + /// + Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0; + + /// + /// Find the Table protocol + /// + Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable); + + /// + /// Read tables from the storage file. + /// + Instance = 0; + + while (Status == EFI_SUCCESS) { + /// + /// Read the ACPI tables + /// + Status = FwVol->ReadSection ( + FwVol, + &gCppcAcpiTableStorageGuid, + EFI_SECTION_RAW, + Instance, + (VOID **) &Table, + &Size, + &FvStatus + ); + + if (!EFI_ERROR (Status)) { + + LoadTable = FALSE; + TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table; + + switch (((EFI_ACPI_DESCRIPTION_HEADER*) TableHeader)->OemTableId) { + + case EFI_SIGNATURE_64 ('P', 'c', 'c', 't', 'T', 'a', 'b', 'l'): + /// + /// This is PCCT. Cppc should be enabled if we reach here so load the table. + /// + LoadTable = TRUE; + DEBUG ((EFI_D_ERROR, "PCCT: Found PCCT signature.\n")); + + UpdateCounter = 1; /// Number of objects to initialize. + for (CurrPtr = (UINT8 *) TableHeader; ((CurrPtr <= ((UINT8 *) TableHeader + TableHeader->Length))) && UpdateCounter !=0; CurrPtr++) { + Signature = (UINT32 *) (CurrPtr + 1); + /// + /// Patch the EFI_ACPI_5_0_PCCT_SUBSPACE_GENERIC structure. + /// + if ((*CurrPtr == AML_NAME_OP) && (*Signature == EFI_SIGNATURE_32 ('P', 'C', 'C', 'T'))) { + CurrPtr -= sizeof (EFI_ACPI_DESCRIPTION_HEADER); // backup the current pointer in order to use the PCCT header structure + PcctHeaderPtr = (EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER *) CurrPtr; + PcctHeaderPtr->Flags = (UINT32) mAcpiPlatformPolicyProtocol->EnableCppcPlatformSCI; + PcctHeaderPtr->Reserved = 0; + + CurrPtr += sizeof (EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER); + PcctPtr = (EFI_ACPI_5_0_PCCT_SUBSPACE_GENERIC *) CurrPtr; + PcctPtr->Type = 0x0; + PcctPtr->Length = 62; + PcctPtr->BaseAddress = mCppcBaseAddressMem; /// Shared memory address + PcctPtr->AddressLength = CPPC_SIZE; /// sizeof(Shared memory) in bytes + + PcctPtr->DoorbellRegister.AddressSpaceId = 1; /// IO address type + PcctPtr->DoorbellRegister.RegisterBitWidth = 8; /// byte + PcctPtr->DoorbellRegister.RegisterBitOffset = 0x0; /// offset=0 + PcctPtr->DoorbellRegister.AccessSize = 1; /// byte access + PcctPtr->DoorbellRegister.Address = MmioRead16 (MmPciExpressAddress (0,0, PCI_DEV_NUM_ICH_LPC, 0, R_ACPI_BAR)) &~BIT0; + PcctPtr->DoorbellRegister.Address += R_ACPI_GPE_CNTL; /// PMBASE + GPE_CNTL register offset + PcctPtr->DoorbellPreserve = 0xFD; /// preserve all bits except bit 1 + PcctPtr->DoorbellWrite = 2; /// write bit 1 = 1 to trigger GPE + PcctPtr->NominalLatency = 5000; /// 5ms + PcctPtr->MaximumPeriodicAccessRate = 0x0; + PcctPtr->MinimumRequestTurnaroundTime = 0x0; + + UpdateCounter--; + DEBUG((EFI_D_ERROR, "PCCT: Patch the EFI_ACPI_5_0_PCCT_SUBSPACE_GENERIC structure.\n")); + } + } + break; + + default: + break; + } + + /// + /// Add the table + /// + if (LoadTable) { + TableHandle = 0; + Status = AcpiTable->InstallAcpiTable ( + AcpiTable, + Table, + Table->Length, + &TableHandle + ); + } + + /// + /// Increment the instance + /// + Instance++; + Table = NULL; + } + } +} + +VOID +LoadAcpiTablesCpc( + VOID + ) +/** +@brief + Load ACPI SSDT tables. + + @param[in] None + + @retval None + +**/ +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + UINTN Index; + EFI_FIRMWARE_VOLUME_PROTOCOL *FwVol; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + INTN Instance; + EFI_ACPI_COMMON_HEADER *Table; + UINTN Size; + EFI_FV_FILETYPE FileType; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINT32 FvStatus; + EFI_ACPI_DESCRIPTION_HEADER *TableHeader; + UINTN TableHandle; + EFI_ACPI_TABLE_VERSION Version; + BOOLEAN LoadTable; + + FwVol = NULL; + Table = NULL; + + /// + /// Locate FV protocol. + /// + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolumeProtocolGuid, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Look for FV with ACPI storage file + /// + for (Index = 0; Index < NumberOfHandles; Index++) { + + /// + /// Get the protocol on this handle + /// This should not fail because of LocateHandleBuffer + /// + Status = gBS->HandleProtocol ( + HandleBuffer[Index], + &gEfiFirmwareVolumeProtocolGuid, + (VOID **) &FwVol + ); + ASSERT_EFI_ERROR (Status); + + if ((Status == EFI_SUCCESS) && (FwVol != NULL)) { + /// + /// See if it has the ACPI storage file + /// + Size = 0; + FvStatus = 0; + Status = FwVol->ReadFile ( + FwVol, + &gCppcAcpiTableStorageGuid, + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + /// + /// If we found it, then we are done + /// + if (Status == EFI_SUCCESS) { + break; + } + } + } + + /// + /// Our exit status is determined by the success of the previous operations + /// If the protocol was found, Instance already points to it. + /// + /// Free any allocated buffers + /// + FreePool (HandleBuffer); + + /// + /// Sanity check that we found our data file + /// + ASSERT (FwVol); + if (FwVol == NULL) { + return; + } + + /// + /// By default, a table belongs in all ACPI table versions published. + /// + Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0; + + /// + /// Find the Table protocol + /// + Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable); + + /// + /// Read tables from the storage file. + /// + Instance = 0; + + while (Status == EFI_SUCCESS) { + /// + /// Read the ACPI tables + /// + Status = FwVol->ReadSection ( + FwVol, + &gCppcAcpiTableStorageGuid, + EFI_SECTION_RAW, + Instance, + (VOID **) &Table, + &Size, + &FvStatus + ); + + if (!EFI_ERROR (Status)) { + + LoadTable = FALSE; + TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table; + + switch (((EFI_ACPI_DESCRIPTION_HEADER*) TableHeader)->OemTableId) { + + case EFI_SIGNATURE_64 ('C', 'p', 'c', '_', 'T', 'a', 'b', 'l'): + /// + /// This is the _CPC SSDT. Cppc should be enabled if we reach here so load the table. + /// + LoadTable = TRUE; + DEBUG ((EFI_D_ERROR, "CPPC: Found _CPC SSDT signature.\n")); + break; + + default: + break; + } + + /// + /// Add the table + /// + if (LoadTable) { + TableHandle = 0; + Status = AcpiTable->InstallAcpiTable ( + AcpiTable, + Table, + Table->Length, + &TableHandle + ); + } + + /// + /// Increment the instance + /// + Instance++; + Table = NULL; + } + } +} + +EFI_STATUS +LocateSupportProtocol ( + IN EFI_GUID *Protocol, + OUT VOID **Instance, + IN BOOLEAN Type + ) +/** + @brief + Locate the first instance of a protocol. If the protocol requested is an + FV protocol, then it will return the first FV that contains the ACPI table + storage file. + + @param[in] The protocol to find. + @param[in] Return pointer to the first instance of the protocol + @param[in] TRUE if the desired protocol is a FV protocol + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_NOT_FOUND - The protocol could not be located. + @retval EFI_OUT_OF_RESOURCES - There are not enough resources to find the protocol. +**/ +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + EFI_FV_FILETYPE FileType; + UINT32 FvStatus; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINTN Size; + UINTN i; + + /// + /// Locate protocol. + /// + Status = gBS->LocateHandleBuffer ( + ByProtocol, + Protocol, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + + /// + /// Defined errors at this time are not found and out of resources. + /// + return Status; + } + + /// + /// Looking for FV with ACPI storage file + /// + for (i = 0; i < NumberOfHandles; i++) { + + /// + /// Get the protocol on this handle + /// This should not fail because of LocateHandleBuffer + /// + Status = gBS->HandleProtocol ( + HandleBuffer[i], + Protocol, + Instance + ); + ASSERT_EFI_ERROR (Status); + + if (!Type) { + + /// + /// Not looking for the FV protocol, so find the first instance of the + /// protocol. There should not be any errors because our handle buffer + /// should always contain at least one or LocateHandleBuffer would have + /// returned not found. + /// + break; + } + + /// + /// See if it has the ACPI storage file + /// + Size = 0; + FvStatus = 0; + Status = ((EFI_FIRMWARE_VOLUME_PROTOCOL *) (*Instance))->ReadFile ( + *Instance, + &gCppcAcpiTableStorageGuid, + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + /// + /// If we found it, then we are done + /// + if (Status == EFI_SUCCESS) { + break; + } + } + + /// + /// Our exit status is determined by the success of the previous operations + /// If the protocol was found, Instance already points to it. + /// + /// Free any allocated buffers + /// + FreePool (HandleBuffer); + + return Status; +} diff --git a/ReferenceCode/AcpiTables/Cppc/Dxe/Cppc.dxs b/ReferenceCode/AcpiTables/Cppc/Dxe/Cppc.dxs new file mode 100644 index 0000000..d1df44e --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/Dxe/Cppc.dxs @@ -0,0 +1,35 @@ +/** @file + Dependency expression source file. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement + +**/ + + +#include "EfiDepex.h" +#include EFI_PROTOCOL_DEPENDENCY (CpuIo) +#include EFI_PROTOCOL_DEPENDENCY (AcpiSupport) +#include EFI_PROTOCOL_DEPENDENCY (AcpiPlatformPolicy) +#include EFI_PROTOCOL_DEPENDENCY (PowerMgmtInitDone) + +DEPENDENCY_START + EFI_CPU_IO_PROTOCOL_GUID AND + EFI_ACPI_SUPPORT_GUID AND + ACPI_PLATFORM_POLICY_PROTOCOL_GUID AND + EFI_POWER_MGMT_INIT_DONE_PROTOCOL_GUID +DEPENDENCY_END diff --git a/ReferenceCode/AcpiTables/Cppc/Dxe/Cppc.h b/ReferenceCode/AcpiTables/Cppc/Dxe/Cppc.h new file mode 100644 index 0000000..289fe93 --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/Dxe/Cppc.h @@ -0,0 +1,245 @@ +/** @file + Header file for the Collaborative Processor Performance Control (CPPC) driver. + +@copyright + Copyright (c) 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ + +#ifndef _CPPC_H_ +#define _CPPC_H_ + +#include "EdkIIGlueBase.h" +#include "EdkIIGlueDxe.h" +#include "EfiScriptLib.h" +#include "Acpi.h" +#include "SaAccess.h" +#include "CpuAccess.h" +#include "CpuPlatformLib.h" +/// +/// Consumed protocols +/// +#include EFI_PROTOCOL_DEPENDENCY (AcpiTable) +#include EFI_PROTOCOL_DEPENDENCY (FirmwareVolume) +#include EFI_PROTOCOL_CONSUMER (PciRootBridgeIo) +#include EFI_PROTOCOL_DEFINITION (AcpiPlatformPolicy) + +#define CPPC_SIZE 0x1000 /// 4kb of runtime memory for CPPC shared memory buffer +#define PCI_DEV_NUM_ICH_LPC 31 /// ICH is Device 31 +#define R_ACPI_BAR 0x40 /// ACPI Base Address Register +#define R_ACPI_GPE_CNTL 0x42 /// GPE control register offset +#define CPUID_FULL_FAMILY_MODEL_HASWELL 0x000306C0 +#define EFI_MSR_POWER_CTL 0x000001FC + +/// +/// SSDT data storage file +/// +#include "CppcAcpiTableStorage.h" + +/// +/// AML parsing definitions +/// +#define AML_NAME_OP 0x08 + +/// +/// ASL NAME structure +/// +#pragma pack(1) +typedef struct { + UINT8 NameOp; // Byte [0]=0x08:NameOp. + UINT32 NameString; // Byte [4:1]=Name of object. + UINT8 DWordPrefix; // Byte [5]=0x0C:DWord Prefix. + UINT32 Value; // Byte [9:6] ; Value of named object. +} NAME_LAYOUT; +#pragma pack() + +/// +/// ACPI 5.0 Generic Address Space definition +/// +#pragma pack(1) +typedef struct { + UINT8 AddressSpaceId; + UINT8 RegisterBitWidth; + UINT8 RegisterBitOffset; + UINT8 AccessSize; + UINT64 Address; +} EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE; +#pragma pack() + +/// +/// Platform Communications Channel Table (PCCT) +/// +#pragma pack(1) +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Flags; + UINT64 Reserved; +} EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER; +#pragma pack() + +/// +/// Generic Communications Subspace Structure +/// +#pragma pack(1) +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Reserved[6]; + UINT64 BaseAddress; + UINT64 AddressLength; + EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister; + UINT64 DoorbellPreserve; + UINT64 DoorbellWrite; + UINT32 NominalLatency; + UINT32 MaximumPeriodicAccessRate; + UINT16 MinimumRequestTurnaroundTime; +} EFI_ACPI_5_0_PCCT_SUBSPACE_GENERIC; +#pragma pack() + +/// +/// UINT64 workaround +/// +/// The MS compiler doesn't handle QWORDs very well. I'm breaking +/// them into DWORDs to circumvent the problems. Converting back +/// shouldn't be a big deal. +/// +#pragma pack(1) +typedef union _MSR_REGISTER { + UINT64 Qword; + + struct _DWORDS { + UINT32 Low; + UINT32 High; + } Dwords; + + struct _BYTES { + UINT8 FirstByte; + UINT8 SecondByte; + UINT8 ThirdByte; + UINT8 FouthByte; + UINT8 FifthByte; + UINT8 SixthByte; + UINT8 SeventhByte; + UINT8 EighthByte; + } Bytes; + +} MSR_REGISTER; +#pragma pack() + +#ifndef BIT63 +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 +#define BIT32 0x100000000 +#define BIT33 0x200000000 +#define BIT34 0x400000000 +#define BIT35 0x800000000 +#define BIT36 0x1000000000 +#define BIT37 0x2000000000 +#define BIT38 0x4000000000 +#define BIT39 0x8000000000 +#define BIT40 0x10000000000 +#define BIT41 0x20000000000 +#define BIT42 0x40000000000 +#define BIT43 0x80000000000 +#define BIT44 0x100000000000 +#define BIT45 0x200000000000 +#define BIT46 0x400000000000 +#define BIT47 0x800000000000 +#define BIT48 0x1000000000000 +#define BIT49 0x2000000000000 +#define BIT50 0x4000000000000 +#define BIT51 0x8000000000000 +#define BIT52 0x10000000000000 +#define BIT53 0x20000000000000 +#define BIT54 0x40000000000000 +#define BIT55 0x80000000000000 +#define BIT56 0x100000000000000 +#define BIT57 0x200000000000000 +#define BIT58 0x400000000000000 +#define BIT59 0x800000000000000 +#define BIT60 0x1000000000000000 +#define BIT61 0x2000000000000000 +#define BIT62 0x4000000000000000 +#define BIT63 0x8000000000000000 +#endif + +#define MmPciExpressAddress(Segment, Bus, Device, Function, Register) \ + ( (UINTN) (PciRead32 (PCI_LIB_ADDRESS (0,0,0,0x60)) & 0xFC000000) + \ + (UINTN) (Bus << 20) + \ + (UINTN) (Device << 15) + \ + (UINTN) (Function << 12) + \ + (UINTN) (Register) \ + ) + +EFI_STATUS +InitializeCppc ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +VOID +LoadAcpiTables( + VOID + ); + +VOID +LoadAcpiTablesPcct( + VOID + ); + +VOID +LoadAcpiTablesCpc( + VOID + ); + +EFI_STATUS +LocateSupportProtocol ( + IN EFI_GUID *Protocol, + OUT VOID **Instance, + IN BOOLEAN Type + ); + +#endif diff --git a/ReferenceCode/AcpiTables/Cppc/Dxe/Cppc.inf b/ReferenceCode/AcpiTables/Cppc/Dxe/Cppc.inf new file mode 100644 index 0000000..731cf82 --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/Dxe/Cppc.inf @@ -0,0 +1,91 @@ +## @file +# Component description file for Cppc module +# +#@copyright +# Copyright (c) 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# + + +[defines] +BASE_NAME = Cppc +FILE_GUID = C07A1EB5-5C04-4100-817B-0A11BB5F15DC +COMPONENT_TYPE = RT_DRIVER + +[sources.common] + Cppc.h + Cppc.c + +[includes.common] + $(EFI_SOURCE)/$(PROJECT_ACPI_ROOT) + $(EFI_SOURCE)/$(PROJECT_ACPI_ROOT)/Cppc + $(EFI_SOURCE)/$(PROJECT_ACPI_ROOT)/Cppc/Guid/AcpiTableStorage + . + $(EDK_SOURCE)/Sample/Chipset/PcCompatible + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Framework/Include + $(EDK_SOURCE)/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Core/Dxe/ArchProtocol/Cpu + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EFI_SOURCE) + $(EFI_SOURCE)/Framework + $(EFI_SOURCE)/Include + $(EFI_SOURCE)/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Pcd + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Library + $(EDK_SOURCE)/Foundation/Cpu/Pentium/Include + $(EFI_SOURCE)/$(PROJECT_CPU_ROOT) + $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include + $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include/Library + $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Library/CpuPlatformLib + $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include + +[libraries.common] + EdkIIGlueDxeMemoryAllocationLib + EdkIIGlueBaseLib + EdkIIGlueDxeReportStatusCodeLib + EdkIIGlueDxeDebugLibReportStatusCode + EdkProtocolLib + EfiProtocolLib + EfiDriverLib + ArchProtocolLib + EdkFrameworkProtocolLib + EdkIIGlueBasePciExpressLib + EdkIIGlueUefiLib + EfiScriptLib + AcpiProtocolLib + CpuProtocolLib + CpuPlatformLib + CppcGuidLib + +[nmake.common] + IMAGE_ENTRY_POINT = InitializeCppc + DPX_SOURCE = Cppc.dxs +# +# Module Entry Point +# + C_FLAGS = $(C_FLAGS) -D"__EDKII_GLUE_MODULE_ENTRY_POINT__=InitializeCppc" \ + -D __EDKII_GLUE_BASE_LIB__ \ + -D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \ + -D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ + diff --git a/ReferenceCode/AcpiTables/Cppc/Dxe/CppcDxe.cif b/ReferenceCode/AcpiTables/Cppc/Dxe/CppcDxe.cif new file mode 100644 index 0000000..5379e0e --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/Dxe/CppcDxe.cif @@ -0,0 +1,13 @@ +<component> + name = "CppcDxe" + category = ModulePart + LocalRoot = "ReferenceCode\AcpiTables\Cppc\Dxe\" + RefName = "CppcDxe" +[files] +"CppcDxe.sdl" +"CppcDxe.mak" +"Cppc.c" +"Cppc.dxs" +"Cppc.h" +"Cppc.inf" +<endComponent> diff --git a/ReferenceCode/AcpiTables/Cppc/Dxe/CppcDxe.mak b/ReferenceCode/AcpiTables/Cppc/Dxe/CppcDxe.mak new file mode 100644 index 0000000..a318f31 --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/Dxe/CppcDxe.mak @@ -0,0 +1,96 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2012, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: CppcDxe.mak +# +# Description: Make file to build Intel CPPC components +# +#<AMI_FHDR_END> +#************************************************************************* +EDK : CppcDxe + +CppcDxe : $(BUILD_DIR)\CppcDxe.mak CppcDxeBin + +CppcDxe_OBJECTS = \ +$(BUILD_DIR)\$(INTEL_CPPC_DXE_DIR)\Cppc.obj + +$(BUILD_DIR)\CppcDxe.mak : $(INTEL_CPPC_DXE_DIR)\$(@B).cif $(INTEL_CPPC_DXE_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(INTEL_CPPC_DXE_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +CppcDxe_LIBS =\ + $(EdkIIGlueDxeMemoryAllocationLib_LIB)\ + $(EDKPROTOCOLLIB)\ + $(EFIPROTOCOLLIB)\ + $(ARCHPROTOCOLLIB)\ + $(EDKFRAMEWORKPROTOCOLLIB)\ + $(EFISCRIPTLIB)\ + $(EdkIIGlueBaseLib_LIB)\ + $(EdkIIGlueBasePciExpressLib_LIB)\ + $(EdkIIGlueUefiLib_LIB)\ +!IF "$(x64_BUILD)"=="1" + $(EdkIIGlueBaseLibX64_LIB)\ +!ELSE + $(EdkIIGlueBaseLibIA32_LIB)\ +!ENDIF + $(EdkIIGlueDxeReportStatusCodeLib_LIB)\ + $(EdkIIGlueDxeServicesTableLib_LIB)\ + $(EdkIIGlueDxeDebugLibReportStatusCode_LIB)\ + $(EdkIIGlueDxeHobLib_LIB)\ + $(EdkIIGlueBasePciLibPciExpress_LIB)\ + $(EFIDRIVERLIB)\ + $(AcpiProtocolLib_LIB)\ + $(CppcGuidLib_LIB)\ + $(CpuProtocolLib_LIB)\ + $(CpuPlatformLib_LIB)\ + $(PchPlatformDxeLib_LIB)\ + +CppcDxe_INCLUDES= $(EDK_INCLUDES)\ + $(IndustryStandard_INCLUDES)\ + $(EdkIIGlueLib_INCLUDES)\ + $(CPPC_INCLUDES)\ + /I ReferenceCode\AcpiTables\ + /I$(ArchProtocolLib_DIR)\Cpu\ + $(PROJECT_CPU_INCLUDES)\ + /I$(PROJECT_CPU_ROOT)\Library\CpuPlatformLib\ + /I$(INTEL_SYSTEM_AGENT_DIR)\Include\ + +CppcDxeBin: $(CppcDxe_LIBS) + $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\ + /f $(BUILD_DIR)\CppcDxe.mak all \ + NAME=CppcDxe\ + MAKEFILE=$(BUILD_DIR)\CppcDxe.mak \ + "MY_INCLUDES=$(CppcDxe_INCLUDES)"\ + GUID=C07A1EB5-5C04-4100-817B-0A11BB5F15DC\ + ENTRY_POINT=InitializeCppc \ + TYPE=RT_DRIVER\ + "OBJECTS=$(CppcDxe_OBJECTS)"\ + DEPEX1=$(INTEL_CPPC_DXE_DIR)\Cppc.dxs\ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\ + COMPRESS=1 +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2012, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/Cppc/Dxe/CppcDxe.sdl b/ReferenceCode/AcpiTables/Cppc/Dxe/CppcDxe.sdl new file mode 100644 index 0000000..164ab26 --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/Dxe/CppcDxe.sdl @@ -0,0 +1,30 @@ +TOKEN + Name = "CppcDxe_SUPPORT" + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable CppcDxe support in Project" +End + +MODULE + Help = "Includes CppcDxe.mak to Project" + File = "CppcDxe.mak" +End + +PATH + Name = "INTEL_CPPC_DXE_DIR" +End + +ELINK + Name = "/I$(INTEL_CPPC_DXE_DIR)" + Parent = "CPPC_INCLUDES" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(BUILD_DIR)\CppcDxe.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End diff --git a/ReferenceCode/AcpiTables/Cppc/Guid/AcpiTableStorage/CppcAcpiTableStorage.c b/ReferenceCode/AcpiTables/Cppc/Guid/AcpiTableStorage/CppcAcpiTableStorage.c new file mode 100644 index 0000000..af25bc6 --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/Guid/AcpiTableStorage/CppcAcpiTableStorage.c @@ -0,0 +1,33 @@ +/** @file + The GUID definition for Cppc ACPI table storage file name + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ + +#include "EdkIIGlueDxe.h" +#include "CppcAcpiTableStorage.h" + +/// +/// Protocol GUID definition +/// +EFI_GUID gCppcAcpiTableStorageGuid = CPPC_ACPI_TABLE_STORAGE_GUID; + +/// +/// Protocol description string +/// +EFI_GUID_STRING (&gCppcAcpiTableStorageGuid, "Collaborative Processor Performance Control ACPI Table Storage File Name", "Collaborative Processor Performance Control ACPI Table Storage file name GUID"); diff --git a/ReferenceCode/AcpiTables/Cppc/Guid/AcpiTableStorage/CppcAcpiTableStorage.h b/ReferenceCode/AcpiTables/Cppc/Guid/AcpiTableStorage/CppcAcpiTableStorage.h new file mode 100644 index 0000000..417ad64 --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/Guid/AcpiTableStorage/CppcAcpiTableStorage.h @@ -0,0 +1,30 @@ +/** @file + GUID definition for the Cppc ACPI table storage file name + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ + +#ifndef _CPPC_ACPI_TABLE_STORAGE_H_ +#define _CPPC_ACPI_TABLE_STORAGE_H_ + +#define CPPC_ACPI_TABLE_STORAGE_GUID \ + { 0x60e31de1, 0x3ec, 0x492a, 0x95, 0x98, 0x65, 0xa3, 0xc5, 0xe, 0xf, 0x6b } + +extern EFI_GUID gCppcAcpiTableStorageGuid; + +#endif diff --git a/ReferenceCode/AcpiTables/Cppc/Guid/CppcGuidLib.cif b/ReferenceCode/AcpiTables/Cppc/Guid/CppcGuidLib.cif new file mode 100644 index 0000000..fa8673e --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/Guid/CppcGuidLib.cif @@ -0,0 +1,12 @@ +<component> + name = "CppcGuidLib" + category = ModulePart + LocalRoot = "ReferenceCode\AcpiTables\Cppc\Guid\" + RefName = "CppcGuidLib" +[files] +"CppcGuidLib.sdl" +"CppcGuidLib.mak" +"CppcGuidLib.inf" +"AcpiTableStorage\CppcAcpiTableStorage.c" +"AcpiTableStorage\CppcAcpiTableStorage.h" +<endComponent> diff --git a/ReferenceCode/AcpiTables/Cppc/Guid/CppcGuidLib.inf b/ReferenceCode/AcpiTables/Cppc/Guid/CppcGuidLib.inf new file mode 100644 index 0000000..23131aa --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/Guid/CppcGuidLib.inf @@ -0,0 +1,55 @@ +## @file +# Component description file. +# +#@copyright +# Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# + +[defines] +BASE_NAME = CppcGuidLib +COMPONENT_TYPE = LIBRARY + +[sources.common] + AcpiTableStorage/CppcAcpiTableStorage.c + AcpiTableStorage/CppcAcpiTableStorage.h + +[includes.common] + . + $(EFI_SOURCE) + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Framework/Include + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EFI_SOURCE)/$(PROJECT_ACPI_ROOT)/Cppc +# +# Edk II Glue Library, some hearder are included by R9 header so have to include +# + + $(EFI_SOURCE) + $(EFI_SOURCE)/Framework + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + +[nmake.common] diff --git a/ReferenceCode/AcpiTables/Cppc/Guid/CppcGuidLib.mak b/ReferenceCode/AcpiTables/Cppc/Guid/CppcGuidLib.mak new file mode 100644 index 0000000..86fed09 --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/Guid/CppcGuidLib.mak @@ -0,0 +1,55 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2012, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: CppcGuidLib.mak +# +# Description: Make file to build Intel CPPC GuidLib components +# +#<AMI_FHDR_END> +#************************************************************************* +all : CppcGuidLib + +$(CppcGuidLib_LIB) : CppcGuidLib + +CppcGuidLib : $(BUILD_DIR)\CppcGuidLib.mak CppcGuidLibBin + +$(BUILD_DIR)\CppcGuidLib.mak : $(INTEL_CPPC_GUIDLIB_DIR)\$(@B).cif $(INTEL_CPPC_GUIDLIB_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(INTEL_CPPC_GUIDLIB_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +CppcGuidLib_INCLUDES=\ + $(EDK_INCLUDES)\ + $(EdkIIGlueLib_INCLUDES) + +CppcGuidLibBin : + $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\ + /f $(BUILD_DIR)\CppcGuidLib.mak all\ + "MY_INCLUDES=$(CppcGuidLib_INCLUDES)" \ + TYPE=LIBRARY + +#********************************************************************** +#********************************************************************** +#** ** +#** (C)Copyright 1985-2012, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#********************************************************************** +#**********************************************************************
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/Cppc/Guid/CppcGuidLib.sdl b/ReferenceCode/AcpiTables/Cppc/Guid/CppcGuidLib.sdl new file mode 100644 index 0000000..7e03f5e --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/Guid/CppcGuidLib.sdl @@ -0,0 +1,37 @@ +TOKEN + Name = "CppcGuidLib_SUPPORT" + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable CppcGuidLib support in Project" +End + +MODULE + Help = "Includes CppcGuidLib.mak to Project" + File = "CppcGuidLib.mak" +End + +PATH + Name = "INTEL_CPPC_GUIDLIB_DIR" +End + +TOKEN + Name = "CppcGuidLib_LIB" + Value = "$(BUILD_DIR)\CppcGuidLib.lib" + TokenType = Expression + TargetMAK = Yes +End + +ELINK + Name = "/I$(INTEL_CPPC_GUIDLIB_DIR)" + Parent = "CPPC_INCLUDES" + InvokeOrder = AfterParent +End + +ELINK + Name = "/I$(INTEL_CPPC_GUIDLIB_DIR)\AcpiTableStorage" + Parent = "CPPC_INCLUDES" + InvokeOrder = AfterParent +End
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/Cppc/ReleaseNotes.chm b/ReferenceCode/AcpiTables/Cppc/ReleaseNotes.chm Binary files differnew file mode 100644 index 0000000..34332db --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/ReleaseNotes.chm diff --git a/ReferenceCode/AcpiTables/Cppc/iasl.exe b/ReferenceCode/AcpiTables/Cppc/iasl.exe Binary files differnew file mode 100644 index 0000000..b10ef96 --- /dev/null +++ b/ReferenceCode/AcpiTables/Cppc/iasl.exe diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Art.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Art.asl new file mode 100644 index 0000000..03831ac --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Art.asl @@ -0,0 +1,91 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + Art.asl + +Abstract: + + Intel ACPI Reference Code for Intel Dynamic Power Performance Management + +--*/ + + Scope(\_SB.IETM) + { + + Name(ART1, Package() // ART package when in Quiet Mode / Passive Cooling Mode + { + 0, // Revision + // Source Target Weight, AC0MaxLevel, AC1MaxLevel, AC21MaxLevel, AC31MaxLevel, AC41MaxLevel, AC51MaxLevel, AC61MaxLevel, AC71MaxLevel, AC81MaxLevel, AC91MaxLevel + Package(){\_SB.PCI0.LPCB.H_EC.TFN1, \_SB.PCI0.TPCH, 100, 55, 45, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN1, \_SB.PCI0.TMEM, 100, 60, 50, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN1, \_SB.PCI0.LPCB.H_EC.TSKN, 100, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 60, 50, 40, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN1, \_SB.PCI0.LPCB.H_EC.TAMB, 100, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN1, \_SB.PCI0.LPCB.H_EC.T_VR, 100, 70, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN1, \_SB.PCI0.LPCB.H_EC.TEFN, 100, 40, 35, 30, 25, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN1, \_SB.PCI0.B0D4, 100, 70, 50, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN2, \_SB.PCI0.LPCB.H_EC.T_VR, 100, 65, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN2, \_SB.PCI0.B0D4, 100, 75, 20, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + }) + + Name(ART0, Package() // ART package when in Performance Mode / Active Cooling Mode + { + 0, // Revision + // Source Target Weight, AC0MaxLevel, AC1MaxLevel, AC21MaxLevel, AC31MaxLevel, AC41MaxLevel, AC51MaxLevel, AC61MaxLevel, AC71MaxLevel, AC81MaxLevel, AC91MaxLevel + Package(){\_SB.PCI0.LPCB.H_EC.TFN1, \_SB.PCI0.TPCH, 100, 70, 50, 40, 30, 20, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN1, \_SB.PCI0.TMEM, 100, 80, 60, 50, 30, 10, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN1, \_SB.PCI0.LPCB.H_EC.TSKN, 100, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 90, 75, 50, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN1, \_SB.PCI0.LPCB.H_EC.TAMB, 100, 75, 55, 35, 15, 5, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN1, \_SB.PCI0.LPCB.H_EC.T_VR, 100, 90, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN1, \_SB.PCI0.LPCB.H_EC.TEFN, 100, 60, 50, 40, 30, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN1, \_SB.PCI0.B0D4, 100, 100, 80, 65, 45, 25, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN2, \_SB.PCI0.LPCB.H_EC.T_VR, 100, 95, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN2, \_SB.PCI0.B0D4, 100, 100, 50, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + }) + + // _ART (Active Cooling Relationship Table) + // + // Arguments: + // None + // Return Value: + // A variable-length Package containing a Revision ID and a list of Active Relationship Packages as described below: + // + // Return Value Information + // Package { + // Revision, // Integer - Current revision is: 0 + // ActiveRelationship[0] // Package + // ... + // ActiveRelationship[n] // Package + // } + // + Method(_ART,,,,PkgObj) + { // TODO: Add system-specific _ART code here + If(\ECON) + { + If(\_SB.PCI0.LPCB.H_EC.TSKN.CTYP) + { + Return(ART1) + } Else { + Return(ART0) + } + } + } // End _ART +} diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/B0d4CtdpPolicy.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/B0d4CtdpPolicy.asl new file mode 100644 index 0000000..553612f --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/B0d4CtdpPolicy.asl @@ -0,0 +1,376 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + B0d4CtdpPolicy.asl + +Abstract: + + Intel ACPI Reference Code for Intel Configurable TDP + +--*/ + + +Scope(\_SB.IETM) +{ + Name (CTSP, Package () + { + // + // ConfigTDP Policy + // + ToUUID("E145970A-E4C1-4d73-900E-C9C5A69DD067") + }) +} + +Scope(\_SB.PCI0.B0D4) +{ + // TDPL (Thermal Design Power List) + // + // Returns the list of all supported Configurable TDP points available for the participant device. + // + // Arguments: (0) + // None + // Return Value: + // Package () // Zeroth TDP State + // { + // TDPPower, // DWordConst + // Frequency, // DWordConst + // TDPControl, // DWordConst + // FrequencyControl, // DWordConst + // Reserved1, // DWordConst + // }, + // . + // . + // . + // Package () // Last TDP State + // { + // TDPPower, // DWordConst + // Frequency, // DWordConst + // TDPControl, // DWordConst + // FrequencyControl, // DWordConst + // Reserved1, // DWordConst + // } + // + Method(TDPL,,,,PkgObj) + { + Name(AAAA,0) // PACKAGE_POWER_SKU + Name(BBBB,0) // CONFIG_TDP_LEVEL1 + Name(CCCC,0) // CONFIG_TDP_LEVEL2 + Name(PPUU,0) // PACKAGE_POWER_SKU_UNIT + + Store(CTNL, Local0) // CONFIG_TDP_NUM_LEVELS + If(LOr(LEqual(Local0,1),LEqual(Local0,2))){ // check for CTDP support + Store(\_PR.CLVL,Local0) // use PPM supplied value for CTDP level + } + Else{ + Return(Package (){0}) // no CTDP support + } + + If(LEqual(CLCK,1)){ // check the CONFIG_TDP_LOCK bit + Store(1,Local0) + } + + Store(CPNU(\_PR.PL10,1),AAAA) // convert Custom 0 Power Limit1 to milliwatts + Store(CPNU(\_PR.PL11,1),BBBB) // convert Custom 1 Power Limit1 to milliwatts + Store(CPNU(\_PR.PL12,1),CCCC) // convert Custom 2 Power Limit1 to milliwatts + + // + // Define a package of packages that contain 5 DWords. + // + Name (TMP1, Package (1){ + Package (){0x80000000,0x80000000,0x80000000,0x80000000,0x80000000} + }) + Name (TMP2, Package (2){ + Package (){0x80000000,0x80000000,0x80000000,0x80000000,0x80000000}, + Package (){0x80000000,0x80000000,0x80000000,0x80000000,0x80000000} + }) + Name (TMP3, Package (3){ + Package (){0x80000000,0x80000000,0x80000000,0x80000000,0x80000000}, + Package (){0x80000000,0x80000000,0x80000000,0x80000000,0x80000000}, + Package (){0x80000000,0x80000000,0x80000000,0x80000000,0x80000000} + }) + + // + // if 3 TDP's, use PL0, PL1 and PL2 values + // + If(LEqual(Local0,3)){ + If (LGreater(AAAA,BBBB)){ + If (LGreater(AAAA,CCCC)){ + If (LGreater(BBBB,CCCC)){ + // abc + Store(0,Local3) + Store(0,LEV0) + Store(1,Local4) + Store(1,LEV1) + Store(2,Local5) + Store(2,LEV2) + }Else{ + // acb + Store(0,Local3) + Store(0,LEV0) + Store(1,Local5) + Store(2,LEV1) + Store(2,Local4) + Store(1,LEV2) + } + }Else{ + // cab + Store(0,Local5) + Store(2,LEV0) + Store(1,Local3) + Store(0,LEV1) + Store(2,Local4) + Store(1,LEV2) + } + }Else{ // b > a here + If(LGreater(BBBB,CCCC)){ + If(LGreater(AAAA,CCCC)){ + // bac + Store(0,Local4) + Store(1,LEV0) + Store(1,Local3) + Store(0,LEV1) + Store(2,Local5) + Store(2,LEV2) + }Else{ + // bca + Store(0,Local4) + Store(1,LEV0) + Store(1,Local5) + Store(2,LEV1) + Store(2,Local3) + Store(0,LEV2) + } + }Else{ + // cba + Store(0,Local5) + Store(2,LEV0) + Store(1,Local4) + Store(1,LEV1) + Store(2,Local3) + Store(0,LEV2) + } + } + + // copy for PL0 + Store(Add(\_PR.TAR0,1),Local1) + Multiply(Local1,100,Local2) + Store(AAAA,Index(DeRefOf(Index(TMP3, Local3)),0)) + Store(Local2,Index(DeRefOf(Index(TMP3, Local3)),1)) + Store(\_PR.CTC0,Index(DeRefOf(Index(TMP3, Local3)),2)) + Store(Local1,Index(DeRefOf(Index(TMP3, Local3)),3)) + Store(0,Index(DeRefOf(Index(TMP3, Local3)),4)) + + // copy for PL1 + Store(Add(\_PR.TAR1,1),Local1) + Multiply(Local1,100,Local2) + Store(BBBB,Index(DeRefOf(Index(TMP3, Local4)),0)) + Store(Local2,Index(DeRefOf(Index(TMP3, Local4)),1)) + Store(\_PR.CTC1,Index(DeRefOf(Index(TMP3, Local4)),2)) + Store(Local1,Index(DeRefOf(Index(TMP3, Local4)),3)) + Store(0,Index(DeRefOf(Index(TMP3, Local4)),4)) + + // copy for PL2 + Store(Add(\_PR.TAR2,1),Local1) + Multiply(Local1,100,Local2) + Store(CCCC,Index(DeRefOf(Index(TMP3, Local5)),0)) + Store(Local2,Index(DeRefOf(Index(TMP3, Local5)),1)) + Store(\_PR.CTC2,Index(DeRefOf(Index(TMP3, Local5)),2)) + Store(Local1,Index(DeRefOf(Index(TMP3, Local5)),3)) + Store(0,Index(DeRefOf(Index(TMP3, Local5)),4)) + + Return(TMP3) + } + + // + // if 2 TDP's, use PL0 and PL1 values + // + If(LEqual(Local0,2)){ + If(LGreater(AAAA,BBBB)){ + Store(0,Local3) // store PL0 in Zeroth package + Store(1,Local4) // store PL1 in next package + Store(0,LEV0) + Store(1,LEV1) + Store(0,LEV2) // level 2 is not used so put 0 for safety + }Else{ + Store(0,Local4) // store PL1 in Zeroth package + Store(1,Local3) // store PL0 in next package + Store(1,LEV0) + Store(0,LEV1) + Store(0,LEV2) // level 2 is not used so put 0 for safety + } + + // copy for PL0 + Store(Add(\_PR.TAR0,1),Local1) + Multiply(Local1,100,Local2) + Store(AAAA,Index(DeRefOf(Index(TMP2, Local3)),0)) + Store(Local2,Index(DeRefOf(Index(TMP2, Local3)),1)) + Store(\_PR.CTC0,Index(DeRefOf(Index(TMP2, Local3)),2)) + Store(Local1,Index(DeRefOf(Index(TMP2, Local3)),3)) + Store(0,Index(DeRefOf(Index(TMP2, Local3)),4)) + + // copy for PL1 + Store(Add(\_PR.TAR1,1),Local1) + Multiply(Local1,100,Local2) + Store(BBBB,Index(DeRefOf(Index(TMP2, Local4)),0)) + Store(Local2,Index(DeRefOf(Index(TMP2, Local4)),1)) + Store(\_PR.CTC1,Index(DeRefOf(Index(TMP2, Local4)),2)) + Store(Local1,Index(DeRefOf(Index(TMP2, Local4)),3)) + Store(0,Index(DeRefOf(Index(TMP2, Local4)),4)) + + Return(TMP2) + } + + // + // if 1 TDP, return one PL based on boot index + // + If(LEqual(Local0,1)){ + Switch(ToInteger(\_PR.CBMI)){ + case(0){ + // copy for PL0 + Store(Add(\_PR.TAR0,1),Local1) + Multiply(Local1,100,Local2) + Store(AAAA,Index(DeRefOf(Index(TMP1, 0)),0)) + Store(Local2,Index(DeRefOf(Index(TMP1, 0)),1)) + Store(\_PR.CTC0,Index(DeRefOf(Index(TMP1, 0)),2)) + Store(Local1,Index(DeRefOf(Index(TMP1, 0)),3)) + Store(0,Index(DeRefOf(Index(TMP1, 0)),4)) + Store(0,LEV0) + Store(0,LEV1) + Store(0,LEV2) + } + + case(1){ + // copy for PL1 + Store(Add(\_PR.TAR1,1),Local1) + Multiply(Local1,100,Local2) + Store(BBBB,Index(DeRefOf(Index(TMP1, 0)),0)) + Store(Local2,Index(DeRefOf(Index(TMP1, 0)),1)) + Store(\_PR.CTC1,Index(DeRefOf(Index(TMP1, 0)),2)) + Store(Local1,Index(DeRefOf(Index(TMP1, 0)),3)) + Store(0,Index(DeRefOf(Index(TMP1, 0)),4)) + Store(1,LEV0) + Store(1,LEV1) + Store(1,LEV2) + } + + case(2){ + // copy for PL2 + Store(Add(\_PR.TAR2,1),Local1) + Multiply(Local1,100,Local2) + Store(CCCC,Index(DeRefOf(Index(TMP1, 0)),0)) + Store(Local2,Index(DeRefOf(Index(TMP1, 0)),1)) + Store(\_PR.CTC2,Index(DeRefOf(Index(TMP1, 0)),2)) + Store(Local1,Index(DeRefOf(Index(TMP1, 0)),3)) + Store(0,Index(DeRefOf(Index(TMP1, 0)),4)) + Store(2,LEV0) + Store(2,LEV1) + Store(2,LEV2) + } + } + + Return(TMP1) + } + + Return(0) // we should never get here, this eliminates a compiler warning + } // End of TDPL object + + // + // Returns the max TDP configurable for the platform. + // + Name(MAXT,0) + + // TDPC (Thermal Design Power Capabilities) + // + // The TDPC object evaluates to an integer that identifies the maximum usable TDP point + // from the table returned by the TDPL object at any given time. + // + // Arguments: (0) + // None + // Return Value: + // This value is the zero based index into the TDPL object's entries. + // + Method(TDPC) // For CRB, please return 0. + { + Return(MAXT) // Return valid TDP point. + }//end Method(TDPC) + + Name(LEV0,0) + Name(LEV1,0) + Name(LEV2,0) + + // STDP (Set current operating TDP Point) + // + // The STDP object communicates to the platform BIOS the current operating TDP point whenever it is changed due to any reason. + // In response to this object evaluation, the platform BIOS modifies the packages returned in PPCC object and notifies the driver of + // a change in power limit capabilities as appropriate. + // + // Arguments: (1) + // Arg0 = Config TDP level selected + // 0 = Highest Level values from MSR + // 1 = Middle Level values from MSR + // 2 = Lowest Level values from MSR + // 3 = reserved + // Return Value: + // None + // + // Currently we are using hard coded values for the PPCC values. + // A future reference code release will use PPCC values from the PPM reference code. + // This will allow PPCC values to be selected from SETUP options. + // + Method(STDP,1,Serialized) + { + If (LGreaterEqual(Arg0,\_PR.CLVL)){ // bounds check the input + Return() // invalid input + } + + // + // translate requested index value to the correct PL using the sorted TDPL value. + // + Switch (ToInteger(Arg0)){ + Case (0) { + Store(LEV0,Local0) + } + Case (1) { + Store(LEV1,Local0) + } + Case (2) { + Store(LEV2,Local0) + } + } + + Switch (ToInteger(Local0)){ + Case (0) { + CPL0() // copy PL0 values to PPCC + } + Case (1) { + CPL1() // copy PL1 values to PPCC + } + Case (2) { + CPL2() // copy PL2 values to PPCC + } + } + + Notify (\_SB.PCI0.B0D4, 0x83) // Send a Power Capabilities Changed notification to self + }//end Method(STDP) + +}//end Scope(\_SB.PCI0.B0D4) + diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/B0d4DppmPolicy.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/B0d4DppmPolicy.asl new file mode 100644 index 0000000..1967ea4 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/B0d4DppmPolicy.asl @@ -0,0 +1,177 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + B0d4DppmPolicy.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + + +Scope(\_SB.PCI0.B0D4) +{ + Name(CTYP,0) // Device-specific cooling policy preference + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC0) + { + If(CTYP) + { + Store(\_SB.IETM.CTOK(PTMC),Local1) // Passive Cooling Policy + } + Else + { + Store(\_SB.IETM.CTOK(ATMC),Local1) // Active Cooling Policy + } + If(LGreaterEqual(LSTM,Local1)) + { + Return(Subtract(Local1,20)) // subtract 2 degrees which is the Hysteresis + } + Else + { + Return(Local1) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC1) + { + If(CTYP) + { + Store(\_SB.IETM.CTOK(PTMC),Local0) // Passive Cooling Policy + } + Else + { + Store(\_SB.IETM.CTOK(ATMC),Local0) // Active Cooling Policy + } + Subtract(Local0, 50, Local0) + + If(LGreaterEqual(LSTM,Local0)) + { + Return(Subtract(Local0,20)) // subtract 2 degrees which is the Hysteresis + } + Else + { + Return(Local0) + } + } + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT,0,Serialized) + { + Return(\_SB.IETM.CTOK(SACR)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + Return(\_SB.IETM.CTOK(SAHT)) + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV,0,Serialized) + { + If(CTYP) + { + Return(\_SB.IETM.CTOK(ATMC)) // Passive Cooling Policy + } Else { + Return(\_SB.IETM.CTOK(PTMC)) // Active Cooling Policy + } + } + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP,3,Serialized) + { + If(LOr(LEqual(Arg0,0),LEqual(Arg0,1))) + { + Store(Arg0, CTYP) + P8XH(0, Arg1) + P8XH(1, Arg2) + Notify(B0D4, 0x91) + } + } + +} // End Scope(\_SB.PCI0.B0D4) + diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/B0d4LpmPolicy.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/B0d4LpmPolicy.asl new file mode 100644 index 0000000..331b322 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/B0d4LpmPolicy.asl @@ -0,0 +1,64 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + B0d4LpmPolicy.asl + +Abstract: + + Intel ACPI Reference Code for Intel Low Power Mode + +--*/ + + +Scope(\_SB.IETM) +{ + Name (LPSP, Package () + { + // + // LPM Policy + // + ToUUID("B9455B06-7949-40c6-ABF2-363A70C8706C") + }) + + // CLPM (Current Low Power Mode Setting) + // + // This object evaluates to an integer that indicates the current platform desired LPM mode setting. + // + // Arguments: (0) + // None + // Return Value: + // 0 - Disable LPM + // 1 - Enable LPM + // 2 - Application Specific LPM + // 3 - Use the LPM setting as requested by the OS level interfaces either through the OS Power Plan settings or + // through the LPM API exposed to OS software. + // + Method (CLPM) + { + If(LEqual(\_SB.PCI0.B0D4.LPMS,0)){ // check LPM support in CPU + Return (0) + } + Return (LPMV) // Update LPMV based on current platform desire. + } // End of CLPM object + +}//end Scope(\_SB.IETM) + diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/B0d4Participant.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/B0d4Participant.asl new file mode 100644 index 0000000..69d69d6 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/B0d4Participant.asl @@ -0,0 +1,931 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + B0d4Participant.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +//AMI override for fix BSOD issue +Scope(\_SB.PCI0.B0D4) +{ +/* +Scope(\_SB.PCI0) +{ + Device(B0D4) // SA Thermal Device + { + Name(_ADR, 0x00040000) +*/ +//AMI override for fix BSOD issue + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(SADE,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + // + // Define an OpRegion for the DPTF MSR's accessed via MCHBAR+0x5000 + // + OperationRegion (MBAR, SystemMemory, Add(ShiftLeft(MHBR,15),0x5000), 0x1000) + Field (MBAR, ByteAcc, NoLock, Preserve) + { + Offset (0x930), // PACKAGE_POWER_SKU (MCHBAR+0x5930) + PTDP, 15, // TDP Package Power [14:0] + , 1, // reserved [15] + PMIN, 15, // Minimal Package Power [30:16] + , 1, // Reserved [31] + PMAX, 15, // Maximal Package Power [46:32] + , 1, // Reserved [47] + TMAX, 7, // Maximal Time Window [54:48] + Offset (0x938), // PACKAGE_POWER_SKU_UNIT (MCHBAR+0x5938) + PWRU, 4, // Power Units [3:0] + , 4, // Reserved [7:4] + EGYU, 5, // Energy Units [12:8] + , 3, // Reserved [15:13] + TIMU, 4, // Time Units [19:16] + Offset (0x958), // PLATFORM_INFO (MCHBAR+0x5958) + , 32, // [31:0] + LPMS, 1, // LPM Support [32] + CTNL, 2, // CONFIG_TDP_NUM_LEVELS [34:33] + Offset (0x998), // RP_STATE_CAP_0_0_0_MCHBAR_PCU (MCHBAR+0x5998) + RP0C, 8, // [7:0] RP0_CAP, These fields indicate the maximum RPx base frequency capability for the Integrated GFX Engine (GT). + RP1C, 8, // [15:8] RP1_CAP, Values are in units of 100 MHz. + RPNC, 8, // [23:16] RPN_CAP + Offset (0xF3C), // CONFIG_TDP_NOMINAL (MCHBAR+0x5F3C) + TRAT, 8, // TDP Ratio [7:0] + Offset (0xF40), // CONFIG_TDP_LEVEL1 (MCHBAR+0x5F40) + PTD1, 15, // Package TDP [14:0] + , 1, // reserved [15] + TRA1, 8, // TDP Ratio [23:16] + , 8, // reserved [31:24] + PMX1, 15, // Package MAX Power [46:32] + , 1, // reserved [47] + PMN1, 15, // Package MIN Power [62:48] + Offset (0xF48), // CONFIG_TDP_LEVEL2 (MCHBAR+0x5F48) + PTD2, 15, // Package TDP [14:0] + , 1, // reserved [15] + TRA2, 8, // TDP Ratio [23:16] + , 8, // reserved [31:24] + PMX2, 15, // Package MAX Power [46:32] + , 1, // reserved [47] + PMN2, 15, // Package MIN Power [62:48] + Offset (0xF50), // CONFIG_TDP_CONTROL (MCHBAR+0x5F50) + CTCL, 2, // TDP Level [1:0] + , 29, // reserved [30:2] + CLCK, 1, // Config TDP Lock [31] + Offset (0xF54), // TURBO_ACTIVATION_RATIO (MCHBAR+0x5F54) + MNTR, 8, // Max Non Turbo Ratio [7:0] + } + + Name(XPCC,0) // semaphore to record when PPCC gets called for the first time + + // PPCC (Participant Power Control Capabilities) + // + // The PPCC object evaluates to a package of packages that indicates to DPTF processor + // participant the power control capabilities. + // + // Arguments: (0) + // None + // Return Value: + // PPCC package of packages + // + Method(PPCC,0,Serialized,,PkgObj) + { + If(LAnd(LEqual(XPCC,0),CondRefOf(\_PR.CBMI))){ + Switch(ToInteger(\_PR.CBMI)){ // use the boot index from PPM to choose the PL for PPCC + case(0){ + If(LAnd(LGreaterEqual(\_PR.CLVL,1),LLessEqual(\_PR.CLVL,3))){ + CPL0() // copy PL0 values to PPCC + Store(1,XPCC) + } + } + case(1){ + If(LOr(LEqual(\_PR.CLVL,2),LEqual(\_PR.CLVL,3))){ + CPL1() // copy PL1 values to PPCC + Store(1,XPCC) + } + } + case(2){ + If(LEqual(\_PR.CLVL,3)){ + CPL2() // copy PL2 values to PPCC + Store(1,XPCC) + } + } + } + } + Return(NPCC) + } + + // PPCC (Participant Power Control Capabilities) + // + // The PPCC object evaluates to a package of packages that indicates to DPTF processor + // participant the power control capabilities. + // + // Arguments: (0) + // None + // Return Value: + // PPCC package of packages + // + // PPCC will be initialized by the _INI method with power on default values from the PPM code. + // + Name (NPCC, Package() + { // Field Name : Field Type + 2, // Revision : DWordConst + + Package () // Power Limit 1 + { + 0, // PowerLimitIndex : DWordConst = 0 + 35000, // PowerLimitMinimum : DWordConst + 45000, // PowerLimitMaximum : DWordConst + 28, // TimeWindowMinimum : DWordConst + 32, // TimeWindowMaximum : DWordConst + 1000, // StepSize : DWordConst + }, + Package () // Power Limit 2 + { + 1, // PowerLimitIndex : DWordConst = 1 + 56250, // PowerLimitMinimum : DWordConst + 56250, // PowerLimitMaximum : DWordConst + 0, // TimeWindowMinimum : DWordConst + 0, // TimeWindowMaximum : DWordConst + 1000, // StepSize : DWordConst + } + }) // End of PPCC object + + + // CPNU (Convert Power Number from MMIO register to correct Units) + // + // Arguments: (1) + // Arg0 = Number to be converted + // Arg1 = Units desired + // 0 = Watts + // 1 = MilliWatts + // Return Value: + // Converted integer + // + Method(CPNU,2,Serialized,,IntObj) + { + Name(CNVT,0) // converted number + Name(PPUU,0) // units + Name(RMDR,0) // remainder + + if (LEqual(PWRU,0)) { // use PACKAGE_POWER_SKU_UNIT - Power Units[3:0] + Store(1,PPUU) + } else { + ShiftLeft(Decrement(PWRU),2,PPUU) // get units + } + Divide(Arg0,PPUU,RMDR,CNVT) // convert Arg0 to Watts + + if(LEqual(Arg1,0)){ + Return(CNVT) // return in watts + } else { + Multiply(CNVT,1000,CNVT) // convert to milliwatts + Multiply(RMDR,1000,RMDR) // convert remainder to a useful integer + Divide(RMDR,PPUU,Local0,RMDR) // convert remainder to watts + Add(CNVT,RMDR,CNVT) // add the integer part and the fraction part together + Return(CNVT) // return in milliwatts + } + } + + // MIN4 (find next lower rounded multiple of 4) + // + // Arguments: (1) + // Number to be converted + // Return Value: + // Converted integer + // + Method(MIN4,1,Serialized,,IntObj) + { + Name(RMDR,0) // remainder + Name(DIVD,0) // dividend + + Store(CPNU(Arg0,0),DIVD) // to convert Arg0 to Watts + + Subtract(DIVD,1,DIVD) + If(LOr(LLess(DIVD,4),LEqual(DIVD,0))){ + Return(1) + } Else{ + Divide(DIVD,4,RMDR) + } + + While(LNotEqual(RMDR,0)){ + Subtract(DIVD,1,DIVD) + If(LNotEqual(DIVD,0)){ + Divide(DIVD,4,RMDR) + } + } + + Return(Multiply(DIVD,1000)) // return in milliwatts + } + + // MAX4 (find next higher rounded multiple of 4) + // + // Arguments: (1) + // Number to be converted + // Return Value: + // Converted integer + // + Method(MAX4,1,Serialized,,IntObj) + { + Name(RMDR,0) // remainder + Name(DIVD,0) // dividend + + Store(CPNU(Arg0,0),DIVD) // to convert Arg0 to Watts + + Add(DIVD,1,DIVD) + Divide(DIVD,4,RMDR) + + While(LNotEqual(RMDR,0)){ + Add(DIVD,1,DIVD) + Divide(DIVD,4,RMDR) + } + + Return(Multiply(DIVD,1000)) // return in milliwatts + } + + // CPL0 (Copy PL0 power limits to PPCC) + // + // Arguments: + // None + // Return Value: + // None + // + Method(CPL0,0) + { + Store (2,Index(\_SB.PCI0.B0D4.NPCC,0)) // Revision + Store (0,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),0)) // PowerLimitIndex + If (LEqual(\MPLT, 0)){ + Store (MIN4(\_PR.PL10),Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),1)) // PowerLimitMinimum + } Else { + Store (\MPLT,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),1)) // PowerLimitMinimum + } + Store (CPNU(\_PR.PL10,1),Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),2)) // PowerLimitMaximum + Store (\_PR.PLW0,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),3)) // TimeWindowMinimum + Add (\_PR.PLW0,4,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),4)) // TimeWindowMaximum + Store (PPSZ,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),5)) // StepSize + Store (1,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,2)),0)) // PowerLimitIndex + Store (CPNU(\_PR.PL20,1),Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,2)),1)) // PowerLimitMinimum + Store (CPNU(\_PR.PL20,1),Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,2)),2)) // PowerLimitMaximum + Store (0,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,2)),3)) // TimeWindowMinimum + Store (0,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,2)),4)) // TimeWindowMaximum + Store (PPSZ,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,2)),5)) // StepSize + } + + // CPL1 (Copy PL1 power limits to PPCC) + // + // Arguments: + // None + // Return Value: + // None + // + Method(CPL1,0) + { + Store (2,Index(\_SB.PCI0.B0D4.NPCC,0)) // Revision + Store (0,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),0)) // PowerLimitIndex + If (LEqual(\MPLT, 0)){ + Store (MIN4(\_PR.PL11),Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),1)) // PowerLimitMinimum + } Else { + Store (\MPLT,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),1)) // PowerLimitMinimum + } + Store (CPNU(\_PR.PL11,1),Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),2)) // PowerLimitMaximum + Store (\_PR.PLW1,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),3)) // TimeWindowMinimum + Add (\_PR.PLW1,4,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),4)) // TimeWindowMaximum + Store (PPSZ,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),5)) // StepSize + Store (1,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,2)),0)) // PowerLimitIndex + Store (CPNU(\_PR.PL21,1),Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,2)),1)) // PowerLimitMinimum + Store (CPNU(\_PR.PL21,1),Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,2)),2)) // PowerLimitMaximum + Store (0,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,2)),3)) // TimeWindowMinimum + Store (0,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,2)),4)) // TimeWindowMaximum + Store (PPSZ,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,2)),5)) // StepSize + } + + // CPL2 (Copy PL2 power limits to PPCC) + // + // Arguments: + // None + // Return Value: + // None + // + Method(CPL2,0) + { + Store (2,Index(\_SB.PCI0.B0D4.NPCC,0)) // Revision + Store (0,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),0)) // PowerLimitIndex + If (LEqual(\MPLT, 0)){ + Store (MIN4(\_PR.PL12),Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),1)) // PowerLimitMinimum + } Else { + Store (\MPLT,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),1)) // PowerLimitMinimum + } + Store (CPNU(\_PR.PL12,1),Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),2)) // PowerLimitMaximum + Store (\_PR.PLW2,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),3)) // TimeWindowMinimum + Add (\_PR.PLW2,4,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),4)) // TimeWindowMaximum + Store (PPSZ,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,1)),5)) // StepSize + Store (1,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,2)),0)) // PowerLimitIndex + Store (CPNU(\_PR.PL22,1),Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,2)),1)) // PowerLimitMinimum + Store (CPNU(\_PR.PL22,1),Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,2)),2)) // PowerLimitMaximum + Store (0,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,2)),3)) // TimeWindowMinimum + Store (0,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,2)),4)) // TimeWindowMaximum + Store (PPSZ,Index(DerefOf(Index(\_SB.PCI0.B0D4.NPCC,2)),5)) // StepSize + } + + Name (LSTM,0) // Last temperature reported + + // _PPC (Performance Present Capabilities) + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the range of states supported + // 0 - States 0 through nth state are available (all states available) + // 1 - States 1 through nth state are available + // 2 - States 2 through nth state are available + // ... + // n - State n is available only + // + Name(_PPC,0) + + // SPPC (Set Participant Performance Capability) + // + // SPPC is a control method object that takes one integer parameter that will indicate the maximum allowable + // P-State for OSPM to use at any given time. + // + // Arguments: (1) + // Arg0 - integer + // Return Value: + // None + // + Method(SPPC,1,Serialized) + { + Store(Arg0, \_PR.CPU0._PPC) // Note: CPU0._PPC is an Integer not a Method + + If(CondRefOf(\_SB.PCCD.PENB)) { // is CPPC enabled in SETUP? + Notify(\_SB.PCCD,0x82) // CPPC notify + } Else { + Switch(ToInteger(TCNT)){ + Case(8){ + Notify(\_PR.CPU0, 0x80) // Tell CPU0 driver to re-eval _PPC + Notify(\_PR.CPU1, 0x80) // Tell CPU1 driver to re-eval _PPC + Notify(\_PR.CPU2, 0x80) // Tell CPU2 driver to re-eval _PPC + Notify(\_PR.CPU3, 0x80) // Tell CPU3 driver to re-eval _PPC + Notify(\_PR.CPU4, 0x80) // Tell CPU4 driver to re-eval _PPC + Notify(\_PR.CPU5, 0x80) // Tell CPU5 driver to re-eval _PPC + Notify(\_PR.CPU6, 0x80) // Tell CPU6 driver to re-eval _PPC + Notify(\_PR.CPU7, 0x80) // Tell CPU7 driver to re-eval _PPC + } + Case(4){ + Notify(\_PR.CPU0, 0x80) // Tell CPU0 driver to re-eval _PPC + Notify(\_PR.CPU1, 0x80) // Tell CPU1 driver to re-eval _PPC + Notify(\_PR.CPU2, 0x80) // Tell CPU2 driver to re-eval _PPC + Notify(\_PR.CPU3, 0x80) // Tell CPU3 driver to re-eval _PPC + } + Case(2){ + Notify(\_PR.CPU0, 0x80) // Tell CPU0 driver to re-eval _PPC + Notify(\_PR.CPU1, 0x80) // Tell CPU1 driver to re-eval _PPC + } + Default{ + Notify(\_PR.CPU0, 0x80) // Tell CPU0 driver to re-eval _PPC + } + } + } + } + + Name (TLPO, Package() + { + 1, // Revision, DwordConst + 1, // LPOEnable, DwordConst + 0, // LPOStartPState, DwordConst + 1, // LPOStepSize, DwordConst + 1, // LPOPowerControlSetting, DwordConst + 2 // LPOPerformanceControlSetting, DwordConst + }) + + // CLPO (Current Logical Processor Off lining Setting) + // + // This object is utilized only by DPPM Passive policy. It is not required to implement this object for LPM. + // + // Arguments: (0) + // None + // Return Value: + // This object evaluates to a package that indicates the LPO Control preferences. + // + Method(CLPO,,,,PkgObj) + { + Store (LPOE,Index(TLPO,1)) // LPOEnable + + If(CondRefOf(\_PR.CPU0._PSS)){ // LPOStartPState + Store(SizeOf(\_PR.CPU0._PSS()),Local1) // bounds check with _PSS + } // + Else // + { // + Store (0,Local1) // + } // + If(LLess(LPOP,Local1)){ // + Store (LPOP,Index(TLPO,2)) // + } // + Else // + { // + Decrement(Local1) // Index of LFM entry in _PSS + Store (Local1,Index(TLPO,2)) // + } // + + Store (LPOS,Index(TLPO,3)) // LPOStepSize + Store (LPOW,Index(TLPO,4)) // LPOPowerControlSetting + Store (LPER,Index(TLPO,5)) // LPOPerformanceControlSetting + + Return(TLPO) + } + + // AEXL (Application Exclusion List) + // + // There is a limit of 256 strings for this package. If the list is a bigger number than the limit, it is not effective to use LPO. + // + // Arguments: (0) + // None + // Return Value: + // This object evaluates to a package of strings representing the application names that the DPTF processor participant + // will exclude from core off lining when LPO is triggered. + // + Name (AEXL, Package() + { + "svchost.exe", "dllhost.exe", "smss.exe", "WinSAT.exe" + }) + + // PCCC (Participant Current Control Capabilities) + // + // The PCCC object evaluates to a package of packages that indicates to DPTF processor participant the Icc control capabilities. + // + // Arguments: (0) + // None + // + // Return Value: + // A package of packages as described below: + // + // Package() + // { + // 0x80000000, // DWordConst, Revision + // Package () + // { + // 0x80000000, // DWordConst, CurrentLimitMinimum in milli Amps + // 0x80000000, // DWordConst, CurrentLimitMaximum in milli Amps + // } + // } + Method(PCCC,0,Serialized,,PkgObj) + { + Store (1,Index(PCCX,0)) // Revision + Switch(ToInteger(CPNU(PTDP,0))){ // SKU check + case(57){ + Store (43000,Index(DerefOf(Index(PCCX,1)),0)) // CurrentLimitMinimum + Store (95000,Index(DerefOf(Index(PCCX,1)),1)) // CurrentLimitMaximum + } + case(47){ + Store (39000,Index(DerefOf(Index(PCCX,1)),0)) // CurrentLimitMinimum + Store (85000,Index(DerefOf(Index(PCCX,1)),1)) // CurrentLimitMaximum + } + case(37){ + Store (29000,Index(DerefOf(Index(PCCX,1)),0)) // CurrentLimitMinimum + Store (55000,Index(DerefOf(Index(PCCX,1)),1)) // CurrentLimitMaximum + } + case(25){ + Store (16000,Index(DerefOf(Index(PCCX,1)),0)) // CurrentLimitMinimum + Store (32000,Index(DerefOf(Index(PCCX,1)),1)) // CurrentLimitMaximum + } + case(15){ + Store (14000,Index(DerefOf(Index(PCCX,1)),0)) // CurrentLimitMinimum + Store (32000,Index(DerefOf(Index(PCCX,1)),1)) // CurrentLimitMaximum + } + case(11){ + Store (14000,Index(DerefOf(Index(PCCX,1)),0)) // CurrentLimitMinimum + Store (25000,Index(DerefOf(Index(PCCX,1)),1)) // CurrentLimitMaximum + } + Default{ // UNKNOWN SKU + Store (0xFF,Index(DerefOf(Index(PCCX,1)),0)) // CurrentLimitMinimum + Store (0xFF,Index(DerefOf(Index(PCCX,1)),1)) // CurrentLimitMaximum + } + } // End of Switch(PTDP) + + Return(PCCX) + } // End of PCCC object + + // PCCX (Participant Current Control Capabilities temp structure) + // + // This is used to pass data from the PCCC object to the PDRT object. + // + Name (PCCX, Package() + { + 0x80000000, // DWordConst, Revision + + Package () + { + 0x80000000, // DWordConst, CurrentLimitMinimum + 0x80000000, // DWordConst, CurrentLimitMaximum + } + }) // End of PCCC object + + // KEFF (VR efficiency Table) + // + // This object evaluates to a package of packages that indicates the VR efficiency factor for various processor power. + // + // Arguments: (0) + // None + // + // Return Value: + // A package of packages. + // + Name(KEFF, Package() + { + // Processor PMAX, Efficiency + Package () {444, 0}, + Package () {463, 39}, + Package () {481, 75}, + Package () {499, 108}, + Package () {518, 139}, + Package () {536, 168}, + Package () {554, 195}, + Package () {573, 221}, + Package () {591, 244}, + Package () {609, 267}, + Package () {628, 287}, + Package () {812, 445}, + Package () {983, 551}, + Package () {1163, 621}, + Package () {1342, 673}, + Package () {1527, 710}, + Package () {1704, 742}, + Package () {1885, 767}, + Package () {2072, 785}, + Package () {2255, 802}, + Package () {6044, 897}, + Package () {11740, 924}, + Package () {17576, 926}, + Package () {23605, 919}, + Package () {29821, 909}, + Package () {36223, 898}, + Package () {42856, 886}, + Package () {49723, 873}, + Package () {56870, 858}, + Package () {64380, 842} + }) + + Name (CEUP, Package() + { + 0x80000000, + 0x80000000, + 0x80000000, + 0x80000000, + 0x80000000, + 0x80000000 + }) + + // CEUC (Current Execution Unit Configuration) + // + // This object evaluates to a package that indicates the Execution Unit Control preferences. + // + // Arguments: (0) + // None + // Return Value: + // Package { + // Revision // DWordConst - 0x1 for Sharkbay and Clovertrail platform. + // EUEnable // DwordConst - If this option is 0 then policy does not use any active core controls for graphics. + // TargetGfxFreq // DwordConst - Returns graphics frequency in MHz. + // MaxActiveEUs // DwordConst - Provides the max limit for the number of EUs that driver can request while in passive control. + // MinActiveEUs // DwordConst - Provides the min limit for the number of EUs that driver can request while in passive control. + // StepSize // DwordConst - Instructs the policy to take away EU in the specified percentage steps. E.g. if StepSize is 50% then policy would take away 1/2 of EUs at a time. + // } + // + Method(CEUC,,,,PkgObj) + { + Store(0x1, Index(CEUP,0)) // Revision + Store(ECEU, Index(CEUP,1)) // Enable/disable + Store(TGFG, Index(CEUP,2)) // Gfx frequency + Store(40, Index(CEUP,3)) // Max + Store(20, Index(CEUP,4)) // Min + Store(20, Index(CEUP,5)) // step size + + Return(CEUP) + } // end of CEUC object + + // _TMP (Temperature) + // + // This control method returns the thermal zone's current operating temperature. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin) + // + //AMI override begin + //Method(_TMP) + Method(TMPX) + //AMI override end + { + // Return the temperature to the OS if EC access is enabled. + If(\ECON) + { + Return(\_SB.IETM.CTOK(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PMAX)))) + } + Else + { + // Return a static value if EC access is disabled. + Return(3000) + } + } + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(B0D4, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius, this could be a platform policy with setup item + } + + // _PSS (Performance Supported States) + // + // This optional object indicates to OSPM the number of supported processor performance states that any given system can support. + // + // Arguments: (1) + // None + // Return Value: + // A variable-length Package containing a list of Pstate sub-packages as described below + // + // Return Value Information + // Package { + // PState [0] // Package - Performance state 0 + // .... + // PState [n] // Package - Performance state n + // } + // + // Each Pstate sub-Package contains the elements described below: + // Package { + // CoreFrequency // Integer (DWORD) + // Power // Integer (DWORD) + // Latency // Integer (DWORD) + // BusMasterLatency // Integer (DWORD) + // Control // Integer (DWORD) + // Status // Integer (DWORD) + // } + // + // Stub for the Actual CPU _PSS method. + // + Method(_PSS,,,,PkgObj) + { + If(CondRefOf(\_PR.CPU0._PSS)) + { // Ensure _PSS is present + Return(\_PR.CPU0._PSS()) + } Else { + Return(Package(){ + Package(){0,0,0,0,0,0}, + Package(){0,0,0,0,0,0}}) + } + } + + // _TSS (Throttling Supported States) + // + // Arguments: (0) + // None + // Return Value: + // A variable-length Package containing a list of Tstate sub-packages as described below + // + // Return Value Information + // Package { + // TState [0] // Package - Throttling state 0 + // .... + // TState [n] // Package - Throttling state n + // } + // + // Each Tstate sub-Package contains the elements described below: + // Package { + // Percent // Integer (DWORD) + // Power // Integer (DWORD) + // Latency // Integer (DWORD) + // Control // Integer (DWORD) + // Status // Integer (DWORD) + // } + // + // Stub for the Actual CPU _TSS method. + // + Method(_TSS,,,,PkgObj) + { + If(CondRefOf(\_PR.CPU0._TSS)) + { // Ensure _TSS is present + Return(\_PR.CPU0._TSS()) + } Else { + Return(Package(){ + Package(){0,0,0,0,0}, + Package(){0,0,0,0,0}}) + } + } + + // _TPC (Throttling Present Capabilities) + // + // This optional object is a method that dynamically indicates to OSPM the number of throttling states currently supported by the platform. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the number of states supported: + // 0 - states 0 .. nth state available (all states available) + // 1 - state 1 .. nth state available + // 2 - state 2 .. nth state available + // ... + // n - state n available only + // + Method(_TPC) + { + If(CondRefOf(\_PR.CPU0._TPC)) + { // Ensure _TPC is present + Return(\_PR.CPU0._TPC) + } Else { + Return(0) + } + } + + // _PTC (Processor Throttling Control) + // + // _PTC is an optional object that defines a processor throttling control interface alternative to the I/O address spaced-based P_BLK throttling control register (P_CNT) + // + // PDC0[2] = ACPI object indicating if OSPM is capable of direct access to On Demand throttling MSR + // + // Arguments: (0) + // None + // Return Value: + // A Package as described below + // + // Return Value Information + // Package { + // ControlRegister // Buffer (Resource Descriptor) + // StatusRegister // Buffer (Resource Descriptor) + // } + // + Method(_PTC,,,,PkgObj) + { + If(LAnd(CondRefOf(\PDC0),LNotEqual(\PDC0,0x80000000))) // is object present and initialized? + { + If(And(\PDC0, 0x0004)) { // does OS support MSR interface? + Return(Package() { + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} }) // if OS supports MSR interface + } Else { + Return(Package() { + ResourceTemplate(){Register(SystemIO, 5, 0, PCH_ACPI_PBLK)}, + ResourceTemplate(){Register(SystemIO, 5, 0, PCH_ACPI_PBLK)} }) // if OS support IO based interface + } + } Else { + Return(Package() { + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} }) // if object is not present or not initialized then return MSR interface + } + } + + // _TSD (T-State Dependency) + // + // This optional object provides T-state control cross logical processor dependency information to OSPM. + // + // Arguments: (0) + // None + // Return Value: + // A variable-length Package containing a list of T-state dependency Packages as described below. + // + // Return Value Information + // Package { + // NumEntries // Integer + // Revision // Integer (BYTE) + // Domain // Integer (DWORD) + // CoordType // Integer (DWORD) + // NumProcessors // Integer (DWORD) + // } + // + Method(_TSD,,,,PkgObj) + { + If(CondRefOf(\_PR.CPU0._TSD)) + { // Ensure _TSD is present + Return(\_PR.CPU0._TSD()) + } Else { + Return(Package(){ + Package(){5,0,0,0,0}, + Package(){5,0,0,0,0}}) + } + } + + // _TDL (T-state Depth Limit) + // + // This optional object evaluates to the _TSS entry number of the lowest power throttling state that OSPM may use. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the Throttling Depth Limit _TSS entry number: + // 0 - throttling disabled. + // 1 - state 1 is the lowest power T-state available. + // 2 - state 2 is the lowest power T-state available. + // ... + // n - state n is the lowest power T-state available. + // + Method(_TDL) + { + If(LAnd(CondRefOf(\_PR.CPU0._TSS),CondRefOf(\_PR.CFGD))) + { // Ensure _TSS is present + If(And(\_PR.CFGD, PPM_TSTATE_FINE_GRAINED)) + { + Return(Subtract(SizeOf(\_PR.CPU0.TSMF),1)) + } Else { + Return(Subtract(SizeOf(\_PR.CPU0.TSMC),1)) + } + } Else { + Return(0) + } + } + + // _PDL (P-state Depth Limit) + // + // This optional object evaluates to the _PSS entry number of the lowest performance P-state that OSPM may use when performing passive thermal control. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the P-state Depth Limit _PSS entry number: + // Integer containing the P-state Depth Limit _PSS entry number: + // 0 - P0 is the only P-state available for OSPM use + // 1 - state 1 is the lowest power P-state available + // 2 - state 2 is the lowest power P-state available + // ... + // n - state n is the lowest power P-state available + // + Method(_PDL) + { + If(CondRefOf(\_PR.CPU0._PSS)) + { // Ensure _PSS is present + Return(Subtract(SizeOf(\_PR.CPU0._PSS),1)) + } Else { + Return(0) + } + } +//AMI override for BSOD issue +} // End Scope(\_SB.PCI0.B0D4) +/* + }// End Device(B0D4) +} // End Scope(\_SB.PCI0) +*/ +//AMI override for BSOD issue
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/DplyParticipant.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/DplyParticipant.asl new file mode 100644 index 0000000..d27182c --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/DplyParticipant.asl @@ -0,0 +1,176 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + DplyParticipant.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ +Scope(\_SB.PCI0) +{ + + Device(DPLY) // Display participant + { + Name(_HID, EISAID("INT3406")) + Name(_UID, 0) + + Name(BDLI, 32) // Brightness depth limit index corresponding to 30% + Name(BDHI, 82) // Brightness peformance/power ceiling limit index corresponding to 80% + + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(DISE,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + // DDDL ( Dptf Display Depth Limit) + // + // The DDDL object indicates dynamically a lower limit on the brightness control levels currently supported by the platform + // for the participant. Value returned indicates a Power/Percentage value that is in the _BCL brightness list. + // + // Arguments: (0) + // None + // Return Value: + // Index in Brightness level list + // + Method(DDDL, 0) + { + Return(BDLI) + } + + // DDPC ( Dptf Display Power/performance Control) + // + // The DDPC object indicates dynamically a higher limit (ceiling) on the brightness control levels currently supported by + // the platform for the participant. + // + // Arguments: (0) + // None + // Return Value: + // Index in Brightness level list + // + Method(DDPC, 0) + { + Return(BDHI) + } + + // _BCL (Query List of Brightness Control Levels Supported) + // + // Arguments: (0) + // None + // Return Value: + // A variable-length Package containing a list of Integers representing the supported brightness levels. + // Each integer has 8 bits of significant data. + // List of supported brightness levels in the following sequence: + // Level when machine has full power. + // Level when machine is on batteries. + // Other supported levels. + // Package(){80, 50, 0, 1, 2, 3, 4, 5, ..., 96, 97, 98, 99, 100} + // + Method(_BCL,,,,PkgObj) + { + If(CondRefOf(\_SB.PCI0.GFX0.DD1F._BCL)) + { + Return(\_SB.PCI0.GFX0.DD1F._BCL()) + } Else { + Return(Package(){0}) + } + } + + // _BCM (Set the Brightness Level) + // + // Arguments: (1) + // Arg0 - An Integer containing the new brightness level + // Return Value: + // None + // + Method(_BCM,1) + { + If(CondRefOf(\_SB.PCI0.GFX0.DD1F._BCM)) + { + \_SB.PCI0.GFX0.DD1F._BCM(Arg0) + } + } + + // _BQC (Brightness Query Current level) + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current brightness level (must be one of the values returned from the _BCL method) + // + Method(_BQC,0) + { + If(CondRefOf(\_SB.PCI0.GFX0.DD1F._BQC)) + { + Return(\_SB.PCI0.GFX0.DD1F._BQC()) + } Else { + Return(0x00) + } + } + + // _DCS (Return the Status of Output Device) + // + //Arguments: (0) + // None + // Return Value: + // An Integer containing the device status (32 bits) + // Bit Definitions + // [0] - Output connector exists in the system now + // [1] - Output is activated + // [2] - Output is ready to switch + // [3] - Output is not defective (it is functioning properly) + // [4] - Device is attached (this is optional) + // [31:5] Reserved (must be zero) + // + Method(_DCS,0) + { + If(CondRefOf(\_SB.PCI0.GFX0.DD1F._DCS)) + { + Return(\_SB.PCI0.GFX0.DD1F._DCS()) + } Else { + Return(0x00) + } + } + + } // End DPLY Device +}// end Scope(\_SB.PCI0) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Dppm.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Dppm.asl new file mode 100644 index 0000000..f912020 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Dppm.asl @@ -0,0 +1,66 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + Dppm.asl + +Abstract: + + Intel ACPI Reference Code for Intel Dynamic Power Performance Management + +--*/ + + +Scope(\_SB.IETM) +{ + + // + // DPPM Passive Policy + // + Name (DPSP, Package () + { + ToUUID("42A441D6-AE6A-462B-A84B-4A8CE79027D3"), + }) + + // + // DPPM Active Policy + // + Name (DASP, Package () + { + ToUUID("3A95C389-E4B8-4629-A526-C52C88626BAE"), + }) + + // + // DPPM Crtical Policy + // + Name (DCSP, Package () + { + ToUUID("97C68AE7-15FA-499c-B8C9-5DA81D606E0A"), + }) + + // + // DPPM Cooling Mode Policy + // + Name (DMSP, Package () + { + ToUUID("16CAF1B7-DD38-40ed-B1C1-1B8A1913D531") + }) +} // End Scope(\_SB.IETM) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Dptf.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Dptf.asl new file mode 100644 index 0000000..38244b1 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Dptf.asl @@ -0,0 +1,852 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + Dptf.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +#include "PowerMgmtDefinitions.h" + +DefinitionBlock ( + "Dptf.aml", + "SSDT", + 1, + "DptfTabl", + "DptfTabl", + 0x1000 + ) +{ + + +External(P8XH, MethodObj) +External(ECON, IntObj) +External(TSOD, IntObj) +External(PNHM, IntObj) +External(TCNT, IntObj) +External(\MPLT, IntObj) +External(\PWRS, Intobj) +External(LPMV, IntObj) +External(CRTT, IntObj) +External(ATMC, IntObj) +External(PTMC, IntObj) +External(ATRA, IntObj) +External(PTRA, IntObj) +External(ACTT, IntObj) +External(PSVT, IntObj) +External(ATPC, IntObj) +External(PTPC, IntObj) + +External(DPTF, IntObj) // EnableDptf +External(SADE, IntObj) // EnableSaDevice +External(SACR, IntObj) // CriticalThermalTripPointSa +External(SAHT, IntObj) // HotThermalTripPointSa + +External(PCHD, IntObj) // EnablePchDevice +External(PCHC, IntObj) // CriticalThermalTripPointPch +External(PCHH, IntObj) // HotThermalTripPointPch + +External(MEMD, IntObj) // EnableMemoryDevice +External(MEMC, IntObj) // CriticalThermalTripPointTMEM +External(MEMH, IntObj) // HotThermalTripPointTMEM + +External(FND1, IntObj) // EnableFan1Device +External(FND2, IntObj) // EnableFan2Device + +External(AMBD, IntObj) // EnableAmbientDevice +External(AMAT, IntObj) // ActiveThermalTripPointAmbient +External(AMPT, IntObj) // PassiveThermalTripPointAmbient +External(AMCT, IntObj) // CriticalThermalTripPointAmbient +External(AMHT, IntObj) // HotThermalTripPointAmbient + +External(SKDE, IntObj) // EnableSkinDevice +External(SKAT, IntObj) // ActiveThermalTripPointSkin +External(SKPT, IntObj) // PassiveThermalTripPointSkin +External(SKCT, IntObj) // CriticalThermalTripPointSkin +External(SKHT, IntObj) // HotThermalTripPointSkin + +External(EFDE, IntObj) // EnableExhaustFanDevice +External(EFAT, IntObj) // ActiveThermalTripPointExhaustFan +External(EFPT, IntObj) // PassiveThermalTripPointExhaustFan +External(EFCT, IntObj) // CriticalThermalTripPointExhaustFan +External(EFHT, IntObj) // HotThermalTripPointExhaustFan + +External(VRDE, IntObj) // EnableVRDevice +External(VRAT, IntObj) // ActiveThermalTripPointVR +External(VRPT, IntObj) // PassiveThermalTripPointVR +External(VRCT, IntObj) // CriticalThermalTripPointVR +External(VRHT, IntObj) // HotThermalTripPointVR + +External(WIFD, IntObj) // EnableWifiDevice +External(WFAT, IntObj) // ActiveThermalTripPointWifi +External(WFPT, IntObj) // PassiveThermalTripPointWifi +External(WFCT, IntObj) // CriticalThermalTripPointWifi +External(WFHT, IntObj) // ActiveHotThermalTripPointWifi + +External(WAND, IntObj) // EnableWWANDevice +External(WWAT, IntObj) // ActiveThermalTripPointWWAN +External(WWPT, IntObj) // PassiveThermalTripPointWWAN +External(WWCT, IntObj) // CriticalThermalTripPointWWAN +External(WWHT, IntObj) // ActiveHotThermalTripPointWWAN + +External(WGID, IntObj) // EnableWGigDevice +External(WGAT, IntObj) // ActiveThermalTripPointWGig +External(WGPT, IntObj) // PassiveThermalTripPointWGig +External(WGCT, IntObj) // CriticalThermalTripPointWGig +External(WGHT, IntObj) // ActiveHotThermalTripPointWGig + +External(CTDP, IntObj) // EnableCtdpPolicy +External(LPMP, IntObj) // EnableLpmPolicy +External(DPAP, IntObj) // EnableActivePolicy +External(DPPP, IntObj) // EnablePassivePolicy +External(DPCP, IntObj) // EnableCriticalPolicy +External(DCMP, IntObj) // EnableCoolingModePolicy +External(ECEU, IntObj) // EnableCurrentExecutionUnit +External(TGFG, IntObj) // TargetGfxFreq +External(TRTV, IntObj) // TrtRevision +External(PWRE, IntObj) // EnablePowerDevice +External(PWRP, IntObj) // EnablePowerPolicy + +External(LPOE, IntObj) // LPOEnable +External(LPOP, IntObj) // LPOStartPState +External(LPOS, IntObj) // LPOStepSize +External(LPOW, IntObj) // LPOPowerControlSetting +External(LPER, IntObj) // LPOPerformanceControlSetting + +External(PPSZ, IntObj) // PPCC Step Size +External(\PDC0, IntObj) // CPU0 _PDC Flags + +External(\_TZ.ETMD, IntObj) +External(\_TZ.TZ00, ThermalZoneObj) +External(\_TZ.TZ01, ThermalZoneObj) + +External(\_SB.PCI0, DeviceObj) +External(\_SB.PCI0.B0D4, DeviceObj) +External(\_SB.PCI0.MHBR, FieldUnitObj) + +External(\_SB.PCI0.LPCB.H_EC, DeviceObj) +External(\_SB.PCI0.LPCB.H_EC.ECAV, IntObj) +External(\_SB.PCI0.LPCB.H_EC.ECMD, MethodObj) +External(\_SB.PCI0.LPCB.H_EC.ECRD, MethodObj) // EC Read Method +External(\_SB.PCI0.LPCB.H_EC.ECWT, MethodObj) // EC Write Method +External(\_SB.PCI0.LPCB.H_EC.ECF2, OpRegionObj) +External(\_SB.PCI0.LPCB.H_EC.SKNT, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.CVRT, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.FANT, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.AMBT, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.PPSL, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.PPSH, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.PINV, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.PENV, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.PSTP, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.CMDR, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.TSD0, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.TSD1, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.DIM0, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.DIM1, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.CFSP, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.CPUP, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.CPAP, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.PMAX, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.PECH, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.CFAN, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.TSI, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.HYST, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.TSHT, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.TSLT, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.TSSR, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.B1RC, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.B1FC, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.BAT1._BST, MethodObj) +External(\_SB.PCI0.LPCB.H_EC.B1ML, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.B1MH, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.PPWR, FieldUnitObj) + +External(\_PR.CPU0, ProcessorObj) +External(\_PR.CPU0._PSS, MethodObj) +External(\_PR.CPU0._PPC, IntObj) +External(\_PR.CPU0._TSS, MethodObj) +External(\_PR.CFGD, FieldUnitObj) +External(\_PR.CPU0.TSMF, PkgObj) +External(\_PR.CPU0.TSMC, PkgObj) +External(\_PR.CPU0._PTC, MethodObj) +External(\_PR.CPU0._TSD, MethodObj) +External(\_PR.CPU0._TPC, IntObj) +External(\_PR.CPU1, ProcessorObj) +External(\_PR.CPU2, ProcessorObj) +External(\_PR.CPU3, ProcessorObj) +External(\_PR.CPU4, ProcessorObj) +External(\_PR.CPU5, ProcessorObj) +External(\_PR.CPU6, ProcessorObj) +External(\_PR.CPU7, ProcessorObj) + +External(\_PR.CLVL, FieldUnitObj) +External(\_PR.CBMI, FieldUnitObj) +External(\_PR.PL10, FieldUnitObj) +External(\_PR.PL20, FieldUnitObj) +External(\_PR.PLW0, FieldUnitObj) +External(\_PR.CTC0, FieldUnitObj) +External(\_PR.TAR0, FieldUnitObj) +External(\_PR.PL11, FieldUnitObj) +External(\_PR.PL21, FieldUnitObj) +External(\_PR.PLW1, FieldUnitObj) +External(\_PR.CTC1, FieldUnitObj) +External(\_PR.TAR1, FieldUnitObj) +External(\_PR.PL12, FieldUnitObj) +External(\_PR.PL22, FieldUnitObj) +External(\_PR.PLW2, FieldUnitObj) +External(\_PR.CTC2, FieldUnitObj) +External(\_PR.TAR2, FieldUnitObj) + +External(\_PR.APSV, FieldUnitObj) +External(\_PR.AAC0, FieldUnitObj) +External(\_PR.ACRT, FieldUnitObj) + +External(\_SB.PCCD.PENB, IntObj) + +// Display participant externals +External(DISE, IntObj) // EnableDisplayParticipant +External(\_SB.PCI0.GFX0.DD1F._BCL, MethodObj) +External(\_SB.PCI0.GFX0.DD1F._BCM, MethodObj) +External(\_SB.PCI0.GFX0.DD1F._BQC, MethodObj) +External(\_SB.PCI0.GFX0.DD1F._DCS, MethodObj) + +Scope(\_SB) +{ + // + // DPTF Thermal Zone Device + // + // + Device(IETM) + { + // + // Intel DPTF Thermal Framework Device + // + Name(_HID, EISAID("INT3400")) + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(DPTF,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + // + // Note: there are seven GUID packages in TMPP and up to seven matching store statements in IDSP. + // The store statements must never exceed the number of package elements to prevent an overrun. + // + Name(TMPP,Package() + { + ToUUID("00000000-0000-0000-0000-000000000000"), + ToUUID("00000000-0000-0000-0000-000000000000"), + ToUUID("00000000-0000-0000-0000-000000000000"), + ToUUID("00000000-0000-0000-0000-000000000000"), + ToUUID("00000000-0000-0000-0000-000000000000"), + ToUUID("00000000-0000-0000-0000-000000000000"), + ToUUID("00000000-0000-0000-0000-000000000000") + }) + + // + // Save original trip points so _OSC method can enable/disable Legacy thermal policies by manipulating trip points. + // + Name (PTRP,0) // Passive trip point + Name (PSEM,0) // Passive semaphore + Name (ATRP,0) // Active trip point + Name (ASEM,0) // Active semaphore + Name (YTRP,0) // Critical trip point + Name (YSEM,0) // Critical semaphore + + // IDSP (Intel DPTF Supported Policies) + // + // This object evaluates to a package of packages, with each package containing the UUID + // values to represent a policy implemented and supported by the Intel DPTF software stack. + // + // Arguments: (0) + // None + // Return Value: + // Package of Guid packages + // + Method(IDSP,0,Serialized,,PkgObj) + { + Name(TMPI,0) + + // Passive Policy GUID + If(LAnd(LEqual(DPPP,1),CondRefOf(DPSP))){ + Store(DeRefOf(Index(DPSP,0)), Index(TMPP,TMPI)) + Increment(TMPI) + } + + // Active Policy GUID + If(LAnd(LEqual(DPAP,1),CondRefOf(DASP))){ + Store(DeRefOf(Index(DASP,0)), Index(TMPP,TMPI)) + Increment(TMPI) + } + + // Critical Policy GUID + If(LAnd(LEqual(DPCP,1),CondRefOf(DCSP))){ + Store(DeRefOf(Index(DCSP,0)), Index(TMPP,TMPI)) + Increment(TMPI) + } + + // Cooling Mode Policy GUID + If(LAnd(LEqual(DCMP,1),CondRefOf(DMSP))){ + Store(DeRefOf(Index(DMSP,0)), Index(TMPP,TMPI)) + Increment(TMPI) + } + + // LPM policy GUID + If(LAnd(LEqual(LPMP,1),CondRefOf(LPSP))){ + Store(DeRefOf(Index(LPSP,0)), Index(TMPP,TMPI)) + Increment(TMPI) + } + + // CTDP Policy GUID + If(LAnd(LEqual(CTDP,1),CondRefOf(CTSP))){ + Store(DeRefOf(Index(CTSP,0)), Index(TMPP,TMPI)) + Increment(TMPI) + } + + //Power Policy GUID + If(LAnd(LEqual(PWRP,1),CondRefOf(WPSP))){ + Store(DeRefOf(Index(WPSP,0)), Index(TMPP,TMPI)) + } + + Return(TMPP) + } + + // _OSC (Operating System Capabilities) + // + // This object is evaluated by each DPTF policy implementation to communicate to the platform of the existence and/or control transfer. + // + // Arguments: (4) + // Arg0 - A Buffer containing a UUID + // Arg1 - An Integer containing a Revision ID of the buffer format + // Arg2 - An Integer containing a count of entries in Arg3 + // Arg3 - A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing a list of capabilities + // + Method(_OSC, 4,Serialized,,BuffObj,{BuffObj,IntObj,IntObj,BuffObj}) + { + Name(NUMP,0) + Name (UID2,ToUUID("FFFFFFFF-FFFF-FFFF-FFFF-FFFFFFFFFFFF")) + + // Point to Status DWORD in the Arg3 buffer (STATUS) + CreateDWordField(Arg3, 0, STS1) + + // Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES) + CreateDWordField(Arg3, 4, CAP1) + + // + // _OSC needs to validate the UUID and Revision. + // + // IF Unrecognized UUID + // Return Unrecognized UUID _OSC Failure + // IF Unsupported Revision + // Return Unsupported Revision _OSC Failure + // + // STS0[0] = Reserved + // STS0[1] = _OSC Failure + // STS0[2] = Unrecognized UUID + // STS0[3] = Unsupported Revision + // STS0[4] = Capabilities masked + // + // Get the platform UUID's that are available, this will be a package of packages. + // + IDSP() // initialize TMPP with GUID's + Store(SizeOf(TMPP),NUMP) // how many GUID's in the package? + + // Note: The comparison method used is necessary due to + // limitations of certain OSes which cannot perform direct + // buffer comparisons. + // + // Create a set of "Input" UUID fields. + // + CreateDWordField(Arg0, 0x0, IID0) + CreateDWordField(Arg0, 0x4, IID1) + CreateDWordField(Arg0, 0x8, IID2) + CreateDWordField(Arg0, 0xC, IID3) + // + // Create a set of "Expected" UUID fields. + // + CreateDWordField(UID2, 0x0, EID0) + CreateDWordField(UID2, 0x4, EID1) + CreateDWordField(UID2, 0x8, EID2) + CreateDWordField(UID2, 0xC, EID3) + // + // Compare the input UUID to the list of UUID's in the system. + // + While(NUMP){ + // + // copy one uuid from TMPP to UID2 + // + Store(DeRefOf (Index (TMPP, Subtract(NUMP,1))),UID2) + // + // Verify the input UUID matches the expected UUID. + // + If(LAnd(LAnd(LEqual(IID0, EID0), LEqual(IID1, EID1)), LAnd(LEqual(IID2, EID2), LEqual(IID3, EID3)))){ + Break // break out of while loop when matching UUID is found + } + Decrement(NUMP) + } + + If(LEqual(NUMP,0)){ + // + // Return Unrecognized UUID _OSC Failure + // + And(STS1,0xFFFFFF00,STS1) + Or(STS1,0x6,STS1) + Return(Arg3) + } + + If(LNot(LEqual(Arg1, 1))) + { + // + // Return Unsupported Revision _OSC Failure + // + And(STS1,0xFFFFFF00,STS1) + Or(STS1,0xA,STS1) + Return(Arg3) + } + + If(LNot(LEqual(Arg2, 2))) + { + // + // Return Argument 3 Buffer Count not sufficient + // + And(STS1,0xFFFFFF00,STS1) + Or(STS1,0x2,STS1) + Return(Arg3) + } + + // + // Passive Policy GUID + // + If(LAnd(LEqual(DPPP,1),CondRefOf(\_PR.APSV))){ + If(LEqual(PSEM,0)){ + Store(1,PSEM) + Store(\_PR.APSV,PTRP) // use semaphore so variable is only initialized once + } + // + // copy the GUID to UID2 + // + If(CondRefOf(DPSP)){ + Store(DeRefOf (Index (DPSP, 0)),UID2) + } + // + // Verify the test UUID matches the input UUID. + // + If(LAnd(LAnd(LEqual(IID0, EID0), LEqual(IID1, EID1)), LAnd(LEqual(IID2, EID2), LEqual(IID3, EID3)))){ + // do passive notify + If(Not(And(STS1, 0x01))) // Test Query Flag + { // Not a query operation, so process the request + If(And(CAP1, 0x01)) + { // Enable DPTF + // Nullify the legacy thermal zone. + Store(110,\_PR.APSV) + } Else { // Passive unloading, re-enable legacy thermal zone + Store(PTRP,\_PR.APSV) + } + // Send notification to legacy thermal zone for legacy policy to be enabled/disabled + Notify(\_TZ.TZ00, 0x80) + Notify(\_TZ.TZ01, 0x80) + } + Return(Arg3) + } + } + + // + // Active Policy GUID + // + If(LAnd(LEqual(DPAP,1),CondRefOf(\_PR.AAC0))){ + If(LEqual(ASEM,0)){ + Store(1,ASEM) + Store(\_PR.AAC0,ATRP) // use semaphore so variable is only initialized once + } + // + // copy the GUID to UID2 + // + If(CondRefOf(DASP)){ + Store(DeRefOf (Index (DASP, 0)),UID2) + } + // + // Verify the test UUID matches the input UUID. + // + If(LAnd(LAnd(LEqual(IID0, EID0), LEqual(IID1, EID1)), LAnd(LEqual(IID2, EID2), LEqual(IID3, EID3)))){ + // do active notify + If(Not(And(STS1, 0x01))) // Test Query Flag + { // Not a query operation, so process the request + If(And(CAP1, 0x01)) + { // Enable DPTF + // Nullify the legacy thermal zone. + Store(110,\_PR.AAC0) + } Else { // Passive unloading, re-enable legacy thermal zone + Store(ATRP,\_PR.AAC0) + } + // Send notification to legacy thermal zone for legacy policy to be enabled/disabled + Notify(\_TZ.TZ00, 0x80) + Notify(\_TZ.TZ01, 0x80) + } + Return(Arg3) + } + } + + // + // Critical Policy GUID + // + If(LAnd(LEqual(DPCP,1),CondRefOf(\_PR.ACRT))){ + If(LEqual(YSEM,0)){ + Store(1,YSEM) + Store(\_PR.ACRT,YTRP) // use semaphore so variable is only initialized once + } + // + // copy the GUID to UID2 + // + If(CondRefOf(DCSP)){ + Store(DeRefOf (Index (DCSP, 0)),UID2) + } + // + // Verify the test UUID matches the input UUID. + // + If(LAnd(LAnd(LEqual(IID0, EID0), LEqual(IID1, EID1)), LAnd(LEqual(IID2, EID2), LEqual(IID3, EID3)))){ + // do critical notify + If(Not(And(STS1, 0x01))) // Test Query Flag + { // Not a query operation, so process the request + If(And(CAP1, 0x01)) + { // Enable DPTF + // Nullify the legacy thermal zone. + Store(210,\_PR.ACRT) + } Else { // Passive unloading, re-enable legacy thermal zone + Store(YTRP,\_PR.ACRT) + } + // Send notification to legacy thermal zone for legacy policy to be enabled/disabled + Notify(\_TZ.TZ00, 0x80) + Notify(\_TZ.TZ01, 0x80) + } + Return(Arg3) + } + } + + Return(Arg3) + } + // KTOC (Kelvin to Celsius) + // + // This control method converts from 10ths of degree Kelvin to Celsius. + // + // Arguments: (1) + // Arg0 - Temperature in 10ths of degree Kelvin + // Return Value: + // Temperature in Celsius + // + Method(KTOC,1) + { + Subtract(Arg0, 2732, Local1) + If(LGreater(Local1,0)) // make sure we don't have a negative number + { + Return(Divide(Local1, 10)) + } + Else + { + Return(0) + } + } + + // CTOK (Celsius to Kelvin) + // + // This control method converts from Celsius to 10ths of degree Kelvin. + // + // Arguments: (1) + // Arg0 - Temperature in Celsius + // Return Value: + // Temperature in 10ths of degree Kelvin + // + Method(CTOK, 1) + { + If(And(Arg0, 0x1000)) // Round negative values up to Zero + { + Return(2372) + } + Multiply(Arg0,10,Local0) + And(Local0, 0x0FFF, Local1) + Add(Local1, 2732, Local2) + Return(Local2) + } + + // PDRT (power device relation table) + // + // This object evaluates to a package of packages that indicates the relation between charge rates and target devices. + // + // Arguments: (0) + // None + // Return Value: + // A variable-length package of packages as described below. + // + // Return Value Information + // Package { + // Package [0] // Package + // .... + // Package [n] // Package + // } + // + // Each sub-Package contains the elements described below: + // Package { + // ChargeRate // Integer (DWORD) + // TargetDevice // Integer (DWORD) + // PTYP // Integer (DWORD) + // ControlBuffer // Package + // } + // + Method(PDRT,,,,PkgObj) + { + \_SB.PCI0.B0D4.PCCC() // init global variable PCCX + If (\PWRS){ // check power source + PDAC() // AC table + } Else { + PDDC() // DC table + } + } // end Method(PDRT) + + Method(PDDC,,,,PkgObj) + { + Name(TMPD,Package() + { + Package() {80, \_SB.PCI0.B0D4, 0x09, Package () {0x00010001,0x80000000}}, // Package domain, PL2, target power from CPU PPM + Package() {60, \_SB.PCI0.B0D4, 0x09, Package () {0x00010000,0x80000000}}, // Package domain, PL1, target power from CPU PPM + Package() {55, \_SB.PCI0.B0D4, 0x09, Package () {0x00070000,1}}, // Package domain, Power Control Turbo Disable + Package() {50, \_SB.PCI0.B0D4, 0x09, Package () {0x00030000,0x80000000}}, // Imax Controls - 30A + Package() {50, \_SB.PCI0.B0D4, 0x00, Package () {0x00040000,2}}, // Core control - 2 cores + Package() {40, \_SB.PCI0.DPLY, 0x0A, Package () {0x00050000,60}}, // Display brightness - 60 + Package() {40, \_SB.PCI0.TMEM, 0x02, Package () {0x00010000,1000}}, // Memory domain, PL1, target power from TMEM.PPCC + Package() {30, \_SB.PCI0.B0D4, 0x00, Package () {0x00020000,80}}, // System Agent Thermal Device, target frequency - P State 80% + Package() {20, \_SB.PCI0.B0D4, 0x00, Package () {0x00020001,50}} // System Agent Thermal Device, target frequency - T State 50% + }) + + If(CondRefOf(\_PR.CBMI)){ + Switch(ToInteger(\_PR.CBMI)){ // use the boot index from PPM to choose the Power Limit values and copy them to local variables + case(0){ + If(LAnd(LGreaterEqual(\_PR.CLVL,1),LLessEqual(\_PR.CLVL,3))){ // copy PL0 values + Store (\_SB.PCI0.B0D4.CPNU(\_PR.PL20,1),Local0) // PL2 minimum power + Store (\_SB.PCI0.B0D4.MIN4(\_PR.PL10),Local1) // PL1 minimum power + } + } + case(1){ + If(LOr(LEqual(\_PR.CLVL,2),LEqual(\_PR.CLVL,3))){ // copy PL1 values + Store (\_SB.PCI0.B0D4.CPNU(\_PR.PL21,1),Local0) // PL2 minimum power + Store (\_SB.PCI0.B0D4.MIN4(\_PR.PL11),Local1) // PL1 minimum power + } + } + case(2){ + If(LEqual(\_PR.CLVL,3)){ // copy PL2 values + Store (\_SB.PCI0.B0D4.CPNU(\_PR.PL22,1),Local0) // PL2 minimum power + Store (\_SB.PCI0.B0D4.MIN4(\_PR.PL12),Local1) // PL1 minimum power + } + } + } + } + + // get the iMax value from the PCCC object and copy it to a local variable + Store (DerefOf(Index(DerefOf(Index(\_SB.PCI0.B0D4.PCCX,1)),0)),Local2) // CurrentLimitMinimum + + // update the first three packages with the values that we had to dynamically determine + // this section might have to be updated any time the PDRT is changed + Store(Local0,Index(DeRefOf(Index (DeRefOf (Index (TMPD, 0)),3)),1)) // Package domain, PL2, target power from CPU PPM + Store(Local1,Index(DeRefOf(Index (DeRefOf (Index (TMPD, 1)),3)),1)) // Package domain, PL1, target power from CPU PPM + Store(Local2,Index(DeRefOf(Index (DeRefOf (Index (TMPD, 3)),3)),1)) // Imax Controls - 30A + + Return(TMPD) + } // Method(PDDC) + + Method(PDAC,,,,PkgObj) + { + Name(TMPD,Package() + { + Package() {100, \_SB.PCI0.B0D4, 0x09, Package () {0x00010001,0x80000000}}, // Package domain, PL2, target power from CPU PPM + Package() {100, \_SB.PCI0.B0D4, 0x09, Package () {0x00010000,0x80000000}}, // Package domain, PL1, target power from CPU PPM + Package() {100, \_SB.PCI0.B0D4, 0x09, Package () {0x00070000,0}}, // Package domain, Power Control Turbo Enable + Package() {100, \_SB.PCI0.B0D4, 0x09, Package () {0x00030000,0x80000000}}, // Imax Controls - 30A + Package() {100, \_SB.PCI0.B0D4, 0x00, Package () {0x00040000,0x80000000}}, // Core control - cores from TCNT + Package() {100, \_SB.PCI0.DPLY, 0x0A, Package () {0x00050000,100}}, // Display brightness - 100% + Package() {100, \_SB.PCI0.TMEM, 0x02, Package () {0x00010000,5000}}, // Memory domain, PL1, target power from TMEM.PPCC + Package() {100, \_SB.PCI0.B0D4, 0x00, Package () {0x00020000,100}} // System Agent Thermal Device, target frequency - P State 0% + }) + + If(CondRefOf(\_PR.CBMI)){ + Switch(ToInteger(\_PR.CBMI)){ // use the boot index from PPM to choose the Power Limit values and copy them to local variables + case(0){ + If(LAnd(LGreaterEqual(\_PR.CLVL,1),LLessEqual(\_PR.CLVL,3))){ // copy PL0 values + Store (\_SB.PCI0.B0D4.CPNU(\_PR.PL20,1),Local0) // PL2 maximum power + Store (\_SB.PCI0.B0D4.CPNU(\_PR.PL10,1),Local1) // PL1 maximum power + } + } + case(1){ + If(LOr(LEqual(\_PR.CLVL,2),LEqual(\_PR.CLVL,3))){ // copy PL1 values + Store (\_SB.PCI0.B0D4.CPNU(\_PR.PL21,1),Local0) // PL2 maximum power + Store (\_SB.PCI0.B0D4.CPNU(\_PR.PL11,1),Local1) // PL1 maximum power + } + } + case(2){ + If(LEqual(\_PR.CLVL,3)){ // copy PL2 values + Store (\_SB.PCI0.B0D4.CPNU(\_PR.PL22,1),Local0) // PL2 maximum power + Store (\_SB.PCI0.B0D4.CPNU(\_PR.PL12,1),Local1) // PL1 maximum power + } + } + } + } + + // get the iMax value from the PCCC object and copy it to a local variable + Store (DerefOf(Index(DerefOf(Index(\_SB.PCI0.B0D4.PCCX,1)),1)),Local2) // CurrentLimitMaximum + + // update the first four packages with the values that we had to dynamically determine + // this section might have to be updated any time the PDRT is changed + Store(Local0,Index(DeRefOf(Index (DeRefOf (Index (TMPD, 0)),3)),1)) // Package domain, PL2, target power from CPU PPM + Store(Local1,Index(DeRefOf(Index (DeRefOf (Index (TMPD, 1)),3)),1)) // Package domain, PL1, target power from CPU PPM + Store(Local2,Index(DeRefOf(Index (DeRefOf (Index (TMPD, 3)),3)),1)) // Imax Controls - 30A + Store(TCNT,Index(DeRefOf(Index (DeRefOf (Index (TMPD, 4)),3)),1)) // Core control - cores from TCNT + + Return(TMPD) + } // Method(PDAC) + + } // End IETM Device +} // End \_SB Scope + +// +// EC support code +// +Scope(\_SB.PCI0.LPCB.H_EC) // Open scope to Embedded Controller +{ + // + // Create a Mutex for PATx methods to prevent Sx resume race condition problems asscociated with EC commands. + // + Mutex(PATM, 0) + + // _QF1 (Query - Embedded Controller Query F1) + // + // Handler for EC generated SCI number F1. + // + // Arguments: (0) + // None + // Return Value: + // None + // + Method(_QF1) + { // Thermal sensor threshold crossing event handler + P8XH(0, 0xf1) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.TSSR)), Local0) + While(Local0) // Ensure that events occuring during execution + { // of this handler are not dropped + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.TSSR)) // clear all status bits + If(And(Local0, 0x10, Local1)) + { // Memory temp threshold crossed + Notify(\_SB.PCI0.TMEM, 0x90) + } + If(And(Local0, 0x8, Local1)) + { // Ambient temp threshold crossed + Notify(\_SB.PCI0.LPCB.H_EC.TAMB, 0x90) + } + If(And(Local0, 0x4, Local1)) + { // Skin temp threshold crossed + Notify(\_SB.PCI0.LPCB.H_EC.TSKN, 0x90) + } + If(And(Local0, 0x2, Local1)) + { // Fan temp threshold crossed + Notify(\_SB.PCI0.LPCB.H_EC.TEFN, 0x90) + } + If(And(Local0, 0x01, Local1)) + { // VR temp threshold crossed + Notify(\_SB.PCI0.LPCB.H_EC.T_VR, 0x90) + } + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.TSSR)), Local0) + } + } +} // End \_SB.PCI0.LPCB.H_EC Scope + +// +// Processor files. +// + Include("B0d4Participant.asl") + Include("B0d4DppmPolicy.asl") + Include("B0d4CtdpPolicy.asl") + Include("B0d4LpmPolicy.asl") + +// +// CPU files +// + Include("TcpuParticipant.asl") + Include("TcpuDppmPolicy.asl") + +// +// PCH files +// + Include("TpchParticipant.asl") + Include("TpchDppmPolicy.asl") + +// +// These participants, TAMB, TEFN, TFN1, TFN2, TMEM, TSKN, T_VR, are currently used by DPPM policies only. +// Refer to the specific technology BIOS specification. +// + Include("TAmbParticipant.asl") + Include("TAmbDppmPolicy.asl") + Include("TEfnParticipant.asl") + Include("TEfnDppmPolicy.asl") + Include("TFN1Participant.asl") + Include("TFN2Participant.asl") + Include("TMemParticipant.asl") + Include("TMemDppmPolicy.asl") + Include("TSknParticipant.asl") + Include("TSknDppmPolicy.asl") + Include("T_VRParticipant.asl") + Include("T_VRDppmPolicy.asl") + Include("DplyParticipant.asl") + Include("TPwrParticipant.asl") + Include("WWANParticipant.asl") + Include("WWANDppmPolicy.asl") + +// +// DPPM support files +// + Include("Ertm.asl") + Include("Trt.asl") + Include("Art.asl") + Include("Dppm.asl") + + +} // End SSDT diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/DptfAcpiTables.cif b/ReferenceCode/AcpiTables/Dptf/AcpiTables/DptfAcpiTables.cif new file mode 100644 index 0000000..a374599 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/DptfAcpiTables.cif @@ -0,0 +1,41 @@ +<component> + name = "DptfAcpiTables" + category = ModulePart + LocalRoot = "ReferenceCode\AcpiTables\Dptf\AcpiTables\" + RefName = "DptfAcpiTables" +[files] +"DptfAcpiTables.sdl" +"DptfAcpiTables.mak" +"Art.asl" +"B0d4CtdpPolicy.asl" +"B0d4DppmPolicy.asl" +"B0d4LpmPolicy.asl" +"B0d4Participant.asl" +"Dppm.asl" +"Dptf.asl" +"DplyParticipant.asl" +"DptfAcpiTables.inf" +"Ertm.asl" +"T_VRDppmPolicy.asl" +"T_VRParticipant.asl" +"TAmbDppmPolicy.asl" +"TAmbParticipant.asl" +"TcpuDppmPolicy.asl" +"TcpuParticipant.asl" +"TEfnDppmPolicy.asl" +"TEfnParticipant.asl" +"TFN1Participant.asl" +"TFN2Participant.asl" +"TMemDppmPolicy.asl" +"TMemParticipant.asl" +"TpchDppmPolicy.asl" +"TpchParticipant.asl" +"Trt.asl" +"TSknDppmPolicy.asl" +"TSknParticipant.asl" +"TPwrParticipant.asl" +"WWANParticipant.asl" +"WWANDppmPolicy.asl" +[parts] +"DptfAcpiTablesFfrd" +<endComponent> diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/DptfAcpiTables.inf b/ReferenceCode/AcpiTables/Dptf/AcpiTables/DptfAcpiTables.inf new file mode 100644 index 0000000..dd03937 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/DptfAcpiTables.inf @@ -0,0 +1,67 @@ +## @file +# Component description file for the ACPI tables +# +#@copyright +# Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# + + +[defines] +BASE_NAME = DptfAcpiTables +# +# If the value of this GUID is changed then make sure to change the corresponding GUID (DPTF_ACPI_TABLE_STORAGE_GUID) +# in DptfAcpiTableStorage.h. +# +FILE_GUID = EA139578-FEA0-4dd2-91B5-6953819EF1E4 +COMPONENT_TYPE = ACPITABLE +FFS_EXT = .ffs + +[sources.common] + Dptf.ASL + +[libraries.common] + +[includes.common] + . + $(EFI_SOURCE) + $(EFI_SOURCE)/Include + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EFI_SOURCE)/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include + +# +# Edk II Glue Library, some header are not included by R9 header so have to include +# + $(EFI_SOURCE) + $(EFI_SOURCE)/Framework + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Library + +[nmake.common] diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/DptfAcpiTables.mak b/ReferenceCode/AcpiTables/Dptf/AcpiTables/DptfAcpiTables.mak new file mode 100644 index 0000000..f5dbc7e --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/DptfAcpiTables.mak @@ -0,0 +1,106 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2012, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#********************************************************************** +# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/DPTF/DptfAcpiTables/DptfAcpiTables.mak 5 6/02/13 8:18a Joshchou $ +# +# $Revision: 5 $ +# +# $Date: 6/02/13 8:18a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/DPTF/DptfAcpiTables/DptfAcpiTables.mak $ +# +# 5 6/02/13 8:18a Joshchou +# [TAG] None +# [Category] Improvement +# [Description] Change IASL compiler path to +# $(ACPIPLATFORM_ASL_COMPILER) in SharkBay project. +# +# 4 1/28/13 10:02p Joshchou +# [TAG] None +# [Category] Improvement +# [Description] Change the build tool path. +# +# 3 11/20/12 4:24a Joshchou +# [TAG] None +# [Category] Improvement +# [Description] Create Token for OEM clone +# +# 2 9/26/12 1:58a Victortu +# +# 1 4/24/12 9:25a Victortu +# Intel DPTF initialization. +# +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: DptfAcpiTables.mak +# +# Description: MAke file to build Intel DPTF ACPI ASL components +# +#<AMI_FHDR_END> +#********************************************************************** +#----------------------------------------------------------------------- +# ASL compiler definition +#----------------------------------------------------------------------- +!IF "$(ACPIPLATFORM_ASL_COMPILER)"=="" +!ERROR It is an invalid path, please check your ASL compiler path. +!ENDIF + +IASL = $(ACPIPLATFORM_ASL_COMPILER) +#----------------------------------------------------------------------- +EDK : DPTFACPI + +ALLDPTFSEC = $(BUILD_DIR)\Dptf.sec + +DPTFACPI : $(BUILD_DIR)\DptfAcpiTables.ffs + +$(BUILD_DIR)\Dptf.aml : $(INTEL_DPTF_ASL_FILE) + $(ASLEXPANDER) $(INTEL_DPTF_ASL_FILE) $(BUILD_DIR)\Dptf.asl $(PROJECT_CPU_ROOT)\Include + $(IASL) -p $(BUILD_DIR)\Dptf.aml $(BUILD_DIR)\Dptf.asl + +$(BUILD_DIR)\Dptf.sec: $(BUILD_DIR)\Dptf.aml + $(GENSECTION) -I $** -O $@ -S EFI_SECTION_RAW + +$(BUILD_DIR)\DptfAcpiTables.ffs: $(ALLDPTFSEC) $(INTEL_DPTF_ACPI_TABLE_DIR)\DptfAcpiTables.mak + $(GENFFSFILE) -B $(BUILD_DIR) -V -o $@ -P1 <<$(BUILD_DIR)\DptfAcpiTables.pkg +PACKAGE.INF +[.] +BASE_NAME = DptfAcpiTables +FFS_FILEGUID = EA139578-FEA0-4dd2-91B5-6953819EF1E4 +FFS_FILETYPE = EFI_FV_FILETYPE_FREEFORM +FFS_ATTRIB_CHECKSUM = TRUE + +IMAGE_SCRIPT = +{ + Compress (dummy) { + $(PROJECT_DIR)\$(BUILD_DIR)\Dptf.sec + } +} +<<KEEP +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2012, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/DptfAcpiTables.sdl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/DptfAcpiTables.sdl new file mode 100644 index 0000000..50d6780 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/DptfAcpiTables.sdl @@ -0,0 +1,31 @@ +TOKEN + Name = DptfAcpiTables_SUPPORT + Value = 1 + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable DptfAcpiTables support in Project" +End + +MODULE + Help = "Includes DptfAcpiTables.mak to Project" + File = "DptfAcpiTables.mak" +End + +PATH + Name = "INTEL_DPTF_ACPI_TABLE_DIR" +End + +TOKEN + Name = "INTEL_DPTF_ASL_FILE" + Value = "$(INTEL_DPTF_ACPI_TABLE_DIR)\Dptf.asl" + TokenType = Expression + TargetMAK = Yes +End + +ELINK + Name = "$(BUILD_DIR)\DptfAcpiTables.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ertm.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ertm.asl new file mode 100644 index 0000000..a2f0a50 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ertm.asl @@ -0,0 +1,55 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + Ertm.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.IETM) +{ + // ETRM (Intel DPTF Participant List) + // + // The ETRM object evaluates to a package of packages each of which describes one participant device. + // + Name(ETRM, Package() + { // TODO: Replace with system-specific ETRM data here + Package() {\_SB.TCPU, "INT3401", 0x06, "0"}, // Processor Device + Package() {\_SB.PCI0.TMEM, "INT3402", 0x06, "0"}, // Memory Device + Package() {\_SB.PCI0.LPCB.H_EC.TSKN, "INT3403", 0x06, "0"}, // Skin Temperature Sensor + Package() {\_SB.PCI0.LPCB.H_EC.TAMB, "INT3403", 0x06, "1"}, // Ambient Temperature Sensor + Package() {\_SB.PCI0.LPCB.H_EC.T_VR, "INT3403", 0x06, "2"}, // VR Temperature Sensor + Package() {\_SB.PCI0.LPCB.H_EC.TEFN, "INT3403", 0x06, "3"}, // Exhaust Fan Temperature Sensor + Package() {\_SB.PCI0.WWAN, "INT3408", 0x06, "1"}, // Wireless WWAN temperature sensor Device + Package() {\_SB.PCI0.LPCB.H_EC.TFN1, "INT3404", 0x06, "0"}, // Fan Control Device + Package() {\_SB.PCI0.LPCB.H_EC.TFN2, "INT3404", 0x06, "1"}, // Fan Control Device + Package() {\_SB.PCI0.DPLY, "INT3406", 0x06, "0"}, // Display Participant Device + Package() {\_SB.PCI0.B0D4, "8086_0C03", 0x00, "0x00040000"}, // HSW SA Thermal Device + Package() {\_SB.PCI0.TPCH, "8086_8C24", 0x00, "0x001F0006"}, // LPT PCH Thermal Device + Package() {\_SB.PCI0.B0D4, "8086_0A03", 0x00, "0x00040000"}, // HSW ULT SA Thermal Device + Package() {\_SB.PCI0.TPCH, "8086_9C24", 0x00, "0x001F0006"}, // LPT ULT PCH Thermal Device + Package() {\_SB.PCI0.B0D4, "8086_0D03", 0x00, "0x00040000"} // CRW SA Thermal Device + }) +} diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/Art.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/Art.asl new file mode 100644 index 0000000..54c7fa0 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/Art.asl @@ -0,0 +1,81 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + Art.asl + +Abstract: + + Intel ACPI Reference Code for Intel Dynamic Power Performance Management + +--*/ + + Scope(\_SB.IETM) + { + + Name(ART1, Package() // ART package when in Quiet Mode / Passive Cooling Mode + { + 0, // Revision + // Source Target Weight, AC0MaxLevel, AC1MaxLevel, AC21MaxLevel, AC31MaxLevel, AC41MaxLevel, AC51MaxLevel, AC61MaxLevel, AC71MaxLevel, AC81MaxLevel, AC91MaxLevel + Package(){\_SB.PCI0.LPCB.H_EC.TFN1, \_SB.PCI0.LPCB.H_EC.TSKN, 100, 65, 50, 30, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN2, \_SB.PCI0.LPCB.H_EC.TSKN, 100, 65, 50, 30, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN1, \_SB.PCI0.B0D4, 100, 65, 50, 30, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN2, \_SB.PCI0.B0D4, 100, 65, 50, 30, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + }) + + Name(ART0, Package() // ART package when in Performance Mode / Active Cooling Mode + { + 0, // Revision + // Source Target Weight, AC0MaxLevel, AC1MaxLevel, AC21MaxLevel, AC31MaxLevel, AC41MaxLevel, AC51MaxLevel, AC61MaxLevel, AC71MaxLevel, AC81MaxLevel, AC91MaxLevel + Package(){\_SB.PCI0.LPCB.H_EC.TFN1, \_SB.PCI0.LPCB.H_EC.TSKN, 100, 65, 50, 30, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN2, \_SB.PCI0.LPCB.H_EC.TSKN, 100, 65, 50, 30, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN1, \_SB.PCI0.B0D4, 100, 65, 50, 30, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + Package(){\_SB.PCI0.LPCB.H_EC.TFN2, \_SB.PCI0.B0D4, 100, 65, 50, 30, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}, + }) + + // _ART (Active Cooling Relationship Table) + // + // Arguments: + // None + // Return Value: + // A variable-length Package containing a Revision ID and a list of Active Relationship Packages as described below: + // + // Return Value Information + // Package { + // Revision, // Integer - Current revision is: 0 + // ActiveRelationship[0] // Package + // ... + // ActiveRelationship[n] // Package + // } + // + Method(_ART,,,,PkgObj) + { // TODO: Add system-specific _ART code here + If(\ECON) + { + If(\_SB.PCI0.LPCB.H_EC.TSKN.CTYP) + { + Return(ART1) + } Else { + Return(ART0) + } + } + } // End _ART +} diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/B0d4DppmPolicy.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/B0d4DppmPolicy.asl new file mode 100644 index 0000000..d46e240 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/B0d4DppmPolicy.asl @@ -0,0 +1,192 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + B0d4DppmPolicy.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + + +Scope(\_SB.PCI0.B0D4) +{ + Name(CTYP,0) // Device-specific cooling policy preference + Name(AHYS,60) // Active Cooling Hysteresis configuration. Use this in conjuction with GTSH to define _ACx hysteresis points. (in 1/10 of K) + Name(AC1D,40) // _AC1 Delta from _AC0 (in 1/10 of K) + Name(AC2D,80) // _AC2 Delta from _AC0 (in 1/10 of K) + Name(GTSH, 0) // No HW Hysteresis for B0D4 + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC0) + { + Store(\_SB.IETM.CTOK(ATMC),Local1) + If(LGreaterEqual(LSTM,Local1)) + { + Subtract(AHYS, GTSH, Local2) + Subtract(Local1, Local2, Local3) // Include Hysteresis + Return(Local3) + } + Else + { + Return(Local1) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC1) + { + Store(\_SB.IETM.CTOK(ATMC),Local0) // Active Cooling Policy + Subtract(Local0, AC1D, Local1) + If(LGreaterEqual(LSTM,Local1)) + { + Subtract(AHYS, GTSH, Local2) + Subtract(Local1, Local2, Local3) // Include Hysteresis + Return(Local3) + } + Else + { + Return(Local1) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC2) + { + Store(\_SB.IETM.CTOK(ATMC),Local0) // Active Cooling Policy + Subtract(Local0, AC2D, Local1) + If(LGreaterEqual(LSTM,Local1)) + { + Subtract(AHYS, GTSH, Local2) + Subtract(Local1, Local2, Local3) // Include Hysteresis + Return(Local3) + } + Else + { + Return(Local1) + } + } + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT,0,Serialized) + { + Return(\_SB.IETM.CTOK(SACR)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + Return(\_SB.IETM.CTOK(SAHT)) + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV,0,Serialized) + { + Return(\_SB.IETM.CTOK(PTMC)) + } + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP,3,Serialized) + { + If(LOr(LEqual(Arg0,0),LEqual(Arg0,1))) + { + Store(Arg0, CTYP) + P8XH(0, Arg1) + P8XH(1, Arg2) + Notify(B0D4, 0x91) + } + } + +} // End Scope(\_SB.PCI0.B0D4) + diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/DptfAcpiTablesFfrd.cif b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/DptfAcpiTablesFfrd.cif new file mode 100644 index 0000000..9d67abb --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/DptfAcpiTablesFfrd.cif @@ -0,0 +1,25 @@ +<component> + name = "DptfAcpiTablesFfrd" + category = ModulePart + LocalRoot = "ReferenceCode\AcpiTables\Dptf\AcpiTables\Ffrd\" + RefName = "DptfAcpiTablesFfrd" +[files] +"DptfAcpiTablesFfrd.sdl" +"DptfAcpiTablesFfrd.mak" +"DptfAcpiTablesFfrd.inf" +"B0d4DppmPolicy.asl" +"Art.asl" +"DptfFfrd.asl" +"Ertm.asl" +"TAmbParticipant.asl" +"TEfnParticipant.asl" +"TFN1Participant.asl" +"TFN2Participant.asl" +"TMemDppmPolicy.asl" +"TInlDppmPolicy.asl" +"TInlParticipant.asl" +"TMemParticipant.asl" +"Trt.asl" +"TSknParticipant.asl" +"TSknDppmPolicy.asl" +<endComponent> diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/DptfAcpiTablesFfrd.inf b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/DptfAcpiTablesFfrd.inf new file mode 100644 index 0000000..6a73ca0 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/DptfAcpiTablesFfrd.inf @@ -0,0 +1,68 @@ +## @file +# Component description file for the ACPI tables +# +#@copyright +# Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# + + +[defines] +BASE_NAME = DptfAcpiTablesFfrd +# +# If the value of this GUID is changed then make sure to change the corresponding GUID (DPTF_ACPI_TABLE_STORAGE_GUID) +# in DptfAcpiTableStorage.h. +# +FILE_GUID = 2820908B-87F6-446b-A100-74EEE36E2918 +COMPONENT_TYPE = ACPITABLE +FFS_EXT = .ffs + +[sources.common] + DptfFfrd.ASL + +[libraries.common] + +[includes.common] + . + .. + $(EFI_SOURCE) + $(EFI_SOURCE)/Include + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EFI_SOURCE)/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include + +# +# Edk II Glue Library, some header are not included by R9 header so have to include +# + $(EFI_SOURCE) + $(EFI_SOURCE)/Framework + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Library + +[nmake.common] diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/DptfAcpiTablesFfrd.mak b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/DptfAcpiTablesFfrd.mak new file mode 100644 index 0000000..7fa30fa --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/DptfAcpiTablesFfrd.mak @@ -0,0 +1,81 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: DptfAcpiTablesFfrd.mak +# +# Description: MAke file to build Aptio ACPI ASL components +# +# +#<AMI_FHDR_END> +#************************************************************************* +all : BuildDptfAcpiTablesFfrd + +BuildDptfAcpiTablesFfrd : $(BUILD_DIR)\DptfAcpiTablesFfrd.ffs + +#----------------------------------------------------------------------- +# ASL compiler definition +#----------------------------------------------------------------------- +!IF "$(ACPIPLATFORM_ASL_COMPILER)"=="" +!ERROR It is an invalid path, please check your ASL compiler path. +!ENDIF + +IASL = $(ACPIPLATFORM_ASL_COMPILER) +#----------------------------------------------------------------------- + +$(BUILD_DIR)\DptfAcpiTablesFfrd.aml : $(INTEL_DptfAcpiTablesFfrd_DIR)\DptfFfrd.asl + $(ASLEXPANDER) $(INTEL_DptfAcpiTablesFfrd_DIR)\DptfFfrd.asl $(BUILD_DIR)\DptfFfrd.asl $(PROJECT_CPU_ROOT)\Include + $(IASL) -p $(BUILD_DIR)\DptfAcpiTablesFfrd.aml $(BUILD_DIR)\DptfFfrd.asl + +$(BUILD_DIR)\DptfAcpiTablesFfrd.sec: $(BUILD_DIR)\DptfAcpiTablesFfrd.aml + $(GENSECTION) -I $*.aml -O $@ -S EFI_SECTION_RAW + +#Note. Expand the package with DptfAcpiTablesFfrd tables. +# DXE phase will load the tables +# and update Aml contents if provided in Acpiplatform.c + +$(BUILD_DIR)\DptfAcpiTablesFfrd.ffs: $(BUILD_DIR)\DptfAcpiTablesFfrd.sec + $(GENFFSFILE) -B $(BUILD_DIR) -V -o $@ -P1 <<$(BUILD_DIR)\DptfAcpiTablesFfrd.pkg + +PACKAGE.INF +[.] +BASE_NAME = DptfAcpiTablesFfrd +FFS_FILEGUID = 2820908B-87F6-446b-A100-74EEE36E2918 +FFS_FILETYPE = EFI_FV_FILETYPE_FREEFORM +FFS_ATTRIB_CHECKSUM = TRUE + +IMAGE_SCRIPT = +{ + Compress (dummy) { + $(PROJECT_DIR)\$(BUILD_DIR)\DptfAcpiTablesFfrd.sec + } +} +<<KEEP + + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/DptfAcpiTablesFfrd.sdl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/DptfAcpiTablesFfrd.sdl new file mode 100644 index 0000000..5285e7e --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/DptfAcpiTablesFfrd.sdl @@ -0,0 +1,25 @@ +TOKEN + Name = "DptfAcpiTablesFfrd_SUPPORT" + Value = "1" + Help = "Main switch to enable DptfAcpiTablesFfrd support in Project" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Master = Yes +End + +PATH + Name = "INTEL_DptfAcpiTablesFfrd_DIR" +End + +MODULE + Help = "Includes DptfAcpiTablesFfrd.mak to Project" + File = "DptfAcpiTablesFfrd.mak" +End + +ELINK + Name = "$(BUILD_DIR)\DptfAcpiTablesFfrd.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent + Token = "DptfAcpiTablesFfrd_SUPPORT" "=" "1" +End diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/DptfFfrd.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/DptfFfrd.asl new file mode 100644 index 0000000..0afa8d7 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/DptfFfrd.asl @@ -0,0 +1,874 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + DptfFfrd.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +#include "PowerMgmtDefinitions.h" + +DefinitionBlock ( + "DptfFfrd.aml", + "SSDT", + 1, + "DptfFf", + "DptfFfrd", + 0x1000 + ) +{ + + +External(P8XH, MethodObj) +External(ECON, IntObj) +External(TSOD, IntObj) +External(PNHM, IntObj) +External(TCNT, IntObj) +External(\MPLT, IntObj) +External(\PWRS, Intobj) +External(LPMV, IntObj) +External(CRTT, IntObj) +External(ATMC, IntObj) +External(PTMC, IntObj) +External(ATRA, IntObj) +External(PTRA, IntObj) +External(ACTT, IntObj) +External(PSVT, IntObj) +External(ATPC, IntObj) +External(PTPC, IntObj) + +External(DPTF, IntObj) // EnableDptf +External(SADE, IntObj) // EnableSaDevice +External(SACR, IntObj) // CriticalThermalTripPointSa +External(SAHT, IntObj) // HotThermalTripPointSa + +External(PCHD, IntObj) // EnablePchDevice +External(PCHC, IntObj) // CriticalThermalTripPointPch +External(PCHH, IntObj) // HotThermalTripPointPch + +External(MEMD, IntObj) // EnableMemoryDevice +External(MEMC, IntObj) // CriticalThermalTripPointTMEM +External(MEMH, IntObj) // HotThermalTripPointTMEM + +External(FND1, IntObj) // EnableFan1Device +External(FND2, IntObj) // EnableFan2Device + +External(AMBD, IntObj) // EnableAmbientDevice +External(AMAT, IntObj) // ActiveThermalTripPointAmbient +External(AMPT, IntObj) // PassiveThermalTripPointAmbient +External(AMCT, IntObj) // CriticalThermalTripPointAmbient +External(AMHT, IntObj) // HotThermalTripPointAmbient + +External(SKDE, IntObj) // EnableSkinDevice +External(SKAT, IntObj) // ActiveThermalTripPointSkin +External(SKPT, IntObj) // PassiveThermalTripPointSkin +External(SKCT, IntObj) // CriticalThermalTripPointSkin +External(SKHT, IntObj) // HotThermalTripPointSkin + +External(EFDE, IntObj) // EnableExhaustFanDevice +External(EFAT, IntObj) // ActiveThermalTripPointExhaustFan +External(EFPT, IntObj) // PassiveThermalTripPointExhaustFan +External(EFCT, IntObj) // CriticalThermalTripPointExhaustFan +External(EFHT, IntObj) // HotThermalTripPointExhaustFan + +External(VRDE, IntObj) // EnableVRDevice +External(VRAT, IntObj) // ActiveThermalTripPointVR +External(VRPT, IntObj) // PassiveThermalTripPointVR +External(VRCT, IntObj) // CriticalThermalTripPointVR +External(VRHT, IntObj) // HotThermalTripPointVR + +External(WIFD, IntObj) // EnableWifiDevice +External(WFAT, IntObj) // ActiveThermalTripPointWifi +External(WFPT, IntObj) // PassiveThermalTripPointWifi +External(WFCT, IntObj) // CriticalThermalTripPointWifi +External(WFHT, IntObj) // ActiveHotThermalTripPointWifi + +External(WAND, IntObj) // EnableWWANDevice +External(WWAT, IntObj) // ActiveThermalTripPointWWAN +External(WWPT, IntObj) // PassiveThermalTripPointWWAN +External(WWCT, IntObj) // CriticalThermalTripPointWWAN +External(WWHT, IntObj) // ActiveHotThermalTripPointWWAN + +External(CTDP, IntObj) // EnableCtdpPolicy +External(LPMP, IntObj) // EnableLpmPolicy +External(DPAP, IntObj) // EnableActivePolicy +External(DPPP, IntObj) // EnablePassivePolicy +External(DPCP, IntObj) // EnableCriticalPolicy +External(DCMP, IntObj) // EnableCoolingModePolicy +External(ECEU, IntObj) // EnableCurrentExecutionUnit +External(TGFG, IntObj) // TargetGfxFreq +External(TRTV, IntObj) // TrtRevision +External(PWRE, IntObj) // EnablePowerDevice +External(PWRP, IntObj) // EnablePowerPolicy + +External(LPOE, IntObj) // LPOEnable +External(LPOP, IntObj) // LPOStartPState +External(LPOS, IntObj) // LPOStepSize +External(LPOW, IntObj) // LPOPowerControlSetting +External(LPER, IntObj) // LPOPerformanceControlSetting + +External(PPSZ, IntObj) // PPCC Step Size +External(\PDC0, IntObj) // CPU0 _PDC Flags + +External(WWSD,IntObj) // EnableWwanTempSensorDevice +External(CVSD,IntObj) // EnableCpuVrTempSensorDevice +External(SSDD,IntObj) // EnableSsdTempSensorDevice +External(INLD,IntObj) // EnableInletFanTempSensorDevice +External(IFAT,IntObj) // ActiveThermalTripPointInletFan +External(IFPT,IntObj) // PassiveThermalTripPointInletFan +External(IFCT,IntObj) // CriticalThermalTripPointInletFan +External(IFHT,IntObj) // HotThermalTripPointInletFan + +External(\_TZ.ETMD, IntObj) +External(\_TZ.TZ00, ThermalZoneObj) +External(\_TZ.FAN0, DeviceObj) +External(\_TZ.FAN0._FST, PkgObj) + +External(\_SB.PCI0, DeviceObj) +External(\_SB.PCI0.B0D4, DeviceObj) +External(\_SB.PCI0.MHBR, FieldUnitObj) + +External(\_SB.PCI0.LPCB.H_EC, DeviceObj) +External(\_SB.PCI0.LPCB.H_EC.ECAV, IntObj) +External(\_SB.PCI0.LPCB.H_EC.ECMD, MethodObj) +External(\_SB.PCI0.LPCB.H_EC.ECRD, MethodObj) // EC Read Method +External(\_SB.PCI0.LPCB.H_EC.ECWT, MethodObj) // EC Write Method +External(\_SB.PCI0.LPCB.H_EC.ECF2, OpRegionObj) +External(\_SB.PCI0.LPCB.H_EC.SKNT, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.CVRT, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.FANT, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.AMBT, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.PPSL, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.PPSH, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.PINV, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.PENV, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.PSTP, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.CMDR, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.TSD0, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.TSD1, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.DIM0, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.DIM1, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.CFSP, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.CFS2, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.CPUP, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.CPAP, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.PMAX, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.PECH, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.CFAN, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.TSI, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.HYST, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.TSHT, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.TSLT, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.TSSR, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.B1RC, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.B1FC, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.BAT1._BST, MethodObj) +External(\_SB.PCI0.LPCB.H_EC.B1ML, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.B1MH, FieldUnitObj) +External(\_SB.PCI0.LPCB.H_EC.PPWR, FieldUnitObj) + +External(\_PR.CPU0, ProcessorObj) +External(\_PR.CPU0._PSS, MethodObj) +External(\_PR.CPU0._PPC, IntObj) +External(\_PR.CPU0._TSS, MethodObj) +External(\_PR.CFGD, FieldUnitObj) +External(\_PR.CPU0.TSMF, PkgObj) +External(\_PR.CPU0.TSMC, PkgObj) +External(\_PR.CPU0._PTC, MethodObj) +External(\_PR.CPU0._TSD, MethodObj) +External(\_PR.CPU0._TPC, IntObj) +External(\_PR.CPU1, ProcessorObj) +External(\_PR.CPU2, ProcessorObj) +External(\_PR.CPU3, ProcessorObj) +External(\_PR.CPU4, ProcessorObj) +External(\_PR.CPU5, ProcessorObj) +External(\_PR.CPU6, ProcessorObj) +External(\_PR.CPU7, ProcessorObj) + +External(\_PR.CLVL, FieldUnitObj) +External(\_PR.CBMI, FieldUnitObj) +External(\_PR.PL10, FieldUnitObj) +External(\_PR.PL20, FieldUnitObj) +External(\_PR.PLW0, FieldUnitObj) +External(\_PR.CTC0, FieldUnitObj) +External(\_PR.TAR0, FieldUnitObj) +External(\_PR.PL11, FieldUnitObj) +External(\_PR.PL21, FieldUnitObj) +External(\_PR.PLW1, FieldUnitObj) +External(\_PR.CTC1, FieldUnitObj) +External(\_PR.TAR1, FieldUnitObj) +External(\_PR.PL12, FieldUnitObj) +External(\_PR.PL22, FieldUnitObj) +External(\_PR.PLW2, FieldUnitObj) +External(\_PR.CTC2, FieldUnitObj) +External(\_PR.TAR2, FieldUnitObj) + +External(\_PR.APSV, FieldUnitObj) +External(\_PR.AAC0, FieldUnitObj) +External(\_PR.ACRT, FieldUnitObj) + +External(\_SB.PCCD.PENB, IntObj) + +// Display participant externals +External(DISE, IntObj) // EnableDisplayParticipant +External(\_SB.PCI0.GFX0.DD1F._BCL, MethodObj) +External(\_SB.PCI0.GFX0.DD1F._BCM, MethodObj) +External(\_SB.PCI0.GFX0.DD1F._BQC, MethodObj) +External(\_SB.PCI0.GFX0.DD1F._DCS, MethodObj) + +Scope(\_SB) +{ + // + // DPTF Thermal Zone Device + // + // + Device(IETM) + { + // + // Intel DPTF Thermal Framework Device + // + Name(_HID, EISAID("INT3400")) + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(DPTF,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + // + // Note: there are seven GUID packages in TMPP and up to seven matching store statements in IDSP. + // The store statements must never exceed the number of package elements to prevent an overrun. + // + Name(TMPP,Package() + { + ToUUID("00000000-0000-0000-0000-000000000000"), + ToUUID("00000000-0000-0000-0000-000000000000"), + ToUUID("00000000-0000-0000-0000-000000000000"), + ToUUID("00000000-0000-0000-0000-000000000000"), + ToUUID("00000000-0000-0000-0000-000000000000"), + ToUUID("00000000-0000-0000-0000-000000000000"), + ToUUID("00000000-0000-0000-0000-000000000000") + }) + + // + // Save original trip points so _OSC method can enable/disable Legacy thermal policies by manipulating trip points. + // + Name (PTRP,0) // Passive trip point + Name (PSEM,0) // Passive semaphore + Name (ATRP,0) // Active trip point + Name (ASEM,0) // Active semaphore + Name (YTRP,0) // Critical trip point + Name (YSEM,0) // Critical semaphore + + // IDSP (Intel DPTF Supported Policies) + // + // This object evaluates to a package of packages, with each package containing the UUID + // values to represent a policy implemented and supported by the Intel DPTF software stack. + // + // Arguments: (0) + // None + // Return Value: + // Package of Guid packages + // + Method(IDSP,0,Serialized,,PkgObj) + { + Name(TMPI,0) + + // Passive Policy GUID + If(LAnd(LEqual(DPPP,1),CondRefOf(DPSP))){ + Store(DeRefOf(Index(DPSP,0)), Index(TMPP,TMPI)) + Increment(TMPI) + } + + // Active Policy GUID + If(LAnd(LEqual(DPAP,1),CondRefOf(DASP))){ + Store(DeRefOf(Index(DASP,0)), Index(TMPP,TMPI)) + Increment(TMPI) + } + + // Critical Policy GUID + If(LAnd(LEqual(DPCP,1),CondRefOf(DCSP))){ + Store(DeRefOf(Index(DCSP,0)), Index(TMPP,TMPI)) + Increment(TMPI) + } + + // Cooling Mode Policy GUID + If(LAnd(LEqual(DCMP,1),CondRefOf(DMSP))){ + Store(DeRefOf(Index(DMSP,0)), Index(TMPP,TMPI)) + Increment(TMPI) + } + + // LPM policy GUID + If(LAnd(LEqual(LPMP,1),CondRefOf(LPSP))){ + Store(DeRefOf(Index(LPSP,0)), Index(TMPP,TMPI)) + Increment(TMPI) + } + + // CTDP Policy GUID + If(LAnd(LEqual(CTDP,1),CondRefOf(CTSP))){ + Store(DeRefOf(Index(CTSP,0)), Index(TMPP,TMPI)) + Increment(TMPI) + } + + //Power Policy GUID + If(LAnd(LEqual(PWRP,1),CondRefOf(WPSP))){ + Store(DeRefOf(Index(WPSP,0)), Index(TMPP,TMPI)) + } + + Return(TMPP) + } + + // _OSC (Operating System Capabilities) + // + // This object is evaluated by each DPTF policy implementation to communicate to the platform of the existence and/or control transfer. + // + // Arguments: (4) + // Arg0 - A Buffer containing a UUID + // Arg1 - An Integer containing a Revision ID of the buffer format + // Arg2 - An Integer containing a count of entries in Arg3 + // Arg3 - A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing a list of capabilities + // + Method(_OSC, 4,Serialized,,BuffObj,{BuffObj,IntObj,IntObj,BuffObj}) + { + Name(NUMP,0) + Name (UID2,ToUUID("FFFFFFFF-FFFF-FFFF-FFFF-FFFFFFFFFFFF")) + + // Point to Status DWORD in the Arg3 buffer (STATUS) + CreateDWordField(Arg3, 0, STS1) + + // Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES) + CreateDWordField(Arg3, 4, CAP1) + + // + // _OSC needs to validate the UUID and Revision. + // + // IF Unrecognized UUID + // Return Unrecognized UUID _OSC Failure + // IF Unsupported Revision + // Return Unsupported Revision _OSC Failure + // + // STS0[0] = Reserved + // STS0[1] = _OSC Failure + // STS0[2] = Unrecognized UUID + // STS0[3] = Unsupported Revision + // STS0[4] = Capabilities masked + // + // Get the platform UUID's that are available, this will be a package of packages. + // + IDSP() // initialize TMPP with GUID's + Store(SizeOf(TMPP),NUMP) // how many GUID's in the package? + + // Note: The comparison method used is necessary due to + // limitations of certain OSes which cannot perform direct + // buffer comparisons. + // + // Create a set of "Input" UUID fields. + // + CreateDWordField(Arg0, 0x0, IID0) + CreateDWordField(Arg0, 0x4, IID1) + CreateDWordField(Arg0, 0x8, IID2) + CreateDWordField(Arg0, 0xC, IID3) + // + // Create a set of "Expected" UUID fields. + // + CreateDWordField(UID2, 0x0, EID0) + CreateDWordField(UID2, 0x4, EID1) + CreateDWordField(UID2, 0x8, EID2) + CreateDWordField(UID2, 0xC, EID3) + // + // Compare the input UUID to the list of UUID's in the system. + // + While(NUMP){ + // + // copy one uuid from TMPP to UID2 + // + Store(DeRefOf (Index (TMPP, Subtract(NUMP,1))),UID2) + // + // Verify the input UUID matches the expected UUID. + // + If(LAnd(LAnd(LEqual(IID0, EID0), LEqual(IID1, EID1)), LAnd(LEqual(IID2, EID2), LEqual(IID3, EID3)))){ + Break // break out of while loop when matching UUID is found + } + Decrement(NUMP) + } + + If(LEqual(NUMP,0)){ + // + // Return Unrecognized UUID _OSC Failure + // + And(STS1,0xFFFFFF00,STS1) + Or(STS1,0x6,STS1) + Return(Arg3) + } + + If(LNot(LEqual(Arg1, 1))) + { + // + // Return Unsupported Revision _OSC Failure + // + And(STS1,0xFFFFFF00,STS1) + Or(STS1,0xA,STS1) + Return(Arg3) + } + + If(LNot(LEqual(Arg2, 2))) + { + // + // Return Argument 3 Buffer Count not sufficient + // + And(STS1,0xFFFFFF00,STS1) + Or(STS1,0x2,STS1) + Return(Arg3) + } + + // + // Passive Policy GUID + // + If(LAnd(LEqual(DPPP,1),CondRefOf(\_PR.APSV))){ + If(LEqual(PSEM,0)){ + Store(1,PSEM) + Store(\_PR.APSV,PTRP) // use semaphore so variable is only initialized once + } + // + // copy the GUID to UID2 + // + If(CondRefOf(DPSP)){ + Store(DeRefOf (Index (DPSP, 0)),UID2) + } + // + // Verify the test UUID matches the input UUID. + // + If(LAnd(LAnd(LEqual(IID0, EID0), LEqual(IID1, EID1)), LAnd(LEqual(IID2, EID2), LEqual(IID3, EID3)))){ + // do passive notify + If(Not(And(STS1, 0x01))) // Test Query Flag + { // Not a query operation, so process the request + If(And(CAP1, 0x01)) + { // Enable DPTF + // Nullify the legacy thermal zone. + Store(110,\_PR.APSV) + } Else { // Passive unloading, re-enable legacy thermal zone + Store(PTRP,\_PR.APSV) + } + // Send notification to legacy thermal zone for legacy policy to be enabled/disabled + Notify(\_TZ.TZ00, 0x80) + } + Return(Arg3) + } + } + + // + // Active Policy GUID + // + If(LAnd(LEqual(DPAP,1),CondRefOf(\_PR.AAC0))){ + If(LEqual(ASEM,0)){ + Store(1,ASEM) + Store(\_PR.AAC0,ATRP) // use semaphore so variable is only initialized once + } + // + // copy the GUID to UID2 + // + If(CondRefOf(DASP)){ + Store(DeRefOf (Index (DASP, 0)),UID2) + } + // + // Verify the test UUID matches the input UUID. + // + If(LAnd(LAnd(LEqual(IID0, EID0), LEqual(IID1, EID1)), LAnd(LEqual(IID2, EID2), LEqual(IID3, EID3)))){ + // do active notify + If(Not(And(STS1, 0x01))) // Test Query Flag + { // Not a query operation, so process the request + If(And(CAP1, 0x01)) + { // Enable DPTF + // Nullify the legacy thermal zone. + Store(110,\_PR.AAC0) + Store(0, \_TZ.ETMD) // Legacy Active TM Management relies on this variable. + } Else { // Passive unloading, re-enable legacy thermal zone + Store(ATRP,\_PR.AAC0) + Store(1, \_TZ.ETMD) + } + // Send notification to legacy thermal zone for legacy policy to be enabled/disabled + Notify(\_TZ.TZ00, 0x80) + } + Return(Arg3) + } + } + + // + // Critical Policy GUID + // + If(LAnd(LEqual(DPCP,1),CondRefOf(\_PR.ACRT))){ + If(LEqual(YSEM,0)){ + Store(1,YSEM) + Store(\_PR.ACRT,YTRP) // use semaphore so variable is only initialized once + } + // + // copy the GUID to UID2 + // + If(CondRefOf(DCSP)){ + Store(DeRefOf (Index (DCSP, 0)),UID2) + } + // + // Verify the test UUID matches the input UUID. + // + If(LAnd(LAnd(LEqual(IID0, EID0), LEqual(IID1, EID1)), LAnd(LEqual(IID2, EID2), LEqual(IID3, EID3)))){ + // do critical notify + If(Not(And(STS1, 0x01))) // Test Query Flag + { // Not a query operation, so process the request + If(And(CAP1, 0x01)) + { // Enable DPTF + // Nullify the legacy thermal zone. + Store(210,\_PR.ACRT) + } Else { // Passive unloading, re-enable legacy thermal zone + Store(YTRP,\_PR.ACRT) + } + // Send notification to legacy thermal zone for legacy policy to be enabled/disabled + Notify(\_TZ.TZ00, 0x80) + } + Return(Arg3) + } + } + + Return(Arg3) + } + // KTOC (Kelvin to Celsius) + // + // This control method converts from 10ths of degree Kelvin to Celsius. + // + // Arguments: (1) + // Arg0 - Temperature in 10ths of degree Kelvin + // Return Value: + // Temperature in Celsius + // + Method(KTOC,1) + { + Subtract(Arg0, 2732, Local1) + If(LGreater(Local1,0)) // make sure we don't have a negative number + { + Return(Divide(Local1, 10)) + } + Else + { + Return(0) + } + } + + // CTOK (Celsius to Kelvin) + // + // This control method converts from Celsius to 10ths of degree Kelvin. + // + // Arguments: (1) + // Arg0 - Temperature in Celsius + // Return Value: + // Temperature in 10ths of degree Kelvin + // + Method(CTOK, 1) + { + If(And(Arg0, 0x1000)) // Round negative values up to Zero + { + Return(2372) + } + Multiply(Arg0,10,Local0) + And(Local0, 0x0FFF, Local1) + Add(Local1, 2732, Local2) + Return(Local2) + } + + // PDRT (power device relation table) + // + // This object evaluates to a package of packages that indicates the relation between charge rates and target devices. + // + // Arguments: (0) + // None + // Return Value: + // A variable-length package of packages as described below. + // + // Return Value Information + // Package { + // Package [0] // Package + // .... + // Package [n] // Package + // } + // + // Each sub-Package contains the elements described below: + // Package { + // ChargeRate // Integer (DWORD) + // TargetDevice // Integer (DWORD) + // PTYP // Integer (DWORD) + // ControlBuffer // Package + // } + // + Method(PDRT,,,,PkgObj) + { + \_SB.PCI0.B0D4.PCCC() // init global variable PCCX + If (\PWRS){ // check power source + PDAC() // AC table + } Else { + PDDC() // DC table + } + } // end Method(PDRT) + + Method(PDDC,,,,PkgObj) + { + Name(TMPD,Package() + { + Package() {80, \_SB.PCI0.B0D4, 0x09, Package () {0x00010001,0x80000000}}, // Package domain, PL2, target power from CPU PPM + Package() {60, \_SB.PCI0.B0D4, 0x09, Package () {0x00010000,0x80000000}}, // Package domain, PL1, target power from CPU PPM + Package() {55, \_SB.PCI0.B0D4, 0x09, Package () {0x00070000,1}}, // Package domain, Power Control Turbo Disable + Package() {50, \_SB.PCI0.B0D4, 0x09, Package () {0x00030000,0x80000000}}, // Imax Controls - 30A + Package() {50, \_SB.PCI0.B0D4, 0x00, Package () {0x00040000,2}}, // Core control - 2 cores + Package() {40, \_SB.PCI0.DPLY, 0x0A, Package () {0x00050000,60}}, // Display brightness - 60 + Package() {40, \_SB.PCI0.TMEM, 0x02, Package () {0x00010000,1000}}, // Memory domain, PL1, target power from TMEM.PPCC + Package() {30, \_SB.PCI0.B0D4, 0x00, Package () {0x00020000,80}}, // System Agent Thermal Device, target frequency - P State 80% + Package() {20, \_SB.PCI0.B0D4, 0x00, Package () {0x00020001,50}} // System Agent Thermal Device, target frequency - T State 50% + }) + + If(CondRefOf(\_PR.CBMI)){ + Switch(ToInteger(\_PR.CBMI)){ // use the boot index from PPM to choose the Power Limit values and copy them to local variables + case(0){ + If(LAnd(LGreaterEqual(\_PR.CLVL,1),LLessEqual(\_PR.CLVL,3))){ // copy PL0 values + Store (\_SB.PCI0.B0D4.CPNU(\_PR.PL20,1),Local0) // PL2 minimum power + Store (\_SB.PCI0.B0D4.MIN4(\_PR.PL10),Local1) // PL1 minimum power + } + } + case(1){ + If(LOr(LEqual(\_PR.CLVL,2),LEqual(\_PR.CLVL,3))){ // copy PL1 values + Store (\_SB.PCI0.B0D4.CPNU(\_PR.PL21,1),Local0) // PL2 minimum power + Store (\_SB.PCI0.B0D4.MIN4(\_PR.PL11),Local1) // PL1 minimum power + } + } + case(2){ + If(LEqual(\_PR.CLVL,3)){ // copy PL2 values + Store (\_SB.PCI0.B0D4.CPNU(\_PR.PL22,1),Local0) // PL2 minimum power + Store (\_SB.PCI0.B0D4.MIN4(\_PR.PL12),Local1) // PL1 minimum power + } + } + } + } + + // get the iMax value from the PCCC object and copy it to a local variable + Store (DerefOf(Index(DerefOf(Index(\_SB.PCI0.B0D4.PCCX,1)),0)),Local2) // CurrentLimitMinimum + + // update the first three packages with the values that we had to dynamically determine + // this section might have to be updated any time the PDRT is changed + Store(Local0,Index(DeRefOf(Index (DeRefOf (Index (TMPD, 0)),3)),1)) // Package domain, PL2, target power from CPU PPM + Store(Local1,Index(DeRefOf(Index (DeRefOf (Index (TMPD, 1)),3)),1)) // Package domain, PL1, target power from CPU PPM + Store(Local2,Index(DeRefOf(Index (DeRefOf (Index (TMPD, 3)),3)),1)) // Imax Controls - 30A + + Return(TMPD) + } // Method(PDDC) + + Method(PDAC,,,,PkgObj) + { + Name(TMPD,Package() + { + Package() {100, \_SB.PCI0.B0D4, 0x09, Package () {0x00010001,0x80000000}}, // Package domain, PL2, target power from CPU PPM + Package() {100, \_SB.PCI0.B0D4, 0x09, Package () {0x00010000,0x80000000}}, // Package domain, PL1, target power from CPU PPM + Package() {100, \_SB.PCI0.B0D4, 0x09, Package () {0x00070000,0}}, // Package domain, Power Control Turbo Enable + Package() {100, \_SB.PCI0.B0D4, 0x09, Package () {0x00030000,0x80000000}}, // Imax Controls - 30A + Package() {100, \_SB.PCI0.B0D4, 0x00, Package () {0x00040000,0x80000000}}, // Core control - cores from TCNT + Package() {100, \_SB.PCI0.DPLY, 0x0A, Package () {0x00050000,100}}, // Display brightness - 100% + Package() {100, \_SB.PCI0.TMEM, 0x02, Package () {0x00010000,5000}}, // Memory domain, PL1, target power from TMEM.PPCC + Package() {100, \_SB.PCI0.B0D4, 0x00, Package () {0x00020000,100}} // System Agent Thermal Device, target frequency - P State 0% + }) + + If(CondRefOf(\_PR.CBMI)){ + Switch(ToInteger(\_PR.CBMI)){ // use the boot index from PPM to choose the Power Limit values and copy them to local variables + case(0){ + If(LAnd(LGreaterEqual(\_PR.CLVL,1),LLessEqual(\_PR.CLVL,3))){ // copy PL0 values + Store (\_SB.PCI0.B0D4.CPNU(\_PR.PL20,1),Local0) // PL2 maximum power + Store (\_SB.PCI0.B0D4.CPNU(\_PR.PL10,1),Local1) // PL1 maximum power + } + } + case(1){ + If(LOr(LEqual(\_PR.CLVL,2),LEqual(\_PR.CLVL,3))){ // copy PL1 values + Store (\_SB.PCI0.B0D4.CPNU(\_PR.PL21,1),Local0) // PL2 maximum power + Store (\_SB.PCI0.B0D4.CPNU(\_PR.PL11,1),Local1) // PL1 maximum power + } + } + case(2){ + If(LEqual(\_PR.CLVL,3)){ // copy PL2 values + Store (\_SB.PCI0.B0D4.CPNU(\_PR.PL22,1),Local0) // PL2 maximum power + Store (\_SB.PCI0.B0D4.CPNU(\_PR.PL12,1),Local1) // PL1 maximum power + } + } + } + } + + // get the iMax value from the PCCC object and copy it to a local variable + Store (DerefOf(Index(DerefOf(Index(\_SB.PCI0.B0D4.PCCX,1)),1)),Local2) // CurrentLimitMaximum + + // update the first four packages with the values that we had to dynamically determine + // this section might have to be updated any time the PDRT is changed + Store(Local0,Index(DeRefOf(Index (DeRefOf (Index (TMPD, 0)),3)),1)) // Package domain, PL2, target power from CPU PPM + Store(Local1,Index(DeRefOf(Index (DeRefOf (Index (TMPD, 1)),3)),1)) // Package domain, PL1, target power from CPU PPM + Store(Local2,Index(DeRefOf(Index (DeRefOf (Index (TMPD, 3)),3)),1)) // Imax Controls - 30A + Store(TCNT,Index(DeRefOf(Index (DeRefOf (Index (TMPD, 4)),3)),1)) // Core control - cores from TCNT + + Return(TMPD) + } // Method(PDAC) + + } // End IETM Device +} // End \_SB Scope + +// +// EC support code +// +Scope(\_SB.PCI0.LPCB.H_EC) // Open scope to Embedded Controller +{ + // + // Create a Mutex for PATx methods to prevent Sx resume race condition problems asscociated with EC commands. + // + Mutex(PATM, 0) + + // _QF1 (Query - Embedded Controller Query F1) + // + // Handler for EC generated SCI number F1. + // + // Arguments: (0) + // None + // Return Value: + // None + // + Method(_QF1) + { // Thermal sensor threshold crossing event handler + P8XH(0, 0xf1) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.TSSR)), Local0) + While(Local0) // Ensure that events occuring during execution + { // of this handler are not dropped + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.TSSR)) // clear all status bits + If(And(Local0, 0x20, Local1)) + { // BIT5: Board Fan Inlet Temperature Sensor Threshold Crossed + Notify(\_SB.PCI0.LPCB.H_EC.TINL, 0x90) + } + If(And(Local0, 0x10, Local1)) + { // BIT4: Memory Temperature Sensor Threshold Crossed + Notify(\_SB.PCI0.TMEM, 0x90) + } + If(And(Local0, 0x8, Local1)) + { // BIT3: WWAN Board Temperature Sensor Threshold Crossed + Notify(\_SB.PCI0.LPCB.H_EC.TAMB, 0x90) + } + If(And(Local0, 0x4, Local1)) + { // BIT2: CPU VR Board Temperature Sensor Threshold Crossed + Notify(\_SB.PCI0.LPCB.H_EC.TSKN, 0x90) + } + If(And(Local0, 0x2, Local1)) + { // BIT1: SSD Board Temperature Sensor Threshold Crossed. + Notify(\_SB.PCI0.LPCB.H_EC.TEFN, 0x90) + } + // BIT0: Not used on Harris Beach. + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.TSSR)), Local0) + } + } +} // End \_SB.PCI0.LPCB.H_EC Scope + +// +// Processor files. +// +// AMI MODIFY BEGIN + //Include("B0d4Participant.asl") + Include("B0d4DppmPolicy.asl") + //Include("B0d4CtdpPolicy.asl") + //Include("B0d4LpmPolicy.asl") + #Include "../B0d4Participant.asl" + #Include "../B0d4CtdpPolicy.asl" + #Include "../B0d4LpmPolicy.asl" +// AMI MODIFY END + +// +// PCH files +// +// AMI MODIFY BEGIN + //Include("TpchParticipant.asl") + //Include("TpchDppmPolicy.asl") + #Include "../TpchParticipant.asl" + #Include "../TpchDppmPolicy.asl" +// AMI MODIFY END + +// +// These participants are used by DPPM policies. +// + Include("TAmbParticipant.asl") + // AMI MODIFY BEGIN + //Include("TAmbDppmPolicy.asl") + #Include "../TAmbDppmPolicy.asl" + // AMI MODIFY END + Include("TEfnParticipant.asl") + // AMI MODIFY BEGIN + //Include("TEfnDppmPolicy.asl") + #Include "../TEfnDppmPolicy.asl" + // AMI MODIFY END + Include("TFN1Participant.asl") + Include("TFN2Participant.asl") + Include("TMemParticipant.asl") + Include("TMemDppmPolicy.asl") + Include("TSknParticipant.asl") + Include("TSknDppmPolicy.asl") + // AMI MODIFY BEGIN + //Include("DplyParticipant.asl") + //Include("TPwrParticipant.asl") + #Include "../DplyParticipant.asl" + #Include "../TPwrParticipant.asl" + // AMI MODIFY END + Include("TInlParticipant.asl") + Include("TInlDppmPolicy.asl") + // AMI MODIFY BEGIN + //Include("WWANParticipant.asl") + //Include("WWANDppmPolicy.asl") + #Include "../WWANParticipant.asl" + #Include "../WWANDppmPolicy.asl" + // AMI MODIFY END +// +// DPPM support files +// + Include("Ertm.asl") + Include("Trt.asl") + Include("Art.asl") + // AMI MODIFY BEGIN + //Include("Dppm.asl") + #Include "../Dppm.asl" + // AMI MODIFY END + +} // End SSDT diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/Ertm.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/Ertm.asl new file mode 100644 index 0000000..d92ce41 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/Ertm.asl @@ -0,0 +1,53 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + Ertm.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.IETM) +{ + // ETRM (Intel DPTF Participant List) + // + // The ETRM object evaluates to a package of packages each of which describes one participant device. + // + Name(ETRM, Package() + { // TODO: Replace with system-specific ETRM data here + Package() {\_SB.PCI0.TMEM, "INT3402", 0x06, "0"}, // Memory Device + Package() {\_SB.PCI0.LPCB.H_EC.TSKN, "INT3403", 0x06, "0"}, // CPU VR Temperature Sensor + Package() {\_SB.PCI0.LPCB.H_EC.TAMB, "INT3403", 0x06, "1"}, // WWAN Temperature Sensor + Package() {\_SB.PCI0.LPCB.H_EC.TEFN, "INT3403", 0x06, "3"}, // SSD Board Temperature Sensor + Package() {\_SB.PCI0.LPCB.H_EC.TINL, "INT3403", 0x06, "5"}, // Board Fan Inlet Temperature Sensor + Package() {\_SB.PCI0.LPCB.H_EC.TPWR, "INT3407", 0x06, "0"}, // Platform Power Device + Package() {\_SB.PCI0.LPCB.H_EC.TFN1, "INT3404", 0x06, "0"}, // Fan Control Device + Package() {\_SB.PCI0.LPCB.H_EC.TFN2, "INT3404", 0x06, "1"}, // Fan Control Device + Package() {\_SB.PCI0.DPLY, "INT3406", 0x06, "0"}, // Display Participant Device + Package() {\_SB.PCI0.B0D4, "8086_0A03", 0x00, "0x00040000"}, // HSW ULT SA Thermal Device + Package() {\_SB.PCI0.TPCH, "8086_9C24", 0x00, "0x001F0006"}, // LPT ULT PCH Thermal Device + Package() {\_SB.PCI0.B0D4, "8086_0D03", 0x00, "0x00040000"} // CRW SA Thermal Device + }) +} + diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TAmbParticipant.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TAmbParticipant.asl new file mode 100644 index 0000000..c9bb332 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TAmbParticipant.asl @@ -0,0 +1,184 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TambParticipant.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.LPCB.H_EC) +{ + + Device(TAMB) // Ambient temperature sensor + { + Name(_HID, EISAID("INT3403")) // Intel DPTF Temperature Sensor Device + Name(_UID, 1) + + Name(HITP, 0x64) + Name(AAUX, 0x10) + Name(_STR, Unicode ("WWAN Board Temperature Sensor")) + Name(PTYP, 0x03) + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(WWSD,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + // _TMP (Temperature) + // + // This control method returns the thermal zone's current operating temperature. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin) + // + Method(_TMP,0,Serialized) + { + If(\ECON) + { + // Get the Ambient Temperature. + Return(\_SB.IETM.CTOK(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.AMBT)))) + } Else { + Return(3000) + } + } + + // Returns Number of Aux Trips available + Name(PATC, 2) + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT0, 1, Serialized) + { + If (\ECON) + { + Store (Acquire(\_SB.PCI0.LPCB.H_EC.PATM, 100),Local0) // save Acquire result so we can check for Mutex acquired + If (LEqual(Local0, Zero)) // check for Mutex acquired + { + Store(\_SB.IETM.KTOC(Arg0),AAUX) + \_SB.PCI0.LPCB.H_EC.ECWT(0x3, RefOf(\_SB.PCI0.LPCB.H_EC.TSI)) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.HYST)) + \_SB.PCI0.LPCB.H_EC.ECWT(AAUX, RefOf(\_SB.PCI0.LPCB.H_EC.TSLT)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x4A) //Set Trip point. + Release(\_SB.PCI0.LPCB.H_EC.PATM) + } + } + } + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT1, 1, Serialized) + { + If (\ECON) + { + Store (Acquire(\_SB.PCI0.LPCB.H_EC.PATM, 100),Local0) // save Acquire result so we can check for Mutex acquired + If (LEqual(Local0, Zero)) // check for Mutex acquired + { + Store(\_SB.IETM.KTOC(Arg0),HITP) + \_SB.PCI0.LPCB.H_EC.ECWT(0x3, RefOf(\_SB.PCI0.LPCB.H_EC.TSI)) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.HYST)) + \_SB.PCI0.LPCB.H_EC.ECWT(HITP, RefOf(\_SB.PCI0.LPCB.H_EC.TSHT)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x4A) //Set Trip point. + Release(\_SB.PCI0.LPCB.H_EC.PATM) + } + } + } + + // Thermal Sensor Hysteresis, 2 degrees + Name(GTSH, 20) + + Name(LSTM,0) // Last temperature reported + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(TAMB, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius, this could be a platform policy with setup item + } + + } // End TAMB Device +}// end Scope(\_SB.PCI0.LPCB.H_EC) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TEfnParticipant.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TEfnParticipant.asl new file mode 100644 index 0000000..2907303 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TEfnParticipant.asl @@ -0,0 +1,184 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TEFNParticipant.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.LPCB.H_EC) +{ + + Device(TEFN) + { + Name(_HID, EISAID("INT3403")) // Intel DPTF Temperature Sensor Device + Name(_UID, 3) + + Name(HITP, 0x64) + Name(EAUX, 0x10) + Name(_STR, Unicode ("SSD Board Temperature Sensor")) + Name(PTYP, 0x03) + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(SSDD,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + // _TMP (Temperature) + // + // This control method returns the thermal zone's current operating temperature. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin) + // + Method(_TMP, 0, Serialized) + { + If(\ECON) + { + // Get the Exhaust Fan Temperature. + Return(\_SB.IETM.CTOK(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.FANT)))) + } Else { + Return(3000) + } + } + + // Number of Aux Trips available + Name(PATC, 2) + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT0, 1, Serialized) + { + If (\ECON) + { + Store (Acquire(\_SB.PCI0.LPCB.H_EC.PATM, 100),Local0) // save Acquire result so we can check for Mutex acquired + If (LEqual(Local0, Zero)) // check for Mutex acquired + { + Store(\_SB.IETM.KTOC(Arg0),EAUX) + \_SB.PCI0.LPCB.H_EC.ECWT(0x1, RefOf(\_SB.PCI0.LPCB.H_EC.TSI)) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.HYST)) + \_SB.PCI0.LPCB.H_EC.ECWT(EAUX, RefOf(\_SB.PCI0.LPCB.H_EC.TSLT)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x4A) //Set Trip point. + Release(\_SB.PCI0.LPCB.H_EC.PATM) + } + } + } + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT1, 1, Serialized) + { + If (\ECON) + { + Store (Acquire(\_SB.PCI0.LPCB.H_EC.PATM, 100),Local0) // save Acquire result so we can check for Mutex acquired + If (LEqual(Local0, Zero)) // check for Mutex acquired + { + Store(\_SB.IETM.KTOC(Arg0),HITP) + \_SB.PCI0.LPCB.H_EC.ECWT(0x1, RefOf(\_SB.PCI0.LPCB.H_EC.TSI)) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.HYST)) + \_SB.PCI0.LPCB.H_EC.ECWT(HITP, RefOf(\_SB.PCI0.LPCB.H_EC.TSHT)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x4A) //Set Trip point. + Release(\_SB.PCI0.LPCB.H_EC.PATM) + } + } + } + + // Thermal Sensor Hysteresis, 2 degrees + Name(GTSH, 20) + + Name(LSTM,0) // Last temperature reported + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(TEFN, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius, this could be a platform policy with setup item + } + + } // End TEFN Device +}// end Scope(\_SB.PCI0.LPCB.H_EC) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TFN1Participant.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TFN1Participant.asl new file mode 100644 index 0000000..b76893e --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TFN1Participant.asl @@ -0,0 +1,172 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TFN1Participant.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.LPCB.H_EC) +{ + + Device(TFN1) + { + Name(_HID, EISAID("INT3404")) // Intel DPTF Fan Device + Name(_UID, 0) + Name(_STR, Unicode ("CPU Fan #1")) + + Name(FON, 1) // Indicates if Fan is ON Currently + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(FND1,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + // _FIF (Fan Information) + // + // The optional _FIF object provides OSPM with fan device capability information. + // + // Arguments: (0) + // None + // Return Value: + // A Package containing the fan device parameters. + // + Method(_FIF) + { + Return (Package (){ + 0, // Revision:Integer + 1, // FineGrainControl:Integer Boolean + 2, // StepSize:Integer DWORD + 0 // LowSpeedNotificationSupport:Integer Boolean + }) + } + + // _FPS (Fan Performance States) + // + // Evaluates to a variable-length package containing a list of packages that describe the fan device's performance states. + // + // Arguments: (0) + // None + // Return Value: + // A variable-length Package containing a Revision ID and a list of Packages that describe the fan device's performance states. + // + Method(_FPS,,,,PkgObj) + { + Return (Package() + { + 0, // Revision:Integer + // Control, TripPoint, Speed, NoiseLevel, Power + Package(){100, 0xFFFFFFFF, 7000, 500, 5000}, + Package(){ 95, 0xFFFFFFFF, 6650, 475, 4750}, + Package(){ 90, 0xFFFFFFFF, 6300, 450, 4500}, + Package(){ 85, 0xFFFFFFFF, 5950, 425, 4250}, + Package(){ 80, 0xFFFFFFFF, 5600, 400, 4000}, + Package(){ 75, 0xFFFFFFFF, 5250, 375, 3750}, + Package(){ 70, 0xFFFFFFFF, 4900, 350, 3500}, + Package(){ 60, 0xFFFFFFFF, 4200, 300, 3000}, + Package(){ 50, 0xFFFFFFFF, 3500, 250, 2500}, + Package(){ 40, 0xFFFFFFFF, 2800, 200, 2000}, + Package(){ 25, 0xFFFFFFFF, 1750, 125, 1250}, + Package(){ 0, 0xFFFFFFFF, 0, 0, 0} // OFF + }) + } + + // _FSL (Fan Set Level) + // + // The optional _FSL object is a control method that OSPM evaluates to set a fan device's speed (performance state) to a specific level. + // + // Arguments: (1) + // Arg0 - Level (Integer): conveys to the platform the fan speed level to be set. + // Return Value: + // None + // + // Argument Information + // Arg0: Level. If the fan supports fine-grained control, Level is a percentage of maximum level (0-100) + // that the platform is to engage the fan. If the fan does not support fine-grained control, + // Level is a Control field value from a package in the _FPS object's package list. + // A Level value of zero causes the platform to turn off the fan. + // + Method(_FSL,1,Serialized) + { + If(\ECON) + { + \_SB.PCI0.LPCB.H_EC.ECWT(1, RefOf(\_SB.PCI0.LPCB.H_EC.PPSL)) + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PPSH)) + \_SB.PCI0.LPCB.H_EC.ECWT(ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PENV)), RefOf(\_SB.PCI0.LPCB.H_EC.PINV)) + \_SB.PCI0.LPCB.H_EC.ECWT(Arg0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) + \_SB.PCI0.LPCB.H_EC.ECWT(100, RefOf(\_SB.PCI0.LPCB.H_EC.PSTP)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) // Command to turn the fan on + Notify(\_SB.IETM, 0x83) // Notify DPTF TZ that fan speed has changed + + // Notify OSPM on Fan Speed Changes via DPTF + Store(Arg0, Index(\_TZ.FAN0._FST, 1)) + Notify(\_TZ.FAN0, 0x80) + } + } + + Name(TFST, Package() + { + 0, // Revision:Integer + 0xFFFFFFFF, // Control:Integer DWORD + 0xFFFFFFFF // Speed:Integer DWORD + }) + + //_FST (Fan Status) + // + // The optional _FST object provides status information for the fan device. + // + // Arguments: (0) + // None + // Return Value: + // A Package containing fan device status information + // + Method(_FST,,,,PkgObj) + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PENV)), Index(TFST, 1)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.CFSP)), Index(TFST, 2)) + Return(TFST) + } + + } // End TFN1 Device +}// end Scope(\_SB.PCI0.LPCB.H_EC) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TFN2Participant.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TFN2Participant.asl new file mode 100644 index 0000000..82a36d4 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TFN2Participant.asl @@ -0,0 +1,166 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TFN2Participant.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.LPCB.H_EC) +{ + + Device(TFN2) + { + Name(_HID, EISAID("INT3404")) // Intel DPTF Fan Device + Name(_UID, 1) + Name(_STR, Unicode ("CPU Fan #2")) + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(FND2,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + // _FIF (Fan Information) + // + // The optional _FIF object provides OSPM with fan device capability information. + // + // Arguments: (0) + // None + // Return Value: + // A Package containing the fan device parameters. + // + Method(_FIF) + { + Return (Package (){ + 0, // Revision:Integer + 1, // FineGrainControl:Integer Boolean + 2, // StepSize:Integer DWORD + 0 // LowSpeedNotificationSupport:Integer Boolean + }) + } + + // _FPS (Fan Performance States) + // + // Evaluates to a variable-length package containing a list of packages that describe the fan device's performance states. + // + // Arguments: (0) + // None + // Return Value: + // A variable-length Package containing a Revision ID and a list of Packages that describe the fan device's performance states. + // + Method(_FPS,,,,PkgObj) + { + Return (Package() + { + 0, // Revision:Integer + // Control, TripPoint, Speed, NoiseLevel, Power + Package(){100, 0xFFFFFFFF, 7000, 500, 5000}, + Package(){ 95, 0xFFFFFFFF, 6650, 475, 4750}, + Package(){ 90, 0xFFFFFFFF, 6300, 450, 4500}, + Package(){ 85, 0xFFFFFFFF, 5950, 425, 4250}, + Package(){ 80, 0xFFFFFFFF, 5600, 400, 4000}, + Package(){ 75, 0xFFFFFFFF, 5250, 375, 3750}, + Package(){ 70, 0xFFFFFFFF, 4900, 350, 3500}, + Package(){ 60, 0xFFFFFFFF, 4200, 300, 3000}, + Package(){ 50, 0xFFFFFFFF, 3500, 250, 2500}, + Package(){ 40, 0xFFFFFFFF, 2800, 200, 2000}, + Package(){ 25, 0xFFFFFFFF, 1750, 125, 1250}, + Package(){ 0, 0xFFFFFFFF, 0, 0, 0} // OFF + }) + } + + // _FSL (Fan Set Level) + // + // The optional _FSL object is a control method that OSPM evaluates to set a fan device's speed (performance state) to a specific level. + // + // Arguments: (1) + // Arg0 - Level (Integer): conveys to the platform the fan speed level to be set. + // Return Value: + // None + // + // Argument Information + // Arg0: Level. If the fan supports fine-grained control, Level is a percentage of maximum level (0-100) + // that the platform is to engage the fan. If the fan does not support fine-grained control, + // Level is a Control field value from a package in the _FPS object's package list. + // A Level value of zero causes the platform to turn off the fan. + // + Method(_FSL,1,Serialized) + { + If(\ECON) + { + \_SB.PCI0.LPCB.H_EC.ECWT(2, RefOf(\_SB.PCI0.LPCB.H_EC.PPSL)) + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PPSH)) + \_SB.PCI0.LPCB.H_EC.ECWT(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PENV)), RefOf(\_SB.PCI0.LPCB.H_EC.PINV)) + \_SB.PCI0.LPCB.H_EC.ECWT(Arg0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) + \_SB.PCI0.LPCB.H_EC.ECWT(100, RefOf(\_SB.PCI0.LPCB.H_EC.PSTP)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) // Command to turn the fan on + Notify(\_SB.IETM, 0x83) // Notify DPTF TZ that fan speed has changed + } + } + + Name(TFST, Package() + { + 0, // Revision:Integer + 0xFFFFFFFF, // Control:Integer DWORD + 0xFFFFFFFF // Speed:Integer DWORD + }) + + //_FST (Fan Status) + // + // The optional _FST object provides status information for the fan device. + // + // Arguments: (0) + // None + // Return Value: + // A Package containing fan device status information + // + Method(_FST,,,,PkgObj) + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PENV)), Index(TFST, 1)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.CFS2)), Index(TFST, 2)) + Return(TFST) + } + + } // End TFN2 Device +}// end Scope(\_SB.PCI0.LPCB.H_EC) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TInlDppmPolicy.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TInlDppmPolicy.asl new file mode 100644 index 0000000..b4d1db3 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TInlDppmPolicy.asl @@ -0,0 +1,140 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TInlDppmPolicy.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.LPCB.H_EC.TINL) +{ + Name(CTYP,0) // Device-specific cooling policy preference + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP, 3, Serialized) + { + If(LOr(LEqual(Arg0,0),LEqual(Arg0,1))) + { + Store(Arg0, CTYP) + P8XH(0, Arg1) + P8XH(1, Arg2) + Notify(\_SB.PCI0.LPCB.H_EC.TINL, 0x91) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC0) + { + If(CTYP) + { + Store(\_SB.IETM.CTOK(IFPT),Local1) // Passive Cooling Policy + } Else { + Store(\_SB.IETM.CTOK(IFAT),Local1) // Active Cooling Policy + } + If(LGreaterEqual(LSTM,Local1)) + { + Return(Subtract(Local1,20)) // subtract 2 degrees which is the Hysteresis + } + Else + { + Return(Local1) + } + } + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT, 0, Serialized) + { + Return(\_SB.IETM.CTOK(IFCT)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + Return(\_SB.IETM.CTOK(IFHT)) + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV, 0, Serialized) + { + If(CTYP) + { + Return(\_SB.IETM.CTOK(IFAT)) // Active Cooling Policy + } Else { + Return(\_SB.IETM.CTOK(IFPT)) // Passive Cooling Policy + } + } + +} // End Scope(\_SB.PCI0.LPCB.H_EC.TINL) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TInlParticipant.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TInlParticipant.asl new file mode 100644 index 0000000..45b85eb --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TInlParticipant.asl @@ -0,0 +1,186 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + InltParticipant.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.LPCB.H_EC) +{ + + Device(TINL) + { + Name(_HID, EISAID("INT3403")) // Intel DPTF Temperature Sensor Device + Name(_UID, 5) + + Name(HITP, 0x64) + Name(SAUX, 0x10) + Name(_STR, Unicode ("Board Fan Inlet Temperature Sensor")) + Name(PTYP, 0x03) + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(INLD,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + // _TMP (Temperature) + // + // This control method returns the thermal zone's current operating temperature. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin) + // + Method(_TMP) + { + If(\ECON) + { + Store(\_SB.PCI0.LPCB.H_EC.DIM1,Local1) // DIMM1 temperature + Return(\_SB.IETM.CTOK(Local1)) // EC reports in Celcius, convert to 10ths of degree Kelvin + } + Else + { + Return(3000) + } + } + + Name(PATC, 2) + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT0, 1, Serialized) + { + If (\ECON) + { + Store (Acquire(\_SB.PCI0.LPCB.H_EC.PATM, 100),Local0) // save Acquire result so we can check for Mutex acquired + If (LEqual(Local0, Zero)) // check for Mutex acquired + { + Store(\_SB.IETM.KTOC(Arg0),SAUX) + \_SB.PCI0.LPCB.H_EC.ECWT(0x5, RefOf(\_SB.PCI0.LPCB.H_EC.TSI)) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.HYST)) + \_SB.PCI0.LPCB.H_EC.ECWT(SAUX, RefOf(\_SB.PCI0.LPCB.H_EC.TSLT)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x4A) //Set Trip point. + Release(\_SB.PCI0.LPCB.H_EC.PATM) + } + } + } + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT1, 1, Serialized) + { + If (\ECON) + { + Store (Acquire(\_SB.PCI0.LPCB.H_EC.PATM, 100),Local0) // save Acquire result so we can check for Mutex acquired + If (LEqual(Local0, Zero)) // check for Mutex acquired + { + Store(\_SB.IETM.KTOC(Arg0),HITP) + \_SB.PCI0.LPCB.H_EC.ECWT(0x5, RefOf(\_SB.PCI0.LPCB.H_EC.TSI)) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.HYST)) + \_SB.PCI0.LPCB.H_EC.ECWT(HITP, RefOf(\_SB.PCI0.LPCB.H_EC.TSHT)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x4A) //Set Trip point. + Release(\_SB.PCI0.LPCB.H_EC.PATM) + } + } + } + + // Thermal Sensor Hysteresis, 2 degrees + Name(GTSH, 20) + + Name(LSTM,0) // Last temperature reported + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(TINL, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius, this could be a platform policy with setup item + } + + } // End TINL Device + +}// end Scope(\_SB.PCI0.LPCB.H_EC) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TMemDppmPolicy.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TMemDppmPolicy.asl new file mode 100644 index 0000000..440107c --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TMemDppmPolicy.asl @@ -0,0 +1,188 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TMemDppmPolicy.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.TMEM) +{ + Name(CTYP,0) // Device-specific cooling policy preference + Name(AHYS,50) // Active Cooling Hysteresis configuration. Use this in conjuction with GTSH to define _ACx hysteresis points. (in 1/10 of K) + Name(AC1D,30) // _AC1 Delta from _AC0 (in 1/10 of K) + Name(AC2D,60) // _AC2 Delta from _AC0 (in 1/10 of K) + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT) + { + Return(\_SB.IETM.CTOK(MEMC)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + Return(\_SB.IETM.CTOK(MEMH)) + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV) + { + Return(\_SB.IETM.CTOK(PTRA)) + } + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP, 3, Serialized) + { + If(LOr(LEqual(Arg0,0),LEqual(Arg0,1))) + { + Store(Arg0, CTYP) + P8XH(0, Arg1) + P8XH(1, Arg2) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC0) + { + Store(\_SB.IETM.CTOK(ATRA),Local1) + + If(LGreaterEqual(LSTM,Local1)) + { + Subtract(AHYS, GTSH, Local2) + Subtract(Local1, Local2, Local3) // Include Hysteresis + Return(Local3) + } + Else + { + Return(Local1) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC1) + { + Store(\_SB.IETM.CTOK(ATRA),Local0) // Active Cooling Policy + Subtract(Local0, AC1D, Local1) + If(LGreaterEqual(LSTM,Local1)) + { + Subtract(AHYS, GTSH, Local2) + Subtract(Local1, Local2, Local3) // Include Hysteresis + Return(Local3) + } + Else + { + Return(Local1) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC2) + { + Store(\_SB.IETM.CTOK(ATRA),Local0) // Active Cooling Policy + Subtract(Local0, AC2D, Local1) + If(LGreaterEqual(LSTM,Local1)) + { + Subtract(AHYS, GTSH, Local2) + Subtract(Local1, Local2, Local3) // Include Hysteresis + Return(Local3) + } + Else + { + Return(Local1) + } + } +} // End Scope(\_SB.PCI0.TMEM) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TMemParticipant.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TMemParticipant.asl new file mode 100644 index 0000000..7ed96cd --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TMemParticipant.asl @@ -0,0 +1,252 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TMemParticipant.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0) +{ + + Device(TMEM) + { + Name(_HID, EISAID("INT3402")) // Intel DPTF Memory Device + Name(_UID, 0) + + Name(HITP, 0x64) + Name(SAUX, 0x10) + Name(_STR, Unicode ("Memory Participant")) + Name(LSTM,0) // Last temperature reported + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(MEMD,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + // PPCC (Participant Power Control Capabilities) + // + // The PPCC object evaluates to a package of packages that indicates to DPTF processor + // participant the power control capabilities. + // + // Arguments: (0) + // None + // Return Value: + // PPCC package of packages + // + Method(PPCC,0,Serialized,,PkgObj) + { + Return(NPCC) + } + + Name (NPCC, Package() + { // Field Name : Field Type + 2, // Revision : DWordConst + + Package () // Power Limit 1 + { + 0, // PowerLimitIndex : DWordConst = 0 + 1000, // PowerLimitMinimum : DWordConst + 5000, // PowerLimitMaximum : DWordConst + 1, // TimeWindowMinimum : DWordConst + 28, // TimeWindowMaximum : DWordConst + 1000, // StepSize : DWordConst + }, + Package () // Power Limit 2 + { + 1, // PowerLimitIndex : DWordConst = 1 + 1000, // PowerLimitMinimum : DWordConst + 10000, // PowerLimitMaximum : DWordConst + 0, // TimeWindowMinimum : DWordConst + 0, // TimeWindowMaximum : DWordConst + 1000, // StepSize : DWordConst + } + }) // End of PPCC object + + // _TMP (Temperature) + // + // This control method returns the thermal zone's current operating temperature. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin) + // + Method(_TMP) + { + If(\ECON) + { + If(\TSOD) // if TS-on-DIMM sensor present and selected in BIOS SETUP return higher temp + { + If(LGreater(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.TSD0)),\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.TSD1)))) + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.TSD0)),Local1) // TS-on-DIMM0 temperature + } + Else + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.TSD1)),Local1) // TS-on-DIMM1 temperature + } + } + Else // else return higher On-Board DDR Thermal Sensor temp + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.DIM0)),Local1) // DIMM0 temperature + } + Return(\_SB.IETM.CTOK(Local1)) // EC reports in Celcius, convert to 10ths of degree Kelvin + } + Else + { + Return(3000) + } + } + + Name(PATC, 2) + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT0, 1, Serialized) + { + If (\ECON) + { + Store (Acquire(\_SB.PCI0.LPCB.H_EC.PATM, 100),Local0) // save Acquire result so we can check for Mutex acquired + If (LEqual(Local0, Zero)) // check for Mutex acquired + { + Store(\_SB.IETM.KTOC(Arg0),SAUX) + \_SB.PCI0.LPCB.H_EC.ECWT(0x4, RefOf(\_SB.PCI0.LPCB.H_EC.TSI)) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.HYST)) + \_SB.PCI0.LPCB.H_EC.ECWT(SAUX, RefOf(\_SB.PCI0.LPCB.H_EC.TSLT)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x4A) //Set Trip point. + Release(\_SB.PCI0.LPCB.H_EC.PATM) + } + } + } + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT1, 1, Serialized) + { + If (\ECON) + { + Store (Acquire(\_SB.PCI0.LPCB.H_EC.PATM, 100),Local0) // save Acquire result so we can check for Mutex acquired + If (LEqual(Local0, Zero)) // check for Mutex acquired + { + Store(\_SB.IETM.KTOC(Arg0),HITP) + \_SB.PCI0.LPCB.H_EC.ECWT(0x4, RefOf(\_SB.PCI0.LPCB.H_EC.TSI)) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.HYST)) + \_SB.PCI0.LPCB.H_EC.ECWT(HITP, RefOf(\_SB.PCI0.LPCB.H_EC.TSHT)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x4A) //Set Trip point. + Release(\_SB.PCI0.LPCB.H_EC.PATM) + } + } + } + + // Thermal Sensor Hysteresis, 2 degrees + Name(GTSH, 20) + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(TMEM, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius, this could be a platform policy with setup item + } + + // PGMB (Pci GMch Bar) + // + // This object is required to be implemented on platforms supporting Intel code name Sandy Bridge processor. + // This object is not required for platforms supporting Intel code name Ivy Bridge processor. + // + // Arguments: (0) + // None + // Return Value: + // Return MCH Bar value. + // + Method(PGMB, 0) + { + Return(\_SB.PCI0.MHBR) // Return MCH Bar value + } + + } // End TMEM Device + +}// end Scope(\_SB.PCI0) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TSknDppmPolicy.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TSknDppmPolicy.asl new file mode 100644 index 0000000..f1fccab --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TSknDppmPolicy.asl @@ -0,0 +1,190 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TSknDppmPolicy.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.LPCB.H_EC.TSKN) +{ + Name(CTYP,0) // Device-specific cooling policy preference + Name(AHYS,30) // Active Cooling Hysteresis configuration. Use this in conjuction with GTSH to define _ACx hysteresis points. (in 1/10 of K) + Name(AC1D,30) // _AC1 Delta from _AC0 (in 1/10 of K) + Name(AC2D,60) // _AC2 Delta from _AC0 (in 1/10 of K) + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP,3,Serialized) + { + If(LOr(LEqual(Arg0,0),LEqual(Arg0,1))) + { + Store(Arg0, CTYP) + P8XH(0, Arg1) + P8XH(1, Arg2) + Notify(\_SB.PCI0.LPCB.H_EC.TSKN, 0x91) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC0) + { + Store(\_SB.IETM.CTOK(SKAT),Local1) + + If(LGreaterEqual(LSTM,Local1)) + { + Subtract(AHYS, GTSH, Local2) + Subtract(Local1, Local2, Local3) // Include Hysteresis + Return(Local3) + } + Else + { + Return(Local1) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC1) + { + Store(\_SB.IETM.CTOK(SKAT),Local0) // Active Cooling Policy + Subtract(Local0, AC1D, Local1) + If(LGreaterEqual(LSTM,Local1)) + { + Subtract(AHYS, GTSH, Local2) + Subtract(Local1, Local2, Local3) // Include Hysteresis + Return(Local3) + } + Else + { + Return(Local1) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC2) + { + Store(\_SB.IETM.CTOK(SKAT),Local0) // Active Cooling Policy + Subtract(Local0, AC2D, Local1) + If(LGreaterEqual(LSTM,Local1)) + { + Subtract(AHYS, GTSH, Local2) + Subtract(Local1, Local2, Local3) // Include Hysteresis + Return(Local3) + } + Else + { + Return(Local1) + } + } + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT) + { + Return(\_SB.IETM.CTOK(SKCT)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + Return(\_SB.IETM.CTOK(SKHT) ) + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV) + { + Return(\_SB.IETM.CTOK(SKPT)) // Passive Cooling Policy + } + +} // End Scope(\_SB.PCI0.LPCB.H_EC.TSKN) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TSknParticipant.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TSknParticipant.asl new file mode 100644 index 0000000..b2c2859 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/TSknParticipant.asl @@ -0,0 +1,183 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TSknParticipant.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.LPCB.H_EC) +{ + + Device(TSKN) // Skin temperature sensor + { + Name(_HID, EISAID("INT3403")) // Intel DPTF Temperature Sensor Device + Name(_UID, 0) + + Name(HITP, 0x64) + Name(SAUX, 0x10) + Name(_STR, Unicode ("CPU VR Board Temperature Sensor")) + Name(PTYP, 0x03) + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(CVSD,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + // _TMP (Temperature) + // + // This control method returns the thermal zone's current operating temperature. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin) + // + Method(_TMP,0,Serialized) + { + If(\ECON) + { // Get the Skin Temperature. + Return(\_SB.IETM.CTOK(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.SKNT)))) + } Else { + Return(3000) + } + } + + // Number of Aux Trips available + Name(PATC, 2) + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT0, 1, Serialized) + { + If (\ECON) + { + Store (Acquire(\_SB.PCI0.LPCB.H_EC.PATM, 100),Local0) // save Acquire result so we can check for Mutex acquired + If (LEqual(Local0, Zero)) // check for Mutex acquired + { + Store(\_SB.IETM.KTOC(Arg0),SAUX) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.TSI)) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.HYST)) + \_SB.PCI0.LPCB.H_EC.ECWT(SAUX, RefOf(\_SB.PCI0.LPCB.H_EC.TSLT)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x4A) // Set Trip point + Release(\_SB.PCI0.LPCB.H_EC.PATM) + } + } + } + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT1, 1, Serialized) + { + If (\ECON) + { + Store (Acquire(\_SB.PCI0.LPCB.H_EC.PATM, 100),Local0) // save Acquire result so we can check for Mutex acquired + If (LEqual(Local0, Zero)) // check for Mutex acquired + { + Store(\_SB.IETM.KTOC(Arg0),HITP) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.TSI)) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.HYST)) + // Set High Trip to PSV or ACT + \_SB.PCI0.LPCB.H_EC.ECWT(HITP, RefOf(\_SB.PCI0.LPCB.H_EC.TSHT)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x4A) //Set Trip point. + Release(\_SB.PCI0.LPCB.H_EC.PATM) + } + } + } + + // Thermal Sensor Hysteresis, 2 degrees + Name(GTSH, 20) + + Name(LSTM,0) // Last temperature reported + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(TSKN, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius, this could be a platform policy with setup item + } + + } // End TSKN Device +}// end Scope(\_SB.PCI0.LPCB.H_EC) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/Trt.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/Trt.asl new file mode 100644 index 0000000..6dcd130 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Ffrd/Trt.asl @@ -0,0 +1,86 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + Trt.asl + +Abstract: + + Intel ACPI Reference Code for Intel Dynamic Power Performance Management + +--*/ + +Scope(\_SB.IETM) +{ + + Name(TRT0, Package() + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.B0D4, 10, 100, 0, 0, 0, 0}, + + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TPCH, 30, 50, 0, 0, 0, 0}, + + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 300, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TSKN, 1, 300, 0, 0, 0, 0}, + + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TAMB, 1, 200, 0, 0, 0, 0}, + + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TINL, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.LPCB.H_EC.TINL, 20, 200, 0, 0, 0, 0} + }) + + // TRTR (Thermal Relationship Table Revision) + // + // This object evaluates to an integer value that defines the revision of the _TRT object. + // + // Arguments: (0) + // None + // Return Value: + // 0: Traditional TRT as defined by the ACPI Specification. + // 1: Priority based TRT + // + Method(TRTR) + { + Return(TRTV) + } + + // _TRT (Thermal Relationship Table) + // + // Arguments: (0) + // None + // Return Value: + // A variable-length Package containing a list of Thermal Relationship Packages as described below. + // + // Return Value Information + // Package { + // ThermalRelationship[0] // Package + // ... + // ThermalRelationship[n] // Package + // } + // + Method(_TRT,,,,PkgObj) + { + Return(TRT0) + } // End _TRT +} + diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/TAmbDppmPolicy.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TAmbDppmPolicy.asl new file mode 100644 index 0000000..8546d23 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TAmbDppmPolicy.asl @@ -0,0 +1,140 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TamdDppmPolicy.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.LPCB.H_EC.TAMB) +{ + Name(CTYP,0) // Device-specific cooling policy preference + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP, 3, Serialized) + { + If(LOr(LEqual(Arg0,0),LEqual(Arg0,1))) + { + Store(Arg0, CTYP) + P8XH(0, Arg1) + P8XH(1, Arg2) + Notify(\_SB.PCI0.LPCB.H_EC.TAMB, 0x91) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC0) + { + If(CTYP) + { + Store(\_SB.IETM.CTOK(AMPT),Local1) // Passive Cooling Policy + } Else { + Store(\_SB.IETM.CTOK(AMAT),Local1) // Active Cooling Policy + } + If(LGreaterEqual(LSTM,Local1)) + { + Return(Subtract(Local1,20)) // subtract 2 degrees which is the Hysteresis + } + Else + { + Return(Local1) + } + } + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT, 0, Serialized) + { + Return(\_SB.IETM.CTOK(AMCT)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + Return(\_SB.IETM.CTOK(AMHT)) + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV, 0, Serialized) + { + If(CTYP) + { + Return(\_SB.IETM.CTOK(AMAT)) // Active Cooling Policy + } Else { + Return(\_SB.IETM.CTOK(AMPT)) // Passive Cooling Policy + } + } + +} // End Scope(\_SB.PCI0.LPCB.H_EC.TAMB) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/TAmbParticipant.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TAmbParticipant.asl new file mode 100644 index 0000000..f7a91b9 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TAmbParticipant.asl @@ -0,0 +1,184 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TambParticipant.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.LPCB.H_EC) +{ + + Device(TAMB) // Ambient temperature sensor + { + Name(_HID, EISAID("INT3403")) // Intel DPTF Temperature Sensor Device + Name(_UID, 1) + + Name(HITP, 0x64) + Name(AAUX, 0x10) + Name(_STR, Unicode ("Ambience Temperature Sensor")) + Name(PTYP, 0x03) + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(AMBD,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + // _TMP (Temperature) + // + // This control method returns the thermal zone's current operating temperature. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin) + // + Method(_TMP,0,Serialized) + { + If(\ECON) + { + // Get the Ambient Temperature. + Return(\_SB.IETM.CTOK(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.AMBT)))) + } Else { + Return(3000) + } + } + + // Returns Number of Aux Trips available + Name(PATC, 2) + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT0, 1, Serialized) + { + If (\ECON) + { + Store (Acquire(\_SB.PCI0.LPCB.H_EC.PATM, 100),Local0) // save Acquire result so we can check for Mutex acquired + If (LEqual(Local0, Zero)) // check for Mutex acquired + { + Store(\_SB.IETM.KTOC(Arg0),AAUX) + \_SB.PCI0.LPCB.H_EC.ECWT(0x3, RefOf(\_SB.PCI0.LPCB.H_EC.TSI)) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.HYST)) + \_SB.PCI0.LPCB.H_EC.ECWT(AAUX, RefOf(\_SB.PCI0.LPCB.H_EC.TSLT)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x4A) //Set Trip point. + Release(\_SB.PCI0.LPCB.H_EC.PATM) + } + } + } + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT1, 1, Serialized) + { + If (\ECON) + { + Store (Acquire(\_SB.PCI0.LPCB.H_EC.PATM, 100),Local0) // save Acquire result so we can check for Mutex acquired + If (LEqual(Local0, Zero)) // check for Mutex acquired + { + Store(\_SB.IETM.KTOC(Arg0),HITP) + \_SB.PCI0.LPCB.H_EC.ECWT(0x3, RefOf(\_SB.PCI0.LPCB.H_EC.TSI)) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.HYST)) + \_SB.PCI0.LPCB.H_EC.ECWT(HITP, RefOf(\_SB.PCI0.LPCB.H_EC.TSHT)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x4A) //Set Trip point. + Release(\_SB.PCI0.LPCB.H_EC.PATM) + } + } + } + + // Thermal Sensor Hysteresis, 2 degrees + Name(GTSH, 20) + + Name(LSTM,0) // Last temperature reported + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(TAMB, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius, this could be a platform policy with setup item + } + + } // End TAMB Device +}// end Scope(\_SB.PCI0.LPCB.H_EC) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/TEfnDppmPolicy.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TEfnDppmPolicy.asl new file mode 100644 index 0000000..9f696d1 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TEfnDppmPolicy.asl @@ -0,0 +1,179 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TEFNDppmPolicy.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.LPCB.H_EC.TEFN) +{ + Name(CTYP,0) // Device-specific cooling policy preference + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP, 3, Serialized) + { + If(LOr(LEqual(Arg0,0),LEqual(Arg0,1))) + { + Store(Arg0, CTYP) + P8XH(0, Arg1) + P8XH(1, Arg2) + Notify(\_SB.PCI0.LPCB.H_EC.TEFN, 0x91) + } + } + + // Returns the value at which the OS initiates Active + // cooling. + Method(_AC0) + { + If(CTYP) + { + Store(\_SB.IETM.CTOK(EFPT),Local1) // Passive Cooling Policy + } Else { + Store(\_SB.IETM.CTOK(EFAT),Local1) // Active Cooling Policy + } + If(LGreaterEqual(LSTM,Local1)) + { + Return(Subtract(Local1,20)) // subtract 2 degrees which is the Hysteresis + } + Else + { + Return(Local1) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC1) + { + Return(Subtract(_AC0(), 50)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC2) + { + Return(Subtract(_AC1(), 50)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC3) + { + Return(Subtract(_AC2(), 50)) + } + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT, 0, Serialized) + { + Return(\_SB.IETM.CTOK(EFCT)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + Return(\_SB.IETM.CTOK(EFHT)) + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV, 0, Serialized) + { + If(CTYP) + { + Return(\_SB.IETM.CTOK(EFAT)) // Active Cooling Policy + } Else { + Return(\_SB.IETM.CTOK(EFPT)) // Passive Cooling Policy + } + } + +} // End Scope(\_SB.PCI0.LPCB.H_EC.TEFN) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/TEfnParticipant.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TEfnParticipant.asl new file mode 100644 index 0000000..ad61fdb --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TEfnParticipant.asl @@ -0,0 +1,184 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TEFNParticipant.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.LPCB.H_EC) +{ + + Device(TEFN) + { + Name(_HID, EISAID("INT3403")) // Intel DPTF Temperature Sensor Device + Name(_UID, 3) + + Name(HITP, 0x64) + Name(EAUX, 0x10) + Name(_STR, Unicode ("Exhaust Fan Temperature Sensor")) + Name(PTYP, 0x03) + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(EFDE,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + // _TMP (Temperature) + // + // This control method returns the thermal zone's current operating temperature. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin) + // + Method(_TMP, 0, Serialized) + { + If(\ECON) + { + // Get the Exhaust Fan Temperature. + Return(\_SB.IETM.CTOK(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.FANT)))) + } Else { + Return(3000) + } + } + + // Number of Aux Trips available + Name(PATC, 2) + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT0, 1, Serialized) + { + If (\ECON) + { + Store (Acquire(\_SB.PCI0.LPCB.H_EC.PATM, 100),Local0) // save Acquire result so we can check for Mutex acquired + If (LEqual(Local0, Zero)) // check for Mutex acquired + { + Store(\_SB.IETM.KTOC(Arg0),EAUX) + \_SB.PCI0.LPCB.H_EC.ECWT(0x1, RefOf(\_SB.PCI0.LPCB.H_EC.TSI)) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.HYST)) + \_SB.PCI0.LPCB.H_EC.ECWT(EAUX, RefOf(\_SB.PCI0.LPCB.H_EC.TSLT)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x4A) //Set Trip point. + Release(\_SB.PCI0.LPCB.H_EC.PATM) + } + } + } + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT1, 1, Serialized) + { + If (\ECON) + { + Store (Acquire(\_SB.PCI0.LPCB.H_EC.PATM, 100),Local0) // save Acquire result so we can check for Mutex acquired + If (LEqual(Local0, Zero)) // check for Mutex acquired + { + Store(\_SB.IETM.KTOC(Arg0),HITP) + \_SB.PCI0.LPCB.H_EC.ECWT(0x1, RefOf(\_SB.PCI0.LPCB.H_EC.TSI)) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.HYST)) + \_SB.PCI0.LPCB.H_EC.ECWT(HITP, RefOf(\_SB.PCI0.LPCB.H_EC.TSHT)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x4A) //Set Trip point. + Release(\_SB.PCI0.LPCB.H_EC.PATM) + } + } + } + + // Thermal Sensor Hysteresis, 2 degrees + Name(GTSH, 20) + + Name(LSTM,0) // Last temperature reported + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(TEFN, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius, this could be a platform policy with setup item + } + + } // End TEFN Device +}// end Scope(\_SB.PCI0.LPCB.H_EC) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/TFN1Participant.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TFN1Participant.asl new file mode 100644 index 0000000..a119363 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TFN1Participant.asl @@ -0,0 +1,170 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TFN1Participant.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.LPCB.H_EC) +{ + + Device(TFN1) + { + Name(_HID, EISAID("INT3404")) // Intel DPTF Fan Device + Name(_UID, 0) + + Name(FON, 1) // Indicates if Fan is ON Currently + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(FND1,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + // _FIF (Fan Information) + // + // The optional _FIF object provides OSPM with fan device capability information. + // + // Arguments: (0) + // None + // Return Value: + // A Package containing the fan device parameters. + // + Method(_FIF) + { + Return (Package (){ + 0, // Revision:Integer + 1, // FineGrainControl:Integer Boolean + 2, // StepSize:Integer DWORD + 0 // LowSpeedNotificationSupport:Integer Boolean + }) + } + + // _FPS (Fan Performance States) + // + // Evaluates to a variable-length package containing a list of packages that describe the fan device's performance states. + // + // Arguments: (0) + // None + // Return Value: + // A variable-length Package containing a Revision ID and a list of Packages that describe the fan device's performance states. + // + Method(_FPS,,,,PkgObj) + { + Return (Package() + { + 0, // Revision:Integer + // Control, TripPoint, Speed, NoiseLevel, Power + Package(){100, 0xFFFFFFFF, 7000, 500, 5000}, + Package(){ 95, 0xFFFFFFFF, 6650, 475, 4750}, + Package(){ 90, 0xFFFFFFFF, 6300, 450, 4500}, + Package(){ 85, 0xFFFFFFFF, 5950, 425, 4250}, + Package(){ 80, 0xFFFFFFFF, 5600, 400, 4000}, + Package(){ 75, 0xFFFFFFFF, 5250, 375, 3750}, + Package(){ 70, 0xFFFFFFFF, 4900, 350, 3500}, + Package(){ 60, 0xFFFFFFFF, 4200, 300, 3000}, + Package(){ 50, 0xFFFFFFFF, 3500, 250, 2500}, + Package(){ 40, 0xFFFFFFFF, 2800, 200, 2000}, + Package(){ 25, 0xFFFFFFFF, 1750, 125, 1250}, + Package(){ 0, 0xFFFFFFFF, 0, 0, 0} // OFF + }) + } + + // _FSL (Fan Set Level) + // + // The optional _FSL object is a control method that OSPM evaluates to set a fan device's speed (performance state) to a specific level. + // + // Arguments: (1) + // Arg0 - Level (Integer): conveys to the platform the fan speed level to be set. + // Return Value: + // None + // + // Argument Information + // Arg0: Level. If the fan supports fine-grained control, Level is a percentage of maximum level (0-100) + // that the platform is to engage the fan. If the fan does not support fine-grained control, + // Level is a Control field value from a package in the _FPS object's package list. + // A Level value of zero causes the platform to turn off the fan. + // + Method(_FSL,1,Serialized) + { + If(\ECON) + { + If(LNot(LEqual(Arg0,\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PENV))))) + { // EC implementation-sepcific PWM port control + \_SB.PCI0.LPCB.H_EC.ECWT(1, RefOf(\_SB.PCI0.LPCB.H_EC.PPSL)) + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PPSH)) + \_SB.PCI0.LPCB.H_EC.ECWT(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PENV)), RefOf(\_SB.PCI0.LPCB.H_EC.PINV)) + \_SB.PCI0.LPCB.H_EC.ECWT(Arg0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) + \_SB.PCI0.LPCB.H_EC.ECWT(100, RefOf(\_SB.PCI0.LPCB.H_EC.PSTP)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) // Command to turn the fan on + Notify(\_SB.IETM, 0x83) // Notify DPTF TZ that fan speed has changed + } + } + } + + Name(TFST, Package() + { + 0, // Revision:Integer + 0xFFFFFFFF, // Control:Integer DWORD + 0xFFFFFFFF // Speed:Integer DWORD + }) + + //_FST (Fan Status) + // + // The optional _FST object provides status information for the fan device. + // + // Arguments: (0) + // None + // Return Value: + // A Package containing fan device status information + // + Method(_FST,,,,PkgObj) + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PENV)), Index(TFST, 1)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.CFSP)), Index(TFST, 2)) + Return(TFST) + } + + } // End TFN1 Device +}// end Scope(\_SB.PCI0.LPCB.H_EC) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/TFN2Participant.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TFN2Participant.asl new file mode 100644 index 0000000..c585e72 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TFN2Participant.asl @@ -0,0 +1,167 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TFN2Participant.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.LPCB.H_EC) +{ + + Device(TFN2) + { + Name(_HID, EISAID("INT3404")) // Intel DPPM Fan Device 2 DUMMY DEVICE + Name(_UID, 1) + + Name(FCTL, 100) + Name(FSPD, 200) + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(FND2,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + // _FIF (Fan Information) + // + // The optional _FIF object provides OSPM with fan device capability information. + // + // Arguments: (0) + // None + // Return Value: + // A Package containing the fan device parameters. + // + Name(_FIF, Package() + { + 0, + 1, + 50, + 0 + }) + + // _FPS (Fan Performance States) + // + // Evaluates to a variable-length package containing a list of packages that describe the fan device's performance states. + // + // Arguments: (0) + // None + // Return Value: + // A variable-length Package containing a Revision ID and a list of Packages that describe the fan device's performance states. + // + Method(_FPS,,,,PkgObj) // Get Fan P-States + { + // Get Fan Device Data default as CRB + Return (Package() + { + 0, // Revision + // + // Control Trip Point Speed NoiseLevel Power + Package(){100, 0xFFFFFFFF, 200, 700, 7000}, + Package(){ 50, 0xFFFFFFFF, 100, 350, 3500}, + Package(){ 0, 0xFFFFFFFF, 0, 0, 0} // OFF + }) + } + + // _FSL (Fan Set Level) + // + // The optional _FSL object is a control method that OSPM evaluates to set a fan device's speed (performance state) to a specific level. + // + // Arguments: (1) + // Arg0 - Level (Integer): conveys to the platform the fan speed level to be set. + // Return Value: + // None + // + // Argument Information + // Arg0: Level. If the fan supports fine-grained control, Level is a percentage of maximum level (0-100) + // that the platform is to engage the fan. If the fan does not support fine-grained control, + // Level is a Control field value from a package in the _FPS object's package list. + // A Level value of zero causes the platform to turn off the fan. + // + Method(_FSL, 1, Serialized) + { + If(\ECON) + { + If(LNot(LEqual(Arg0, FCTL))) + { + Store(Arg0, FCTL) + If (LGreaterEqual(Arg0, 51)) + { + Store(200, FSPD) + } + If (LGreaterEqual(Arg0, 1)) + { + Store(100, FSPD) + } + Else + { + Store(0, FSPD) + } + } + } + } + + Name(TFST, Package() + { + 0, // Revision + 0xFFFFFFFF, // Control + 0xFFFFFFFF // Speed + }) + + //_FST (Fan Status) + // + // The optional _FST object provides status information for the fan device. + // + // Arguments: (0) + // None + // Return Value: + // A Package containing fan device status information + // + Method(_FST,,,,PkgObj) + { + Store(FCTL, Index(TFST, 1)) + Store(FSPD, Index(TFST, 2)) + Return(TFST) + } + } // End TFN2 Device +}// end Scope(\_SB.PCI0.LPCB.H_EC) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/TMemDppmPolicy.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TMemDppmPolicy.asl new file mode 100644 index 0000000..c01d155 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TMemDppmPolicy.asl @@ -0,0 +1,173 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TMemDppmPolicy.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.TMEM) +{ + Name(CTYP,0) // Device-specific cooling policy preference + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT) + { + Return(\_SB.IETM.CTOK(MEMC)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + Return(\_SB.IETM.CTOK(MEMH)) + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV) + { + If(CTYP) + { + Return(\_SB.IETM.CTOK(ATRA)) // Passive Cooling Policy + } Else { + Return(\_SB.IETM.CTOK(PTRA)) // Active Cooling Policy + } + } + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP, 3, Serialized) + { + If(LOr(LEqual(Arg0,0),LEqual(Arg0,1))) + { + Store(Arg0, CTYP) + P8XH(0, Arg1) + P8XH(1, Arg2) + Notify(TMEM, 0x91) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC0) + { + If(CTYP) + { + Store(\_SB.IETM.CTOK(PTRA),Local1) // Passive Cooling Policy + } + Else + { + Store(\_SB.IETM.CTOK(ATRA),Local1) // Active Cooling Policy + } + If(LGreaterEqual(LSTM,Local1)) + { + Return(Subtract(Local1,20)) // subtract 2 degrees which is the Hysteresis + } + Else + { + Return(Local1) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC1) + { + If(CTYP) + { + Store(\_SB.IETM.CTOK(PTRA),Local0) // Passive Cooling Policy + } + Else + { + Store(\_SB.IETM.CTOK(ATRA),Local0) // Active Cooling Policy + } + Subtract(Local0, 50, Local0) + If(LGreaterEqual(LSTM,Local0)) + { + Return(Subtract(Local0,20)) // subtract 2 degrees which is the Hysteresis + } + Else + { + Return(Local0) + } + } +} // End Scope(\_SB.PCI0.TMEM) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/TMemParticipant.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TMemParticipant.asl new file mode 100644 index 0000000..0520b32 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TMemParticipant.asl @@ -0,0 +1,264 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TMemParticipant.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0) +{ + + Device(TMEM) + { + Name(_HID, EISAID("INT3402")) // Intel DPTF Memory Device + Name(_UID, 0) + + Name(SAUX, 0x10) + Name(LSTM,0) // Last temperature reported + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(MEMD,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + // PPCC (Participant Power Control Capabilities) + // + // The PPCC object evaluates to a package of packages that indicates to DPTF processor + // participant the power control capabilities. + // + // Arguments: (0) + // None + // Return Value: + // PPCC package of packages + // + Method(PPCC,0,Serialized,,PkgObj) + { + Return(NPCC) + } + + Name (NPCC, Package() + { // Field Name : Field Type + 2, // Revision : DWordConst + + Package () // Power Limit 1 + { + 0, // PowerLimitIndex : DWordConst = 0 + 1000, // PowerLimitMinimum : DWordConst + 5000, // PowerLimitMaximum : DWordConst + 1, // TimeWindowMinimum : DWordConst + 28, // TimeWindowMaximum : DWordConst + 1000, // StepSize : DWordConst + }, + Package () // Power Limit 2 + { + 1, // PowerLimitIndex : DWordConst = 1 + 1000, // PowerLimitMinimum : DWordConst + 10000, // PowerLimitMaximum : DWordConst + 0, // TimeWindowMinimum : DWordConst + 0, // TimeWindowMaximum : DWordConst + 1000, // StepSize : DWordConst + } + }) // End of PPCC object + + // _TMP (Temperature) + // + // This control method returns the thermal zone's current operating temperature. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin) + // + Method(_TMP) + { + If(\ECON) + { + If(\TSOD) // if TS-on-DIMM sensor present and selected in BIOS SETUP return higher temp + { + If(LGreater(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.TSD0)),\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.TSD1)))) + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.TSD0)),Local1) // TS-on-DIMM0 temperature + } + Else + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.TSD1)),Local1) // TS-on-DIMM1 temperature + } + } + Else // else return higher On-Board DDR Thermal Sensor temp + { + If(LGreater(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.DIM0)),\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.DIM1)))) + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.DIM0)),Local1) // DIMM0 temperature + } + Else + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.DIM1)),Local1) // DIMM1 temperature + } + } + Return(\_SB.IETM.CTOK(Local1)) // EC reports in Celcius, convert to 10ths of degree Kelvin + } + Else + { + Return(3000) + } + } + + Name(PATC, 2) + + Name(AT0, Ones) + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT0, 1) // send Arg0 to EC as Programmable Auxiliary Trip Point 0 + { + If (\ECON) + { + Store (Acquire(\_SB.PCI0.LPCB.H_EC.PATM, 100),Local0) // save Acquire result so we can check for Mutex acquired + If (LEqual(Local0, Zero)) // check for Mutex acquired + { + Store(Arg0, AT0) // used for debugging + Store(\_SB.IETM.KTOC(Arg0),SAUX) + \_SB.PCI0.LPCB.H_EC.ECWT(0x4, RefOf(\_SB.PCI0.LPCB.H_EC.TSI)) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.HYST)) // Thermal Sensor Hysteresis, 2 degrees + \_SB.PCI0.LPCB.H_EC.ECWT(SAUX, RefOf(\_SB.PCI0.LPCB.H_EC.TSLT)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x4A) // Set Trip point + Release(\_SB.PCI0.LPCB.H_EC.PATM) + } + } + } + + Name(AT1, Ones) + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT1, 1) // send Arg0 to EC as Programmable Auxiliary Trip Point 1 + { + If (\ECON) + { + Store (Acquire(\_SB.PCI0.LPCB.H_EC.PATM, 100),Local0) // save Acquire result so we can check for Mutex acquired + If (LEqual(Local0, Zero)) // check for Mutex acquired + { + Store(Arg0, AT1) // used for debugging + Store(\_SB.IETM.KTOC(Arg0),SAUX) + \_SB.PCI0.LPCB.H_EC.ECWT(0x4, RefOf(\_SB.PCI0.LPCB.H_EC.TSI)) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.HYST)) // Thermal Sensor Hysteresis, 2 degrees + \_SB.PCI0.LPCB.H_EC.ECWT(SAUX, RefOf(\_SB.PCI0.LPCB.H_EC.TSHT)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x4A) // Set Trip point + Release(\_SB.PCI0.LPCB.H_EC.PATM) + } + } + } + + + // Thermal Sensor Hysteresis, 2 degrees + Name(GTSH, 20) + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(TMEM, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius, this could be a platform policy with setup item + } + + // PGMB (Pci GMch Bar) + // + // This object is required to be implemented on platforms supporting Intel code name Sandy Bridge processor. + // This object is not required for platforms supporting Intel code name Ivy Bridge processor. + // + // Arguments: (0) + // None + // Return Value: + // Return MCH Bar value. + // + Method(PGMB, 0) + { + Return(\_SB.PCI0.MHBR) // Return MCH Bar value + } + + } // End TMEM Device + +}// end Scope(\_SB.PCI0) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/TPwrParticipant.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TPwrParticipant.asl new file mode 100644 index 0000000..07532b8 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TPwrParticipant.asl @@ -0,0 +1,260 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TPwrParticipant.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + + +Scope(\_SB.IETM) +{ + // + // Power Policy + // + Name (WPSP, Package () + { + ToUUID("64568CCD-6597-4BFC-B9D6-9D33854013CE") + }) +} + +Scope(\_SB.PCI0.LPCB.H_EC) +{ + + Device(TPWR) // Power participant + { + Name(_HID, EISAID("INT3407")) //Intel DPTF platform power device + Name(_UID, 0) + Name(_STR, Unicode ("Platform Power")) + Name(PTYP, 0x11) + + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(PWRE,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + // _BST (Battery Status) + // + // Arguments: (0) + // None + // Return Value: + // A Package containing the battery status in the format below: + // Package { + // Battery State + // Battery Present Rate + // Battery Remaining Capacity + // Battery Present Voltage + // } + // + Method(_BST,,,,PkgObj) + { + If(CondRefOf(\_SB.PCI0.LPCB.H_EC.BAT1._BST)) + { + Return(\_SB.PCI0.LPCB.H_EC.BAT1._BST()) + } Else { + Return(Package(){0,0,0,0}) + } + } + + // PSOC (Platform State of Charge) + // + // This object evaluates to the remaining battery state of charge in %. + // + // Arguments: (0) + // None + // Return Value: + // remaining battery charge in % + // + Method(PSOC) + { + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECAV,0)) // check EC opregion available + { + Return (0) // EC not available + } + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1FC)),0)) // prevent divide by zero + { + Return (0) // Full charge cannot be 0, indicate malfunction in battery + } + If(LGreater(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1RC)),\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1FC)))) // remaining charge > full charge + { + Return(0) // Remaining Charge cannot be greater than Full Charge, this illegal value indicates the battery is malfunctioning + } + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1RC)),\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1FC)))) // remaining charge == full charge + { + Return(100) // indicate battery is fully charged + } + If(LLess(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1RC)),\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1FC)))) // (RC*100)/FC=percent + { + Multiply(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1RC)),100,Local0) // RC*100 + Divide(Local0,\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1FC)),Local2,Local1) // divide by FC + Divide(Local2,100,,Local2) // account for the remainder in percent + Divide(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1FC)),200,,Local3) // what number is 0.5%? + If(LGreaterEqual(Local2,Local3)){ // round up if the remainder is equal or above .5 + Add(Local1,1,Local1) + } + Return(Local1) // current charge in percent + } + } + + // PMAX (Platform MAXimum) + // + // The PMAX object provides maximum power that can be supported by the battery in mW. + // + // Arguments: (0) + // None + // Return Value: + // maximum power in mW + // + Method(PMAX,0,Serialized) + { + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.ECAV)),1)) // Check If EC opregion is available + { + // convert PMAX from signed to unsigned integer + // PMAX Value = (NOT(OR(FFFF0000, ECValue))+1) * 10. + Add(ShiftLeft(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1MH)), 8),\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1ML)),Local0) // Get high and low byte from EC. + If(Local0){ // don't convert a zero + Not(Or(0xFFFF0000,Local0,Local0),Local0) // make it a 32 bit value before inverting the bits + Multiply(Add(1,Local0,Local0),10,Local0) // add 1 and multiply by 10 + } + Return(Local0) + } Else { + Return(0) // EC not available + } + } + + + // APWR (Adapter PoWeR) + // + // Arguments: (0) + // None + // Return Value: + // AC Adapter supplied power in mW. + // + Method(APWR) + { + If (LEqual(PSRC(),0)) + { + Return(0) // EC unavailable or AC unavailable + } Else { + Return(Multiply(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PPWR)),10)) + } + } + + + // PSRC (Power SouRCe) + // + // The PSRC object provides power source type. + // + // Arguments: (0) + // None + // Return Value: + // 0x00 = DC + // 0x01 = AC + // 0x02 = USB + // + Method(PSRC) + { + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.ECAV)),1)) // Check If EC opregion is available + { + Return(\PWRS) // currently supports DC/AC only + } Else { + Return(0) // EC not available, default to battery + } + } + + // ARTG (Adapter RaTinG) + // + // The ARTG object provides AC adapter rating in mW. + // ARTG should return 0 if PSRC is DC (0). + // + // Arguments: (0) + // None + // Return Value: + // AC adapter rating in mW + // + Method(ARTG) + { + If (LEqual(PSRC(),0)) + { + Return(0) + } Else { +// TODO: setup option to choose adapter rating + Return(45000) // 45 watts + } + } + + + // CTYP (Charger TYPe) + // + // The CTYP object provides charger type. + // + // Arguments: (0) + // None + // Return Value: + // 0x01 = Traditional + // 0x02 = Hybrid + // + Method(CTYP) + { + Return(2) + } + + // PROP (Platform Rest Of worst case Power) + // + // The PROP object provides maximum worst case platform rest of power. + // + // Arguments: (0) + // None + // Return Value: + // power in mW + // + Method(PROP) + { + Return(15000) // 15 watts + } + + } // End TPWR Device +}// end Scope(\_SB.PCI0.LPCB.H_EC) + diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/TSknDppmPolicy.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TSknDppmPolicy.asl new file mode 100644 index 0000000..1187bf8 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TSknDppmPolicy.asl @@ -0,0 +1,172 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TSknDppmPolicy.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.LPCB.H_EC.TSKN) +{ + Name(CTYP,0) // Device-specific cooling policy preference + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP,3,Serialized) + { + If(LOr(LEqual(Arg0,0),LEqual(Arg0,1))) + { + Store(Arg0, CTYP) + P8XH(0, Arg1) + P8XH(1, Arg2) + Notify(\_SB.PCI0.LPCB.H_EC.TSKN, 0x91) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC3) + { + If(CTYP) + { + Store(\_SB.IETM.CTOK(SKPT),Local1) // Passive Cooling Policy + } Else { + Store(\_SB.IETM.CTOK(SKAT),Local1) // Active Cooling Policy + } + If(LGreaterEqual(LSTM,Local1)) + { + Return(Subtract(Local1,20)) // subtract 2 degrees which is the Hysteresis + } + Else + { + Return(Local1) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC4) + { + Return(Subtract(_AC3(), 50)) + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC5) + { + Return(Subtract(_AC3(), 100)) + } + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT) + { + Return(\_SB.IETM.CTOK(SKCT)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + Return(\_SB.IETM.CTOK(SKHT) ) + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV) + { + If(CTYP) + { + Return(\_SB.IETM.CTOK(SKAT)) // Active Cooling Policy + } Else { + Return(\_SB.IETM.CTOK(SKPT)) // Passive Cooling Policy + } + } + +} // End Scope(\_SB.PCI0.LPCB.H_EC.TSKN) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/TSknParticipant.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TSknParticipant.asl new file mode 100644 index 0000000..bb6586c --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TSknParticipant.asl @@ -0,0 +1,183 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TSknParticipant.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.LPCB.H_EC) +{ + + Device(TSKN) // Skin temperature sensor + { + Name(_HID, EISAID("INT3403")) // Intel DPTF Temperature Sensor Device + Name(_UID, 0) + + Name(HITP, 0x64) + Name(SAUX, 0x10) + Name(_STR, Unicode ("Skin Temperature Sensor")) + Name(PTYP, 0x03) + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(SKDE,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + // _TMP (Temperature) + // + // This control method returns the thermal zone's current operating temperature. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin) + // + Method(_TMP,0,Serialized) + { + If(\ECON) + { // Get the Skin Temperature. + Return(\_SB.IETM.CTOK(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.SKNT)))) + } Else { + Return(3000) + } + } + + // Number of Aux Trips available + Name(PATC, 2) + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT0, 1, Serialized) + { + If (\ECON) + { + Store (Acquire(\_SB.PCI0.LPCB.H_EC.PATM, 100),Local0) // save Acquire result so we can check for Mutex acquired + If (LEqual(Local0, Zero)) // check for Mutex acquired + { + Store(\_SB.IETM.KTOC(Arg0),SAUX) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.TSI)) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.HYST)) + \_SB.PCI0.LPCB.H_EC.ECWT(SAUX, RefOf(\_SB.PCI0.LPCB.H_EC.TSLT)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x4A) // Set Trip point + Release(\_SB.PCI0.LPCB.H_EC.PATM) + } + } + } + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT1, 1, Serialized) + { + If (\ECON) + { + Store (Acquire(\_SB.PCI0.LPCB.H_EC.PATM, 100),Local0) // save Acquire result so we can check for Mutex acquired + If (LEqual(Local0, Zero)) // check for Mutex acquired + { + Store(\_SB.IETM.KTOC(Arg0),HITP) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.TSI)) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.HYST)) + // Set High Trip to PSV or ACT + \_SB.PCI0.LPCB.H_EC.ECWT(HITP, RefOf(\_SB.PCI0.LPCB.H_EC.TSHT)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x4A) //Set Trip point. + Release(\_SB.PCI0.LPCB.H_EC.PATM) + } + } + } + + // Thermal Sensor Hysteresis, 2 degrees + Name(GTSH, 20) + + Name(LSTM,0) // Last temperature reported + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(TSKN, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius, this could be a platform policy with setup item + } + + } // End TSKN Device +}// end Scope(\_SB.PCI0.LPCB.H_EC) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/T_VRDppmPolicy.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/T_VRDppmPolicy.asl new file mode 100644 index 0000000..d022df7 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/T_VRDppmPolicy.asl @@ -0,0 +1,140 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + T_VRDppmPolicy.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.LPCB.H_EC.T_VR) +{ + Name(CTYP,0) // Device-specific cooling policy preference + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP, 3, Serialized) + { + If(LOr(LEqual(Arg0,0),LEqual(Arg0,1))) + { + Store(Arg0, CTYP) + P8XH(0, Arg1) + P8XH(1, Arg2) + Notify(\_SB.PCI0.LPCB.H_EC.T_VR, 0x91) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC0) + { + If(CTYP) + { + Store(\_SB.IETM.CTOK(VRPT),Local1) // Passive Cooling Policy + } Else { + Store(\_SB.IETM.CTOK(VRAT),Local1) // Active Cooling Policy + } + If(LGreaterEqual(LSTM,Local1)) + { + Return(Subtract(Local1,20)) // subtract 2 degrees which is the Hysteresis + } + Else + { + Return(Local1) + } + } + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT, 0, Serialized) + { + Return(\_SB.IETM.CTOK(VRCT)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + Return(\_SB.IETM.CTOK(VRHT)) + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV, 0, Serialized) + { + If(CTYP) + { + Return(\_SB.IETM.CTOK(VRAT)) // Active Cooling Policy + } Else { + Return(\_SB.IETM.CTOK(VRPT)) // Passive Cooling Policy + } + } + +} // End Scope(\_SB.PCI0.LPCB.H_EC.T_VR) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/T_VRParticipant.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/T_VRParticipant.asl new file mode 100644 index 0000000..6ade5f0 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/T_VRParticipant.asl @@ -0,0 +1,184 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + T_VRParticipant.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.LPCB.H_EC) +{ + + Device(T_VR) // VR temperature sensor + { + Name(_HID, EISAID("INT3403")) // Intel DPTF Temperature Sensor Device + Name(_UID, 2) + + Name(HITP, 0x64) + Name(VAUX, 0x10) + Name(_STR, Unicode ("VR Temperature Sensor")) + Name(PTYP, 0x03) + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(VRDE,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + // _TMP (Temperature) + // + // This control method returns the thermal zone's current operating temperature. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin) + // + Method(_TMP, 0, Serialized) + { + If(\ECON) + { + // Get the CPU VR Temperature. + Return(\_SB.IETM.CTOK(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.CVRT)))) + } Else { + Return(3000) + } + } + + // Returns Number of Aux Trips available + Name(PATC, 2) + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT0, 1, Serialized) + { + If (\ECON) + { + Store (Acquire(\_SB.PCI0.LPCB.H_EC.PATM, 100),Local0) // save Acquire result so we can check for Mutex acquired + If (LEqual(Local0, Zero)) // check for Mutex acquired + { + Store(\_SB.IETM.KTOC(Arg0),VAUX) + \_SB.PCI0.LPCB.H_EC.ECWT(0x0, RefOf(\_SB.PCI0.LPCB.H_EC.TSI)) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.HYST)) + \_SB.PCI0.LPCB.H_EC.ECWT(VAUX, RefOf(\_SB.PCI0.LPCB.H_EC.TSLT)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x4A) // Set Trip point. + Release(\_SB.PCI0.LPCB.H_EC.PATM) + } + } + } + + // PATx (Participant Programmable Auxiliary Trip) - Sets Aux Trip Point + // + // The PATx objects shall take a single integer parameter, in tenths of degree Kelvin, which + // represents the temperature at which the device should notify the participant driver of + // an auxiliary trip event. A PATx control method returns no value. + // + // Arguments: (1) + // Arg0 - temperature in tenths of degree Kelvin + // Return Value: + // None + // + Method(PAT1, 1, Serialized) + { + If (\ECON) + { + Store (Acquire(\_SB.PCI0.LPCB.H_EC.PATM, 100),Local0) // save Acquire result so we can check for Mutex acquired + If (LEqual(Local0, Zero)) // check for Mutex acquired + { + Store(\_SB.IETM.KTOC(Arg0),HITP) + \_SB.PCI0.LPCB.H_EC.ECWT(0x0, RefOf(\_SB.PCI0.LPCB.H_EC.TSI)) + \_SB.PCI0.LPCB.H_EC.ECWT(0x2, RefOf(\_SB.PCI0.LPCB.H_EC.HYST)) + \_SB.PCI0.LPCB.H_EC.ECWT(HITP, RefOf(\_SB.PCI0.LPCB.H_EC.TSHT)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x4A) // Set Trip point. + Release(\_SB.PCI0.LPCB.H_EC.PATM) + } + } + } + + // Thermal Sensor Hysteresis, 2 degrees + Name(GTSH, 20) + + Name(LSTM,0) // Last temperature reported + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(T_VR, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius, this could be a platform policy with setup item + } + + } // End T_VR Device +}// end Scope(\_SB.PCI0.LPCB.H_EC) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/TcpuDppmPolicy.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TcpuDppmPolicy.asl new file mode 100644 index 0000000..2561099 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TcpuDppmPolicy.asl @@ -0,0 +1,304 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TcpuDppmPolicy.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.TCPU) +{ + Name(CTYP,0) // Device-specific cooling policy preference + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC0) + { + If(CTYP) + { + Store(\_SB.IETM.CTOK(PSVT),Local1) // Passive Cooling Policy + } + Else + { + Store(\_SB.IETM.CTOK(ACTT),Local1) // Active Cooling Policy + } + If(LGreaterEqual(LSTM,Local1)) + { + Return(Subtract(Local1,Multiply(2, 10))) + } + Else + { + Return(Local1) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC1) + { + If(CTYP) + { + Store(\_SB.IETM.CTOK(PSVT),Local0) // Passive Cooling Policy + } + Else + { + Store(\_SB.IETM.CTOK(ACTT),Local0) // Active Cooling Policy + } + Subtract(Local0, 50, Local0) + + If(LGreaterEqual(LSTM,Local0)) + { + Return (Subtract(Local0, Multiply(2, 10))) + } + Else + { + Return(Local0) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC2) + { + If(CTYP) + { + Store(\_SB.IETM.CTOK(PSVT),Local0) // Passive Cooling Policy + } + Else + { + Store(\_SB.IETM.CTOK(ACTT),Local0) // Active Cooling Policy + } + Subtract(Local0, 100, Local0) + If(LGreaterEqual(LSTM,Local0)) + { + Return (Subtract(Local0, Multiply(2, 10))) + } + Else + { + Return(Local0) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC3) + { + If(CTYP) + { + Store(\_SB.IETM.CTOK(PSVT),Local0) // Passive Cooling Policy + } + Else + { + Store(\_SB.IETM.CTOK(ACTT),Local0) // Active Cooling Policy + } + Subtract(Local0, 150, Local0) + If(LGreaterEqual(LSTM,Local0)) + { + Return (Subtract(Local0, Multiply(2, 10))) + } + Else + { + Return(Local0) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC4) + { + If(CTYP) + { + Store(\_SB.IETM.CTOK(PSVT),Local0) // Passive Cooling Policy + } + Else + { + Store(\_SB.IETM.CTOK(ACTT),Local0) // Active Cooling Policy + } + Subtract(Local0, 200, Local0) + If(LGreaterEqual(LSTM,Local0)) + { + Return (Subtract(Local0, Multiply(2, 10))) + } + Else + { + Return(Local0) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC5) + { + If(CTYP) + { + Store(\_SB.IETM.CTOK(PSVT),Local0) // Passive Cooling Policy + } + Else + { + Store(\_SB.IETM.CTOK(ACTT),Local0) // Active Cooling Policy + } + Subtract(Local0, 250, Local0) + If(LGreaterEqual(LSTM,Local0)) + { + Return (Subtract(Local0, Multiply(2, 10))) + } + Else + { + Return(Local0) + } + } + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT,0,Serialized) + { + Return(\_SB.IETM.CTOK(CRTT)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + Return(\_SB.IETM.CTOK(Subtract(CRTT, 3))) + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV,0,Serialized) + { + If(CTYP) + { + Return(\_SB.IETM.CTOK(ACTT)) // Passive Cooling Policy + } Else { + Return(\_SB.IETM.CTOK(PSVT)) // Active Cooling Policy + } + } + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP, 3, Serialized) + { + If(LOr(LEqual(Arg0,0),LEqual(Arg0,1))) + { + Store(Arg0, CTYP) + P8XH(0, Arg1) + P8XH(1, Arg2) + Notify(\_SB.TCPU, 0x91) + } + } + +} // End Scope(\_SB.TCPU) + diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/TcpuParticipant.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TcpuParticipant.asl new file mode 100644 index 0000000..ac6e1cb --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TcpuParticipant.asl @@ -0,0 +1,423 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TcpuParticipant.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + + +Scope(\_SB) +{ + Device(TCPU) + { + External (PPCS) + + Name(_HID, EISAID("INT3401")) // Intel Dptf Processor Device, 1 per package + Name(_UID,0) + + Name(CINT,1) + Name(LSTM,0) // Last temperature reported + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(SADE,2)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + // PGMB (Pci GMch Bar) + // + // This object is required to be implemented on platforms supporting Intel code name Sandy Bridge processor. + // This object is not required for platforms supporting Intel code name Ivy Bridge processor. + // + // Arguments: (0) + // None + // Return Value: + // Return MCH Bar value. + // + Method(PGMB, 0) + { + Return(\_SB.PCI0.MHBR) // Return MCH Bar value + } + + // _PPC (Performance Present Capabilities) + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the range of states supported + // 0 - States 0 through nth state are available (all states available) + // 1 - States 1 through nth state are available + // 2 - States 2 through nth state are available + // ... + // n - State n is available only + // + Name(_PPC,0) + + // SPPC (Set Participant Performance Capability) + // + // SPPC is a control method object that takes one integer parameter that will indicate the maximum allowable + // P-State for OSPM to use at any given time. + // + // Arguments: (1) + // Arg0 - integer + // Return Value: + // None + // + Method(SPPC,1,Serialized) + { + Store(Arg0, \_PR.CPU0._PPC) // Note: CPU0._PPC is an Integer not a Method + + If(CondRefOf(\_SB.PCCD.PENB)) { // is CPPC enabled in SETUP? + Notify(\_SB.PCCD,0x82) // CPPC notify + } Else { + Switch(ToInteger(TCNT)){ + Case(8){ + Notify(\_PR.CPU0, 0x80) // Tell CPU0 driver to re-eval _PPC + Notify(\_PR.CPU1, 0x80) // Tell CPU1 driver to re-eval _PPC + Notify(\_PR.CPU2, 0x80) // Tell CPU2 driver to re-eval _PPC + Notify(\_PR.CPU3, 0x80) // Tell CPU3 driver to re-eval _PPC + Notify(\_PR.CPU4, 0x80) // Tell CPU4 driver to re-eval _PPC + Notify(\_PR.CPU5, 0x80) // Tell CPU5 driver to re-eval _PPC + Notify(\_PR.CPU6, 0x80) // Tell CPU6 driver to re-eval _PPC + Notify(\_PR.CPU7, 0x80) // Tell CPU7 driver to re-eval _PPC + } + Case(4){ + Notify(\_PR.CPU0, 0x80) // Tell CPU0 driver to re-eval _PPC + Notify(\_PR.CPU1, 0x80) // Tell CPU1 driver to re-eval _PPC + Notify(\_PR.CPU2, 0x80) // Tell CPU2 driver to re-eval _PPC + Notify(\_PR.CPU3, 0x80) // Tell CPU3 driver to re-eval _PPC + } + Case(2){ + Notify(\_PR.CPU0, 0x80) // Tell CPU0 driver to re-eval _PPC + Notify(\_PR.CPU1, 0x80) // Tell CPU1 driver to re-eval _PPC + } + Default{ + Notify(\_PR.CPU0, 0x80) // Tell CPU0 driver to re-eval _PPC + } + } + } + } + + // _TMP (Temperature) + // + // This control method returns the thermal zone's current operating temperature. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin) + // + //AMI override begin + //Method(_TMP) + Method(TMPX) + //AMI override end + { + // Return the temperature to the OS if EC access is enabled. + If(\ECON) + { + Return(\_SB.IETM.CTOK(\_SB.PCI0.LPCB.H_EC.PECH)) + } + Else + { + // Return a static value as EC access is disabled or DPTF is active. + Return(3000) + } + } + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(TCPU, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius, this could be a platform policy with setup item + } + + // _PSS (Performance Supported States) + // + // This optional object indicates to OSPM the number of supported processor performance states that any given system can support. + // + // Arguments: (1) + // None + // Return Value: + // A variable-length Package containing a list of Pstate sub-packages as described below + // + // Return Value Information + // Package { + // PState [0] // Package - Performance state 0 + // .... + // PState [n] // Package - Performance state n + // } + // + // Each Pstate sub-Package contains the elements described below: + // Package { + // CoreFrequency // Integer (DWORD) + // Power // Integer (DWORD) + // Latency // Integer (DWORD) + // BusMasterLatency // Integer (DWORD) + // Control // Integer (DWORD) + // Status // Integer (DWORD) + // } + // + // Stub for the Actual CPU _PSS method. + // + Method(_PSS,,,,PkgObj) + { + If(CondRefOf(\_PR.CPU0._PSS)) + { // Ensure _PSS is present + Return(\_PR.CPU0._PSS()) + } Else { + Return(Package(){ + Package(){0,0,0,0,0,0}, + Package(){0,0,0,0,0,0}}) + } + } + + // _TSS (Throttling Supported States) + // + // Arguments: (0) + // None + // Return Value: + // A variable-length Package containing a list of Tstate sub-packages as described below + // + // Return Value Information + // Package { + // TState [0] // Package - Throttling state 0 + // .... + // TState [n] // Package - Throttling state n + // } + // + // Each Tstate sub-Package contains the elements described below: + // Package { + // Percent // Integer (DWORD) + // Power // Integer (DWORD) + // Latency // Integer (DWORD) + // Control // Integer (DWORD) + // Status // Integer (DWORD) + // } + // + // Stub for the Actual CPU _TSS method. + // + Method(_TSS,,,,PkgObj) + { + If(CondRefOf(\_PR.CPU0._TSS)) + { // Ensure _TSS is present + Return(\_PR.CPU0._TSS()) + } Else { + Return(Package(){ + Package(){0,0,0,0,0}, + Package(){0,0,0,0,0}}) + } + } + + // _TPC (Throttling Present Capabilities) + // + // This optional object is a method that dynamically indicates to OSPM the number of throttling states currently supported by the platform. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the number of states supported: + // 0 - states 0 .. nth state available (all states available) + // 1 - state 1 .. nth state available + // 2 - state 2 .. nth state available + // ... + // n - state n available only + // + Method(_TPC) + { + If(CondRefOf(\_PR.CPU0._TPC)) + { // Ensure _TPC is present + Return(\_PR.CPU0._TPC) + } Else { + Return(0) + } + } + + // _PTC (Processor Throttling Control) + // + // _PTC is an optional object that defines a processor throttling control interface alternative to the I/O address spaced-based P_BLK throttling control register (P_CNT) + // + // PDC0[2] = ACPI object indicating if OSPM is capable of direct access to On Demand throttling MSR + // + // Arguments: (0) + // None + // Return Value: + // A Package as described below + // + // Return Value Information + // Package { + // ControlRegister // Buffer (Resource Descriptor) + // StatusRegister // Buffer (Resource Descriptor) + // } + // + Method(_PTC,,,,PkgObj) + { + If(LAnd(CondRefOf(\PDC0),LNotEqual(\PDC0,0x80000000))) // is object present and initialized? + { + If(And(\PDC0, 0x0004)) { // does OS support MSR interface? + Return(Package() { + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} }) // if OS supports MSR interface + } Else { + Return(Package() { + ResourceTemplate(){Register(SystemIO, 5, 0, PCH_ACPI_PBLK)}, + ResourceTemplate(){Register(SystemIO, 5, 0, PCH_ACPI_PBLK)} }) // if OS support IO based interface + } + } Else { + Return(Package() { + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} }) // if object is not present or not initialized then return MSR interface + } + } + + // _TSD (T-State Dependency) + // + // This optional object provides T-state control cross logical processor dependency information to OSPM. + // + // Arguments: (0) + // None + // Return Value: + // A variable-length Package containing a list of T-state dependency Packages as described below. + // + // Return Value Information + // Package { + // NumEntries // Integer + // Revision // Integer (BYTE) + // Domain // Integer (DWORD) + // CoordType // Integer (DWORD) + // NumProcessors // Integer (DWORD) + // } + // + Method(_TSD,,,,PkgObj) + { + If(CondRefOf(\_PR.CPU0._TSD)) + { // Ensure _TSD is present + Return(\_PR.CPU0._TSD()) + } Else { + Return(Package(){ + Package(){5,0,0,0,0}, + Package(){5,0,0,0,0}}) + } + } + + // _TDL (T-state Depth Limit) + // + // This optional object evaluates to the _TSS entry number of the lowest power throttling state that OSPM may use. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the Throttling Depth Limit _TSS entry number: + // 0 - throttling disabled. + // 1 - state 1 is the lowest power T-state available. + // 2 - state 2 is the lowest power T-state available. + // ... + // n - state n is the lowest power T-state available. + // + Method(_TDL) + { + If(LAnd(CondRefOf(\_PR.CPU0._TSS),CondRefOf(\_PR.CFGD))) + { // Ensure _TSS is present + If(And(\_PR.CFGD, PPM_TSTATE_FINE_GRAINED)) + { + Return(Subtract(SizeOf(\_PR.CPU0.TSMF),1)) + } Else { + Return(Subtract(SizeOf(\_PR.CPU0.TSMC),1)) + } + } Else { + Return(0) + } + } + + // _PDL (P-state Depth Limit) + // + // This optional object evaluates to the _PSS entry number of the lowest performance P-state that OSPM may use when performing passive thermal control. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the P-state Depth Limit _PSS entry number: + // Integer containing the P-state Depth Limit _PSS entry number: + // 0 - P0 is the only P-state available for OSPM use + // 1 - state 1 is the lowest power P-state available + // 2 - state 2 is the lowest power P-state available + // ... + // n - state n is the lowest power P-state available + // + Method(_PDL) + { + If(CondRefOf(\_PR.CPU0._PSS)) + { // Ensure _PSS is present + Return(Subtract(SizeOf(\_PR.CPU0._PSS),1)) + } Else { + Return(0) + } + } + + } // End Device(TCPU) +} // End Scope(\_SB) + diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/TpchDppmPolicy.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TpchDppmPolicy.asl new file mode 100644 index 0000000..affa078 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TpchDppmPolicy.asl @@ -0,0 +1,175 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TpchDppmPolicy.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.TPCH) +{ + Name (CTYP, 0) // Device-specific cooling policy preference + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP,3,Serialized) + { + If(LOr(LEqual(Arg0,0),LEqual(Arg0,1))) + { + Store(Arg0, CTYP) + P8XH(0, Arg1) + P8XH(1, Arg2) + Notify(\_SB.PCI0.TPCH, 0x91) + } + } + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT,0,Serialized) + { + Return(\_SB.IETM.CTOK(PCHC)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + Return(\_SB.IETM.CTOK(PCHH)) + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV,0,Serialized) + { + If(CTYP) + { + Return(\_SB.IETM.CTOK(ATPC)) // Passive Cooling Policy + } Else { + Return(\_SB.IETM.CTOK(PTPC)) // Active Cooling Policy + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC0) + { + If(CTYP) + { + Store(\_SB.IETM.CTOK(PTPC),Local1) // Passive Cooling Policy + } + Else + { + Store(\_SB.IETM.CTOK(ATPC),Local1) // Active Cooling Policy + } + If(LGreaterEqual(LSTM,Local1)) + { + Return(Subtract(Local1,20)) // subtract 2 degrees which is the Hysteresis + } + Else + { + Return(Local1) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC1) + { + If(CTYP) + { + Store(\_SB.IETM.CTOK(PTPC),Local0) // Passive Cooling Policy + } + Else + { + Store(\_SB.IETM.CTOK(ATPC),Local0) // Active Cooling Policy + } + Subtract(Local0, 50, Local0) + If(LGreaterEqual(LSTM,Local0)) + { + Return(Subtract(Local0,20)) // subtract 2 degrees which is the Hysteresis + } + Else + { + Return(Local0) + } + } + +} // End Scope(\_SB.PCI0.TPCH) + diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/TpchParticipant.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TpchParticipant.asl new file mode 100644 index 0000000..c8b816b --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/TpchParticipant.asl @@ -0,0 +1,113 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + TpchParticipant.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + + +Scope(\_SB.PCI0) +{ + // + // This device is currently used by DPPM policies only. + // Refer to the specific technology BIOS specification. + // + Device (TPCH) + { + Name (_ADR,0x001F0006) // Device 31, Function 6 + Name (LSTM,0) // Last temperature reported + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(PCHD,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + OperationRegion(PCHT,PCI_Config,0x10,0x08) // PCH Thermal BAR + Field(PCHT,DWordAcc,NoLock,Preserve) + { + Offset(0x0), // EPBAR (Offset 10h) + STYP, 1, // Space type + ADRG, 2, // Address Range + PREF, 1, // Prefetchable + , 8, // hardwired to 0 + TBAR, 52 // Thermal BAR + } + + // Thermal Sensor Hysteresis, 3 degree Centigrade + Name(GTSH, 30) + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(TPCH, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius, this could be a platform policy with setup item + } + + } // End Device(TPCH) +} // End Scope(\_SB.PCI0) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/Trt.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Trt.asl new file mode 100644 index 0000000..b3f6e37 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/Trt.asl @@ -0,0 +1,757 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + Trt.asl + +Abstract: + + Intel ACPI Reference Code for Intel Dynamic Power Performance Management + +--*/ + +Scope(\_SB.IETM) +{ + + Name(TRTI, Package() // TRT package when TFN1 is at 0% speed + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TPCH, 30, 20, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.TCPU, 28, 50, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.TMEM, 10, 100, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 28, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TMEM, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.TCPU, 03, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.B0D4, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.TMEM, 44, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TSKN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TAMB, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.T_VR, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TEFN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.TMEM, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.TCPU, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.WWAN, 20, 50, 0, 0, 0, 0} + }) + + Name(TRTH, Package() // TRT package when TFN1 is at 15% speed + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TPCH, 30, 20, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.TCPU, 36, 50, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.TMEM, 10, 100, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 36, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TMEM, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.TCPU, 3, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.B0D4, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.TMEM, 44, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TSKN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TAMB, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.T_VR, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TEFN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.TMEM, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.TCPU, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.WWAN, 20, 50, 0, 0, 0, 0} + }) + + Name(TRTG, Package() // TRT package when TFN1 is at 20% speed + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TPCH, 30, 20, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.TCPU, 36, 50, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.TMEM, 10, 100, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 36, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TMEM, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.TCPU, 3, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.B0D4, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.TMEM, 44, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TSKN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TAMB, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.T_VR, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TEFN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.TMEM, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.TCPU, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.WWAN, 20, 50, 0, 0, 0, 0} + }) + + Name(TRTF, Package() // TRT package when TFN1 is at 25% speed + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TPCH, 30, 20, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.TCPU, 36, 50, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.TMEM, 10, 100, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 36, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TMEM, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.TCPU, 3, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.B0D4, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.TMEM, 44, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TSKN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TAMB, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.T_VR, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TEFN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.TMEM, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.TCPU, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.WWAN, 20, 50, 0, 0, 0, 0} + }) + + Name(TRTE, Package() // TRT package when TFN1 is at 30% speed + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TPCH, 30, 20, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.TCPU, 36, 50, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.TMEM, 10, 100, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 36, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TMEM, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.TCPU, 3, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.B0D4, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.TMEM, 44, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TSKN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TAMB, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.T_VR, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TEFN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.TMEM, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.TCPU, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.WWAN, 20, 50, 0, 0, 0, 0} + }) + + Name(TRTD, Package() // TRT package when TFN1 is at 35% speed + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TPCH, 30, 20, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.TCPU, 36, 50, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.TMEM, 10, 100, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 36, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TMEM, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.TCPU, 3, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.B0D4, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.TMEM, 44, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TSKN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TAMB, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.T_VR, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TEFN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.TMEM, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.TCPU, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.WWAN, 20, 50, 0, 0, 0, 0} + }) + + Name(TRTC, Package() // TRT package when TFN1 is at 40% speed + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TPCH, 30, 20, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.TCPU, 36, 50, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.TMEM, 10, 100, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 36, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TMEM, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.TCPU, 3, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.B0D4, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.TMEM, 44, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TSKN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TAMB, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.T_VR, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TEFN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.TMEM, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.TCPU, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.WWAN, 20, 50, 0, 0, 0, 0} + }) + + Name(TRTB, Package() // TRT package when TFN1 is at 45% speed + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TPCH, 30, 20, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.TCPU, 36, 50, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.TMEM, 10, 100, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 36, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TMEM, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.TCPU, 3, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.B0D4, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.TMEM, 44, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TSKN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TAMB, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.T_VR, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TEFN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.TMEM, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.TCPU, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.WWAN, 20, 50, 0, 0, 0, 0} + }) + + Name(TRTA, Package() // TRT package when TFN1 is at 50% speed + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TPCH, 30, 20, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.TCPU, 36, 50, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.TMEM, 10, 100, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 36, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TMEM, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.TCPU, 3, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.B0D4, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.TMEM, 44, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TSKN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TAMB, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.T_VR, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TEFN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.TMEM, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.TCPU, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.WWAN, 20, 50, 0, 0, 0, 0} + }) + + Name(TRT9, Package() // TRT package when TFN1 is at 55% speed + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TPCH, 30, 20, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.TCPU, 34, 50, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.TMEM, 10, 100, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 34, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TMEM, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.TCPU, 3, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.B0D4, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.TMEM, 44, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TSKN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TAMB, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.T_VR, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TEFN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.TMEM, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.TCPU, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.WWAN, 20, 50, 0, 0, 0, 0} + }) + + Name(TRT8, Package() // TRT package when TFN1 is at 60% speed + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TPCH, 30, 20, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.TCPU, 32, 50, 8, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.TMEM, 10, 100, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 32, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TMEM, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.TCPU, 3, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.B0D4, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.TMEM, 44, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TSKN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TAMB, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.T_VR, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TEFN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.TMEM, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.TCPU, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.WWAN, 20, 50, 0, 0, 0, 0} + }) + + Name(TRT7, Package() // TRT package when TFN1 is at 65% speed + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TPCH, 30, 20, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.TCPU, 30, 50, 7, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.TMEM, 10, 100, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 30, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TMEM, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.TCPU, 3, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.B0D4, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.TMEM, 44, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TSKN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TAMB, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.T_VR, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TEFN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.TMEM, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.TCPU, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.WWAN, 20, 50, 0, 0, 0, 0} + }) + + Name(TRT6, Package() // TRT package when TFN1 is at 70% speed + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TPCH, 30, 20, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.TCPU, 28, 50, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.TMEM, 10, 100, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 28, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TMEM, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.TCPU, 3, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.B0D4, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.TMEM, 44, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TSKN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TAMB, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.T_VR, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TEFN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.TMEM, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.TCPU, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.WWAN, 20, 50, 0, 0, 0, 0} + }) + + Name(TRT5, Package() // TRT package when TFN1 is at 75% speed + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TPCH, 30, 20, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.TCPU, 26, 50, 5, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.TMEM, 10, 100, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 26, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TMEM, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.TCPU, 3, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.B0D4, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.TMEM, 44, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TSKN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TAMB, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.T_VR, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TEFN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.TMEM, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.TCPU, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.WWAN, 20, 50, 0, 0, 0, 0} + }) + + Name(TRT4, Package() // TRT package when TFN1 is at 80% speed + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TPCH, 30, 20, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.TCPU, 24, 50, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.TMEM, 10, 100, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 24, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TMEM, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.TCPU, 3, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.B0D4, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.TMEM, 44, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TSKN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TAMB, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.T_VR, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TEFN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.TMEM, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.TCPU, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.WWAN, 20, 50, 0, 0, 0, 0} + }) + + Name(TRT3, Package() // TRT package when TFN1 is at 85% speed + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TPCH, 30, 20, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.TCPU, 22, 50, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.TMEM, 10, 100, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 22, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TMEM, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.TCPU, 3, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.B0D4, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.TMEM, 44, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TSKN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TAMB, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.T_VR, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TEFN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.TMEM, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.TCPU, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.WWAN, 20, 50, 0, 0, 0, 0} + }) + + Name(TRT2, Package() // TRT package when TFN1 is at 90% speed + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TPCH, 30, 20, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.TCPU, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.TMEM, 10, 100, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 21, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TMEM, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.TCPU, 3, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.B0D4, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.TMEM, 44, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TSKN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TAMB, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.T_VR, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TEFN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.TMEM, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.TCPU, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.WWAN, 20, 50, 0, 0, 0, 0} + }) + + Name(TRT1, Package() // TRT package when TFN1 is at 95% speed + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TPCH, 30, 20, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.TCPU, 18, 50, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.TMEM, 10, 100, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TMEM, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.TCPU, 3, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.B0D4, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.TMEM, 44, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TSKN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TAMB, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.T_VR, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TEFN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.TMEM, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.TCPU, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.WWAN, 20, 50, 0, 0, 0, 0} + }) + + Name(TRT0, Package() // TRT package when TFN1 is at 100% speed + { + // Source Target Influence Period Reserved + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TPCH, 30, 20, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.TCPU, 16, 50, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.TMEM, 10, 100, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.TCPU, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 18, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.TMEM, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TAMB, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.T_VR, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.LPCB.H_EC.TEFN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.TCPU, 3, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.B0D4, 30, 100, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.TMEM, 44, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TSKN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TAMB, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.T_VR, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.LPCB.H_EC.TEFN, 1, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.TMEM, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.TCPU, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.LPCB.H_EC.TSKN, 20, 50, 0, 0, 0, 0}, + Package(){\_SB.PCI0.B0D4, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.TMEM, \_SB.PCI0.WWAN, 20, 200, 0, 0, 0, 0}, + Package(){\_SB.PCI0.DPLY, \_SB.PCI0.WWAN, 20, 50, 0, 0, 0, 0} + }) + + // TRTR (Thermal Relationship Table Revision) + // + // This object evaluates to an integer value that defines the revision of the _TRT object. + // + // Arguments: (0) + // None + // Return Value: + // 0: Traditional TRT as defined by the ACPI Specification. + // 1: Priority based TRT + // + Method(TRTR) + { + Return(TRTV) + } + + // _TRT (Thermal Relationship Table) + // + // Arguments: (0) + // None + // Return Value: + // A variable-length Package containing a list of Thermal Relationship Packages as described below. + // + // Return Value Information + // Package { + // ThermalRelationship[0] // Package + // ... + // ThermalRelationship[n] // Package + // } + // + Method(_TRT,,,,PkgObj) + { + If(\ECON) + { + If(\_SB.PCI0.LPCB.H_EC.CFAN) // CFAN Holds On/Off information + { + If(LEqual(\_SB.PCI0.LPCB.H_EC.PENV, 0)) // PENV holds duty cycle in percent + { + Return(TRTI) + } + + If(LLessEqual(\_SB.PCI0.LPCB.H_EC.PENV, 15)) // PENV holds duty cycle in percent + { + Return(TRTH) + } + + If(LLessEqual(\_SB.PCI0.LPCB.H_EC.PENV, 20)) + { + Return(TRTG) + } + + If(LLessEqual(\_SB.PCI0.LPCB.H_EC.PENV, 25)) + { + Return(TRTF) + } + + If(LLessEqual(\_SB.PCI0.LPCB.H_EC.PENV, 30)) + { + Return(TRTE) + } + + If(LLessEqual(\_SB.PCI0.LPCB.H_EC.PENV, 35)) + { + Return(TRTD) + } + + If(LLessEqual(\_SB.PCI0.LPCB.H_EC.PENV, 40)) + { + Return(TRTC) + } + + If(LLessEqual(\_SB.PCI0.LPCB.H_EC.PENV, 45)) + { + Return(TRTB) + } + + If(LLessEqual(\_SB.PCI0.LPCB.H_EC.PENV, 50)) + { + Return(TRTA) + } + + If(LLessEqual(\_SB.PCI0.LPCB.H_EC.PENV, 55)) + { + Return(TRT9) + } + + If(LLessEqual(\_SB.PCI0.LPCB.H_EC.PENV, 60)) + { + Return(TRT8) + } + + If(LLessEqual(\_SB.PCI0.LPCB.H_EC.PENV, 65)) + { + Return(TRT7) + } + + If(LLessEqual(\_SB.PCI0.LPCB.H_EC.PENV, 70)) + { + Return(TRT6) + } + + If(LLessEqual(\_SB.PCI0.LPCB.H_EC.PENV, 75)) + { + Return(TRT5) + } + + If(LLessEqual(\_SB.PCI0.LPCB.H_EC.PENV, 80)) + { + Return(TRT4) + } + + If(LLessEqual(\_SB.PCI0.LPCB.H_EC.PENV, 85)) + { + Return(TRT3) + } + + If(LLessEqual(\_SB.PCI0.LPCB.H_EC.PENV, 90)) + { + Return(TRT2) + } + + If(LLessEqual(\_SB.PCI0.LPCB.H_EC.PENV, 95)) + { + Return(TRT1) + } + + If(LLessEqual(\_SB.PCI0.LPCB.H_EC.PENV, 100)) + { + Return(TRT0) + } + } + } + + Return(TRTI) // Return 0% State TRT by default + } // End _TRT +} diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/WWANDppmPolicy.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/WWANDppmPolicy.asl new file mode 100644 index 0000000..d827eed --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/WWANDppmPolicy.asl @@ -0,0 +1,140 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + WWANDppmPolicy.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0.WWAN) +{ + Name(CTYP,0) // Device-specific cooling policy preference + + // _SCP (Set Cooling Policy) + // + // Arguments: (3) + // Arg0 - Mode An Integer containing the cooling mode policy code + // Arg1 - AcousticLimit An Integer containing the acoustic limit + // Arg2 - PowerLimit An Integer containing the power limit + // Return Value: + // None + // + // Argument Information: + // Mode - 0 = Active, 1 = Passive + // Acoustic Limit - Specifies the maximum acceptable acoustic level that active cooling devices may generate. + // Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance. + // Power Limit - Specifies the maximum acceptable power level that active cooling devices may consume. + // Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool. + // + Method(_SCP, 3, Serialized) + { + If(LOr(LEqual(Arg0,0),LEqual(Arg0,1))) + { + Store(Arg0, CTYP) + P8XH(0, Arg1) + P8XH(1, Arg2) + Notify(\_SB.PCI0.WWAN, 0x91) + } + } + + // _ACx (Active Cooling) + // + // This optional object, if present under a thermal zone, returns the + // temperature trip point at which OSPM must start or stop Active cooling, + // where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the active cooling temperature threshold in tenths of degrees Kelvin + // + Method(_AC0) + { + If(CTYP) + { + Store(\_SB.IETM.CTOK(WWPT),Local1) // Passive Cooling Policy + } Else { + Store(\_SB.IETM.CTOK(WWAT),Local1) // Active Cooling Policy + } + If(LGreater(LSTM,Local1)) + { + Return(Subtract(Local1,GTSH)) // subtract 2 degrees which is the Hysteresis + } + Else + { + Return(Local1) + } + } + + // _CRT (Critical Temperature) + // + // This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the critical temperature threshold in tenths of degrees Kelvin + // + Method(_CRT, 0, Serialized) + { + Return(\_SB.IETM.CTOK(WWCT)) + } + + // _HOT (Hot Temperature) + // + // This optional object, when defined under a thermal zone, returns the critical temperature + // at which OSPM may choose to transition the system into the S4 sleeping state. + // + // Arguments: (0) + // None + // Return Value: + // The return value is an integer that represents the critical sleep threshold tenths of degrees Kelvin. + // + Method(_HOT,0,Serialized) + { + Return(\_SB.IETM.CTOK(WWHT)) + } + + // _PSV (Passive) + // + // This optional object, if present under a thermal zone, evaluates to the temperature + // at which OSPM must activate passive cooling policy. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the passive cooling temperature threshold in tenths of degrees Kelvin + // + Method(_PSV, 0, Serialized) + { + If(CTYP) + { + Return(\_SB.IETM.CTOK(WWAT)) // Active Cooling Policy + } Else { + Return(\_SB.IETM.CTOK(WWPT)) // Passive Cooling Policy + } + } + +} // End Scope(\_SB.PCI0.WWAN) diff --git a/ReferenceCode/AcpiTables/Dptf/AcpiTables/WWANParticipant.asl b/ReferenceCode/AcpiTables/Dptf/AcpiTables/WWANParticipant.asl new file mode 100644 index 0000000..600939a --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/AcpiTables/WWANParticipant.asl @@ -0,0 +1,104 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + WWANParticipant.asl + +Abstract: + + Intel ACPI Reference Code for Dynamic Platform & Thermal Framework + +--*/ + +Scope(\_SB.PCI0) +{ + + Device(WWAN) // WWAN temperature sensor + { + Name(_HID, EISAID("INT3408")) + Name(_UID, 1) + Name(_STR, Unicode("Intel DPTF WWAN Participant")) + Name(PTYP, 0x0F) + + + // _STA (Status) + // + // This object returns the current status of a device. + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing a device status bitmap: + // Bit 0 - Set if the device is present. + // Bit 1 - Set if the device is enabled and decoding its resources. + // Bit 2 - Set if the device should be shown in the UI. + // Bit 3 - Set if the device is functioning properly (cleared if device failed its diagnostics). + // Bit 4 - Set if the battery is present. + // Bits 5-31 - Reserved (must be cleared). + // + Method(_STA) + { + If (LEqual(WAND,1)){ + Return(0x0F) + } Else { + Return(0x00) + } + } + + // Thermal Sensor Hysteresis, 2 degrees + Name(GTSH, 20) + + Name(LSTM,0) // Last temperature reported + + // _DTI (Device Temperature Indication) + // + // Conveys the temperature of a device's internal temperature sensor to the platform when a temperature trip point + // is crossed or when a meaningful temperature change occurs. + // + // Arguments: (1) + // Arg0 - An Integer containing the current value of the temperature sensor (in tenths Kelvin) + // Return Value: + // None + // + Method(_DTI, 1) + { + Store(Arg0,LSTM) + Notify(WWAN, 0x91) // notify the participant of a trip point change event + } + + // _NTT (Notification Temperature Threshold) + // + // Returns the temperature change threshold for devices containing native temperature sensors to cause + // evaluation of the _DTI object + // + // Arguments: (0) + // None + // Return Value: + // An Integer containing the temperature threshold in tenths of degrees Kelvin. + // + Method(_NTT, 0) + { + Return(2782) // 5 degree Celcius, this could be a platform policy with setup item + } + + } // end of Device(WWAN) +} // end of Scope(\_SB.PCI0) + diff --git a/ReferenceCode/AcpiTables/Dptf/Dptf.cif b/ReferenceCode/AcpiTables/Dptf/Dptf.cif new file mode 100644 index 0000000..6bdc49c --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/Dptf.cif @@ -0,0 +1,13 @@ +<component> + name = "Intel DPTF" + category = eModule + LocalRoot = "ReferenceCode\AcpiTables\Dptf\" + RefName = "Dptf" +[files] +"Dptf.sdl" +"ReleaseNotes.chm" +[parts] +"DptfDxe" +"DptfAcpiTables" +"DptfGuidLib" +<endComponent> diff --git a/ReferenceCode/AcpiTables/Dptf/Dptf.sdl b/ReferenceCode/AcpiTables/Dptf/Dptf.sdl new file mode 100644 index 0000000..9786c10 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/Dptf.sdl @@ -0,0 +1,26 @@ +TOKEN + Name = Dptf_SUPPORT + Value = 1 + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Master = Yes + Help = "Main switch to enable Dptf support in Project" +End + +PATH + Name = "INTEL_DPTF_DIR" + Help = "Intel DPTF source directory" +End + +ELINK + Name = "DPTF_INCLUDES" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "/I$(INTEL_DPTF_DIR)" + Parent = "DPTF_INCLUDES" + InvokeOrder = AfterParent +End
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/Dptf/Dxe/Dptf.c b/ReferenceCode/AcpiTables/Dptf/Dxe/Dptf.c new file mode 100644 index 0000000..caee0a7 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/Dxe/Dptf.c @@ -0,0 +1,440 @@ +/** @file + This DXE driver configures and supports Dptf. + +@copyright + Copyright (c) 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement + +**/ +#include "Dptf.h" + +ACPI_PLATFORM_POLICY_PROTOCOL *mAcpiPlatformPolicyProtocol; + +EFI_RUNTIME_SERVICES *gRT; + +/// +/// Driver entry point +/// +EFI_DRIVER_ENTRY_POINT (InitializeDptf) + +EFI_STATUS +InitializeDptf ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +/** +@brief + This procedure does all the DPTF initialization and loads the ACPI tables. + + @param[in] ImageHandle - The firmware allocated handle to the Driver Image + @param[in] SystemTable - Pointer to the EFI System Table + + @retval EFI_SUCCESS - The driver installed/initialized correctly. +**/ +{ + EFI_STATUS Status; + + gRT = SystemTable->RuntimeServices; + + /// + /// Initialize the EFI Runtime Library + /// + DxeInitializeDriverLib (ImageHandle, SystemTable); + + /// + /// S3 boot script + /// + INITIALIZE_SCRIPT (ImageHandle, SystemTable); + + /// + /// Locate platform configuration information and copy it to a global variable. + /// + Status = gBS->LocateProtocol ( + &gAcpiPlatformPolicyProtocolGuid, + NULL, + (VOID**) &mAcpiPlatformPolicyProtocol + ); + if (EFI_ERROR(Status)) { + DEBUG ((EFI_D_ERROR, "No ACPI Platform Policy Protocol available.")); + } else { + DEBUG ((EFI_D_INFO, "ACPI Platform Policy Protocol is loaded.")); + } + ASSERT_EFI_ERROR(Status); + + /// + /// Check if Dptf is enabled and load the ACPI SSDT. + /// + if (mAcpiPlatformPolicyProtocol->EnableDptf == 1) { + /// + /// Load the SSDT ACPI Tables. + /// + switch (mAcpiPlatformPolicyProtocol->BoardId) { + case 0x30: // BoardId for Ffrd + LoadAcpiTablesFfrd (); + break; + default: + LoadAcpiTables (); + } + } + + return EFI_SUCCESS; +} + +VOID +LoadAcpiTables( + VOID + ) +/** +@brief + This procedure loads the ACPI SSDT tables. + + @param[in] None + + @retval None + +**/ +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + UINTN Index; + EFI_FIRMWARE_VOLUME_PROTOCOL *FwVol; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + INTN Instance; + EFI_ACPI_COMMON_HEADER *Table; + UINTN Size; + EFI_FV_FILETYPE FileType; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINT32 FvStatus; + EFI_ACPI_DESCRIPTION_HEADER *TableHeader; + UINTN TableHandle; + EFI_ACPI_TABLE_VERSION Version; + BOOLEAN LoadTable; + + FwVol = NULL; + Table = NULL; + + /// + /// Locate FV protocol. + /// + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolumeProtocolGuid, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Look for FV with ACPI storage file + /// + for (Index = 0; Index < NumberOfHandles; Index++) { + + /// + /// Get the protocol on this handle + /// This should not fail because of LocateHandleBuffer + /// + Status = gBS->HandleProtocol ( + HandleBuffer[Index], + &gEfiFirmwareVolumeProtocolGuid, + (VOID **) &FwVol + ); + ASSERT_EFI_ERROR (Status); + + if ((Status == EFI_SUCCESS) && (FwVol != NULL)) { + /// + /// See if it has the ACPI storage file + /// + Size = 0; + FvStatus = 0; + Status = FwVol->ReadFile ( + FwVol, + &gDptfAcpiTableStorageGuid, + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + /// + /// If we found it, then we are done + /// + if (Status == EFI_SUCCESS) { + break; + } + } + } + + /// + /// Our exit status is determined by the success of the previous operations + /// If the protocol was found, Instance already points to it. + /// + /// Free any allocated buffers + /// + FreePool (HandleBuffer); + + /// + /// Sanity check that we found our data file + /// + ASSERT (FwVol); + if (FwVol == NULL) { + return; + } + + /// + /// By default, a table belongs in all ACPI table versions published. + /// + Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0; + + /// + /// Find the Table protocol + /// + Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable); + + /// + /// Read tables from the storage file. + /// + Instance = 0; + + while (Status == EFI_SUCCESS) { + /// + /// Read the ACPI tables + /// + Status = FwVol->ReadSection ( + FwVol, + &gDptfAcpiTableStorageGuid, + EFI_SECTION_RAW, + Instance, + (VOID **) &Table, + &Size, + &FvStatus + ); + + if (!EFI_ERROR (Status)) { + + LoadTable = FALSE; + TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table; + + switch (((EFI_ACPI_DESCRIPTION_HEADER*) TableHeader)->OemTableId) { + + case EFI_SIGNATURE_64 ('D', 'p', 't', 'f', 'T', 'a', 'b', 'l'): + /// + /// This is Dptf SSDT. Dptf should be enabled if we reach here so load the table. + /// + LoadTable = TRUE; + DEBUG ((EFI_D_INFO, "Found Dptf SSDT signature.")); + break; + + default: + break; + } + + /// + /// Add the table + /// + if (LoadTable) { + TableHandle = 0; + Status = AcpiTable->InstallAcpiTable ( + AcpiTable, + Table, + Table->Length, + &TableHandle + ); + } + + /// + /// Increment the instance + /// + Instance++; + Table = NULL; + } + } +} + +VOID +LoadAcpiTablesFfrd( + VOID + ) +/** +@brief + This procedure loads the ACPI SSDT tables. + + @param[in] None + + @retval None + +**/ +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + UINTN Index; + EFI_FIRMWARE_VOLUME_PROTOCOL *FwVol; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + INTN Instance; + EFI_ACPI_COMMON_HEADER *Table; + UINTN Size; + EFI_FV_FILETYPE FileType; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINT32 FvStatus; + EFI_ACPI_DESCRIPTION_HEADER *TableHeader; + UINTN TableHandle; + EFI_ACPI_TABLE_VERSION Version; + BOOLEAN LoadTable; + + FwVol = NULL; + Table = NULL; + + /// + /// Locate FV protocol. + /// + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolumeProtocolGuid, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Look for FV with ACPI storage file + /// + for (Index = 0; Index < NumberOfHandles; Index++) { + + /// + /// Get the protocol on this handle + /// This should not fail because of LocateHandleBuffer + /// + Status = gBS->HandleProtocol ( + HandleBuffer[Index], + &gEfiFirmwareVolumeProtocolGuid, + (VOID **) &FwVol + ); + ASSERT_EFI_ERROR (Status); + + if ((Status == EFI_SUCCESS) && (FwVol != NULL)) { + /// + /// See if it has the ACPI storage file + /// + Size = 0; + FvStatus = 0; + Status = FwVol->ReadFile ( + FwVol, + &gDptfAcpiTableStorageGuidFfrd, + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + /// + /// If we found it, then we are done + /// + if (Status == EFI_SUCCESS) { + break; + } + } + } + + /// + /// Our exit status is determined by the success of the previous operations + /// If the protocol was found, Instance already points to it. + /// + /// Free any allocated buffers + /// + FreePool (HandleBuffer); + + /// + /// Sanity check that we found our data file + /// + ASSERT (FwVol); + if (FwVol == NULL) { + return; + } + + /// + /// By default, a table belongs in all ACPI table versions published. + /// + Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0; + + /// + /// Find the Table protocol + /// + Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable); + + /// + /// Read tables from the storage file. + /// + Instance = 0; + + while (Status == EFI_SUCCESS) { + /// + /// Read the ACPI tables + /// + Status = FwVol->ReadSection ( + FwVol, + &gDptfAcpiTableStorageGuidFfrd, + EFI_SECTION_RAW, + Instance, + (VOID **) &Table, + &Size, + &FvStatus + ); + + if (!EFI_ERROR (Status)) { + + LoadTable = FALSE; + TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table; + + switch (((EFI_ACPI_DESCRIPTION_HEADER*) TableHeader)->OemTableId) { + + case EFI_SIGNATURE_64 ('D', 'p', 't', 'f', 'F', 'f', 'r', 'd'): + /// + /// This is Dptf SSDT. Dptf should be enabled if we reach here so load the table. + /// + LoadTable = TRUE; + DEBUG ((EFI_D_INFO, "Found Dptf SSDT signature.")); + break; + + default: + break; + } + + /// + /// Add the table + /// + if (LoadTable) { + TableHandle = 0; + Status = AcpiTable->InstallAcpiTable ( + AcpiTable, + Table, + Table->Length, + &TableHandle + ); + } + + /// + /// Increment the instance + /// + Instance++; + Table = NULL; + } + } +} diff --git a/ReferenceCode/AcpiTables/Dptf/Dxe/Dptf.dxs b/ReferenceCode/AcpiTables/Dptf/Dxe/Dptf.dxs new file mode 100644 index 0000000..3804c02 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/Dxe/Dptf.dxs @@ -0,0 +1,33 @@ +/** @file + Dependency expression source file. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement + +**/ + + +#include "EfiDepex.h" +#include EFI_PROTOCOL_DEPENDENCY (CpuIo) +#include EFI_PROTOCOL_DEPENDENCY (AcpiSupport) +#include EFI_PROTOCOL_DEPENDENCY (AcpiPlatformPolicy) + +DEPENDENCY_START + EFI_CPU_IO_PROTOCOL_GUID AND + EFI_ACPI_SUPPORT_GUID AND + ACPI_PLATFORM_POLICY_PROTOCOL_GUID +DEPENDENCY_END diff --git a/ReferenceCode/AcpiTables/Dptf/Dxe/Dptf.h b/ReferenceCode/AcpiTables/Dptf/Dxe/Dptf.h new file mode 100644 index 0000000..8f66020 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/Dxe/Dptf.h @@ -0,0 +1,196 @@ +/** @file + Header file for the Dptf driver. + +@copyright + Copyright (c) 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ + +#ifndef _DPTF_H_ +#define _DPTF_H_ + +#include "EdkIIGlueBase.h" +#include "EdkIIGlueDxe.h" +#include "EdkIIGluePcd.h" +#include "Acpi.h" +#include "CpuIA32.h" +#include "EfiScriptLib.h" +#include "SaAccess.h" + +/// +/// Consumed protocols +/// +#include EFI_PROTOCOL_DEPENDENCY (AcpiTable) +#include EFI_PROTOCOL_DEPENDENCY (FirmwareVolume) +#include EFI_PROTOCOL_CONSUMER (PciRootBridgeIo) +#include EFI_PROTOCOL_DEFINITION (AcpiPlatformPolicy) + +#ifndef DPTF_BASE_ADDRESS +#define DPTF_BASE_ADDRESS 0xFED98000 +#endif +#ifndef DPTF_LENGTH +#define DPTF_LENGTH 0x8000 +#endif + +/// +/// SSDT data storage file +/// +#include "DptfAcpiTableStorage.h" + +/// +/// AML parsing definitions +/// +#define AML_METHOD_OP 0x14 + +/// +/// MSR definitions +/// +#define MSR_PLATFORM_INFO 0xCE + #define CONFIG_TDP_NUM_LEVELS_OFFSET 33 + #define CONFIG_TDP_NUM_LEVELS_MASK (0x3 << 1) // Bits 34:33 + #define LOW_POWER_MODE_OFFSET 32 + #define LOW_POWER_MODE_MASK 0x1 + +/// +/// UINT64 workaround +/// +/// The MS compiler doesn't handle QWORDs very well. I'm breaking +/// them into DWORDs to circumvent the problems. Converting back +/// shouldn't be a big deal. +/// +#pragma pack(1) +typedef union _MSR_REGISTER { + UINT64 Qword; + + struct _DWORDS { + UINT32 Low; + UINT32 High; + } Dwords; + + struct _BYTES { + UINT8 FirstByte; + UINT8 SecondByte; + UINT8 ThirdByte; + UINT8 FouthByte; + UINT8 FifthByte; + UINT8 SixthByte; + UINT8 SeventhByte; + UINT8 EighthByte; + } Bytes; + +} MSR_REGISTER; +#pragma pack() + +/// +/// register definitions +/// +#define MCHBAR (0x48) +#define MCHBAR_MCHBAR_MASK 0x7fffff8000 + +#define TMBAR (0x10) + +#ifndef BIT63 +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 +#define BIT32 0x100000000 +#define BIT33 0x200000000 +#define BIT34 0x400000000 +#define BIT35 0x800000000 +#define BIT36 0x1000000000 +#define BIT37 0x2000000000 +#define BIT38 0x4000000000 +#define BIT39 0x8000000000 +#define BIT40 0x10000000000 +#define BIT41 0x20000000000 +#define BIT42 0x40000000000 +#define BIT43 0x80000000000 +#define BIT44 0x100000000000 +#define BIT45 0x200000000000 +#define BIT46 0x400000000000 +#define BIT47 0x800000000000 +#define BIT48 0x1000000000000 +#define BIT49 0x2000000000000 +#define BIT50 0x4000000000000 +#define BIT51 0x8000000000000 +#define BIT52 0x10000000000000 +#define BIT53 0x20000000000000 +#define BIT54 0x40000000000000 +#define BIT55 0x80000000000000 +#define BIT56 0x100000000000000 +#define BIT57 0x200000000000000 +#define BIT58 0x400000000000000 +#define BIT59 0x800000000000000 +#define BIT60 0x1000000000000000 +#define BIT61 0x2000000000000000 +#define BIT62 0x4000000000000000 +#define BIT63 0x8000000000000000 +#endif + +#define MmPciExpressAddress(Segment, Bus, Device, Function, Register) \ + ( (UINTN) (PciRead32 (PCI_LIB_ADDRESS (0,0,0,0x60)) & 0xFC000000) + \ + (UINTN) (Bus << 20) + \ + (UINTN) (Device << 15) + \ + (UINTN) (Function << 12) + \ + (UINTN) (Register) \ + ) + +EFI_STATUS +InitializeDptf ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +VOID +LoadAcpiTables( + VOID + ); + +VOID +LoadAcpiTablesFfrd( + VOID + ); + +#endif diff --git a/ReferenceCode/AcpiTables/Dptf/Dxe/Dptf.inf b/ReferenceCode/AcpiTables/Dptf/Dxe/Dptf.inf new file mode 100644 index 0000000..1de1ee6 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/Dxe/Dptf.inf @@ -0,0 +1,83 @@ +## @file +# Component description file for Dptf module +# +#@copyright +# Copyright (c) 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# + + +[defines] +BASE_NAME = Dptf +FILE_GUID = 918ABA30-3D8D-4bb5-B849-45CC4FC7DE7C +COMPONENT_TYPE = RT_DRIVER + +[sources.common] + Dptf.h + Dptf.c + +[includes.common] + $(EFI_SOURCE)/$(PROJECT_ACPI_ROOT) + $(EFI_SOURCE)/$(PROJECT_ACPI_ROOT)/Dptf + $(EFI_SOURCE)/$(PROJECT_ACPI_ROOT)/Dptf/Guid/AcpiTableStorage + . + $(EDK_SOURCE)/Sample/Chipset/PcCompatible + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Framework/Include + $(EDK_SOURCE)/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Core/Dxe/ArchProtocol/Cpu + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EFI_SOURCE) + $(EFI_SOURCE)/Framework + $(EFI_SOURCE)/Include + $(EFI_SOURCE)/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Pcd + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Library + $(EDK_SOURCE)/Foundation/Cpu/Pentium/Include + $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include + +[libraries.common] + EdkIIGlueDxeReportStatusCodeLib + EdkIIGlueDxeDebugLibReportStatusCode + EdkProtocolLib + EfiProtocolLib + EfiDriverLib + ArchProtocolLib + EdkFrameworkProtocolLib + EdkIIGlueBasePciExpressLib + EdkIIGlueUefiBootServicesTableLib + EdkIIGlueUefiLib + EdkIIGlueBaseLib + EfiScriptLib + AcpiProtocolLib + DptfGuidLib + +[nmake.common] + IMAGE_ENTRY_POINT = InitializeDptf + DPX_SOURCE = Dptf.dxs +# +# Module Entry Point +# + C_FLAGS = $(C_FLAGS) -D"__EDKII_GLUE_MODULE_ENTRY_POINT__=InitializeDptf" \ + -D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \ + -D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ diff --git a/ReferenceCode/AcpiTables/Dptf/Dxe/DptfDxe.cif b/ReferenceCode/AcpiTables/Dptf/Dxe/DptfDxe.cif new file mode 100644 index 0000000..78cbeda --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/Dxe/DptfDxe.cif @@ -0,0 +1,13 @@ +<component> + name = "DptfDxe" + category = ModulePart + LocalRoot = "ReferenceCode\AcpiTables\Dptf\Dxe\" + RefName = "DptfDxe" +[files] +"DptfDxe.sdl" +"DptfDxe.mak" +"Dptf.c" +"Dptf.dxs" +"Dptf.h" +"Dptf.inf" +<endComponent> diff --git a/ReferenceCode/AcpiTables/Dptf/Dxe/DptfDxe.mak b/ReferenceCode/AcpiTables/Dptf/Dxe/DptfDxe.mak new file mode 100644 index 0000000..1a0ac0a --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/Dxe/DptfDxe.mak @@ -0,0 +1,106 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2012, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/DPTF/DptfDxe/DptfDxe.mak 2 9/26/12 2:00a Victortu $ +# +# $Revision: 2 $ +# +# $Date: 9/26/12 2:00a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/DPTF/DptfDxe/DptfDxe.mak $ +# +# 2 9/26/12 2:00a Victortu +# +# 1 4/24/12 9:25a Victortu +# Intel DPTF initialization. +# +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: DptfDxe.mak +# +# Description: MAke file to build Intel DPTF components +# +#<AMI_FHDR_END> +#************************************************************************* +EDK : DptfDxe + +DptfDxe : $(BUILD_DIR)\DptfDxe.mak DptfDxeBin + +DptfDxe_OBJECTS = \ +$(BUILD_DIR)\$(INTEL_DPTF_DXE_DIR)\Dptf.obj + +$(BUILD_DIR)\DptfDxe.mak : $(INTEL_DPTF_DXE_DIR)\$(@B).cif $(INTEL_DPTF_DXE_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(INTEL_DPTF_DXE_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +DptfDxe_LIBS =\ + $(EDKPROTOCOLLIB)\ + $(EFIPROTOCOLLIB)\ + $(ARCHPROTOCOLLIB)\ + $(EDKFRAMEWORKPROTOCOLLIB)\ + $(EFISCRIPTLIB)\ + $(EdkIIGlueBaseLib_LIB)\ + $(EdkIIGlueBasePciExpressLib_LIB)\ + $(EdkIIGlueUefiBootServicesTableLib_LIB)\ + $(EdkIIGlueUefiLib_LIB)\ +!IF "$(x64_BUILD)"=="1" + $(EdkIIGlueBaseLibX64_LIB)\ +!ELSE + $(EdkIIGlueBaseLibIA32_LIB)\ +!ENDIF + $(EdkIIGlueDxeReportStatusCodeLib_LIB)\ + $(EdkIIGlueDxeServicesTableLib_LIB)\ + $(EdkIIGlueDxeDebugLibReportStatusCode_LIB)\ + $(EdkIIGlueDxeHobLib_LIB)\ + $(EFIDRIVERLIB)\ + $(AcpiProtocolLib_LIB)\ + $(DptfGuidLib_LIB)\ + +DptfDxe_INCLUDES= $(EDK_INCLUDES)\ + $(IndustryStandard_INCLUDES)\ + $(EdkIIGlueLib_INCLUDES)\ + $(DPTF_INCLUDES)\ + /I ReferenceCode\AcpiTables\ + /I$(ArchProtocolLib_DIR)\Cpu\ + /I$(INTEL_SYSTEM_AGENT_DIR)\Include\ + +DptfDxeBin: $(DptfDxe_LIBS) + $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\ + /f $(BUILD_DIR)\DptfDxe.mak all \ + NAME=DptfDxe\ + MAKEFILE=$(BUILD_DIR)\DptfDxe.mak \ + "MY_INCLUDES=$(DptfDxe_INCLUDES)"\ + GUID=918ABA30-3D8D-4bb5-B849-45CC4FC7DE7C\ + ENTRY_POINT=InitializeDptf \ + TYPE=RT_DRIVER\ + "OBJECTS=$(DptfDxe_OBJECTS)"\ + DEPEX1=$(INTEL_DPTF_DXE_DIR)\Dptf.dxs\ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\ + COMPRESS=1 +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2012, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/Dptf/Dxe/DptfDxe.sdl b/ReferenceCode/AcpiTables/Dptf/Dxe/DptfDxe.sdl new file mode 100644 index 0000000..03960e9 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/Dxe/DptfDxe.sdl @@ -0,0 +1,30 @@ +TOKEN + Name = DptfDxe_SUPPORT + Value = 1 + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable DptfDxe support in Project" +End + +MODULE + Help = "Includes DptfDxe.mak to Project" + File = "DptfDxe.mak" +End + +PATH + Name = "INTEL_DPTF_DXE_DIR" +End + +ELINK + Name = "/I$(INTEL_DPTF_DXE_DIR)" + Parent = "DPTF_INCLUDES" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(BUILD_DIR)\DptfDxe.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End diff --git a/ReferenceCode/AcpiTables/Dptf/Guid/AcpiTableStorage/DptfAcpiTableStorage.c b/ReferenceCode/AcpiTables/Dptf/Guid/AcpiTableStorage/DptfAcpiTableStorage.c new file mode 100644 index 0000000..35552e2 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/Guid/AcpiTableStorage/DptfAcpiTableStorage.c @@ -0,0 +1,34 @@ +/** @file + The GUID definition for Dptf ACPI table storage file name + +@copyright + Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ + +#include "EdkIIGlueDxe.h" +#include "DptfAcpiTableStorage.h" + +/// +/// Protocol GUID definition +/// +EFI_GUID gDptfAcpiTableStorageGuid = DPTF_ACPI_TABLE_STORAGE_GUID; +EFI_GUID gDptfAcpiTableStorageGuidFfrd = DPTF_ACPI_TABLE_STORAGE_GUID_FFRD; + +/// +/// Protocol description string +/// +EFI_GUID_STRING (&gDptfAcpiTableStorageGuid, "Dynamic Platform Thermal Framework ACPI Table Storage File Name", "Dynamic Platform Thermal Framework ACPI Table Storage file name GUID"); diff --git a/ReferenceCode/AcpiTables/Dptf/Guid/AcpiTableStorage/DptfAcpiTableStorage.h b/ReferenceCode/AcpiTables/Dptf/Guid/AcpiTableStorage/DptfAcpiTableStorage.h new file mode 100644 index 0000000..a5330a0 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/Guid/AcpiTableStorage/DptfAcpiTableStorage.h @@ -0,0 +1,35 @@ +/** @file + GUID definition for the Dptf ACPI table storage file name + +@copyright + Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ + +#ifndef _DPTF_ACPI_TABLE_STORAGE_H_ +#define _DPTF_ACPI_TABLE_STORAGE_H_ + +#define DPTF_ACPI_TABLE_STORAGE_GUID \ + { 0xea139578, 0xfea0, 0x4dd2, 0x91, 0xb5, 0x69, 0x53, 0x81, 0x9e, 0xf1, 0xe4 } + +extern EFI_GUID gDptfAcpiTableStorageGuid; + +#define DPTF_ACPI_TABLE_STORAGE_GUID_FFRD \ + { 0x2820908b, 0x87f6, 0x446b, 0xa1, 0x0, 0x74, 0xee, 0xe3, 0x6e, 0x29, 0x18 } + +extern EFI_GUID gDptfAcpiTableStorageGuidFfrd; + +#endif diff --git a/ReferenceCode/AcpiTables/Dptf/Guid/DptfGuidLib.cif b/ReferenceCode/AcpiTables/Dptf/Guid/DptfGuidLib.cif new file mode 100644 index 0000000..f888fb6 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/Guid/DptfGuidLib.cif @@ -0,0 +1,12 @@ +<component> + name = "DptfGuidLib" + category = ModulePart + LocalRoot = "ReferenceCode\AcpiTables\Dptf\Guid\" + RefName = "DptfGuidLib" +[files] +"DptfGuidLib.sdl" +"DptfGuidLib.mak" +"DptfGuidLib.inf" +"AcpiTableStorage\DptfAcpiTableStorage.c" +"AcpiTableStorage\DptfAcpiTableStorage.h" +<endComponent> diff --git a/ReferenceCode/AcpiTables/Dptf/Guid/DptfGuidLib.inf b/ReferenceCode/AcpiTables/Dptf/Guid/DptfGuidLib.inf new file mode 100644 index 0000000..7d800c8 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/Guid/DptfGuidLib.inf @@ -0,0 +1,55 @@ +## @file +# Component description file. +# +#@copyright +# Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# + +[defines] +BASE_NAME = DptfGuidLib +COMPONENT_TYPE = LIBRARY + +[sources.common] + AcpiTableStorage/DptfAcpiTableStorage.c + AcpiTableStorage/DptfAcpiTableStorage.h + +[includes.common] + . + $(EFI_SOURCE) + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Framework/Include + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EFI_SOURCE)/$(PROJECT_ACPI_ROOT)-Dptf +# +# Edk II Glue Library, some hearder are included by R9 header so have to include +# + + $(EFI_SOURCE) + $(EFI_SOURCE)/Framework + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + +[nmake.common] diff --git a/ReferenceCode/AcpiTables/Dptf/Guid/DptfGuidLib.mak b/ReferenceCode/AcpiTables/Dptf/Guid/DptfGuidLib.mak new file mode 100644 index 0000000..f1a7a22 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/Guid/DptfGuidLib.mak @@ -0,0 +1,69 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2012, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* + +# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/DPTF/DptfGuidLib/DptfGuidLib.mak 1 4/24/12 9:27a Victortu $ +# +# $Revision: 1 $ +# +# $Date: 4/24/12 9:27a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/DPTF/DptfGuidLib/DptfGuidLib.mak $ +# +# 1 4/24/12 9:27a Victortu +# +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: DptfGuidLib.mak +# +# Description: MAke file to build Intel DPTF GuidLib components +# +#<AMI_FHDR_END> +#************************************************************************* +all : DptfGuidLib + +$(DptfGuidLib_LIB) : DptfGuidLib + +DptfGuidLib : $(BUILD_DIR)\DptfGuidLib.mak DptfGuidLibBin + +$(BUILD_DIR)\DptfGuidLib.mak : $(INTEL_DPTF_GUIDLIB_DIR)\$(@B).cif $(INTEL_DPTF_GUIDLIB_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(INTEL_DPTF_GUIDLIB_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +DptfGuidLib_INCLUDES=\ + $(EDK_INCLUDES)\ + $(EdkIIGlueLib_INCLUDES) + +DptfGuidLibBin : + $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\ + /f $(BUILD_DIR)\DptfGuidLib.mak all\ + "MY_INCLUDES=$(DptfGuidLib_INCLUDES)" \ + TYPE=LIBRARY + +#********************************************************************** +#********************************************************************** +#** ** +#** (C)Copyright 1985-2012, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#********************************************************************** +#**********************************************************************
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/Dptf/Guid/DptfGuidLib.sdl b/ReferenceCode/AcpiTables/Dptf/Guid/DptfGuidLib.sdl new file mode 100644 index 0000000..ffd5a8b --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/Guid/DptfGuidLib.sdl @@ -0,0 +1,37 @@ +TOKEN + Name = DptfGuidLib_SUPPORT + Value = 1 + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable DptfGuidLib support in Project" +End + +MODULE + Help = "Includes DptfGuidLib.mak to Project" + File = "DptfGuidLib.mak" +End + +PATH + Name = "INTEL_DPTF_GUIDLIB_DIR" +End + +TOKEN + Name = "DptfGuidLib_LIB" + Value = "$(BUILD_DIR)\DptfGuidLib.lib" + TokenType = Expression + TargetMAK = Yes +End + +ELINK + Name = "/I$(INTEL_DPTF_GUIDLIB_DIR)" + Parent = "DPTF_INCLUDES" + InvokeOrder = AfterParent +End + +ELINK + Name = "/I$(INTEL_DPTF_GUIDLIB_DIR)\AcpiTableStorage" + Parent = "DPTF_INCLUDES" + InvokeOrder = AfterParent +End
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/Dptf/ReleaseNotes.chm b/ReferenceCode/AcpiTables/Dptf/ReleaseNotes.chm Binary files differnew file mode 100644 index 0000000..20ed9ac --- /dev/null +++ b/ReferenceCode/AcpiTables/Dptf/ReleaseNotes.chm diff --git a/ReferenceCode/AcpiTables/Dsdt/98_LINK.ASL b/ReferenceCode/AcpiTables/Dsdt/98_LINK.ASL new file mode 100644 index 0000000..b4b67be --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/98_LINK.ASL @@ -0,0 +1,628 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + + +// Use this information when determining the Possible IRQs that can be +// used in a given system. +// +// The following IRQs are always in use by legacy devices: +// 0 = System Timer +// 2 = 8259 PIC +// 8 = RTC +// 9 = SCI Interrupt (It may be used, we choose not to) +// 13 = Co-processor Error +// +// The following may be in use by legacy devices: +// 1 = If using PS/2 Keyboard +// 3 = If COMx Port Enabled and IRQ = 3 +// 4 = If COMx Port Enabled and IRQ = 4 +// 5 = If LPT Port Enabled and IRQ = 5 +// 6 = If FDC Enabled +// 7 = If LPT Port Enabled and IRQ = 7 +// 12 = If using PS/2 Mouse +// 14 = Primary IDE (If populated and in Compatibility Mode) +// 15 = Secondary IDE (If populated and in Compatibility Mode) +// +// The following will never be in use by legacy devices: +// 10 = Assign to PARC, PCRC, PERC, PGRC +// 11 = Assign to PBRC, PDRC, PFRC, PHRC + +Device(LNKA) // PARC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) // PCI Interrupt Link Device + + Name(_UID,1) // Unique to other Link Devices + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PARC,0x80,PARC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSA) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLA,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLA,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PARC,0x0F),IRQ0) + + Return(RTLA) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PARC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PARC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKB) // PBRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,2) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PBRC,0x80,PBRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSB) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLB,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLB,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PBRC,0x0F),IRQ0) + + Return(RTLB) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PBRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PBRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKC) // PCRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,3) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PCRC,0x80,PCRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSC) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLC,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLC,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PCRC,0x0F),IRQ0) + + Return(RTLC) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PCRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PCRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKD) // PDRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,4) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PDRC,0x80,PDRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSD) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLD,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLD,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PDRC,0x0F),IRQ0) + + Return(RTLD) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PDRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PDRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKE) // PERC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,5) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PERC,0x80,PERC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSE) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLE,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLE,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PERC,0x0F),IRQ0) + + Return(RTLE) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PERC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PERC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKF) // PFRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,6) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PFRC,0x80,PFRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSF) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLF,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLF,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PFRC,0x0F),IRQ0) + + Return(RTLF) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PFRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PFRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKG) // PGRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,7) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PGRC,0x80,PGRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSG) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLG,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLG,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PGRC,0x0F),IRQ0) + + Return(RTLG) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PGRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PGRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKH) // PHRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,8) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(PHRC,0x80,PHRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSH) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLH,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLH,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(PHRC,0x0F),IRQ0) + + Return(RTLH) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,PHRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(PHRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} diff --git a/ReferenceCode/AcpiTables/Dsdt/ALS.ASL b/ReferenceCode/AcpiTables/Dsdt/ALS.ASL new file mode 100644 index 0000000..517aa49 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/ALS.ASL @@ -0,0 +1,57 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + + +Device(ALSD) +{ + Name(_HID,"ACPI0008") + + Method(_STA,0) + { + If(LEqual(ALSE,2)) + { + Return(0x000B) // ALS Enabled. Don't show it in UI. + } + + Return(0x0000) // ALS Disabled. Hide it. + } + + Method(_ALI) + { + Return (Or(ShiftLeft(LHIH,8),LLOW)) + } + + Name(_ALR, Package() + { + Package() {70, 0}, + Package() {73, 10}, + Package() {85, 80}, + Package() {100, 300}, + Package() {150, 1000} + }) + +} diff --git a/ReferenceCode/AcpiTables/Dsdt/AcpiAsl.cif b/ReferenceCode/AcpiTables/Dsdt/AcpiAsl.cif new file mode 100644 index 0000000..4dfcbd6 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/AcpiAsl.cif @@ -0,0 +1,43 @@ +<component> + name = "AcpiAsl" + category = ModulePart + LocalRoot = "ReferenceCode\AcpiTables\Dsdt\" + RefName = "AcpiAsl" +[files] +"AcpiAsl.sdl" +"AcpiAsl.mak" +"Platform.asl" +"GloblNvs.asl" +"CPU.asl" +"THERMAL.ASL" +"PCI_DRC.ASL" +"Video.asl" +"PCIEDOCK.ASL" +"LpcB.asl" +"98_LINK.ASL" +"EC.ASL" +"ALS.ASL" +"Bat0Virt.asl" +"Bat1Real.asl" +"Bat2Real.asl" +"LPC_DEV.ASL" +"NAT_SIO.ASL" +"NAT_LPT.ASL" +"NAT_COM.ASL" +"SMSC1007_SIO.ASL" +"SMSC1007_COM.ASL" +"Gpe.asl" +"WPCN381U_SIO.asl" +"WPCN381U_COM.asl" +"WPCN381U_LPT.ASL" +"SMSC1000_SIO.asl" +"SMSC1000_COM.asl" +"SMSC1000_LPT.asl" +"DSDT.ASL" +"token.asl" +"H8S2113_SIO.ASL" +"Nfc.asl" +"wcam.asl" +[parts] +"AcpiAslWrap" +<endComponent> diff --git a/ReferenceCode/AcpiTables/Dsdt/AcpiAsl.mak b/ReferenceCode/AcpiTables/Dsdt/AcpiAsl.mak new file mode 100644 index 0000000..72b2e84 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/AcpiAsl.mak @@ -0,0 +1,39 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: AcpiAsl.mak +# +# Description: MAke file to build Aptio ACPI ASL components +# +# +#<AMI_FHDR_END> +#************************************************************************* + + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/AcpiTables/Dsdt/AcpiAsl.sdl b/ReferenceCode/AcpiTables/Dsdt/AcpiAsl.sdl new file mode 100644 index 0000000..a75ed2e --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/AcpiAsl.sdl @@ -0,0 +1,417 @@ +IODEVICE + Name = "System PS2 Keyboard Controller" + ASLfile = "core\em\acpi\PS2KB.asl" + ASLdeviceName = "PS2K" + GPEbit = 01dh + SleepNum = 03h + Token = "PCH_SKU" "=" "1" + Token = "CRB_SIO_SUPPORT" "=" "0" + Token = "VirtualSerial_SUPPORT" "=" "1" +End + +IODEVICE + Name = "System PS2 Mouse Controller" + ASLfile = "core\em\acpi\PS2MS.asl" + ASLdeviceName = "PS2M" + GPEbit = 01dh + SleepNum = 03h + Token = "PCH_SKU" "=" "1" + Token = "CRB_SIO_SUPPORT" "=" "0" + Token = "VirtualSerial_SUPPORT" "=" "1" +End + +IODEVICE + Name = "System PS2 Keyboard Controller" + ASLfile = "core\em\acpi\PS2KB.asl" + ASLdeviceName = "PS2K" + GPEbit = 01dh + SleepNum = 03h + Token = "PCH_SKU" "=" "1" + Token = "EC_H8SMC" "=" "1" + Token = "CRB_EC_SUPPORT" "=" "1" +End + +IODEVICE + Name = "System PS2 Mouse Controller" + ASLfile = "core\em\acpi\PS2MS.asl" + ASLdeviceName = "PS2M" + GPEbit = 01dh + SleepNum = 03h + Token = "PCH_SKU" "=" "1" + Token = "EC_H8SMC" "=" "1" + Token = "CRB_EC_SUPPORT" "=" "1" +End + +TOKEN + Name = "PlatformAcpiTables_SUPPORT" + Value = "1" + Help = "Main switch to enable SaAcpiTables support in Project" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Master = Yes +End + +TOKEN + Name = "TRTP" + Value = "0x01" + Help = "TRAP_TYPE_PPM" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "WDTE" + Value = "0x01" + Help = "WDT enabled" + TokenType = Integer + TargetASL = Yes + Token = "CougarPoint_SUPPORT" "=" "1" +End + +TOKEN + Name = "WDTE" + Value = "0x00" + Help = "WDT enabled" + TokenType = Integer + TargetASL = Yes + Token = "Ibexpeak_SUPPORT" "=" "1" +End + +TOKEN + Name = "TRTD" + Value = "0x02" + Help = "TRAP_TYPE_DTS" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "TRTI" + Value = "0x03" + Help = "TRAP_TYPE_IGD" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "PFTI" + Value = "0x04" + Help = "PFAT IO Trap flag" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "GCDD" + Value = "0x01" + Help = "SW_SMI_GET_CURRENT_DISPLAY_DEVICE" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "DSTA" + Value = "0x0A" + Help = "SW_SMI_DISPLAY_SWITCH_TOGGLE_ACPI" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "DSLO" + Value = "0x0C" + Help = "SW_SMI_DISPLAY_SWITCH_LID_OPEN_ACPI" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "DSLC" + Value = "0x0E" + Help = "SW_SMI_DISPLAY_SWITCH_LID_CLOSE_ACPI" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "PITS" + Value = "0x10" + Help = "SW_SMI_POPUP_ICON_TOGGLE" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "SBCS" + Value = "0x12" + Help = "SW_SMI_SET_BACKLIGHT_CONTROL" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "SALS" + Value = "0x13" + Help = "SW_SMI_SET_ALI_LEVEL" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "LSSS" + Value = "0x2A" + Help = "SW_SMI_LID_STATE_SWITCH" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "SOOT" + Value = "0x35" + Help = "SW_SMI_SAVE_OSB_OS_TYPE" + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "PDBR" + Value = "0x4D" + Help = "SW_SMI_PCIE_DOCK_BRIDGE_RESOURCE_PATCH" + TokenType = Integer + TargetASL = Yes +End + +TOKEN + Name = "BW1P" + Value = "0x21" + Help = "Haswell - WhiteTip Mountain1 PPV Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BW2C" + Value = "0x22" + Help = "Haswell - WhiteTip Mountain2 Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BW2P" + Value = "0x23" + Help = "Haswell - WhiteTip Mountain2 PPV Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BSPC" + Value = "0x24" + Help = "Haswell - Sawtooth Peak Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BSPP" + Value = "0x25" + Help = "Haswell - Sawtooth Peak PPV Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BICO" + Value = "0x27" + Help = "Haswell - WhiteTip Mountain2 CDK Open Chasis Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BICC" + Value = "0x28" + Help = "Haswell - WhiteTip Mountain2 CDK Close Chasis Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BHB" + Value = "0x30" + Help = "Haswell - Harris Beach FFRD Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BFS2" + Value = "0x31" + Help = "Haswell - FFRD SKU2 Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BFS3" + Value = "0x32" + Help = "Haswell - FFRD SKU3 Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BFS4" + Value = "0x33" + Help = "Haswell - FFRD SKU4 Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "BRH" + Value = "0x35" + Help = "Haswell - Reed Harbor TDV Board ID for ASL code." + TokenType = Integer + TargetASL = Yes + Range = "16-bit IO register" +End + +PATH + Name = "INTEL_ACPI_ASL_DIR" +End + +MODULE + Help = "Includes AcpiAsl.mak to Project" + File = "AcpiAsl.mak" +End + +ELINK + Name = "INTEL_EC_ASL" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "INTEL_GENERIC_ASL" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "$(INTEL_GENERIC_ASL)" + Parent = "GENERIC_ASL" + Priority = 10 + InvokeOrder = AfterParent +End + +ELINK + Name = "$(BUILD_DIR)\Cpu.asl" + Parent = "GENERIC_ASL" + Disable = Yes + InvokeOrder = AfterParent + Lock = Yes +End + +ELINK + Name = "Board\Em\Acpi\oemdsdt.asl" + Parent = "GENERIC_ASL" + Disable = Yes + InvokeOrder = AfterParent + Lock = Yes +End + +ELINK + Name = "Board\Em\Acpi\OEMRMISC.asl" + Parent = "GENERIC_ASL" + Disable = Yes + InvokeOrder = AfterParent + Lock = Yes +End + +ELINK + Name = "$(SB_CHIPSET_DIR)\IRQLink.asl" + Parent = "GENERIC_ASL" + Token = "PlatformAcpiTables_SUPPORT" "=" "0" + InvokeOrder = BeforeParent +End + +ELINK + Name = "$(INTEL_ACPI_ASL_DIR)\GloblNvs.asl" + Parent = "GENERIC_ASL_BEFORE_PCITREE" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(INTEL_ACPI_ASL_DIR)\CPU.asl" + Parent = "INTEL_GENERIC_ASL" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(INTEL_ACPI_ASL_DIR)\Platform.asl" + Parent = "INTEL_GENERIC_ASL" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(INTEL_ACPI_ASL_DIR)\PCI_DRC.asl" + Parent = "INTEL_GENERIC_ASL" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(INTEL_ACPI_ASL_DIR)\Video.asl" + Parent = "INTEL_GENERIC_ASL" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(INTEL_ACPI_ASL_DIR)\Gpe.asl" + Parent = "INTEL_GENERIC_ASL" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(INTEL_ACPI_ASL_DIR)\PCIEDOCK.asl" + Parent = "INTEL_GENERIC_ASL" + InvokeOrder = AfterParent + Token = "FACP_FLAG_DCK_CAP" "=" "1" + Token = "CRB_EC_SUPPORT" "=" "1" +End + +ELINK + Name = "$(INTEL_ACPI_ASL_DIR)\Thermal.asl" + Parent = "INTEL_GENERIC_ASL" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(INTEL_ACPI_ASL_DIR)\wcam.asl" + Parent = "INTEL_GENERIC_ASL" + InvokeOrder = AfterParent +End diff --git a/ReferenceCode/AcpiTables/Dsdt/Bat0Virt.asl b/ReferenceCode/AcpiTables/Dsdt/Bat0Virt.asl new file mode 100644 index 0000000..a87232c --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/Bat0Virt.asl @@ -0,0 +1,322 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Scope(\) +{ + // these fields come from the Global NVS area + Field(GNVS,AnyAcc,Lock,Preserve) + { + Offset(31), + B0SC, 8, // (31) Battery 0 Stored Capacity + Offset(34), + B0SS, 8, // (34) Battery 0 Stored Status + } +} + + +Method(_Q53) +{ + P8XH(0,0x53) // show query number on Port 80 + VBSE() // Virtual Battery Switch Event, remove if not needed. +} + + +// Virtual Battery Switch Event: +// This method handles the Virtual Battery switch on the CRB. +// +// Arguments: +// None +// +// Return Value: +// None +Method(VBSE,0,Serialized) // called from EC.asl +{ + // Check for Virtual Battery Mode. If the CRB is + // running on real batteries, skip this whole section. + + If(LEqual(BNUM,0)) + { + // Check that the current and NVS Power States + // are different. The 2 may be out of sync due to + // Virtual Battery hot-key support. + + If(LNotEqual(ECRD(RefOf(VPWR)),PWRS)) + { + // Update NVS Power State. + + Store(ECRD(RefOf(VPWR)),PWRS) + + + // Perform needed ACPI Notifications. + + PNOT() + } + } +} + + +// +// called from EC.asl _Q52 method +// +// Virtual Battery Hot Keys: +// This method passes the hot key scan code to the BTTM method. +// +// Arguments: +// None +// +// Return Value: +// None +Method(VBHK,0,Serialized) +{ + // 1/! Scan Code = 0x02 + + Store(ECRD(RefOf(SCAN)), Local0) + + If(LEqual(Local0,0x02)) // Battery = 10%. + { + BTTM(10) + } + + // 2/@ Scan Code = 0x03 + + If(LEqual(Local0,0x03)) // Battery = 20%. + { + BTTM(20) + } + + // 3/# Scan Code = 0x04 + + If(LEqual(Local0,0x04)) // Battery = 30%. + { + BTTM(30) + } + + // 4/$ Scan Code = 0x05 + + If(LEqual(Local0,0x05)) // Battery = 40%. + { + BTTM(40) + } + + // 5/% Scan Code = 0x06 + + If(LEqual(Local0,0x06)) // Battery = 50%. + { + BTTM(50) + } + + // 6/^ Scan Code = 0x07 + + If(LEqual(Local0,0x07)) // Battery = 60%. + { + BTTM(60) + } + + // 7/& Scan Code = 0x08 + + If(LEqual(Local0,0x08)) // Battery = 70%. + { + BTTM(70) + } + + // 8/* Scan Code = 0x09 + + If(LEqual(Local0,0x09)) // Battery = 80%. + { + BTTM(80) + } + + // 9/( Scan Code = 0x0A + + If(LEqual(Local0,0x0A)) // Battery = 90%. + { + BTTM(90) + } + + // 0/) Scan Code = 0x0B + + If(LEqual(Local0,0x0B)) // Battery = 100%. + { + BTTM(100) + } + + // _/- Scan Code = 0x0C + + If(LEqual(Local0,0x0C)) // Battery = Battery - 2%. + { + If(LGreaterEqual(B0SC,2)) + { + BTTM(Subtract(B0SC,2)) + } + } + + // +/= Scan Code = 0x0D + + If(LEqual(Local0,0x0D)) // Battery = Battery + 2%. + { + If(LLessEqual(B0SC,98)) + { + BTTM(Add(B0SC,2)) + } + } + + // F5 Scan Code = 0x3F + + If(LEqual(Local0,0x3F)) // Virtual Power State Change. + { + // Check for Virtual Battery Mode. If the CRB is + // running on real batteries, skip this whole section. + + If(LEqual(BNUM,0)) + { + // Toggle the Virtual Power State. + Xor(PWRS,1,PWRS) + + + // Perform needed ACPI Notifications. + PNOT() + } + } +} + + +// Battery Test Method: +// This method updates the Virtual Battery percentages and +// notifies the OS of these changes. +// +// Arguments: +// Arg0: The desired Virtual Battery Percentage. +// +// Return Value: +// None + +Method(BTTM,1,Serialized) +{ + If(PWRS) + { + If(LGreaterEqual(Arg0,B0SC)) + { + Store(Arg0,B0SC) + Notify(BAT0,0x80) + } + } + Else + { + If(LLessEqual(Arg0,B0SC)) + { + Store(Arg0,B0SC) + Notify(BAT0,0x80) + } + } +} + + // Define the Virtual Battery 0 Control Method. + + Device(BAT0) + { + Name(_HID,EISAID("PNP0C0A")) + + Name(_UID,0) + + Method(_STA,0) + { + If(LOr(LOr(LEqual(BID,BHB), LEqual(BID,BFS2)), LOr(LEqual(BID,BFS3), LEqual(BID,BFS4)))) //BoardIdHarrisBeachFfrd, BoardIdFfrdSku2, BoardIdFfrdSku3, BoardIdFfrdSku4 + { + Return(0x0000) // Yes. Hide Virtual. + } + If(LEqual(BID,BRH)) // BoardIdReedHarborTdv + { + Return(0x0000) // Yes. Hide it. + } + + If(And(BNUM,3)) // Battery 1 or 2 present? + { + If(LLessEqual(OSYS,2002)) + { + Return(0x000A) // Yes. Hide Virtual for Win XP + } + + Return(0x000B) // Yes. Hide Virtual. + } + + Return(0x001F) // No. Show Virtual. + } + + Method(_BIF,0) + { + Return(Package() { + 0x00000000, // Power Unit = mWh. + 0x00002710, // 10000 mWh Design Capacity. + 0x00002710, // 10000 mWh Last Full Charge. + 0x00000001, // Secondary Battery Technology. + 0xFFFFFFFF, // Unknown Design Voltage. + 0x000003E8, // 10% Warning Level. + 0x00000190, // 4% Low Level. + 0x00000064, // 1% Granularity Level 1. + 0x00000064, // 1% Granularity Level 2. + "CRB Battery 0", + "Battery 0", + "Fake", + "-Virtual Battery 0-"}) + } + + Method(_BST,0) + { + Name(PKG0,Package() { + 0xFFFFFFFF, // Battery State. + 0xFFFFFFFF, // Battery Present Rate. + 0xFFFFFFFF, // Battery Remaining Capacity. + 0xFFFFFFFF // Battery Present Voltage. + }) + + // Virtual AC/Battery Check. + + If(PWRS) + { + // Return Charging. + + Store(2,Index(PKG0,0)) + } + Else + { + // Return Discharging. + + Store(1,Index(PKG0,0)) + } + Store(0x7FFFFFFF,Index(PKG0,1)) + Store(Multiply(B0SC,100),Index(PKG0,2)) + Return(PKG0) + } + + // Return that everything runs off Battery. + + Method(_PCL,0) + { + Return(\_SB) + } + } + diff --git a/ReferenceCode/AcpiTables/Dsdt/Bat1Real.asl b/ReferenceCode/AcpiTables/Dsdt/Bat1Real.asl new file mode 100644 index 0000000..500d1d4 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/Bat1Real.asl @@ -0,0 +1,198 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Scope(\) +{ + // these fields come from the Global NVS area + Field(GNVS,AnyAcc,Lock,Preserve) + { + Offset(30), // Battery Support Registers: + BNUM, 8, // (30) Battery Number Present + Offset(32), + B1SC, 8, // (32) Battery 1 Stored Capacity + Offset(35), + B1SS, 8, // (35) Battery 1 Stored Status + } +} + + // Define the Real Battery 1 Control Method. + + Device(BAT1) + { + Name(_HID,EISAID("PNP0C0A")) + + Name(_UID,1) + + Method(_STA,0) + { + If(And(BNUM,1)) // Battery 1 present? + { + Return(0x001F) // Yes. Show it. + } + + If(LLessEqual(OSYS,2002)) + { + Return(0x000A) // hide it for Win XP support + } + + Return(0x000B) // No. Hide it. + } + + Method(_BIF,0) + { + Name(BPKG, Package() { + 0x00000000, // Power Unit = mWh. + 0xFFFFFFFF, // Unknown Design Capacity. + 0xFFFFFFFF, // Unknown Last Full Charge. + 0x00000001, // Secondary Battery Technology. + 0xFFFFFFFF, // Unknown Design Voltage. + 0x00000000, // 10% Warning Level. + 0x00000000, // 4% Low Level. + 0x00000064, // 1% Granularity Level 1. + 0x00000000, // 1% Granularity Level 2. + "SR Real Battery", + "123456789", + "Real", + "Intel SR 1" + }) + + If (LAnd(LAnd(ECRD(RefOf(B1DV)),ECRD(RefOf(B1FC))),ECRD(RefOf(B1DC)))) + { + // Convert mAh and mV to mWh + Store(Divide(Multiply(ECRD(RefOf(B1DC)), ECRD(RefOf(B1DV))),1000), Index(BPKG,1)) + Store(Divide(Multiply(ECRD(RefOf(B1FC)), ECRD(RefOf(B1DV))),1000), Index(BPKG,2)) + Store(B1DV, Index(BPKG,4)) + Store(Divide(Multiply(ECRD(RefOf(B1FC)), ECRD(RefOf(B1DV))),10000), Index(BPKG,5)) + Store(Divide(Multiply(ECRD(RefOf(B1FC)), ECRD(RefOf(B1DV))),25000), Index(BPKG,6)) + Store(Divide(Multiply(ECRD(RefOf(B1DC)), ECRD(RefOf(B1DV))),100000), Index(BPKG,7)) + } + + Return (BPKG) + } + + Method(_BST,0, Serialized) + { + Name(PKG1,Package() { + 0xFFFFFFFF, // Battery State. + 0xFFFFFFFF, // Battery Present Rate. (in mWh) + 0xFFFFFFFF, // Battery Remaining Capacity. (in mWh) + 0xFFFFFFFF // Battery Present Voltage. (in mV) + }) + + // Optimization for EC Low Power Mode due to many EC accesses in this method + // Wake EC for whole _BST method + Store(Zero, Local1) + if (LGreaterEqual(OSYS, 2013)) { + if (LEqual(ECLP, 0x1)) { + Store (Acquire(\EHLD, 100), Local2) + if (LEqual(Local2, Zero)) { // check for Mutex acquired, if Mutex not acquired _BST could take longer than expected to execute + if (LEqual(\ECUP,Zero)) { + Store(One, Local1) + \_SB.WTGP(88,1) + Sleep(8) + Store(One, \ECUP) + \_SB.PCI0.LPCB.H_EC.ECMD (0x2D) // Notify EC of CS exit + } else { + Release(\EHLD) + } + } + } + } + + // Fix up the Battery Status. + Store(And(ECRD(RefOf(B1ST)), 0x07),Index(PKG1,0)) + If(And(ECRD(RefOf(B1ST)), 0x01)) + { + // Calculate discharge rate + // Return Rate in mW since we report _BIF data in mW + Store(Multiply(ECRD(RefOf(B1DI)), ECRD(RefOf(B1FV))), Local0) + Store(Divide(Local0, 1000), Local0) + Store(Local0, Index(PKG1,1)) + } + Else + { + // Calculate charge rate + // Return Rate in mW since we report _BIF data in mW + Store(Multiply(ECRD(RefOf(B1CI)), ECRD(RefOf(B1FV))), Local0) + Store(Divide(Local0, 1000), Local0) + Store(Local0, Index(PKG1,1)) + } + + // Calculate Remaining Capacity in mWh = + // (Remaininng Capacity (mAh) * Design Voltage (mV))/1000 + // Use Remaininng Capacity in mAh multiply with a fixed Design Voltage + // for Remaininng Capacity in mWh + Store(Divide(Multiply(ECRD(RefOf(B1RC)), ECRD(RefOf(B1DV))),1000),Index(PKG1,2)) + + // Report Battery Present Voltage (mV) + Store(ECRD(RefOf(B1FV)), Index(PKG1,3)) + + // Optimization for EC Low Power Mode due to many EC accesses in this method + // Put EC back into Low Power Mode + if (LGreaterEqual(OSYS, 2013)) { + if (LEqual(ECLP, 0x1)) { + if (LEqual(Local1, One)) { + \_SB.WTGP(88,0) + \_SB.PCI0.LPCB.H_EC.ECMD (0x2C) // Notify EC of CS entry + Store(Zero, \ECUP) + Release(\EHLD) + } + } + } + + Return(PKG1) + } + + Method(_BTP,1) + { + // arg0 = Trip Point, sent to EC as Threshold. + // transfer input value from mWh to % + If(LAnd(LNotEqual(ECRD(RefOf(B1FC)),0),LNotEqual(ECRD(RefOf(B1FV)),0))) + { + Store(Divide(Multiply(Arg0, 100), Divide(Multiply(ECRD(RefOf(B1FC)), ECRD(RefOf(B1FV))),1000)),Local0) + + // adjust offset between OS & EC + Add(Local0,1,Local0) + + // store TP value in EC name space offset 219 + Store(Local0, ECRD(RefOf(BTP1))) + + // Send EC Battery Threshold Update Command - 0x34 + ECMD(0x34) + } + + Return() + + } + // Return that everything runs off Battery. + + Method(_PCL,0) + { + Return(\_SB) + } + } + diff --git a/ReferenceCode/AcpiTables/Dsdt/Bat2Real.asl b/ReferenceCode/AcpiTables/Dsdt/Bat2Real.asl new file mode 100644 index 0000000..13ad9d4 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/Bat2Real.asl @@ -0,0 +1,182 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Scope(\) +{ + // these fields come from the Global NVS area + Field(GNVS,AnyAcc,Lock,Preserve) + { + Offset(33), + B2SC, 8, // (33) Battery 2 Stored Capacity + Offset(36), + B2SS, 8 // (36) Battery 2 Stored Status + } +} + + // Define the Real Battery 2 Control Method. + + Device(BAT2) + { + Name(_HID,EISAID("PNP0C0A")) + Name(_UID,2) + + Method(_STA,0) + { + If(LOr(LOr(LEqual(BID,BHB), LEqual(BID,BFS2)), LOr(LEqual(BID,BFS3), LEqual(BID,BFS4)))) //BoardIdHarrisBeachFfrd, BoardIdFfrdSku2, BoardIdFfrdSku3, BoardIdFfrdSku4 + { + Return(0x0000) // Yes. Hide it. + } + If(LEqual(BID,BRH)) // BoardIdReedHarborTdv + { + Return(0x0000) // Yes. Hide it. + } + + If(And(BNUM,2)) // Battery 2 present? + { + Return(0x001F) // Yes. Show it. + } + + If(LLessEqual(OSYS,2002)) + { + Return(0x000A) // hide it for Win XP support + } + + Return(0x000B) // No. Hide it. + } + + Method(_BIF,0) + { + Name(BPK2, Package() { + 0x00000000, // Power Unit = mWh. + 0xFFFFFFFF, // Unknown Design Capacity. + 0xFFFFFFFF, // Unknown Last Full Charge. + 0x00000001, // Secondary Battery Technology. + 0xFFFFFFFF, // Unknown Design Voltage. + 0x00000000, // 10% Warning Level. + 0x00000000, // 4% Low Level. + 0x00000064, // 1% Granularity Level 1. + 0x00000000, // 1% Granularity Level 2. + "SR Real Battery", + "123456789", + "Real", + "Intel SR 2" + }) + + If (LAnd(LAnd(ECRD(RefOf(B1DV)),ECRD(RefOf(B2FC))),ECRD(RefOf(B1DC)))) + { + // Convert mAh and mV to mWh + Store(Divide(Multiply(ECRD(RefOf(B1DC)), ECRD(RefOf(B1DV))),1000), Index(BPK2,1)) + Store(Divide(Multiply(ECRD(RefOf(B2FC)), ECRD(RefOf(B1DV))),1000), Index(BPK2,2)) + Store(B1DV, Index(BPK2,4)) + Store(Divide(Multiply(ECRD(RefOf(B2FC)), ECRD(RefOf(B1DV))),10000), Index(BPK2,5)) + Store(Divide(Multiply(ECRD(RefOf(B2FC)), ECRD(RefOf(B1DV))),25000), Index(BPK2,6)) + Store(Divide(Multiply(ECRD(RefOf(B1DC)), ECRD(RefOf(B1DV))),100000), Index(BPK2,7)) + } + + Return (BPK2) + } + + Method(_BST,0, Serialized) + { + Name(PKG2,Package() { + 0xFFFFFFFF, // Battery State. + 0xFFFFFFFF, // Battery Present Rate. (in mWh) + 0xFFFFFFFF, // Battery Remaining Capacity. (in mWh) + 0xFFFFFFFF // Battery Present Voltage. (in mV) + }) + + // Optimization for EC Low Power Mode due to many EC accesses in this method + // Wake EC for whole _BST method + Store(Zero, Local1) + if (LGreaterEqual(OSYS, 2013)) { + if (LEqual(ECLP, 0x1)) { + Store (Acquire(\EHLD, 100), Local2) + if (LEqual(Local2, Zero)) { // check for Mutex acquired, if Mutex not acquired _BST could take longer than expected to execute + if (LEqual(\ECUP,Zero)) { + Store(One, Local1) + \_SB.WTGP(88,1) + Sleep(8) + Store(One, \ECUP) + \_SB.PCI0.LPCB.H_EC.ECMD (0x2D) // Notify EC of CS exit + } else { + Release(\EHLD) + } + } + } + } + + // Fix up the Battery Status. + Store(And(ECRD(RefOf(B2ST)), 0x07),Index(PKG2,0)) + If(And(ECRD(RefOf(B2ST)), 0x01)) + { + // Calculate discharge rate + // Return Rate in mW since we report _BIF data in mW + Store(Multiply(ECRD(RefOf(B2DI)), ECRD(RefOf(B2FV))), Local0) + Store(Divide(Local0, 1000), Local0) + Store(Local0, Index(PKG2,1)) + } + Else + { + // Calculate charge rate + // Return Rate in mW since we report _BIF data in mW + Store(Multiply(ECRD(RefOf(B2CI)), ECRD(RefOf(B2FV))), Local0) + Store(Divide(Local0, 1000), Local0) + Store(Local0, Index(PKG2,1)) + } + + // Calculate Remaining Capacity in mWh = + // (Remaininng Charge (mAh) * Present Voltage (mV))/1000 + Store(Divide(Multiply(ECRD(RefOf(B2RC)), ECRD(RefOf(B2FV))),1000),Index(PKG2,2)) + + // Report Battery Present Voltage (mV) + Store(ECRD(RefOf(B2FV)), Index(PKG2,3)) + + // Optimization for EC Low Power Mode due to many EC accesses in this method + // Put EC back into Low Power Mode + if (LGreaterEqual(OSYS, 2013)) { + if (LEqual(ECLP, 0x1)) { + if (LEqual(Local1, One)) { + \_SB.WTGP(88,0) + \_SB.PCI0.LPCB.H_EC.ECMD (0x2C) // Notify EC of CS entry + Store(Zero, \ECUP) + Release(\EHLD) + } + } + } + + Return(PKG2) + } + + // Return that everything runs off Battery. + + Method(_PCL,0) + { + Return(\_SB) + } + } + + diff --git a/ReferenceCode/AcpiTables/Dsdt/CPU.asl b/ReferenceCode/AcpiTables/Dsdt/CPU.asl new file mode 100644 index 0000000..7e6f6aa --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/CPU.asl @@ -0,0 +1,171 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + + + // NOTE: The _PDC Implementation is out of the scope of this + // reference code. Please see the latest Hyper-Threading Technology + // Reference Code for complete implementation details. + + Scope(\_PR) + { + Processor(CPU0, // Unique name for Processor 0. + 1, // Unique ID for Processor 0. + 0x1810, // CPU0 ACPI P_BLK address = ACPIBASE + 10h. + 6) // CPU0 P_BLK length = 6 bytes. + { + Method(_DEP){ + ADBG("CPU0 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("CPU0 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("CPU0 DEP NULL") + Return(Package() {}) + } + } + } + + Processor(CPU1, // Unique name for Processor 1. + 2, // Unique ID for Processor 1. + 0x1810, + 6) // CPU1 P_BLK length = 6 bytes. + { + Method(_DEP){ + ADBG("CPU1 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("CPU1 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("CPU1 DEP NULL") + Return(Package() {}) + } + } + } + + Processor(CPU2, // Unique name for Processor 2. + 3, // Unique ID for Processor 2. + 0x1810, + 6) // CPU2 P_BLK length = 6 bytes. + { + Method(_DEP){ + ADBG("CPU2 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("CPU2 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("CPU2 DEP NULL") + Return(Package() {}) + } + } + } + + Processor(CPU3, // Unique name for Processor 3. + 4, // Unique ID for Processor 3. + 0x1810, + 6) // CPU3 P_BLK length = 6 bytes. + { + Method(_DEP){ + ADBG("CPU3 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("CPU3 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("CPU3 DEP NULL") + Return(Package() {}) + } + } + } + Processor(CPU4, // Unique name for Processor 4. + 5, // Unique ID for Processor 4. + 0x1810, + 6) // CPU4 P_BLK length = 6 bytes. + { + Method(_DEP){ + ADBG("CPU4 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("CPU4 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("CPU4 DEP NULL") + Return(Package() {}) + } + } + } + + Processor(CPU5, // Unique name for Processor 5. + 6, // Unique ID for Processor 5. + 0x1810, + 6) // CPU5 P_BLK length = 6 bytes. + { + Method(_DEP){ + ADBG("CPU5 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("CPU5 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("CPU5 DEP NULL") + Return(Package() {}) + } + } + } + Processor(CPU6, // Unique name for Processor 6. + 7, // Unique ID for Processor 6. + 0x1810, + 6) // CPU6 P_BLK length = 6 bytes. + { + Method(_DEP){ + ADBG("CPU6 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("CPU6 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("CPU6 DEP NULL") + Return(Package() {}) + } + } + } + + Processor(CPU7, // Unique name for Processor 7. + 8, // Unique ID for Processor 7. + 0x1810, + 6) // CPU7 P_BLK length = 6 bytes. + { + Method(_DEP){ + ADBG("CPU7 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("CPU7 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("CPU7 DEP NULL") + Return(Package() {}) + } + } + } + + } // End _PR + + diff --git a/ReferenceCode/AcpiTables/Dsdt/DSDT.ASL b/ReferenceCode/AcpiTables/Dsdt/DSDT.ASL new file mode 100644 index 0000000..748996f --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/DSDT.ASL @@ -0,0 +1,96 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +DefinitionBlock ( + "DSDT.aml", + "DSDT", + 0x02, // DSDT revision. + // A Revision field value greater than or equal to 2 signifies that integers + // declared within the Definition Block are to be evaluated as 64-bit values + "INTEL", // OEM ID (6 byte string) + "HSW-LPT", // OEM table ID (8 byte string) + 0x0 // OEM version of DSDT table (4 byte Integer) + ) + +// BEGIN OF ASL SCOPE +{ + +External(LHIH) +External(LLOW) +External(IGDS) +External(LIDS) +External(BRTL) +External(ALSE) +External(GSMI) +External(\_SB.PCI0.GFX0.ALSI) +External(\_SB.PCI0.GFX0.CDCK) +External(\_SB.PCI0.GFX0.CBLV) +External(\_SB.PCI0.GFX0.GSSE) +External(\_SB.PCI0.PEG0, DeviceObj) +External(\_SB.PCI0.PEG0.PEGP, DeviceObj) +External(\_SB.PCI0.PEG1, DeviceObj) +External(\_SB.PCI0.PEG2, DeviceObj) +External(\_SB.PCI0.GFX0.DD1F, DeviceObj) +External(\_SB.PCI0.GFX0.GDCK, MethodObj) +External(\_SB.PCI0.GFX0.GHDS, MethodObj) +External(\_SB.PCI0.GFX0.AINT, MethodObj) +External(\_SB.PCI0.GFX0.GLID, MethodObj) +External(\_SB.PCI0.GFX0.GSCI, MethodObj) +External(\_PR.CPU0, DeviceObj) +External(\_PR.CPU0._PSS, MethodObj) +External(\_PR.CPU0._PPC, IntObj) + + +// Miscellaneous services enabled in Project + include ("amlupd.asl") + include ("token.asl") + include ("GloblNvs.asl") + include ("PCItree.asl") + include ("Platform.asl") + include ("CPU.asl") + include ("Thermal.asl") + include ("PCI_DRC.asl") + include ("Video.asl") + include ("Gpe.asl") + include ("PCIEDOCK.asl") + include ("Pch.asl") // Not in this package. Refer to the PCH Reference Code accordingly +//---------------------------------------------------------------------- + Name(\_S0, Package(4){0x0,0x0,0,0}) // mandatory System state + if(SS1) { Name(\_S1, Package(4){0x1,0x0,0,0})} + if(SS3) { Name(\_S3, Package(4){0x5,0x0,0,0})} + if(SS4) { Name(\_S4, Package(4){0x6,0x0,0,0})} + Name(\_S5, Package(4){0x7,0x0,0,0}) // mandatory System state + + Method(PTS, 1) { // METHOD CALLED FROM _PTS PRIOR TO ENTER ANY SLEEP STATE + If(Arg0) // entering any sleep state + { + } + } + Method(WAK, 1) { // METHOD CALLED FROM _WAK RIGHT AFTER WAKE UP + } +}// End of ASL File + diff --git a/ReferenceCode/AcpiTables/Dsdt/EC.ASL b/ReferenceCode/AcpiTables/Dsdt/EC.ASL new file mode 100644 index 0000000..b223a9a --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/EC.ASL @@ -0,0 +1,1893 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +External(\_SB.IETM, DeviceObj) + +External(TBAB) +External(RTIP) +External(HGAS, MethodObj) +External(HPFS, MethodObj) +External(HBRT, MethodObj) +External(CHPS, MethodObj) +External(UP1D) +External(UPRW) +External(SVRF, MethodObj) +External(\_SB.PCI0.CTCU, MethodObj) +External(\_SB.PCI0.CTCN, MethodObj) +External(\_SB.PCI0.CTCD, MethodObj) +#if !defined(ASL_Remove_SaSsdt_Data_To_Dsdt) || (ASL_Remove_SaSsdt_Data_To_Dsdt == 0) +External(\_SB.PCI0.GFX0.CLID) +External(\_SB.PCI0.GFX0.IUEH, MethodObj) +External(\_SB.PCI0.GFX0.IUER, DeviceObj) +#endif +#define POWER_BUTTON 0 +#define WINDOWS_BUTTON 1 +#define VOLUME_UP_BUTTON 2 +#define VOLUME_DOWN_BUTTON 3 +#define ROTATION_LOCK_BUTTON 4 +#define CONVERTIBLE_BUTTON 6 +#define DOCK_INDICATOR 7 + +Device(H_EC) // Hitachi Embedded Controller +{ + Name(_HID, EISAID("PNP0C09")) + + Name(_UID,1) + + Name(ECAV, Zero) // OS Bug Checks if EC OpRegion accessed before Embedded Controller Driver loaded + + Method(_CRS,0) + { + Name(BFFR, ResourceTemplate() + { + IO(Decode16,0x62,0x62,0,1) // DIN/DOUT + IO(Decode16,0x66,0x66,0,1) // CMD/STS + }) + + Return(BFFR) + } + + Method(_STA) + { + If (LEqual(ECON,1)){ + Return(0x0F) + } + Return(0x00) + } + + OperationRegion(ECF2,EmbeddedControl,0,0xFF) + Field(ECF2,ByteAcc,Lock,Preserve) + { + Offset(1), + PLMX, 8, // 1 Max Platform temprature + LTMP, 8, // 2 Sensor Temperature + RPWR, 1, // 3.0 Real AC Power (AC Present = 1) + , 2, // 3.2:1 Reserved + CFAN, 1, // 3.3 CPU Fan (Fan On = 1) + , 2, // 3.5:4 Reserved + LSTE, 1, // 3.6 Lid State (Lid Open = 1) + , 1, // 3.7 Reserved + SPTR, 8, // 4 SMBus Protocol Register + SSTS, 8, // 5 SMBus Status Register + SADR, 8, // 6 SMBus Address Register + SCMD, 8, // 7 SMBus Command Register + SBFR, 256, // 8 SMBus Block Buffer + SCNT, 8, // 40 SMBus Block Count + Offset(47), + CTMP, 8, // 47 EC Critical Temperature + DOCK, 1, // 48.0 Docking state (docked = 1) + EJET, 1, // 48.1 Eject switch state (Eject (Q-Switch off) = 1) + , 1, // 48.2 Reserved + PBNS, 1, // 48.3 Power Button State (0 = Pressed) + VPWR, 1, // 48.4 Virtual AC Power (AC Present = 1) + , 3, // 48.7:5 Reserved + SCAN, 8, // 49 Hot-Key Scan Code + B1ST, 8, // 50 Battery 1 Status + B1CR, 8, // 51 Battery 1 Current Rate + B1CC, 8, // 52 Battery 1 Current Capacity + B1VT, 8, // 53 Battery 1 Voltage + B2ST, 8, // 54 Battery 2 Status + B2CR, 8, // 55 Battery 2 Current Rate + B2CC, 8, // 56 Battery 2 Current Capacity + B2VT, 8, // 57 Battery 2 Voltage + CMDR, 8, // 58 KSC command register + LUXL, 8, // 59 LUX - Low Byte + LUXH, 8, // 60 LUX - High Byte + ACH0, 8, // 61 Channel 0 RAW Value + ACH1, 8, // 62 Channel 1 RAW Value + Offset(65), + PPSL, 8, // 65 PWM Port Select low byte + PPSH, 8, // 66 PWM Port Select high byte + PINV, 8, // 67 PWM initial value + PENV, 8, // 68 PWM ending value + PSTP, 8, // 69 PWM ms delay between steps + Offset(71), + CPUP, 16, // 71 CPU Power mW + BPWR, 16, // 73 Brick Power cW(100ths) + PPWR, 16, // 75 Platform Power cW(100ths) + CVRT, 8, // 77 CPU VR (IMVP) Temp + FANT, 8, // 78 Heat exchanger fan temp + SKNT, 8, // 79 Skin temp + AMBT, 8, // 80 Ambient temp + Offset(82), // 82-85 DPTF fields + TSI, 4, // Hysteresis selection is global and meant for all four sensors. + // # 0 = CPU VR (IMVP) temperature sensor + // # 1 = Heat Exchanger temperature sensor + // # 2 = Skin temperature sensor + // # 3 = Ambient temperature sensor + // # 4 = DIMM temperature sensor + // # Above 4 invalid + HYST, 4, // 82.4-7 Hysteresis in deg C + TSHT, 8, // 83 Thermal Sensor (N) high trip point + TSLT, 8, // 84 Thermal Sensor (N) low trip point + TSSR, 8, // 85 TSSR- thermal sensor status register: + // TSSR bits defined: + // BIT0: CPU VR Temp Sensor Trip Flag + // BIT1: Fan Temp Sensor Trip Flag + // BIT2: Skin Temp Sensor Trip Flag + // BIT3: Ambient Temp Sensor Trip Flag + // BIT4: DIMM Trip Point Flag + // BIT[7:5] Reserved + Offset(86), + B1CM, 8, // 86 Battery 1 Command (Place holder for now) + B1DC, 16, // 87 Battery 1 Design Capacity (mWh) + B1RC, 16, // 89 Battery 1 Remaining Capacity (mWh) + B1FC, 16, // 91 Battery 1 Full Charge Capacity (mWh) + B1FV, 16, // 93 Battery 1 Full Resolution Voltage (mV) + B1DI, 16, // 95 Battery 1 Full Resolution Discharge Current (mA) + B1CI, 16, // 97 Battery 1 Full Resolution Charge Current (mA) + B2RC, 16, // 99 Battery 2 Remaining Capacity (mWh) + B2FC, 16, // 101 Battery 2 Full Charge Capacity (mWh) + B2FV, 16, // 103 Battery 2 Full Resolution Voltage (mV) + B2DI, 16, // 105 Battery 2 Full Resolution Discharge Current (mA) + B2CI, 16, // 107 Battery 2 Full Resolution Charge Current (mA) + CPAP, 16, // 109 CPU average power in mW + BKAP, 16, // 111 Brick average power in cW(0.01) + PLAP, 16, // 113 Platform average power in cW(0.01) + CFSP, 16, // 115 CPU Fan speed in rpm + BRTV, 8, // 117 Brightness value for San Rafael second panel + , 8, // 118 reserved + SLPC, 8, // 119 Select Performance Counters + DLED, 1, // 120.0 EC Connected Standby Debug LED (CAPS LOCK) + PB10, 1, // 120.1 10 Second Power Button Control + Offset(124), + PTIM, 8, // 124 CPU,GFX pwr sample timer + DHPD, 8, // 125 Digital display hot-plug detect + DIM0, 8, // 126 DIMM0 temperature + DIM1, 8, // 127 DIMM1 temperature + PMAX, 8, // 128 CPU,MCH & PCH Max temp + PPDT, 8, // 129 PCH DTS reading from PCH + PECL, 8, // 130 CPU PECI reading fractional value (1/64 Celcius) + PECH, 8, // 131 CPU PECI reading integer value (unit Celicus) + PMDT, 8, // 132 MCH DTS reading from PCH + TSD0, 8, // 133 TS-on-DIMM0 temperature + TSD1, 8, // 134 TS-on-DIMM1 temperature + TSD2, 8, // 135 TS-on-DIMM2 temperature + TSD3, 8, // 136 TS-on-DIMM3 temperature + PAKN, 8, // 137 Packet sequence number + CPUE, 32, // 138 CPU energy + Offset(155), + PRCL, 8, // 155 Repeat cycle (LSB) + PRC0, 8, // 156 Repeat cycle + PRC1, 8, // 157 Repeat cycle + PRCM, 8, // 158 Repeat cycle (MSB) + PRIN, 8, // 159 Repear Intervel + PSTE, 8, // 160 Stop on Error + PCAD, 8, // 161 Peci Clinet Addess + PEWL, 8, // 162 Write Length + PWRL, 8, // 163 Read lenght + PECD, 8, // 164 Command Code + PEHI, 8, // 165 Host ID + PECI, 8, // 166 Index + PEPL, 8, // 167 Parameter (LSB) + PEPM, 8, // 168 Parameter (MSB) + PWFC, 8, // 169 Write FCS + PECC, 8, // 170 Completion code + PDT0, 8, // 171 Data 0 + PDT1, 8, // 172 Data 1 + PDT2, 8, // 173 Data 2 + PDT3, 8, // 174 Data 3 + PRFC, 8, // 175 Read FCS + PRS0, 8, // 176 Reserved + PRS1, 8, // 177 Reserved + PRS2, 8, // 178 Reserved + PRS3, 8, // 179 Reserved + PRS4, 8, // 180 Reserved + Offset(187), + PRCS, 8, // 187 Peci Repeat Command Status + PEC0, 8, // 188 Peci Error Count(LSB) + PEC1, 8, // 189 Peci Error Count + PEC2, 8, // 190 Peci Error Count + PEC3, 8, // 191 Peci Error Count(MSB) + GTVR, 8, // 192 CPU GT VR temp + MCRT, 8, // 193 Minicard Region Temp + Offset(194), + IBT1, 8, // 194 ISCT Byte 1 + // 194.0 Enable/Disable ISCT - SAOS bit + // 194.1 WLAN powered in S3 + // 194.2 WLAN powered in S4 + // 194.3 WLAN powered in S5 + // 194.4 WWAN powered in S3 + // 194.5 WWAN powered in S4 + // 194.6 WWAN powered in S5 + // 194.7 Reserved + IBT2, 8, // 195 ISCT Byte 2 + // 195.0 WLAN Wireless Status (0 = Disabled, 1 = Enabled) + // 195.1 WWAN Wireless Status (0 = Disabled, 1 = Enabled) + // 195.2:7 Reserved + WTMS, 8, // 196 Wake timer Settings + // 196.0 Timer Enabled in S3 + // 196.1 Timer Enabled in S4 + // 196.2 Timer Enabled in S5 + // 196.3:6 Reserved + // 196.7 Enable/Disable EC Timer + AWT2, 8, // 197 ACPIWakeTmrByte2 - Wake timer value (BIT23-16) + AWT1, 8, // 198 ACPIWakeTmrByte1 - Wake timer value (BIT15-8) + AWT0, 8, // 199 ACPIWakeTmrByte0 - Wake timer value (BIT7-0) + SPT2, 1, // 200.0 SATA Por2 - Cable connect power control. 1=ON;0=OFF + ,7, // 200.7-1 Reserved + Offset(211), + B1DV, 16, // 211 Battery 1 Design Voltage (mV) + Offset(215), + B1ML, 8, // 215 BattAPmaxL - Battery Pack A maximum low byte + B1MH, 8, // 216 BattAPmaxH - Battery Pack A maximum high byte + B2ML, 8, // 217 BattBPmaxL - Battery Pack B maximum low byte + B2MH, 8, // 218 BattBPmaxH - Battery Pack B maximum high byte + BTP1, 8, // 219 Battery 1 Trip Point in % + } + + + // ECRD (Embedded Read Method) + // + // Handle all commands sent to EC by BIOS + // + // Arguments: (1) + // Arg0 - Object to Read + // Return Value: + // Read Value + // + Method(ECRD,1,Serialized, 0, IntObj, FieldUnitObj) + { + If(LAnd(LEqual(\ECUP,Zero),LEqual(\_SB.RDGP(88),0))) + { + \_SB.WTGP(88,1) + Sleep(16) + } + Store(DerefOf (Arg0), Local0) + Return(Local0) + } + + // ECWT (Embedded Write Method) + // + // Handle all commands sent to EC by BIOS + // + // Arguments: (2) + // Arg0 - Value to Write + // Arg1 - Object to Write to + // + Method(ECWT,2,Serialized,,,{IntObj, FieldUnitObj}) + { + If(LAnd(LEqual(\ECUP,Zero),LEqual(\_SB.RDGP(88),0))) + { + \_SB.WTGP(88,1) + Sleep(16) + } + Store(Arg0,Arg1) + } + + // ECMD (Embedded Controller Command) + // + // Handle all commands sent to EC by BIOS + // + // Arguments: (1) + // Arg0 - EC command + // Return Value: + // 0x00 = Success + // 0xFF = Failure + // + Method(ECMD,1,Serialized) + { + While(ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.CMDR))){Stall(20)} // make sure no command is currently being processed so we don't overwrite it + ECWT(Arg0, RefOf(\_SB.PCI0.LPCB.H_EC.CMDR)) + Return (0x00) + } + + Include("ALS.ASL") + + + // Virtual battery code + // + Include("Bat0Virt.asl") + + // Real battery code + // + Include("Bat1Real.asl") + Include("Bat2Real.asl") + + // The _REG Method is needed because communication with the EC + // before the driver is loaded is prohibited in WIN2000/WINXP. + + Method(_REG,2) + { + If(LAnd(LEqual(Arg0,3),LEqual(Arg1,1))) + { + // Must be running NT 5.0 OS. + // Update ECAV Object. ASL should check for this value to be One before accessing EC OpRegion. + Store(One, ECAV) + + // Turn off the CPU Fan if Active Cooling + // is disabled. + + If(LEqual(0,ACTT)) + { + ECWT(0,RefOf(CFAN)) + } + + // Turn off pwm fan so it starts in a known state + If(LEqual(1, THOF)) + { + \_TZ.FN00._OFF() + } + + // Update the Ambiant Light Illuminence Values. + + Store(ECRD(RefOf(LUXH)),LHIH) + Store(ECRD(RefOf(LUXL)),LLOW) + + If(LAnd(LEqual(ALSE,2),IGDS)) + { + Store(ECRD(RefOf(LUXH)), Local0) + Or(ShiftLeft(Local0, 8), ECRD(RefOf(LUXL)), \_SB.PCI0.GFX0.ALSI) + } + + // Save the Lid State in global NVS and IGD OpRegion. + //Store(LSTE,\_SB.PCI0.GFX0.CLID) + If (LEqual(ECRD(RefOf(LSTE)), 0)) + { + Store(0,\_SB.PCI0.GFX0.CLID) + } + If (LEqual(ECRD(RefOf(LSTE)), 1)) + { + Store(3,\_SB.PCI0.GFX0.CLID) + } + Store(ECRD(RefOf(LSTE)),LIDS) + + // Update the Dock Status + Store(\DSTS,\_SB.PCI0.GFX0.CDCK) + + // Unconditionally fix up the Battery and Power State. + + // Initialize the Number of Present Batteries. + // 1 = Real Battery 1 is present + // 2 = Real Battery 2 is present + // 3 = Real Battery 1 and 2 are present + + Store(0,BNUM) + Or(BNUM,ShiftRight(And(ECRD(RefOf(B1ST)),0x08),3),BNUM) + Or(BNUM,ShiftRight(And(ECRD(RefOf(B2ST)),0x08),2),BNUM) + + // Save the current Power State for later. + + Store(PWRS,Local0) + + // Initialize the Power State. + // BNUM = 0 = Virtual Power State + // BNUM > 0 = Real Power State + + If(LEqual(BNUM,0)) + { + Store(ECRD(RefOf(VPWR)),PWRS) + } + Else + { + Store(ECRD(RefOf(RPWR)),PWRS) + } + + // Perform needed ACPI Notifications. + + PNOT() + + // + // Call Power button init method for 10sec PB OVR + // + ^VGBI.PBIN() + } + } + + Method(_GPE) + { + Store (23, Local0) // GPI7 for other boards + + If(LOr(LOr(LEqual(BID,BWT1), LEqual(BID,BW1P)), LOr(LEqual(BID,BW2C), LEqual(BID,BW2P)))) // BoardIdWhiteTipMountain1, BoardIdWhiteTipMountain1Ppv, BoardIdWhiteTipMountain2, BoardIdWhiteTipMountain2Ppv + { + Store(10, Local0) // GPI10 + } + + If(LOr(LOr(LEqual(BID,BSPC), LEqual(BID,BSPP)), LEqual(BID,BRH))) // BoardIdSawToothPeak, BoardIdSawToothPeakPpv, BoardIdReedHarborTdv + { + Store(10, Local0) // GPI10 + } + + return (Local0) + } + + // For the below _Qxx Methods, The Runtime SCI has been asserted, + // the EC Driver performed it's query, and the value returned from + // the Query = xx. + + Method(_Q30) // Real Battery AC Insertion Event. + { + P8XH(0,0x30) + + // Set Global Power State = AC Mode. + + Store(1,PWRS) + + // Perform needed ACPI Notifications. + + PNOT() + } + + Method(_Q31) // Real Battery AC Removal Event. + { + P8XH(0,0x31) + + // Set Global Power State = Battery Mode. + + Store(0,PWRS) + + // Perform needed ACPI Notifications. + + PNOT() + } + + Method(_Q32) // Real Battery Capacity Change. + { + P8XH(0,0x32) + + // Perform needed ACPI Notifications. + + PNOT() + } + + Method(_Q33) // Real Battery Insertion/Removal Event. + { + P8XH(0,0x33) + + // Initialize the Number of Present Batteries. + // 1 = Real Battery 1 is present + // 2 = Real Battery 2 is present + // 3 = Real Battery 1 and 2 are present + + Store(0,BNUM) + Or(BNUM,ShiftRight(And(ECRD(RefOf(B1ST)),0x08),3),BNUM) + Or(BNUM,ShiftRight(And(ECRD(RefOf(B2ST)),0x08),2),BNUM) + + // Perform needed ACPI Notifications. + + PNOT() + } + + Method(_Q40, 0, Serialized) // Dock complete Event + { + P8XH(0,0x40) + If(LEqual(\_SB.PCI0.HDEF.DCKS, 1)) + { + If(LEqual(\_SB.PCI0.HDEF.DCKM, 0)) + { + Store(1, \_SB.PCI0.HDEF.DCKA) + Stall(50) + While(LNotEqual(\_SB.PCI0.HDEF.DCKM, 1)) + { + Stall(50) + } + } + } + + Sleep(1000) // Delay 1 second for hot docking stability + Store(\PDBR, \SSMP) + Store(1, \DSTS) + Sleep(1000) // Delay 1 second for hot docking stability + Notify(\_SB.PCI0.DOCK, 0x00) + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + Or(PB1E, 0x10, PB1E) // Set Dock status + ^VGBI.UPBT(DOCK_INDICATOR, One) + ADBG("Notify 0xCA") + Notify(^VGBI, 0xCA) // Notify Virtual GPIO driver that Docking event happens. + } + + If(IGDS) + { + \_SB.PCI0.GFX0.GDCK(1) + } + } + + Method(_Q41) // Surprise Removal + { + P8XH(0,0x41) + If(LEqual(\_SB.PCI0.HDEF.DCKS, 1)) + { + If(LEqual(\_SB.PCI0.HDEF.DCKM, 1)) + { + Store(0, \_SB.PCI0.HDEF.DCKA) + } + } + Store(0, \DSTS) + Notify(\_SB.PCI0.DOCK, 0x01) + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + And(PB1E, Not(0x10), PB1E) // Clear Dock Status + ^VGBI.UPBT(DOCK_INDICATOR, Zero) + ADBG("Notify 0xCB") + Notify(^VGBI, 0xCB) // Notify Virtual GPIO driver that Undocking event happens. + } Else { + If(IGDS) + { + \_SB.PCI0.GFX0.GDCK(0) + } + } + } + + Method(_Q42) // Undocking request Event + { + P8XH(0,0x42) + If(LAnd(\_SB.PCI0.HDEF.DCKS, 1)) + { + Store(0, \_SB.PCI0.HDEF.DCKA) + } + Notify(\_SB.PCI0.DOCK, 0x01) + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + And(PB1E, Not(0x10), PB1E) // Clear Dock Status + ^VGBI.UPBT(DOCK_INDICATOR, Zero) + If(CondRefOf(\_SB.PCI0.GFX0.IUER)) + { + Store(\_SB.PCI0.GFX0.IUER, Local0) + And(Local0, Not(0x80), \_SB.PCI0.GFX0.IUER) + } + ADBG("Notify 0xCB") + Notify(^VGBI, 0xCB) // Notify Virtual GPIO driver that Undocking event happens. + } Else { + If(IGDS) + { + \_SB.PCI0.GFX0.GDCK(0) + } + } + } + + Method(_Q43) // Express Card Presence Changed on Saddlestring (Docking) + { + P8XH(0,0x43) + + Notify(\_SB.PCI0.RP07, 0x0) + } + + Method(_Q44) // Virtual Dock Presence Changed + { + If(\DSTS) + { + Notify(\_SB.PCI0.DOCK, 1) //UnDocked + Store(0, \DSTS) + } + Else + { + Notify(\_SB.PCI0.DOCK, 0) //Docked + Store(1, \DSTS) + } + } + + Method(_Q51) // Lid Switch Event. + { + P8XH(0,0x51) + + // Update Lid NVS State. + + Store(ECRD(RefOf(LSTE)),LIDS) + + \_SB.PCI0.GFX0.GLID(LIDS) + + // If ETM is not disabled, notify IETM device + If (LEqual(\_TZ.ETMD, 0)) + { + If(CondRefOf(\_SB.IETM)) + { + Notify(\_SB.IETM,0x83) + } + } + Notify(\_SB.LID0,0x80) + } + + + Method(_Q52) // Hot-Key Event. + { + P8XH(0,0x52) + + // This event will be generated whenever a + // CRTL+ALT+SHIFT+"Next Key" is hit. This event handler + // will base code execution on the "Next Key" Scan Code + // stored in the EC Memory Space. + + Store(ECRD(RefOf(SCAN)),Local2) + P8XH(1,Local2) + + + // "D" Scan Code = 0x20 + + If(LEqual(SCAN,0x20)) + { + ADBG("CAS+D") + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + // + // CAS+D test emulation mode + // 1. Windows press notify 0xC2 + // 2. Volume up press notify 0xC4 + // 3. Volume up release notify 0xC5 + // 4. Windows release notify 0xC3 + // + + Sleep(1000) // 1sec delay is needed for Powerbutton and Windows Home button. + + ^VGBI.UPBT(WINDOWS_BUTTON, One) // Update VBDS + ADBG("Notify 0xC2") + Notify(^VGBI, 0xC2) // Notify Virtual GPIO driver that Windows Home button is pressed. + + ^VGBI.UPBT(VOLUME_UP_BUTTON, One) + ADBG("Notify 0xC4") + Notify(^VGBI, 0xC4) // Notify Virtual GPIO driver that Vol up button is pressed. + + ^VGBI.UPBT(VOLUME_UP_BUTTON, Zero) + ADBG("Notify 0xC5") + Notify(^VGBI, 0xC5) // Notify Virtual GPIO driver that Vol up button is released. + + ^VGBI.UPBT(WINDOWS_BUTTON, Zero) + ADBG("Notify 0xC3") + Notify(^VGBI, 0xC3) // Notify Virtual GPIO driver that Windows Home button is released. + } + } + + // "F" Scan Code = 0x21 + + If(LEqual(SCAN,0x21)) + { + ADBG("CAS+F") + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + // + // CAS+F test emulation mode + // 1. Windows press notify 0xC2 + // 2. Volume down press notify 0xC6 + // 3. Volume down release notify 0xC7 + // 4. Windows release notify 0xC3 + // + + Sleep(1000) // 1sec delay is needed for Powerbutton and Windows Home button + + ^VGBI.UPBT(WINDOWS_BUTTON, One) // Update VBDS + ADBG("Notify 0xC2") + Notify(^VGBI, 0xC2) // Notify Virtual GPIO driver that Windows Home button is pressed. + + ^VGBI.UPBT(VOLUME_DOWN_BUTTON, One) + ADBG("Notify 0xC6") + Notify(^VGBI, 0xC6) // Notify Virtual GPIO driver that Vol down button is pressed. + + ^VGBI.UPBT(VOLUME_DOWN_BUTTON, Zero) + ADBG("Notify 0xC7") + Notify(^VGBI, 0xC7) // Notify Virtual GPIO driver that Vol down button is released. + + ^VGBI.UPBT(WINDOWS_BUTTON, Zero) // Update VBDS + ADBG("Notify 0xC3") + Notify(^VGBI, 0xC3) // Notify Virtual GPIO driver that Windows Home button is released. + } + } + + // Intel Ultrabook Event Handlers. + + // "G" Scan Code = 0x22 + + If(LEqual(Local2,0x22)) + { + ADBG("CAS+G") + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + // + // CAS+G test emulation mode + // 1. Windows press notify 0xC2 + // 2. Powerbutton press notify 0xC0 + // 3. Powerbutton release notify 0xC1 + // 4. Windows release notify 0xC3 + // + + Sleep(1000) // 1sec delay is needed for Powerbutton and Windows Home button + + ^VGBI.UPBT(WINDOWS_BUTTON, One) + ADBG("Notify 0xC2") + Notify(^VGBI, 0xC2) // Notify Virtual GPIO driver that Windows Home button is pressed. + If(And(PB1E, 1)) + { + ^VGBI.UPBT(POWER_BUTTON, One) + ADBG("Notify 0xC0") + Notify(^VGBI, 0xC0) // Notify Virtual GPIO driver that Power button is pressed. + + ^VGBI.UPBT(POWER_BUTTON, Zero) + ADBG("Notify 0xC1") + Notify(^VGBI, 0xC1) // Notify Virtual GPIO driver that Power button is released. + } + + ^VGBI.UPBT(WINDOWS_BUTTON, Zero) + ADBG("Notify 0xC3") + Notify(^VGBI, 0xC3) // Notify Virtual GPIO driver that Windows Home button is released. + } Else { + // Power Button. If HID Event Driver loaded, use it. Otherwise, use GFX Driver. + If(LEqual(\_SB.HIDD.HRDY, 1)) + { + \_SB.HIDD.HPEM(9) + } Else { + ADBG("IUEH") + \_SB.PCI0.GFX0.IUEH(0) + } + } + } + + // "H" Scan Code = 0x23 + + If(LEqual(Local2,0x23)) + { + ADBG("CAS+H") + // Windows Button. If HID Event Driver loaded, use it. Otherwise, use GFX Driver. + Sleep(1000) + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + ^VGBI.UPBT(WINDOWS_BUTTON, One) + ADBG("Notify 0xC2") + Notify(^VGBI, 0xC2) // Notify Virtual GPIO driver that Windows Home button is pressed. + ^VGBI.UPBT(WINDOWS_BUTTON, Zero) + ADBG("Notify 0xC3") + Notify(^VGBI, 0xC3) // Notify Virtual GPIO driver that Windows Home button is released. + } Else { + If(LEqual(\_SB.HIDD.HRDY, 1)) + { + \_SB.HIDD.HPEM(1) + } Else { + ADBG("IUEH") + \_SB.PCI0.GFX0.IUEH(1) + } + } + } + + // "J" Scan Code = 0x24 + If(LEqual(Local2,0x24)) + { + ADBG("CAS+J") + // Volume Up. If HID Event Driver loaded, use it. Otherwise, use GFX Driver. + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + ^VGBI.UPBT(VOLUME_UP_BUTTON, One) + ADBG("Notify 0xC4") + Notify(^VGBI, 0xC4) // Notify Virtual GPIO driver that Volume UP button is pressed. + + ^VGBI.UPBT(VOLUME_UP_BUTTON, Zero) + ADBG("Notify 0xC5") + Notify(^VGBI, 0xC5) // Notify Virtual GPIO driver that Volume UP button is released. + } Else { + If(LEqual(\_SB.HIDD.HRDY, 1)) + { + \_SB.HIDD.HPEM(17) + } Else { + ADBG("IUEH") + \_SB.PCI0.GFX0.IUEH(2) + }// End of If(LEqual(\_SB.HIDD.HRDY, 1)) + } // If(LAnd(CondRefOf(^VGBI._STA)),(LEqual(And(^VGBI._STA(),One),One))) + } + + // "K" Scan Code = 0x25 + + If(LEqual(Local2,0x25)) + { + ADBG("CAS+K") + // Volume Down. If HID Event Driver loaded, use it. Otherwise, use GFX Driver. + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + ^VGBI.UPBT(VOLUME_DOWN_BUTTON, One) + ADBG("Notify 0xC6") + Notify(^VGBI, 0xC6) // Notify Virtual GPIO driver that Volue Down button is pressed. + + ^VGBI.UPBT(VOLUME_DOWN_BUTTON, Zero) + ADBG("Notify 0xC7") + Notify(^VGBI, 0xC7) // Notify Virtual GPIO driver that Volue Down button is released. + } Else { + If(LEqual(\_SB.HIDD.HRDY, 1)) + { + \_SB.HIDD.HPEM(18) + } Else { + ADBG("IUEH") + \_SB.PCI0.GFX0.IUEH(3) + } + } + } + + // "L" Scan Code = 0x26 + + If(LEqual(Local2,0x26)) + { + ADBG("CAS+L") + // Rotation Lock. If HID Event Driver loaded, use it. Otherwise, use GFX Driver. + Sleep(1000) + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + Xor(PB1E, 0x04, PB1E) // Toggle Rotation Lock Status (bit2 of PB1E) + ^VGBI.UPBT(ROTATION_LOCK_BUTTON, One) + ADBG("Notify 0xC8") + Notify(^VGBI, 0xC8) // Notify Virtual GPIO driver that Rotation Lock button is pressed. + + ^VGBI.UPBT(ROTATION_LOCK_BUTTON, Zero) + ADBG("Notify 0xC9") + Notify(^VGBI, 0xC9) // Notify Virtual GPIO driver that Rotation Lock button is released. + } Else { + If(LEqual(\_SB.HIDD.HRDY, 1)) + { + \_SB.HIDD.HPEM(2) + } Else { + ADBG("IUEH") + \_SB.PCI0.GFX0.IUEH(4) + } + } + } + + // ";" Scan Code = 0x27 + If(LEqual(Local2,0x27)) + { + ADBG("CAS+;") + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + Xor(PB1E, 0x08, PB1E) // Toggle Slate/Laptop Lock Status + If(And(PB1E, 0x08)) // Slave/Laptop Mode changed 0 -> 1 Laptop mode + { + ^VGBI.UPBT(CONVERTIBLE_BUTTON, One) + ADBG("Notify 0xCD") + Notify(^VGBI, 0xCD) // Notify Virtual GPIO driver that the system is now in Laptop mode. + } Else { // Slave/Laptop Mode Changed 1 -> 0 Slate/Tablet Mode + ^VGBI.UPBT(CONVERTIBLE_BUTTON, Zero) + ADBG("Notify 0xCC") + Notify(^VGBI, 0xCC) // Notify Virtual GPIO driver that the system is now in Slate/Tablet mode. + } + } Else { + \_SB.PCI0.GFX0.IUEH(6) // Convertible Indicator lock + } + } + + // "'" Scan Code = 0x28 + If(LEqual(Local2,0x28)) + { + ADBG("CAS+'") + + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + Xor(PB1E, 0x10, PB1E) // Toggle Dock/Undock Status + If(And(PB1E, 0x10)) // Dock/Undock status changed 0 -> 1 Dock mode + { + ^VGBI.UPBT(DOCK_INDICATOR, One) + ADBG("Notify 0xCA") + Notify(^VGBI, 0xCA) // Notify Virtual GPIO driver that the system is now in Dock mode. + } Else { // Dock/Undock status Changed 1 -> 0 Undock mode + ^VGBI.UPBT(DOCK_INDICATOR, Zero) + ADBG("Notify 0xCB") + Notify(^VGBI, 0xCB) // Notify Virtual GPIO driver that the system is now in Undock mode. + } + } Else { + \_SB.PCI0.GFX0.IUEH(7) // Docking Indicator lock + } + } + + // F1 Scan Code = 0x3B + If(LEqual(Local2,0x3B)) // EC passes directly to kbd buffer, Windows handles this + { + ADBG("FN+F1") // Sleep + If(LEqual(BID,BRH)) // BoardIdReedHarborTdv + { + ADBG("Sleep") + } Else { + If(IGDS) + { + \_SB.PCI0.GFX0.GHDS(0) // GMCH SCI hotkey display switch, table index 0 + } + } + } + + // F2 Scan Code = 0x3C + If(LEqual(Local2,0x3C)) + { + ADBG("FN+F2") + If(LEqual(BID,BRH)){ // BoardIdReedHarborTdv +// TODO: Display Sleep for Reed Harbor + ADBG("Display Sleep") + } Else { + If(IGDS) // all other boards + { + \_SB.PCI0.GFX0.GHDS(1) // GMCH SCI hotkey display switch, table index 1 + } + } + } + + // F3 Scan Code = 0x3D + If(LEqual(Local2,0x3D)) + { + ADBG("FN+F3") + If(LEqual(BID,BRH)){ // BoardIdReedHarborTdv +// TODO: GPIO_57 RFKILL for WiFi for Reed Harbor + ADBG("RFKILL") + } Else { + If(IGDS) // all other boards + { + \_SB.PCI0.GFX0.GHDS(2) // GMCH SCI hotkey display switch, table index 2 + } + } + } + + // F4 Scan Code = 0x3E + If(LEqual(Local2,0x3E)) + { + ADBG("FN+F4") + // BoardIdReedHarborTdv + If(LEqual(BID,BRH)) // Hot Key decrease brightness. + { + If(And(4,DSEN)) + { + BRTN(0x87) + } Else { + Store(BRTL, Local0) + // Current brightness is a percentage. + // This must be done if ALS if enabled, as the driver will change the brightness based on ambient light. + Store(\_SB.PCI0.GFX0.CBLV, BRTL) + // 1 % will be lost in the conversion so need to make sure we account for it. + AND(Add(BRTL, 1),0xFE, BRTL) + If(LGreaterEqual(BRTL, 10)) + { + Subtract(BRTL, 10, BRTL) + } + \_SB.PCI0.GFX0.AINT(1, BRTL) + } + } Else { // Hot Key Display Switch for all other boards. + If(IGDS) + { + \_SB.PCI0.GFX0.GHDS(3) // GMCH SCI hotkey display switch, table index 3 + } + } + } + + If(LEqual(BID,BRH)) // BoardIdReedHarborTdv + { + // F5 Scan Code = 0x3F + If(LEqual(Local2,0x3F)) + { + ADBG("FN+F5") // brightness up + If(And(4,DSEN)) + { + BRTN(0x86) + } Else { + Store(BRTL, Local0) + // Current brightness is a percentage. + // This must be done if ALS if enabled, as the driver will change the brightness based on ambient light. + Store(\_SB.PCI0.GFX0.CBLV, BRTL) + // 1 % will be lost in the conversion so need to make sure we account for it. + AND(Add(BRTL, 1),0xFE, BRTL) + If(LLessEqual(BRTL, 90)) + { + Add(BRTL, 10, BRTL) + } + \_SB.PCI0.GFX0.AINT(1, BRTL) + } + } // end If(LEqual(Local2,0x3E)) + } Else { // all other boards + // Virtual Battery Hot Keys(VBHK) - VBHK uses keys 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, -, + and F5. + If(LEqual(BNUM,0)) // Check for Virtual Battery Mode before testing the hot-keys specific to Virtual Battery Support. + { + VBHK() // remove this call if no virtual battery is needed. + } + } + + // F6 Scan Code = 0x40 + If(LEqual(Local2,0x40)) + { + ADBG("FN+F6") + If(LEqual(BID,BRH)) // BoardIdReedHarborTdv + { + If(IGDS) // toggle display + { + \_SB.PCI0.GFX0.GHDS(0) // GMCH SCI hotkey display switch, table index 0 + } + } Else { + If(IGDS) // Cycle Brightness for all other boards + { + If(CondRefOf(HGAS)) + { + HGAS() + } Else { + If(And(4,DSEN)) + { + BRTN(0x85) + } + } + } + } + } + + // Disable these Function keys for Reed Harbor. + If(LEqual(BID,BRH)) // BoardIdReedHarborTdv + { + // F7 Scan Code = 0x41 + If(LEqual(Local2,0x41)) // EC passes directly to kbd buffer + { + ADBG("FN+F7") // mute + } + // F8 Scan Code = 0x42 + If(LEqual(Local2,0x42)) // EC passes directly to kbd buffer + { + ADBG("FN+F8") // volume down + } + // F9 Scan Code = 0x43 + If(LEqual(Local2,0x43)) // EC passes directly to kbd buffer + { + ADBG("FN+F9") // volume up + } + // F10 Scan Code = 0x44 + If(LEqual(Local2,0x44)) // blank + { + ADBG("FN+10") + } + } Else { + + // F7 Scan Code = 0x41 + If(LEqual(Local2,0x41)) // Zero Brightness + { + If(IGDS) + { + If(CondRefOf(CHPS)) + { + CHPS() //Display the current hybrid policy on Port 80 header + } Else { + If(And(4,DSEN)) + { + BRTN(0x88) + } + } + } + } + + // F8 Scan Code = 0x42 + If(LEqual(Local2,0x42)) // Panel Fitting Hot Key. + { + If(IGDS) + { + If(CondRefOf(HPFS)) + { + HPFS() + } Else { + \_SB.PCI0.GFX0.AINT(2, 0) + } + } + } + + // F9 Scan Code = 0x43 + If(LEqual(Local2,0x43)) // Decrease Brightness Level. + { + If(CondRefOf(HBRT)) + { + HBRT(4) + } + If(IGDS) + { + If(And(4,DSEN)) + { + BRTN(0x87) + } Else { + Store(BRTL, Local0) + // Current brightness is a percentage. + // This must be done if ALS if enabled, as the driver will change the brightness based on ambient light. + Store(\_SB.PCI0.GFX0.CBLV, BRTL) + // 1 % will be lost in the conversion so need to make sure we account for it. + AND(Add(BRTL, 1),0xFE, BRTL) + If(LGreaterEqual(BRTL, 10)) + { + Subtract(BRTL, 10, BRTL) + } + \_SB.PCI0.GFX0.AINT(1, BRTL) + } + } + } + + // F10 Scan Code = 0x44 + If(LEqual(Local2,0x44)) // Increase Brightness Level. + { + If(CondRefOf(HBRT)) + { + HBRT(3) + } + If(IGDS) + { + If(And(4,DSEN)) + { + BRTN(0x86) + } Else { + Store(BRTL, Local0) + // Current brightness is a percentage. + // This must be done if ALS if enabled, as the driver will change the brightness based on ambient light. + Store(\_SB.PCI0.GFX0.CBLV, BRTL) + // 1 % will be lost in the conversion so need to make sure we account for it. + AND(Add(BRTL, 1),0xFE, BRTL) + If(LLessEqual(BRTL, 90)) + { + Add(BRTL, 10, BRTL) + } + \_SB.PCI0.GFX0.AINT(1, BRTL) + } + } + } + } // end If(LEqual(BID,BRH)) + + // "F12" Scan Code = 0x58 + If(LEqual(Local2,0x58)) + { + // Airplane Mode toggle. + If(\_SB.HIDD.HRDY) + { + \_SB.HIDD.HPEM(8) + } + } + + // Calculator (-) Key = 0x4A + + If(LEqual(Local2,0x4A)) // ACPI Debug Mode is Off. + { + Store(0,DBGS) + } + + // Calculator (+) Key = 0x4E + + If(LEqual(Local2,0x4E)) // ACPI Debug Mode is On. + { + Store(1,DBGS) + } + + // Calculator (Enter) Key = 0x1C + If(LEqual(Local2,0x1C)) // Set ACPI Break Point. + { + BreakPoint + } + + + // "D" Scan Code = 0x20 + If(LEqual(Local2,0x20)) // Virtual Dock + { + \_SB.PCI0.GFX0.GDCK(1) + } + + // "U" Scan Code = 0x16 + If(LEqual(Local2,0x16)) // Virtual Undock + { + \_SB.PCI0.GFX0.GDCK(0) + } + + // "0" Scan Code = 0x01 + If(LEqual(Local2,0x01)) // Toggle Wireless On/Off state. + { + + } + + + + // HK: "O" Scan Code = 0x18 + If(LEqual(Local2,0x18)) // CTDP Up + { + If(LAnd(CondRefOf(\_SB.PCI0.CTCU),LEqual(CTDB,1))){ // only allow this feature if it is enabled in SETUP + \_SB.PCI0.CTCU() + } + } + + // HK: "[" Scan Code = 0x1A + If(LEqual(Local2,0x1A)) // CTDP Nominal + { + If(LAnd(CondRefOf(\_SB.PCI0.CTCN),LEqual(CTDB,1))){ // only allow this feature if it is enabled in SETUP + \_SB.PCI0.CTCN() + } + } + + // HK: "]" Scan Code = 0x1B + If(LEqual(Local2,0x1B)) // CTDP Down + { + If(LAnd(CondRefOf(\_SB.PCI0.CTCD),LEqual(CTDB,1))){ // only allow this feature if it is enabled in SETUP + \_SB.PCI0.CTCD() + } + } + + // "Fn+F12" Scan Code = 0x62 + If(LEqual(Local2,0x62)) // Web-Cam power control + { + P8XH(0, 0x62) + } + + } // end Method(_Q52) hot key event + + Method(_Q54) // Power Button Event for iSCT and Control method Power Button(10sec PB Override without V-GPIO driver) + { + + P8XH(0,0x54) + + // + // iSCT and 10Sec PB Override are now mutual exclusive at least for this event. + // Make sure iSCT is enabled before notifying IAOE. + // + If(And(ICNF, 1)) + { + Notify(IAOE,0x80) + } + + // + // Check if 10sec PB Override and EC 10sec mode. + // If 10sec PB OVR is enabled but EC 10sec mode is not enabled, then BIOS has to handle + // Power button event. + // PB1E Bit0 -> Setup setting for 10sec PB OVR + // PB10 -> EC setting for 10sec PB OVR + // + If(LAnd(And(PB1E, 1), LNot(ECRD(RefOf(PB10))))){ + + // + // Check UAMS(User Absent Mode State) to notify the power button event. + // + If(UAMS){ // UAMS has a non-Zero value, means the system is under User Absent Mode. Send Wake up event. + ADBG("PB Wake up 0x02") + If(CondRefOf(\_SB.PWRB)){ + Notify(\_SB.PWRB, 0x02) + } + } Else { // UAMS is Zero, means the system is ON. Send Sleep event. + ADBG("PB Sleep 0x80") + If(CondRefOf(\_SB.PWRB)){ + Notify(\_SB.PWRB, 0x80) + } + } + } + } // end Method(_Q54) Power button event. + + Method (_Q70) // ALS "Light Intensity" event + { + P8XH(0,0x70) + + // Update the LUX Values. + + Store(ECRD(RefOf(LUXH)),LHIH) + Store(ECRD(RefOf(LUXL)),LLOW) + + If(LAnd(LEqual(ALSE,2),IGDS)) + { + // Handle the ALS event via the OpRegion method + + Store(ECRD(RefOf(LUXH)), Local0) + Or(ShiftLeft(Local0, 8), ECRD(RefOf(LUXL)), Local0) + \_SB.PCI0.GFX0.AINT(0, Local0) + Notify(ALSD,0x80) // notify MS driver of change + } + } + + Method(_QD5) // 10 second power button press. + { + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + ^VGBI.UPBT(POWER_BUTTON, One) + ADBG("Notify 0xC0") + ECMD (0x2D) // Wake up EC first. This is needed to get the release event immediately after press event. + Notify(^VGBI, 0xC0) // Notify Virtual GPIO driver that the power button is pressed. + } Else { + If(CondRefOf(\_SB.PCI0.GFX0.IUER)) + { + Store(\_SB.PCI0.GFX0.IUER, Local0) + And(Local0, 0xC0, \_SB.PCI0.GFX0.IUER) // Clear 4:0 button events on entry. + Store(\_SB.PCI0.GFX0.IUER, Local0) + Or(Local0, 0x01, \_SB.PCI0.GFX0.IUER) // Set Power Button Status = pressed. + } + } // End IF + }// End of Method + + Method(_QD6) // 10 second power button de-press. + { + If(LAnd(CondRefOf(^VGBI._STA),LEqual(And(^VGBI._STA(),One),One))) // VirtualButton driver is loaded(means it is Winblue) + { + ^VGBI.UPBT(POWER_BUTTON, Zero) + ADBG("Notify 0xC1") + Notify(^VGBI, 0xC1) // Notify Virtual GPIO driver that the power button is released. + } Else { + If(CondRefOf(\_SB.PCI0.GFX0.IUER)) + { + Store(\_SB.PCI0.GFX0.IUER, Local0) + And(Local0, 0xC0, \_SB.PCI0.GFX0.IUER) // Clear 4:0 button events on entry. + } + } + } +// +// Reed Harbor hardware buttons. +// + Method(_Q80) // Volume Up + { + If(LEqual(BID,BRH)){ // BoardIdReedHarborTdv +ADBG("Volume Up") + \_SB.PCI0.GFX0.IUEH(2) + } + } + Method(_Q81) // Volume Down + { + If(LEqual(BID,BRH)){ // BoardIdReedHarborTdv +ADBG("Volume Down") + \_SB.PCI0.GFX0.IUEH(3) + } + } + Method(_Q85) // Windows Home button + { + If(LEqual(BID,BRH)){ // BoardIdReedHarborTdv +ADBG("Windows Home") + Sleep(1000) + \_SB.PCI0.GFX0.IUEH(1) + } + } + + Method(_QF0) // Thermal Event. + { + If(LEqual(DBGS,0)) + { + // Only handle the numerous Thermal Events if + // we are NOT doing ACPI Debugging. + Notify(\_TZ.TZ00,0x80) + Notify(\_TZ.TZ01,0x80) + } + } + +Device(WDT0) // WDT Device Resource Consumption +{ + Name(_HID,EISAID("PNP0C02")) + + Name(_UID,3) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x6A4,0x6A4,0x1,0x1) // 1 Byte EC Prv Intfc. + IO(Decode16,0x6A0,0x6A0,0x1,0x1) // 1 Byte EC Prv Intfc. + }) +} + +/************************************************************************; +;* +;* Name: CHDK +;* +;* Description: Check DOCK status, returen True if Dock status equal Arg0 +;* +;************************************************************************/ + + Method(CHDK, 1) + { + // If not Mobile Platform then skip the code and return 0 + If(LEqual(ECON,1)){ + If(LEqual(ECRD(RefOf(DOCK)), Arg0)) + { // If not docked then it's hot plug + Return(1) + } + } + Return(0) + } + + // + // Hardware Button Array support + // + + Device(BIND) // Button Indicators. + { + Name(_HID, "INT33D2") + Name(_CID, "PNP0C40") + + Method(_STA, 0,Serialized) + { + If(LAnd(And(IUBE,1), LGreaterEqual(OSYS, 2012))) + { + Return(0x000F) + } + Return(0x00) + } + // + // _DSM : Device Specific Method for the Windows Compatible Button Array. + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // Arg3: Package Parameters + // + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) + { + // Compare passed in UUID to supported UUID. + + If (LEqual(Arg0, ToUUID ("DFBCF3C5-E7A5-44E6-9C1F-29C76F6E059C"))) + { + If (LEqual(0,ToInteger(Arg1))) // Revision 0. + { + Switch (ToInteger(Arg2)) // Switch to Function Index. + { + // + // Function 0, Query of supported functions. + // + + Case (0) + { + Return (Buffer() {0x03}) + } + + // + // Function 1, Windows Compatible Button Array Power Button Properties. + // + + Case (1) + { + // Only return support if platform enabled via setup. + // PB1E's Bit0 is set only when both CS and 10s PB OVR are enabled. + If(LEqual(And(PB1E, 1), 1)) + { + Return (0x07) + } + + Return(0x00) + + } + } // End Switch statement + } // End Revision check + } // End UUID check + + // If the code falls through to this point, just return a buffer of 0. + + Return (Buffer() {0x00}) + + } // End _DSM Method + } + + Device(CIND) // Convertible Indicators. + { + Name(_HID, "INT33D3") + Name(_CID, "PNP0C60") + + Method(_STA, 0,Serialized) + { + If(LAnd(And(IUCE,1), LGreaterEqual(OSYS, 2012))) + { + Return(0x000F) + } + Return(0x00) + } + } + + Device(DIND) // Docking Indicators. + { + Name(_HID, "INT33D4") + Name(_CID, "PNP0C70") + Method(_STA, 0,Serialized) + { + If(LAnd(And(IUDE,1), LGreaterEqual(OSYS, 2012))) + { + Return(0x000F) + } + Return(0x00) + } + } + + Device(VGBI) // Virtual GPIO Button "Interface." + { + + Name(_HID, EISAID("INT33D6")) // HID for Intel Virtual GPIO Button Interface. + Name(VBDS,0) + Name(ONTM,0) // Temporary variable to initialise VBDS only once in the boot + + Method(_STA,0,Serialized) + { + If(LGreaterEqual(OSYS,2013)) // Virtual Button applicable for Winblue and higher version of WinOS + { + ADBG("WinB VGBI STA") + Return(0x0F) // Device present,enabled and should be shown in UI. + } Else { + Return(0x00) // Device NOT present + } + }// End of _STA + + Method(VBDL,0,Serialized) // Virtual Button Driver Load - Refer Bios Arch Spec + { + ADBG("VBDL") + If(LEqual(And(PB1E,One),One)){ // 10 Sec Power Button Enabled in setup? + ADBG("VBDL EN") + + // + // Clear PBST so that we can hide the default power button. + // + If(CondRefOf(\_SB.PWRB.PBST)) + { + Store(0, \_SB.PWRB.PBST) + Notify(\_SB.PWRB, 1) // Device check + } + + // First send 0x74 to EC to disable _Q54 event for Power button. + If(CondRefOf(ECMD)){ + ADBG("Disable _Q54") + ECMD(0x74) + } + + // Set EC 10s enable bit. + ECWT(1, RefOf(PB10)) + + } Else { + // 10s power button disabled, clear EC 10s enable bit. + ADBG("VBDL DIS") + ECWT(0, RefOf(PB10)) + + // + // Here we know V-GPIO driver is loaded but 10s PB is disabled. + // Set PBST so that the default power button can handle the request. + // + If(CondRefOf(\_SB.PWRB.PBST)) + { + Store(1, \_SB.PWRB.PBST) + Notify(\_SB.PWRB, 1) // Device check + } + } + } + + Method(VGBS,0,Serialized) // Virtual GPIO Button Status - Refer Bios Arch Spec + { + // Bit[7] : Docking Indicatory Status + // Bit[6] : Convertible/Slate Indicator Status + // Bit[5] : Reserved + // Bit[4] : Rotation Lock Button Status + // Bit[3] : Volume Down Button Status + // Bit[2] : Volume Up Button Status + // Bit[1] : Windows Home Button Status + // Bit[0] : Power Button Status + + ADBG("VGBS") + If(LEqual(ONTM,0)) + { + // Initial setup option on VBDS and thereafter hotkeys should be updating the VBDS + if(LEqual(And(PB1E,0x04),0x04)) // Rotation Lock + { + UPBT(ROTATION_LOCK_BUTTON,One) + } + + if(LEqual(And(PB1E,0x08),0x08)) // Slate/Laptop + { + UPBT(CONVERTIBLE_BUTTON,One) + } + + if(LEqual(And(PB1E,0x10),0x10)) // Undock/Dock + { + UPBT(DOCK_INDICATOR,One) + } + Store(One,ONTM) + } + Return(VBDS) + }// End of Method + + // + // UPBT Update Button Status + // + // Arg0: Bit location of the target button + // 0: Power Button + // 1: Windows Button + // 2: Volume up Button + // 3: Volume down Button + // 4: Rotation Lock Button + // 5: Reserved + // 6: Convertible state 0 - Slate, 1 - Notebook + // 7: Dock Indicator 0 - Undock, 1 - Dock + // + // Arg1: On/Off state, 0 - Clear the target bit, 1 - Set the target bit. + // + Method(UPBT,2,Serialized) // Update Button Status + { + ShiftLeft(One, Arg0, Local0) + if(Arg1){ // Button Press/ON + Or(VBDS, Local0, VBDS) + } Else { // Button Press/OFF + And(VBDS, Not(Local0),VBDS) + } + } // End of UPBT + + Method(PBIN, 0, Serialized) + { + ADBG("VGBI PB INIT") + // + // Send EC 0x73 command to make 0x54 Power button notification is available. + // This is needed to support no Virtual GPIO driver case. + // Once the driver calls VBDL, VBDL sends 0x74(disable PB 0x54) to EC. + // + If(LAnd(And(PB1E, 1), LNot(ECRD(RefOf(PB10))))) + { + If(CondRefOf(\_SB.PWRB.PBST)) + { + Store(1, \_SB.PWRB.PBST) + Notify(\_SB.PWRB, 1) // Device check + } + If(CondRefOf(ECMD)){ + ADBG("Enable _Q54") + ECMD(0x73) // Enable Power Button 0x54 Notification + } + } + } + } // End of VGBI + +} // End H_EC + + // System Bus + +Scope(\_SB) +{ + + // Define an AC Device. + + Device(ADP1) + { + Name(_HID,"ACPI0003") + + Method(_STA) + { + If (LEqual(ECON,1)){ + Return(0x0F) + } + Return(0x00) + } + + // Return the value that determines if running + // from AC or not. + + Method(_PSR,0) + { + Return(PWRS) + } + + // Return that everything runs off of AC. + + Method(_PCL,0) + { + Return(\_SB) + } + } + + // Define a Lid Switch. + + Device(LID0) + { + Name(_HID,EISAID("PNP0C0D")) + + Method(_STA) + { + If(LEqual(ECON,1)){ + Return(0x0F) + } + Return(0x00) + } + + Method(_LID,0) + { + // 0 = Closed, 1 = Open. + + Return(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.LSTE))) + } + } + + // Define a (Control Method) Power Button. + + Device(PWRB) + { + Name(_HID,EISAID("PNP0C0C")) + + // The PRW isn't working when + // placed in any of the logical locations ( PS2K, PS2M, + // H_EC ), so a Power Button Device was created specifically + // for the WAKETIME_SCI PRW. + + // + // Power button status flag used to communicate H_EC.VBDL + // + Name(PBST, 1) + + Method(_PRW, 0) { + If(LEqual(LANP,1)){ + // + // When LAN is present, GPIO27 becomes ME GPIO(HSD 4834440). Remove PBT. + // + Return(Package(){0,0}) + } + If(LEqual(BID, BWT1)) + { + Return(Package(){27,4}) // GPI027 = GPE27 for WhiteTipMountain1 + } + If(LEqual(BID, BW1P)) + { + Return(Package(){27,4}) // GPI027 = GPE27 for WhiteTipMountain1 PPV + } + If(LEqual(BID, BW2C)) + { + Return(Package(){27,4}) // GPI027 = GPE27 for WhiteTipMountain2 + } + If(LEqual(BID, BW2P)) + { + Return(Package(){27,4}) // GPI027 = GPE27 for WhiteTipMountain2 PPV + } + If(LEqual(BID, BSPC)) + { + Return(Package(){27,4}) // GPI027 = GPE27 for SawToothPeak + } + If(LEqual(BID, BSPP)) + { + Return(Package(){27,4}) // GPI027 = GPE27 for SawToothPeak PPV + } + + Return(Package(){30,4}) //GPI14 = GPE30 = Waketime SCI for Haswell Traditional boards + } + + Method(_STA, 0) + { + If(LAnd(LEqual(ECON,1), PBST)){ + Return(0x0F) + } + Return(0x00) + } + + }//end device PWRB + + Device(HIDD) // HID Device. + { + Name(_HID,"INT33D5") // Intel Ultrabook HID Platform Event Driver. + Name(_CID,"PNP0C02") // Generic Motherboard Resources. + + Name (HBSY, 0) // HID Busy + Name (HIDX, 0) // HID Index + Name (HMDE, 0) // HID Mode + Name (HRDY, 0) // HID Ready + + Method(_STA,0,Serialized) // Status Method. + { + If(LEqual(BID, BHB)) // Hide device for HarrisBeach + { + Return(0x00) + } + Else + { + Return(0x0F) + } + } + + // + // HID Driver Descriptor Method - Called by HID Driver during initialization + // to obtain HID Descriptor information. + // + // Input: None + // + // Output: Package containing a complete HID Descriptor information. + // + Method(HDDM,0,Serialized) + { + // Placeholder. + Name(DPKG, Package(4) {0x11111111, 0x22222222, 0x33333333, 0x44444444}) + Return(DPKG) + } + + // + // HID Driver Event Method - Called by HID Driver to get the specific + // platform event. + // + // Input: None + // + // Output: Plastform HID Event. + // Mode 0 = Index of HID Input Report, per pre-defined Table. + // Mode 1 = Package containing a complete HID Input Report. + // + Method(HDEM,0,Serialized) + { + Store(0,HBSY) // Clear HID Busy. + // Simple Mode is hardcoded for now. Return Simple Mode HID Index Value. + If(LEqual(HMDE,0)) + { + Return(HIDX) + } + Return(HMDE) + } + + // + // HID Driver Mode Method - Called by HID Driver during initialization to get + // the platform mode of operation. + // + // Input: None + // + // Output: Mode the platform is running in. + // 0 = Simple Mode. + // 1 = Advanced Mode. + // + Method(HDMM,0,Serialized) + { + Return(HMDE) // Return Mode of operation. + } + + // + // HID Driver Status Method - called by HID Driver to report platform readiness status. + // Input: Driver Status. + // 0 = Driver Unloaded. + // 1 = Driver Loaded and Ready. + // + // Output: None + // + Method(HDSM,1,Serialized) + { + Store(Arg0,HRDY) // Store HID Ready Status. + // Eventually code will communicate to platform the Driver status (enabled/disabled). + } + + // + // HID Platform Event Method - called by Platform to communicate HID Event to Driver. + // Input: + // Mode 0 = Index of HID Event. + // Mode 1 = Package containing a complete HID Report. + // + Method(HPEM,1,Serialized) // HID Platform Event Method. + { + Store(1,HBSY) // Set HID Busy. + // Simple Mode is hardcoded for now. Simply store HID Index value. + If(LEqual(HMDE,0)) + { + Store(Arg0,HIDX) + } Else { + Store(Arg0,HIDX) + } + Notify(\_SB.HIDD,0xC0) // Notify Driver to get HID Event. + Store(0,Local0) // Initialize Local0 as a timeout counter. + While(LAnd(LLess(Local0,250),HBSY)) // Wait <= 1 second for Driver to ACK success. + { + Sleep(4) // Delay 4 ms. + Increment(Local0) // Increment Timeout. + } + If(LEqual(HBSY,1)) // Failure? + { + Store(0,HBSY) // Yes. Clear HID Busy Flag. + Store(0,HIDX) // Set HID Simple Mode Index = 0 = Undefined. + Return(1) // Return Failure. + } Else { + Return(0) // Return Success. + } + } + } + + +}//end scope _SB + + diff --git a/ReferenceCode/AcpiTables/Dsdt/GloblNvs.asl b/ReferenceCode/AcpiTables/Dsdt/GloblNvs.asl new file mode 100644 index 0000000..07f4381 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/GloblNvs.asl @@ -0,0 +1,560 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + + + // Define a Global region of ACPI NVS Region that may be used for any + // type of implementation. The starting offset and size will be fixed + // up by the System BIOS during POST. Note that the Size must be a word + // in size to be fixed up correctly. + + OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55) + Field(GNVS,AnyAcc,Lock,Preserve) + { + Offset(0), // Miscellaneous Dynamic Registers: + OSYS, 16, // (000) Operating System + SMIF, 8, // (002) SMI Function Call (ASL to SMI via I/O Trap) + PRM0, 8, // (003) SMIF - Parameter 0 + PRM1, 8, // (004) SMIF - Parameter 1 + SCIF, 8, // (005) SCI Function Call (SMI to ASL via _L00) + PRM2, 8, // (006) SCIF - Parameter 0 + PRM3, 8, // (007) SCIF - Parameter 1 + LCKF, 8, // (008) Global Lock Function Call (EC Communication) + PRM4, 8, // (009) LCKF - Parameter 0 + PRM5, 8, // (010) LCKF - Parameter 1 + P80D, 32, // (011) Port 80 Debug Port Value + PWRS, 8, // (015) Power State (AC Mode = 1) + DBGS, 8, // (016) Debug State + Offset(17), // Thermal Policy Registers: + THOF, 8, // (017) Enable Thermal Offset for KSC + ACT1, 8, // (018) Active Trip Point 1 + ACTT, 8, // (019) Active Trip Point + PSVT, 8, // (020) Passive Trip Point + TC1V, 8, // (021) Passive Trip Point TC1 Value + TC2V, 8, // (022) Passive Trip Point TC2 Value + TSPV, 8, // (023) Passive Trip Point TSP Value + CRTT, 8, // (024) Critical Trip Point + DTSE, 8, // (025) Digital Thermal Sensor Enable + DTS1, 8, // (026) Digital Thermal Sensor 1 Reading + DTS2, 8, // (027) Digital Thermal Sensor 2 Reading + DTSF, 8, // (028) DTS SMI Function Call + Offset(30), // Battery Support Registers: (Moved outside this ASL code but still in used) +// BNUM, 8, // (030) Battery Number Present +// B0SC, 8, // (031) Battery 0 Stored Capacity +// B1SC, 8, // (032) Battery 1 Stored Capacity +// B2SC, 8, // (033) Battery 2 Stored Capacity +// B0SS, 8, // (034) Battery 0 Stored Status +// B1SS, 8, // (035) Battery 1 Stored Status +// B2SS, 8, // (036) Battery 2 Stored Status + Offset(37), // Revision Field: + REVN, 8, // (037) Revison of GlobalNvsArea + Offset(40), // CPU Identification Registers: + APIC, 8, // (040) APIC Enabled by SBIOS (APIC Enabled = 1) + TCNT, 8, // (041) Number of Enabled Threads + PCP0, 8, // (042) PDC Settings, Processor 0 + PCP1, 8, // (043) PDC Settings, Processor 1 + PPCM, 8, // (044) Maximum PPC state + PPMF, 32, // (045) PPM Flags (Same as CFGD) + C67L, 8, // (049) C6/C7 Entry/Exit latency + Offset(50), // SIO CMOS Configuration Registers: + NATP, 8, // (050) National SIO Present + CMAP, 8, // (051) COM A Port + CMBP, 8, // (052) COM B Port + LPTP, 8, // (053) LPT Port + FDCP, 8, // (054) FDC Port + CMCP, 8, // (055) SMSC Com Port + CIRP, 8, // (056) SMSC Com CIR Port + SMSC, 8, // (057) SMSC1007 SIO Present + W381, 8, // (058) WPCN381U SIO Present + SMC1, 8, // (059) SMSC1000 SIO Present + EMAE, 8, // (060) EMA Enable + EMAP, 16, // (061) EMA Pointer + EMAL, 16, // (063) EMA Length + Offset(66), // MEF Registers: + MEFE, 8, // (066) MEF Enable + Offset(67), // PCIe Dock: + DSTS, 8, // (067) PCIe Dock Status + Offset(72), // TPM Registers: + MORD, 8, // (072) Memory Overwrite Request Data + TCGP, 8, // (073) Used for save the Mor and/or physical presence paramter + PPRP, 32, // (074) Physical Presence request operation response + PPRQ, 8, // (078) Physical Presence request operation + LPPR, 8, // (079) Last Physical Presence request operation + Offset(80), // SATA Registers: + GTF0, 56, // (080) GTF Task File Buffer for Port 0 + GTF2, 56, // (087) GTF Task File Buffer for Port 2 + IDEM, 8, // (094) IDE Mode (Compatible\Enhanced) + GTF1, 56, // (095) GTF Task File Buffer for Port 1 + BID, 16, // (102) Platform board id + PLID, 8, // (104) Platform id + ECTG, 8, // (105) Toggle EC + Offset(112), + OSCC, 8, // (112) PCIE OSC Control + NEXP, 8, // (113) Native PCIE Setup Value + Offset(114), + SBV1, 8, // (114) USB Sideband Deferring GPE Vector (HOST_ALERT#1) + SBV2, 8, // (115) USB Sideband Deferring GPE Vector (HOST_ALERT#2) + Offset(122), // Global Variables + DSEN, 8, // (122) _DOS Display Support Flag. + ECON, 8, // (123) Embedded Controller Availability Flag. + GPIC, 8, // (124) Global IOAPIC/8259 Interrupt Mode Flag. + CTYP, 8, // (125) Global Cooling Type Flag. + L01C, 8, // (126) Global L01 Counter. + VFN0, 8, // (127) Virtual Fan0 Status. + VFN1, 8, // (128) Virtual Fan1 Status. + VFN2, 8, // (129) Virtual Fan2 Status. + VFN3, 8, // (130) Virtual Fan3 Status. + VFN4, 8, // (131) Virtual Fan4 Status. + VFN5, 8, // (132) Virtual Fan5 Status. + VFN6, 8, // (133) Virtual Fan6 Status. + VFN7, 8, // (134) Virtual Fan7 Status. + VFN8, 8, // (135) Virtual Fan8 Status. + VFN9, 8, // (136) Virtual Fan9 Status. + + Offset(143), + ATMC, 8, // (143) Active Trip Point for MCH + PTMC, 8, // (144) Passive Trip Point for MCH + ATRA, 8, // (145) Active Trip Point for TMEM + PTRA, 8, // (146) Passive Trip Point for TMEM + PNHM, 32, // (147) CPUID Feature Information [EAX] + TBAB, 32, // (151) Thermal Base Low Address for BIOS + TBAH, 32, // (155) Thermal Base High Address for BIOS + RTIP, 8, // (159) Run Time Interface for Intelligent Power Savings + TSOD, 8, // (160) TS-on-DIMM is chosen in SETUP and present on the DIMM + ATPC, 8, // (161) Active Trip Point for PCH + PTPC, 8, // (162) Passive Trip Point for PCH + PFLV, 8, // (163) Platform Flavor + BREV, 8, // (164) Board Rev + Offset(165), + PDTS, 8, // (165) Package Temperature + PKGA, 8, // (166) Package Temperature MSR available + PAMT, 8, // (167) Peci Access Method + AC0F, 8, // (168) _AC0 Fan Speed + AC1F, 8, // (169) _AC1 Fan Speed + DTS3, 8, // (170) Digital Thermal Sensor 3 Reading + DTS4, 8, // (171) Digital Thermal Sensor 4 Reading + Offset(176), // (172):(175) are reserved for future use + LTR1, 8, // (176) Latency Tolerance Reporting Enable + LTR2, 8, // (177) Latency Tolerance Reporting Enable + LTR3, 8, // (178) Latency Tolerance Reporting Enable + LTR4, 8, // (179) Latency Tolerance Reporting Enable + LTR5, 8, // (180) Latency Tolerance Reporting Enable + LTR6, 8, // (181) Latency Tolerance Reporting Enable + LTR7, 8, // (182) Latency Tolerance Reporting Enable + LTR8, 8, // (183) Latency Tolerance Reporting Enable + Offset(184), + OBF1, 8, // (184) Optimized Buffer Flush and Fill + OBF2, 8, // (185) Optimized Buffer Flush and Fill + OBF3, 8, // (186) Optimized Buffer Flush and Fill + OBF4, 8, // (187) Optimized Buffer Flush and Fill + OBF5, 8, // (188) Optimized Buffer Flush and Fill + OBF6, 8, // (189) Optimized Buffer Flush and Fill + OBF7, 8, // (190) Optimized Buffer Flush and Fill + OBF8, 8, // (191) Optimized Buffer Flush and Fill + Offset (192), + XHCI, 8, // (192) xHCI controller mode + XTUB, 32, // (193) XTU Continous structure Base Address + XTUS, 32, // (197) XMP Size + XMPB, 32, // (201) XMP Base Address + DDRF, 8, // (205) DDR Reference Frequency + + RTD3, 8, // (206) Runtime D3 support. + PEP0, 8, // (207) User selctable Delay for Device D0 transition. + PEP3, 8, // (208) User selctable Delay for Device D3 transition. + // + // DPTF Devices and trip points + // + DPTF, 8, // (209) EnableDptf + + SADE, 8, // (210) EnableSaDevice + SACR, 8, // (211) CriticalThermalTripPointSa + SAHT, 8, // (212) HotThermalTripPointSa + + PCHD, 8, // (213) EnablePchDevice + PCHC, 8, // (214) CriticalThermalTripPointPch + PCHH, 8, // (215) HotThermalTripPointPch + // + // DPTF Policies + // + CTDP, 8, // (216) EnableCtdpPolicy + LPMP, 8, // (217) EnableLpmPolicy + LPMV, 8, // (218) CurrentLowPowerMode for LPM + ECEU, 8, // (219) EnableCurrentExecutionUnit + TGFG, 16, // (220) TargetGfxFreq + // + // DPPM Devices and trip points + // + MEMD, 8, // (222) EnableMemoryDevice + MEMC, 8, // (223) CriticalThermalTripPointTMEM + MEMH, 8, // (224) HotThermalTripPointTMEM + + FND1, 8, // (225) EnableFan1Device + FND2, 8, // (226) EnableFan2Device + + AMBD, 8, // (227) EnableAmbientDevice + AMAT, 8, // (228) ActiveThermalTripPointAmbient + AMPT, 8, // (229) PassiveThermalTripPointAmbient + AMCT, 8, // (230) CriticalThermalTripPointAmbient + AMHT, 8, // (231) HotThermalTripPointAmbient + + SKDE, 8, // (232) EnableSkinDevice + SKAT, 8, // (233) ActiveThermalTripPointSkin + SKPT, 8, // (234) PassiveThermalTripPointSkin + SKCT, 8, // (235) CriticalThermalTripPointSkin + SKHT, 8, // (236) HotThermalTripPointSkin + + EFDE, 8, // (237) EnableExhaustFanDevice + EFAT, 8, // (238) ActiveThermalTripPointExhaustFan + EFPT, 8, // (239) PassiveThermalTripPointExhaustFan + EFCT, 8, // (240) CriticalThermalTripPointExhaustFan + EFHT, 8, // (241) HotThermalTripPointExhaustFan + + VRDE, 8, // (242) EnableVRDevice + VRAT, 8, // (243) ActiveThermalTripPointVR + VRPT, 8, // (244) PassiveThermalTripPointVR + VRCT, 8, // (245) CriticalThermalTripPointVR + VRHT, 8, // (246) HotThermalTripPointVR + // + // DPPM Policies + // + DPAP, 8, // (247) EnableActivePolicy + DPPP, 8, // (248) EnablePassivePolicy + DPCP, 8, // (249) EnableCriticalPolicy + DCMP, 8, // (250) EnableCoolingModePolicy + TRTV, 8, // (251) TrtRevision + // + // CLPO (Current Logical Processor Off lining Setting) + // + LPOE, 8, // (252) LPOEnable + LPOP, 8, // (253) LPOStartPState + LPOS, 8, // (254) LPOStepSize + LPOW, 8, // (255) LPOPowerControlSetting + LPER, 8, // (256) LPOPerformanceControlSetting + // + // Miscellaneous DPTF + // + PPSZ, 32, // (257) PPCC Step Size + DISE, 8, // (261) EnableDisplayParticipant + // + // PFAT + // + PFMA, 64, // (262) PFAT Memory Address for Tool Interface + PFMS, 8, // (270) PFAT Memory Size for Tool Interface + PFIA, 16, // (271) PFAT IoTrap Address for Tool Interface + // + // ISCT + // + ICNF, 8, // (273) Isct Configuration + // + // ADSP + // + DSP0, 32, // (274) Audio DSP BAR0 + DSP1, 32, // (278) Audio DSP BAR1 + // + // NFC + // + NFCE, 8, // (282) NFC module selection + // + // ADSP Codec Selection + // + CODS, 8, // (283) Audio Codec selection + // + // Sensor Hub Enable + // + SNHE, 8, // (284) Sensor Hub Enable + + S0ID, 8, // (285) Low Power S0 Idle Enable + + // + // BIOS only version of Config TDP + // + CTDB, 8, // (286) enable/disable BIOS only version of Config TDP + + Offset(519), + PWRE, 8, // (519) EnablePowerDevice + PWRP, 8, // (520) EnablePowerPolicy + XHPR, 8, // (521) RTD3 USB Power Resource config + // + // Intel Serial(R) IO Sensor Device Selection + // + SDS0, 8, // (522) I2C0 Sensor Device Selection + SDS1, 16, // (523) I2C1 Sensor Device Selection + SDS2, 8, // (525) SPI0 Sensor Device Selection + SDS3, 8, // (526) SPI1 Sensor Device Selection + SDS4, 8, // (527) UART0 Sensor Device Selection + SDS5, 8, // (528) UART1 Sensor Device Selection + Offset(530), // 529 no longer used + RIC0, 8, // (530) RTD3 support for I2C0 SH + PEPY, 8, // (531) RTD3 PEP support list(BIT0 - GFx , BIT1 - Sata, BIT2 - UART, BIT3 - SDHC, Bit4 - I2C0, BIT5 - I2C1, Bit6 - XHCI, Bit7 - Audio) + DVS0, 8, // (532) Port0 DevSlp Enable + DVS1, 8, // (533) Port1 DevSlp Enable + DVS2, 8, // (534) Port2 DevSlp Enable + DVS3, 8, // (535) Port3 DevSlp Enable + GBSX, 8, // (536) Virtual GPIO button Notify Sleep State Change + IUBE, 8, // (537) IUER Button Enable + IUCE, 8, // (538) IUER Convertible Enable + IUDE, 8, // (539) IUER Dock Enable + ECNO, 8, // (540) EC Notification of Low Power S0 Idle State + AUDD, 16, // (541) RTD3 Audio Codec device delay + DSPD, 16, // (543) RTD3 ADSP device delay + IC0D, 16, // (545) RTD3 SensorHub delay time after applying power to device + IC1D, 16, // (547) RTD3 TouchPanel delay time after applying power to device + IC1S, 16, // (549) RTD3 TouchPad delay time after applying power to device + VRRD, 16, // (551) VR Ramp up delay + PSCP, 8, // (553) P-state Capping + RWAG, 8, // (554) Rtd3 W/A Gpio, allow W/A for port 1 and 6 to use GPIO from SDHC device + I20D, 16, // (555) Delay in _PS0 after powering up I2C0 Controller + I21D, 16, // (557) Delay in _PS0 after powering up I2C1 Controller + + Offset(561), + RCG0, 8 , // (561) RTD3 Config Setting(BIT0:ZPODD,BIT1:USB Camera Port4, BIT2/3:SATA Port3) + ECDB, 8, // (562) EC Debug Light (CAPS LOCK) for when in Low Power S0 Idle State + P2ME, 8, // (563) Ps2 Mouse Enable + + SSH0, 16, // (564) SSCN-LOW for I2C0 + SSL0, 16, // (566) SSCN-HIGH for I2C0 + SSD0, 16, // (568) SSCN-HOLD for I2C0 + FMH0, 16, // (570) FMCN-LOW for I2C0 + FML0, 16, // (572) FMCN-HIGH for I2C0 + FMD0, 16, // (574) FMCN-HOLD for I2C0 + FPH0, 16, // (576) FPCN-LOW for I2C0 + FPL0, 16, // (578) FPCN-HIGH for I2C0 + FPD0, 16, // (580) FPCN-HOLD for I2C0 + SSH1, 16, // (582) SSCN-LOW for I2C1 + SSL1, 16, // (584) SSCN-HIGH for I2C1 + SSD1, 16, // (586) SSCN-HOLD for I2C1 + FMH1, 16, // (588) FMCN-LOW for I2C1 + FML1, 16, // (590) FMCN-HIGH for I2C1 + FMD1, 16, // (592) FMCN-HOLD for I2C1 + FPH1, 16, // (594) FPCN-LOW for I2C1 + FPL1, 16, // (596) FPCN-HIGH for I2C1 + FPD1, 16, // (598) FPCN-HOLD for I2C1 + M0C0, 16, // (600) M0D3 for I2C0 + M1C0, 16, // (602) M1D3 for I2C0 + M2C0, 16, // (604) M0D0 for I2C0 + M0C1, 16, // (606) M0D3 for I2C1 + M1C1, 16, // (608) M1D3 for I2C1 + M2C1, 16, // (610) M0D0 for I2C1 + M0C2, 16, // (612) M0D3 for SPI0 + M1C2, 16, // (614) M1D3 for SPI0 + M0C3, 16, // (616) M0D3 for SPI1 + M1C3, 16, // (618) M1D3 for SPI1 + M0C4, 16, // (620) M0D3 for UA00 + M1C4, 16, // (622) M1D3 for UA00 + M0C5, 16, // (624) M0D3 for UA01 + M1C5, 16, // (626) M1D3 for UA01 + TBSF, 8, // (628) ThunderBolt SMI Function Number + GIRQ, 32, // (629) GPIO IRQ + DMTP, 8, // (633) PIRQS 34,50(GPIO) + DMTD, 8, // (634) PIRQX 39,55(GPIO) + DMSH, 8, // (635) PIRQM 28,14(GPIO) + LANP, 8, // (636) LAN PHY Status 0 = Not Present, 1 = Present + Offset(638), // 637 no longer used. + SHSB, 8, // (638) Sensor Standby mode + PLCS, 8, // (639) set PL1 limit when entering CS + PLVL, 16, // (640) PL1 limit value + GN1E, 8, // (642) EnableGen1Participant + G1AT, 8, // (643) ActiveThermalTripPointGen1 + G1PT, 8, // (644) PassiveThermalTripPointGen1 + G1CT, 8, // (645) CriticalThermalTripPointGen1 + G1HT, 8, // (646) HotThermalTripPointGen1 + GN2E, 8, // (647) EnableGen2Participant + G2AT, 8, // (648) ActiveThermalTripPointGen2 + G2PT, 8, // (649) PassiveThermalTripPointGen2 + G2CT, 8, // (650) CriticalThermalTripPointGen2 + G2HT, 8, // (651) HotThermalTripPointGen2 + WWSD, 8, // (652) EnableWwanTempSensorDevice + CVSD, 8, // (653) EnableCpuVrTempSensorDevice + SSDD, 8, // (654) EnableSsdTempSensorDevice + INLD, 8, // (655) EnableInletFanTempSensorDevice + IFAT, 8, // (656) ActiveThermalTripPointInletFan + IFPT, 8, // (657) PassiveThermalTripPointInletFan + IFCT, 8, // (658) CriticalThermalTripPointInletFan + IFHT, 8, // (659) HotThermalTripPointInletFan + DOSD, 8, // (660) DMA OS detection, 1 = check for OS version when enabling DMA, 0 = don't care about OS + USBH, 8, // (661) USB Sensor Hub Enable/Disable + BCV4, 8, // (662) Broadcom's Bluetooth adapter's revision + WTV0, 8, // (663) I2C0/WITT devices version + WTV1, 8, // (664) I2C1/WITT devices version + APFU, 8, // (665) Atmel panel FW update Enable/Disable + SOHP, 8, // (666) SMI on Hot Plug for TBT devices + NOHP, 8, // (667) Notify on Hot Plug for TBT devices + TBSE, 8, // (668) ThunderBolt Root port selector + WKFN, 8, // (669) WAK Finished + PEPC, 16, // (670) PEP Constraints + VRSD, 16, // (672) VR Staggering delay + PB1E, 8, // (674) 10sec Power button support Bit0: 10 sec P-button Enable/Disable + // Bit1: Internal Flag + // Bit2: Rotation Lock flag, 0:unlock, 1:lock + // Bit3: Slate/Laptop Mode Flag, 0: Slate, 1: Laptop + // Bit4: Undock / Dock Flag, 0: Undock, 1: Dock + // Bit5, 6: reserved for future use. + // Bit7: EC 10sec PB Override state for S3/S4 wake up. + WAND, 8, // (675) EnableWWANParticipant + WWAT, 8, // (676) ActiveThermalTripPointWWAN + WWPT, 8, // (677) PassiveThermalTripPointWWAN + WWCT, 8, // (678) CriticalThermalTripPointWWAN + WWHT, 8, // (679) HotThermalTripPointWWAN + Offset(685), + MPLT, 16, // (685) Minimum Power Limit for DPTF use via PPCC Object + GR13, 8, // (687) GPIO13 Rework for Sawtooth Peak + SPST, 8, // (688) SATA port state, Bit0 - Port0, Bit1 - Port1, Bit2 - Port2, Bit3 - Port3 + ECLP, 8, // (689) EC Low Power Mode: 1 - Enabled, 0 - Disabled + INSC, 8, // (690) Intel RMT Configuration + } + +#if defined(ASL_Remove_SaSsdt_Data_To_Dsdt) && (ASL_Remove_SaSsdt_Data_To_Dsdt == 1) +/// +/// Below Data structure is copy from SaSsdt.asl +/// + OperationRegion(SANV,SystemMemory,0xFFFF0000,0xAA55) + Field(SANV,AnyAcc,Lock,Preserve) + { + SARV, 32, /// (000) SA RC Revision + ASLB, 32, /// (004) IGD OpRegion base address + IMON, 8, /// (008) IMON Current Value + IGDS, 8, /// (009) IGD State (Primary Display = 1) + CADL, 8, /// (010) Current Attached Device List + PADL, 8, /// (011) Previous Attached Device List + CSTE, 16, /// (012) Current Display State + NSTE, 16, /// (014) Next Display State + DID9, 32, /// (016) Device Id 9 + DIDA, 32, /// (020) Device Id 10 + DIDB, 32, /// (024) Device Id 11 + IBTT, 8, /// (028) IGD Boot Display Device + IPAT, 8, /// (029) IGD Panel Type CMOs option + IPSC, 8, /// (030) IGD Panel Scaling + IBLC, 8, /// (031) IGD BLC Configuration + IBIA, 8, /// (032) IGD BIA Configuration + ISSC, 8, /// (033) IGD SSC Configuration + IPCF, 8, /// (034) IGD Power Conservation Feature Flag + IDMS, 8, /// (035) IGD DVMT Memory Size + IF1E, 8, /// (036) IGD Function 1 Enable + HVCO, 8, /// (037) HPLL VCO + NXD1, 32, /// (038) Next state DID1 for _DGS + NXD2, 32, /// (042) Next state DID2 for _DGS + NXD3, 32, /// (046) Next state DID3 for _DGS + NXD4, 32, /// (050) Next state DID4 for _DGS + NXD5, 32, /// (054) Next state DID5 for _DGS + NXD6, 32, /// (058) Next state DID6 for _DGS + NXD7, 32, /// (062) Next state DID7 for _DGS + NXD8, 32, /// (066) Next state DID8 for _DGS + GSMI, 8, /// (070) GMCH SMI/SCI mode (0=SCI) + PAVP, 8, /// (071) IGD PAVP data + LIDS, 8, /// (072) Lid State (Lid Open = 1) + KSV0, 32, /// (073) First four bytes of AKSV (mannufacturing mode) + KSV1, 8, /// (077) Fifth byte of AKSV (mannufacturing mode) + BBAR, 32, /// (078) IGFX Audio (D3F0) MMIO BAR Address + BLCS, 8, /// (082) Backlight Control Support + BRTL, 8, /// (083) Brightness Level Percentage + ALSE, 8, /// (084) ALS Enable + ALAF, 8, /// (085) Ambient Light Adjusment Factor + LLOW, 8, /// (086) LUX Low Value + LHIH, 8, /// (087) LUX High Value + ALFP, 8, /// (088) Active LFP + AUDA, 32, /// (089) Audio MMIO WA 1 + AUDB, 32, /// (093) Audio MMIO WA 2 + AUDC, 32, /// (097) Audio MMIO WA 3 + DIDC, 32, /// (101) Device Id 12 + DIDD, 32, /// (105) Device Id 13 + DIDE, 32, /// (109) Device Id 14 + DIDF, 32, /// (113) Device Id 15 +//AMI_OVERRIDE --- Change name from CADR to CCSA to fix that the system has BsOD issue. It is due to the name(CADR) is conflict with AMI Aptio definition name. >> + CCSA, 32, /// (117) Codec Save Address + CCNT, 32, /// (121) Codec Save Count +//CADR, 32, /// (117) Codec Save Address +//CCNT, 8, /// (121) Codec Save Count +//AMI_OVERRIDE --- << + /// + /// Switchable Graphics Info + /// + Offset(200), + SGMD, 8, /// (200) SG Mode (0=Disabled, 1=SG Muxed, 2=SG Muxless, 3=DGPU Only) + SGFL, 8, /// (201) SG Feature List + PWOK, 8, /// (202) dGPU PWROK GPIO assigned + HLRS, 8, /// (203) dGPU HLD RST GPIO assigned + PWEN, 8, /// (204) dGPU PWR Enable GPIO assigned + PRST, 8, /// (205) dGPU Present Detect GPIO assigned + CPSP, 32, /// (206) PEG Endpoint Capability Structure Presence (Bit 0: Virtual Channel Capability) + EECP, 8, /// (210) PEG Endpoint PCIe Capability Structure Offset + EVCP, 16, /// (211) PEG Endpoint Virtual Channel Capability Structure Offset + XBAS, 32, /// (213) Any Device's PCIe Config Space Base Address + GBAS, 16, /// (217) GPIO Base Address + SGGP, 8, /// (219) SG GPIO Support + NVGA, 32, /// (220) NVIG opregion address + NVHA, 32, /// (224) NVHM opregion address + AMDA, 32, /// (228) AMDA opregion address + NDID, 8, /// (232) Number of Valid Device IDs + DID1, 32, /// (233) Device ID 1 + DID2, 32, /// (237) Device ID 2 + DID3, 32, /// (241) Device ID 3 + DID4, 32, /// (245) Device ID 4 + DID5, 32, /// (249) Device ID 5 + DID6, 32, /// (253) Device ID 6 + DID7, 32, /// (257) Device ID 7 + DID8, 32, /// (261) Device ID 8 + OBS1, 32, /// (265) Occupied Buses - from 0 to 31 + OBS2, 32, /// (269) Occupied Buses - from 32 to 63 + OBS3, 32, /// (273) Occupied Buses - from 64 to 95 + OBS4, 32, /// (277) Occupied Buses - from 96 to 127 + OBS5, 32, /// (281) Occupied Buses - from 128 to 159 + OBS6, 32, /// (285) Occupied Buses - from 160 to 191 + OBS7, 32, /// (289) Occupied Buses - from 192 to 223 + OBS8, 32, /// (293) Occupied Buses - from 224 to 255 + LTRA, 8, /// (297) Latency Tolerance Reporting Enable + OBFA, 8, /// (298) Optimized Buffer Flush and Fill + LTRB, 8, /// (299) Latency Tolerance Reporting Enable + OBFB, 8, /// (300) Optimized Buffer Flush and Fill + LTRC, 8, /// (301) Latency Tolerance Reporting Enable + OBFC, 8, /// (302) Optimized Buffer Flush and Fill + SMSL, 16, /// (303) SA Peg Latency Tolerance Reporting Max Snoop Latency + SNSL, 16, /// (305) SA Peg Latency Tolerance Reporting Max No Snoop Latency + P0UB, 8, /// (307) Peg0 Unused Bundle Control + P1UB, 8, /// (308) Peg1 Unused Bundle Control + P2UB, 8, /// (309) Peg2 Unused Bundle Control + EDPV, 8, /// (310) Check for eDP display device + NXDX, 32, /// (311) Next state DID for eDP + DIDX, 32, /// (315) Device ID for eDP device + PCSL, 8, /// (319) The lowest C-state for the package + SC7A, 8, /// (316) Run-time C7 Allowed feature (0=Disabled, 1=Enabled) +// AMI_OVERRIDE... + DSEL, 8, /// (319) dGPU Display Select GPIO assigned + ESEL, 8, /// (320) dGPU EDID Select GPIO assigned + PSEL, 8, /// (321) dGPU PWM Select GPIO assigned + MXD1, 32, /// (322) DID1 Mux Setting + MXD2, 32, /// (326) DID2 Mux Setting + MXD3, 32, /// (330) DID3 Mux Setting + MXD4, 32, /// (334) DID4 Mux Setting + MXD5, 32, /// (338) DID5 Mux Setting + MXD6, 32, /// (342) DID6 Mux Setting + MXD7, 32, /// (346) DID7 Mux Setting + MXD8, 32, /// (350) DID8 Mux Setting + PXFD, 8, /// (354) ATI 5.0 Fixed/Dynamic ATI 5.0 Fixed/Dynamic + EBAS, 32, /// (355) Endpoint PCIe Base Address + HYSS, 32, /// (359) dGPU SSID for MSHyBrid restore +// AMI_OVERRIDE...end. + } +#endif diff --git a/ReferenceCode/AcpiTables/Dsdt/Gpe.asl b/ReferenceCode/AcpiTables/Dsdt/Gpe.asl new file mode 100644 index 0000000..5a0b222 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/Gpe.asl @@ -0,0 +1,947 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + + // General Purpose Events. This Scope handles the Run-time and + // Wake-time SCIs. The specific method called will be determined by + // the _Lxx value, where xx equals the bit location in the General + // Purpose Event register(s). + + //AMI_OVERRIDE Fixed EIP115617 Lan wake issue >> + //External(D1F0) + //External(D1F1) + //External(D1F2) + //AMI_OVERRIDE Fixed EIP115617 Lan wake issue << +#if !defined(ASL_Remove_SaSsdt_Data_To_Dsdt) || (ASL_Remove_SaSsdt_Data_To_Dsdt == 0) + External(\_SB.PCI0.PEG0.HPME, MethodObj) + External(\_SB.PCI0.PEG1.HPME, MethodObj) + External(\_SB.PCI0.PEG2.HPME, MethodObj) +#endif + + Scope(\_GPE) + { + // Note: + // Originally, the two GPE methods below are automatically generated, but, for ASL code restructuring, + // disabled the automatic generation and declare the ASL code here. + // + +#if 0 //AMI_OVERRIDE --- PciTree.asl has this Gpe event. >> + Method(XL0B, 0) { + Notify(\_SB.PCI0.P0P1, 0x02) + } +#endif //AMI_OVERRIDE --- PciTree.asl has this Gpe event. << + + + // + // This PME event (PCH's GPE #9) is received on one or more of the PCI Express* ports or + // an assert PMEGPE message received via DMI + // + Method(XL09, 0) { + // + // If the Root Port is enabled, run PCI_EXP_STS handler + // +#if defined(ASL_RC_PORT_0) && (ASL_RC_PORT_0==1) + If(LAnd(LEqual(RP1D,0), LEqual(\_SB.PCI0.RP01.RPAV,1))) + { + \_SB.PCI0.RP01.HPME() + Notify(\_SB.PCI0.RP01, 0x02) + } +#endif // ASL_RC_PORT_0 + +#if defined(ASL_RC_PORT_1) && (ASL_RC_PORT_1==1) + If(LAnd(LEqual(RP2D,0), LEqual(\_SB.PCI0.RP02.RPAV,1))) + { + \_SB.PCI0.RP02.HPME() + Notify(\_SB.PCI0.RP02, 0x02) + } +#endif // ASL_RC_PORT_1 + +#if defined(ASL_RC_PORT_2) && (ASL_RC_PORT_2==1) + If(LAnd(LEqual(RP3D,0), LEqual(\_SB.PCI0.RP03.RPAV,1))) + { + \_SB.PCI0.RP03.HPME() + Notify(\_SB.PCI0.RP03, 0x02) + } +#endif // ASL_RC_PORT_2 + +#if defined(ASL_RC_PORT_3) && (ASL_RC_PORT_3==1) + If(LAnd(LEqual(RP4D,0), LEqual(\_SB.PCI0.RP04.RPAV,1))) + { + \_SB.PCI0.RP04.HPME() + Notify(\_SB.PCI0.RP04, 0x02) + } +#endif // ASL_RC_PORT_3 + +#if defined(ASL_RC_PORT_4) && (ASL_RC_PORT_4==1) + If(LAnd(LEqual(RP5D,0), LEqual(\_SB.PCI0.RP05.RPAV,1))) + { + \_SB.PCI0.RP05.HPME() + Notify(\_SB.PCI0.RP05, 0x02) + } +#endif // ASL_RC_PORT_4 + +#if defined(ASL_RC_PORT_5) && (ASL_RC_PORT_5==1) + If(LAnd(LEqual(RP6D,0), LEqual(\_SB.PCI0.RP06.RPAV,1))) + { + \_SB.PCI0.RP06.HPME() + Notify(\_SB.PCI0.RP06, 0x02) + } +#endif // ASL_RC_PORT_5 + +#if defined(ASL_RC_PORT_6) && (ASL_RC_PORT_6==1) + If(LAnd(LEqual(RP7D,0), LEqual(\_SB.PCI0.RP07.RPAV,1))) + { + \_SB.PCI0.RP07.HPME() + Notify(\_SB.PCI0.RP07, 0x02) + } +#endif // ASL_RC_PORT_6 + +#if defined(ASL_RC_PORT_7) && (ASL_RC_PORT_7==1) + If(LAnd(LEqual(RP8D,0), LEqual(\_SB.PCI0.RP08.RPAV,1))) + { + \_SB.PCI0.RP08.HPME() + Notify(\_SB.PCI0.RP08, 0x02) + } +#endif // ASL_RC_PORT_7 + +#if defined(ASL_RC_PEG_0) && (ASL_RC_PEG_0 == 1) + //AMI_OVERRIDE Fixed EIP115617 Lan wake issue >> + If(LEqual(\_SB.PCI0.D1F0,1)) + //AMI_OVERRIDE Fixed EIP115617 Lan wake issue << + { + \_SB.PCI0.PEG0.HPME() + Notify(\_SB.PCI0.PEG0, 0x02) + Notify(\_SB.PCI0.PEG0.PEGP, 0x02) + } +#if defined(ASL_RC_PEG_1) && (ASL_RC_PEG_1 == 1) + //AMI_OVERRIDE Fixed EIP115617 Lan wake issue >> + If(LEqual(\_SB.PCI0.D1F1,1)) + //AMI_OVERRIDE Fixed EIP115617 Lan wake issue << + { + \_SB.PCI0.PEG1.HPME() + Notify(\_SB.PCI0.PEG1, 0x02) + } +#if defined(ASL_RC_PEG_2) && (ASL_RC_PEG_2 == 1) + //AMI_OVERRIDE Fixed EIP115617 Lan wake issue >> + If(LEqual(\_SB.PCI0.D1F2,1)) + //AMI_OVERRIDE Fixed EIP115617 Lan wake issue << + { + \_SB.PCI0.PEG2.HPME() + Notify(\_SB.PCI0.PEG2, 0x02) + } +#endif // ASL_RC_PEG_2 +#endif // ASL_RC_PEG_1 +#endif // ASL_RC_PEG_0 + } + + // + // This PME event (PCH's GPE #13) is received when any PCH internal device with PCI Power Management capabilities + // on bus 0 asserts the equivalent of the PME# signal. + // + Method(XL0D, 0) { + If(LAnd(\_SB.PCI0.EHC1.PMEE, \_SB.PCI0.EHC1.PMES)){ + Notify(\_SB.PCI0.EHC1, 0x02) + } + If(LAnd(\_SB.PCI0.EHC2.PMEE, \_SB.PCI0.EHC2.PMES)){ + Notify(\_SB.PCI0.EHC2, 0x02) + } + If(LAnd(\_SB.PCI0.XHC.PMEE, \_SB.PCI0.XHC.PMES)){ + Notify(\_SB.PCI0.XHC, 0x02) + } + ElseIf(LEqual(\_SB.PCI0.XHC.PMEE, 0)) { + Store(1, \_SB.PCI0.XHC.PMES) // Clear PMES Bit because an SCI is occurring when PMEE bit is not set + } + If(LAnd(\_SB.PCI0.HDEF.PMEE, \_SB.PCI0.HDEF.PMES)){ + Notify(\_SB.PCI0.HDEF, 0x02) + } + Notify(\_SB.PCI0.GLAN, 0x02) + } + + // PCI Express Hot-Plug caused the wake event. + + Method(XL01) + { + Add(L01C,1,L01C) // Increment L01 Entry Count. + + P8XH(0,0x01) // Output information to Port 80h. + P8XH(1,L01C) + + + // Check Root Port 1 for a Hot Plug Event if the Port is + // enabled. + +#if defined(ASL_RC_PORT_0) && (ASL_RC_PORT_0==1) + If(LAnd(LEqual(RP1D,0),\_SB.PCI0.RP01.HPSX)) + { + // Delay for 100ms to meet the timing requirements + // of the PCI Express Base Specification, Revision + // 1.0A, Section 6.6 ("...software must wait at + // least 100ms from the end of reset of one or more + // device before it is permitted to issue + // Configuration Requests to those devices"). +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x1)){ + Sleep(100) + } +#else + Sleep(100) +#endif + + If(\_SB.PCI0.RP01.PDCX) + { + // Clear all status bits first. + + Store(1,\_SB.PCI0.RP01.PDCX) + Store(1,\_SB.PCI0.RP01.HPSX) + + // + // PCH BIOS Spec Update Rev 1.03, Section 8.9 PCI Express* Hot-Plug BIOS Support + // In addition, BIOS should intercept Presence Detect Changed interrupt, enable L0s on + // hot plug and disable L0s on hot unplug. BIOS should also make sure the L0s is + // disabled on empty slots prior booting to OS. + // + If(LNot(\_SB.PCI0.RP01.PDSX)) { + // The PCI Express slot is empty, so disable L0s on hot unplug + // + Store(0,\_SB.PCI0.RP01.L0SE) + + } + + // Perform proper notification + // to the OS. +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x1)){ + Notify(\_SB.PCI0.RP01,0) + } +#else + Notify(\_SB.PCI0.RP01,0) +#endif + } + Else + { + // False event. Clear Hot-Plug Status + // then exit. + + Store(1,\_SB.PCI0.RP01.HPSX) + } + } +#endif // ASL_RC_PORT_0 + + // Check Root Port 2 for a Hot Plug Event if the Port is + // enabled. + +#if defined(ASL_RC_PORT_1) && (ASL_RC_PORT_1==1) + If(LAnd(LEqual(RP2D,0),\_SB.PCI0.RP02.HPSX)) + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x2)){ + Sleep(100) + } +#else + Sleep(100) +#endif + + If(\_SB.PCI0.RP02.PDCX) + { + Store(1,\_SB.PCI0.RP02.PDCX) + Store(1,\_SB.PCI0.RP02.HPSX) + + If(LNot(\_SB.PCI0.RP02.PDSX)) { + Store(0,\_SB.PCI0.RP02.L0SE) + } + +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x2)){ + Notify(\_SB.PCI0.RP02,0) + } +#else + Notify(\_SB.PCI0.RP02,0) +#endif + } + Else + { + Store(1,\_SB.PCI0.RP02.HPSX) + } + } +#endif // ASL_RC_PORT_1 + + // Check Root Port 3 for a Hot Plug Event if the Port is + // enabled. + +#if defined(ASL_RC_PORT_2) && (ASL_RC_PORT_2==1) + If(LAnd(LEqual(RP3D,0),\_SB.PCI0.RP03.HPSX)) + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x3)){ + Sleep(100) + } +#else + If(LAnd(LNotEqual(BID, BICO),LNotEqual(BID, BICC))) { + Sleep(100) + } +#endif + + If(\_SB.PCI0.RP03.PDCX) + { + Store(1,\_SB.PCI0.RP03.PDCX) + Store(1,\_SB.PCI0.RP03.HPSX) + + If(LNot(\_SB.PCI0.RP03.PDSX)) { + Store(0,\_SB.PCI0.RP03.L0SE) + } + +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x3)){ + Notify(\_SB.PCI0.RP03,0) + } +#else + If(LAnd(LNotEqual(BID, BICO),LNotEqual(BID, BICC))) { + Notify(\_SB.PCI0.RP03,0) + } +#endif + } + Else + { + Store(1,\_SB.PCI0.RP03.HPSX) + } + } +#endif // ASL_RC_PORT_2 + + // Check Root Port 4 for a Hot Plug Event if the Port is + // enabled. + +#if defined(ASL_RC_PORT_3) && (ASL_RC_PORT_3==1) + If(LAnd(LEqual(RP4D,0),\_SB.PCI0.RP04.HPSX)) + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x4)){ + Sleep(100) + } +#else + Sleep(100) +#endif + + If(\_SB.PCI0.RP04.PDCX) + { + Store(1,\_SB.PCI0.RP04.PDCX) + Store(1,\_SB.PCI0.RP04.HPSX) + + If(LNot(\_SB.PCI0.RP04.PDSX)) { + Store(0,\_SB.PCI0.RP04.L0SE) + } + +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x4)){ + Notify(\_SB.PCI0.RP04,0) + } +#else + Notify(\_SB.PCI0.RP04,0) +#endif + } + Else + { + Store(1,\_SB.PCI0.RP04.HPSX) + } + } +#endif // ASL_RC_PORT_3 + + // Check Root Port 5 for a Hot Plug Event if the Port is + // enabled. + +#if defined(ASL_RC_PORT_4) && (ASL_RC_PORT_4==1) + If(LAnd(LEqual(RP5D,0),\_SB.PCI0.RP05.HPSX)) + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x5)){ + Sleep(100) + } +#else + If(LAnd(LNotEqual(BID, BICO),LNotEqual(BID, BICC))) { + Sleep(100) + } +#endif + + If(\_SB.PCI0.RP05.PDCX) + { + Store(1,\_SB.PCI0.RP05.PDCX) + Store(1,\_SB.PCI0.RP05.HPSX) + + If(LNot(\_SB.PCI0.RP05.PDSX)) { + Store(0,\_SB.PCI0.RP05.L0SE) + } + +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x5)){ + Notify(\_SB.PCI0.RP05,0) + } +#else + If(LAnd(LNotEqual(BID, BICO),LNotEqual(BID, BICC))) { + Notify(\_SB.PCI0.RP05,0) + } +#endif + } + Else + { + Store(1,\_SB.PCI0.RP05.HPSX) + } + } +#endif // ASL_RC_PORT_4 + + // Check Root Port 6 for a Hot Plug Event if the Port is + // enabled. + +#if defined(ASL_RC_PORT_5) && (ASL_RC_PORT_5==1) + If(LAnd(LEqual(RP6D,0),\_SB.PCI0.RP06.HPSX)) + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x6)){ + Sleep(100) + } +#else + Sleep(100) +#endif + + If(\_SB.PCI0.RP06.PDCX) + { + Store(1,\_SB.PCI0.RP06.PDCX) + Store(1,\_SB.PCI0.RP06.HPSX) + + If(LNot(\_SB.PCI0.RP06.PDSX)) { + Store(0,\_SB.PCI0.RP06.L0SE) + } + +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x6)){ + Notify(\_SB.PCI0.RP06,0) + } +#else + Notify(\_SB.PCI0.RP06,0) +#endif + } + Else + { + Store(1,\_SB.PCI0.RP06.HPSX) + } + } +#endif // ASL_RC_PORT_5 + + // Check Root Port 7 for a Hot Plug Event if the Port is + // enabled. + +#if defined(ASL_RC_PORT_6) && (ASL_RC_PORT_6==1) + If(LAnd(LEqual(RP7D,0),\_SB.PCI0.RP07.HPSX)) + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x7)){ + Sleep(100) + } +#else + Sleep(100) +#endif + + If(\_SB.PCI0.RP07.PDCX) + { + Store(1,\_SB.PCI0.RP07.PDCX) + Store(1,\_SB.PCI0.RP07.HPSX) + + If(LNot(\_SB.PCI0.RP07.PDSX)) { + Store(0,\_SB.PCI0.RP07.L0SE) + } + + If(LEqual(PFLV,FDTP)) + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x7)){ + Notify(\_SB.PCI0.RP07,0) + } +#else + Notify(\_SB.PCI0.RP07,0) +#endif + } + Else + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If (LAnd(LNotEqual(\TBRP,0x7), \ECON)) +#else + If (\ECON) +#endif + { + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.DOCK)), 0)) + { // If not docked then it's hot plug + Notify(\_SB.PCI0.RP07,0) + } + } + } + } + Else + { + Store(1,\_SB.PCI0.RP07.HPSX) + } + } +#endif // ASL_RC_PORT_6 + + // Check Root Port 8 for a Hot Plug Event if the Port is + // enabled. + +#if defined(ASL_RC_PORT_7) && (ASL_RC_PORT_7==1) + If(LAnd(LEqual(RP8D,0),\_SB.PCI0.RP08.HPSX)) + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x8)){ + Sleep(100) + } +#else + Sleep(100) +#endif + + If(\_SB.PCI0.RP08.PDCX) + { + Store(1,\_SB.PCI0.RP08.PDCX) + Store(1,\_SB.PCI0.RP08.HPSX) + + If(LNot(\_SB.PCI0.RP08.PDSX)) { + Store(0,\_SB.PCI0.RP08.L0SE) + } + + If(LEqual(PFLV,FDTP)) + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If(LNotEqual(\TBRP,0x8)){ + Notify(\_SB.PCI0.RP08,0) + } +#else + Notify(\_SB.PCI0.RP08,0) +#endif + } + Else + { +#if defined(ASL_Thunderbolt_SUPPORT) && (ASL_Thunderbolt_SUPPORT == 1) + If (LAnd(LNotEqual(\TBRP,0x8), \ECON)) +#else + If (\ECON) +#endif + { + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.DOCK)), 0)) + { // If not docked then it's hot plug + Notify(\_SB.PCI0.RP08,0) + } + } + } + } + Else + { + Store(1,\_SB.PCI0.RP08.HPSX) + } + } +#endif // ASL_RC_PORT_7 + } + + // + // Software GPE caused the event. + // + Method(XL02) + { + // Clear GPE status bit. + Store(0,GPEC) + + // + // Handle DTS Thermal Events. + // + External(DTSE, IntObj) + If(CondRefOf(DTSE)){ + If(LGreaterEqual(DTSE, 0x01)){ + Notify(\_TZ.TZ00,0x80) + Notify(\_TZ.TZ01,0x80) + } + } + // + // CPPC Begin + // + // If GPE was asserted on doorbell ring, notify CPPC driver. If GPE was asserted by CPPC to signal + // command completion, clear internal flag. This method is required for CPPC driver to function. + // + External(\_SB.PCCD.PENB, IntObj) + If(CondRefOf(\_SB.PCCD.PENB)){ + If(LEqual(\_SB.PCCD.PENB, 1)) // If CPPC is enabled in BIOS setup, then process command. + { + Notify(\_SB.PCCD, 0x80) + } + } + // + // CPPC End + // + } + + // IGD OpRegion SCI event (see IGD OpRegion/Software SCI BIOS SPEC). + Method(XL06) + { + If(LAnd(\_SB.PCI0.GFX0.GSSE, LNot(GSMI))) // Graphics software SCI event? + { + \_SB.PCI0.GFX0.GSCI() // Handle the SWSCI + } + } + + // SMBus Alert caused the wake event + Method(XL07) + { + Store(0x20,\_SB.PCI0.SBUS.HSTS) + } + +#if 0 //AMI_OVERRIDE --- It is for CRB SIO using,OEM doesn't need to it. >> + // RI# caused the wake event (COMA). + + Method(XL08) + { + Notify(\_SB.PCI0.LPCB.SM17.UAR1,0x02) + } +#endif //AMI_OVERRIDE --- It is for CRB SIO using,OEM doesn't need to it. << + +#if define ASL_CRB_EC_SUPPORT && ASL_CRB_EC_SUPPORT = 1 //AMI_OVERRIDE + // + // GPI014 = EC WAKETIME SCI + // + Method(XL1E) + { + // Do nothing if Desktop platform + If (LEqual(\ECON,0)) + { + Return () + } + + // If the wake event is not a Virtual Lid or Battery, then + // it must be a Wake from either the Keyboard or Mouse. A + // Power Button Event will be sent for both events such + // that the video turns back on for these "attended wake" + // events. + + // Check for Virtual Lid Event. + + If(LNotEqual(LIDS,\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.LSTE)))) + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.LSTE)),LIDS) + + If(IGDS) + { + // Upon waking a lid event may fail if driver is not ready. + // If it does, set the high bit of the variable to indicate that + // another notification is required during system callbacks. + If(\_SB.PCI0.GFX0.GLID(LIDS)) + { + Or(0x80000000,\_SB.PCI0.GFX0.CLID, \_SB.PCI0.GFX0.CLID) + } + } + Notify(\_SB.LID0,0x80) + } + Else + { + // Check for Virtual Power Event. + + If(LEqual(BNUM,0)) + { + If(LNotEqual(PWRS,\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.VPWR)))) + { + // Update NVS Power State. + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.VPWR)),PWRS) + + // Perform needed ACPI Notifications. + PNOT() + } + } + + // Make it an attended wake event, no matter what. + Notify(\_SB.PWRB,0x02) + } + Return () + } +#endif //AMI_OVERRIDE + +#if 0 //AMI_OVERRIDE --- Below ASL code is for Thunderbolt, AMI thunderbolt module has taken care it already.>> + // + //OS up handshake procedure to host router upstream port each time + //exiting from Sx State .Avoids intermediate + //PCIe Scan by OS during resorce allocation + // + Method(OSUP, 1) + { + Add(Arg0, 0x548, Local0) + OperationRegion(PXVD,SystemMemory,Local0,0x08) + Field(PXVD,DWordAcc, NoLock, Preserve) + { + TB2P, 32, + P2TB, 32 + } + + Store(100, Local1) + Store(0x0D, P2TB) // Write OS_Up to PCIe2TBT + While(LGreater(Local1, 0)) + { + Store(Subtract(Local1, 1), Local1) + Store(TB2P, Local2) + If(LEqual(Local2, 0xFFFFFFFF))// Device gone + { + Return(2) + } + If(And(Local2, 1)) // Done + { + break + } + Sleep(50) + } + Store(0x00, P2TB) // Write 0 to PCIe2TBT + Return(1) + } + + Method(MMTB) + { + ADBG("MMTB") + Store(PEBS, Local0) // MMIO Base address + + Add(Local0, 0xE0000, Local0) // RP01 + Subtract(ToInteger(TBSE), 1, Local1) + Multiply(Local1, 0x1000, Local1) + Add(Local0, Local1, Local0) // RP0x + + OperationRegion (MMMM, SystemMemory, Local0, 0x1A) + Field (MMMM, AnyAcc, NoLock, Preserve) + { + Offset(0x19), + SBUS, 8 + } + Store(SBUS, Local2) + Store(PEBS, Local0) + Multiply(Local2, 0x100000, Local2) + Add(Local2, Local0, Local0) // TBT HR US port + Return(Local0) + } + + // + //OS up handshake Method ,invokes OSUP based on + //Vendor/Device ID Check + // + Method(OSUW) + { + ADBG("OSUW") + Store(MMTB(), Local0) + OperationRegion(PXVD,SystemMemory,Local0,0x4) + Field(PXVD,DWordAcc, NoLock, Preserve) + { + VEDI, 32 // Vendor/Device ID + } + Store(VEDI, Local1) + + If(LNotEqual(Local1, 0xFFFFFFFF)) + { + Return (OSUP(Local0)) + } + Else + { + Return (0) + } + } + + Method(TBFF)// Check for FFFF in TBT + { + ADBG("TBFF") + Store(MMTB(), Local0) + OperationRegion(PXVD,SystemMemory,Local0,0x4) + Field(PXVD,DWordAcc, NoLock, Preserve) + { + VEDI, 32 // Vendor/Device ID + } + Store(VEDI, Local1) + + If(LEqual(Local1, 0xFFFFFFFF)) + { + Return (OSUP(Local0)) + } + Else + { + Return (0) + } + } + + // Subordinate bus of TBT RP + Method(TSUB) + { + Store(PEBS, Local0) // MMIO Base address + + Add(Local0, 0xE0000, Local0) // RP01 + Subtract(ToInteger(TBSE), 1, Local1) + Multiply(Local1, 0x1000, Local1) + Add(Local0, Local1, Local0) // RP0x + + OperationRegion (MMMM, SystemMemory, Local0, 0x1A) + Field (MMMM, AnyAcc, NoLock, Preserve) + { + Offset(0x19), + SBUS, 8 + } + Return(SBUS) + } + + // Wait for subordinate bus in TBT RP + Method(WSUB) + { + Store(0, Local0) + Store(0, Local1) + While(1) + { + Store(TSUB(), Local1) + If(Local1) + { + Break + } + Else + { + Add(Local0, 1, Local0) + If(LGreater(Local0, 1000)) + { + Sleep(1000) + ADBG("WSUB Deadlock") + } + Else + { + Sleep(16) + } + } + } + } + + // Wait for _WAK finished + Method(WWAK) + { + Store(0, Local0) + Store(0, Local1) + While(1) + { + Acquire(WFDM, 0xFFFF) + Store(WKFN, Local0) + Release(WFDM) + + If(Local0) + { + Break + } + Else + { + Add(Local1, 1, Local1) + If(LGreater(Local1, 1000)) + { + Sleep(1000) + ADBG("WWAK Deadlock") + } + Else + { + Sleep(16) + } + } + } + Return(Local1) + } + // + // Method to Handle enumerate PCIe structure through + // SMI for Thunderbolt devices + // + Method(_E2A) + { + + WWAK() + WSUB() + OperationRegion(SPRT,SystemIO, 0xB2,2) + Field (SPRT, ByteAcc, Lock, Preserve) + { + SSMP, 8 + } + + ADBG("_E2A") + Acquire(OSUM, 0xFFFF) + Store(TBFF(), Local0) + If(LEqual(Local0, 1))// Only HR + { + Sleep(16) + Release(OSUM) + Return () + } + If(LEqual(Local0, 2)) // Disconnect + { + If(NOHP) + { + ADBG("_E2A Ntfy") + If(LEqual(TBSE, 5)) + { + Notify(\_SB.PCI0.RP05,0) + } + If(LEqual(TBSE, 3)) + { + Notify(\_SB.PCI0.RP03,0) + } + } + Sleep(16) + Release(OSUM) + Return () + } + + // HR and EP + If(LEqual(SOHP, 1)) + { + // Trigger SMI to enumerate PCIe Structure + ADBG("_E2A SMI") + Store(21, TBSF) + Store(0xF7, SSMP) + } + If(LEqual(NOHP, 1)) + { + //Notify Rootports + ADBG("_E2A Ntfy") + If(LEqual(TBSE, 5)) + { + Notify(\_SB.PCI0.RP05,0) + } + If(LEqual(TBSE, 3)) + { + Notify(\_SB.PCI0.RP03,0) + } + } + Sleep(16) + Release(OSUM) + } +#endif //AMI_OVERRIDE --- it is for Thunderbolt, AMI thunderbolt module has taken care it already. << + + +// For Reed Harbor only: Rotation Lock button is connected to GPI00. +#if define ASL_RHT_BOARD && ASL_RHT_BOARD = 1 //AMI_OVERRIDE + Method(_L00) + { + If(LEqual(BID,BRH)) // BoardIdReedHarborTdv + { + ADBG("Rotation Lock") + Sleep(1000) + \_SB.PCI0.GFX0.IUEH(4) // Rotation lock + } + } +#endif //AMI_OVERRIDE + +} diff --git a/ReferenceCode/AcpiTables/Dsdt/H8S2113_SIO.ASL b/ReferenceCode/AcpiTables/Dsdt/H8S2113_SIO.ASL new file mode 100644 index 0000000..e3bbd80 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/H8S2113_SIO.ASL @@ -0,0 +1,134 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ +Device(H8S2) +{ + Name(_HID,EISAID("PNP0A05")) + + Name(_UID, 5) + + Method(_STA,0,Serialized) + { + If(LEqual(PFLV,FMBL)) + { + Return(0x000F) + } + + Return(0x0000) + } + + Device(UAR9) // Serial Port UART 9 + { + Name(_HID, EISAID("PNP0501")) + + Name(_UID, 1) + + // + // Status Method for UART 9. + // + Method(_STA, 0, Serialized) + { + If(LAnd(LEqual(PFLV,FMBL), LNotEqual(BID, BHB))) + { + Return(0x000F) + } + + Return(0x0000) + } + + // + // Disable Method for UART 9. + // + // + // Current Resource Setting Method for UART 9. + // + Method(_CRS, 0, Serialized) + { + // + // Create the Buffer that stores the resources to be returned. + // + Name(BUF0, ResourceTemplate() + { + IO(Decode16,0x03F8,0x03F8,0x01,0x08) + IRQNoFlags(){4} + }) + + // + // TO-DO: Need to implement the code updating BUF0 (I/O 0x3F8~0x3FF and IRQ 4 are the default setting) + // according to the real resources assigned when the EC commands are available. + // + + Return(BUF0) + } + + + // + // Set Resource Setting Method for UART 9. + // + Method(_SRS,1,Serialized) + { + CreateByteField(Arg0, 0x02, IOLO) + CreateByteField(Arg0, 0x03, IOHI) + CreateWordField(Arg0, 0x09, IRQW) + + If(LEqual(IOHI, 0x03)) + { + If(LEqual(IOLO, 0xF8)) + { + If(LEqual(IRQW, 4)) + { + Store(1, HSCS) + } + } + } + + // + // TO-DO: Need to implement the code setting the resources based on the arguments when the EC commands are available. + // + } + + // + // D0 Method for COM Port. + // + Method(_PS0,0,Serialized) + { + // + // TO-DO: Need to implement the code put the device on D0 state when the EC commands are available. + // + } + + // + // D3 Method for COM Port. + // + Method(_PS3,0,Serialized) + { + // + // TO-DO: Need to implement the code putting the device on D3 state when the EC commands are available. + // + } + } +} + +
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/Dsdt/LPC_DEV.ASL b/ReferenceCode/AcpiTables/Dsdt/LPC_DEV.ASL new file mode 100644 index 0000000..6908a3e --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/LPC_DEV.ASL @@ -0,0 +1,302 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + +Device(DMAC) // DMA Controller +{ + Name(_HID,EISAID("PNP0200")) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x00,0x00,0x01,0x20) + IO(Decode16,0x81,0x81,0x01,0x11) + IO(Decode16,0x93,0x93,0x01,0x0D) + IO(Decode16,0xC0,0xC0,0x01,0x20) + DMA(Compatibility,NotBusMaster,Transfer8_16) {4} + }) +} + +Device(FWHD) // Firmware Hub Device +{ + Name(_HID,EISAID("INT0800")) + + Name(_CRS,ResourceTemplate() + { + Memory32Fixed(ReadOnly,0xFF000000,0x1000000) + }) +} + + +Device(HPET) // High Performance Event Timer +{ + Name(_HID,EISAID("PNP0103")) + Name(_UID, 0) + + Name(BUF0,ResourceTemplate() + { + Memory32Fixed(ReadWrite,0xFED00000,0x400,FED0) + }) + + Method(_STA,0) + { + // Show this Device only if the OS is WINXP or beyond. + + If(LGreaterEqual(OSYS,2001)) + { + If(HPAE) + { + Return(0x000F) // Enabled, do Display. + } + } + Else + { + // OS = WIN98, WINME, or WIN2000. + + If(HPAE) + { + Return(0x000B) // Enabled, don't Display. + } + } + + Return(0x0000) // Return Nothing. + } + + Method(_CRS,0,Serialized) + { + If(HPAE) + { + // Check if HPETimer Base should be modified. + + CreateDwordField(BUF0,^FED0._BAS,HPT0) + + If(LEqual(HPAS,1)) + { + Store(0xFED01000,HPT0) + } + + If(LEqual(HPAS,2)) + { + Store(0xFED02000,HPT0) + } + + If(LEqual(HPAS,3)) + { + Store(0xFED03000,HPT0) + } + } + + Return(BUF0) + } +} + +Device(IPIC) // 8259 PIC +{ + Name(_HID,EISAID("PNP0000")) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x20,0x20,0x01,0x02) + IO(Decode16,0x24,0x24,0x01,0x02) + IO(Decode16,0x28,0x28,0x01,0x02) + IO(Decode16,0x2C,0x2C,0x01,0x02) + IO(Decode16,0x30,0x30,0x01,0x02) + IO(Decode16,0x34,0x34,0x01,0x02) + IO(Decode16,0x38,0x38,0x01,0x02) + IO(Decode16,0x3C,0x3C,0x01,0x02) + IO(Decode16,0xA0,0xA0,0x01,0x02) + IO(Decode16,0xA4,0xA4,0x01,0x02) + IO(Decode16,0xA8,0xA8,0x01,0x02) + IO(Decode16,0xAC,0xAC,0x01,0x02) + IO(Decode16,0xB0,0xB0,0x01,0x02) + IO(Decode16,0xB4,0xB4,0x01,0x02) + IO(Decode16,0xB8,0xB8,0x01,0x02) + IO(Decode16,0xBC,0xBC,0x01,0x02) + IO(Decode16,0x4D0,0x4D0,0x01,0x02) + IRQNoFlags() {2} + }) +} + +#ifdef TRAD_FLAG +Device(MATH) // Math Co-Processor +{ + Name(_HID,EISAID("PNP0C04")) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0xF0,0xF0,0x01,0x01) + IRQNoFlags() {13} + }) + + // + // Report device present for LPT-H. + // + Method (_STA, 0x0, NotSerialized) + { + // LPT-H Chipset DID start with 0x8xxx while LPT-LP start with 0x9xxx + If(LEqual(And(CDID,0xF000), 0x8000)) { + Return(0x1F) + } else { + Return(0x0) + } + } +} +#endif // TRAD_FLAG + +Device(LDRC) // LPC Device Resource Consumption +{ + Name(_HID,EISAID("PNP0C02")) + + Name(_UID,2) + +#if 0 + Name(_CRS,ResourceTemplate() // This is for Cougar Point + { + IO(Decode16,0x2E,0x2E,0x1,0x02) // SIO Access. + IO(Decode16,0x4E,0x4E,0x1,0x02) // LPC Slot Access. + IO(Decode16,0x61,0x61,0x1,0x1) // NMI Status. + IO(Decode16,0x63,0x63,0x1,0x1) // Processor I/F. + IO(Decode16,0x65,0x65,0x1,0x1) // Processor I/F. + IO(Decode16,0x67,0x67,0x1,0x1) // Processor I/F. + IO(Decode16,0x70,0x70,0x1,0x1) // NMI Enable. + IO(Decode16,0x80,0x80,0x1,0x1) // Port 80h. + IO(Decode16,0x92,0x92,0x1,0x1) // Processor I/F. + IO(Decode16,0xB2,0xB2,0x01,0x02) // Software SMI. + IO(Decode16,0x680,0x680,0x1,0x20) // 32 Byte I/O. + IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // ACPI IO Trap. + IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // DTS IO Trap. + IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // HotKey IO Trap. + + IO(Decode16, 0x800,0x800,0x1,0xFF) // PCH GPIO Base. + IO(Decode16, 0x900,0x900,0x1,0xFF) // PCH GPIO Base. + IO(Decode16, 0xA00,0xA00,0x1,0xFF) // PCH GPIO Base. + IO(Decode16, 0xB00,0xB00,0x1,0xFF) // PCH GPIO Base. + IO(Decode16, 0x1800,0x1800,0x1,0xFF) // PCH ACPI Base + + IO(Decode16,0x164e,0x164e,0x1,0x02) // 16 Byte I/O. + }) +#else + Name(BUF0,ResourceTemplate() // This is for Cougar Point + { + IO(Decode16,0x2E,0x2E,0x1,0x02) // SIO Access. + IO(Decode16,0x4E,0x4E,0x1,0x02) // LPC Slot Access. + IO(Decode16,0x61,0x61,0x1,0x1) // NMI Status. + IO(Decode16,0x63,0x63,0x1,0x1) // Processor I/F. + IO(Decode16,0x65,0x65,0x1,0x1) // Processor I/F. + IO(Decode16,0x67,0x67,0x1,0x1) // Processor I/F. + IO(Decode16,0x70,0x70,0x1,0x1) // NMI Enable. + IO(Decode16,0x80,0x80,0x1,0x1) // Port 80h. + IO(Decode16,0x92,0x92,0x1,0x1) // Processor I/F. + IO(Decode16,0xB2,0xB2,0x01,0x02) // Software SMI. + IO(Decode16,0x680,0x680,0x1,0x20) // 32 Byte I/O. + IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // ACPI IO Trap. + IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // DTS IO Trap. + IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // HotKey IO Trap. + + IO(Decode16, 0x800,0x800,0x1,0xFF, GIO0) // PCH GPIO Base. + IO(Decode16, 0x900,0x900,0x1,0xFF, GIO1) // PCH GPIO Base. + IO(Decode16, 0xA00,0xA00,0x1,0xFF, GIO2) // PCH GPIO Base. + IO(Decode16, 0xB00,0xB00,0x1,0xFF, GIO3) // PCH GPIO Base. + IO(Decode16, 0x1800,0x1800,0x1,0xFF) // PCH ACPI Base + + IO(Decode16,0x164e,0x164e,0x1,0x02) // 16 Byte I/O. + }) + + Method(_CRS,0) + { + CreateWordField(BUF0, ^GIO0._MIN, IO0M) + CreateWordField(BUF0, ^GIO0._MAX, IO0X) + Store(GPBS, IO0M) + Store(GPBS, IO0X) + + CreateWordField(BUF0, ^GIO1._MIN, IO1M) + CreateWordField(BUF0, ^GIO1._MAX, IO1X) + Store(Add(GPBS, 0x100), IO1M) + Store(Add(GPBS, 0x100), IO1X) + + CreateWordField(BUF0, ^GIO2._MIN, IO2M) + CreateWordField(BUF0, ^GIO2._MAX, IO2X) + Store(Add(GPBS, 0x200), IO2M) + Store(Add(GPBS, 0x200), IO2X) + + CreateWordField(BUF0, ^GIO3._MIN, IO3M) + CreateWordField(BUF0, ^GIO3._MAX, IO3X) + Store(Add(GPBS, 0x300), IO3M) + Store(Add(GPBS, 0x300), IO3X) + + Return(BUF0) + } +#endif +} + +Device(RTC) // RTC +{ + Name(_HID,EISAID("PNP0B00")) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x70,0x70,0x01,0x08) + IRQNoFlags() {8} + }) +} + +Device(TIMR) // 8254 Timer +{ + Name(_HID,EISAID("PNP0100")) + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x40,0x40,0x01,0x04) + IO(Decode16,0x50,0x50,0x10,0x04) + IRQNoFlags() {0} + }) +} + +Device(CWDT) +{ + Name(_HID,EISAID("INT3F0D")) + Name(_CID,EISAID("PNP0C02")) + Name(BUF0,ResourceTemplate() + { + IO(Decode16, 0x1854, 0x1854, 0x4, 0x4) // PMBS 0x1800 + Offset 0x54 + } + ) + + Method(_STA,0,Serialized) + { + If(LEqual(WDTE,1)) + { + Return(0x0F) + } + Else + { + Return(0x00) + } + } + + Method(_CRS,0,Serialized) + { + Return(BUF0) + } +} diff --git a/ReferenceCode/AcpiTables/Dsdt/LpcB.asl b/ReferenceCode/AcpiTables/Dsdt/LpcB.asl new file mode 100644 index 0000000..647a34d --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/LpcB.asl @@ -0,0 +1,178 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +// LPC Bridge - Device 31, Function 0 +// Define the needed LPC registers used by ASL. + +scope(\_SB){ + OperationRegion(\_SB.PCI0.LPCB.LPC1, PCI_Config, 0x00, 0x100) + Field(\_SB.PCI0.LPCB.LPC1, AnyAcc, NoLock, Preserve) + { + Offset(0x02), + CDID,16, + Offset(0x08), + CRID, 8, + Offset(0x60), + PARC, 8, + PBRC, 8, + PCRC, 8, + PDRC, 8, + Offset(0x68), + PERC, 8, + PFRC, 8, + PGRC, 8, + PHRC, 8, + Offset(0xAC), + , 8, + , 8, + XUSB, 1 + } + + Include ("98_LINK.ASL") +} + OperationRegion(LPC0, PCI_Config, 0x40, 0xC0) + Field(LPC0, AnyAcc, NoLock, Preserve) + { + Offset(0x40), // 0x80h + IOD0, 8, + IOD1, 8, + Offset(0x78), // 0xB8h + , 6, + GR03, 2, + , 8, + GR08, 2, + GR09, 2, + GR0A, 2, + GR0B, 2, + , 8, + Offset(0x7C), // 0xBCh + , 2, + GR19, 2, + , 28, + Offset(0x0B0), // 0xF0h + RAEN, 1, + , 13, + RCBA, 18 + } + +#if 0 //AMI_OVERRIDE --- Include EC.ASL in EC module. >> + Include ("EC.ASL") +#endif //AMI_OVERRIDE --- Include EC.ASL in EC module. << + Include ("LPC_DEV.ASL") +#if 0 //AMI_OVERRIDE --- Using AMI SIO module. >> + Include ("NAT_SIO.ASL") + Include ("SMSC1007_SIO.ASL") + Include ("WPCN381U_SIO.ASL") + Include ("SMSC1000_SIO.ASL") + Include ("H8S2113_SIO.ASL") +#endif //AMI_OVERRIDE --- Using AMI SIO module. << + + // Define the KBC_COMMAND_REG-64, KBC_DATA_REG-60 Registers as an ACPI Operating + // Region. These registers will be used to skip kbd mouse + // resource settings if not present. +#if 0 //AMI_OVERRIDE --- Using AMI ACPI ASL code and SIO module. >> + OperationRegion(PKBS, SystemIO, 0x60, 0x05) + Field(PKBS, ByteAcc, Lock, Preserve) + { + PKBD, 8, + , 8, + , 8, + , 8, + PKBC, 8 + } + Device(PS2K) // PS2 Keyboard + { + Name(_HID,"MSFT0001") + Name(_CID,EISAID("PNP0303")) + + Method(_STA) + { + If(LEqual(BID, BHB)) + { + Return(0x000F) + } + // Only report resources to the OS if the Keyboard is present + If(LOr(And(LEqual(PKBD,0xFF), LEqual(PKBC, 0xFF)), LEqual(BID, BFCC))) + { + Return(0x0000) + } + Return(0x000F) + } + + Name(_CRS,ResourceTemplate() + { + IO(Decode16,0x60,0x60,0x01,0x01) + IO(Decode16,0x64,0x64,0x01,0x01) + IRQ(Edge,ActiveHigh,Exclusive){0x01} + }) + + Name(_PRS, ResourceTemplate(){ + StartDependentFn(0, 0) { + FixedIO(0x60,0x01) + FixedIO(0x64,0x01) + IRQNoFlags(){1} + } + EndDependentFn() + }) + + } + + Device(PS2M) // PS/2 Mouse + { + Name(_HID,"MSFT0003") + Name(_CID,EISAID("PNP0F03")) + + Method(_STA) + { + If(LOr(LEqual(BID, BHB), LEqual(BID, BFCC))) + { + Return(0x0000) + } + + If (P2ME) + { + Return(0x000F) + } + + Return(0x0000) + } + + Name(_CRS,ResourceTemplate() + { + IRQ(Edge,ActiveHigh,Exclusive){0x0C} + }) + + Name(_PRS, ResourceTemplate(){ + StartDependentFn(0, 0) { + IRQNoFlags(){12} + } + EndDependentFn() + }) + } +#endif //AMI_OVERRIDE --- Using AMI ACPI ASL code and SIO module. << + + diff --git a/ReferenceCode/AcpiTables/Dsdt/NAT_COM.ASL b/ReferenceCode/AcpiTables/Dsdt/NAT_COM.ASL new file mode 100644 index 0000000..6a1b9c5 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/NAT_COM.ASL @@ -0,0 +1,481 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + + +Device(UAR3) // Serial Port A +{ + Name(_HID, EISAID("PNP0501")) + + Name(_UID,2) + + // Status Method for COM A. + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if the SIO Device is + // not set to Disabled in BIOS Setup. + + If(LAnd(NATP,CMAP)) + { + // Set the SIO to COM A. + + Store(3,R07H) + + // Display COMA and return status. + + If(R30H) + { + Return(0x000F) + } + + Return(0x000D) + } + + Return(0x0000) + } + + // Disable Method for COM A. + + Method(_DIS,0,Serialized) + { + Store(3,R07H) + Store(0,R30H) + } + + // Current Resource Setting Method for COM A. + + Method(_CRS,0,Serialized) + { + // Create the Buffer that stores the Resources to + // be returned. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x03F8,0x03F8,0x01,0x08) + IRQNoFlags(){4} + }) + + // Set SIO to COM A. + + Store(3,R07H) + + // Skip this sequence if the COMA Port is Disabled + // in BIOS Setup. + + If(LAnd(NATP,CMAP)) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Write IO and Length values into the Buffer. + + Store(R60H,IOH0) + Store(R61H,IOL0) + Store(R60H,IOH1) + Store(R61H,IOL1) + Store(8,LEN0) + + // Write the IRQ value into the Buffer. + + And(R70H,0x0F,Local0) + If(Local0) + { + ShiftLeft(One,Local0,IRQW) + } + Else + { + Store(Zero,IRQW) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for COM A. + + // Build a Buffer with all valid COM Port Resources. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x2E8,0x2E8,0x01,0x08) + IRQNoFlags(){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){3,4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){3,4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3E8,0x3E8,0x01,0x08) + IRQNoFlags(){3,4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2E8,0x2E8,0x01,0x08) + IRQNoFlags(){3,4,5,6,7,10,11,12} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for COM A. + + Method(_SRS,1,Serialized) + { + // Point to the specific information in the passed + // in Buffer. + + CreateByteField(Arg0,0x02,IOLO) + CreateByteField(Arg0,0x03,IOHI) + CreateWordField(Arg0,0x09,IRQW) + + // Set the SIO to COM A. + + Store(3,R07H) + + // Disable the device. + + Store(0,R30H) + + // Set the Base IO Address. + + Store(IOLO,R61H) + Store(IOHI,R60H) + + // Set the IRQ. + + FindSetRightBit(IRQW,Local0) + If(LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,R70H) + + // Set the Decode Range so COM A works on ICH7 and + // future platforms. + + AND(IOD0,0xF8,IOD0) // Clear all bits. + + If(LEqual(IOHI,0x03)) // Address = 0x3xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x07,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x01,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x05,IOD0) + } + } + + // Enable the device. + + Store(1,R30H) + } + + // D0 Method for COM Port. + + Method(_PS0,0,Serialized) + { + Store(3,R07H) + Store(1,R30H) + } + + // D3 Method for COM Port. + + Method(_PS3,0,Serialized) + { + Store(3,R07H) + Store(0,R30H) + } +} + +Device(UAR4) // Serial Port B +{ + Name(_HID, EISAID("PNP0501")) + + Name(_UID,3) + + // Status Method for COM B. + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if the SIO Device is + // not set to Disabled in BIOS Setup. + + If(LAnd(NATP,CMBP)) + { + // Set the SIO to COM B. + + Store(2,R07H) + + // Display COM B and return status. + + If(R30H) + { + Return(0x000F) + } + + Return(0x000D) + } + + Return(0x0000) + } + + // Disable Method for COM B. + + Method(_DIS,0,Serialized) + { + Store(2,R07H) + Store(0,R30H) + } + + // Current Resource Setting Method for COM B. + + Method(_CRS,0,Serialized) + { + // Create the Buffer that stores the Resources to + // be returned. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x02F8,0x02F8,0x01,0x08) + IRQNoFlags(){3} + }) + + // Set SIO to COM B. + + Store(2,R07H) + + // Skip this sequence if the COM B Port is Disabled + // in BIOS Setup. + + If(LAnd(NATP,CMBP)) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Write IO and Length values into the Buffer. + + Store(R60H,IOH0) + Store(R61H,IOL0) + Store(R60H,IOH1) + Store(R61H,IOL1) + Store(8,LEN0) + + // Write the IRQ value into the Buffer. + + And(R70H,0x0F,Local0) + If(Local0) + { + ShiftLeft(One,Local0,IRQW) + } + Else + { + Store(Zero,IRQW) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for COM B. + + // Build a Buffer with all valid COM B Port Resources. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x2E8,0x2E8,0x01,0x08) + IRQNoFlags(){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3E8,0x3E8,0x01,0x08) + IRQNoFlags(){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2E8,0x2E8,0x01,0x08) + IRQNoFlags(){4} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){4} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3E8,0x3E8,0x01,0x08) + IRQNoFlags(){4} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){4} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for COM B. + + Method(_SRS,1,Serialized) + { + // Point to the specific information in the passed + // in Buffer. + + CreateByteField(Arg0,0x02,IOLO) + CreateByteField(Arg0,0x03,IOHI) + CreateWordField(Arg0,0x09,IRQW) + + // Set the SIO to COM B. + + Store(2,R07H) + + // Disable the device. + + Store(0,R30H) + + // Set the Base IO Address. + + Store(IOLO,R61H) + Store(IOHI,R60H) + + // Set the IRQ. + + FindSetRightBit(IRQW,Local0) + If(LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,R70H) + + // Set the Decode Range so COM B works on ICH7 and + // future platforms. + + AND(IOD0,0x8F,IOD0) // Clear all bits. + + If(LEqual(IOHI,0x03)) // Address = 0x3xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x70,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x10,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x50,IOD0) + } + } + + // Enable the device. + + Store(1,R30H) + } + + // D0 Method for COM B Port. + + Method(_PS0,0,Serialized) + { + Store(2,R07H) + Store(1,R30H) + } + + // D3 Method for COM B Port. + + Method(_PS3,0,Serialized) + { + Store(2,R07H) + Store(0,R30H) + } +} diff --git a/ReferenceCode/AcpiTables/Dsdt/NAT_LPT.ASL b/ReferenceCode/AcpiTables/Dsdt/NAT_LPT.ASL new file mode 100644 index 0000000..72b2208 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/NAT_LPT.ASL @@ -0,0 +1,942 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + + +// This ASL file will support the LPT in Output, BiDirectional, EPP, +// & ECP mode. Only 1 of these devices will be shown by the OS at any +// given time, and that one will depend on the BIOS configuration. + +Device(LPT1) // Printer, Output Mode +{ + Name(_HID,EISAID("PNP0400")) + Name(_UID,1) + + // Status Method for LPT-Output Mode. + + Method(_STA,0,Serialized) + { + // Output mode = 000xxxxxb - check that no bits are set. + Store(1,R07H) + If(LEqual(And(RF0H,0xE0),0x00)) + { + // LPT is in Output Mode. Only report resources + // to the OS if the SIO Device is not set to + // Disabled in BIOS Setup. + + If(LAnd(NATP,LPTP)) + { + // Set SIO to LPT. + + + // Display POUT and return Status. + + If(R30H) + { + Return(0x000F) + } + + Return(0x000D) + } + } + + Return(0x0000) + } + + // Disable Method for LPT-Output Mode. + + Method(_DIS,0,Serialized) + { + // Set SIO to LPT. + + Store(1,R07H) + + If(LEqual(And(RF0H,0xE0),0x00)) + { + Store(0,R30H) + } + } + + // Current Resource Setting Method for LPT-Output Mode. + + Method(_CRS,0,Serialized) + { + // Create a buffer to return to OS. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x0378,0x0378,0x01,0x04) + IRQNoFlags(){7} + }) + + // Skip this sequence if the LPT Device is not set + // to Output Mode. + + If(LEqual(And(RF0H,0xE0),0x00)) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Set SIO to LPT. + + Store(1,R07H) + + // Write IO and Length values into the Buffer. + + Store(R61H,IOL0) + Store(R60H,IOH0) + Store(IOL0,IOL1) + Store(IOH0,IOH1) + Store(4,LEN0) + + // Write the IRQ value into the Buffer. + + If(And(R70H,0x0F)) + { + ShiftLeft(One,And(R70H,0x0F),IRQW) + } + Else + { + Store(Zero,IRQW) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for LPT-Output Mode. + + // Build a Buffer with all valid LPT Port Resources. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3BC,0x3BC,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3BC,0x3BC,0x01,0x04) + IRQNoFlags(){5} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for LPT-Output Mode. + + Method(_SRS,1,Serialized) + { + // Point to the specific information in the passed + // in Buffer. + + CreateByteField(Arg0,0x02,IOL0) + CreateByteField(Arg0,0x03,IOH0) + CreateWordField(Arg0,0x09,IRQW) + + // Set SIO to LPT. + + Store(1,R07H) + + // Disable the LPT. + + Store(0,R30H) + + // Set to Output Mode. + + And(RF0H,0x0F,RF0H) + + // Disable the DMA channels. + + Store(4,R74H) + + // Set the Base IO Address. + + Store(IOL0,R61H) + Store(IOH0,R60H) + + // Set the IRQ. + + FindSetRightBit(IRQW,Local0) + If (LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,R70H) + + // Set the Decode Range so POUT works when docked. + + And(IOD1,0xFC,IOD1) // Decode all bits. + + If(LEqual(IOH0,0x03)) // Address = 0x3xx + { + If(LEqual(IOL0,0x78)) // Address = 0x378 + { + Or(IOD1,0x00,IOD1) + } + Else + { + Or(IOD1,0x02,IOD1) // Address = 0x3BC + } + } + Else // Address = 0x278 + { + Or(IOD1,0x01,IOD1) + } + + // Enable the LPT. + + Store(1,R30H) + } + + // D0 Method for LPT-Output Mode. + + Method(_PS0,0,Serialized) + { + Store(1,R07H) + Store(1,R30H) + } + + // D3 Method for LPT-Output Mode. + + Method(_PS3,0,Serialized) + { + Store(1,R07H) + Store(0,R30H) + } +} + +Device(PBI1) // Printer, BiDirectional Mode +{ + Name(_HID,EISAID("PNP0400")) + Name(_UID,2) + + // Status Method for LPT-BiDirectional Mode. + + Method(_STA,0,Serialized) + { + // BiDirectional mode = 001xxxxxb, so check that only + // bit 5 is set. + + Store(1,R07H) + If(LEqual(And(RF0H,0xE0),0x20)) + { + // LPT is in BiDirectional Mode. Only report + // resources to the OS if the SIO Device is not + // set to Disabled in BIOS Setup. + + If(LAnd(NATP,LPTP)) + { + // Display PBID and return Status. + + If(R30H) + { + Return(0x000F) + } + + Return(0x000D) + } + } + + Return(0x0000) + } + + // Disable Method for LPT-BiDirectional Mode. + + Method(_DIS,0,Serialized) + { + // Set SIO to LPT. + + Store(1,R07H) + + If(LEqual(And(RF0H,0xE0),0x20)) + { + Store(0,R30H) + } + } + + // Current Resource Setting Method for LPT-BiDirectional Mode. + + Method(_CRS,0,Serialized) + { + // Create a buffer to return to OS. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x0378,0x0378,0x01,0x04) + IRQNoFlags(){7} + }) + + // Skip this sequence if the LPT Device is not set + // to BiDirectional Mode. + + If(LEqual(And(RF0H,0xE0),0x20)) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Set SIO to LPT. + + Store(1,R07H) + + // Write IO and Length values into the Buffer. + + Store(R61H,IOL0) + Store(R60H,IOH0) + Store(IOL0,IOL1) + Store(IOH0,IOH1) + Store(4,LEN0) + + // Write the IRQ value into the Buffer. + + If(And(R70H,0x0F)) + { + ShiftLeft(One,And(R70H,0x0F),IRQW) + } + Else + { + Store(Zero, IRQW) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for LPT-BiDirectional Mode. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3BC,0x3BC,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3BC,0x3BC,0x01,0x04) + IRQNoFlags(){5} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for LPT-BiDirectional Mode. + + Method(_SRS,1,Serialized) + { + // Arg0 passed into _SRS is the buffer identical to BUF0. + + CreateByteField(Arg0,0x02,IOL0) + CreateByteField(Arg0,0x03,IOH0) + CreateWordField(Arg0,0x09,IRQW) + + Store(1,R07H) + + // Disable the LPT. + + Store(0,R30H) + + // Set to Bi-Directional Mode. + + Or(And(RF0H,0x0F),0x20,RF0H) + + // Disable the DMA channels. + + Store(4,R74H) + + // Set the Base IO Address. + + Store(IOL0,R61H) + Store(IOH0,R60H) + + // Set the IRQ. + + FindSetRightBit(IRQW,Local0) + If (LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,R70H) + + // Set the Decode Range so PBID works when docked. + + And(IOD1,0xFC,IOD1) // Decode all bits. + + If(LEqual(IOH0,0x03)) // Address = 0x3xx + { + If(LEqual(IOL0,0x78)) // Address = 0x378 + { + Or(IOD1,0x00,IOD1) + } + Else + { + Or(IOD1,0x02,IOD1) // Address = 0x3BC + } + } + Else // Address = 0x278 + { + Or(IOD1,0x01,IOD1) + } + + // Enable the LPT. + + Store(1,R30H) + } + + // D0 Method for LPT-BiDirectional Mode. + + Method(_PS0,0,Serialized) + { + Store(1,R07H) + Store(1,R30H) + } + + // D3 Method for LPT-BiDirectional Mode. + + Method(_PS3,0,Serialized) + { + Store(1,R07H) + Store(0,R30H) + } +} + +Device(PEP1) // Printer, EPP Mode +{ + Name(_HID,EISAID("PNP0400")) + Name(_UID,3) + + // Status Method for LPT-EPP Mode. + + Method(_STA,0,Serialized) + { + // EPP 1.9 mode = 011xxxxxb. + + Store(1,R07H) + If(LOr(LEqual(And(RF0H,0xE0),0x60), LEqual(And(RF0H,0xE0),0x40))) + { + // LPT is in EPP Mode. Only report resources + // to the OS if the SIO Device is not set to + // Disabled in BIOS Setup. + + If(LAnd(NATP,LPTP)) + { + // Display PEPP and return Status. + + If(R30H) + { + Return(0x000F) + } + Else + { + Return(0x000D) + } + } + } + + Return(0x0000) + } + + // Disable Method for LPT-EPP Mode. + + Method(_DIS,0,Serialized) + { + // Set SIO to LPT. + + Store(1,R07H) + + If(LOr(LEqual(And(RF0H,0xE0),0x60), LEqual(And(RF0H,0xE0),0x40))) + { + Store(0,R30H) + } + } + + // Current Resource Setting Method for LPT-EPP Mode. + + Method(_CRS,0,Serialized) + { + // Create a buffer to return to OS. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x0378,0x0378,0x01,0x08) + IRQNoFlags(){7} + }) + + // Skip this sequence if the LPT Device is not set + // to EPP Mode. + + If(LOr(LEqual(And(RF0H,0xE0),0x60), LEqual(And(RF0H,0xE0),0x40))) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Set SIO to LPT. + + Store(1,R07H) + + // Write IO and Length values into the Buffer. + + Store(R61H,IOL0) + Store(R60H,IOH0) + Store(IOL0,IOL1) + Store(IOH0,IOH1) + Store(8,LEN0) + + // Write the IRQ value into the Buffer. + + If(And(R70H,0x0F)) + { + ShiftLeft(One,And(R70H,0x0F),IRQW) + } + Else + { + Store(Zero, IRQW) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for LPT-EPP Mode. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x08) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x08) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x08) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x08) + IRQNoFlags(){5} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for LPT-EPP Mode. + + Method(_SRS,1,Serialized) + { + // Arg0 passed into _SRS is the buffer identical to BUF0. + + CreateByteField(Arg0,0x02,IOL0) + CreateByteField(Arg0,0x03,IOH0) + CreateWordField(Arg0,0x09,IRQW) + + Store(1,R07H) + + // Disable the LPT. + + Store(0,R30H) + + // Set to EPP 1.9 Mode. + + Or(And(RF0H,0x0F),0x60,RF0H) + + // Disable the DMA channels. + + Store(4,R74H) + + // Set the Base IO Address. + + Store(IOL0,R61H) + Store(IOH0,R60H) + + // Set the IRQ. + + FindSetRightBit(IRQW,Local0) + If (LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,R70H) + + // Set the Decode Range so PEPP works when docked. + + And(IOD1,0xFC,IOD1) // Decode all bits. + + If(LEqual(IOH0,0x03)) // Address = 0x378 + { + Or(IOD1,0x00,IOD1) + } + Else // Address = 0x278 + { + Or(IOD1,0x01,IOD1) + } + + // Enable the LPT. + + Store(1,R30H) + } + + // D0 Method for LPT-EPP Mode. + + Method(_PS0,0,Serialized) + { + Store(1,R07H) + Store(1,R30H) + } + + // D3 Method for LPT-EPP Mode. + + Method(_PS3,0,Serialized) + { + Store(1,R07H) + Store(0,R30H) + } +} + +Device(PEC1) // Printer, ECP Mode +{ + Name(_HID,EISAID("PNP0401")) + Name(_UID,4) + + // Status Method for LPT-ECP Mode. + + Method(_STA,0,Serialized) + { + // ECP mode = 1111xxxxxb. + + Store(1,R07H) + If(LOr(LEqual(And(RF0H,0xE0),0xE0), LEqual(And(RF0H,0xE0),0x80))) + { + // LPT is in ECP Mode. Only report resources + // to the OS if the SIO Device is not set to + // Disabled in BIOS Setup. + + If(LAnd(NATP,LPTP)) + { + // Display PECP and return Status. + + If(R30H) + { + Return(0x000F) + } + Else + { + Return(0x000D) + } + } + } + + Return(0x0000) + } + + // Disable Method for LPT-ECP Mode. + + Method(_DIS,0,Serialized) + { + // Set SIO to LPT. + + Store(1,R07H) + + If(LOr(LEqual(And(RF0H,0xE0),0xE0), LEqual(And(RF0H,0xE0),0x80))) + { + Store(0,R30H) + } + } + + // Current Resource Setting Method for LPT-ECP Mode. + + Method(_CRS,0,Serialized) + { + // Create a buffer to return to OS. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x0378,0x0378,0x01,0x08) + IO(Decode16,0x0778,0x0778,0x01,0x08) + IRQNoFlags(){7} + DMA(Compatibility,NotBusMaster,Transfer8_16,){1} + }) + + // Skip this sequence if the LPT Device is not set + // to ECP Mode. + + If(LOr(LEqual(And(RF0H,0xE0),0xE0), LEqual(And(RF0H,0xE0),0x80))) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateByteField(BUF0,0x0A,IOL2) + CreateByteField(BUF0,0x0B,IOH2) + CreateByteField(BUF0,0x0C,IOL3) + CreateByteField(BUF0,0x0D,IOH3) + CreateByteField(BUF0,0x0F,LEN1) + CreateWordField(BUF0,0x11,IRQW) + CreateByteField(BUF0,0x14,DMA0) + + // Set SIO to LPT. + + Store(1,R07H) + + // Write IO and Length values into the Buffer. + + Store(R61H,IOL0) + Store(R60H,IOH0) + Store(IOL0,IOL1) + Store(IOH0,IOH1) + Store(IOL0,IOL2) + Store(Add(0x4,IOH0),IOH2) + Store(IOL0,IOL3) + Store(Add(0x4,IOH0),IOH3) + Store(8,LEN0) + Store(8,LEN1) + + // Write the IRQ value into the Buffer. + + And(R70H,0x0F,Local0) + If(Local0) + { + ShiftLeft(One,Local0,IRQW) + } + Else + { + Store(Zero,IRQW) + } + + // Write the DMA value into the Buffer. + + Store(R74H,Local0) + If(LEqual(Local0,0x04)) + { + Store(Zero,DMA0) + } + Else + { + ShiftLeft(One,Local0,DMA0) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for LPT-ECP Mode. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x08) + IO(Decode16,0x778,0x778,0x01,0x08) + IRQNoFlags(){7} + DMA(Compatibility,NotBusMaster,Transfer8_16){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x08) + IO(Decode16,0x678,0x678,0x01,0x08) + IRQNoFlags(){7} + DMA(Compatibility,NotBusMaster,Transfer8_16){1,2,3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x08) + IO(Decode16,0x778,0x778,0x01,0x08) + IRQNoFlags(){5} + DMA(Compatibility,NotBusMaster,Transfer8_16){1,2,3} + + + + + + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for LPT-ECP Mode. + + Method(_SRS,1,Serialized) + { + // Arg0 passed into _SRS is the buffer identical to BUF0. + + CreateByteField(Arg0,0x02,IOL0) + CreateByteField(Arg0,0x03,IOH0) + CreateWordField(Arg0,0x11,IRQW) + CreateByteField(Arg0,0x14,DMA0) + + Store(1,R07H) + + // Disable the LPT. + + Store(0,R30H) + + // Set to ECP Mode with EPP Mode 4 support. + + Or(RF0H,0xF0,RF0H) + + // Set the Base I/O Address + + Store(IOL0,R61H) + Store(IOH0,R60H) + + // Set the IRQ + + FindSetRightBit(IRQW,Local0) + If (LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,R70H) + + // Set the DMA Channel + + FindSetRightBit(DMA0,Local0) + If (LNotEqual(DMA0,Zero)) + { + Decrement(Local0) + } + Store(Local0,R74H) + + // Set the Decode Range so PECP works when docked. + + And(IOD1,0xFC,IOD1) // Decode all bits. + + If(LEqual(IOH0,0x03)) // Address = 0x378 + { + Or(IOD1,0x00,IOD1) + } + Else // Address = 0x278 + { + Or(IOD1,0x01,IOD1) + } + + // Enable the LPT. + + Store(1,R30H) + } + + // D0 Method for LPT-ECP Mode. + + Method(_PS0,0,Serialized) + { + Store(1,R07H) + Store(1,R30H) + } + + // D3 Method for LPT-ECP Mode. + + Method(_PS3,0,Serialized) + { + Store(1,R07H) + Store(0,R30H) + } +} diff --git a/ReferenceCode/AcpiTables/Dsdt/NAT_SIO.ASL b/ReferenceCode/AcpiTables/Dsdt/NAT_SIO.ASL new file mode 100644 index 0000000..a09b4c8 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/NAT_SIO.ASL @@ -0,0 +1,96 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Device(N393) +{ + Name(_HID,EISAID("PNP0A05")) + + Name(_UID,1) + + // Status Method for the National SIO. + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if the SIO Device is + // present on the Docking Board. + + If(NATP) + { + Return(0x000F) + } + + Return(0x0000) + } + + // Define the SIO Index/Data Registers as an ACPI Operating + // Region. These registers will be used communicate to the SIO. + + OperationRegion(N393, SystemIO, 0x02E, 0x02) + Field(N393, ByteAcc, Lock, Preserve) + { + INDX, 8, + DATA, 8 + } + + // Use ACPI Defined IndexField so consecutive Index/Data I/Os are + // assured to be uninterrupted. + + IndexField(INDX, DATA, ByteAcc, Lock, Preserve) + { + Offset(0x07), // Logical Device Number. + R07H, 8, + Offset(0x20), // SIO Configuration and ID. + R20H, 8, + R21H, 8, + R22H, 8, + R23H, 8, + R24H, 8, + R25H, 8, + R26H, 8, + R27H, 8, + R28H, 8, + R29H, 8, + R2AH, 8, + Offset(0x30), // Logical Device Activate. + R30H, 8, + Offset(0x60), // I/O Space Configuration. + R60H, 8, + R61H, 8, + Offset(0x70), // Interrupt Configuration. + R70H, 8, + R71H, 8, + Offset(0x74), // DMA Configuration. + R74H, 8, + R75H, 8, + Offset(0xF0), // Special Logical Device Configuration. + RF0H, 8, + RF1H, 8 + } + + Include ("NAT_COM.ASL") + Include ("NAT_LPT.ASL") +} diff --git a/ReferenceCode/AcpiTables/Dsdt/Nfc.asl b/ReferenceCode/AcpiTables/Dsdt/Nfc.asl new file mode 100644 index 0000000..c828ac7 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/Nfc.asl @@ -0,0 +1,93 @@ + /**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Ivy Bridge *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + +// +// NFC modules definitions. +// + +scope (\) +{ + // + // Magnetics Peak NFC module + // + Device(NFC1) + { + Name(_HID, EISAID("SKTD000")) + + Method(_STA) + { + If(LEqual(NFCE, 3)) + { + Return(0x0F) // NFC enabled, show it + } + Else + { + Return(0x00) // NFC disabled, hide it + } + } + } + + // + // NXP NFC module + // + Device(NFC2) + { + Name(_HID, EISAID("NXP5442")) + + Method(_STA) + { + If(LEqual(NFCE, 2)) + { + Return(0x0F) // NFC enabled, show it + } + Else + { + Return(0x00) // NFC disabled, hide it + } + } + } + + // + // Magnetics Peak 2 NFC module + // + Device(NFC3) + { + Name(_HID, EISAID("ICV0A12")) + + Method(_STA) + { + If(LEqual(NFCE, 1)) + { + Return(0x0F) // NFC enabled, show it + } + Else + { + Return(0x00) // NFC disabled, hide it + } + } + } +} + diff --git a/ReferenceCode/AcpiTables/Dsdt/PCIEDOCK.ASL b/ReferenceCode/AcpiTables/Dsdt/PCIEDOCK.ASL new file mode 100644 index 0000000..6c2c18b --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/PCIEDOCK.ASL @@ -0,0 +1,89 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Device (\_SB.PCI0.DOCK) +{ + + Name(_HID, "ABCD0000") + Name(_CID, EISAID("PNP0C15")) + Name(_UID,"SADDLESTRING") + + Method(_EJ0, 1) { + P8XH(0,0xED) + If(LEqual(ECON,1)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(1, RefOf(\_SB.PCI0.LPCB.H_EC.EJET)) + } + Return () + } + + Method(_STA, 0) { + If(LEqual(ECON,0)) + { + Return(0x0) + } + If(LEqual(S0ID,1)) + { + Return(0x0) + } + if(\DSTS) { + P8XH(1,0x13) + P8XH(0,0x13) + Return(0x0F) + } else { + P8XH(1,0x14) + P8XH(0,0x14) + Return(0x0) + } + } + + Method(_DCK, 1) { + P8XH(0,0xD3) + + If (Arg0) { + Return (1) + } + Else { + Store(0, \DSTS) + If(LEqual(ECON,1)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.EJET)) + } + Return (1) + } + } + + + Name(_EDL, Package( ) { // DOCK1 has several dependent devices + \_SB.PCI0.RP07.PXSX, + \_SB.PCI0.RP08.PXSX, + \_SB.PCI0.EHC1, + \_SB.PCI0.SAT0, + \_SB.PCI0.HDEF, + }) + +} diff --git a/ReferenceCode/AcpiTables/Dsdt/PCI_DRC.ASL b/ReferenceCode/AcpiTables/Dsdt/PCI_DRC.ASL new file mode 100644 index 0000000..a461e59 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/PCI_DRC.ASL @@ -0,0 +1,138 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Scope (\_SB.PCI0){ + + Device(PDRC) + { + // + // PCI Device Resource Consumption + // + + Name(_HID,EISAID("PNP0C02")) + + Name(_UID,1) + + Name(BUF0,ResourceTemplate() + { + // + // RCRB BAR _BAS will be updated in _CRS below according to B0:D31:F0:Reg.F0 + // + Memory32Fixed(ReadWrite,0,0x04000,RCRB) + // + // MCH BAR _BAS will be updated in _CRS below according to B0:D0:F0:Reg.48h + // + Memory32Fixed(ReadWrite,0,0x08000,MCHB) + // + // DMI BAR _BAS will be updated in _CRS below according to B0:D0:F0:Reg.68h + // + Memory32Fixed(ReadWrite,0,0x01000,DMIB) + // + // EP BAR _BAS will be updated in _CRS below according to B0:D0:F0:Reg.40h + // + Memory32Fixed(ReadWrite,0,0x01000,EGPB) + // + // PCI Express BAR _BAS and _LEN will be updated in _CRS below according to B0:D0:F0:Reg.60h + // + Memory32Fixed(ReadWrite,0,0,PCIX) + + // + // MISC ICH TTT base address reserved for the TxT module use. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed(ReadWrite,0xFED20000,0x20000) + + // + // VTD engine memory range. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed(ReadOnly, 0xFED90000, 0x00004000) + + // + // MISC ICH. Check if the hard code meets the real configuration. + // If not, dynamically update it like the _CRS method below. + // + Memory32Fixed(ReadWrite,0xFED45000,0x4B000,TPMM) + + // + // FLASH range + // + Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000, FIOH) //16MB as per IOH spec + + // + // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) + // + Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH) + + // + // Thermal Base Address. TBAR _BAS and _LEN will be updated in _CRS below according to B0:D31:F6:Reg.40h + // + Memory32Fixed (ReadWrite, 0, 0x01000, TBAR) + + // + // S3 Save And Restore temporay memory bar + // + Memory32Fixed (ReadWrite, 0, 0x10000, SNRB) + + }) + + + Method(_CRS,0,Serialized) + { + CreateDwordField(BUF0,^RCRB._BAS,RBR0) + ShiftLeft(\_SB.PCI0.LPCB.RCBA,14,RBR0) + + CreateDwordField(BUF0,^TBAR._BAS,TBR0) + Store(TBAB,TBR0) + CreateDwordField(BUF0,^TBAR._LEN,TBLN) + If(LEqual(TBAB,0)){ + Store(0,TBLN) + } + + CreateDwordField(BUF0,^SNRB._BAS,SNR0) + Store(\SRMB,SNR0) // SRMB is defined in PCH.asl + + + CreateDwordField(BUF0,^MCHB._BAS,MBR0) + ShiftLeft(\_SB.PCI0.MHBR,15,MBR0) + + CreateDwordField(BUF0,^DMIB._BAS,DBR0) + ShiftLeft(\_SB.PCI0.DIBR,12,DBR0) + + CreateDwordField(BUF0,^EGPB._BAS,EBR0) + ShiftLeft(\_SB.PCI0.EPBR,12,EBR0) + + CreateDwordField(BUF0,^PCIX._BAS,XBR0) + ShiftLeft(\_SB.PCI0.PXBR,26,XBR0) + + CreateDwordField(BUF0,^PCIX._LEN,XSZ0) + ShiftRight(0x10000000, \_SB.PCI0.PXSZ,XSZ0) + + Return(BUF0) + } + } //end of PDRC +} // end of SB diff --git a/ReferenceCode/AcpiTables/Dsdt/Platform.asl b/ReferenceCode/AcpiTables/Dsdt/Platform.asl new file mode 100644 index 0000000..401f94a --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/Platform.asl @@ -0,0 +1,1880 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +// Define the following External variables to prevent a WARNING when +// using ASL.EXE and an ERROR when using IASL.EXE. + +External(PDC0) +External(PDC1) +External(PDC2) +External(PDC3) +External(PDC4) +External(PDC5) +External(PDC6) +External(PDC7) +External(\_PR.CFGD) + +External(\_SB.IAOE.PTSL) +External(\_SB.IAOE.ECTM) +External(\_SB.IAOE.RCTM) +External(\_SB.IAOE.ITMR) +External(\_SB.IAOE.FFSE) +External(\_SB.IFFS.FFSS) +External(\_SB.IAOE.PCIS) + +External(\_SB.IAOE.IBT1) // Isct Byte1 for EC +External(\_SB.IAOE.WKRS) // ISCT Wake Reason +#if !defined(ASL_Remove_SaSsdt_Data_To_Dsdt) || (ASL_Remove_SaSsdt_Data_To_Dsdt == 0) +External(\_SB.PCI0.GFX0.TCHE) // Technology enabled indicator +External(\_SB.PCI0.GFX0.STAT) // State Indicator +External(\_SB.PCI0.B0D3.ABAR) +External(\_SB.PCI0.B0D3.BARA) +External(\SGMD) +#endif + +External(\_SB.TPM.PTS, MethodObj) +External(\_SB.PCI0.I2C0.SHUB.PI2C.PUAM, MethodObj) //DUAM - Device User Absent Mode +External(\_SB.PCI0.PAUD.PUAM, MethodObj) //PUAM - PowerResource User Absent Mode +External(\_SB.PCI0.XHC.DUAM, MethodObj) //DUAM - Device User Absent Mode for XHCI controller +#ifndef AMI_OVERRIDE_FOR_ACPI_DEBUG +External(\MDBG, MethodObj) +#endif // AMI_OVERRIDE_FOR_ACPI_DEBUG + +External(\_SB.PCI0.PEG0.PEGP.EPON, MethodObj) +External(\_SB.PCI0.RP05.PEGP.EPON, MethodObj) + +#define CONVERTIBLE_BUTTON 6 +#define DOCK_INDICATOR 7 + +Name(ECUP, 1) // EC State indicator: 1- Normal Mode 0- Low Power Mode +Mutex(EHLD, 0) // EC Hold indicator: 0- No one accessing the EC Power State 1- Someone else is accessing the EC Power State + +// NFC module support +include("Nfc.asl") + +// Create a Global MUTEX. + +Mutex(MUTX,0) + +//AMI_OVERRIDE --- Debug output registers. >> +//------------------------------------------------------------------------ +// Procedure: DBG8 +// Procedure: DBG9 +// Description: Logical names for Debug ports 0x80(byte) and 0x90(word). +// If such debug ports exist in the System, the value, stored +// into the Port will be displayed to LED +// Input: Nothing +// Output: Nothing +//------------------------------------------------------------------------- + +OperationRegion (DEB0, SystemIO, 0x80, 1) +Field (DEB0, ByteAcc, NoLock, Preserve) +{ DBG8, 8 } + +OperationRegion (DEB1, SystemIO, 0x90, 2) +Field (DEB1, WordAcc, NoLock, Preserve) +{ DBG9, 16 } +//AMI_OVERRIDE --- Debug output registers. << + +#if 0 //AMI_OVERRIDE --- Below ASL code is for Thunderbolt, AMI thunderbolt module has taken care it already.>> +// OS Up mutex +Mutex(OSUM, 0) +// WAK Finished mutex +Mutex(WFDM, 0) +#endif //AMI_OVERRIDE --- it is for Thunderbolt, AMI thunderbolt module has taken care it already. << + +// Define Port 80 as an ACPI Operating Region to use for debugging. Please +// note that the Intel CRBs have the ability to ouput an entire DWord to +// Port 80h for debugging purposes, so the model implemented here may not be +// able to be used on OEM Designs. + +OperationRegion(PRT0,SystemIO,0x80,4) +Field(PRT0,DwordAcc,Lock,Preserve) +{ + P80H, 32 +} + + +// Port 80h Update: +// Update 8 bits of the 32-bit Port 80h. +// +// Arguments: +// Arg0: 0 = Write Port 80h, Bits 7:0 Only. +// 1 = Write Port 80h, Bits 15:8 Only. +// 2 = Write Port 80h, Bits 23:16 Only. +// 3 = Write Port 80h, Bits 31:24 Only. +// Arg1: 8-bit Value to write +// +// Return Value: +// None + +Method(P8XH,2,Serialized) +{ + If(LEqual(Arg0,0)) // Write Port 80h, Bits 7:0. + { + Store(Or(And(P80D,0xFFFFFF00),Arg1),P80D) + } + + If(LEqual(Arg0,1)) // Write Port 80h, Bits 15:8. + { + Store(Or(And(P80D,0xFFFF00FF),ShiftLeft(Arg1,8)),P80D) + } + + If(LEqual(Arg0,2)) // Write Port 80h, Bits 23:16. + { + Store(Or(And(P80D,0xFF00FFFF),ShiftLeft(Arg1,16)),P80D) + } + + If(LEqual(Arg0,3)) // Write Port 80h, Bits 31:24. + { + Store(Or(And(P80D,0x00FFFFFF),ShiftLeft(Arg1,24)),P80D) + } + + Store(P80D,P80H) +} + +Method(ADBG,1,Serialized) +{ +#ifndef AMI_OVERRIDE_FOR_ACPI_DEBUG + If(CondRefOf(MDBG)) + { + Return(MDBG(Arg0)) + } + Return(0) +#endif // AMI_OVERRIDE_FOR_ACPI_DEBUG +} + +// +// Define SW SMI port as an ACPI Operating Region to use for generate SW SMI. +// +OperationRegion(SPRT,SystemIO, 0xB2,2) +Field (SPRT, ByteAcc, Lock, Preserve) { + SSMP, 8 +} + +// The _PIC Control Method is optional for ACPI design. It allows the +// OS to inform the ASL code which interrupt controller is being used, +// the 8259 or APIC. The reference code in this document will address +// PCI IRQ Routing and resource allocation for both cases. +// +// The values passed into _PIC are: +// 0 = 8259 +// 1 = IOAPIC + +Method(\_PIC,1) +{ + Store(Arg0,GPIC) + Store(Arg0,PICM) +} + +// Prepare to Sleep. The hook is called when the OS is about to +// enter a sleep state. The argument passed is the numeric value of +// the Sx state. + +Method(_PTS,1) +{ + Store(0,P80D) // Zero out the entire Port 80h DWord. + P8XH(0,Arg0) // Output Sleep State to Port 80h, Byte 0. + + PTS(Arg0) //AMI_OVERRIDE --- Invoke PTS Method PRIOR TO ENTER ANY SLEEP STATE + ADBG(Concatenate("_PTS=",ToHexString(Arg0))) +#if 0 //AMI_OVERRIDE --- Below ASL code is for Thunderbolt, AMI thunderbolt module has taken care it already.>> + If(LOr(LEqual(BID, BICO),LEqual(BID, BICC))) { + Acquire(WFDM, 0xFFFF) + Store(0, WKFN) + Release(WFDM) + } + +#endif //AMI_OVERRIDE --- it is for Thunderbolt, AMI thunderbolt module has taken care it already. << + // + // Save Sleep state if iSCT is present + // + If(And(ICNF, 0x10)) + { + If(CondRefOf(\_SB.IAOE.PTSL)) + { + Store(Arg0, \_SB.IAOE.PTSL) + } + } + + // If code is executed, Wake from RI# via Serial Modem will be + // enabled. If code is not executed, COM Port Debugging throughout + // all Sx states will be enabled. + + If(LEqual(Arg0,3)) + { + // + // Disable update DTS temperature and threshold value in every SMI + // + If(LAnd(DTSE, LGreater(TCNT, 1))) + { + TRAP(\TRTD,30) + } + + // + // Set EC timer if iSCT enabled and EC timer is being used + // +#ifndef AMI_OVERRIDE_FOR_EC_SUPPORT + If(LEqual(\ECON,1)) + { +#endif // AMI_OVERRIDE_FOR_EC_SUPPORT + If(And(ICNF, 0x01)) + { + // + // ISCT SASD - Set EC based timer. + // + If(LAnd(And(ICNF, 0x10), LEqual(\_SB.IAOE.ITMR, 0))) + { + If (LAnd(CondRefOf(\_SB.PCI0.LPCB.H_EC.AWT0), CondRefOf(\_SB.IAOE.ECTM))) + { + If (LGreater(\_SB.IAOE.ECTM, 0)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(And(\_SB.IAOE.ECTM, 0xFF), RefOf(\_SB.PCI0.LPCB.H_EC.AWT0)) + \_SB.PCI0.LPCB.H_EC.ECWT(ShiftRight(And(\_SB.IAOE.ECTM, 0xFF00), 8), RefOf(\_SB.PCI0.LPCB.H_EC.AWT1)) + \_SB.PCI0.LPCB.H_EC.ECWT(ShiftRight(And(\_SB.IAOE.ECTM, 0xFF0000), 16), RefOf(\_SB.PCI0.LPCB.H_EC.AWT2)) + // + // Enable EC timer - BIT7 + // Enable wake from S3 on timer exiry - BIT0 + // + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.WTMS)), Local0) + \_SB.PCI0.LPCB.H_EC.ECWT(Or(0x81,Local0), RefOf(\_SB.PCI0.LPCB.H_EC.WTMS)) + } + } + } + + // + // ISCT - Check if RapidStart service exist or not + // If RapidStart then enable EC timer wake from S4. + // + If(LAnd(And(ICNF, 0x10), CondRefOf(\_SB.IFFS.FFSS))) + { + If (And(\_SB.IFFS.FFSS, 0x01)) + { + Store(1, \_SB.IAOE.FFSE) + If (LAnd(CondRefOf(\_SB.PCI0.LPCB.H_EC.WTMS), LEqual(\_SB.IAOE.PTSL, 0x03))) + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.WTMS)), Local0) + // + // Enable wake from S4 on timer exiry - BIT1 + // + \_SB.PCI0.LPCB.H_EC.ECWT(Or(0x02,Local0), RefOf(\_SB.PCI0.LPCB.H_EC.WTMS)) + } + } + Else + { + Store(0, \_SB.IAOE.FFSE) + } + } + } +#ifndef AMI_OVERRIDE_FOR_EC_SUPPORT + } +#endif // AMI_OVERRIDE_FOR_EC_SUPPORT + + } + // + // Save EC 10Sec mode to NVS data PB1E Bit7 at S3/S4 entry + // + If(LOr(LEqual(Arg0,3), LEqual(Arg0,4))) + { + If(LAnd(CondRefOf(\_SB.PCI0.LPCB.H_EC.PB10), \ECON)){ + // + // Check EC 10sec PB mode is enabled.(H_EC.PB10) + // PB10 is cleared at every boot so we need to keep the state before entering S3/S4. + // + If(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PB10))) + { + // + // EC 10sec PB mode is enabled. Save the state in PB1E bit7 + // + Or(PB1E, 0x80, PB1E) + } + Else + { + // + // EC 10sec PB mode is not enabled. Clear PB1E bit7. + // + And(PB1E, 0x7F, PB1E) + } + } + } + + +#if 0 //AMI_OVERRIDE --- It is for CRB SIO using, OEM doesn't need to it. >> + If(LEqual(DBGS,0)) + { + Store(0,RT10) // Set MAXIM Transceiver = FORCEOFF. + Store(0x20,PME1) // Set SMSC GPI15 = Wake Event. + Store(1,PME0) // Set SMSC PME Enable. + Store(0x20,PMS1) // Clear GPI15 Status. + Store(1,PMS0) // Clear PME Status. + } +#endif //AMI_OVERRIDE --- It is for CRB SIO using, OEM doesn't need to it. << + + // Generate a SW SMI trap to save some NVRAM data back to CMOS. + + // Don't enable IGD OpRegion support yet. + // TRAP(1, 81) + // + // Call TPM.PTS + // + If(CondRefOf(\_SB.TPM.PTS)) + { + // + // Call TPM PTS method + // + \_SB.TPM.PTS (Arg0) + } + + // StandBy LED Drive. Program High for sleep state s3, s4 and s5 only fro desktop. + If(LOr(LOr(LEqual(Arg0,3), LEqual(Arg0,4)), LEqual(Arg0,5))){ + If(LEqual(PFLV,FDTP)){ + Store(1, \GP27) + } + } +} + +#if 0 //AMI_OVERRIDE --- Below ASL code is for Thunderbolt, AMI thunderbolt module has taken care it already.>> +External(\_GPE.OSUP, MethodObj) +External(\_GPE.MMTB, MethodObj) + + Method(MMRP) + { + Store(PEBS, Local0) // MMIO Base address + Add(Local0, 0xE0000, Local0) // RP01 + Subtract(ToInteger(TBSE), 1, Local1) + Multiply(Local1, 0x1000, Local1) + Add(Local0, Local1, Local0) // RP0x + + Return(Local0) + } +#endif //AMI_OVERRIDE --- It is for CRB SIO using, OEM doesn't need to it. << + +// Wake. This hook is called when the OS is about to wake from a +// sleep state. The argument passed is the numeric value of the +// sleep state the system is waking from. + +Method(_WAK,1,Serialized) +{ + P8XH(1,0xAB) // Beginning of _WAK. + + WAK(Arg0) //AMI_OVERRIDE --- Invoke WAK Method WHILE WAKE FROM ANY SLEEP STATE + + ADBG("_WAK") + + If(LOr(LEqual(Arg0,3), LEqual(Arg0,4))) // If S3 or S4 Resume + { + // + // During S3/S4 wake add indicator for 'Switchable/Hybrid Graphics endpoint device is on' + // + If(CondRefOf(\_SB.PCI0.PEG0.PEGP.EPON)) + { + \_SB.PCI0.PEG0.PEGP.EPON() + } + + If(CondRefOf(\_SB.PCI0.RP05.PEGP.EPON)) + { + \_SB.PCI0.RP05.PEGP.EPON() + } + } + + // + // Save a valid Audio BAR for the ABWA W/A + // + If (LAnd (LNotEqual (And(\_SB.PCI0.B0D3.ABAR, 0xFFFFC004), 0xFFFFC004), LNotEqual (And (\_SB.PCI0.B0D3.ABAR, 0xFFFFC000), 0))) { + Store (\_SB.PCI0.B0D3.ABAR, \_SB.PCI0.B0D3.BARA) + } + + // + // Clear iSCT timers and sleep settings if iSCT is present + // + If(And(ICNF, 0x10)) + { + // + // If Graphics Driver supports disable display notification in ISCT mode + // + If (And(\_SB.PCI0.GFX0.TCHE, 0x100)) + { + // + // Notify Gfx driver that the platform is in Isct Mode + // + If (LEqual(\_SB.IAOE.ITMR, 1)) + { + // + // If ISCT Mode and Wake Reason is ISCT wake (RTC Timer or Network PME) + // Then notify graphics driver to turn off display + // + If (LAnd(And(\_SB.IAOE.IBT1, 0x01), LOr(And(\_SB.IAOE.WKRS, 0x02), And(\_SB.IAOE.WKRS, 0x10)))) { + Store(Or(And(\_SB.PCI0.GFX0.STAT, Not(0x03)), 0x01), \_SB.PCI0.GFX0.STAT) // BITS[1:0] = 01, ISCT Resume + } else { + Store(And(\_SB.PCI0.GFX0.STAT, Not(0x03)), \_SB.PCI0.GFX0.STAT) // BITS[1:0] = 00, Normal Resume to S0 + } + } else { + If(LEqual(\ECON,1)) { + If(CondRefOf(\_SB.PCI0.LPCB.H_EC.IBT1)) { + // + // If ISCT Mode and Wake Reason is ISCT wake (EC Timer or Network PME) + // Then notify graphics driver to turn off display + // + If (LAnd(And(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.IBT1)), 0x01), LOr(And(\_SB.IAOE.WKRS, 0x02), And(\_SB.IAOE.WKRS, 0x10)))) { + Store(Or(And(\_SB.PCI0.GFX0.STAT, Not(0x03)), 0x01), \_SB.PCI0.GFX0.STAT) // BITS[1:0] = 01, ISCT Resume + } else { + Store(And(\_SB.PCI0.GFX0.STAT, Not(0x03)), \_SB.PCI0.GFX0.STAT) // BITS[1:0] = 00, Normal Resume to S0 + } + } + } // (LEqual(\ECON,1)) + } + } + + If(CondRefOf(\_SB.IAOE.PTSL)) + { + Store(0, \_SB.IAOE.PTSL) + } + If (LEqual(\_SB.IAOE.ITMR, 0)) { + If(CondRefOf(\_SB.PCI0.LPCB.H_EC.WTMS)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.WTMS)) + } + } + If (CondRefOf(\_SB.IAOE.ECTM)) + { + Store(0, \_SB.IAOE.ECTM) + } + If (CondRefOf(\_SB.IAOE.RCTM)) + { + Store(0, \_SB.IAOE.RCTM) + } + } + + If(NEXP) + { + // Reinitialize the Native PCI Express after resume + + If(And(OSCC,0x02)) + { + \_SB.PCI0.NHPG() + } + If(And(OSCC,0x04)) // PME control granted? + { + \_SB.PCI0.NPME() + } + } + + If(LEqual(Arg0,3)) + { + // Turn off the CPU Fan for all OSes if Active Cooling + // is disabled. + + If(LEqual(0,ACTT)) + { + If(LEqual(\ECON,1)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.CFAN)) + } + } + } + + If(LOr(LEqual(Arg0,3), LEqual(Arg0,4))) // If S3 or S4 Resume + { + + // + // Restore EC 10sec PB override mode + // + If(LAnd(CondRefOf(\_SB.PCI0.LPCB.H_EC.PB10), \ECON)){ + If(And(PB1E, 0x80)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(1, RefOf(\_SB.PCI0.LPCB.H_EC.PB10)) + } + } + + // Check to send Convertible/Dock state changes upon resume from Sx. + + If(And(GBSX,0x40)) + { + \_SB.PCI0.GFX0.IUEH(6) + + // + // Do the same thing for Virtul Button device. + // Toggle Bit3 of PB1E(Slate/Notebook status) + // +#if defined(ASL_CRB_EC_SUPPORT) && (ASL_CRB_EC_SUPPORT == 1) + Xor(PB1E, 0x08, PB1E) + + // + // Update VGBS(V-GPIO Button state) accordingly. + // + If(And(PB1E, 0x08)){ + If(LAnd(CondRefOf(\_SB.PCI0.LPCB.H_EC.VGBI), \ECON)) + { + \_SB.PCI0.LPCB.H_EC.VGBI.UPBT(CONVERTIBLE_BUTTON, One) + } + } + Else + { + If(LAnd(CondRefOf(\_SB.PCI0.LPCB.H_EC.VGBI), \ECON)) + { + \_SB.PCI0.LPCB.H_EC.VGBI.UPBT(CONVERTIBLE_BUTTON, Zero) + } + } +#endif //#ifdef ASL_CRB_EC_SUPPORT + } + + If(And(GBSX,0x80)) + { + \_SB.PCI0.GFX0.IUEH(7) + + // + // Do the same thing for Virtul Button device. + // Toggle Bit4 of PB1E (Dock/Undock status) + // +#if defined(ASL_CRB_EC_SUPPORT) && (ASL_CRB_EC_SUPPORT == 1) + Xor(PB1E, 0x10, PB1E) + + // + // Update VGBS(Virtual Button state) accordingly. + // + If(And(PB1E, 0x10)) + { + If(LAnd(CondRefOf(\_SB.PCI0.LPCB.H_EC.VGBI), \ECON)) + { + \_SB.PCI0.LPCB.H_EC.VGBI.UPBT(DOCK_INDICATOR, One) + } + } + Else + { + If(LAnd(CondRefOf(\_SB.PCI0.LPCB.H_EC.VGBI), \ECON)) + { + \_SB.PCI0.LPCB.H_EC.VGBI.UPBT(DOCK_INDICATOR, Zero) + } + } + +#endif //#ifdef ASL_CRB_EC_SUPPORT + } + + +#if defined(ASL_CRB_EC_SUPPORT) && (ASL_CRB_EC_SUPPORT == 1) + // + // Prevent reinitializing Virtual GPIO Button status + // + If(CondRefOf(\_SB.PCI0.LPCB.H_EC.VGBI.ONTM)) + { + Store(1, \_SB.PCI0.LPCB.H_EC.VGBI.ONTM) + } +#endif //#ifdef ASL_CRB_EC_SUPPORT + If(LAnd(DTSE, LGreater(TCNT, 1))) + { + TRAP(\TRTD, 20) + } + + // Windows XP SP2 does not properly restore the P-State + // upon resume from S4 or S3 with degrade modes enabled. + // Use the existing _PPC methods to cycle the available + // P-States such that the processor ends up running at + // the proper P-State. + // + // Note: For S4, another possible W/A is to always boot + // the system in LFM. + // + + If(LEqual(OSYS,2002)) + { + If(And(\_PR.CFGD,0x01)) + { + If(LGreater(\_PR.CPU0._PPC,0)) + { + Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC) + PNOT() + Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC) + PNOT() + } + Else + { + Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC) + PNOT() + Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC) + PNOT() + } + } + } + + If(LEqual(\ECON,1)) + { + // Update Lid state after S3 or S4 resume + If(LOr(LEqual(Arg0,3), LEqual(Arg0,4))) // If S3 or S4 Resume + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.LSTE)), LIDS) + + If(IGDS) + { + If (LEqual(LIDS, 0)) + { + Store(0x80000000,\_SB.PCI0.GFX0.CLID) + } + If (LEqual(LIDS, 1)) + { + Store(0x80000003,\_SB.PCI0.GFX0.CLID) + } + } + Notify(\_SB.LID0,0x80) + } + + // Detect the change of Dock state + If(LNotEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.DOCK)), \DSTS)) + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.DOCK)), \DSTS) + If(LAnd(\_SB.PCI0.HDEF.DCKS, 1)) + { + Store(\DSTS, \_SB.PCI0.HDEF.DCKA) + } + If(LEqual(\DSTS, 1)) // Docked. + { + If(LEqual(Arg0,3)) + { + Sleep(1000) // Delay 1 second for hot docking stability + Store(\PDBR, \SSMP) + Sleep(1000) // Delay 1 second for hot docking stability + } + Notify(\_SB.PCI0.DOCK, 0) + } + Else // Undocked. + { + Notify(\_SB.PCI0.DOCK, 1) + } + } + + // Detect the change of Power State. + If(LEqual(BNUM,0)) + { + If(LNotEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.VPWR)),PWRS)) + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.VPWR)),PWRS) + // Perform needed ACPI Notifications. + PNOT() + } + } + Else + { + If(LNotEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.RPWR)),PWRS)) + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.RPWR)),PWRS) + // Perform needed ACPI Notifications. + PNOT() + } + } + } + +#if 0 //AMI_OVERRIDE --- Below ASL code is for Thunderbolt, AMI thunderbolt module has taken care it already.>> + If(LOr(LEqual(BID, BICO),LEqual(BID, BICC))) { + Acquire(OSUM, 0xFFFF) + Store(MMRP(), Local0) + OperationRegion(RP_X,SystemMemory,Local0,0x20) + Field(RP_X,DWordAcc, NoLock, Preserve) + { + REG0, 32, + REG1, 32, + REG2, 32, + REG3, 32, + REG4, 32, + REG5, 32, + REG6, 32, + REG7, 32 + } + Store(REG6, Local1) + Store(0x00F0F000, REG6) + Store(\_GPE.MMTB(), Local2) + \_GPE.OSUP(Local2) + Store(Local1, REG6) + Release(OSUM) + } +#endif //AMI_OVERRIDE --- it is for Thunderbolt, AMI thunderbolt module has taken care it already. << + + // For PCI Express Express Cards, it is possible a device was + // either inserted or removed during an Sx State. The problem + // is that no wake event will occur for a given warm inseration + // or removal, so the OS will not become aware of any change. + // To get around this, re-enumerate all Express Card slots. + // + // If the Root Port is enabled, it may be assumed to be hot-pluggable. + +#if defined(ASL_RC_PORT_0) && (ASL_RC_PORT_0==1) + If(LEqual(RP1D,0)) + { + Notify (\_SB.PCI0.RP01,0) + } +#endif // ASL_RC_PORT_0 + +#if defined(ASL_RC_PORT_1) && (ASL_RC_PORT_1==1) + If(LEqual(RP2D,0)) + { + Notify (\_SB.PCI0.RP02,0) + } +#endif // ASL_RC_PORT_1 + +#if defined(ASL_RC_PORT_2) && (ASL_RC_PORT_2==1) + If(LEqual(RP3D,0)) + { + Notify (\_SB.PCI0.RP03,0) + } +#endif // ASL_RC_PORT_2 + +#if defined(ASL_RC_PORT_3) && (ASL_RC_PORT_3==1) + If(LEqual(RP4D,0)) + { + Notify (\_SB.PCI0.RP04,0) + } +#endif // ASL_RC_PORT_3 + +#if defined(ASL_RC_PORT_4) && (ASL_RC_PORT_4==1) + If(LEqual(RP5D,0)) + { + Notify (\_SB.PCI0.RP05,0) + } +#endif // ASL_RC_PORT_4 + +#if defined(ASL_RC_PORT_5) && (ASL_RC_PORT_5==1) + If(LEqual(\RP6D,0)) + { + Notify (\_SB.PCI0.RP06,0) + } +#endif // ASL_RC_PORT_5 + +#if defined(ASL_RC_PORT_6) && (ASL_RC_PORT_6==1) + If(LEqual(RP7D,0)) + { + If(LEqual(\DSTS,0)) // UnDocked. + { + Notify (\_SB.PCI0.RP07,0) + } + } +#endif // ASL_RC_PORT_6 + +#if defined(ASL_RC_PORT_7) && (ASL_RC_PORT_7==1) + If(LEqual(RP8D,0)) + { + If(LEqual(\DSTS,0)) // UnDocked. + { + Notify (\_SB.PCI0.RP08,0) + } + } +#endif // ASL_RC_PORT_7 + } + + If(LOr(LEqual(Arg0,3), LEqual(Arg0,4))) // If S3 or S4 Resume + { + // + // To support Win8, RapidStart resume from G3 and resume from DeepSx state + // + \_SB.PCI0.XHC.XWAK() + } +#if 0 //AMI_OVERRIDE --- Below ASL code is for Thunderbolt, AMI thunderbolt module has taken care it already.>> + If(LOr(LEqual(BID, BICO),LEqual(BID, BICC))) { + Acquire(WFDM, 0xFFFF) + Store(1, WKFN) + Release(WFDM) + ADBG(Concatenate("_WAK=", ToHexString(Timer))) + } +#endif //AMI_OVERRIDE --- it is for Thunderbolt, AMI thunderbolt module has taken care it already. << + Return(Package(){0,0}) +} + +// Get Buffer: +// This method will take a buffer passed into the method and +// create then return a smaller buffer based on the pointer +// and size parameters passed in. +// +// Arguments: +// Arg0: Pointer to start of new Buffer in passed in Buffer. +// Arg1: Size of Buffer to create. +// Arg2: Original Buffer +// +// Return Value: +// Newly created buffer. + +Method(GETB,3,Serialized) +{ + Multiply(Arg0,8,Local0) // Convert Index. + Multiply(Arg1,8,Local1) // Convert Size. + CreateField(Arg2,Local0,Local1,TBF3) // Create Buffer. + + Return(TBF3) // Return Buffer. +} + +// Power Notification: +// Perform all needed OS notifications during a +// Power Switch. +// +// Arguments: +// None +// +// Return Value: +// None + +Method(PNOT,0,Serialized) +{ + // + // If MP enabled and driver support is present, notify all + // processors. + // + If(CondRefOf(\_SB.PCCD.PENB)) { // is CPPC enabled in SETUP? + Notify(\_SB.PCCD,0x82) // CPPC notify + } Else { + If(LGreater(TCNT, 1)) + { + If(And(PDC0,0x0008)){ + Notify(\_PR.CPU0,0x80) // Eval CPU0 _PPC. + } + If(And(PDC1,0x0008)){ + Notify(\_PR.CPU1,0x80) // Eval CPU1 _PPC. + } + If(And(PDC2,0x0008)){ + Notify(\_PR.CPU2,0x80) // Eval CPU2 _PPC. + } + If(And(PDC3,0x0008)){ + Notify(\_PR.CPU3,0x80) // Eval CPU3 _PPC. + } + If(And(PDC4,0x0008)){ + Notify(\_PR.CPU4,0x80) // Eval CPU4 _PPC. + } + If(And(PDC5,0x0008)){ + Notify(\_PR.CPU5,0x80) // Eval CPU5 _PPC. + } + If(And(PDC6,0x0008)){ + Notify(\_PR.CPU6,0x80) // Eval CPU6 _PPC. + } + If(And(PDC7,0x0008)){ + Notify(\_PR.CPU7,0x80) // Eval CPU7 _PPC. + } + }Else{ + Notify(\_PR.CPU0,0x80) // Eval _PPC. + } + } + + If(LGreater(TCNT, 1)){ + If(LAnd(And(PDC0,0x0008),And(PDC0,0x0010))){ + Notify(\_PR.CPU0,0x81) // Eval CPU0 _CST. + } + If(LAnd(And(PDC1,0x0008),And(PDC1,0x0010))){ + Notify(\_PR.CPU1,0x81) // Eval CPU1 _CST. + } + If(LAnd(And(PDC2,0x0008),And(PDC2,0x0010))){ + Notify(\_PR.CPU2,0x81) // Eval CPU2 _CST. + } + If(LAnd(And(PDC3,0x0008),And(PDC3,0x0010))){ + Notify(\_PR.CPU3,0x81) // Eval CPU3 _CST. + } + If(LAnd(And(PDC4,0x0008),And(PDC4,0x0010))){ + Notify(\_PR.CPU4,0x81) // Eval CPU4 _CST. + } + If(LAnd(And(PDC5,0x0008),And(PDC5,0x0010))){ + Notify(\_PR.CPU5,0x81) // Eval CPU5 _CST. + } + If(LAnd(And(PDC6,0x0008),And(PDC6,0x0010))){ + Notify(\_PR.CPU6,0x81) // Eval CPU6 _CST. + } + If(LAnd(And(PDC7,0x0008),And(PDC7,0x0010))){ + Notify(\_PR.CPU7,0x81) // Eval CPU7 _CST. + } + }Else{ + Notify(\_PR.CPU0,0x81) // Eval _CST. + } + + // Update the Battery 1 and 2 Stored Capacity and + // Stored Status. Battery 0 information is always accurrate. + + If(LEqual(\ECON,1)) + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1CC)),B1SC) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1ST)),B1SS) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B2CC)),B2SC) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B2ST)),B2SS) + + // Perform update to all Batteries in the System. + If(LGreaterEqual(OSYS,2006)) // Vista and Win7 later on OS + { + Notify(\_SB.PCI0.LPCB.H_EC.BAT0,0x81) // Eval BAT0 _BST. + Notify(\_SB.PCI0.LPCB.H_EC.BAT1,0x81) // Eval BAT1 _BST. + Notify(\_SB.PCI0.LPCB.H_EC.BAT2,0x81) // Eval BAT2 _BST. + } + Else + { + Notify(\_SB.PCI0.LPCB.H_EC.BAT0,0x80) // Eval BAT0 _BST. + Notify(\_SB.PCI0.LPCB.H_EC.BAT1,0x80) // Eval BAT1 _BST. + Notify(\_SB.PCI0.LPCB.H_EC.BAT2,0x80) // Eval BAT2 _BST. + } + } + + If (LEqual(DPTF,1)){ + Notify(\_SB.IETM, 0x86) // Notification sent to DPTF driver (Policy) for PDRT reevaluation after AC/DC transtion has occurred. + } +} + +// +// Memory window to the CTDP registers starting at MCHBAR+5000h. +// +OperationRegion (MBAR, SystemMemory, Add(ShiftLeft(\_SB.PCI0.MHBR,15),0x5000), 0x1000) + Field (MBAR, ByteAcc, NoLock, Preserve) + { + Offset (0x938), // PACKAGE_POWER_SKU_UNIT (MCHBAR+0x5938) + PWRU, 4, // Power Units [3:0] unit value is calculated by 1 W / Power(2,PWR_UNIT). The default value of 0011b corresponds to 1/8 W. + Offset (0x9A0), // TURBO_POWER_LIMIT1 (MCHBAR+0x59A0) + PPL1, 15, // PKG_PWR_LIM_1 [14:0] + PL1E,1, // PKG_PWR_LIM1_EN [15] + CLP1,1, // Package Clamping Limitation 1 + } +Name(CLMP, 0) // save the clamp bit +Name(PLEN,0) // save the power limit enable bit +Name(PLSV,0x8000) // save value of PL1 upon entering CS +Name(CSEM, 0) //semaphore to avoid multiple calls to SPL1. SPL1/RPL1 must always be called in pairs, like push/pop off a stack +// +// SPL1 (Set PL1 to 4.5 watts with clamp bit set) +// Per Legacy Thermal management CS requirements, we would like to set the PL1 limit when entering CS to 4.5W with clamp bit set via MMIO. +// This can be done in the ACPI object which gets called by graphics driver during CS Entry. +// Likewise, during CS exit, the BIOS must reset the PL1 value to the previous value prior to CS entry and reset the clamp bit. +// +// Arguments: +// None +// +// Return Value: +// None +Method(SPL1,0,Serialized) +{ + Name(PPUU,0) // units + If (LEqual(CSEM, 1)) + { + Return() // we have already been called, must have CS exit before calling again + } + Store(1, CSEM) // record first call + + Store (PPL1, PLSV) // save PL1 value upon entering CS + Store (PL1E, PLEN) // save PL1 Enable bit upon entering CS + Store (CLP1, CLMP) // save PL1 Clamp bit upon entering CS + + If (LEqual(PWRU,0)) { // use PACKAGE_POWER_SKU_UNIT - Power Units[3:0] + Store(1,PPUU) + } Else { + ShiftLeft(Decrement(PWRU),2,PPUU) // get units + } + + Multiply(PLVL,PPUU,Local0) // convert SETUP value to power units in milli-watts + Divide(Local0,1000,,Local1) // convert SETUP value to power units in watts + Store(Local1, PPL1) // copy value to PL1 + Store(1, PL1E) // set Enable bit + Store(1, CLP1) // set Clamp bit +} +// +// RPL1 (Restore the PL1 register to the values prior to CS entry) +// +// Arguments: +// None +// +// Return Value: +// None +Method(RPL1,0,Serialized) +{ + Store (PLSV, PPL1) // restore value of PL1 upon exiting CS + Store(PLEN, PL1E) // restore the PL1 enable bit + Store(CLMP, CLP1) // restore the PL1 Clamp bit + Store(0, CSEM) // restore semaphore +} + +Name(DDPS, 0) // Current Display Power Status. 0= D0; non-zero = Dx state;. Initial value is zero. +Name(UAMS, 0) // User Absent Mode state, Zero - User Present; non-Zero - User not present +// GUAM - Global User Absent Mode +// Run when a change to User Absent mode is made, e.g. screen/display on/off events. +// Any device that needs notifications of these events includes its own UAMN Control Method. +// +// Arguments: +// Power State: +// 00h = On +// 01h = Standby +// 02h = Suspend +// 04h = Off +// 08h = Reduced On +// +// Return Value: +// None +// +Method(GUAM,1,Serialized) +{ + If(LNotEqual(Arg0, DDPS)){ // Display controller D-State changed? + Store(Arg0, DDPS) //Update DDPS to current state + Store(LAnd(Arg0, Not(PWRS)), UAMS) // UAMS: User Absent Mode state, Zero - User Present; non-Zero - User not present + + //Port 80 code for CS + If(Arg0){ + if(LEqual(ECNO,0x01)){ // Check EC notification enabled in Setup + ADBG("EC Notify") + if(LEqual(ECDB,0x01)){ + ADBG("EC Debug") + \_SB.PCI0.LPCB.H_EC.ECWT(1, RefOf(\_SB.PCI0.LPCB.H_EC.DLED)) //Set EC CS Debug Light (CAPS LOCK) + } + \_SB.PCI0.LPCB.H_EC.ECMD (0x2C) // Notify EC of CS entry + If(LEqual(ECLP, 0x1)) { + Store(Zero,\ECUP) + } + } + P8XH(0, 0xC5) + P8XH(1, 00) + ADBG("Enter CS") + If(PSCP){ + // if P-state Capping is enabled + If (LAnd(CondRefOf(\_PR.CPU0._PSS), CondRefOf(\_PR.CPU0._PPC))) + { + Subtract(SizeOf(\_PR.CPU0._PSS), One, \_PR.CPU0._PPC) + PNOT() + } + } + If(PLCS){ + SPL1() // set PL1 to low value upon CS entry + } + } Else { + if(LEqual(ECNO,0x01)){ // Check EC notification enabled in Setup + ADBG("EC Notify") + Store (Acquire(\EHLD, 0xFFFF), Local0) // Wait for Mutex for telling EC to exit Low Power Mode + if (LEqual(Local0, Zero)) { + \_SB.PCI0.LPCB.H_EC.ECMD (0x2D) // Notify EC of CS exit + If(LEqual(ECLP, 0x1)) { + Store(One,\ECUP) + } + Release(\EHLD) + } + ADBG("EC Debug") + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.DLED)) //Clear EC CS Debug Light (CAPS LOCK) + } + P8XH(0, 0xC5) + P8XH(1, 0xAB) + ADBG("Exit CS") + If(PSCP){ + // if P-state Capping s enabled + If (CondRefOf(\_PR.CPU0._PPC)) + { + Store(Zero, \_PR.CPU0._PPC) + PNOT() + } + } + If(PLCS){ + RPL1() // restore PL1 to pre-CS value upon exiting CS + } + } + + P_CS() // Powergating during CS + } +} + +// Power CS Powergated Devices: +// Method to enable/disable power during CS +Method(P_CS,0,Serialized) +{ + // NOTE: Do not turn ON Touch devices from here. Touch does not have PUAM + If(CondRefOf(\_SB.PCI0.PAUD.PUAM)){ // Notify Codec(HD-A/ADSP) + \_SB.PCI0.PAUD.PUAM() + } + // Adding back USB powergating (ONLY for Win8) until RTD3 walkup port setup implementation is complete */ + If(LEqual(OSYS,2012)){ // ONLY for Win8 OS + If(CondRefOf(\_SB.PCI0.XHC.DUAM)){ // Notify USB port- RVP + \_SB.PCI0.XHC.DUAM() + } + } + // TODO: Add calls to UAMN methods for + // * USB controller(s) + // * Embedded Controller + // * Sensor devices + // * Audio DSP? + // * Any other devices dependent on User Absent mode for power controls +} + +// SMI I/O Trap: +// Generate a Mutex protected SMI I/O Trap. +// +// Arguments: +// Arg0: I/O Trap type. +// 2 - For DTS +// 3 - For IGD +// 4 - For Pfat Tools +// Arg1: SMI I/O Trap Function to call. +// +// Return Value: +// SMI I/O Trap Return value. +// 0 = Success. Non-zero = Failure. + +Method(TRAP,2,Serialized) +{ + Store(Arg1,SMIF) // Store SMI Function. + + If(LEqual(Arg0,\TRTD)) // Is DTS IO Trap? + { + Store(Arg1,DTSF) // Store the function number global NVS + Store(0,TRPD) // Generate IO Trap. + Return(DTSF) // Return status from SMI handler + } + + If(LEqual(Arg0,\TRTI)) // Is IGD IO Trap? + { + Store(0,TRPH) // Generate IO Trap. + } + + If(LEqual(Arg0,\PFTI)) // Is PFAT TOOLS IO Trap? + { + Store(0,TRPF) // Generate IO Trap + } + + Return(SMIF) // Return SMIF. 0 = Success. +} + +// Note: Only add the indicator device needed by the platform. + +// +// System Bus +// +Scope(\_SB.PCI0) +{ + + Method(PTMA) + { + Return(PFMA) + } + + Method(PTMS) + { + Return(PFMS) + } + + Method(PTIA) + { + Return(PFIA) + } + + Method(_INI,0) + { + // Determine the OS and store the value, where: + // + // OSYS = 1000 = Linux. + // OSYS = 2000 = WIN2000. + // OSYS = 2001 = WINXP, RTM or SP1. + // OSYS = 2002 = WINXP SP2. + // OSYS = 2006 = Vista. + // OSYS = 2009 = Windows 7 and Windows Server 2008 R2. + // OSYS = 2012 = Windows 8 and Windows Server 2012. + // OSYS = 2013 = Windows Blue. + // + // Assume Windows 2000 at a minimum. + + Store(2000,OSYS) + + // Check for a specific OS which supports _OSI. + + If(CondRefOf(\_OSI,Local0)) + { + If(\_OSI("Linux")) + { + Store(1000,OSYS) + } + + If(\_OSI("Windows 2001")) + { + Store(2001,OSYS) + } + + If(\_OSI("Windows 2001 SP1")) + { + Store(2001,OSYS) + } + + If(\_OSI("Windows 2001 SP2")) + { + Store(2002,OSYS) + } + + If (\_OSI( "Windows 2001.1")) + { + Store (2003, OSYS) + } + + If(\_OSI("Windows 2006")) + { + Store(2006,OSYS) + } + + If(\_OSI("Windows 2009")) + { + Store(2009,OSYS) + } + + If(\_OSI("Windows 2012")) + { + Store(2012,OSYS) + } + + If(\_OSI("Windows 2013")) + { + Store(2013,OSYS) + } + } +#if 0 //AMI_OVERRIDE --- Below ASL code is for Thunderbolt, AMI thunderbolt module has taken care it already.>> + If(LOr(LEqual(BID, BICO),LEqual(BID, BICC))) { + Acquire(OSUM, 0xFFFF) + Store(MMRP(), Local1) + OperationRegion(RP_X,SystemMemory,Local1,0x20) + Field(RP_X,DWordAcc, NoLock, Preserve) + { + REG0, 32, + REG1, 32, + REG2, 32, + REG3, 32, + REG4, 32, + REG5, 32, + REG6, 32, + REG7, 32 + } + Store(REG6, Local2) + Store(0x00F0F000, REG6) + Store(\_GPE.MMTB(), Local3) + \_GPE.OSUP(Local3) + Store(Local2, REG6) + Release(OSUM) + Acquire(WFDM, 0xFFFF) + Store(1, WKFN) + + Release(WFDM) + } +#endif //AMI_OVERRIDE --- it is for Thunderbolt, AMI thunderbolt module has taken care it already. << + PINI() + } + + Method(NHPG,0,Serialized) + { +#if defined(ASL_RC_PORT_0) && (ASL_RC_PORT_0==1) + Store(0,^RP01.HPEX) // clear the hot plug SCI enable bit +#endif // ASL_RC_PORT_0 +#if defined(ASL_RC_PORT_1) && (ASL_RC_PORT_1==1) + Store(0,^RP02.HPEX) // clear the hot plug SCI enable bit +#endif // ASL_RC_PORT_1 +#if defined(ASL_RC_PORT_2) && (ASL_RC_PORT_2==1) + Store(0,^RP03.HPEX) // clear the hot plug SCI enable bit +#endif // ASL_RC_PORT_2 +#if defined(ASL_RC_PORT_3) && (ASL_RC_PORT_3==1) + Store(0,^RP04.HPEX) // clear the hot plug SCI enable bit +#endif // ASL_RC_PORT_3 +#if defined(ASL_RC_PORT_4) && (ASL_RC_PORT_4==1) + Store(0,^RP05.HPEX) // clear the hot plug SCI enable bit +#endif // ASL_RC_PORT_4 +#if defined(ASL_RC_PORT_5) && (ASL_RC_PORT_5==1) + Store(0,^RP06.HPEX) // clear the hot plug SCI enable bit +#endif // ASL_RC_PORT_5 +#if defined(ASL_RC_PORT_6) && (ASL_RC_PORT_6==1) + Store(0,^RP07.HPEX) // clear the hot plug SCI enable bit +#endif // ASL_RC_PORT_6 +#if defined(ASL_RC_PORT_7) && (ASL_RC_PORT_7==1) + Store(0,^RP08.HPEX) // clear the hot plug SCI enable bit +#endif // ASL_RC_PORT_7 +#if defined(ASL_RC_PORT_0) && (ASL_RC_PORT_0==1) + Store(1,^RP01.HPSX) // clear the hot plug SCI status bit +#endif // ASL_RC_PORT_0 +#if defined(ASL_RC_PORT_1) && (ASL_RC_PORT_1==1) + Store(1,^RP02.HPSX) // clear the hot plug SCI status bit +#endif // ASL_RC_PORT_1 +#if defined(ASL_RC_PORT_2) && (ASL_RC_PORT_2==1) + Store(1,^RP03.HPSX) // clear the hot plug SCI status bit +#endif // ASL_RC_PORT_2 +#if defined(ASL_RC_PORT_3) && (ASL_RC_PORT_3==1) + Store(1,^RP04.HPSX) // clear the hot plug SCI status bit +#endif // ASL_RC_PORT_3 +#if defined(ASL_RC_PORT_4) && (ASL_RC_PORT_4==1) + Store(1,^RP05.HPSX) // clear the hot plug SCI status bit +#endif // ASL_RC_PORT_4 +#if defined(ASL_RC_PORT_5) && (ASL_RC_PORT_5==1) + Store(1,^RP06.HPSX) // clear the hot plug SCI status bit +#endif // ASL_RC_PORT_5 +#if defined(ASL_RC_PORT_6) && (ASL_RC_PORT_6==1) + Store(1,^RP07.HPSX) // clear the hot plug SCI status bit +#endif // ASL_RC_PORT_6 +#if defined(ASL_RC_PORT_7) && (ASL_RC_PORT_7==1) + Store(1,^RP08.HPSX) // clear the hot plug SCI status bit +#endif // ASL_RC_PORT_7 + } + + Method(NPME,0,Serialized) + { +#if defined(ASL_RC_PORT_0) && (ASL_RC_PORT_0==1) + Store(0,^RP01.PMEX) // clear the PME SCI enable bit +#endif +#if defined(ASL_RC_PORT_1) && (ASL_RC_PORT_1==1) + Store(0,^RP02.PMEX) // clear the PME SCI enable bit +#endif +#if defined(ASL_RC_PORT_2) && (ASL_RC_PORT_2==1) + Store(0,^RP03.PMEX) // clear the PME SCI enable bit +#endif +#if defined(ASL_RC_PORT_3) && (ASL_RC_PORT_3==1) + Store(0,^RP04.PMEX) // clear the PME SCI enable bit +#endif +#if defined(ASL_RC_PORT_4) && (ASL_RC_PORT_4==1) + Store(0,^RP05.PMEX) // clear the PME SCI enable bit +#endif +#if defined(ASL_RC_PORT_5) && (ASL_RC_PORT_5==1) + Store(0,^RP06.PMEX) // clear the PME SCI enable bit +#endif +#if defined(ASL_RC_PORT_6) && (ASL_RC_PORT_6==1) + Store(0,^RP07.PMEX) // clear the PME SCI enable bit +#endif +#if defined(ASL_RC_PORT_7) && (ASL_RC_PORT_7==1) + Store(0,^RP08.PMEX) // clear the PME SCI enable bit +#endif +#if defined(ASL_RC_PORT_0) && (ASL_RC_PORT_0==1) + Store(1,^RP01.PMSX) // clear the PME SCI status bit +#endif +#if defined(ASL_RC_PORT_1) && (ASL_RC_PORT_1==1) + Store(1,^RP02.PMSX) // clear the PME SCI status bit +#endif +#if defined(ASL_RC_PORT_2) && (ASL_RC_PORT_2==1) + Store(1,^RP03.PMSX) // clear the PME SCI status bit +#endif +#if defined(ASL_RC_PORT_3) && (ASL_RC_PORT_3==1) + Store(1,^RP04.PMSX) // clear the PME SCI status bit +#endif +#if defined(ASL_RC_PORT_4) && (ASL_RC_PORT_4==1) + Store(1,^RP05.PMSX) // clear the PME SCI status bit +#endif +#if defined(ASL_RC_PORT_5) && (ASL_RC_PORT_5==1) + Store(1,^RP06.PMSX) // clear the PME SCI enable bit +#endif +#if defined(ASL_RC_PORT_6) && (ASL_RC_PORT_6==1) + Store(1,^RP07.PMSX) // clear the PME SCI status bit +#endif +#if defined(ASL_RC_PORT_7) && (ASL_RC_PORT_7==1) + Store(1,^RP08.PMSX) // clear the PME SCI status bit +#endif + } +} + +Scope (\) +{ + // + // Global Name, returns current Interrupt controller mode; + // updated from _PIC control method + // + Name(PICM, 0) + + // + // Procedure: GPRW + // + // Description: Generic Wake up Control Method ("Big brother") + // to detect the Max Sleep State available in ASL Name scope + // and Return the Package compatible with _PRW format. + // Input: Arg0 = bit offset within GPE register space device event will be triggered to. + // Arg1 = Max Sleep state, device can resume the System from. + // If Arg1 = 0, Update Arg1 with Max _Sx state enabled in the System. + // Output: _PRW package + // + Name(PRWP, Package(){Zero, Zero}) // _PRW Package + + Method(GPRW, 2) + { + Store(Arg0, Index(PRWP, 0)) // copy GPE# + // + // SS1-SS4 - enabled in BIOS Setup Sleep states + // + Store(ShiftLeft(SS1,1),Local0) // S1 ? + Or(Local0,ShiftLeft(SS2,2),Local0) // S2 ? + Or(Local0,ShiftLeft(SS3,3),Local0) // S3 ? + Or(Local0,ShiftLeft(SS4,4),Local0) // S4 ? + // + // Local0 has a bit mask of enabled Sx(1 based) + // bit mask of enabled in BIOS Setup Sleep states(1 based) + // + If(And(ShiftLeft(1, Arg1), Local0)) + { + // + // Requested wake up value (Arg1) is present in Sx list of available Sleep states + // + Store(Arg1, Index(PRWP, 1)) // copy Sx# + } + Else + { + // + // Not available -> match Wake up value to the higher Sx state + // + ShiftRight(Local0, 1, Local0) + // If(LOr(LEqual(OSFL, 1), LEqual(OSFL, 2))) { // ??? Win9x + // FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Max Sx + // } Else { // ??? Win2k / XP + FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 == Min Sx + // } + } + + Return(PRWP) + } +} + + +Scope (\_SB) +{ + Name(OSCI, 0) // \_SB._OSC DWORD2 input + Name(OSCO, 0) // \_SB._OSC DWORD2 output + // _OSC (Operating System Capabilities) + // _OSC under \_SB scope is used to convey platform wide OSPM capabilities. + // ACPI 5.0 specification enables OSPM to query for Platform CPPC support + // through _OSC evaluation. Upon _OSC evaluation, platform can indicate + // support/non-support for CPPC through the return buffer. For a complete + // description of _OSC ACPI Control Method, refer to ACPI 5.0 + // specification, section 6.2.10. + // Arguments: (4) + // Arg0 - A Buffer containing the UUID "0811B06E-4A27-44F9-8D60-3CBBC22E7B48" + // Arg1 - An Integer containing the Revision ID of the buffer format + // Arg2 - An Integer containing a count of entries in Arg3 + // Arg3 - A Buffer containing a list of DWORD capabilities + // Return Value: + // A Buffer containing the list of capabilities + // + Method(_OSC,4,Serialized) + { + +//ami override + If(LNotEqual(OSCM(Arg0,Arg1,Arg2,Arg3),0)) + { + Return(Arg3) + } +//ami override + + // + // Point to Status DWORD in the Arg3 buffer (STATUS) + // + CreateDWordField(Arg3, 0, STS0) + // + // Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES) + // + CreateDwordField(Arg3, 4, CAP0) + + // + // Check UUID + // + If(LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48"))) + { + // + // Check Revision + // + If(LEqual(Arg1,One)) + { + If(And(CAP0,0x04)) // Check _PR3 Support(BIT2) + { + Store(0x04, OSCO) + If(LNotEqual(And(SGMD,0x0F),2)) // Check Switchable/Hybrid graphics is not enabled in bios setup [SgModeMuxless]? + { + If(LEqual(RTD3,0)) // Is RTD3 support disabled in Bios Setup? + { + // RTD3 is disabled via BIOS Setup. + And(CAP0, 0x3B, CAP0) // Clear _PR3 capability + Or(STS0, 0x10, STS0) // Indicate capability bit is cleared + } + } + } + + // Process command. Regardless of query or control, we do the same thing. + If(And(CAP0,0x20)) // Check CPC Support + { + If(CondRefOf(\_SB.PCCD.PENB)){ + If(LEqual(\_SB.PCCD.PENB, 0)){ + // PENB = 0 => CPPC is disabled via BIOS Setup. + And(CAP0, 0x1F, CAP0) // Clear _CPC capability + Or(STS0, 0x10, STS0) // Indicate capability bit is cleared + } + } Else { + // PENB object not found in namespace => CPPC is disabled via BIOS Setup. + And(CAP0, 0x1F, CAP0) // Clear _CPC capability + Or(STS0, 0x10, STS0) // Indicate capability bit is cleared + } + } + } Else{ + And(STS0,0xFFFFFF00,STS0) + Or(STS0,0xA, STS0) // Unrecognised Revision and report OSC failure + } + } Else { + And(STS0,0xFFFFFF00,STS0) + Or (STS0,0x6, STS0) // Unrecognised UUID and report OSC failure + } + + Return(Arg3) + } // End _OSC + + Device (PEPD) + { + Name (_HID, "INT33A1") + Name (_CID, EISAID ("PNP0D80")) + Name (_UID, 0x1) + + Name(PEPP, Zero) + Name (DEVS, Package() + { + 2, + Package() {"\\_SB.PCI0.GFX0"}, + Package() {"\\_SB.PCI0.SAT0.PRT1"} + }) + + Name (DEVX, Package() + { + Package() {"\\_SB.PCI0.GFX0",0xffffffff}, + Package() {"\\_SB.PCI0.SAT0.PRT1",0xffffffff}, + Package() {"\\_SB.PCI0.UA01", 0xffffffff}, + Package() {"\\_SB.PCI0.SDHC", 0xffffffff }, + Package() {"\\_SB.PCI0.I2C0", 0xffffffff }, + Package() {"\\_SB.PCI0.I2C1", 0xffffffff }, + Package() {"\\_SB.PCI0.XHC", 0xffffffff }, + Package() {"HDAUDIO\\FUNC_01&VEN_10EC&DEV_0282&SUBSYS_00000000&REV_1000\\4&a02b74b&0&0001", 0xffffffff }, + }) + + Name(DEVY, Package() // uPEP Device List + { + // + // 1: ACPI Device Descriptor: Fully Qualified namestring + // 2: Enabled/Disabled Field + // 0 = This device is disabled and applies no constraints + // >0 = This device is enabled and applies constraints + // 3: Constraint Package: entry per LPI state in LPIT + // a. Associated LPI State UID + // ID == 0xFF: same constraints apply to all states in LPIT + // b: minimum Dx state as pre-condition + // c: (optional) OEM specific OEM may provide an additional encoding + // which further defines the D-state Constraint + // 0x0-0x7F - Reserved + // 0x80-0xFF - OEM defined + // + Package() {"\\_PR.CPU0", 0x1, Package() {0, Package(){0xFF, 0}}}, + Package() {"\\_PR.CPU1", 0x1, Package() {0, Package(){0xFF, 0}}}, + Package() {"\\_PR.CPU2", 0x1, Package() {0, Package(){0xFF, 0}}}, + Package() {"\\_PR.CPU3", 0x1, Package() {0, Package(){0xFF, 0}}}, + Package() {"\\_SB.PCI0.GFX0", 0x1, Package() {0, Package(){0xFF, 3}}}, + Package() {"\\_SB.PCI0.SAT0", 0x1, Package() {0, Package(){0xFF, 3}}}, + Package() {"\\_SB.PCI0.SAT0.PRT0", 0x1, Package() {0, Package(){0xFF, 0, 0x81}}}, + Package() {"\\_SB.PCI0.SAT0.PRT1", 0x1, Package() {0, Package(){0xFF, 0, 0x81}}}, + Package() {"\\_SB.PCI0.SAT0.PRT2", 0x1, Package() {0, Package(){0xFF, 0, 0x81}}}, + Package() {"\\_SB.PCI0.SAT0.PRT3", 0x1, Package() {0, Package(){0xFF, 0, 0x81}}}, + Package() {"\\_SB.PCI0.UA00", 0x1, Package() {0, Package(){0xFF, 3}}}, + Package() {"\\_SB.PCI0.UA01", 0x1, Package() {0, Package(){0xFF, 3}}}, + Package() {"\\_SB.PCI0.SDHC", 0x1, Package() {0, Package(){0xFF, 3}}}, + Package() {"\\_SB.PCI0.I2C0", 0x1, Package() {0, Package(){0xFF, 3}}}, + Package() {"\\_SB.PCI0.I2C1", 0x1, Package() {0, Package(){0xFF, 3}}}, + Package() {"\\_SB.PCI0.XHC", 0x1, Package() {0, Package(){0xFF, 3}}}, + Package() {"HDAUDIO\\FUNC_01&VEN_10EC&DEV_0282*", 0x1, Package() {0, Package(){0x0, 0}, Package(){0x1, 3}}}, + Package() {"\\_SB.PCI0.ADSP", 0x1, Package() {0, Package(){0x0, 0}, Package(){0x1, 3}}}, + }) + + Name(BCCD, Package() // Bugcheck Critical Device(s) + { + // + // 1: ACPI Device Descriptor: Fully Qualified name string + // 2: Package of packages: 1 or more specific commands to power up critical device + // 2a: Package: GAS-structure describing location of PEP accessible power control + // Refer to ACPI 5.0 spec section 5.2.3.1 for details + // a: Address Space ID (0 = System Memory) + // NOTE: A GAS Address Space of 0x7F (FFH) indicates remaining package + // elements are Intel defined + // b: Register bit width (32 = DWORD) + // c: Register bit offset + // d: Access size (3 = DWORD Access) + // e: Address (for System Memory = 64-bit physical address) + // 2b: Package containing: + // a: AND mask - not applicable for all Trigger Types + // b: Value (bits required to power up the critical device) + // c: Trigger Type: + // 0 = Read + // 1 = Write + // 2 = Write followed by Read + // 3 = Read Modify Write + // 4 = Read Modify Write followed by Read + // 2c: Power up delay: Time delay before next operation in uSec + // + Package() {"\\_SB.PCI0.SAT0", Package() { + Package() {Package() {1, 8, 0, 1, 0xB2}, // GAS Structure 8-bit IO Port + Package() {0x0, 0xCD, 0x1}, // Write 0xCD + 16000} // Power up delay = 16ms + } + }, + Package() {"\\_SB.PCI0.SAT0.PRT0", Package(){ + Package() {Package() {1, 8, 0, 1, 0xB2}, // GAS Structure 8-bit IO Port + Package() {0x0, 0xCD, 0x1}, // Write 0xCD + 16000} // Power up delay = 16ms + } + }, + Package() {"\\_SB.PCI0.SAT0.PRT1", Package(){ + Package() {Package() {1, 8, 0, 1, 0xB2}, // GAS Structure 8-bit IO Port + Package() {0x0, 0xCD, 0x1}, // Write 0xCD + 16000} // Power up delay = 16ms + } + }, + Package() {"\\_SB.PCI0.SAT0.PRT2", Package(){ + Package() {Package() {1, 8, 0, 1, 0xB2}, // GAS Structure 8-bit IO Port + Package() {0x0, 0xCD, 0x1}, // Write 0xCD + 16000} // Power up delay = 16ms + } + }, + Package() {"\\_SB.PCI0.SAT0.PRT3", Package(){ + Package() {Package() {1, 8, 0, 1, 0xB2}, // GAS Structure 8-bit IO Port + Package() {0x0, 0xCD, 0x1}, // Write 0xCD + 16000} // Power up delay = 16ms + } + }, + }) + + Method(_STA, 0x0, NotSerialized) + { + If(LGreaterEqual(OSYS,2012)) + { + If(LEqual(And(CDID,0xF000), 0x9000)) // LPT-H Chipset DID start with 0x8xxx while LPT-LP start with 0x9xxx + { + If(LEqual(S0ID, 1)) + { + Return(0xf) + } + } + } + Return(0) + } + + Method(_DSM, 0x4, Serialized) + { + If(LEqual(Arg0,ToUUID("B8FEBFE0-BAF8-454b-AECD-49FB91137B21"))) //PEP driver should use same UUID + { + If(LEqual(Arg2, Zero)) + { + Return(Buffer(One) + { + 0x07 + }) + } + If(LEqual(Arg2, One)) + { + Store(0x1, PEPP) + Return(0xf) + } + If(LEqual(Arg2, 2)) + { + If(LEqual(Arg1, Zero)) { // Revision ID is Zero + // TBD Needs to find a better logic here.... + Switch(PEPY){ + Case(1){ // Grpahics alone enabled + Return(Package(){1,Package() {"\\_SB.PCI0.GFX0"}}) + } + Case(2){ // SATA alone enabled + Return(Package(){1,Package() {"\\_SB.PCI0.SAT0.PRT1"}}) + } + Case(3){ // Both SATA and Gfx enabled + Return(DEVS) + } + Default{ // All devices are disabled + Return(Package(){0}) + } + } // End of Switch(PEPY) + } + + If(LEqual(Arg1, One)) { // Revision ID is One + If(LNot(And(PEPY,0x01))){ // Check if PEP GFx disabled in Setup + Store (0x00, Index (DeRefOf(Index (DEVX, 0)), 1)) // Disable Gfx + } + If(LNot(And(PEPY,0x02))){ // Check if PEP Sata disabled in Setup + Store (0x00, Index (DeRefOf(Index (DEVX, 1)), 1)) // Disable Sata + } + If(LNot(And(PEPY,0x04))){ // Check if PEP UART disabled in Setup + Store (0x00, Index (DeRefOf(Index (DEVX, 2)), 1)) // Disable UART + } + If(LNot(And(PEPY,0x08))){ // Check if PEP SDHC disabled in Setup + Store (0x00, Index (DeRefOf(Index (DEVX, 3)), 1)) // Disable SDHC + } + If(LNot(And(PEPY,0x10))){ // Check if PEP I2C0 disabled in Setup + Store (0x00, Index (DeRefOf(Index (DEVX, 4)), 1)) // Disable I2C0 + } + If(LNot(And(PEPY,0x20))){ // Check if PEP I2C1 disabled in Setup + Store (0x00, Index (DeRefOf(Index (DEVX, 5)), 1)) // Disable I2C1 + } + If(LNot(And(PEPY,0x40))){ // Check if PEP XHCI disabled in Setup + Store (0x00, Index (DeRefOf(Index (DEVX, 6)), 1)) // Disable XHCI + } + If(LNot(And(PEPY,0x80))){ // Check if PEP audio disabled in Setup + Store (0x00, Index (DeRefOf(Index (DEVX, 7)), 1)) // Disable Audio + } + Return(DEVX) + } + } //If(LEqual(Arg2, 2)) + }// If(LEqual(Arg0,ToUUID("B8FEBFE0-BAF8-454b-AECD-49FB91137B21"))) + + If(LEqual(Arg0,ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"))) + { + // Number of Functions (including this one) + If(LEqual(Arg2, Zero)) + { + Return(Buffer(One){0x07}) + } + // Device Constraints Enumeration + If(LEqual(Arg2, One)) + { + // Update uPEP device list based on PEPC (Low Power S0 Constraint) + // Bit[1:0] - SATA (0:None, 1:SATA Ports[all], 2:SATA Controller) + // [2] - En/Dis UART 0 + // [3] - UART 1 + // [4] - SDIO + // [5] - I2C 0 + // [6] - I2C 1 + // [7] - XHCI + // [8] - Azalia + // [9] - ADSP + + If(LNotEqual(And(PEPC, 0x0003), 1)) // PEPC Bit[1:0] - SATA (0:None, 1:SATA Ports[all], 2:SATA Controller) + { + // No Constraint for SATA Ports (SAT0.PRT0, PRT1, PRT2, PRT3) + Store (0x00, Index (DeRefOf(Index (DEVY, 6)), 1)) // SAT0.PRT0 + Store (0x00, Index (DeRefOf(Index (DEVY, 7)), 1)) // SAT0.PRT1 + Store (0x00, Index (DeRefOf(Index (DEVY, 8)), 1)) // SAT0.PRT2 + Store (0x00, Index (DeRefOf(Index (DEVY, 9)), 1)) // SAT0.PRT3 + } + + If(LNotEqual(And(PEPC, 0x0003), 2)) // PEPC Bit[1:0] - SATA (0:None, 1:SATA Ports[all], 2:SATA Controller) + { + // No Constraint for SATA Controller (SAT0) + Store (0x00, Index (DeRefOf(Index (DEVY, 5)), 1)) // SAT0 + + // Disable SATA Ports if no drive is connected + If(LNot(And(SPST,1))) + { + // Disable SATA Ports 0 + Store (0x00, Index (DeRefOf(Index (DEVY, 6)), 1)) // SAT0.PRT0 + } + If(LNot(And(SPST, 2))) + { + // Disable SATA Ports 1 + Store (0x00, Index (DeRefOf(Index (DEVY, 7)), 1)) // SAT0.PRT1 + } + If(LNot(And(SPST, 4))) + { + // Disable SATA Ports 2 + Store (0x00, Index (DeRefOf(Index (DEVY, 8)), 1)) // SAT0.PRT2 + } + If(LNot(And(SPST, 8))) + { + // Disable SATA Ports 3 + Store (0x00, Index (DeRefOf(Index (DEVY, 9)), 1)) // SAT0.PRT3 + } + } + + If(LEqual(And(PEPC,0x0004),0)) // PEPC Bit[2] - En/Dis UART 0 + { + // Disabled UA00 + Store (0x00, Index (DeRefOf(Index (DEVY, 10)), 1)) // UA00 + } + + If(LEqual(And(PEPC,0x0008),0)) // PEPC Bit[3] - En/Dis UART 1 + { + // Disabled UA01 + Store (0x00, Index (DeRefOf(Index (DEVY, 11)), 1)) // UA01 + } + + If(LEqual(And(PEPC,0x0010),0)) // PEPC Bit[4] - En/Dis SDIO + { + // Disabled SDHC + Store (0x00, Index (DeRefOf(Index (DEVY, 12)), 1)) // SDHC + } + + If(LEqual(And(PEPC,0x0020),0)) // PEPC Bit[5] - En/Dis I2C 0 + { + // Disabled I2C0 + Store (0x00, Index (DeRefOf(Index (DEVY, 13)), 1)) // I2C0 + } + + If(LEqual(And(PEPC,0x0040),0)) // PEPC Bit[6] - En/Dis I2C 1 + { + // Disabled I2C1 + Store (0x00, Index (DeRefOf(Index (DEVY, 14)), 1)) // I2C1 + } + + If(LEqual(And(PEPC,0x0080),0)) // PEPC Bit[7] - En/Dis XHCI + { + // Disabled XHCI + Store (0x00, Index (DeRefOf(Index (DEVY, 15)), 1)) // XHC + } + + If(LEqual(And(PEPC,0x0100),0)) // PEPC Bit[9] - En/Dis Azalia + { + // Disabled Azalia + Store (0x00, Index (DeRefOf(Index (DEVY, 16)), 1)) // Azalia + } + + If(LEqual(And(PEPC,0x0200),0)) // PEPC Bit[10] - En/Dis ADSP + { + // Disabled ADSP + Store (0x00, Index (DeRefOf(Index (DEVY, 17)), 1)) // ADSP + } + + Return(DEVY) + } + // BCCD + If(LEqual(Arg2, 2)) + { + Return(BCCD) + } + }// If(LEqual(Arg0,ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"))) + Return(One) + } // Method(_DSM) + } //device (PEPD) + +} // End Scope(\_SB) + +Scope (\_SB) +{ + // + // define a BT RF-Kill device. + // + Device (BTKL) + { + Name(_HID, "INT3420") + + Method (_STA, 0x0, NotSerialized) + { + If (\_OSI ("Windows 2012")) { // WIN8? + If (LEqual(BID, BW2C)) { // WTM2? + Return(0x0F) + } + } + Return(0x00) // not support BT RF-Kill, device hide. + } + + // D0 Method for BTKL + Method(_PS0,0,Serialized) + { + // de-assert GPIO87 + And(\GL0A, 0x7F, \GL0A) + } + + // D3 Method for BTKL + Method(_PS3,0,Serialized) + { + // assert GPIO87 + Or(\GL0A, 0x80, \GL0A) + } + + // detect GPIO pin status + Method(PSTS) + { + Return(RDGP(87)) + } + } +} // End Scope(\_SB) diff --git a/ReferenceCode/AcpiTables/Dsdt/SMSC1000_COM.asl b/ReferenceCode/AcpiTables/Dsdt/SMSC1000_COM.asl new file mode 100644 index 0000000..0de4c73 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/SMSC1000_COM.asl @@ -0,0 +1,574 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Device(UAR6) // SMSC1000 UART 1. +{ + // Identify UART 2 as a COM Port. + + Name(_HID, EISAID("PNP0501")) + + Name(_UID,5) + + // Status Method for UART 1. + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if the SIO Device is + // not set to Disabled in BIOS Setup. + + If(SMC1) + { + // Display UART 1 and return status. + + Store(0,CR55) + Store(CR02,Local0) + Store(0,CRAA) + + If(And(Local0,0x08)) + { + Return(0x000F) + } + + Return(0x000D) + } + + Return(0x0000) + } + + // Disable Method for UART 1. + + Method(_DIS,0,Serialized) + { + Store(0,CR55) + Store(And(CR02,0xF0),CR02) + Store(0,CRAA) + } + + // Current Resource Setting Method for UART 1. + Method(_CRS,0,Serialized) + { + // Create the Buffer that stores the Resources to + // be returned. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x03F8,0x03F8,0x01,0x08) + IRQNoFlags(){4} + }) + + // Skip this sequence if SIO device is not connected + + If(SMC1) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Write the base address into the Buffer. + + Store(0,CR55) + + ShiftLeft(CR24,2,IOL0) // Low Byte. + ShiftLeft(CR24,2,IOL1) + + ShiftRight(CR24,6,IOH0) // High Byte. + ShiftRight(CR24,6,IOH1) + + // Write the length into the Buffer. + + Store(8,LEN0) + + // Write the IRQ value into the Buffer. + + ShiftLeft(One,ShiftRight(And(CR28,0xF0),4),IRQW) + + Store(0,CRAA) + } + + Return(BUF0) + } + + // Possible Resource Setting Method for UART 1. + Name(_PRS,ResourceTemplate() + { + + StartDependentFn(0,2) + { + IO(Decode16,0x2E8,0x2E8,0x01,0x08) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3E8,0x3E8,0x01,0x08) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2E8,0x2E8,0x01,0x08) + IRQNoFlags(){4} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){4} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3E8,0x3E8,0x01,0x08) + IRQNoFlags(){4} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){4} + } + EndDependentFn() + }) + + + // Set Resource Setting Method for UART 1. + Method(_SRS,1,Serialized) + { + // Point to the specific information in the passed + // in Buffer. + + CreateByteField(Arg0,0x02,IOLO) + CreateByteField(Arg0,0x03,IOHI) + CreateWordField(Arg0,0x09,IRQW) + + // Disable the device. + + Store(0,CR55) + Store(And(CR02,0xF0),CR02) + + // Set the Base IO Address. + + Store(ShiftRight(IOLO,2),CR24) + Or(CR24,ShiftLeft(IOHI,6),CR24) + + // Set the IRQ. + + And(CR28,0x0F,CR28) + Or(CR28,ShiftLeft(Subtract(FindSetRightBit(IRQW),1),4),CR28) + + // Set the Decode Range so UART 1 works with ICH7 and + // future platforms. + + AND(IOD0,0xF8,IOD0) // Clear all bits. + + If(LEqual(IOHI,0x03)) // Address = 0x3xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x07,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x01,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x05,IOD0) + } + } + + // Enable the device. + + Store(Or(CR02,0x08),CR02) + Store(0,CRAA) + } + + // D0 Method for UART 1. + + Method(_PS0,0,Serialized) + { + Store(0,CR55) + Store(Or(CR02,0x08),CR02) + Store(0,CRAA) + } + + // D3 Method for UART 1. + + Method(_PS3,0,Serialized) + { + Store(0,CR55) + Store(And(CR02,0xF0),CR02) + Store(0,CRAA) + } +} + +Device(UAR7) // SMSC1000 UART 2. +{ + // Identify UART 2 as an IR Device. + + Name(_HID, EISAID("PNP0510")) + + Name(_UID,1) + + // Status Method for UART 2. + Method(_STA,0,Serialized) + { + // + //Check SIO Device is Present or not. + // + If (SMC1) + { + Store(0,CR55) + Store(CR02,Local0) + Store(0,CRAA) + If (And(Local0,0x80)) + { + Return (0x000F) + } + Return (0x000D) // Not present + } + Return (0x0000) + } + + // Disable Method for UART 2. + Method(_DIS,0,Serialized) + { + Store(0,CR55) + Store(And(CR02,0x0F),CR02) + // + // Disable IR on Logical Device Activate Register + // + Store(And(CR3A,0xFA),CR02) + Store(0,CRAA) + } + + + // + // Current Resource Setting Method for UART 2. + // + Method(_CRS,0,Serialized) + { + // Create the FIR Buffer that stores the Resources to + // be returned. + Name(BUF0,ResourceTemplate() + { + IO(Decode16, 0x0000, 0x0000, 0x01, 0x08) + IO(Decode16, 0x0000, 0x0000, 0x01, 0x08) + IRQNoFlags() {6} + DMA(Compatibility, NotBusMaster, Transfer8, ) {2} + }) + + If(SMC1) + { + // Create pointers to the specific byte. + // + CreateByteField(BUF0,0x02,IO10) + CreateByteField(BUF0,0x03,IO11) + CreateByteField(BUF0,0x04,IO12) + CreateByteField(BUF0,0x05,IO13) + CreateByteField(BUF0,0x0a,IO20) + CreateByteField(BUF0,0x0b,IO21) + CreateByteField(BUF0,0x0c,IO22) + CreateByteField(BUF0,0x0d,IO23) + CreateWordField(BUF0,0x11,IRQW) + CreateByteField(BUF0,0x14,DMA0) + + Store(0,CR55) + + // + // Write the Base Address into the Buffer. + // + ShiftLeft(CR25,2,IO10) // Low Byte. + ShiftRight(And(CR25,0xC0), 6, IO11) + Store(IO10, IO12) + Store(IO11, IO13) + + ShiftLeft(CR2B,3,IO20) // Low Byte. + ShiftRight(And(CR2B,0xE0), 5, IO21) + Store(IO20, IO22) + Store(IO21, IO23) + + // + // Write the IRQ value into the Buffer. + // + Store(0x0,Local1) + And(CR28,0x0F,Local1) + ShiftLeft(1, Local1, IRQW) + + // Write DMA value into buffer + Store(0x0,Local1) + And(CR2C,0x0F,Local1) + + If(LEqual(Local1, 0x0F)){ + Store(0, DMA0) //No DMA + } + Else{ + ShiftLeft(1, Local1, DMA0) + } + Store(0,CRAA) + } + Return(BUF0) + } + + // + // Possible Resource Setting Method for UART 2. + // + + Name(_PRS, ResourceTemplate() { + StartDependentFn(0, 0) { + IO(Decode16,0x2f8,0x2f8,0x01,0x08) + IO(Decode16,0x7E0,0x7E0,0x01,0x08) + IRQNoFlags(){6} + DMA(Compatibility, NotBusMaster, Transfer8_16) {1} + } + StartDependentFnNoPri() { + IO(Decode16, 0x3F8, 0x3F8, 1, 8) + IO(Decode16,0x7E0,0x7E0,0x01,0x08) + IRQNoFlags() {3,4,5,6,7,10,11,12} + DMA(Compatibility, NotBusMaster, Transfer8_16) {1,2,3} + } + StartDependentFnNoPri() { + IO(Decode16, 0x2F8, 0x3F8, 1, 8) + IO(Decode16,0x7E0,0x7E0,0x01,0x08) + IRQNoFlags() {3,4,5,6,7,10,11,12} + DMA(Compatibility, NotBusMaster, Transfer8_16) {1,2,3} + } + StartDependentFnNoPri() { + IO(Decode16, 0x3E8, 0x3E8, 1, 8) + IO(Decode16,0x7E0,0x7E0,0x01,0x08) + IRQNoFlags() {3,4,5,6,7,10,11,12} + DMA(Compatibility, NotBusMaster, Transfer8_16) {1,2,3} + } + StartDependentFnNoPri() { + IO(Decode16, 0x2E8, 0x3E8, 1, 8) + IO(Decode16,0x7E0,0x7E0,0x01,0x08) + IRQNoFlags() {3,4,5,6,7,10,11,12} + DMA(Compatibility, NotBusMaster, Transfer8_16) {1,2,3} + } + EndDependentFn() + }) + + + // Set Resource Setting Method for UART 2. + // Set Resource Setting Method for UART 2. + Method(_SRS,1,Serialized) + { + Store(0,CR55) + Store(CR2B, Local0) + Store(0,CRAA) + If(Local0) + { + // Point to the specific information in the passed + // in Buffer. + CreateByteField(Arg0,0x02,IO10) + CreateByteField(Arg0,0x03,IO11) + CreateByteField(Arg0,0x0a,IO20) + CreateByteField(Arg0,0x0b,IO21) + CreateWordField(Arg0,0x11,IRQW) + CreateByteField(Arg0,0x14,DMA0) + + Store(0,CR55) + + // + // Disable the device. + // + And(CR02,0x0F,CR02) + + // + // Set the Base IO Address. + // + Store(ShiftRight(IO10,2),CR25) + Or(CR25,ShiftLeft(IO11,6),CR25) + If(IO20){ + Store(ShiftRight(IO20,3),CR2B) + Or(CR2B,ShiftLeft(IO21,5),CR2B) + } + + // + // Set the IRQ. + // + And(CR28,0xF0,CR28) + Or(CR28,Subtract(FindSetRightBit(IRQW),1),CR28) + + // Set DMA + And(CR2C,0xF0,CR2C) + If(DMA0) + { + Or(CR2C,Subtract(FindSetRightBit(DMA0),1),CR2C) + } + Else + { + Or(CR2C,0x0F,CR2C) // No DMA + } + + // + // Set the Decode Range so UART 2 works with ICH7 and + // future platforms. + // + AND(IOD0,0x8F,IOD0) // Clear all bits. + If(LEqual(IO11,0x03)) // Address = 0x3xx + { + If(LEqual(IO10,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x070,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IO10,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x010,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x050,IOD0) + } + } + + // + // Enable the device. + // + Or(CR02,0x80,CR02) + + Store(0,CRAA) + + } + Else + { + // Point to the specific information in the passed + // in Buffer. + CreateByteField(Arg0,0x02,IOLO) + CreateByteField(Arg0,0x03,IOHI) + CreateWordField(Arg0,0x09,IRQR) + + Store(0,CR55) + + // + // Disable the device. + // + And(CR02,0x0F,CR02) + + // + // Set the Base IO Address. + // + Store(ShiftRight(IOLO,2),CR25) + Or(CR25,ShiftLeft(IOHI,6),CR25) + + // + // Set the IRQ. + // + And(CR28,0xF0,CR28) + Or(CR28,Subtract(FindSetRightBit(IRQR),1),CR28) + + // + // Set the Decode Range so UART 2 works with ICH7 and + // future platforms. + // + AND(IOD0,0x8F,IOD0) // Clear all bits. + + If(LEqual(IOHI,0x03)) // Address = 0x3xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x070,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x010,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x050,IOD0) + } + } + + // + // Enable the device. + // + Or(CR02,0x80,CR02) + + Store(0,CRAA) + } + } + + // + // D0 Method for UART 2. + // + Method(_PS0,0,Serialized) + { + Store(0,CR55) + Store(Or(CR02,0x80),CR02) + Store(0,CRAA) + + } + + // + // D3 Method for UART 2. + // + Method(_PS3,0,Serialized) + { + Store(0,CR55) + Store(And(CR02,0x0F),CR02) + Store(0,CRAA) + + } +} diff --git a/ReferenceCode/AcpiTables/Dsdt/SMSC1000_LPT.asl b/ReferenceCode/AcpiTables/Dsdt/SMSC1000_LPT.asl new file mode 100644 index 0000000..235a714 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/SMSC1000_LPT.asl @@ -0,0 +1,226 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Device(LPT1) // Printer, Output Mode +{ + Name(_HID,EISAID("PNP0400")) + Name(_UID,5) + + // Status Method for LPT-Output Mode. + + Method(_STA,0,Serialized) + { + If(SMC1) + { + // Check if SIO Device is Present & Display LPT1 and return status. + + Store(0,CR55) + Store(CR01,Local0) + Store(0,CRAA) + + If(And(Local0,0x0C)) + { + Return(0x000F) + } + + Return(0x000D) + } + + Return(0x0000) + } + + + // Disable Method for LPT-Output Mode. + + Method(_DIS,0,Serialized) + { + // Set SIO to LPT. + Store(0,CR55) + Store(And(CR01,0x0FB),CR01) + Store(0,CRAA) + } + + // Current Resource Setting Method for LPT-Output Mode. + + Method(_CRS,0,Serialized) + { + // Create a buffer to return to OS. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x0378,0x0378,0x01,0x04) + IRQNoFlags(){5} + }) + + If(SMC1) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + Store(0,CR55) + + ShiftLeft(CR23,2,IOL0) // Low Byte. + ShiftLeft(CR23,2,IOL1) + + ShiftRight(CR23,6,IOH0) // High Byte. + ShiftRight(CR23,6,IOH1) + + // Write the length into the Buffer. + + Store(4,LEN0) + + // Write the IRQ value into the Buffer. + + Store(0x0,Local1) + And(CR27,0x0F,Local1) + ShiftLeft(1, Local1, IRQW) + Store(0,CRAA) + } + + Return(BUF0) + } + + // Possible Resource Setting Method for LPT-Output Mode. + // Build a Buffer with all valid LPT Port Resources. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3BC,0x3BC,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3BC,0x3BC,0x01,0x04) + IRQNoFlags(){7} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for LPT-Output Mode. + Method(_SRS,1,Serialized) + { + // Point to the specific information in the passed + // in Buffer. + + CreateByteField(Arg0,0x02,IOL0) + CreateByteField(Arg0,0x03,IOH0) + CreateWordField(Arg0,0x09,IRQW) + + // Disable the device. + Store(0,CR55) + Store(And(CR01,0x0FB),CR01) + + // Set the Base IO Address. + Store(ShiftRight(IOL0,2),CR23) + Or(CR23,ShiftLeft(IOH0,6),CR23) + + // Set the IRQ. + FindSetRightBit(IRQW,Local0) + If (LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,CR27) + + // Set the Decode Range so POUT works when docked. + And(IOD1,0xFC,IOD1) // Decode all bits. + + If(LEqual(IOH0,0x03)) // Address = 0x3xx + { + If(LEqual(IOL0,0x78)) // Address = 0x378 + { + Or(IOD1,0x00,IOD1) + } + Else + { + Or(IOD1,0x02,IOD1) // Address = 0x3BC + } + } + Else // Address = 0x278 + { + Or(IOD1,0x01,IOD1) + } + + // Enable the LPT. + + Or(CR01,0x04,CR01) + Store(0,CRAA) + } + + // D0 Method for LPT-Output Mode. + + Method(_PS0,0,Serialized) + { + Store(0,CR55) + Store(Or(CR01,0x04),CR01) + Store(0,CRAA) + } + + // D3 Method for LPT-Output Mode. + + Method(_PS3,0,Serialized) + { + Store(0,CR55) + Store(And(CR01,0x0FB),CR01) + Store(0,CRAA) + } +} diff --git a/ReferenceCode/AcpiTables/Dsdt/SMSC1000_SIO.asl b/ReferenceCode/AcpiTables/Dsdt/SMSC1000_SIO.asl new file mode 100644 index 0000000..8ba11dc --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/SMSC1000_SIO.asl @@ -0,0 +1,92 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Device(SM10) +{ + Name(_HID,EISAID("PNP0A05")) + + Name(_UID,4) + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if the SIO Device is + // present on the Docking Board. + + If(SMC1) + { + Return(0x000F) + } + + Return(0x0000) + } + + // Define the SMSC1000 Reduced SIO Index/Data Registers as an ACPI + // Operating Region. These registers will be used communicate + // to the SIO. + + OperationRegion(SM10,SystemIO,\SP2O,0x02) + Field(SM10, ByteAcc, Lock, Preserve) + { + INDX, 8, + DATA, 8 + } + + // Use ACPI Defined IndexField so consecutive Index/Data I/Os are + // assured to be uninterrupted. + + IndexField(INDX,DATA,ByteAcc,Lock,Preserve) + { + CR00,8, + CR01,8, + Offset(0x02), + CR02, 8, // UART Power Management + Offset(0x0C), + CR0C, 8, // UARTMODE + Offset(0x23), + CR23,8, + Offset(0x24), + CR24, 8, // UART 1 Base Address + CR25, 8, // UART 2 Base Address + Offset(0x27), + CR27, 8, + Offset(0x28), + CR28, 8, // UART IRQ Select + Offset(0x2B), + CR2B, 8, //SCE (FIR) Base Address + CR2C, 8, //SCE (FIR) DMA Select + Offset(0x3A), + CR3A, 8, // LPC Docking Activate + CR3B, 8, // LPC Docking Base (High) + CR3C, 8, // LPC Docking Base (Low) + Offset(0x55), + CR55, 8, // Configuration Enable Key + Offset(0xAA), + CRAA, 8 // Configuration Disable Key + } + Include("SMSC1000_COM.ASL") + Include("SMSC1000_LPT.ASL") +}
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/Dsdt/SMSC1007_COM.ASL b/ReferenceCode/AcpiTables/Dsdt/SMSC1007_COM.ASL new file mode 100644 index 0000000..c2c820f --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/SMSC1007_COM.ASL @@ -0,0 +1,593 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Device(UAR1) // SMSC 1007 UART 1. +{ + // Identify UART 2 as a COM Port. + + Name(_HID, EISAID("PNP0501")) + + Name(_UID,0) + + // Enable Wake on Ring through a Serial Modem. + + Method(_PRW, 0) { Return(GPRW(0x08, 3)) } // can wakeup from S3 state + + // Status Method for UART 1. + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if the SIO Device is + // not set to Disabled in BIOS Setup. + + If(LAnd(SMSC,CMCP)) + { + // Display UART 1 and return status. + + Store(0,CR55) + Store(CR02,Local0) + Store(0,CRAA) + + If(And(Local0,0x08)) + { + Return(0x000F) + } + + Return(0x000D) + } + + Return(0x0000) + } + + // Disable Method for UART 1. + + Method(_DIS,0,Serialized) + { + Store(0,CR55) + Store(And(CR02,0xF0),CR02) + Store(0,CRAA) + } + + // Current Resource Setting Method for UART 1. + + Method(_CRS,0,Serialized) + { + // Create the Buffer that stores the Resources to + // be returned. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x03F8,0x03F8,0x01,0x08) + IRQNoFlags(){4} + }) + + // Skip this sequence if UART 1 is Disabled + // in BIOS Setup. + + If(LAnd(SMSC,CMCP)) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Write the base address into the Buffer. + + Store(0,CR55) + + ShiftLeft(CR24,2,IOL0) // Low Byte. + ShiftLeft(CR24,2,IOL1) + + ShiftRight(CR24,6,IOH0) // High Byte. + ShiftRight(CR24,6,IOH1) + + // Write the length into the Buffer. + + Store(8,LEN0) + + // Write the IRQ value into the Buffer. + + ShiftLeft(One,ShiftRight(And(CR28,0xF0),4),IRQW) + + Store(0,CRAA) + } + + Return(BUF0) + } + + // Possible Resource Setting Method for UART 1. + + + Name(_PRS,ResourceTemplate() + { + + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){4} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3E8,0x3E8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2E8,0x2E8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for UART 1. + + Method(_SRS,1,Serialized) + { + // Point to the specific information in the passed + // in Buffer. + + CreateByteField(Arg0,0x02,IOLO) + CreateByteField(Arg0,0x03,IOHI) + CreateWordField(Arg0,0x09,IRQW) + + // Disable the device. + + Store(0,CR55) + Store(And(CR02,0xF0),CR02) + + // Set the Base IO Address. + + Store(ShiftRight(IOLO,2),CR24) + Or(CR24,ShiftLeft(IOHI,6),CR24) + + // Set the IRQ. + + And(CR28,0x0F,CR28) + Or(CR28,ShiftLeft(Subtract(FindSetRightBit(IRQW),1),4),CR28) + + // Set the Decode Range so UART 1 works with ICH7 and + // future platforms. + + AND(IOD0,0xF8,IOD0) // Clear all bits. + + If(LEqual(IOHI,0x03)) // Address = 0x3xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x07,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x01,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x05,IOD0) + } + } + + // Enable the device. + + Store(Or(CR02,0x08),CR02) + Store(0,CRAA) + } + + // D0 Method for UART 1. + + Method(_PS0,0,Serialized) + { + Store(0,CR55) + Store(Or(CR02,0x08),CR02) + Store(0,CRAA) + } + + // D3 Method for UART 1. + + Method(_PS3,0,Serialized) + { + Store(0,CR55) + Store(And(CR02,0xF0),CR02) + Store(0,CRAA) + } +} + +Device(UAR2) // SMSC 1007 UART 2. +{ + // Identify UART 2 as an IR Device. + + Name(_HID, EISAID("PNP0510")) + + Name(_UID,0) + + // Status Method for UART 2. + + Method(_STA,0,Serialized) + { + // + //Check SIR Base Address, If ADR9 and ADR8 are 0, SIR disabled. + // + If (LAnd(SMSC,CIRP)) + { + Store(0,CR55) + Store(CR02,Local0) + Store(0,CRAA) + If (And(Local0,0x80)) + { + Return (0x000F) + } + Return (0x000D) // Not present + } + Return (0x0000) + } + // Disable Method for UART 2. + + Method(_DIS,0,Serialized) + { + Store(0,CR55) + + Store(And(CR02,0x0F),CR02) + + // + // Disable IR on Logical Device Activate Register + // + Store(And(CR3A,0xFA),CR02) + + Store(0,CRAA) + } + + + // + // Current Resource Setting Method for UART 2. + // + Method(_CRS,0,Serialized) + { + + // Create the FIR Buffer that stores the Resources to + // be returned. + Name(BUF0,ResourceTemplate() + { + IO(Decode16, 0x0000, 0x0000, 0x01, 0x08) + IO(Decode16, 0x0000, 0x0000, 0x01, 0x08) + IRQNoFlags() {7} + DMA(Compatibility, NotBusMaster, Transfer8, ) {2} + }) + + // Skip this sequence if UART 2 is Disabled + // in BIOS Setup. + + If (LAnd(SMSC,CIRP)) + { + // + // Create pointers to the specific byte. + // + CreateByteField(BUF0,0x02,IO10) + CreateByteField(BUF0,0x03,IO11) + CreateByteField(BUF0,0x04,IO12) + CreateByteField(BUF0,0x05,IO13) + CreateByteField(BUF0,0x0a,IO20) + CreateByteField(BUF0,0x0b,IO21) + CreateByteField(BUF0,0x0c,IO22) + CreateByteField(BUF0,0x0d,IO23) + CreateWordField(BUF0,0x11,IRQW) + CreateByteField(BUF0,0x14,DMA0) + + Store(0,CR55) + + // + // Write the Base Address into the Buffer. + // + ShiftLeft(CR25,2,IO10) // Low Byte. + ShiftRight(And(CR25,0xC0), 6, IO11) + Store(IO10, IO12) + Store(IO11, IO13) + + ShiftLeft(CR2B,3,IO20) // Low Byte. + ShiftRight(And(CR2B,0xE0), 5, IO21) + Store(IO20, IO22) + Store(IO21, IO23) + + // + // Write the IRQ value into the Buffer. + // + Store(0x0,Local1) + And(CR28,0x0F,Local1) + ShiftLeft(1, Local1, IRQW) + + // Write DMA value into buffer + Store(0x0,Local1) + And(CR2C,0x0F,Local1) + If(LEqual(Local1, 0x0F)){ + Store(0, DMA0) //No DMA + }Else{ + ShiftLeft(1, Local1, DMA0) + } + + Store(0,CRAA) + } + + Return(BUF0) + } + + // + // Possible Resource Setting Method for UART 2. + // + // Build a Buffer with all valid UART 2 Resources. + + Name(_PRS, ResourceTemplate() { +// IRQ, No DMA +StartDependentFn(0, 0) { + IO(Decode16,0x3E8,0x3E8,0x01,0x08) + IO(Decode16,0x7E8,0x7E8,0x01,0x08) + IRQNoFlags(){3} + DMA(Compatibility, NotBusMaster, Transfer8_16) {3} + } + StartDependentFnNoPri() { + IO(Decode16, 0x3F8, 0x3F8, 1, 8) + IO(Decode16,0x7E8,0x7E8,0x01,0x08) + IRQNoFlags() {3,4,5,6,7,10,11,12} + DMA(Compatibility, NotBusMaster, Transfer8_16) {1,2,3} + } + StartDependentFnNoPri() { + IO(Decode16, 0x2F8, 0x3F8, 1, 8) + IO(Decode16,0x7E8,0x7E8,0x01,0x08) + IRQNoFlags() {3,4,5,6,7,10,11,12} + DMA(Compatibility, NotBusMaster, Transfer8_16) {1,2,3} + } + StartDependentFnNoPri() { + IO(Decode16, 0x3E8, 0x3E8, 1, 8) + IO(Decode16,0x7E8,0x7E8,0x01,0x08) + IRQNoFlags() {3,4,5,6,7,10,11,12} + DMA(Compatibility, NotBusMaster, Transfer8_16) {1,2,3} + } + StartDependentFnNoPri() { + IO(Decode16, 0x2E8, 0x3E8, 1, 8) + IO(Decode16,0x7E8,0x7E8,0x01,0x08) + IRQNoFlags() {3,4,5,6,7,10,11,12} + DMA(Compatibility, NotBusMaster, Transfer8_16) {1,2,3} + } + EndDependentFn() + + }) + + + // Set Resource Setting Method for UART 2. + // Set Resource Setting Method for UART 2. + Method(_SRS,1,Serialized) + { + Store(0,CR55) + Store(CR2B, Local0) + Store(0,CRAA) + If(Local0) + { + // Point to the specific information in the passed + // in Buffer. + CreateByteField(Arg0,0x02,IO10) + CreateByteField(Arg0,0x03,IO11) + CreateByteField(Arg0,0x0a,IO20) + CreateByteField(Arg0,0x0b,IO21) + CreateWordField(Arg0,0x11,IRQW) + CreateByteField(Arg0,0x14,DMA0) + + Store(0,CR55) + + // + // Disable the device. + // + And(CR02,0x0F,CR02) + + // + // If UART2 mode has not already been configured, set it here. + // +// Store(0x0B, CR0C) +// Store(0x40, CR0A) +// Store(0x0C, CR0C) + + // + // Set the Base IO Address. + // + Store(ShiftRight(IO10,2),CR25) + Or(CR25,ShiftLeft(IO11,6),CR25) + If(IO20){ + Store(ShiftRight(IO20,3),CR2B) + Or(CR2B,ShiftLeft(IO21,5),CR2B) + } + + + // + // Set the IRQ. + // + And(CR28,0xF0,CR28) + Or(CR28,Subtract(FindSetRightBit(IRQW),1),CR28) + + // Set DMA + And(CR2C,0xF0,CR2C) + If(DMA0) + { + Or(CR2C,Subtract(FindSetRightBit(DMA0),1),CR2C) + } + Else + { + Or(CR2C,0x0F,CR2C) // No DMA + } + + // + // Set the Decode Range so UART 2 works with ICH7 and + // future platforms. + // + AND(IOD0,0x8F,IOD0) // Clear all bits. + If(LEqual(IO11,0x03)) // Address = 0x3xx + { + If(LEqual(IO10,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x070,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IO10,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x010,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x050,IOD0) + } + } + + // + // Enable the device. + // + Or(CR02,0x80,CR02) + + Store(0,CRAA) + + } + Else + { + // Point to the specific information in the passed + // in Buffer. + CreateByteField(Arg0,0x02,IOLO) + CreateByteField(Arg0,0x03,IOHI) + CreateWordField(Arg0,0x09,IRQR) + + Store(0,CR55) + + // + // Disable the device. + // + And(CR02,0x0F,CR02) + + // + // If UART2 mode has not already been configured, set it here. + // +// Store(0x0B, CR0C) +// Store(0x40, CR0A) +// Store(0x0C, CR0C) + + // + // Set the Base IO Address. + // + Store(ShiftRight(IOLO,2),CR25) + Or(CR25,ShiftLeft(IOHI,6),CR25) + + // + // Set the IRQ. + // + And(CR28,0xF0,CR28) + Or(CR28,Subtract(FindSetRightBit(IRQR),1),CR28) + + // + // Set the Decode Range so UART 2 works with ICH7 and + // future platforms. + // + AND(IOD0,0x8F,IOD0) // Clear all bits. + + If(LEqual(IOHI,0x03)) // Address = 0x3xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x070,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x010,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x050,IOD0) + } + } + + // + // Enable the device. + // + Or(CR02,0x80,CR02) + + Store(0,CRAA) + } + } + + // + // D0 Method for UART 2. + // + Method(_PS0,0,Serialized) + { + Store(0,CR55) + Store(Or(CR02,0x80),CR02) + Store(0,CRAA) + + } + + // + // D3 Method for UART 2. + // + Method(_PS3,0,Serialized) + { + Store(0,CR55) + Store(And(CR02,0x0F),CR02) + Store(0,CRAA) + + } +} diff --git a/ReferenceCode/AcpiTables/Dsdt/SMSC1007_SIO.ASL b/ReferenceCode/AcpiTables/Dsdt/SMSC1007_SIO.ASL new file mode 100644 index 0000000..6874fe6 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/SMSC1007_SIO.ASL @@ -0,0 +1,149 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + + // Define the SMSC Runtime I/O Registers and the LPC Docking I/O Register + // as an ACPI Operating Region. The base address for both can be found + // in the SMSC 1007 Configuration Registers, specfically at CR30 for the + // Runtime I/O Base and CR3B and CR3C for the LPC Docking Base. + // +Scope(\) +{ + OperationRegion(S_IO,SystemIo,\IO2B,0x11) + Field(S_IO, ByteAcc, NoLock, Preserve) + { + PMS0, 8, + PME0, 8, + PMS1, 8, + PMS2, 8, + PMS3, 8, + PME1, 8, + PME2, 8, + PME3, 8, + Offset(0x08), + SS10, 1, + SS11, 1, + SS12, 1, + SS13, 1, + SS14, 1, + SS15, 1, + SS16, 1, + SS17, 1, + SMS2, 8, + Offset(0x0A), + SE10, 1, + SE11, 1, + SE12, 1, + SE13, 1, + SE14, 1, + SE15, 1, + SE16, 1, + SE17, 1, + SME2, 8, + Offset(0x0C), + RT10, 1, // GP10 = 1 = SMSC COM Port On, 0 = Off, in Wake Mode. + RT11, 1, // GP11 + RT12, 1, // GP12 + RT13, 1, // GP13 + RT14, 1, // GP14 + RT15, 1, // GP15 + RT16, 1, // GP16 + RT17, 1, // GP17 + Offset(0x0E), + RT30, 1, // GP30 + RT31, 1, // GP31 + RT32, 1, // GP32 + RT33, 1, // GP33 + RT34, 1, // GP34 + RT35, 1, // GP35 + RT36, 1, // GP36 + RT37, 1, // GP37 + Offset(0x10), + DLPC, 1, // DLPC Switch + CK33, 1, // 33MHz Clock + CK14, 1 // 14MHz Clock + } +} + +Device(SM17) +{ + Name(_HID,EISAID("PNP0A05")) + + Name(_UID,2) + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if the SIO Device is + // present on the Docking Board. + + If(SMSC) + { + Return(0x000F) + } + + Return(0x0000) + } + + // Define the SM17 Reduced SIO Index/Data Registers as an ACPI + // Operating Region. These registers will be used communicate + // to the SIO. + + OperationRegion(SM17,SystemIO,\SP1O,0x02) + Field(SM17, ByteAcc, Lock, Preserve) + { + INDX, 8, + DATA, 8 + } + + // Use ACPI Defined IndexField so consecutive Index/Data I/Os are + // assured to be uninterrupted. + + IndexField(INDX,DATA,ByteAcc,Lock,Preserve) + { + Offset(0x02), + CR02, 8, // UART Power Management + Offset(0x0C), + CR0C, 8, // UARTMODE + Offset(0x24), + CR24, 8, // UART 1 Base Address + CR25, 8, // UART 2 Base Address + Offset(0x28), + CR28, 8, // UART IRQ Select + Offset(0x2B), + CR2B, 8, //SCE (FIR) Base Address + CR2C, 8, //SCE (FIR) DMA Select + Offset(0x3A), + CR3A, 8, // LPC Docking Activate + CR3B, 8, // LPC Docking Base (High) + CR3C, 8, // LPC Docking Base (Low) + Offset(0x55), + CR55, 8, // Configuration Enable Key + Offset(0xAA), + CRAA, 8 // Configuration Disable Key + } + + Include("SMSC1007_COM.ASL") +} diff --git a/ReferenceCode/AcpiTables/Dsdt/THERMAL.ASL b/ReferenceCode/AcpiTables/Dsdt/THERMAL.ASL new file mode 100644 index 0000000..f38392f --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/THERMAL.ASL @@ -0,0 +1,681 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ +External(\_PR.APSV) +External(\_PR.ACRT) +External(\_PR.AAC0) + +// THERMAL.ASL represents a Thermal Zone to be used for testing on the +// Customer Reference Boards. +Scope(\_TZ) +{ + + // Notes: + // 1) WIN2K strictly uses interrupt driven thermal events. + // 2) Temperature values are stored in tenths of Kelvin to + // eliminate the decimal place. + // 3) Kelvin = Celsius + 273.2. + // 4) All temperature must be >= 289K. + + Name(ETMD, 1) + + // Temprature Threshold in Celsius, used to guard against hardware returning bad temprature readings + Name(THLD, 120) + + // + // YBTx -- _ACx Thermal Trip Points for YellowBluff platform + // + // Matrix of Thermal Trip points & Fan Control (YellowBluff Platform) + // T('C) PWM Duty Cycle + Name(YBT4, 55) // 35 + Name(YBT3, 64) // 55 + Name(YBT2, 73) // 75 + Name(YBT1, 80) // 90 + Name(YBT0, 91) // 100 + + // Fan 0 = Package Processor Fan - Maximum speed + PowerResource(FN00, 0, 0) + { + Method(_STA, 0, Serialized) + { + // Return Virtual Fan 0 status. + Return(VFN0) + } + + // This method is called when the temprature goes above _AC0. + // Regardless of other FAN states, set to ACF0 since this is max cooling state: temp > _AC0 + Method(_ON, 0, Serialized) + { + // Set Virtual Fan 0 On. + Store(1,VFN0) + + // If EC access is enabled. + If(LAnd(ECON, ETMD)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(AC0F, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) + } + } + + // This method is called when the temprature goes below _AC0. + // If FAN1 is on, use its value (AC1F): _AC0 > temp > _AC1 + // If FAN1 is off, use FAN2 value (AC2F): _AC0 > _AC1 > temp + Method(_OFF, 0, Serialized) + { + // Set Virtual Fan 0 Off. + Store(0,VFN0) + + // If EC access is enabled. + If(LAnd(ECON, ETMD)) + { + If(LNotEqual(VFN1,0)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(AC1F, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC1F + } + Else + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC2F = 0 + } + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) + } + } + } + + // Associate Virtual Fan 0 Power Resource with the FAN0 Device. + Device(FAN0) + { + Name(_HID, EISAID("PNP0C0B")) + Name(_UID, 0) + Name(_PR0, Package(1){FN00}) +#if defined(ASL_CRB_EC_SUPPORT) && (ASL_CRB_EC_SUPPORT == 1) + Method(_DEP) // Fan method depends on EC Wrapper Op Region to be available + { + Return(Package() {\_SB.PCI0.LPCB.H_EC}) + } +#endif + } + + // Fan 1 = Package Processor Fan. + PowerResource(FN01,0,0) + { + Method(_STA,0,Serialized) + { + // Return Virtual Fan 1 status. + Return(VFN1) + } + + // This method is called when the temprature goes above _AC1. + // If FAN0 is on, do nothing since we're already at AC0F: temp > _AC0 > _AC1 + // If FAN0 is off, use FAN1 value (AC1F): _AC0 > temp > _AC1 + Method(_ON,0,Serialized) + { + // Set Virtual Fan 1 On. + Store(1,VFN1) + + // If EC access is enabled. + If(LAnd(ECON, ETMD)) + { + If(LEqual(VFN0,0)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(AC1F, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC1F + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) + } + } + } + + // This method is called when the temprature goes below _AC1. + // If FAN2 is on, use its value (AC2F): _AC1 > temp > _AC2 + // If FAN2 is off, use FAN3 value (AC3F): _AC1 > _AC2 > temp + Method(_OFF,0,Serialized) + { + // Set Virtual Fan 1 Off. + Store(0,VFN1) + + // If EC access is enabled. + If(LAnd(ECON, ETMD)) + { + If(LNotEqual(VFN2,0)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC2F = 0 + } + Else + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC3F = 0 + } + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) + } + } + } + + // Associate Virtual Fan 1 Power Resource with the FAN1 Device. + Device(FAN1) + { + Name(_HID, EISAID("PNP0C0B")) + Name(_UID, 1) + Name(_PR0, Package(1){FN01}) +#if defined(ASL_CRB_EC_SUPPORT) && (ASL_CRB_EC_SUPPORT == 1) + Method(_DEP) // Fan method depends on EC Wrapper Op Region to be available + { + Return(Package() {\_SB.PCI0.LPCB.H_EC}) + } +#endif + } + + + // Fan 2 = Package Processor Fan. + PowerResource(FN02,0,0) + { + Method(_STA,0,Serialized) + { + // Return Virtual Fan 2 status. + Return(VFN2) + } + + // This method is called when the temprature goes above _AC2. + // If FAN1 is on, do nothing since we're already at AC1F or greater: temp > _AC1 > _AC2 + // If FAN1 is off, use FAN2 value (AC2F): _AC1 > temp > _AC2 + Method(_ON,0,Serialized) + { + // Set Virtual Fan 2 On. + Store(1,VFN2) + + // If EC access is enabled. + If(LAnd(ECON, ETMD)) + { + If(LEqual(VFN1,0)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC2F = 0 + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) + } + } + } + + // This method is called when the temprature goes below _AC2. + // If FAN3 is on, use its value (AC3F): _AC2 > temp > _AC3 + // If FAN3 is off, use FAN4 value (AC4F): _AC2 > _AC3 > temp + Method(_OFF,0,Serialized) + { + // Set Virtual Fan 2 Off. + Store(0,VFN2) + + // If EC access is enabled. + If(LAnd(ECON, ETMD)) + { + If(LNotEqual(VFN3,0)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC3F = 0 + } + Else + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC4F = 0 + } + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) + } + } + } + + // Associate Virtual Fan 2 Power Resource with the FAN0 Device. + Device(FAN2) + { + Name(_HID, EISAID("PNP0C0B")) + Name(_UID, 2) + Name(_PR0, Package(1){FN02}) +#if defined(ASL_CRB_EC_SUPPORT) && (ASL_CRB_EC_SUPPORT == 1) + Method(_DEP) // Fan method depends on EC Wrapper Op Region to be available + { + Return(Package() {\_SB.PCI0.LPCB.H_EC}) + } +#endif + } + + // Fan 3 = Package Processor Fan. + PowerResource(FN03,0,0) + { + Method(_STA,0,Serialized) + { + // Return Virtual Fan 3 status. + Return(VFN3) + } + + // This method is called when the temprature goes above _AC3. + // If FAN2 is on, do nothing since we're already at AC2F or greater: temp > _AC2 > _AC3 + // If FAN2 is off, use FAN3 value (AC3F): _AC2 > temp > _AC3 + Method(_ON,0,Serialized) + { + // Set Virtual Fan 3 On. + Store(1,VFN3) + + // If EC access is enabled. + If(LAnd(ECON, ETMD)) + { + If(LEqual(VFN2,0)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC3F = 0 + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) + } + } + } + + // This method is called when the temprature goes below _AC3. + // If FAN4 is on, use its value (AC4F): _AC3 > temp > _AC4 + // If FAN4 is off, use FAN5 value (AC5F): _AC3 > _AC4 > temp + Method(_OFF,0,Serialized) + { + // Set Virtual Fan 3 Off. + Store(0,VFN3) + + // If EC access is enabled. + If(LAnd(ECON, ETMD)) + { + If(LNotEqual(VFN4,0)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC4F = 0 + } + Else + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC5F = 0 + } + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) + } + } + } + + // Associate Virtual Fan 3 Power Resource with the FAN3 Device. + Device(FAN3) + { + Name(_HID, EISAID("PNP0C0B")) + Name(_UID, 3) + Name(_PR0, Package(1){FN03}) +#if defined(ASL_CRB_EC_SUPPORT) && (ASL_CRB_EC_SUPPORT == 1) + Method(_DEP) // Fan method depends on EC Wrapper Op Region to be available + { + Return(Package() {\_SB.PCI0.LPCB.H_EC}) + } +#endif + } + + // Fan 4 = Package Processor Fan - Lowest Fan Speed + PowerResource(FN04,0,0) + { + Method(_STA,0,Serialized) + { + // Return Virtual Fan 4 status. + Return(VFN4) + } + + // This method is called when the temprature goes above _AC4. + // If FAN3 is on, do nothing since we're already at AC3F or greater: temp > _AC3 > _AC4 + // If FAN3 is off, use FAN4 value (AC4F): _AC3 > temp > _AC4 + Method(_ON,0,Serialized) + { + // Set Virtual Fan 4 On. + Store(1,VFN4) + + // If EC access is enabled. + If(LAnd(ECON, ETMD)) + { + If(LEqual(VFN3,0)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC4F = 0 + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) + } + } + } + + // This method is called when the temprature goes below _AC4. + // FAN4 is the lowest FAN state defined, so we simply go to AC4F + Method(_OFF,0,Serialized) + { + // Set Virtual Fan 4 Off. + Store(0,VFN4) + + // If EC access is enabled. + If(LAnd(ECON, ETMD)) + { + \_SB.PCI0.LPCB.H_EC.ECWT(0, RefOf(\_SB.PCI0.LPCB.H_EC.PENV)) // AC4F = 0 + \_SB.PCI0.LPCB.H_EC.ECMD(0x1a) + } + } + } + + // Associate Virtual Fan 4 Power Resource with the FAN4 Device. + Device(FAN4) + { + Name(_HID, EISAID("PNP0C0B")) + Name(_UID, 4) + Name(_PR0, Package(1){FN04}) +#if defined(ASL_CRB_EC_SUPPORT) && (ASL_CRB_EC_SUPPORT == 1) + Method(_DEP) // Fan method depends on EC Wrapper Op Region to be available + { + Return(Package() {\_SB.PCI0.LPCB.H_EC}) + } +#endif + } + + // Thermal Zone 0 = Package Thermal Zone. + // Package Thermal Zone is used for Active and Critical Policy Control + // Package Thermal Zone returns the maximum temperature + // of all components within the package + ThermalZone(TZ00) + { + // Temporary variable for holding the current temprature reading + Name(PTMP,3000) + + // Notifies ASL Code the current cooling mode. + // 0 - Active cooling + // 1 - Passive cooling + Method(_SCP, 1, Serialized) + { + Store(Arg0, CTYP) + } + + // Return the temperature at which the OS performs Critical Shutdown + Method(_CRT, 0, Serialized) + { + // Returns automatic thermal reporting temperature for CPU throttling if available and valid. + If(CondRefOf(\_PR.ACRT)) + { + If(LNotEqual(\_PR.ACRT,0)) + { + Return(Add(2732, Multiply(\_PR.ACRT, 10))) + } + } + + Return(Add(2732, Multiply(CRTT, 10))) + } + + // Return the temperature(s) at which the OS initiates Active Cooling. + Method(_AC0, 0, Serialized) + { + // Returns automatic thermal reporting temperature for CPU throttling if available and valid. + If(CondRefOf(\_PR.AAC0)) + { + If(LNotEqual(\_PR.AAC0,0)) + { + Return(Add(2732, Multiply(\_PR.AAC0, 10))) + } + } + Return(Add(2732, Multiply(ACTT, 10))) + + } + + Method(_AC1, 0, Serialized) + { + Return(Add(2732, Multiply(ACT1, 10))) + } + + Method(_AC2, 0, Serialized) + { + Return(Add(2732, Multiply(0, 10))) + + } + + Method(_AC3, 0, Serialized) + { + Return(Add(2732, Multiply(0, 10))) + + } + + Method(_AC4, 0, Serialized) + { + Return(Add(2732, Multiply(0, 10))) + + } + + // Return the device(s) to turn on when _ACx is exceeded. + Name(_AL0, Package(){FAN0}) + Name(_AL1, Package(){FAN1}) + Name(_AL2, Package(){FAN2}) + Name(_AL3, Package(){FAN3}) + Name(_AL4, Package(){FAN4}) + + // Return the Package Temperature. + // Source 1: CPU DTS temperature + // Source 2: Max Platform temprature returned by EC + Method(_TMP, 0, Serialized) + { + + If (LNot(ETMD)) // If Legacy TM is disabled, return static value + { + Return (3000) + } + + If (LEqual(DTSE, 0x3)) //Out Of Spec Condition occurred. Return critical temperature for OS shutdown + { + Return(Add(2832,Multiply(CRTT,10))) + } + + // Source 1: If DTS SMM enabled + // + // If Package Temp MSR is available, then send Package DTS Temp + // otherwise send Core DTS Temp + If(LEqual(DTSE, 0x01)) + { + If(LEqual(PKGA, 0x01)) + { + Store(PDTS, Local0) + Return(Add(2732, Multiply(Local0, 10))) + } + // + // Package DTS not support. Report MAX temperature between all cores to OS. + // + Store(DTS1,Local0) + If(LGreater(DTS2, Local0)) + { + Store(DTS2,Local0) + } + If(LGreater(DTS3, Local0)) + { + Store(DTS3,Local0) + } + If(LGreater(DTS4, Local0)) + { + Store(DTS4,Local0) + } + Return(Add(2732, Multiply(Local0, 10))) + } + + // Source 2: Max Platform temprature returned by EC + // If EC enabled/avaialable + If(ECON) + { + // Store current reading in temporary variable + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PLMX)), Local0) // Max Platform temprature + Add(2732, Multiply(Local0, 10), Local0 ) + Store(Local0, PTMP) + Return(Local0) + } + + + // Return a static value if no source is available. + Return(3010) + } + } + + // Thermal Zone 1 = CPU Thermal Zone. + // CPU Thermal Zone is used for Passive Policy Control + // Since Passive Control implies reducing CPU IA core performance states, + // Only CPU's temperature must be used for that purpose. + ThermalZone(TZ01) + { + + // Temporary variable for holding the current temprature reading + Name(PTMP,3000) + + // Notifies ASL Code the current cooling mode. + // 0 - Active cooling + // 1 - Passive cooling + Method(_SCP, 1, Serialized) + { + Store(Arg0,CTYP) + } + + // Return the temperature at which the OS performs Critical Shutdown + Method(_CRT, 0, Serialized) + { + // Returns automatic thermal reporting temperature for CPU throttling if available and valid. + If(CondRefOf(\_PR.ACRT)) + { + If(LNotEqual(\_PR.ACRT,0)) + { + Return(Add(2732, Multiply(\_PR.ACRT, 10))) + } + } + + Return(Add(2732, Multiply(CRTT, 10))) + } + + // Return the CPU Temperature to the OS. + // CPU Temperature is the maximum temperature of all CPU IA cores + // Source 1: CPU temprature reported by DTS SMM + // Source 2: CPU temprature reported by EC via PECI + Method(_TMP,0,Serialized) + { + + If (LNot(ETMD)) // If Legacy TM is disabled, return static value + { + Return (3020) + } + + If (LEqual(DTSE, 0x3)) //Out Of Spec Condition occurred. Return critical temperature for OS shutdown + { + Return(Add(2832,Multiply(CRTT,10))) + } + + // Source 1: If DTS SMM enabled + // If Package Temp MSR is available, then send Package DTS Temp + // otherwise send Core DTS Temp + If(LEqual(DTSE, 0x01)) + { + If(LEqual(PKGA, 0x01)) + { + Store(PDTS, Local0) + Return(Add(2732, Multiply(Local0, 10))) + } + // + // Package DTS not support. Report MAX temperature between all cores to OS. + // + Store(DTS1,Local0) + If(LGreater(DTS2, Local0)) + { + Store(DTS2,Local0) + } + If(LGreater(DTS3, Local0)) + { + Store(DTS3,Local0) + } + If(LGreater(DTS4, Local0)) + { + Store(DTS4,Local0) + } + Return(Add(2732, Multiply(Local0, 10))) + } + + // If EC avialable/enabled + If(ECON) + { + + // Source 2: CPU temprature reported by EC via PECI + // Store current Integer part of reading in temporary variable + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PECH)), Local0) + Multiply(Local0, 10, Local0) + + // Fractional part of temprature + // Fractional part is in 1/64C, Fractional value = (PECL >> 2 ) * 1/64 + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PECL)), Local1) + ShiftRight(Local1, 2, Local1) + Store(Divide( Multiply(Local1, 10), 64), Local1) + + // Add fractional part to decimal part + Add( Local0, Local1, Local0) + + Add(2732, Local0, Local0 ) + Store(Local0, PTMP) + Return(Local0) + } + + + // Return a static value if no source is available. + Return(3030) + } + + // Return the Processor(s) used for Passive Cooling. + Method(_PSL, 0, Serialized) + { + If(LEqual(TCNT, 8)) + { + // CMP - Throttling controls eight logical CPUs. + Return(Package(){\_PR.CPU0,\_PR.CPU1,\_PR.CPU2,\_PR.CPU3,\_PR.CPU4,\_PR.CPU5,\_PR.CPU6,\_PR.CPU7}) + } + + If(LEqual(TCNT, 4)) + { + // CMP - Throttling controls four logical CPUs. + Return(Package(){\_PR.CPU0,\_PR.CPU1,\_PR.CPU2,\_PR.CPU3}) + } + + If(LEqual(TCNT, 2)) + { + // CMP - Throttling controls both CPUs. + Return(Package(){\_PR.CPU0,\_PR.CPU1}) + } + + Return(Package(){\_PR.CPU0}) + } + + // Returns the temperature at which the OS initiates CPU throttling. + Method(_PSV, 0, Serialized) + { + // Returns automatic thermal reporting temperature for CPU throttling if available and valid. + If(CondRefOf(\_PR.APSV)) + { + If(LNotEqual(\_PR.APSV,0)) + { + Return(Add(2732, Multiply(\_PR.APSV, 10))) + } + } + + Return(Add(2732, Multiply(PSVT, 10))) + } + + // Returns TC1 value used in the passive cooling formula. + Method(_TC1, 0, Serialized) + { + Return(TC1V) + } + + // Returns TC2 value used in the passive cooling formula. + Method(_TC2, 0, Serialized) + { + Return(TC2V) + } + + // Returns the sampling period used in the passive cooling formula. + Method(_TSP, 0, Serialized) + { + Return(TSPV) + } + } +} diff --git a/ReferenceCode/AcpiTables/Dsdt/Video.asl b/ReferenceCode/AcpiTables/Dsdt/Video.asl new file mode 100644 index 0000000..41a33b1 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/Video.asl @@ -0,0 +1,48 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +#if !defined(ASL_Remove_SaSsdt_Data_To_Dsdt) || (ASL_Remove_SaSsdt_Data_To_Dsdt == 0) +External(DIDX) +#endif + +// Brightness Notification: +// Generate a brightness related notification +// to the LFP if its populated. +// +// Arguments: +// Arg0: Notification value. +// +// Return Value: +// None + +Method(BRTN,1,Serialized) +{ + If(LEqual(And(DIDX,0x0F00),0x400)) + { + Notify(\_SB.PCI0.GFX0.DD1F,Arg0) + } +} diff --git a/ReferenceCode/AcpiTables/Dsdt/WPCN381U_COM.asl b/ReferenceCode/AcpiTables/Dsdt/WPCN381U_COM.asl new file mode 100644 index 0000000..494f25e --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/WPCN381U_COM.asl @@ -0,0 +1,775 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Device(UAR5) // Serial Port UART 5 +{ + Name(_HID, EISAID("PNP0501")) + + Name(_UID,3) + + // Status Method for UART 5. + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if the SIO Device is + // not set to Disabled in BIOS Setup. + + If(W381) + { + // Set the SIO to UART 5. + + Store(3,WR07) + + // Display UART 5 and return status. + + If(WR30) + { + Return(0x000F) + } + + Return(0x000D) + } + + Return(0x0000) + } + + // Disable Method for UART 5. + + Method(_DIS,0,Serialized) + { + Store(3,WR07) + Store(0,WR30) + } + + // Current Resource Setting Method for UART 5. + + Method(_CRS,0,Serialized) + { + // Create the Buffer that stores the Resources to + // be returned. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x03F8,0x03F8,0x01,0x08) + IRQNoFlags(){4} + }) + + // Set SIO to UART 5. + + Store(3,WR07) + + // Skip this sequence if the UART 5 Port is Disabled + // in BIOS Setup. + + If(W381) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Write IO and Length values into the Buffer. + + Store(WR60,IOH0) + Store(WR61,IOL0) + Store(WR60,IOH1) + Store(WR61,IOL1) + Store(8,LEN0) + + // Write the IRQ value into the Buffer. + + And(WR70,0x0F,Local0) + If(Local0) + { + ShiftLeft(One,Local0,IRQW) + } + Else + { + Store(Zero,IRQW) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for UART 5. + + // Build a Buffer with all valid COM Port Resources. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){4} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3E8,0x3E8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2E8,0x2E8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for UART 5. + + Method(_SRS,1,Serialized) + { + // Point to the specific information in the passed + // in Buffer. + + CreateByteField(Arg0,0x02,IOLO) + CreateByteField(Arg0,0x03,IOHI) + CreateWordField(Arg0,0x09,IRQW) + + // Set the SIO to UART 5. + + Store(3,WR07) + + // Disable the device. + + Store(0,WR30) + + // Set the Base IO Address. + + Store(IOLO,WR61) + Store(IOHI,WR60) + + // Set the IRQ. + + FindSetRightBit(IRQW,Local0) + If(LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,WR70) + + // Set the Decode Range so UART 5 works on ICH7 and + // future platforms. + + AND(IOD0,0xF8,IOD0) // Clear all bits. + + If(LEqual(IOHI,0x03)) // Address = 0x3xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x07,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x01,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x05,IOD0) + } + } + + // Enable the device. + + Store(1,WR30) + } + + // D0 Method for COM Port. + + Method(_PS0,0,Serialized) + { + Store(3,WR07) + Store(1,WR30) + } + + // D3 Method for COM Port. + + Method(_PS3,0,Serialized) + { + Store(3,WR07) + Store(0,WR30) + } +} + +Device(UAR8) // Serial Port UART 8 +{ + Name(_HID, EISAID("PNP0501")) + + Name(_UID,4) + + // Status Method for UART 8. + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if the SIO Device is + // not set to Disabled in BIOS Setup. + + If(W381) + { + And(WR27,0x0E0,Local0) + If (LEqual (Local0, 0x00)) //SIORevID == 000x xxxxb => 374L(LDC2 card) + { + Store(0x2,WR07) + // Check if Serial port 2 is enabled + If(WR30) + { + Return(0x000F) + } + Return(0x000D) + } + } + Return(Zero) + } + + // Disable Method for UART 8. + + Method(_DIS,0,Serialized) + { + Store(2,WR07) + Store(0,WR30) + } + + // Current Resource Setting Method for UART 8. + + Method(_CRS,0,Serialized) + { + // Create the Buffer that stores the Resources to + // be returned. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x02F8,0x02F8,0x01,0x08) + IRQNoFlags(){3} + }) + + // Set SIO to UART 8. + + Store(2,WR07) + + // Skip this sequence if the UART 8 Port is Disabled + // in BIOS Setup. + + If(W381) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Write IO and Length values into the Buffer. + + Store(WR60,IOH0) + Store(WR61,IOL0) + Store(WR60,IOH1) + Store(WR61,IOL1) + Store(8,LEN0) + + // Write the IRQ value into the Buffer. + + And(WR70,0x0F,Local0) + If(Local0) + { + ShiftLeft(One,Local0,IRQW) + } + Else + { + Store(Zero,IRQW) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for UART 8. + + // Build a Buffer with all valid UART 8 Port Resources. + + Name(_PRS,ResourceTemplate() + { + + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3E8,0x3E8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x2E8,0x2E8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for UART 8. + + Method(_SRS,1,Serialized) + { + // Point to the specific information in the passed + // in Buffer. + + CreateByteField(Arg0,0x02,IOLO) + CreateByteField(Arg0,0x03,IOHI) + CreateWordField(Arg0,0x09,IRQW) + + // Set the SIO to UART 8. + + Store(2,WR07) + + // Disable the device. + + Store(0,WR30) + + // Set the Base IO Address. + + Store(IOLO,WR61) + Store(IOHI,WR60) + + // Set the IRQ. + + FindSetRightBit(IRQW,Local0) + If(LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,WR70) + + // Set the Decode Range so UART 8 works on PCH and + // future platforms. + + AND(IOD0,0x8F,IOD0) // Clear all bits. + + If(LEqual(IOHI,0x03)) // Address = 0x3xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x70,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IOLO,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x10,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x50,IOD0) + } + } + + // Enable the device. + + Store(1,WR30) + } + + // D0 Method for UART 8 Port. + + Method(_PS0,0,Serialized) + { + Store(2,WR07) + Store(1,WR30) + } + + // D3 Method for UART 8 Port. + + Method(_PS3,0,Serialized) + { + Store(2,WR07) + Store(0,WR30) + } +} +//Resource for WPCD376I SP3 Device(LDN 0x16) +Device(LD16) // LDN 0x16 +{ + Name(_HID, EISAID("PNP0501")) + Name(_UID,5) + + // Status Method for LDN 0x16. Keep it Disabled as this LDN is part of Consumer IR device + Method(_STA,0,Serialized) + { + Return(0x0000) + } + + // Possible Resource Setting Method for LDN 0x16. + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){3} + } + StartDependentFn(0,2) + { + IO(Decode16,0x3F8,0x3F8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + StartDependentFn(0,2) + { + IO(Decode16,0x2F8,0x2F8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + StartDependentFn(0,2) + { + IO(Decode16,0x3E8,0x3E8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + StartDependentFn(0,2) + { + IO(Decode16,0x2E8,0x2E8,0x01,0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + EndDependentFn() + }) +} +//Resource for WPCD376I CIR Device(LDN 0x15) +Device(LD15) // LDN 0x15 +{ + Name(_HID, EISAID("WEC0001")) + Name(_UID,6) + + // Status Method for LDN 0x15. Keep it Disabled as this LDN is part of Consumer IR device + Method(_STA,0,Serialized) + { + Return(0x0000) + } + + // Possible Resource Setting Method for CIR. + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO (Decode16, 0x07D0, 0x07D0, 0x01, 0x10) + IO (Decode16, 0x07C0, 0x07C0, 0x01, 0x10) + } + EndDependentFn() + }) +} + +//WPCD376I Consumer IR device +Device (ECIR) +{ + Name (_HID, EISAID("WEC1022")) + Name (_UID, One) + + OperationRegion(CIRR,SystemIO,0x7C0,0x20) + Field(CIRR,ByteAcc,NoLock,Preserve) + { + Offset(0x15), //CIR wake up base address offset 5 [0x7D0 + 5] + RXEE, 3, + , 5, + } + + Method (_STA, 0, NotSerialized) + { + If(W381) + { + And(WR27,0x0E0,Local0) + Store(0x15,WR07) + If (LAnd(LEqual (Local0, 0x80), LOr(WR60,WR61))) //SIORevID == 100x xxxxb => 376I and Resource allocated + { + If (WR30) //Check if CIR device is enabled. + { + Return(0x000F) + } + Return(0x000D) + } + } + Return(Zero) + } + + Method (_DIS, 0, NotSerialized) + { + Store (0x15, WR07) + Store (Zero, WR30) + Store (0x16, WR07) + Store (Zero, WR30) + } + + Method(_CRS,0,Serialized) + { + // Create the Buffer that stores the Resources to + // be returned. + + Name(BUF0,ResourceTemplate() + { + IO (Decode16, 0x0, 0x0, 0x01, 0x10) + IO (Decode16, 0x0, 0x0, 0x01, 0x10) + IO (Decode16, 0x0, 0x0, 0x08, 0x08) + IRQNoFlags (){0} + }) + + CreateByteField(BUF0,0x02,IO00) + CreateByteField(BUF0,0x03,IO01) + CreateByteField(BUF0,0x04,IO10) + CreateByteField(BUF0,0x05,IO11) + CreateByteField(BUF0,0x0a,IO20) + CreateByteField(BUF0,0x0b,IO21) + CreateByteField(BUF0,0x0c,IO30) + CreateByteField(BUF0,0x0d,IO31) + CreateByteField(BUF0,0x12,IO40) + CreateByteField(BUF0,0x13,IO41) + CreateByteField(BUF0,0x14,IO50) + CreateByteField(BUF0,0x15,IO51) + CreateWordField(BUF0,0x19,IRQW) + + // Set the SIO to SP3. + Store(0x16,WR07) + // Set the Base IO Address. + Store(WR61,IO40) + Store(WR60,IO41) + Store(WR61,IO50) + Store(WR60,IO51) + // Write the IRQ value into the Buffer. + And(WR70,0x0F,Local0) + If(Local0) + { + ShiftLeft(One,Local0,IRQW) + } + Else + { + Store(Zero,IRQW) + } + + //set resource for CIr device + // Set the SIO to SP3. + Store(0x15,WR07) + // Set the Base IO Address. + Store(WR61,IO00) + Store(WR60,IO01) + Store(WR61,IO10) + Store(WR60,IO11) + + Store(WR63,IO20) + Store(WR62,IO21) + Store(WR63,IO30) + Store(WR62,IO31) + + Return(BUF0) + } + + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO (Decode16, 0x07D0, 0x07D0, 0x01, 0x10) + IO (Decode16, 0x07C0, 0x07C0, 0x01, 0x10) + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags(){3} + } + StartDependentFn(0,2) + { + IO (Decode16, 0x07D0, 0x07D0, 0x01, 0x10) + IO (Decode16, 0x07C0, 0x07C0, 0x01, 0x10) + IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + StartDependentFn(0,2) + { + IO (Decode16, 0x07D0, 0x07D0, 0x01, 0x10) + IO (Decode16, 0x07C0, 0x07C0, 0x01, 0x10) + IO (Decode16, 0x02F8, 0x02F8, 0x08, 0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + StartDependentFn(0,2) + { + IO (Decode16, 0x07D0, 0x07D0, 0x01, 0x10) + IO (Decode16, 0x07C0, 0x07C0, 0x01, 0x10) + IO (Decode16, 0x03E8, 0x03E8, 0x08, 0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + StartDependentFn(0,2) + { + IO (Decode16, 0x07D0, 0x07D0, 0x01, 0x10) + IO (Decode16, 0x07C0, 0x07C0, 0x01, 0x10) + IO (Decode16, 0x02E8, 0x02E8, 0x08, 0x08) + IRQNoFlags(){4,5,6,7,10,11,12} + } + EndDependentFn () + }) + + Method (_SRS, 1, NotSerialized) + { + CreateByteField(Arg0,0x02,IO00) + CreateByteField(Arg0,0x03,IO01) + CreateByteField(Arg0,0x0a,IO20) + CreateByteField(Arg0,0x0b,IO21) + CreateByteField(Arg0,0x12,IO40) + CreateByteField(Arg0,0x13,IO41) + CreateWordField(Arg0,0x19,IRQW) + + // Set the SIO to SP3. + Store(0x16,WR07) + // Set the Base IO Address. + Store(IO40, WR61) + Store(IO41, WR60) + // Set the IRQ. + FindSetRightBit(IRQW,Local0) + If(LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,WR70) + + AND(IOD0,0x8F,IOD0) // Clear all bits. + If(LEqual(IO41,0x03)) // Address = 0x3xx + { + If(LEqual(IO40,0xF8)) // Address = 0x3F8 + { + Or(IOD0,0x00,IOD0) + } + Else // Address = 0x3E8 + { + Or(IOD0,0x70,IOD0) + } + } + Else // Address = 0x2xx + { + If(LEqual(IO40,0xF8)) // Address = 0x2F8 + { + Or(IOD0,0x10,IOD0) + } + Else // Address = 0x2E8 + { + Or(IOD0,0x50,IOD0) + } + } + + //set resource for CIr device + // Set the SIO to SP3. + Store(0x15,WR07) + // Set the Base IO Address. + Store(IO00, WR61) + Store(IO01, WR60) + Store(IO20, WR63) + Store(IO21, WR62) + Store (0x15, WR07) + Store (One, WR30) + Store (0x16, WR07) + Store (0x82, WRF0) + Store (One, WR30) + } + + Method (_S3D, 0, NotSerialized) + { + Return (0x02) + } + + Method (_S4D, 0, NotSerialized) + { + Return (0x02) + } + + Method (_S3W, 0, NotSerialized) + { + Return (0x02) + } + + Method (_S4W, 0, NotSerialized) + { + Return (0x02) + } + + Name (CPS4, Package (0x02) + { + 0x1D, + 0x04 + }) + Method (_PRW, 0, NotSerialized) + { + Return (CPS4) + } + + Method (_PSW, 1, NotSerialized) + { + If (LEqual (Arg0, Zero)) + { + Store (Zero, RXEE) + } + If (LEqual (Arg0, One)) + { + Store (0x07, RXEE) + } + } +} diff --git a/ReferenceCode/AcpiTables/Dsdt/WPCN381U_LPT.ASL b/ReferenceCode/AcpiTables/Dsdt/WPCN381U_LPT.ASL new file mode 100644 index 0000000..2a2cb9e --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/WPCN381U_LPT.ASL @@ -0,0 +1,988 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + + +// This ASL file will support the LPT in Output, BiDirectional, EPP, +// & ECP mode. Only 1 of these devices will be shown by the OS at any +// given time, and that one will depend on the BIOS configuration. +Scope(\_SB.PCI0.LPCB.WPCN){ + +Device(LPT2) // Printer, Output Mode +{ + Name(_HID,EISAID("PNP0400")) + Name(_UID,2) + + // Status Method for LPT-Output Mode. + + Method(_STA,0,Serialized) + { + // Output mode = 000x xxxxb - check that no bits are set. + + Store(1,WR07) + If(LEqual(And(WRF0,0xE0),0x00)) + { + // LPT is in Output Mode. Only report resources + // to the OS if the SIO Device is not set to + // Disabled in BIOS Setup. + + If(W381) + { + // Set SIO to LPT. + + Store(1,WR07) + + // Display POUT and return Status. + + If(WR30) + { + Return(0x000F) + } + + Return(0x000D) + } + } + + Return(0x0000) + } + + // Disable Method for LPT-Output Mode. + + Method(_DIS,0,Serialized) + { + // Set SIO to LPT. + + Store(1,WR07) + + If(LEqual(And(WRF0,0xE0),0x00)) + { + Store(0,WR30) + } + + } + + // Current Resource Setting Method for LPT-Output Mode. + + Method(_CRS,0,Serialized) + { + // Create a buffer to return to OS. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x0378,0x0378,0x01,0x04) + IRQNoFlags(){7} + }) + + // Skip this sequence if the LPT Device is not set + // to Output Mode. + + If(LEqual(And(WRF0,0xE0),0x00)) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Set SIO to LPT. + Store(1,WR07) + + // Write IO and Length values into the Buffer. + + Store(WR61,IOL0) + Store(WR60,IOH0) + Store(IOL0,IOL1) + Store(IOH0,IOH1) + Store(4,LEN0) + + // Write the IRQ value into the Buffer. + + If(And(WR70,0x0F)) + { + ShiftLeft(One,And(WR70,0x0F),IRQW) + } + Else + { + Store(Zero,IRQW) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for LPT-Output Mode. + // Build a Buffer with all valid LPT Port Resources. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3BC,0x3BC,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3BC,0x3BC,0x01,0x04) + IRQNoFlags(){5} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for LPT-Output Mode. + + Method(_SRS,1,Serialized) + { + // Point to the specific information in the passed + // in Buffer. + + CreateByteField(Arg0,0x02,IOL0) + CreateByteField(Arg0,0x03,IOH0) + CreateWordField(Arg0,0x09,IRQW) + + // Set SIO to LPT. + + Store(1,WR07) + + // Disable the LPT. + + Store(0,WR30) + + // Disable the DMA channels. + + Store(4,WR74) + + // Set the Base IO Address. + + Store(IOL0,WR61) + Store(IOH0,WR60) + + // Set the IRQ. + + FindSetRightBit(IRQW,Local0) + If (LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,WR70) + + // Set the Decode Range so POUT works when docked. + + And(IOD1,0xFC,IOD1) // Decode all bits. + + If(LEqual(IOH0,0x03)) // Address = 0x3xx + { + If(LEqual(IOL0,0x78)) // Address = 0x378 + { + Or(IOD1,0x00,IOD1) + } + Else + { + Or(IOD1,0x02,IOD1) // Address = 0x3BC + } + } + Else // Address = 0x278 + { + Or(IOD1,0x01,IOD1) + } + + // Enable the LPT. + Store(1,WR30) + + // Set to Output Mode. + And(WRF0,0x0F,WRF0) + + + + } + + // D0 Method for LPT-Output Mode. + + Method(_PS0,0,Serialized) + { + Store(1,WR07) + Store(1,WR30) + + } + + // D3 Method for LPT-Output Mode. + + Method(_PS3,0,Serialized) + { + Store(1,WR07) + Store(0,WR30) + + } +} + +Device(PBI2) // Printer, BiDirectional Mode +{ + Name(_HID,EISAID("PNP0400")) + Name(_UID,2) + + // Status Method for LPT-BiDirectional Mode. + + Method(_STA,0,Serialized) + { + // BiDirectional mode = 001x xxxxb, so check that only + // bit 5 is set. + Store(1,WR07) + + If(LEqual(And(WRF0,0xE0),0x20)) + { + // LPT is in BiDirectional Mode. Only report + // resources to the OS if the SIO Device is not + // set to Disabled in BIOS Setup. + + If(W381) + { + // Display PBID and return Status. + + If(WR30) + { + Return(0x000F) + } + + Return(0x000D) + } + } + + Return(0x0000) + } + + // Disable Method for LPT-BiDirectional Mode. + + Method(_DIS,0,Serialized) + { + // Set SIO to LPT. + + Store(1,WR07) + + If(LEqual(And(WRF0,0xE0),0x20)) + { + Store(0,WR30) + } + } + + // Current Resource Setting Method for LPT-BiDirectional Mode. + + Method(_CRS,0,Serialized) + { + // Create a buffer to return to OS. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x0378,0x0378,0x01,0x04) + IRQNoFlags(){7} + }) + + // Skip this sequence if the LPT Device is not set + // to BiDirectional Mode. + + If(LEqual(And(WRF0,0xE0),0x20)) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Set SIO to LPT. + + Store(1,WR07) + + // Write IO and Length values into the Buffer. + + Store(WR61,IOL0) + Store(WR60,IOH0) + Store(IOL0,IOL1) + Store(IOH0,IOH1) + Store(4,LEN0) + + // Write the IRQ value into the Buffer. + + If(And(WR70,0x0F)) + { + ShiftLeft(One,And(WR70,0x0F),IRQW) + } + Else + { + Store(Zero, IRQW) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for LPT-BiDirectional Mode. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3BC,0x3BC,0x01,0x04) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x04) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x3BC,0x3BC,0x01,0x04) + IRQNoFlags(){5} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for LPT-BiDirectional Mode. + + Method(_SRS,1,Serialized) + { + // Arg0 passed into _SRS is the buffer identical to BUF0. + + CreateByteField(Arg0,0x02,IOL0) + CreateByteField(Arg0,0x03,IOH0) + CreateWordField(Arg0,0x09,IRQW) + + Store(1,WR07) + + // Disable the LPT. + + Store(0,WR30) + + // Disable the DMA channels. + + Store(4,WR74) + + // Set the Base IO Address. + + Store(IOL0,WR61) + Store(IOH0,WR60) + + // Set the IRQ. + + FindSetRightBit(IRQW,Local0) + If (LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,WR70) + + // Set the Decode Range so PBID works when docked. + + And(IOD1,0xFC,IOD1) // Decode all bits. + + If(LEqual(IOH0,0x03)) // Address = 0x3xx + { + If(LEqual(IOL0,0x78)) // Address = 0x378 + { + Or(IOD1,0x00,IOD1) + } + Else + { + Or(IOD1,0x02,IOD1) // Address = 0x3BC + } + } + Else // Address = 0x278 + { + Or(IOD1,0x01,IOD1) + } + + // Enable the LPT. + + Store(1,WR30) + + // Set to Bi-Directional Mode. + + Or(And(WRF0,0x0F),0x20,WRF0) + + + } + + // D0 Method for LPT-BiDirectional Mode. + + Method(_PS0,0,Serialized) + { + Store(1,WR07) + Store(1,WR30) + + } + + // D3 Method for LPT-BiDirectional Mode. + + Method(_PS3,0,Serialized) + { + Store(1,WR07) + Store(0,WR30) + } +} + +Device(PEP2) // Printer, EPP Mode +{ + Name(_HID,EISAID("PNP0400")) + Name(_UID,2) + + // Status Method for LPT-EPP Mode. + + Method(_STA,0,Serialized) + { + // EPP 1.9 mode = 011x xxxxb. + + Store(1,WR07) + If(LOr(LEqual(And(WRF0,0xE0),0x60), LEqual(And(WRF0,0xE0),0x40))) + { + // LPT is in EPP Mode. Only report resources + // to the OS if the SIO Device is not set to + // Disabled in BIOS Setup. + + // Display PEPP and return Status. + + If(WR30) + { + Return(0x000F) + } + Else + { + Return(0x000D) + } + } + + + Return(0x0000) + } + + // Disable Method for LPT-EPP Mode. + + Method(_DIS,0,Serialized) + { + // Set SIO to LPT. + + Store(1,WR07) + + If(LOr(LEqual(And(WRF0,0xE0),0x60), LEqual(And(WRF0,0xE0),0x40))) + { + Store(0,WR30) + } + } + + // Current Resource Setting Method for LPT-EPP Mode. + + Method(_CRS,0,Serialized) + { + // Create a buffer to return to OS. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x0378,0x0378,0x01,0x08) + IRQNoFlags(){7} + }) + + // Skip this sequence if the LPT Device is not set + // to EPP Mode. + + If(LOr(LEqual(And(WRF0,0xE0),0x60), LEqual(And(WRF0,0xE0),0x40))) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateWordField(BUF0,0x09,IRQW) + + // Set SIO to LPT. + + Store(1,WR07) + + // Write IO and Length values into the Buffer. + + Store(WR61,IOL0) + Store(WR60,IOH0) + Store(IOL0,IOL1) + Store(IOH0,IOH1) + Store(8,LEN0) + + // Write the IRQ value into the Buffer. + + If(And(WR70,0x0F)) + { + ShiftLeft(One,And(WR70,0x0F),IRQW) + } + Else + { + Store(Zero, IRQW) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for LPT-EPP Mode. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x08) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x08) + IRQNoFlags(){7} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x08) + IRQNoFlags(){5} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x08) + IRQNoFlags(){5} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for LPT-EPP Mode. + + Method(_SRS,1,Serialized) + { + // Arg0 passed into _SRS is the buffer identical to BUF0. + + CreateByteField(Arg0,0x02,IOL0) + CreateByteField(Arg0,0x03,IOH0) + CreateWordField(Arg0,0x09,IRQW) + + Store(1,WR07) + + // Disable the LPT. + + Store(0,WR30) + + // Disable the DMA channels. + + Store(4,WR74) + + // Set the Base IO Address. + + Store(IOL0,WR61) + Store(IOH0,WR60) + + // Set the IRQ. + + FindSetRightBit(IRQW,Local0) + If (LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,WR70) + + // Set the Decode Range so PEPP works when docked. + + And(IOD1,0xFC,IOD1) // Decode all bits. + + If(LEqual(IOH0,0x03)) // Address = 0x378 + { + Or(IOD1,0x00,IOD1) + } + Else // Address = 0x278 + { + Or(IOD1,0x01,IOD1) + } + + // Enable the LPT. + + Store(1,WR30) + + // Set to SPP + EPP 1.9 Mode. + + Or(And(WRF0,0x0F),0x60,WRF0) + + } + + // D0 Method for LPT-EPP Mode. + + Method(_PS0,0,Serialized) + { + Store(1,WR07) + Store(1,WR30) + } + + // D3 Method for LPT-EPP Mode. + + Method(_PS3,0,Serialized) + { + Store(1,WR07) + Store(0,WR30) + } +} + +Device(PEC2) // Printer, ECP Mode +{ + Name(_HID,EISAID("PNP0401")) + Name(_UID,2) + + // Status Method for LPT-ECP Mode. + + Method(_STA,0,Serialized) + { + // ECP mode = 111x xxxxb. + + Store(1,WR07) + If(LOr(LEqual(And(WRF0,0xE0),0xE0), LEqual(And(WRF0,0xE0),0x80))) + { + // LPT is in ECP Mode. Only report resources + // to the OS if the SIO Device is not set to + // Disabled in BIOS Setup. + + + + // Display PECP and return Status. + + If(WR30) + { + Return(0x000F) + } + Else + { + Return(0x000D) + } + + } + + Return(0x0000) + } + + // Disable Method for LPT-ECP Mode. + + Method(_DIS,0,Serialized) + { + // Set SIO to LPT. + + Store(1,WR07) + + If(LOr(LEqual(And(WRF0,0xE0),0xE0), LEqual(And(WRF0,0xE0),0x80))) + { + Store(0,WR30) + } + } + + // Current Resource Setting Method for LPT-ECP Mode. + + Method(_CRS,0,Serialized) + { + // Create a buffer to return to OS. + + Name(BUF0,ResourceTemplate() + { + IO(Decode16,0x0378,0x0378,0x01,0x08) + IO(Decode16,0x0778,0x0778,0x01,0x08) + IRQNoFlags(){7} + DMA(Compatibility,NotBusMaster,Transfer8_16,){1} + }) + + // Skip this sequence if the LPT Device is not set + // to ECP Mode. + + If(LOr(LEqual(And(WRF0,0xE0),0xE0), LEqual(And(WRF0,0xE0),0x80))) + { + // Create pointers to the specific byte. + + CreateByteField(BUF0,0x02,IOL0) + CreateByteField(BUF0,0x03,IOH0) + CreateByteField(BUF0,0x04,IOL1) + CreateByteField(BUF0,0x05,IOH1) + CreateByteField(BUF0,0x07,LEN0) + CreateByteField(BUF0,0x0A,IOL2) + CreateByteField(BUF0,0x0B,IOH2) + CreateByteField(BUF0,0x0C,IOL3) + CreateByteField(BUF0,0x0D,IOH3) + CreateByteField(BUF0,0x0F,LEN1) + CreateWordField(BUF0,0x11,IRQW) + CreateByteField(BUF0,0x14,DMA0) + + // Set SIO to LPT. + + Store(1,WR07) + + // Write IO and Length values into the Buffer. + + Store(WR61,IOL0) + Store(WR60,IOH0) + Store(IOL0,IOL1) + Store(IOH0,IOH1) + Store(IOL0,IOL2) + Store(Add(0x4,IOH0),IOH2) + Store(IOL0,IOL3) + Store(Add(0x4,IOH0),IOH3) + Store(8,LEN0) + Store(8,LEN1) + + // Write the IRQ value into the Buffer. + + And(WR70,0x0F,Local0) + If(Local0) + { + ShiftLeft(One,Local0,IRQW) + } + Else + { + Store(Zero,IRQW) + } + + // Write the DMA value into the Buffer. + + Store(WR74,Local0) + If(LEqual(Local0,0x04)) + { + Store(Zero,DMA0) + } + Else + { + ShiftLeft(One,Local0,DMA0) + } + } + + Return(BUF0) + } + + // Possible Resource Setting Method for LPT-ECP Mode. + + Name(_PRS,ResourceTemplate() + { + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x08) + IO(Decode16,0x778,0x778,0x01,0x08) + IRQNoFlags(){7} + DMA(Compatibility,NotBusMaster,Transfer8_16){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x08) + IO(Decode16,0x678,0x678,0x01,0x08) + IRQNoFlags(){7} + DMA(Compatibility,NotBusMaster,Transfer8_16){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x08) + IO(Decode16,0x778,0x778,0x01,0x08) + IRQNoFlags(){5} + DMA(Compatibility,NotBusMaster,Transfer8_16){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x08) + IO(Decode16,0x678,0x678,0x01,0x08) + IRQNoFlags(){5} + DMA(Compatibility,NotBusMaster,Transfer8_16){3} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x08) + IO(Decode16,0x778,0x778,0x01,0x08) + IRQNoFlags(){7} + DMA(Compatibility,NotBusMaster,Transfer8_16){1} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x08) + IO(Decode16,0x678,0x678,0x01,0x08) + IRQNoFlags(){7} + DMA(Compatibility,NotBusMaster,Transfer8_16){1} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x378,0x378,0x01,0x08) + IO(Decode16,0x778,0x778,0x01,0x08) + IRQNoFlags(){5} + DMA(Compatibility,NotBusMaster,Transfer8_16){1} + } + + StartDependentFn(0,2) + { + IO(Decode16,0x278,0x278,0x01,0x08) + IO(Decode16,0x678,0x678,0x01,0x08) + IRQNoFlags(){5} + DMA(Compatibility,NotBusMaster,Transfer8_16){1} + } + + EndDependentFn() + }) + + + // Set Resource Setting Method for LPT-ECP Mode. + + Method(_SRS,1,Serialized) + { + // Arg0 passed into _SRS is the buffer identical to BUF0. + + CreateByteField(Arg0,0x02,IOL0) + CreateByteField(Arg0,0x03,IOH0) + CreateWordField(Arg0,0x11,IRQW) + CreateByteField(Arg0,0x14,DMA0) + + Store(1,WR07) + + // Disable the LPT. + + Store(0,WR30) + + + // Set the Base I/O Address + + Store(IOL0,WR61) + Store(IOH0,WR60) + + // Set the IRQ + + FindSetRightBit(IRQW,Local0) + If (LNotEqual(IRQW,Zero)) + { + Decrement(Local0) + } + Store(Local0,WR70) + + // Set the DMA Channel + + FindSetRightBit(DMA0,Local0) + If (LNotEqual(DMA0,Zero)) + { + Decrement(Local0) + } + Store(Local0,WR74) + + // Set the Decode Range so PECP works when docked. + + And(IOD1,0xFC,IOD1) // Decode all bits. + + If(LEqual(IOH0,0x03)) // Address = 0x378 + { + Or(IOD1,0x00,IOD1) + } + Else // Address = 0x278 + { + Or(IOD1,0x01,IOD1) + } + + // Enable the LPT. + + Store(1,WR30) + + // Set to ECP Mode with EPP Mode 4 support. + + Or(WRF0,0xF0,WRF0) + + } + + // D0 Method for LPT-ECP Mode. + + Method(_PS0,0,Serialized) + { + Store(1,WR07) + Store(1,WR30) + } + + // D3 Method for LPT-ECP Mode. + + Method(_PS3,0,Serialized) + { + Store(1,WR07) + Store(0,WR30) + } +} + +} // End of Scope() diff --git a/ReferenceCode/AcpiTables/Dsdt/WPCN381U_SIO.asl b/ReferenceCode/AcpiTables/Dsdt/WPCN381U_SIO.asl new file mode 100644 index 0000000..9bf40f5 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/WPCN381U_SIO.asl @@ -0,0 +1,98 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Device(WPCN) +{ + Name(_HID,EISAID("PNP0A05")) + + Name(_UID,3) + + // Status Method for the National SIO. + + Method(_STA,0,Serialized) + { + // Only report resources to the OS if the SIO Device is + // present on the Docking Board. + + If(W381) + { + Return(0x000F) + } + + Return(0x0000) + } + + // Define the SIO Index/Data Registers as an ACPI Operating + // Region. These registers will be used communicate to the SIO. + + OperationRegion(WPCN, SystemIO, 0x02E, 0x02) + Field(WPCN, ByteAcc, Lock, Preserve) + { + INDX, 8, + DATA, 8 + } + + // Use ACPI Defined IndexField so consecutive Index/Data I/Os are + // assured to be uninterrupted. + + IndexField(INDX, DATA, ByteAcc, Lock, Preserve) + { + Offset(0x07), // Logical Device Number. + WR07, 8, + Offset(0x20), // SIO Configuration and ID. + WR20, 8, + WR21, 8, + WR22, 8, + WR23, 8, + WR24, 8, + WR25, 8, + WR26, 8, + WR27, 8, + WR28, 8, + WR29, 8, + WR2A, 8, + Offset(0x30), // Logical Device Activate. + WR30, 8, + Offset(0x60), // I/O Space Configuration. + WR60, 8, + WR61, 8, + WR62, 8, + WR63, 8, + Offset(0x70), // Interrupt Configuration. + WR70, 8, + WR71, 8, + Offset(0x74), // DMA Configuration. + WR74, 8, + WR75, 8, + Offset(0xF0), // Special Logical Device Configuration. + WRF0, 8, + WRF1, 8 + } + + Include ("WPCN381U_COM.ASL") + Include ("WPCN381U_LPT.ASL") +} diff --git a/ReferenceCode/AcpiTables/Dsdt/token.asl b/ReferenceCode/AcpiTables/Dsdt/token.asl new file mode 100644 index 0000000..d62a151 --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/token.asl @@ -0,0 +1,145 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +Name(SP2O, 0x4e) // Super I/O (SMSC 1007) Index/Data configuration port for ASL. +Name(SP1O, 0x164e) // Super I/O (SMSC 1007) Index/Data configuration port for ASL. +Name(IO1B, 0x600) // Super I/O (SMSC 1007) GPIO base address +Name(IO1L, 0x70) // Super I/O (SMSC 1007) GPIO base address length +Name(IO2B, 0x680) // Super I/O (SMSC 1007) PME base address +Name(IO2L, 0x20) // Super I/O (SMSC 1007) PME base address length +Name(IO3B, 0x290) // Super I/O (SMSC 1007) HHM Base Address +Name(IO3L, 0x10) // Super I/O (SMSC 1007) HHM base address length +Name(SP3O, 0x2e) // Super I/O (Winbond 3xx) Index/Data configuration port for ASL. +Name(IO4B, 0xa20) // Super I/O (Winbond 3xx) GPIO base address length +Name(IO4L, 0x20) // Super I/O (Winbond 3xx) GPIO base address length +Name(HSCS, 0x1) // Hitachi H8S2113D Super I/O COM port status. +Name(MCHB, 0xfed10000) // MCH BAR address +Name(MCHL, 0x8000) // MCH BAR length +Name(EGPB, 0xfed19000) // EP BAR address +Name(EGPL, 0x1000) // EP BAR length +Name(DMIB, 0xfed18000) // DMI BAR address +Name(DMIL, 0x1000) // DMI BAR length +Name(IFPB, 0xfed14000) // Base addrerss of 4K MMIO Window any write to which will FLUSH GMCH Global Write Buffer to let software + // guarantee coherency between writes from an isochronous agent and writes from the CPU. +Name(IFPL, 0x1000) // Length of the MMIO region above. +Name(PEBS, EDKII_GLUE_PciExpressBaseAddress) // PCI Express BAR address +Name(PELN, PLATFORM_PCIEXPRESS_LENGTH) // PCI Express BAR length +Name(TTTB, 0xfed20000) // +Name(TTTL, 0x20000) // +Name(SMBS, 0xefa0) // SMBus I/O Registes Base Address +Name(SMBL, 0x10) // SMBus I/O Registes Range +Name(PBLK, 0x1810) // Boot-strap CPU Control Block register address. Use return value of PM_BASE_ADDRESS with proper offset. +Name(PMBS, 0x1800) // ASL alias for ACPI I/O base address. +Name(PMLN, 0x100) // Power Management registers block length +Name(LVL2, 0x1814) // Processor LVL2 register I/O address. +Name(LVL3, 0x1815) // Processor LVL3 register I/O address. +Name(LVL4, 0x1816) // Processor LVL4 register I/O address. +Name(SMIP, 0xb2) // I/O port to triggle SMI +Name(GPBS, 0x800) // GPIO Register Block address +Name(GPLN, 0x400) // GPIO Register Block length +Name(APCB, 0xfec00000) // Default I/O APIC(s) memory start address, 0x0FEC00000 - default, 0 - I/O APIC's disabled +Name(APCL, 0x1000) // I/O APIC(s) memory decoded range, 0x1000 - default, 0 - I/O APIC's not decoded +Name(PM30, 0x1830) // SMI Control Register +Name(SRCB, 0xfed1c000) // RCBA (Root Complex Base Address) +Name(SRCL, 0x4000) // RCBA length +Name(HPTB, 0xfed00000) // Same as HPET_BASE_ADDRESS for ASL use +Name(HPTC, 0xfed1f404) // High Precision Event Timer Configuration Register +Name(ACPH, 0xde) // North Bridge Scratchpad Data Register for patch ACPI. +Name(ASSB, 0x0) // ACPI Sleep State Buffer for BIOS Usage. +Name(AOTB, 0x0) // ACPI OS Type Buffer for BIOS Usage. +Name(AAXB, 0x0) // ACPI Auxiliary Buffer for BIOS Usage. +Name(PEHP, 0x1) // _OSC: Pci Express Native Hot Plug Control +Name(SHPC, 0x1) // _OSC: Standard Hot Plug Controller (SHPC) Native Hot Plug control +Name(PEPM, 0x1) // _OSC: Pci Express Native Power Management Events control +Name(PEER, 0x1) // _OSC: Pci Express Advanced Error Reporting control +Name(PECS, 0x1) // _OSC: Pci Express Capability Structure control +Name(ITKE, 0x0) // This will be overridden by the ITK module. +Name(DSSP, 0x0) // ON - Disable SATA Software Setting Preservation feature so that it will not preserve the state after hardware reset. i.e. After a hardware reset HDD will change security state as power-on. OFF - Do not change it in POST, leave it as default (enabled). +Name(FHPP, 0x0) // Set to 1 to always prompt for HDD password (in AHCI mode). +Name(FMBL, 0x1) // Platform Flavor - Mobile flavor for ASL code. +Name(FDTP, 0x2) // Platform Flavor - Desktop flavor for ASL code. +Name(FUPS, 0x3) // Platform Flavor - UP Server flavor for ASL code. +Name(FEMD, 0x4) // Platform Flavor - Embedded flavor for ASL code. +Name(BGR, 0x1) // Haswell - Grays Reef Board ID for ASL code. +Name(BFR, 0x2) // Haswell - Flathead Rock Board ID for ASL code. +Name(BBR, 0x3) // Haswell - Basking Ridge Board ID for ASL code. +Name(BWC, 0x4) // Haswell - Walnut Canyon Board ID for ASL code. +Name(BGRP, 0x9) // Haswell - Grays Reef PPV Board ID for ASL code. +Name(BGRC, 0xa) // Haswell - Grays Reef CPV Board ID for ASL code. +Name(BFRP, 0xb) // Haswell - Flathead Rock PPV Board ID for ASL code. +Name(BBRP, 0xc) // Haswell - Basking Ridge PPV Board ID for ASL code. +Name(BRPS, 0x10) // Haswell - STHIPPVRSVD1 Board ID for ASL code. +Name(BRCS, 0x11) // Haswell - STHICPVRSVD2 Board ID for ASL code. +Name(BRDS, 0x12) // Haswell - STHIDOERSVD3 Board ID for ASL code. +Name(BR4S, 0x13) // Haswell - STHIPPVRSVD4 Board ID for ASL code. +Name(BR5S, 0x14) // Haswell - STHIPPVRSVD5 Board ID for ASL code. +Name(BWT1, 0x20) // Haswell - WhiteTip Mountain1 Board ID for ASL code. +Name(BW1P, 0x21) // Haswell - WhiteTip Mountain1 PPV Board ID for ASL code. +Name(BW2C, 0x22) // Haswell - WhiteTip Mountain2 Board ID for ASL code. +Name(BW2P, 0x23) // Haswell - WhiteTip Mountain2 PPV Board ID for ASL code. +Name(BSPC, 0x24) // Haswell - Sawtooth Peak Board ID for ASL code. +Name(BSPP, 0x25) // Haswell - Sawtooth Peak PPV Board ID for ASL code. +Name(BTS, 0x26) // Haswell - TopSham Board ID for ASL code. +Name(BICO, 0x27) // Haswell - WhiteTip Mountain2 CDK Open Chasis Board ID for ASL code. +Name(BICC, 0x28) // Haswell - WhiteTip Mountain2 CDK Closed Chasis Board ID for ASL code. +Name(BHB, 0x30) // Haswell - Harris Beach FFRD Board ID for ASL code. +Name(BFS2, 0x31) // Haswell - FFRD SKU2 Board ID for ASL code. +Name(BFS3, 0x32) // Haswell - FFRD SKU3 Board ID for ASL code. +Name(BFS4, 0x33) // Haswell - FFRD SKU4 Board ID for ASL code. +Name(BRH, 0x35) // Haswell - Reed Harbor TDV Board ID for ASL code. + +Name(BFHC, 0x40) // Haswell - Flathead Creek Board ID for ASL code +Name(BFD1, 0x41) // Haswell - Flathead Creek DOE1 Board ID for ASL code. +Name(BFD2, 0x42) // Haswell - Flathead Creek DOE2 Board ID for ASL code. +Name(BFCC, 0x43) // Haswell - Flathead Creek CRB Board ID for ASL code. +Name(BHCP, 0x44) // Haswell - Haddock Creek Board ID for ASL code. +Name(BCOC, 0x45) // Haswell - CRB OC Board ID for ASL code. +Name(BFHP, 0x46) // Haswell - Flathead Creek PPV Board ID for ASL code. +Name(BFCP, 0x47) // Haswell - Flathead Creek CPV Board ID for ASL code. +Name(BTDT, 0x50) // BidwellBar - TumaloFalls DT Board ID for ASL code. +Name(BTMB, 0x51) // BidwellBar - TumaloFalls MB Board ID for ASL code. +Name(BBGB, 0x52) // Big Creek MB Board ID for ASL code. +Name(BHC2, 0x53) // Haswell - Haddock Creek Fab2 Board ID for ASL code. + +Name(TCGM, 0x1) // Flag to check TCG Module support in platform.asl +Name(TRTP, 0x1) // PPM IO Trap flag +Name(WDTE, 0x1) // Flag for WDT enabled/disabled +Name(TRTD, 0x2) // DTS IO Trap flag +Name(TRTI, 0x3) // IGD IO Trap flag +Name(PFTI, 0x4) // PFAT IO Trap flag +Name(GCDD, 0x1) // SW_SMI_GET_CURRENT_DISPLAY_DEVICE +Name(DSTA, 0xa) // SW_SMI_DISPLAY_SWITCH_TOGGLE_ACPI +Name(DSLO, 0xc) // SW_SMI_DISPLAY_SWITCH_LID_OPEN_ACPI +Name(DSLC, 0xe) // SW_SMI_DISPLAY_SWITCH_LID_CLOSE_ACPI +Name(PITS, 0x10) // SW_SMI_POPUP_ICON_TOGGLE +Name(SBCS, 0x12) // SW_SMI_SET_BACKLIGHT_CONTROL +Name(SALS, 0x13) // SW_SMI_SET_ALI_LEVEL +Name(LSSS, 0x2a) // SW_SMI_LID_STATE_SWITCH +Name(SOOT, 0x35) // SW_SMI_SAVE_OSB_OS_TYPE +Name(PDBR, 0x4d) // SW_SMI_PCIE_DOCK_BRIDGE_RESOURCE_PATCH +Name(DPPB, 0xfed98000) // Thermal Solution Resource Base Address +Name(DPPL, 0x8000) // Length of Thermal Solution Resource Base Address diff --git a/ReferenceCode/AcpiTables/Dsdt/wcam.asl b/ReferenceCode/AcpiTables/Dsdt/wcam.asl new file mode 100644 index 0000000..8d75b2d --- /dev/null +++ b/ReferenceCode/AcpiTables/Dsdt/wcam.asl @@ -0,0 +1,21 @@ +Device(WCAM) +{ + Name(_ADR, 0x05) + Method(_UPC, 0, Serialized) { + Name(UPCP, Package() { 0x00,0xFF,0x00,0x00 }) // Not connectable, Proprietary connector + Return(UPCP) + } + + Method(_PLD, 0, Serialized) { + Name(PLDP, Package(1) + { + Buffer(0x14) + { + 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Revision 2 + 0x24, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Not visible, Center + 0xC8, 0x00, 0xA0, 0x00 + } + }) + Return (PLDP) + } +}
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/Protocol/AcpiInfo/AcpiInfo.c b/ReferenceCode/AcpiTables/Protocol/AcpiInfo/AcpiInfo.c new file mode 100644 index 0000000..615e5cc --- /dev/null +++ b/ReferenceCode/AcpiTables/Protocol/AcpiInfo/AcpiInfo.c @@ -0,0 +1,42 @@ +/** @file + +@brief + This file defines the Acpi Info Protocol. + +@copyright + Copyright (c) 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +/// +/// Statements that include other files +/// +/// +/// External include files do NOT need to be explicitly specified in real EDKII environment +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGlueDxe.h" +#endif + +#include "AcpiInfo.h" + +/// +/// Protocol GUID definition +/// +EFI_GUID gEfiAcpiInfoProtocolGuid = EFI_ACPI_INFO_PROTOCOL_GUID; + +/// +/// Protocol description string +/// +EFI_GUID_STRING(&gEfiAcpiInfoProtocolGuid, "Acpi Info Protocol", "Acpi Information Protocol"); diff --git a/ReferenceCode/AcpiTables/Protocol/AcpiInfo/AcpiInfo.h b/ReferenceCode/AcpiTables/Protocol/AcpiInfo/AcpiInfo.h new file mode 100644 index 0000000..9454f7d --- /dev/null +++ b/ReferenceCode/AcpiTables/Protocol/AcpiInfo/AcpiInfo.h @@ -0,0 +1,68 @@ +/** @file + This file defines the ACPI Info Protocol. + +@copyright + Copyright (c) 2012 - 2014 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _ACPI_INFO_H_ +#define _ACPI_INFO_H_ + +/// +/// Define ACPI INFO protocol GUID (EDK and EDKII have different GUID formats) +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define EFI_ACPI_INFO_PROTOCOL_GUID \ + { \ + 0xfcdc1aa3, 0x1f1e, 0x4d47, 0xbf, 0x61, 0x3c, 0x3b, 0xd2, 0x65, 0x5d, 0x1e \ + } +#else +#define EFI_ACPI_INFO_PROTOCOL_GUID \ + { \ + 0xfcdc1aa3, 0x1f1e, 0x4d47, \ + { \ + 0xbf, 0x61, 0x3c, 0x3b, 0xd2, 0x65, 0x5d, 0x1e \ + } \ + } +#endif + +/// +/// Extern the GUID for protocol users. +/// +extern EFI_GUID gEfiAcpiInfoProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _EFI_ACPI_INFO_PROTOCOL EFI_ACPI_INFO_PROTOCOL; + +/// +/// Protocol revision number +/// Any backwards compatible changes to this protocol will result in an update in the revision number +/// Major changes will require publication of a new protocol +/// +/// Revision 1: Original version +/// +#define ACPI_INFO_PROTOCOL_REVISION_1 1 +#define ACPI_RC_VERSION 0x01090000 + +/// +/// Protocol definition +/// +struct _EFI_ACPI_INFO_PROTOCOL { + UINT8 Revision; + UINT32 RCVersion; +}; + +#endif diff --git a/ReferenceCode/AcpiTables/Protocol/AcpiPlatformPolicy/AcpiPlatformPolicy.c b/ReferenceCode/AcpiTables/Protocol/AcpiPlatformPolicy/AcpiPlatformPolicy.c new file mode 100644 index 0000000..8a9b683 --- /dev/null +++ b/ReferenceCode/AcpiTables/Protocol/AcpiPlatformPolicy/AcpiPlatformPolicy.c @@ -0,0 +1,38 @@ +/** @file + +@brief + This file defines the ACPI Policy Protocol. + +@copyright + Copyright (c) 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ + +/// +/// Statements that include other files +/// +#include "EdkIIGlueDxe.h" +#include "AcpiPlatformPolicy.h" + +/// +/// Protocol GUID definition +/// +EFI_GUID gAcpiPlatformPolicyProtocolGuid = ACPI_PLATFORM_POLICY_PROTOCOL_GUID; + +/// +/// Protocol description string +/// +EFI_GUID_STRING (&gAcpiPlatformPolicyProtocolGuid, "AcpiPlatformPolicy Protocol", "Intel(R) DXE Phase ACPI Platform Policy Protocol"); diff --git a/ReferenceCode/AcpiTables/Protocol/AcpiPlatformPolicy/AcpiPlatformPolicy.h b/ReferenceCode/AcpiTables/Protocol/AcpiPlatformPolicy/AcpiPlatformPolicy.h new file mode 100644 index 0000000..5dc7727 --- /dev/null +++ b/ReferenceCode/AcpiTables/Protocol/AcpiPlatformPolicy/AcpiPlatformPolicy.h @@ -0,0 +1,59 @@ +/** @file + Interface definition details between ACPI and platform drivers during DXE phase. + +@copyright + Copyright (c) 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ + +#ifndef _ACPI_PLATFORM_POLICY_H_ +#define _ACPI_PLATFORM_POLICY_H_ + +/// +/// ACPI policy provided by platform for DXE phase +/// +#define ACPI_PLATFORM_POLICY_PROTOCOL_GUID \ + { 0xe9a6ca5a, 0x85bc, 0x4840, 0x87, 0x84, 0x94, 0xcf, 0xc9, 0xed, 0x67, 0x66 } + +/// +/// Extern the GUID for protocol users. +/// +extern EFI_GUID gAcpiPlatformPolicyProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +EFI_FORWARD_DECLARATION (ACPI_PLATFORM_POLICY_PROTOCOL); + +/// +/// Protocol revision number +/// +#define ACPI_PLATFORM_POLICY_PROTOCOL_REVISION_1 1 + +/// +/// ACPI DXE Platform Policy +/// +struct _ACPI_PLATFORM_POLICY_PROTOCOL { + UINT8 Revision; + UINT16 BoardId; + UINT8 EnableDptf; ///< 0=Disable; 1=Enable; DEFAULT=0 + UINT8 EnableCppc; ///< 0=Disable; 1=Enable; DEFAULT=0 + UINT8 EnableCppcPlatformSCI; ///< 0=Disable; 1=Enable; DEFAULT=0 + UINT8 EnableRtD3; ///< 0=Disable; 1=Enable; DEFAULT=0 + UINT8 EnableAcpiDebug; ///< 0=Disable; 1=Enable; DEFAULT=0 +}; + +#endif diff --git a/ReferenceCode/AcpiTables/Protocol/AcpiProtocolLib.cif b/ReferenceCode/AcpiTables/Protocol/AcpiProtocolLib.cif new file mode 100644 index 0000000..59b6e4e --- /dev/null +++ b/ReferenceCode/AcpiTables/Protocol/AcpiProtocolLib.cif @@ -0,0 +1,14 @@ +<component> + name = "AcpiProtocolLib" + category = ModulePart + LocalRoot = "ReferenceCode\AcpiTables\Protocol\" + RefName = "AcpiProtocolLib" +[files] +"AcpiProtocolLib.sdl" +"AcpiProtocolLib.mak" +"AcpiProtocolLib.inf" +"AcpiInfo\AcpiInfo.c" +"AcpiInfo\AcpiInfo.h" +"AcpiPlatformPolicy\AcpiPlatformPolicy.c" +"AcpiPlatformPolicy\AcpiPlatformPolicy.h" +<endComponent> diff --git a/ReferenceCode/AcpiTables/Protocol/AcpiProtocolLib.inf b/ReferenceCode/AcpiTables/Protocol/AcpiProtocolLib.inf new file mode 100644 index 0000000..a4ed178 --- /dev/null +++ b/ReferenceCode/AcpiTables/Protocol/AcpiProtocolLib.inf @@ -0,0 +1,56 @@ +## @file +# Component description file for Acpi protocol module +# +#@copyright +# Copyright (c) 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# + + +[defines] +BASE_NAME = AcpiProtocolLib +COMPONENT_TYPE = LIBRARY + +[sources.common] + AcpiPlatformPolicy/AcpiPlatformPolicy.h + AcpiPlatformPolicy/AcpiPlatformPolicy.c + AcpiInfo/AcpiInfo.h + AcpiInfo/AcpiInfo.c + +[includes.common] + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EFI_SOURCE)/$(PROJECT_ACPI_ROOT) + +# +# Edk II Glue Library, some header are included by R9 header so have to include +# + $(EFI_SOURCE) + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + +[libraries.common] + EdkFrameworkProtocolLib + +[nmake.common] +C_STD_INCLUDE= diff --git a/ReferenceCode/AcpiTables/Protocol/AcpiProtocolLib.mak b/ReferenceCode/AcpiTables/Protocol/AcpiProtocolLib.mak new file mode 100644 index 0000000..5e84a5e --- /dev/null +++ b/ReferenceCode/AcpiTables/Protocol/AcpiProtocolLib.mak @@ -0,0 +1,55 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: AcpiProtocolLib.mak +# +# Description: +# +#<AMI_FHDR_END> +#************************************************************************* +all : AcpiProtocolLib + +$(AcpiProtocolLib_LIB) : AcpiProtocolLib + +AcpiProtocolLib : $(BUILD_DIR)\AcpiProtocolLib.mak AcpiProtocolLibBin + +$(BUILD_DIR)\AcpiProtocolLib.mak : $(AcpiProtocolLib_DIR)\$(@B).cif $(AcpiProtocolLib_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(AcpiProtocolLib_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +AcpiProtocolLib_INCLUDES =\ + $(EDK_INCLUDES) \ + $(EdkIIGlueLib_INCLUDES) + +AcpiProtocolLibBin : + $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\ + /f $(BUILD_DIR)\AcpiProtocolLib.mak all\ + "MY_INCLUDES=$(AcpiProtocolLib_INCLUDES)" \ + TYPE=LIBRARY + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/AcpiTables/Protocol/AcpiProtocolLib.sdl b/ReferenceCode/AcpiTables/Protocol/AcpiProtocolLib.sdl new file mode 100644 index 0000000..14f9503 --- /dev/null +++ b/ReferenceCode/AcpiTables/Protocol/AcpiProtocolLib.sdl @@ -0,0 +1,36 @@ +TOKEN + Name = "AcpiProtocolLib_SUPPORT" + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable AcpiProtocolLib support in Project" +End + +MODULE + Help = "Includes AcpiProtocolLib.mak to Project" + File = "AcpiProtocolLib.mak" +End + +PATH + Name = "AcpiProtocolLib_DIR" +End + +TOKEN + Name = "AcpiProtocolLib_LIB" + Value = "$(BUILD_DIR)\AcpiProtocolLib.lib" + TokenType = Expression + TargetMAK = Yes +End + +ELINK + Name = "AcpiProtocolLib_INCLUDES" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "/I$(AcpiProtocolLib_DIR)" + Parent = "AcpiProtocolLib_INCLUDES" + InvokeOrder = AfterParent +End
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/SampleCode/Lpit/LowPowerIdleTable.h b/ReferenceCode/AcpiTables/SampleCode/Lpit/LowPowerIdleTable.h new file mode 100644 index 0000000..9ef102b --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/Lpit/LowPowerIdleTable.h @@ -0,0 +1,68 @@ +/** @file + +This file defines the Low Power Idle Table definition, defined by +Intel IA-PC LPIT (Low Power Idle Table) Specification draft. + +@copyright +Copyright (c) 2013, Intel Corporation. All rights reserved.<BR> +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. +This file contains an 'Intel Peripheral Driver' and is +licensed for Intel CPUs and chipsets under the terms of your +license agreement with Intel or your vendor. This file may +be modified by the user, subject to additional terms of the +license agreement + +**/ + +#ifndef _LOW_POWER_IDLE_TABLE_H_ +#define _LOW_POWER_IDLE_TABLE_H_ + +// +// Include files +// +#include "Acpi2_0.h" + +// +// LPIT Definitions +// + +#define EFI_ACPI_LOW_POWER_IDLE_TABLE_REVISION 0x1 + +// +// Ensure proper structure formats +// +#pragma pack(1) + +typedef union _EFI_ACPI_LPI_STATE_FLAGS { + struct { + UINT32 Disabled :1; + UINT32 CounterUnavailable :1; + UINT32 Reserved :30; + }; + UINT32 AsUlong; +} EFI_ACPI_LPI_STATE_FLAGS, *PEFI_ACPI_LPI_STATE_FLAGS; + +// Only Mwait LPI here: + +typedef struct _EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR { + UINT32 Type; // offset: 0 + UINT32 Length; // offset: 4 + UINT16 UniqueId; // offset: 8 + UINT8 Reserved[2]; // offset: 10 + EFI_ACPI_LPI_STATE_FLAGS Flags; // offset: 12 + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EntryTrigger; // offset: 16 + UINT32 Residency; // offset: 28 + UINT32 Latency; // offset: 32 + EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResidencyCounter; // offset: 36 + UINT64 ResidencyCounterFrequency; //offset: 48 +} EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR; + +#pragma pack() + +#endif //_LOW_POWER_IDLE_TABLE_H_ diff --git a/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.act b/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.act new file mode 100644 index 0000000..82849de --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.act @@ -0,0 +1,110 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement + --*/ +/*++ + +Copyright (c) 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + + +Module Name: + +Lpit.act + +Abstract: + +This file contains a structure definition for the ACPI Low Power Idle Table +(LPIT). The contents of this file should only be modified +for bug fixes, no porting is required. The table layout is defined in +LowPowerIdleTable.h and the table contents are defined in Lpit.h. + +--*/ + + // + // Statements that include other files + // + +#include "Lpit.h" + + // + // Low Power Idle Table + // Please modify all values in Lpit.h only. + // + +EFI_ACPI_LOW_POWER_IDLE_TABLE Lpit = { + + // + // Header + // + + + EFI_ACPI_LOW_POWER_IDLE_TABLE_SIGNATURE, + sizeof (EFI_ACPI_LOW_POWER_IDLE_TABLE), + EFI_ACPI_LOW_POWER_IDLE_TABLE_REVISION , + + // + // Checksum will be updated at runtime + // + 0x00, + + // + // It is expected that these values will be updated at runtime + // + 'A', 'L', 'A', 'S', 'K', 'A', + + 0, + EFI_ACPI_OEM_LPIT_REVISION, + EFI_ACPI_CREATER_ID, + EFI_ACPI_CREATER_REVISION, + + + + // + // Descriptor + // + { + { + EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE, + sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR), + EFI_ACPI_HSW_LPI_AUDIO_ID, + {0,0}, + {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG}, // Flags + EFI_ACPI_HSW_LPI_TRIGGER, //EntryTrigger + EFI_ACPI_HSW_LPI_MIN_RES, //Residency + EFI_ACPI_HSW_LPI_LATENCY, //Latency + EFI_ACPI_HSW_LPI_RES_COUNTER, //ResidencyCounter + EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_TSC //Residency counter frequency + }, + { + EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE, + sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR), + EFI_ACPI_HSW_LPI_CS_ID, + {0,0}, + {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG}, // Flags + EFI_ACPI_HSW_LPI_TRIGGER, //EntryTrigger + EFI_ACPI_HSW_LPI_MIN_RES, //Residency + EFI_ACPI_HSW_LPI_LATENCY, //Latency + EFI_ACPI_HSW_LPI_RES_COUNTER, //ResidencyCounter + EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_TSC //Residency counter frequency + } + } + +}; + +VOID +main ( + VOID + ) + +{ +}
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.cif b/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.cif new file mode 100644 index 0000000..b9f6d91 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.cif @@ -0,0 +1,12 @@ +<component> + name = "lpit" + category = ModulePart + LocalRoot = "ReferenceCode\AcpiTables\SampleCode\Lpit\" + RefName = "lpit" +[files] +"LowPowerIdleTable.h" +"lpit.act" +"lpit.h" +"lpit.mak" +"lpit.sdl" +<endComponent> diff --git a/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.h b/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.h new file mode 100644 index 0000000..17e6eed --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.h @@ -0,0 +1,114 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement + --*/ +/*++ + +Copyright (c) 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + + +Module Name: + +Lpit.h + +Abstract: + +This file describes the contents of the ACPI Low Power Idle Table (LPIT). +All changes to the LPIT contents should be done in this file. + + + +--*/ + +#ifndef _LPIT_H_ +#define _LPIT_H_ + +// +// Statements that include other files +// + +#include "LowPowerIdleTable.h" + +// +// Defines for LPIT table, some are HSW ULT specific +// + + +// signature "LPIT" +#define EFI_ACPI_LOW_POWER_IDLE_TABLE_SIGNATURE 0x5449504c + +#define EFI_ACPI_OEM_LPIT_REVISION 0x00000000 +#define EFI_ACPI_CREATER_ID 0x2e494d41 //"AMI." +#define EFI_ACPI_CREATER_REVISION 0x5 +#define EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE 0x0 +#define EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG 0x0 +#define EFI_ACPI_LOW_POWER_IDLE_NO_RES_COUNTER_FLAG 0x2 +#define EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_TSC 0x0 + +// +// LPI state count (only 1 on HSW ULT) +// + +#define EFI_ACPI_HSW_LPI_STATE_COUNT 2 + +// +// LPI TRIGGER (HW C10 on HSW ULT) +// +#define EFI_ACPI_HSW_LPI_TRIGGER {0x7F,0x1,0x2,0x0,0x60} + +// +// LPI residency counter (HW C10 on HSW ULT) +// +#define EFI_ACPI_HSW_LPI_RES_COUNTER {0x7F,64,0x0,0x0,0x632} + +// +// LPI DUMMY COUNTER +// +#define EFI_ACPI_HSW_DUMMY_RES_COUNTER {0x0,0,0x0,0x0,0x0} + + +// +// LPI break-even residency in us (HW C10 on HSW ULT) +// +#define EFI_ACPI_HSW_LPI_MIN_RES 30000 + +// +// LPI latency in us (HW C10 on HSW ULT) +// +#define EFI_ACPI_HSW_LPI_LATENCY 3000 + +// +// LPI ID (HW C10 on HSW ULT) +// +#define EFI_ACPI_HSW_LPI_AUDIO_ID 0 + +// +// LPI ID (HW C10 on HSW ULT) +// +#define EFI_ACPI_HSW_LPI_CS_ID 1 + +// +// LPI ACPI table header +// + +#pragma pack(1) + +typedef struct _EFI_ACPI_LOW_POWER_IDLE_TABLE { + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR LpiStates[EFI_ACPI_HSW_LPI_STATE_COUNT]; +} EFI_ACPI_LOW_POWER_IDLE_TABLE; + +#pragma pack() + + +#endif //_LPIT_H_ diff --git a/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.mak b/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.mak new file mode 100644 index 0000000..5c78da2 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.mak @@ -0,0 +1,75 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: lpit.mak +# +# Description: MAke file to build Aptio ACPI ASL components +# +# +#<AMI_FHDR_END> +#************************************************************************* +all : Lpit + +Lpit : $(BUILD_DIR)\Lpit.ffS + +Lpit_Includes = \ + $(EDK_INCLUDES)\ + +Lpit_Defines = \ + /D"TIANO_RELEASE_VERSION=0x00080006"\ + +Lpit_ACPIS = \ + $(BUILD_DIR)\Lpit.acpi\ + +$(BUILD_DIR)\Lpit.asl: $(BUILD_DIR)\token.mak $(LPIT_DIR)\lpit.mak + copy << $@ +<< + +$(BUILD_DIR)\Lpit.exe : $(LPIT_DIR)\lpit.act $(LPIT_DIR)\lpit.h + @CL $(CFLAGS) $(Lpit_Defines) /Fo$(BUILD_DIR)\ $(Lpit_Includes) /TC $(LPIT_DIR)\lpit.act + @Link /OUT:$(BUILD_DIR)\Lpit.exe /NODEFAULTLIB /ENTRY:main $(BUILD_DIR)\Lpit.obj + +$(BUILD_DIR)\Lpit.acpi : $(BUILD_DIR)\Lpit.exe + $(GENACPI) $(BUILD_DIR)\Lpit.exe $(BUILD_DIR)\Lpit.acpi + +$(BUILD_DIR)\Lpit.sec : $(Lpit_ACPIS) + $(GENSECTION) -I $** -O $@ -S EFI_SECTION_RAW + +$(BUILD_DIR)\Lpit.ffs: $(BUILD_DIR)\Lpit.sec $(LPIT_DIR)\lpit.mak + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=9DD795EB-41E8-4591-8E63-5EF4AA33B908\ + TYPE=EFI_FV_FILETYPE_FREEFORM \ + FFS_CHECKSUM=1\ + RAWFILE=$(BUILD_DIR)\Lpit.sec FFSFILE=$(BUILD_DIR)\Lpit.ffs COMPRESS=0 NAME=Lpit + + + + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.sdl b/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.sdl new file mode 100644 index 0000000..188ddd8 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/Lpit/lpit.sdl @@ -0,0 +1,38 @@ +TOKEN + Name = "LPIT_SUPPORT" + Value = "1" + Help = "Main switch to enable LPIT support in Project" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Master = Yes +End + +PATH + Name = "LPIT_DIR" +End + +MODULE + Help = "Includes LPIT.mak to Project" + File = "lpit.mak" +End + +ELINK + Name = "$(BUILD_DIR)\Lpit.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(BUILD_DIR)\Lpit.asl" + Parent = "GENERIC_ASL" + InvokeOrder = AfterParent +End + +TOKEN + Name = "LPIT_GUID" + Value = "{0x9dd795eb, 0x41e8, 0x4591, 0x8e, 0x63, 0x5e, 0xf4, 0xaa, 0x33, 0xb9, 0x8}" + Help = "lpit Acpi Package" + TokenType = Expression + TargetH = Yes +End
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/BRRtd3.asl b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/BRRtd3.asl new file mode 100644 index 0000000..fd364d6 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/BRRtd3.asl @@ -0,0 +1,1250 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + +DefinitionBlock ( + "Rtd3.aml", + "SSDT", + 1, + "AcpiRef", + "BR0_Rtd3", + 0x1000 + ) +{ +#define BRRTD3 1 +Include("RTD3Common.asl") +#undef BRRTD3 + +External(BBR, IntObj) // BaskinRidge +External(BWC, IntObj) // Walnut Canyon +External(\_SB.PCI0.EHC2.HUBN.PR01.PR11, DeviceObj) +External(\_SB.PCI0.EHC2.HUBN.PR01.PR12, DeviceObj) +External(\_SB.PCI0.LPCB.GR19) +External(\_SB.PCI0.LPCB.GR0B) +External(\RT14) +External(\RT16) +External(\RT17) +External(\RT32) +External(\RT35) +External(\GL01) +External(\GIV1) +External(\GL00) +External(\GL04) +External(\GL05) +External(\GL06) +External(\GL08) +External(\SS11) +External(\SE11) +External(\SS13) +External(\SE13) +External(PFLV) +External(FDTP) + + +If(LOr(LAnd(LEqual(BID,BBR),LEqual(RTD3,1)),LAnd(LEqual(BID,BWC),LEqual(RTD3,1)))) { + + +// +// PCIe RTD3 - for slot#3 +// + +Scope (\_SB.PCI0.RP03) +{ + Name(WC, 0) +} + +Scope (\_SB.PCI0.RP03) +{ + Name(_PR0, Package(){PXP3}) + Name(_PR3, Package(){PXP3}) + Name(WKEN, 0) + + Method(_S0W, 0) + { // PMEs can be generated from D3cold + If(And(\_SB.OSCO, 0x04)) + { // OS comprehends D3cold, as described via \_SB._OSC + Return(4) + } Else { + Return(3) + } + } // End _S0W + + Method(_DSW, 3) + { + If(Arg1) + { // Entering Sx, need to disable WAKE# from generating runtime PME + Store(0, WKEN) + } Else { // Staying in S0 + If(LAnd(Arg0, Arg2)) // Exiting D0 and arming for wake + { // Set PME + Store(1, WKEN) + } Else { // Disable runtime PME, either because staying in D0 or disabling wake + Store(0, WKEN) + } + } + } // End _DSW + + + // Define a power resource for PCIe RP3 D0-D3hot + PowerResource(PXP3, 0, 0) + { + Name(OFFC, 0) // _OFF Counter + Name(ONC, 0) // _ON Counter + Name(PWRS, 0xFF) // current power status + + Method(_STA, 0) + { + If(LAnd(NAnd(GL00, 0x40), And(GL06, 0x80))){ + Return (1) + } Else { + Return (0) + } + + } + Method(_ON) // Turn on core power to PCIe Slot3 + { + Increment(ONC) + //Power ON for Slot3 + And(\GL00, 0x0BF, \GL00) + Sleep(PEP0) // Sleep for programmable delay + Store(1, PWRS) + Or(\GL06, 0x80, \GL06) + } + + Method(_OFF) // Turn off core power to PCIe Slot1 + { + Increment(OFFC) + //Power OFF for Slot3 + And(\GL06, 0x7F, \GL06) + Or(\GL00, 0x40, \GL00) + Store(1, \_SB.PCI0.RP03.LDIS) //Not required as power not removed at this time + Store(0, \_SB.PCI0.RP03.LDIS) //toggle link disable + + If(\_SB.PCI0.RP03.WKEN) { + Store(0, PWRS) + } + } + } // End PXP3 +} // End RP03 +/* +Scope(\_SB.PCI0.RP03.PXSX) +{ // PCIe Device beneath RP03 + Method(_S0W, 0) + { // PMEs can be generated from D3cold + If(And(\_SB.OSCO, 0x04)) + { // OS comprehends D3cold, as described via \_SB._OSC + Return(4) + } Else { + Return(3) + } + } // End _S0W +} // End PXSX +*/ +// +// PCIe RTD3 - for slot#4 +// +Scope (\_SB.PCI0.RP04) +{ + Name(_PR0, Package(){PXP4}) + Name(_PR3, Package(){PXP4}) + Name(WKEN, 0) + + Method(_S0W, 0) + { // PMEs can be generated from D3cold + If(And(\_SB.OSCO, 0x04)) + { // OS comprehends D3cold, as described via \_SB._OSC + Return(4) + } Else { + Return(3) + } + } // End _S0W + + Method(_DSW, 3) + { + If(Arg1) + { // Entering Sx, need to disable WAKE# from generating runtime PME + Store(0, WKEN) + } Else { // Staying in S0 + If(LAnd(Arg0, Arg2)) // Exiting D0 and arming for wake + { // Set PME + Store(1, WKEN) + } Else { // Disable runtime PME, either because staying in D0 or disabling wake + Store(0, WKEN) + } + } + } // End _DSW + + + // Define a power resource for PCIe RP4 D0-D3hot + PowerResource(PXP4, 0, 0) + { + Name(OFFC, 0) // _OFF Counter + Name(ONC, 0) // _ON Counter + Name(PWRS, 0xFF) // current power status + + Method(_STA, 0) + { + If(LAnd(NAnd(RT16, 1), And(RT17, 1))){ + Return (1) // + } else { + Return (0) + } + } + Method(_ON) // Turn on core power to PCIe Slot4 + { + Increment(ONC) + //Power ON for Slot4 + And(\RT16, 0x0, \RT16) //Apply power + Sleep(PEP0) // Sleep for programmable delay + Or(\RT17, 0x1, \RT17) //De-assert PERST# + Store(1, PWRS) + } + + Method(_OFF) // Turn off core power to PCIe Slot1 + { + Increment(OFFC) + //Power OFF for Slot4 + And(\RT17, 0x0, \RT17) + Or(\RT16, 0x1, \RT16) + Store(1, \_SB.PCI0.RP04.LDIS) + Store(0, \_SB.PCI0.RP04.LDIS) //toggle link disable + + If(\_SB.PCI0.RP04.WKEN) { + Store(0, PWRS) + Store(1, \SS11) //Clear SMI status + Store(1, \SE11) //Enable SMI + } + } + } // End PXP4 + +} // End RP04 +/* +Scope(\_SB.PCI0.RP04.PXSX) +{ // PCIe Device beneath RP04 + Method(_S0W, 0) + { // PMEs can be generated from D3cold + If(And(\_SB.OSCO, 0x04)) + { // OS comprehends D3cold, as described via \_SB._OSC + Return(4) + } Else { + Return(3) + } + } // End _S0W +} // End PXSX +*/ + +// +// PCIe RTD3 - for slot#5 +// +Scope (\_SB.PCI0.RP05) +{ + Name(_PR0, Package(){PXP5}) + Name(_PR3, Package(){PXP5}) + Name(WKEN, 0) + + Method(_S0W, 0) + { // PMEs can be generated from D3cold + If(And(\_SB.OSCO, 0x04)) + { // OS comprehends D3cold, as described via \_SB._OSC + Return(4) + } Else { + Return(3) + } + } // End _S0W + + Method(_DSW, 3) + { + If(Arg1) + { // Entering Sx, need to disable WAKE# from generating runtime PME + Store(0, WKEN) + } Else { // Staying in S0 + If(LAnd(Arg0, Arg2)) // Exiting D0 and arming for wake + { // Set PME + Store(1, WKEN) + } Else { // Disable runtime PME, either because staying in D0 or disabling wake + Store(0, WKEN) + } + } + } // End _DSW + + + // Define a power resource for PCIe RP5 D0-D3hot + PowerResource(PXP5, 0, 0) + { + Name(OFFC, 0) // _OFF Counter + Name(ONC, 0) // _ON Counter + Name(PWRS, 0xFF) // current power status + + Method(_STA, 0) + { + If(LAnd(NAnd(RT32, 1), And(RT35, 1))){ + Return (1) + } else { + Return (0) + } + + } + Method(_ON) // Turn on core power to PCIe Slot1 + { + P8XH(0,0x11) + P8XH(1,0x50) + Increment(ONC) + //Power ON for Slot5 + And(\RT32, 0x0, \RT32) + Store(1, PWRS) + Sleep(PEP0) // Sleep for programmable delay + Or(\RT35, 0x1, \RT35) + } + + Method(_OFF) // Turn off core power to PCIe Slot5 + { + Increment(OFFC) + //Power OFF for Slot5 + And(\RT35, 0x0, \RT35) + Or(\RT32, 0x1, \RT32) + + Store(1, \_SB.PCI0.RP05.LDIS) + Store(0, \_SB.PCI0.RP05.LDIS) //toggle link disable + Store(0, PWRS) + Sleep(PEP3) // user selectable delay + If(\_SB.PCI0.RP05.WKEN) { + Store(1, \SS13) //Clear SMI status + Store(1, \SE13) //Enable SMI + } + } + } // End PXP5 + +} // End RP05 +/* For Debug +Scope(\_SB.PCI0.RP05.PXSX) +{ // PCIe Device beneath RP05 + Method(_S0W, 0) + { // PMEs can be generated from D3cold + If(And(\_SB.OSCO, 0x04)) + { // OS comprehends D3cold, as described via \_SB._OSC + Return(4) + } Else { + Return(3) + } + } // End _S0W +} // End PXSX +*/ + +// +// GPE Event Handler +// + +Scope(\_GPE) { + // + // GPIO19 routed to GPE0b[25] => 32+25 = 57(0x39) = PCIE slot 3 wake event + // + + Method(_L39) { + // PCIe WAKE# + Increment(\_SB.PCI0.RP03.WC) + If(\_SB.PCI0.RP03.WKEN){ + Store(0, \_SB.PCI0.LPCB.GR19) //Mask SCI - to stop SCI flooding + Notify(\_SB.PCI0.RP03, 0x02) // DeviceWake + } + } + + // + // GPI03 = SMSC 1007 nIO_SMI routed to PCH GPIO 3 + // + Method(_L13) { + /* + If(LAnd(\_SB.PCI0.RP04.WKEN, SS11)){ + Store(0, SE11) + Store(1, SS11) + Notify(\_SB.PCI0.RP04, 0x02) // DeviceWake + } + If(LAnd(\_SB.PCI0.RP05.WKEN, SS13)){ + Store(0, SE13) + Store(1, SS13) + Notify(\_SB.PCI0.RP05, 0x02) // DeviceWake + } + */ + } + // + // GPIO11 - ZPODD DA + // + Method(_L1B){ + // + // Do nothing if Desktop platform + // + If(LEqual(PFLV,FDTP)) { + Return () + } + + // + // Toggle GPI invert + // + If(LEqual(And(\GL01, 0x08),0x08)) { // GPI11 is high + Or(\GIV1, 0x08, \GIV1) //GP_INV should be set to trigger low + }Else { + And(\GIV1, 0xF7, \GIV1) //GP_INV should be set to trigger high + } + + // Only do this if ZPODD not under _DSM control + If(LEqual(\_SB.PCI0.SAT0.UDSM, Zero)) { + // + // Notify OSPM + // + //If(WKEN) { // _DSW called to enable ODD to generate a wake event + //send notification for Port 2 + Notify(\_SB.PCI0.SAT0.PRT2, 2) // Device Wake to Device (Windows) + //} + } Else { + + // Drive GPIO68 to High to power on device. + // + Or(\GL08, 0x10, \GL08) + // + // Notify the OSPM + // + Notify(\_SB.PCI0.SAT0, 0x82) + } // \_SB.PCI0.SAT0.UDSM + Return () + } +} + +// +// AHCI RTD3 +// +Scope(\_SB.PCI0.SAT0) { + // + // _DSM Device Specific Method supporting AHCI LPM/DEVSLP + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // Arg3: Package Parameters + // + Name(DRV, 0) // Storage for _DSM Arg3 parameter 0 + Name(PWR, 0) // Storage for _DSM Arg3 parameter 1 + Name(UDSM, 0) // Use _DSM for ZPODD control. 0 = Disabled; 1 = Enabled + + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + If (LEqual(Arg0, ToUUID ("E4DB149B-FCFE-425b-A6D8-92357D78FC7F"))) { + // + // Switch by function index + // + Switch (Arg2) { + Case (0) { + // Standard query - A bitmask of functions supported + // Supports function 0-3 + Name(RBUF, Buffer(1){0x00}) + CreateByteField (RBUF, 0, SFUN) + Store (0x0F, SFUN) + Return (RBUF) + } + Case (1) { + // Query Device IDs (Addresses) of children where drive power and/or PHYSLP are supported + //Return (Package(){0x0000FFFF, 0x0001FFFF, 0x0002FFFF}) //Debug - All Ports supports Link control + Return (Package(){0x0000FFFF}) //Only Port0 in MintSpring supports Link control + + } + // + // Control power to device. + // + Case (2) { + Store(ToInteger(DerefOf(Index(Arg3, Zero))), DRV) + Store(ToInteger(DerefOf(Index(Arg3, One))), PWR) + + Switch(DRV){ + Case (0x0000FFFF){ + If(PWR){ // Applying Power + // Turn on drive and link power to drive at Port 0 + Store(1, RT14) // De assert physlp -> Link ON, LED ON + ^PRT0.P0PR._ON() + } Else { // Remove Link Power + Store(0, RT14) // Assert physlp -> Link OFF, LED OFF + } + } + //We don't have Link power control in Mintspring. so the code below can be removed. + Case (0x0001FFFF){ + If(PWR){ // Applying Power + // Turn on drive and link power to drive at Port 1 + \_SB.PCI0.SAT0.PRT1.P1PR._ON() + } Else { // Remove Link Power + NoOp // No link power control on these ports. + } + } + Case (0x0002FFFF){ + // Turn on drive and link power to drive at Port 2 + If(PWR){ // Applying Power + // Turn on drive and link power to drive at Port 2 + //^PRT2.P2PR._ON() + } Else { // Remove Link Power + NoOp // No link power control on these ports + } + } + Case (Ones){ + // Turn on drive and link power to all drives + If(PWR){ // Applying Power + Store(1, RT14) // De assert physlp -> Link ON, LED ON (Link might be disabled) + ^PRT0.P0PR._ON() + \_SB.PCI0.SAT0.PRT1.P1PR._ON() + ^PRT2.P2PR._ON() + } + } + } + Return (0) + } + // + // Current status of Device/Link of Port + // + Case (3){ + Store(ToInteger(DerefOf(Index(Arg3, Zero))), DRV) + Switch(DRV){ + Case (0x0000FFFF){ + Store(ShiftRight(NAnd(GL04, 0x04), 2), Local0) // Bit0 => Device power state + If(LEqual(RT14,1)){ //If Link ON + Or(Local0, 2, Local0) //Bit1 => Link power state + } + Return (Local0) + } + + Case (0x0001FFFF){ + Store(ShiftRight(NAnd(GL04, 0x08), 2), Local0) // Bit0 => Device power state + Or(Local0, 2, Local0) //Bit1 => Link power state + Return (Local0) + } + + Case (0x0002FFFF){ + Store(ShiftRight(And(GL08, 0x010), 2), Local0) // Bit0 => Device power state + Or(Local0, 2, Local0) //Bit1 => Link power state + Return (Local0) + } + + Default { + Return (Ones) + } + } + } + Default { + Return (0) + } + } //Switch (Arg2) + } Else { + Return (0) + } + } + + // D0 Method for SATA HBA(for debug) + Method(_PS0,0,Serialized) + { + } + + // D3 Method for SATA HBA(for debug) + Method(_PS3,0,Serialized) + { + } + + Scope(PRT0) { + Name(_PR0, Package(){P0PR}) + Name(_PR3, Package(){P0PR}) + + + PowerResource(P0PR, 0, 0){ // SATA_PWR_EN#0 is PCH GPIO34 + Method(_STA){ + If(And(GL04, 0x04)) { + Return(0x00) + } Else { + Return(0x01) + } + } + + Method(_ON, 0) + { // Turn on the PFET + And(GL04, 0xfb, GL04) + // Delay for power ramp + Sleep(16) + } + + Method(_OFF, 0) + { // Turn off the PFET + // TODO: when removing power, need to ensure DEVSLP is either deasserted or reverts to an input + //(safer, no need to keep track if it was asserted before) + Store(1, RT14) // De assert physlp -> Link ON, LED ON + Or(GL04, 0x04, GL04) + } + } // End P0PR + } // End PRT0 + + Scope(PRT1) { + + Name(_PR0, Package(){P1PR}) + Name(_PR3, Package(){P1PR}) + + + PowerResource(P1PR, 0, 0){ // SATA_PWR_EN#0 is PCH GPIO35 on Emerald Lake + Method(_STA){ +// Or(GU04, 8, GU04) // GPIO init code incorrect- make this GPIO non-native + If(And(GL04, 0x08)) { + Return(0x00) + } Else { + Return(0x01) + } + } + + Method(_ON, 0) + { // Turn on the PFET + And(GL04, 0xf7, GL04) + // Delay for power ramp + Sleep(16) + } + + Method(_OFF, 0) + { // Turn off the PFET + Or(GL04, 8, GL04) + } + } // End P1PR + } //End PRT1 + + Scope(PRT2) { // Port 2- Cable Connect power + // + // _DSM Device Specific Method supporting SATA ZPODD function + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // Arg3: Package Parameters + // + Method (_DSM, 4, NotSerialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + If (LEqual(Arg0, ToUUID ("bdfaef30-aebb-11de-8a39-0800200c9a66"))) { + // + // Switch by function index + // + Switch (ToInteger(Arg2)) { + // + // Standard query - A bitmask of functions supported + // Supports function 0-5 + // + Case (0) { + switch(ToInteger(Arg1)) { + case(1) { + // + // Return - 0 (No Functions supported) for Desktop Platforms + // + If(LEqual(PFLV,FDTP)) { + Return (Buffer () {0}) + } + Return (Buffer () {0xF}) + } + Default {Return (Buffer () {0})} + } + } + // + // Enable ZPODD feature + // + Case (1) { + // + // Enable Power ON/OFF + // + // Function 1: Enable Power OFF/ON. Enables the Power Off/ON hardware in the system. + // When called, the BIOS is informed that the host software is using this interface. + If(LEqual(\_SB.PCI0.SAT0.UDSM, Zero)){ //if Ownership not acquired + Store (1, \_SB.PCI0.SAT0.UDSM) // Indicate ZPODD _DSM control enabled + } + Store(2, \_SB.PCI0.LPCB.GR0B) // Enable SCI (for ZPODD wake) in LPC register + Return (1) + } + // + // Power Off Device + // + Case (2) { + // + // Drive GPIO68 to low to power off device. + // + And(\GL08, 0xEF, \GL08) + Return (1) + } + // + // Power ON Device + // + Case (3) { + Or(\GL08, 0x10, \GL08) + Sleep(16) // To turn the FET + Return (1) + } + Default { + Return (0) + } + } + } Else { + Return (0) + } + } + Name(_PR0, Package(){P2PR}) + Name(_PR3, Package(){P2PR}) + + Name(WKEN, 0) // Device on this port wake enabled? + + Method(_S0W, 0) + { // PMEs can be generated from D3cold + Store(2, \_SB.PCI0.LPCB.GR0B) // Enable SCI (for ZPODD wake) in LPC register + If(And(\_SB.OSCO, 0x04)) + { // OS comprehends D3cold, as described via \_SB._OSC + Return(4) + } Else { + Return(3) + } + } // End _S0W + + Method(_DSW, 3) + { + If(Arg1) + { // Entering Sx, need to disable DA from generating runtime PME + Store(0, WKEN) + } Else { // Staying in S0 + If(LAnd(Arg0, Arg2)) // Exiting D0 and arming for wake + { // Set WKEN to allow _OFF to enable the wake event + Store(1, WKEN) + } Else { // Clear WKEN to allow _OFF to enable the wake event, + // either because staying in D0 or disabling wake + Store(0, WKEN) + } + } + } // End _DSW + + Method(_PRW, 0) { Return(GPRW(0x13, 4)) } // can wakeup from S4 state + + PowerResource(P2PR, 0, 0){ + Name(_STA, 0x01) + + Method(_ON, 0) + { + Store(0x01, _STA) + Or(GL08, 0x10, GL08) + Sleep(16) // To turn the FET + } + + Method(_OFF, 0) + { + // + // Drive GPIO68 to low to power off device. + // + And(GL08, 0xEF, GL08) + Store(0, _STA) + } + } // End P2PR + } //End PRT2 + + PowerResource(V0PR, 0, 0) + { // Power Resource Aggregate for RAID volume 0 + Name(_STA, 0x01) + Name(PMAP, 0) + + Method(_ON, 0) + { // Turn on the PFET + If(Not(_STA)){ + Store(0x01, _STA) + If(And(PMAP, 0x01)) + { // Turn On Port 0 Power + And(GL04, 0xfb, GL04) + } + If(And(PMAP, 0x02)) + { // Turn On Port 1 Power + And(GL04, 0xf7, GL04) + } + If(And(PMAP, 0x04)) + { // Turn On Port 2 Power + Or(GL08, 0x10, GL08) + } + // Delay for power ramp + Sleep(16) + } + } + + Method(_OFF, 0) + { // Turn off the PFET + If(_STA){ + Store(0x01, _STA) + If(And(PMAP, 1)) + { // Turn Off Port 0 Power + Or(GL04, 0x04, GL04) + } + If(And(PMAP, 2)) + { // Turn Off Port 1 Power + Or(GL04, 0x08, GL04) + } + If(And(PMAP, 4)) + { // Turn Off Port 2 Power + And(GL08, 0xEF, GL08) + } + } + } + } // End V0PR + + PowerResource(V1PR, 0, 0) + { // Power Resource Aggregate for RAID volume 1 + Name(_STA, 0x01) + Name(PMAP, 0) + + Method(_ON, 0) + { // Turn on the PFET + If(Not(_STA)){ + Store(0x01, _STA) + If(And(PMAP, 0x01)) + { // Turn On Port 0 Power + And(GL04, 0xfb, GL04) + } + If(And(PMAP, 0x02)) + { // Turn On Port 1 Power + And(GL04, 0xf7, GL04) + } + If(And(PMAP, 0x04)) + { // Turn On Port 2 Power + Or(GL08, 0x10, GL08) + } + // Delay for power ramp + Sleep(16) + } + } + + Method(_OFF, 0) + { // Turn off the PFET + If(_STA){ + Store(0x01, _STA) + If(And(PMAP, 1)) + { // Turn Off Port 0 Power + Or(GL04, 0x04, GL04) + } + If(And(PMAP, 2)) + { // Turn Off Port 1 Power + Or(GL04, 0x08, GL04) + } + If(And(PMAP, 4)) + { // Turn Off Port 2 Power + And(GL08, 0xEF, GL08) + } + } + } + } // End V1PR + + PowerResource(V2PR, 0, 0) + { // Power Resource Aggregate for RAID volume 2 + Name(_STA, 0x01) + Name(PMAP, 0) + + Method(_ON, 0) + { // Turn on the PFET + If(Not(_STA)){ + Store(0x01, _STA) + If(And(PMAP, 0x01)) + { // Turn On Port 0 Power + And(GL04, 0xfb, GL04) + } + If(And(PMAP, 0x02)) + { // Turn On Port 1 Power + And(GL04, 0xf7, GL04) + } + If(And(PMAP, 0x04)) + { // Turn On Port 2 Power + Or(GL08, 0x10, GL08) + } + // Delay for power ramp + Sleep(16) + } + } + + Method(_OFF, 0) + { // Turn off the PFET + If(_STA){ + Store(0x01, _STA) + If(And(PMAP, 1)) + { // Turn Off Port 0 Power + Or(GL04, 0x04, GL04) + } + If(And(PMAP, 2)) + { // Turn Off Port 1 Power + Or(GL04, 0x08, GL04) + } + If(And(PMAP, 4)) + { // Turn Off Port 2 Power + And(GL08, 0xEF, GL08) + } + } + } + } // End V2PR + + Device(VOL0) { + Name(_ADR,0x0080FFFF) // RAID Volume 0 + + Name(_PR0, Package(){V0PR}) + Name(_PR3, Package(){V0PR}) + + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + If (LEqual(Arg0, ToUUID ("E03E3431-E510-4fa2-ABC0-2D7E901245FE"))) { + // + // Switch by function index + // + Switch (Arg2) { + + Case (0) { + // Standard query - A bitmask of functions supported + // Supports function 0-3 + Name(RBUF, Buffer(1){0x00}) + CreateByteField (RBUF, 0, SFUN) + Store (0x03, SFUN) + Return (RBUF) + } + + Case (1) {// Assign ports to this RAID volume + Store(DeRefOf(Index(Arg3,0)), ^^V0PR.PMAP) // Assign port mapping to the volume's power resource + Return(Package(0){}) + } + Default { + Return (0) + } + } //Switch (Arg2) + } Else { + Return (0) + } + } + } + + Device(VOL1) { + Name(_ADR,0x0081FFFF) // RAID Volume 1 + + Name(_PR0, Package(){V1PR}) + Name(_PR3, Package(){V1PR}) + + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + If (LEqual(Arg0, ToUUID ("E03E3431-E510-4fa2-ABC0-2D7E901245FE"))) { + // + // Switch by function index + // + Switch (Arg2) { + + Case (0) { + // Standard query - A bitmask of functions supported + // Supports function 0-3 + Name(RBUF, Buffer(1){0x00}) + CreateByteField (RBUF, 0, SFUN) + Store (0x03, SFUN) + Return (RBUF) + } + + Case (1) {// Assign ports to this RAID volume + Store(DeRefOf(Index(Arg3,0)), ^^V1PR.PMAP) // Assign port mapping to the volume's power resource + Return(Package(0){}) + } + Default { + Return (0) + } + } //Switch (Arg2) + } Else { + Return (0) + } + } + } + + Device(VOL2) { + Name(_ADR,0x0082FFFF) // RAID Volume 2 + + Name(_PR0, Package(){V2PR}) + Name(_PR3, Package(){V2PR}) + + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + If (LEqual(Arg0, ToUUID ("E03E3431-E510-4fa2-ABC0-2D7E901245FE"))) { + // + // Switch by function index + // + Switch (Arg2) { + + Case (0) { + // Standard query - A bitmask of functions supported + // Supports function 0-3 + Name(RBUF, Buffer(1){0x00}) + CreateByteField (RBUF, 0, SFUN) + Store (0x03, SFUN) + Return (RBUF) + } + + Case (1) {// Assign ports to this RAID volume + Store(DeRefOf(Index(Arg3,0)), ^^V2PR.PMAP) // Assign port mapping to the volume's power resource + Return(Package(0){}) + } + Default { + Return (0) + } + } //Switch (Arg2) + } Else { + Return (0) + } + } + } +} + + Scope(\_SB.PCI0.EHC2){ + Method(_S0W, 0) + { // PMEs can be generated from D3(hot) + Return(3) + } // End _S0W + + // D0 Method for EHCI2 Host Controller + Method(_PS0,0,Serialized) + { + } + + // D3 Method for EHCI2 Host Controller + Method(_PS3,0,Serialized) + { + Store(1, \_SB.PCI0.EHC2.PMES) //Clear PME status + Store(1, \_SB.PCI0.EHC2.PMEE) //Enable PME + } + } + + Scope(\_SB.PCI0.XHC){ + Method(_S0W, 0) + { // PMEs can be generated from D3(hot) + Return(3) + } // End _S0W + + // D0 Method for xHCI Host Controller + Method(_PS0,0,Serialized) + { + } + + // D3 Method for xHCI Host Controller + Method(_PS3,0,Serialized) + { + Store(1, \_SB.PCI0.XHC.PMES) //Clear PME status + Store(1, \_SB.PCI0.XHC.PMEE) //Enable PME + } + } + + Scope(\_SB.PCI0.XHC.RHUB.HS01){ + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF),0x01)) + { + Return(Package(){\PX01}) + } + Else + { + Return(Package() {}) + } + } // End of Method _PR0 + Method(_PR2, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF),0x01)) + { + Return(Package(){\PX01}) + } + Else + { + Return(Package() {}) + } + } // End of Method _PR2 + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF),0x01)) + { + Return(Package(){\PX01}) + } + Else + { + Return (Package() {}) + } + } // End of Method _PR3 + } + + Scope(\_SB.PCI0.XHC.RHUB.HS02){ + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF0),0x10)) + { + Return(Package(){\PX01}) + } + Else + { + Return(Package() {}) + } + } // End of Method _PR0 + Method(_PR2, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF0),0x10)) + { + Return(Package(){\PX01}) + } + Else + { + Return(Package() {}) + } + } // End of Method _PR2 + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF0),0x10)) + { + Return(Package(){\PX01}) + } + Else + { + Return (Package() {}) + } + } // End of Method _PR3 + + } + + Scope(\_SB.PCI0.XHC.RHUB.SSP1){ + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF),0x02)) + { + Return(Package(){\PX01}) + } + Else + { + Return(Package() {}) + } + } + Method(_PR2, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF),0x02)) + { + Return(Package(){\PX01}) + } + Else + { + Return(Package() {}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF),0x02)) + { + Return(Package(){\PX01}) + } + Else + { + Return (Package() {}) + } + }// End of method _PR3 + } // End of Scope(\_SB.PCI0.XHC.RHUB.SSP1) + + Scope(\_SB.PCI0.XHC.RHUB.SSP2){ + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF0),0x20)) + { + Return(Package(){\PX01}) + } + Else + { + Return(Package() {}) + } + } + Method(_PR2, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF0),0x20)) + { + Return(Package(){\PX01}) + } + Else + { + Return(Package() {}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(XHPR,0xF0),0x20)) + { + Return(Package(){\PX01}) + } + Else + { + Return (Package() {}) + } + }// End of method _PR3 + }//Scope(\_SB.PCI0.XHC.RHUB.SSP2) + + Scope(\_SB.PCI0.EHC2.HUBN.PR01.PR11){ + Name(_PR0, Package(){\PX89}) + Name(_PR2, Package(){\PX89}) + Name(_PR3, Package(){\PX89}) + + } + + Scope(\_SB.PCI0.EHC2.HUBN.PR01.PR12){ + Name(_PR0, Package(){\PX89}) + Name(_PR2, Package(){\PX89}) + Name(_PR3, Package(){\PX89}) + + } + + Scope(\) { + PowerResource(PX01, 0, 0){ //Common power rail for USB2.0 ports 0,1 /USB3.0 ports 1,2 - GPIO 40 + Method(_STA){ + If(And(GL05, 0x02)) { //GPIO41 => GL05 BIT0 + Return(0x01) + } Else { + Return(0x00) + } + } + + Method(_ON, 0) + { // Turn on + Or(GL05, 2, GL05) + // Delay for power ramp + Sleep(16) + } + + Method(_OFF, 0) + { // Turn off + And(GL05, 0xfd, GL05) + } + } // End PX01 + + PowerResource(PX89, 0, 0){ //Common power rail for USB2.0 ports 8, 9 (stacked with LAN conn; EHCI) - GPIO 14 + Method(_STA){ + If(And(GL01, 0x40)) { //GPI14 => GL01 BIT6 + Return(0x01) + } Else { + Return(0x00) + } + } + + Method(_ON, 0) + { // Turn on + Or(GL01, 0x40, GL01) + // Delay for power ramp + Sleep(16) + } + + Method(_OFF, 0) + { // Turn off + And(GL01, 0x0bf, GL01) + } + } // End PX89 + +} //Scope(\) + +} //If(LAnd(LEqual(BID,BBR),LEqual(RTD3,1))) + +} // End SSDT
\ No newline at end of file diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/RTD3Common.asl b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/RTD3Common.asl new file mode 100644 index 0000000..9f8857e --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/RTD3Common.asl @@ -0,0 +1,178 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + +External(\_SB.OSCO) +External(\_SB.PCI0,DeviceObj) +External(\_SB.PCI0.SAT0, DeviceObj) +External(\_SB.PCI0.SAT0.PRT0, DeviceObj) +External(\_SB.PCI0.SAT0.PRT1, DeviceObj) +External(\_SB.PCI0.SAT0.PRT2, DeviceObj) + +External(\_SB.PCI0.RP01, DeviceObj) +External(\_SB.PCI0.RP03, DeviceObj) +External(\_SB.PCI0.RP04, DeviceObj) +External(\_SB.PCI0.RP05, DeviceObj) +External(\_SB.PCI0.RP06, DeviceObj) +External(\_SB.PCI0.RP01.LDIS) +External(\_SB.PCI0.RP03.LDIS) +External(\_SB.PCI0.RP04.LDIS) +External(\_SB.PCI0.RP05.LDIS) +External(\_SB.PCI0.RP06.LDIS) +External(\_SB.PCI0.RP01.L23E) +External(\_SB.PCI0.RP03.L23E) +External(\_SB.PCI0.RP04.L23E) +External(\_SB.PCI0.RP05.L23E) +External(\_SB.PCI0.RP06.L23E) +External(\_SB.PCI0.RP01.L23R) +External(\_SB.PCI0.RP03.L23R) +External(\_SB.PCI0.RP04.L23R) +External(\_SB.PCI0.RP05.L23R) +External(\_SB.PCI0.RP06.L23R) +External(\_SB.PCI0.RP01.LEDM) +External(\_SB.PCI0.RP03.LEDM) +External(\_SB.PCI0.RP04.LEDM) +External(\_SB.PCI0.RP05.LEDM) +External(\_SB.PCI0.RP06.LEDM) +External(\_SB.PCI0.RP01.LASX) +External(\_SB.PCI0.RP03.LASX) +External(\_SB.PCI0.RP04.LASX) +External(\_SB.PCI0.RP05.LASX) +External(\_SB.PCI0.RP06.LASX) +External(\CKEN) +External(\PMFS) + +External(\_SB.PCI0.XHC, DeviceObj) +External(\_SB.PCI0.XHC.PMES) +External(\_SB.PCI0.XHC.PMEE) +External(\_SB.PCI0.XHC.MEMB) +External(\_SB.PCI0.EHC2, DeviceObj) +External(\_SB.PCI0.EHC2.PMES) +External(\_SB.PCI0.EHC2.PMEE) +External(\_SB.PCI0.XHC.RHUB, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.SSP1, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.SSP2, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.HS01, DeviceObj) //xHCI HSP port 1 +External(\_SB.PCI0.XHC.RHUB.HS02, DeviceObj) //xHCI HSP port 2 +External(\_SB.PCI0.I2C0, DeviceObj) //I2C Controller +External(\_SB.PCI0.I2C0.SHUB, DeviceObj) // Sensor hub + +External(PEP0) +External(PEP3) +External(XHPR) +External(RCG0, IntObj) // RTD3 Config Setting(BIT0:ZPODD,BIT1:USB Camera Port4, BIT2/3:SATA Port3) +External(\GPRW, MethodObj) +External(P8XH, MethodObj) +External(BID, IntObj) // BoardId +External(RTD3, IntObj) +//AMI_OVERRIDE --- Change name from XDST to XHDS to fix that the system has BsOD issue. It is due to the name(XDST) is conflict with AMI Aptio definition name. >> +//External(XHDS, IntObj) +//External(XDST, IntObj) +//AMI_OVERRIDE --- << +// +// Externs common to ULT0RTD3.asl and FFRDRTD3.asl and exclude for BRRTD3.asl +// +#ifndef BRRTD3 +External(\_SB.GP2A, MethodObj) +External(\_SB.GP2B, MethodObj) +External(\_SB.GP2N, MethodObj) +External(\_SB.RDGP, MethodObj) +External(\_SB.WTGP, MethodObj) +External(\_SB.WTIN, MethodObj) +External(\_SB.RDGI, MethodObj) + +External(\_SB.PCI0.HDEF, DeviceObj) +External(\_SB.PCI0.ADSP, DeviceObj) +External(\_SB.PCI0.I2C1, DeviceObj) //I2C1 Controller +External(\_SB.PCI0.I2C1.TPD1, DeviceObj) // Touch pad +External(\_SB.PCI0.I2C1.TPL0, DeviceObj) // Touch panel +External(\_SB.PCI0.I2C1.TPD0, DeviceObj) // Touch pad +External(\_SB.PCI0.LPCB.H_EC.SPT2) // SATA_CABLE_PWR_EN bit in EC +External(\_SB.PCI0.LPCB.H_EC.ECMD, MethodObj) // EC Command method +External(\_SB.PCI0.LPCB.H_EC.ECAV, IntObj) // EC Driver loaded flag +External(\_SB.PCI0.LPCB.H_EC.ECRD, MethodObj) // EC Read Method +External(\_SB.PCI0.LPCB.H_EC.ECWT, MethodObj) // EC Write Method +External(\_SB.PCI0.SAT0.PRT3, DeviceObj) + +External(\UAMS) +External(RIC0,FieldUnitObj) +External(SDS0,FieldUnitObj) +External(SDS1,FieldUnitObj) +External(IC1D,FieldUnitObj) +External(IC1S,FieldUnitObj) +External(IC0D,FieldUnitObj) +External(I20D,FieldUnitObj) +External(I21D,FieldUnitObj) +External(AUDD,FieldUnitObj) +External(HDAD,FieldUnitObj) +External(SHSB,FieldUnitObj) +External(VRSD,FieldUnitObj) +External(VRRD,FieldUnitObj) + +External(\GO08) +External(\GO45) +External(\GO51) +External(\GS08) +External(\GS45) +External(\GS51) + +Name(LONT, 0) // Last ON Timestamp: The time stamp of the last RTDpower resource _ON method evaluation + +// +// SGON - Staggering ON Method with VR Staggering delay +// Staggering ON Method with VR Staggering (VRSD) delay. Sleep the extra remaining amount of time if necessary. +// Update the global running timer of LONT (Last ON mehtod timestamp) +// +// Arguments: +// Arg0 - GPIO Pin number to toggle power on +// Arg1 - GPIO Value, 0: Active Low, 1: Active High +// +// Return Value: +// Zero - VR staggering is skipped +// One - VR staggering is performed +// +Method(SGON, 2, Serialized) +{ + // Check if device is already driven to power on + If(LNotEqual(\_SB.RDGP(Arg0), Arg1)) { + // Check for VR staggering + Divide(Subtract(Timer(), \LONT), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + If(LLess(Local0, \VRSD)) { //Do not sleep if already past the delay requirement + // Delay for power ramp using Timer Based Sleep + Sleep(Subtract(\VRSD, Local0)) + } + + \_SB.WTGP(Arg0, Arg1) // Drive GPIO to power on device + + Store(Timer(), \LONT) // Update the global Last ON Method Timer + + Return(One) // VR staggering is performed + } Else { + Return(Zero) // VR staggering is skipped + } +} + +#endif + diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/RTD3Pcie.asl b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/RTD3Pcie.asl new file mode 100644 index 0000000..d560c2c --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/RTD3Pcie.asl @@ -0,0 +1,165 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + Name(WKEN, 0) + + Method(_S0W, 0) + { // PMEs can be generated from D3hot + Return(3) //For ULT + } // End _S0W + + Method(_DSW, 3) + { + If(Arg1) + { // Entering Sx, need to disable WAKE# from generating runtime PME + Store(0, WKEN) + } Else { // Staying in S0 + If(LAnd(Arg0, Arg2)) // Exiting D0 and arming for wake + { // Set PME + Store(1, WKEN) + } Else { // Disable runtime PME, either because staying in D0 or disabling wake + Store(0, WKEN) + } + } + } // End _DSW + + // Define a power resource for PCIe RP D0-D3hot + PowerResource(PXP, 0, 0) + { + Method(_STA, 0) + { + if(LAND(LEqual(\_SB.RDGP(PWRG),PONP), LEqual(\_SB.RDGP(RSTG),RONP))){ + Return (1) + } Else { + Return (0) + } + } + Method(_ON) // Turn on core power to PCIe Slot + { + + // Power ON for Slot + // Dont enable power for NGFF because NGFF only has AUX power + If(LNot(NGFF)) { + \_SB.WTGP(PWRG,PONP) + Sleep(PEP0) // Sleep for programmable delay + } + + // Enable PCIe Src Clock + While(LEqual(PMFS,1)){ // PMC message serviced? + Stall(10) + } + Store(Or(ShiftLeft(SCLK, 24), ShiftLeft(SCLK, 16)), Local1) // Set Bit and Mask + Or(Local1, 4, Local1) // OCKEN command + Store(Local1, \CKEN) // Enable Source Clock + While(LEqual(PMFS,1)){ // PMC message serviced? + Stall(10) + } + + \_SB.WTGP(RSTG,RONP) // De-Assert Reset Pin + Store(1, L23R) // Set L23_Rdy to Detect Transition (L23R2DT) + Sleep(16) + Store(0, Local0) + // Wait up to 12 ms for transition to Detect + While(L23R) { + If(Lgreater(Local0, 4)) // Debug - Wait for 5 ms + { + Break + } + Sleep(16) + Increment(Local0) + } + // Once in Detect, wait up to 124 ms for Link Active (typically happens in under 70ms) + // Worst case per PCIe spec from Detect to Link Active is: + // 24ms in Detect (12+12), 72ms in Polling (24+48), 28ms in Config (24+2+2+2+2) + Store(0, Local0) + While(LEqual(LASX,0)) { + If(Lgreater(Local0, 123)) + { + Break + } + Sleep(16) + Increment(Local0) + } + // ADBG(Local0) // uncomment to print the timeout value for debugging + Store(0, LEDM) // PCIEDBG.DMIL1EDM (324[3]) = 0 + } + Method(_OFF) // Turn off core power to PCIe Slot + { + // Set L23_Rdy Entry Request (L23ER) + Store(1, L23E) + Sleep(16) + Store(0, Local0) + While(L23E) { + If(Lgreater(Local0, 4)){ // Debug - Wait for 5 ms + Break + } + Sleep(16) + Increment(Local0) + } + Store(1, LEDM) // PCIEDBG.DMIL1EDM (324[3]) = 1 + + While(LEqual(PMFS,1)){ // PMC message serviced? + Stall(10) + } + // Disable PCIe Src Clock + Store(Or(ShiftLeft(SCLK, 24), 4), Local1) // Set Mask, OCKEN command + Store(Local1, \CKEN) // Disable Source Clock + While(LEqual(PMFS,1)){ // PMC message serviced? + Stall(10) + } + + \_SB.WTGP(RSTG,Not(RONP)) // Assert Reset Pin + + If(LNot(NGFF)) { // Dont disable power for NGFF because NGFF only has AUX power + \_SB.WTGP(PWRG,Not(PONP)) //Power OFF for Slot + } + + Store(1, LDIS) + Store(0, LDIS) //toggle link disable + + If(WKEN) { + Switch(SLOT){ + Case(0x3){ // Root Port 3 + Store(1, \GS08) //Clear GPE STATUS + Store(0, \GO08) //GPIO_OWN to ACPI Driver + } + Case(0x4){ // Root Port 4 + Store(1, \GS45) //Clear GPE STATUS + Store(0, \GO45) //GPIO_OWN to ACPI Driver + } + Case(0x5){ // Root Port 5 + Store(1, \GS51) //Clear GPE STATUS + Store(0, \GO51) //GPIO_OWN to ACPI Driver + } + Default{ + } + } + } + } // End of Method_OFF + } // End PXP + + Name(_PR0, Package(){PXP}) + diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/Rtd3FFRD.asl b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/Rtd3FFRD.asl new file mode 100644 index 0000000..a00d8e0 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/Rtd3FFRD.asl @@ -0,0 +1,1049 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + +DefinitionBlock ( + "Rtd3.aml", + "SSDT", + 1, + "AcpiRef", + "HSW-FFRD", + 0x1000 + ) +{ +#define FFRDRTD3 1 +Include ("RTD3Common.asl") +#undef FFRDRTD3 + +External(PEBS, IntObj) // PCI Express BAR address +External(BHB, IntObj) // Harris Beach FFRD Board +External(\_SB.PCI0.XHC.RHUB.HS05, DeviceObj) +External(\_SB.PCI0.XHC.RHUB.HS06, DeviceObj) +External(\_SB.PCI0.SDHC, DeviceObj) //SDIO +External(\_SB.PCI0.SDHC.WI01, DeviceObj) //SDIO Wifi +External(\_SB.PCI0.I2C1.TPD7, DeviceObj) // Precision Elantech touchpad +External(\_SB.PCI0.I2C1.TPD8, DeviceObj) // Precision Synaptics touchpad + +If(LAnd(LEqual(BID,BHB),LEqual(RTD3,1))) { +// +// PCIe RTD3 - for slot#1 +// +Scope(\_SB.PCI0.RP01) +{ + Name(SLOT, 1) + Name(RSTG, 77) // reset GPIO NGFF_WIFI_RST_N + Name(PWRG, 83) // power GPIO + Name(RONP, 1) // reset on polarity (DE-ASSERT) + Name(PONP, 1) // power on polarity + Name(NGFF, 1) // Is Slot NGFF form factor 1- Yes 0- No + Name(SCLK, 0x1) // Source Clock Enable Bit Location(BIT0) + Include("Rtd3Pcie.asl") +} + +//SATA - START + Scope(\_SB.PCI0.SAT0) { + + // D0 Method for SATA HBA + Method(_PS0,0,Serialized) + { + } + + // D3 Method for SATA HBA + Method(_PS3,0,Serialized) + { + } + + OperationRegion(SMIO,PCI_Config,0x24,4) + Field(SMIO,AnyAcc, NoLock, Preserve) { + Offset(0x00), // SATA MABR6 + MBR6, 32, // SATA ABAR + } + + OperationRegion(ST93,PCI_Config,0x93,1) + Field(ST93,AnyAcc, NoLock, Preserve) { + Offset(0x00), + P0P, 1, // Port 0 Present + P1P, 1, // Port 1 Present + P2P, 1, // Port 2 Present + P3P, 1, // Port 3 Present + } + + Scope(PRT1) { + // Store boot drive connection status + // Initialize to drive connected, value updated in _INI + Name(CONN, 1) + + Method (_INI, 0) + { + // If no drive connected on boot, update connection status and power gate the port + If(LEqual(P1P, 0)) + { + Store (0, CONN) + \_SB.WTGP (90, 1) + } + } + + PowerResource(P1PR, 0, 0){ + Name(OFTM, Zero) // Time returned by Timer() when the Power resource was turned OFF + + Method(_STA){ + If(LEqual(\_SB.RDGP(90),1)) { //GPIO90 + Return(0x00) + } Else { + Return(0x01) + } + } + Method(_ON, 0) + { + if(And(RCG0,0x10)) // RTD3Config0/RCG0 BIT 4 - Setup option to powergate Port 1 + { + // If there was a device present on boot, power on device + If(LEqual(CONN, 1)) + { + If(LNotEqual(^OFTM, Zero)) { // if OFTM != 0 => Disk as turned OFF by asl + Divide(Subtract(Timer(), ^OFTM), 10000, , Local0) //Store Elapsed time in ms + Store(Zero, ^OFTM) // Reset OFTM to zero to indicate minimum 50ms requirement does not apply when _ON called next time + If(LLess(Local0, 50)) // Do not sleep if already past the delay requirement + { + Sleep(Subtract(50, Local0)) // Sleep 100ms - time elapsed + } + } + + SGON(90, Zero) // VR stagger GPIO90 to low to power on device + } + } // if(And(RCG0,0x10)) + } // End of ON Method + Method(_OFF, 0) + { + if(And(RCG0,0x10)) // RTD3Config0/RCG0 BIT 4 - Setup option to powergate Port 1 + { + Add(\_SB.PCI0.SAT0.MBR6,0x198 ,Local0) + OperationRegion(PSTS, SystemMemory, Local0, 0x18) + Field(PSTS, DWordAcc, NoLock, Preserve) { + Offset(0x0), + CMST, 1, //PxCMD.ST + CSUD, 1, //PxCMD.SUD + , 2, + CFRE, 1, //PxCMD.FRE + Offset(0x10), + SDET, 4, //PxSSTS.DET + Offset(0x14), + CDET, 4 //PxSCTL.DET + } + If(LOr(LEqual(SDET, 1), LEqual(SDET, 3))){ //Offline flow only if Device detected and Phy not offline + //Clear ST (PxCMD.ST) 198[0] + Store(0, CMST) + //Clear FRE 198[4] + Store(0, CFRE) + //Clear SUD (PxCMD.SUD) 198[1] + Store(0, CSUD) + //Set DET to 4 (PxSCTL.DET) 1ac[3:0] + Store(4, CDET) + Sleep(16) + //Wait until PxSSTS.DET == 4 + While(LNotEqual(SDET, 4)){ + Sleep(16) + } + } + // Drive GPIO90 to High to power off device + \_SB.WTGP(90,1) + Store(Timer(), ^OFTM) // Store time when Disk turned OFF(non-zero OFTM indicate minimum 50ms requirement does apply when _ON called next time) + } // if(And(RCG0,0x10)) + } // End of OFF method + } // End P1PR + + Name(_PR0, Package(){P1PR}) + Name(_PR3, Package(){P1PR}) + + } //End PRT1 + + // PRT2 . Controlled by EC pin (PF6/PWMU4A/ExCTS). + Scope(PRT2) { + // Store boot drive connection status + // Initialize to drive connected, value updated in _INI + Name(CONN, 1) + + Method (_INI, 0) + { + // If no drive connected on boot, update connection status and power gate the port + If(LEqual(P2P, 0)) + { + Store (0, CONN) + \_SB.WTGP (86, 1) + } + } + + PowerResource(P2PR, 0, 0){ + Name(OFTM, Zero) // Time returned by Timer() when the Power resource was turned OFF + + Method(_STA){ + If(LEqual(\_SB.RDGP(86),1)) { // GPIO86 + Return(0x00) + } Else { + Return(0x01) + } + + } + Method(_ON, 0) + { + if(And(RCG0,0x20)) // RTD3Config0/RCG0 BIT 5 - Setup option to powergate Port 2 + { + // If there was a device present on boot, power on device + If(LEqual(CONN, 1)) + { + If(LNotEqual(^OFTM, Zero)) { // if OFTM != 0 => Disk as turned OFF by asl + Divide(Subtract(Timer(), ^OFTM), 10000, , Local0) // Store Elapsed time in ms + Store(Zero, ^OFTM) // Reset OFTM to zero to indicate minimum 50ms requirement does not apply when _ON called next time + If(LLess(Local0, 50)) // Do not sleep if already past the delay requirement + { + Sleep(Subtract(50, Local0)) //Sleep 100ms - time elapsed + } + } + + SGON(86, Zero) // VR stagger GPIO86 to low to power on device + } + } // if(And(RCG0,0x20)) + } // End of ON Method + Method(_OFF, 0) + { + if(And(RCG0,0x20)) // RTD3Config0/RCG0 BIT 5 - Setup option to powergate Port 2 + { + Add(\_SB.PCI0.SAT0.MBR6,0x218 ,Local0) + OperationRegion(PSTS, SystemMemory, Local0, 0x18) + Field(PSTS, DWordAcc, NoLock, Preserve) { + Offset(0x0), + CMST, 1, //PxCMD.ST + CSUD, 1, //PxCMD.SUD + , 2, + CFRE, 1, //PxCMD.FRE + Offset(0x10), + SDET, 4, + Offset(0x14), + CDET, 4 //PxSCTL.DET + } + If(LOr(LEqual(SDET, 1), LEqual(SDET, 3))){ //Offline flow only if Device detected and Phy not offline + //Clear ST (PxCMD.ST) + Store(0, CMST) + //Clear FRE + Store(0, CFRE) + //Clear SUD (PxCMD.SUD) + Store(0, CSUD) + //Set DET to 4 (PxSCTL.DET) + Store(4, CDET) + Sleep(16) + //Wait until PxSSTS.DET == 4 + While(LNotEqual(SDET, 4)){ + Sleep(16) + } + } + // Drive GPIO86 to High to power off device + \_SB.WTGP(86,1) + Store(Timer(), ^OFTM) // Store time when Disk turned OFF(non-zero OFTM indicate minimum 50ms requirement does apply when _ON called next time) + } // if(And(RCG0,0x20)) + } // End of OFF method + } // End P2PR + + Name(_PR0, Package(){P2PR}) + Name(_PR3, Package(){P2PR}) + + } //End PRT2 + + + // + // _DSM Device Specific Method supporting AHCI DEVSLP + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // Arg3: Package Parameters + // + Name(DRV, 0) // Storage for _DSM Arg3 parameter 0 + Name(PWR, 0) // Storage for _DSM Arg3 parameter 1 + + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + If (LEqual(Arg0, ToUUID ("E4DB149B-FCFE-425b-A6D8-92357D78FC7F"))) { + // + // Switch by function index + // + Switch (Arg2) { + Case (0) { + // Standard query - A bitmask of functions supported + // Supports function 0-3 + Return(0x0f) + } + Case (1) { + // Query Device IDs (Addresses) of children where drive power and/or DevSleep are supported. + // LPT-LP SATA HBA provides autonomous link (DevSleep) support, return a package of 0 elements + Return( Package(){}) // SATA HBA provides native DevSleep + } + // + // Control power to device. + // + Case (2) { + Store(ToInteger(DerefOf(Index(Arg3, Zero))), DRV) + Store(ToInteger(DerefOf(Index(Arg3, One))), PWR) + + Switch(DRV){ + Case (Ones){ + // Turn on drive and link power to all drives. Note that even though + If(PWR){ // Applying Power + //^PRT0.P0PR._ON() // apply power to port 0 + \_SB.PCI0.SAT0.PRT1.P1PR._ON() // apply power to port 1 + \_SB.PCI0.SAT0.PRT2.P2PR._ON() // apply power to port 2 + } + } + } //Switch(DRV) + Return (0) + } //Case (2) + // + // Current status of Device/Link of Port + // + Case (3){ + Store(ToInteger(DerefOf(Index(Arg3, Zero))), DRV) + Switch(DRV){ + Case (0x0000FFFF){ // SATA Port 0 + // Bit0 => Device power state + Store(1, Local0) // always ON + Return (Local0) + } + Case (0x0001FFFF){ // SATA Port 1 + // Bit0 => Device power state + If(LEqual(\_SB.PCI0.SAT0.PRT1.P1PR._STA(), 0)){ + Store(0, Local0) + }Else{ + Store(1, Local0) + } + Return (Local0) + } + Case (0x0002FFFF){ // SATA Port 2 + // Bit0 => Device power state + If(LEqual(\_SB.PCI0.SAT0.PRT2.P2PR._STA(), 0)){ + Store(0, Local0) + }Else{ + Store(1, Local0) + } + Return (Local0) + } + Default { // Invalid SATA Port - error + Return (Ones) + } + } + } + Default { + Return (0) + } + } + } Else { // UUID does not match + Return (0) + } + } //Method(_DSM) + + } //Scope(\_SB.PCI0.SAT0) + +// SATA - END + +//USB - START + Scope(\_SB.PCI0.XHC){ + Name(_S0W, 3) + } + + Scope(\_SB.PCI0.XHC.RHUB){ //USB XHCI RHUB + Method(_PS0,0,Serialized) + { + Store(0x00,USPP) + } + Method(_PS2,0,Serialized) + { + + OperationRegion (XHCM, SystemMemory, And(\_SB.PCI0.XHC.MEMB,0xFFFF0000), 0x600) + Field (XHCM, DWordAcc, NoLock, Preserve) + { + Offset(0x2), + XHCV,16, + Offset(0x480), + HP01, 1, // HS port 1 + Offset(0x490), + HP02, 1, // HS port 2 + Offset(0x4F0), + HP08, 1, // HS port 8 + Offset(0x510), + SP00, 1, // SS port 0 + Offset(0x520), + SP01, 1, // SS port 1 + Offset(0x540), + SP03 , 1, // SS port 3 + } + If(LEqual(XHCV,0xFFFF)) // Controller in D3Hot(MEM_BASE not decoded) + { + Return() + } + If(LAnd(LEqual(HP08,0x00),LEqual(SP03,0x00))) // SD Card reader + { + Or(USPP,0x01, USPP) + } + If(LAnd(LEqual(HP01,0x00),LEqual(SP00,0x00))) // USB(HS1 : 0x480 /SS0 : 0x510) + { + Or(USPP,0x02, USPP) + } + If(LAnd(LEqual(HP02,0x00),LEqual(SP01,0x00))) // USB(HS2 : 0x490 / SS1 : 0x520) + { + Or(USPP,0x04, USPP) + } + } // End of PS2 method + Method(_PS3,0,Serialized) + { + } // End of _PS3 method + } + +Scope(\_SB.PCI0.XHC.RHUB.HS06){ + + PowerResource(PX06, 0, 0){ // power rail for USB3.0 ports 6 - GPIO 84 + Method(_STA){ + If(LEqual(\_SB.RDGP(84),1)) { //GPIO84 + Return(0x01) + } Else { + Return(0x00) + } + } + Method(_ON, 0) + { // Turn on + SGON(84, One) // VR stagger GPIO84 to high to power on device + } + + Method(_OFF, 0) + { // Turn off + \_SB.WTGP(84,0) + } + } // End PX06 + Name(_S0W,2) // Indicate WWAN can wake from D2 while in S0 using selective suspend + Name(_PR0,Package(){\_SB.PCI0.XHC.RHUB.HS06.PX06}) // Power Resource required to support D0 + Name(_PR2,Package(){\_SB.PCI0.XHC.RHUB.HS06.PX06}) // Power Resource required to support D2 + Name(_PR3,Package(){\_SB.PCI0.XHC.RHUB.HS06.PX06}) // Power Resource required to support D3 +} + + Scope(\_SB.PCI0.XHC.RHUB.HS05){ + PowerResource(PX05, 0, 0){ // power rail for USB2.0 ports 5 - GPIO 25 + Method(_STA){ + If(LEqual(\_SB.RDGP(25),1)) { //GPIO25 + Return(0x01) + } Else { + Return(0x00) + } + } + Method(_ON, 0) + { // Turn on + SGON(25, One) // VR stagger GPIO25 to high to power on device + } + + Method(_OFF, 0) + { // Turn off + \_SB.WTGP(25,0) + } + } // End PX05 + Name(_PR0,Package(){\_SB.PCI0.XHC.RHUB.HS05.PX05}) // Power Resource required to support D0 + Name(_PR2,Package(){\_SB.PCI0.XHC.RHUB.HS05.PX05}) // Power Resource required to support D2 + Name(_PR3,Package(){\_SB.PCI0.XHC.RHUB.HS05.PX05}) // Power Resource required to support D3 + } + Scope(\_SB.PCI0.XHC){ //USB XHCI + + Name(UPWR,0) + Name(USPP,0) + // Bit 0 : USB SD Card Reader + // Bit 1 : USB(HS1 : 0x480 /SS0 : 0x510) + // BIT 2 : USB(HS2 : 0x490 / SS1 : 0x520) + + + Method(DUAM,0,Serialized) + { + + OperationRegion (XHCM, SystemMemory, And(\_SB.PCI0.XHC.MEMB,0xFFFF0000), 0x600) + Field (XHCM, DWordAcc, NoLock, Preserve) + { + Offset(0x2), + XHCV,16, + Offset(0x480), + HP01, 1, // HS port 1 + Offset(0x490), + HP02, 1, // HS port 2 + Offset(0x4F0), + HP08, 1, // HS port 8 + Offset(0x510), + SP00, 1, // SS port 0 + Offset(0x520), + SP01, 1, // SS port 1 + Offset(0x540), + SP03 , 1, // SS port 3 + } + + if(LNotEqual(\UAMS,0x00)) // User not present + { + Store(0x00,UPWR) + // Enterng CS, Remove power if SD card not present + + If(LEqual(XHCV,0xFFFF)) // Controller in D3Hot(MEM_BASE not decoded) + { + If(And(USPP,0x01)) // SD Card reader + { + \_SB.WTGP(60,0) + Or(UPWR,0x01, UPWR) + } + If(And(USPP,0x06)) // USB(HS1 : 0x480 /SS0 : 0x510) & USB(HS2 : 0x490 / SS1 : 0x520) + { + \_SB.GP2N(40,1) // Mask OC#(Switch to GPIO mode) + \_SB.WTGP(13,0) // Power gate GPIO13/43 at same time + \_SB.WTGP(43,0) + Or(UPWR,0x02, UPWR) + Or(UPWR,0x04, UPWR) + } + }Else{ // If(Lequal(XHCV,0xFFFF)) + If(LAnd(LEqual(HP08,0x00),LEqual(SP03,0x00))) // SD Card reader + { + \_SB.WTGP(60,0) + Or(UPWR,0x01, UPWR) + } + If(LAnd(LAnd(LEqual(HP01,0x00),LEqual(SP00,0x00)), LAnd(LEqual(HP02,0x00),LEqual(SP01,0x00)))) // USB(HS1 : 0x480 /SS0 : 0x510) &USB(HS2 : 0x490 / SS1 : 0x520) + { + \_SB.GP2N(40,1) // Mask OC#(switch to GPIO mode) + \_SB.WTGP(13,0) // Power gate GPIO13/43 at same time + \_SB.WTGP(43,0) + Or(UPWR,0x02, UPWR) + Or(UPWR,0x04, UPWR) + } + }// If(Lequal(XHCV,0xFFFF)) + }Else{ //if(LNotEqual(\UAMS,0x00)) + + // Exiting CS , Apply power if power removed + if(And(UPWR,0x01)) // SD Card reader + { + \_SB.WTGP(60,1) + } + if(And(UPWR,0x02)) // USB(HS1 : 0x480 /SS0 : 0x510) + { + \_SB.GP2N(40,0) // Un-mask OC# + \_SB.WTGP(13,1) + } + if(And(UPWR,0x04)) // USB(HS2 : 0x490 / SS1 : 0x520) + { + \_SB.GP2N(40,0) // Un-mask OC# + \_SB.WTGP(43,1) + } + } //if(LNotEqual(\UAMS,0x00)) // User not present + } // End of DUAM + } + +//USB - END + + + +// Serial IO Start + + //Power Resource for Audio Codec +Scope(\_SB.PCI0) +{ + PowerResource(PAUD, 0, 0) { + + Name(PSTA, One) // Physical Power Status of Codec 0 - OFF; 1-ON + Name(ONTM, Zero) // 0 - Not in Speculative ON ; Non-Zero - elapsed time in Nanosecs after Physical ON + + Name(_STA, One) // PowerResource Logical Status 0 - OFF; 1-ON + + Method(_ON, 0){ + Store(One, _STA) // Set Logocal power state + PUAM() // Tansition Physical state to match current logical state + } // End _ON + + Method(_OFF, 0){ + Store(Zero, _STA) // Set the current power state + PUAM() // Tansition Physical state to match current logical state + } // End _OFF + + // PUAM - Power Resource User Absent Mode for onboard Audio CODEC + // Arguments: + // + // Uses: + // _STA - Variable updated by Power Resource _ON/_OFF methods + // \UAMS - Variable updated by GUAM method to show User absent/Present + // ONTM - Local variable to store ON time during Speculative ON + // ______________________________ + // | Inputs | Outputs | + // ______________________________ + // | _STA | \UAMS | GPIO | ONTM | + // ______________________________ + // | 1 | 0 | ON | !0 | + // | 1 | !0 | ON | !0 | + // | 0 | 0 | ON | !0 | + // | 0 | !0 | OFF | 0 | + // ______________________________ + + Method(PUAM, 0, Serialized) + { + If (LAnd(LEqual(^_STA, Zero), LNotEqual(\UAMS, Zero))) { //New state = OFF (_STA ==0 && \UAMS != 0) + If(LEqual(\_SB.RDGP(76), One)) { //skip if Power Resource is already in OFF + //Device OFF + // Drive GPIO 76 to Low + \_SB.WTGP(76, Zero) // Remove CODEC Power + Store(Zero, ^PSTA) + Store(Zero, ^ONTM) + } + } Else { // New state = ON (_STA=1) or (_STA=0 and \UAMS=0) + If(LNotEqual(^PSTA, One)) { //skip if Power Resource is already in ON + SGON(76, One) // VR stagger GPIO76 to high to power on device + Store(One, ^PSTA) + Store(Timer(), ^ONTM) // Start the timer for this PR + } + } // Turn power on + } //PUAM + } //PAUD +} //Scope(\_SB.PCI0) + +If(LNot(HDAD)) { // Check Funtion disable register that gets updated depending on setup option + Scope(\_SB.PCI0.HDEF) { + + Method(_PS0,0,Serialized) // D0 Method for HD-A Controller + { + If(LEqual(\_SB.PCI0.PAUD.ONTM, Zero)){ + Return() + } + + // + // Make sure "D0 delay" (AUDD) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // AUDD: Time required for device to be ready after power on + // Local1 = AUDD + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.PAUD.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(AUDD, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) { //Do not sleep if already past the delay requirement audio + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (AUDD + VRRD - time elapsed) + } + } + Method(_PS3,0,Serialized) // D3 Method for HD-A Controller(Dummy routine to support D3 state) + { + } + + Name(_PR0, Package(){\_SB.PCI0.PAUD}) + } +}// IF(HDAD) + +// I2C0 +Scope(\_SB.PCI0.I2C0) { // I2C0 + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + Store(0, Local0) // BIT0 : ADSP Disabled BIT1 : SHUB Disabled + If(LEqual(And(SDS0,0x01), 0x00)) { // Update Local0 BIT1 if SHUB disabled in setup + Or(0x02,Local0,Local0) + } + + If(LEqual(Local0,0x01)){ // Only SHUB enabled + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,\_SB.PCI0.I2C1.PXTC}) + } + Return(Package(){}) // Both SHUB and ADSP codec disabled + } + // D0 Method for I2C0 Controller(Called by _PS0) + Method(PS0X,0,Serialized) + { + Sleep(I20D) // If required add delay in controller to gurantee longest delaying device have time + If(And(LEqual(RIC0,1),LEqual(\_SB.RDGP(44), 0x01))) { // Enabled in Setup and not in DFU mode + // Drive GIO49 High - routed to Sensor HUB STOP mode + \_SB.WTGP(49,1) + Sleep(16) + } + } + + // D3 Method for I2C0 Controller(Called by _PS3) + Method(PS3X,0,Serialized) + { + If(And(LEqual(RIC0,1),LEqual(\_SB.RDGP(44), 0x01))) { // Enabled in Setup and not in DFU mode + // Drive GIO49 Low - routed to Sensor HUB STOP mode + \_SB.WTGP(49,0) + Sleep(16) + } + } +} // \_SB.PCI0.I2C0 +Scope(\_SB.PCI0.I2C0.SHUB) +{ + // D0 Method Hook for I2C1 Controller(Called by _PS0) + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C0.SHUB.PSEN.ONTM,Zero)){ + Return() + } + + // + // Make sure "D0 delay" (IC0D) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC0D: Time required for device to be ready after power on + // Local1 = IC0D + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C0.SHUB.PSEN.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC0D, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for SensorHub + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC0D + VRRD - time elapsed) + } + } + Method(_PS3,0,Serialized) + { + } + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(And(LEqual(RIC0,1),LEqual(\_SB.RDGP(44), 0x01))) { // Enabled in Setup and not in DFU mode + Return(Package(){PSEN,\_SB.PCI0.I2C1.PXTC}) + } Else { + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(And(LEqual(RIC0,1),LEqual(\_SB.RDGP(44), 0x01))) { // Enabled in Setup and not in DFU mode + Return(Package(){PSEN,\_SB.PCI0.I2C1.PXTC}) + } Else { + Return(Package(){}) + } + } + + PowerResource(PSEN, 0, 0) { + Name(ONTM, Zero) // On Timer + + Method(_STA){ + If(LEqual(SHSB, 0)){ + If(LEqual(\_SB.RDGP(46),1)) { //GPIO46 NOTE: 1=> ON; 0=> OFF + Return(0x01) + } + }Else{ + If(LEqual(\_SB.RDGP(70),1)) { //GPIO70 NOTE: 1=> ON; 0=> OFF + Return(0x01) + } + } + Return(0x00) + } + + Method(_ON, 0){ + If(And(LEqual(RIC0,1),LEqual(\_SB.RDGP(44), 0x01))) { // Enabled in Setup and not in DFU mode + // Drive GPIO 46 High + If(LEqual(SHSB, 0)){ + If(LEqual(SGON(46, One), One)) { // VR stagger GPIO46 to high to power on device + Store(Timer(), ^ONTM) // Start the timer + \_SB.GP2B(14, One) // Enable int line from sensor hub. GPIO14 is PIRQM(IOAPIC ln28) + } + }Else{ + If(LEqual(SGON(70, One), One)) { // VR stagger GPIO70 to high to power on device + Store(Timer(), ^ONTM) // Start the timer + \_SB.GP2B(14, One) // Enable int line from sensor hub. GPIO14 is PIRQM(IOAPIC ln28) + } + } + } // End if - Enabled in Setup and not in DFU mode + } // End _ON + + Method(_OFF, 0){ + If(And(LEqual(RIC0,1),LEqual(\_SB.RDGP(44), 0x01))) { // Enabled in Setup and not in DFU mode + // Mask interrupt from Sensorhub GPIPIRQ2IOXAPIC: GPI PIRQ[X:I] to IOxAPIC[39:24] Enable + \_SB.GP2B(14, Zero) // GPIO14 is PIRQM(IOAPIC ln28) + If(LEqual(SHSB, 0)){ + \_SB.WTGP(46, Zero) // Remove Device Power + }Else{ + \_SB.WTGP(70, Zero) + } + Store(Zero, ^ONTM) + Store(Zero , ^ONTM) + }// End if - Enabled in Setup and not in DFU mode + } // End _OFF + } //PSEN +} // Scope(SHUB) + + //Merge TouchPanel/Touch Pad Power control - I2C Sensors Need to Turn ON/OFF at same time + Scope(\_SB.PCI0.I2C1){ + + Method(PS0X,0,Serialized) + { + // If required add delay in controller to gurantee longest delaying device have time + Sleep(I21D) + } + + Method(PS3X,0,Serialized) + { + } + + PowerResource(PXTC, 0, 0){ // power rail for Touch Panel and Touchpad GPIO 89 + + Name(ONTM, 0) // 0 - Not in Speculative ON ; Non-Zero - elapsed time in Nanosecs after Physical ON + Method(_STA){ + If(LEqual(\_SB.RDGP(89),1)) { //GPIO89 NOTE: 1=> ON; 0=> OFF + Return(0x01) + } Else { + Return(0x00) + } + } + Method(_ON, 0) + { + If(LOr(LEqual(\_SB.RDGP(89),0), LEqual(\_SB.RDGP(52),0))) { //GPIO89 NOTE: 1=> ON; 0=> OFF + \_SB.WTGP(52,1) //DeAssert GPIO RST + SGON(89, One) // VR stagger GPIO89 to high to power on device + Store(Timer(), ^ONTM) + //Enable int line from touch screen and Touch pad + \_SB.GP2A(50, One) //TPL0 + If(LAnd(LNotEqual(And(SDS1,0x0800), 0x0800),LNotEqual(And(SDS1,0x1000), 0x1000))) { //Precision Enabled + \_SB.GP2A(55, One) //TPD0/1 + } + } + }// End _ON + + Method(_OFF, 0) + { + //mask interrupt from Touch Screen and Touch Pad GPIPIRQ2IOXAPIC: GPI PIRQ[X:I] to IOxAPIC[39:24] Enable + \_SB.GP2A(50, Zero) //TPL0 + If(LAnd(LNotEqual(And(SDS1,0x0800), 0x0800),LNotEqual(And(SDS1,0x1000), 0x1000))) { //Precision Enabled + \_SB.GP2A(55, Zero) //TPD0/1 + } + \_SB.WTGP(89,0) // Drive GPIO89 to remove power for Touchpad and TouchPanel + \_SB.WTGP(52,0) //GPIO RST to Touch Panel + Store(Zero , ^ONTM) + }// End _OFF + } // End PXTC + + Scope(TPL0){ + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + + // + // Make sure "D0 delay" (IC1D) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1D: Time required for device to be ready after power on + // Local1 = IC1D + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1D, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1D + VRRD - time elapsed) + } + } + Method(_PS3,0,Serialized) + { + } + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x01), 0x01)) + { + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,PXTC}) + } Else { + Return(Package() {}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x01), 0x01)) + { + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,PXTC}) + } Else { + Return(Package() {}) + } + } + } // End of Scope(TPL0) + Scope(TPD1){ + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // + // Make sure "D0 delay" (IC1S) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1S: Time required for device to be ready after power on + // Local1 = IC1S + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1S, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1S + VRRD - time elapsed) + } + } + Method(_PS3,0,Serialized) + { + } + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x08), 0x08)) { + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,PXTC}) + } Else { + Return(Package() {}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x08), 0x08)) { + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,PXTC}) + } Else { + Return(Package() {}) + } + } + }// End of Scope(TPD1) + + //------------------------ + // Elantech Precision touchpad + //------------------------ + Scope(TPD7){ + + // + // Delay for Touchpanel & TouchPad - Both share same I2C bus + // + Method(PS0X,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // + // Make sure "D0 delay" (IC1S) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1S: Time required for device to be ready after power on + // Local1 = IC1S + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1S, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1S + VRRD - time elapsed) + } + } + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0800), 0x0800)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0800), 0x0800)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + }// End of Scope(TPD7) + + //------------------------ + // Synaptics Precision touchpad + //------------------------ + Scope(TPD8){ + + // + // Delay for Touchpanel & TouchPad - Both share same I2C bus + // + Method(PS0X,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // + // Make sure "D0 delay" (IC1S) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1S: Time required for device to be ready after power on + // Local1 = IC1S + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1S, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1S + VRRD - time elapsed) + } + } + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x1000), 0x1000)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x1000), 0x1000)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + }// End of Scope(TPD8) + }// Scope(\_SB.PCI0.I2C1) + +//Serial IO End + + //SDIO Reset support + Scope(\_SB.PCI0.SDHC) + { + // D0 Method for SDHC + Method(PS0X,0,Serialized) + { + // Drive GPIO77 High - 1: No GPIO RST to on board mPCIe/NGFF_WIFI + \_SB.WTGP(77,1) + } + } + + Scope(\_SB.PCI0.SDHC.WI01) + { + // D0 Method for WiFi + Method(PS0X,0,Serialized) + { + // Drive GPIO77 High - 1: No GPIO RST to on board mPCIe/NGFF_WIFI + \_SB.WTGP(77,1) + } + + // D3 Method for WiFi + Method(PS3X,0,Serialized) + { + // Drive GPIO77 Low - 0: GPIO RST to on board mPCIe/NGFF_WIFI + \_SB.WTGP(77,0) + } + } //\_SB.PCI0.SDHC.WI01 + +} //If(LAnd(LEqual(BID,BHB),LEqual(RTD3,1))) +} // End SSDT diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/SsdtRtd3.cif b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/SsdtRtd3.cif new file mode 100644 index 0000000..841f0f9 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/SsdtRtd3.cif @@ -0,0 +1,14 @@ +<component> + name = "SsdtRtd3" + category = ModulePart + LocalRoot = "ReferenceCode\AcpiTables\SampleCode\SsdtRtd3\" + RefName = "SsdtRtd3" +[files] +"SsdtRtd3.sdl" +"SsdtRtd3.mak" +"Ult0Rtd3.asl" +"BRRtd3.asl" +"Rtd3FFRD.asl" +"RTD3Common.asl" +"RTD3Pcie.asl" +<endComponent> diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/SsdtRtd3.mak b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/SsdtRtd3.mak new file mode 100644 index 0000000..aaa91eb --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/SsdtRtd3.mak @@ -0,0 +1,82 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: SsdtRtd3.mak +# +# Description: MAke file to build Aptio ACPI ASL components +# +# +#<AMI_FHDR_END> +#************************************************************************* +all : BuildRTD3 + +BuildRTD3 : $(BUILD_DIR)\Ult0Rtd3.ffs + +#----------------------------------------------------------------------- +# ASL compiler definition +#----------------------------------------------------------------------- +!IF "$(ACPIPLATFORM_ASL_COMPILER)"=="" +!ERROR It is an invalid path, please check your ASL compiler path. +!ENDIF + +IASL = $(ACPIPLATFORM_ASL_COMPILER) +#----------------------------------------------------------------------- +$(BUILD_DIR)\Ult0Rtd3.aml : $(INTEL_RTD3_ASL_FILE) + @cl /C /EP $(INTEL_RTD3_ASL_FILE) > $(BUILD_DIR)\Ult0Rtd3.asl + @cl /C /EP $(INTEL_RTD3_COMMON_ASL_FILE) > $(BUILD_DIR)\RTD3Common.asl + @cl /C /EP $(INTEL_RTD3_PCIE_ASL_FILE) > $(BUILD_DIR)\RTD3Pcie.asl + $(IASL) -p $(BUILD_DIR)\Ult0Rtd3.aml $(BUILD_DIR)\Ult0Rtd3.asl + +$(BUILD_DIR)\Ult0Rtd3.sec: $(BUILD_DIR)\Ult0Rtd3.aml + $(GENSECTION) -I $*.aml -O $@ -S EFI_SECTION_RAW + +#Note. Expand the package with RTD3 tables. +# DXE phase will load the tables +# and update Aml contents if provided in Acpiplatform.c + +$(BUILD_DIR)\Ult0Rtd3.ffs: $(BUILD_DIR)\Ult0Rtd3.sec + $(GENFFSFILE) -B $(BUILD_DIR) -V -o $@ -P1 <<$(BUILD_DIR)\Ult0Rtd3.pkg + +PACKAGE.INF +[.] +BASE_NAME = Ult0Rtd3 +FFS_FILEGUID = 7FFC3536-0A8A-448B-95F4-39F5B9F09ADD +FFS_FILETYPE = EFI_FV_FILETYPE_FREEFORM +FFS_ATTRIB_CHECKSUM = TRUE + +IMAGE_SCRIPT = +{ + Compress (dummy) { + $(PROJECT_DIR)\$(BUILD_DIR)\Ult0Rtd3.sec + } +} +<<KEEP + + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/SsdtRtd3.sdl b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/SsdtRtd3.sdl new file mode 100644 index 0000000..db8df2a --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/SsdtRtd3.sdl @@ -0,0 +1,93 @@ +TOKEN + Name = "RTD3_SUPPORT" + Value = "1" + Help = "Main switch to enable RTD3 support in Project" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Master = Yes +End + +TOKEN + Name = "ULT0RTD3_SUPPORT" + Value = "1" + Help = "Main switch to enable RTD3 support for Whitetip Mountain or Sawtooth Peak CRB" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Token = "RTD3_SUPPORT" "=" "1" +End + +TOKEN + Name = "BRRTD3_SUPPORT" + Value = "0" + Help = "Main switch to enable RTD3 support for Basking Ridge CRB" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Token = "RTD3_SUPPORT" "=" "1" +End + +TOKEN + Name = "RTD3FFRD_SUPPORT" + Value = "0" + Help = "Main switch to enable RTD3 support for FFRD SKU CRB" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Token = "RTD3_SUPPORT" "=" "1" +End + +PATH + Name = "INTEL_SSDTRTD3_DIR" +End + +TOKEN + Name = "INTEL_RTD3_ASL_FILE" + Value = "$(INTEL_SSDTRTD3_DIR)\Ult0Rtd3.asl" + TokenType = Expression + TargetMAK = Yes + Token = "ULT0RTD3_SUPPORT" "=" "1" +End + +TOKEN + Name = "INTEL_RTD3_ASL_FILE" + Value = "$(INTEL_SSDTRTD3_DIR)\BRRtd3.asl" + TokenType = Expression + TargetMAK = Yes + Token = "BRRTD3_SUPPORT" "=" "1" +End + +TOKEN + Name = "INTEL_RTD3_ASL_FILE" + Value = "$(INTEL_SSDTRTD3_DIR)\Rtd3FFRD.asl" + TokenType = Expression + TargetMAK = Yes + Token = "RTD3FFRD_SUPPORT" "=" "1" +End + +TOKEN + Name = "INTEL_RTD3_COMMON_ASL_FILE" + Value = "$(INTEL_SSDTRTD3_DIR)\RTD3Common.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_RTD3_PCIE_ASL_FILE" + Value = "$(INTEL_SSDTRTD3_DIR)\RTD3Pcie.asl" + TokenType = Expression + TargetMAK = Yes +End + +MODULE + Help = "Includes SsdtRtd3.mak to Project" + File = "SsdtRtd3.mak" +End + +ELINK + Name = "$(BUILD_DIR)\Ult0Rtd3.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent + Token = "RTD3_SUPPORT" "=" "1" +End diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/Ult0Rtd3.asl b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/Ult0Rtd3.asl new file mode 100644 index 0000000..e55ac2f --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtRtd3/Ult0Rtd3.asl @@ -0,0 +1,1718 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + +DefinitionBlock ( + "Rtd3.aml", + "SSDT", + 1, + "AcpiRef", + "Ult0Rtd3", + 0x1000 + ) +{ +#define ULT0RTD3 1 +Include ("RTD3Common.asl") +#undef ULT0RTD3 + +External(PEBS, IntObj) // PCI Express BAR address +External(BWT1, IntObj) // WhitTipMountain1 +External(BSPC, IntObj) // SawToothPeak + +External(\_SB.PCI0.I2C0.ACD0, DeviceObj) +External(\_SB.PCI0.I2C0.ACD1, DeviceObj) +External(\_SB.PCI0.I2C0.ACD2, DeviceObj) +External(\_SB.PCI0.I2C1.TPL1, DeviceObj) // Touch panel +External(\_SB.PCI0.I2C1.TPL2, DeviceObj) // NTRIG Digitizer Touch Panel +External(\_SB.PCI0.I2C1.TPD2, DeviceObj) // Alps touchpad +External(\_SB.PCI0.I2C1.TPL3, DeviceObj) // EETI Touch Panel +External(\_SB.PCI0.I2C1.TPD3, DeviceObj) // Cypress touchpad +External(\_SB.PCI0.I2C1.TPD7, DeviceObj) // Precision Elantech touchpad +External(\_SB.PCI0.I2C1.TPD8, DeviceObj) // Precision Synaptics touchpad +External(\_SB.PCI0.SDHC, DeviceObj) //SDIO +External(\_SB.PCI0.SDHC.WI01, DeviceObj) //SDIO Wifi +External(\_SB.PCI0.XHC.RHUB.HS10, DeviceObj) //xHCI SSP port 1 +External(S0ID) +External(\_SB.PCI0.XHC.RHUB.HS11, DeviceObj) //xHCI SSP port 2 +External(\_SB.PCI0.XHC.RHUB.HS04, DeviceObj) //EHCI HSP port 4 + +External(ADSD, FieldUnitObj) +External(CODS, IntObj) +External(\GO17) + + +External(DSPD) +External(RWAG, IntObj) + +If(LAnd(LOr(LEqual(BID,BWT1), LEqual(BID,BSPC)),LEqual(RTD3,1))) { + +If(LEqual(RWAG,1)) { // this enables board W/A for RTD3 on slot 1 + // + // PCIe RTD3 - for slot#1 + // + Scope(\_SB.PCI0.RP01) + { + Name(SLOT, 1) + Name(RSTG, 77) // reset GPIO + Name(PWRG, 83) // power GPIO + Name(RONP, 1) // reset on polarity + Name(PONP, 0) // power on polarity + Name(NGFF, 1) // Is Slot NGFF form factor 1- Yes 0- No + Name(SCLK, 0x1) // Source Clock Enable Bit Location(BIT0) + Include("Rtd3Pcie.asl") + } +} + +If(LEqual(RWAG,6)) { // this enables board W/A for RTD3 on slot 6 + // + // PCIe RTD3 - for slot#6 + // + Scope(\_SB.PCI0.RP06) + { + Name(SLOT, 6) + Name(RSTG, 77) // reset GPIO + Name(PWRG, 83) // power GPIO + Name(RONP, 1) // reset on polarity + Name(PONP, 0) // power on polarity + Name(NGFF, 0) // Is Slot NGFF form factor 1- Yes 0- No + Name(SCLK, 0x2) // Source Clock Enable Bit Location(BIT1) + Include("Rtd3Pcie.asl") + } +} + + // + // PCIe RTD3 - for slot#3 + // + Scope(\_SB.PCI0.RP03) + { + Name(SLOT, 3) + Name(RSTG, 59) // reset GPIO + Name(PWRG, 60) // power GPIO + Name(RONP, 1) // reset on polarity + Name(PONP, 0) // power on polarity + Name(NGFF, 0) // Is Slot NGFF form factor 1- Yes 0- No + Name(SCLK, 0x4) // Source Clock Enable Bit Location(BIT2) + Include("Rtd3Pcie.asl") + } + + // + // PCIe RTD3 - for slot#4 + // + Scope(\_SB.PCI0.RP04) + { + Name(SLOT, 4) + Name(RSTG, 56) // reset GPIO + Name(PWRG, 57) // power GPIO + Name(RONP, 1) // reset on polarity + Name(PONP, 0) // power on polarity + Name(NGFF, 0) // Is Slot NGFF form factor 1- Yes 0- No + Name(SCLK, 0x8) // Source Clock Enable Bit Location(BIT3) + Include("Rtd3Pcie.asl") + } + + // + // PCIe RTD3 - for slot#5 + // + Scope(\_SB.PCI0.RP05) + { + Name(SLOT, 5) + Name(RSTG, 48) // reset GPIO + Name(PWRG, 84) // power GPIO + Name(RONP, 1) // reset on polarity + Name(PONP, 0) // power on polarity + Name(NGFF, 0) // Is Slot NGFF form factor 1- Yes 0- No + Name(SCLK, 0x10) // Source Clock Enable Bit Location(BIT4) + Include("Rtd3Pcie.asl") + } + +//SATA - START + Scope(\_SB.PCI0.SAT0) { + + // D0 Method for SATA HBA + Method(_PS0,0,Serialized) + { + } + + // D3 Method for SATA HBA + Method(_PS3,0,Serialized) + { + } + + OperationRegion(SMIO,PCI_Config,0x24,4) + Field(SMIO,AnyAcc, NoLock, Preserve) { + Offset(0x00), // SATA MABR6 + MBR6, 32, // SATA ABAR + } + + Scope(PRT1) { + Name(UDSM, 0) // Use _DSM for ZPODD control. 0 = Disabled; 1 = Enabled + + // + // _DSM Device Specific Method supporting SATA ZPODD function + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // Arg3: Package Parameters + // + Method (_DSM, 4, NotSerialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + if(LNot(And(RCG0,1))){ + Return(0) // HDD do nothing + } + If (LEqual(Arg0, ToUUID ("bdfaef30-aebb-11de-8a39-0800200c9a66"))) { + // + // Switch by function index + // + Switch (ToInteger(Arg2)) { + // + // Standard query - A bitmask of functions supported + // Supports function 0-5 + // + Case (0) { + if(LEqual(ToInteger(Arg1),1)){ // Check Revision + Return (Buffer () {0xF}) + } + } + Case (1) { // Enable ZPODD feature + // Function 1: Enable Power OFF/ON. Enables the Power Off/ON hardware in the system. + // When called, the BIOS is informed that the host software is using this interface. + If(LEqual(\_SB.PCI0.SAT0.PRT1.UDSM, Zero)){ //if Ownership not acquired + Store (1, \_SB.PCI0.SAT0.PRT1.UDSM) // Indicate ZPODD _DSM control enabled + } + Return (1) // Enable Power ON/OFF + } + Case (2) { + \_SB.WTGP(86,1) // Power Off the device + Store(0,\GO17) // Enable GPIO86 + Return (1) + } + Case (3) { + \_SB.WTGP(86,0) // Power ON Device + Sleep(16) // To turn the FET + + Return (1) + } + Default { + Return (0) + } + } + } Else { + Return (0) + } + } + + Name(_PR0, Package(){P1PR}) + Name(_PR3, Package(){P1PR}) + + Name(WKEN, 0) // Device on this port wake enabled? + + Method(_S0W, 0) + { + if(LNot(And(RCG0,1))){ + }Else{ + // PMEs can be generated from D3cold + If(And(\_SB.OSCO, 0x04)) + { + Return(4) // OS comprehends D3cold, as described via \_SB._OSC + }Else{ + Return(3) + } + } + } // End _S0W + + Method(_DSW, 3) + { + if(LNot(And(RCG0,1))){ + Return() + } + If(Arg1) + { + Store(1,\GO17) + Store(0, WKEN) + }Else{ // Staying in S0 + If(LAnd(Arg0, Arg2)) // Exiting D0 and arming for wake + { // Set WKEN to allow _OFF to enable the wake event + Store(1, WKEN) + } Else { // Clear WKEN to allow _OFF to enable the wake event, + // either because staying in D0 or disabling wake + Store(0, WKEN) + } + } + } // End _DSW + + + PowerResource(P1PR, 0, 0) + { + Name(OFTM, Zero) // Time returned by Timer() when the Power resource was turned OFF + + Method(_STA) + { + if(LNot(And(RCG0,1))){ + If(LEqual(\_SB.RDGP(90),1)) { //GPIO90 + Return(0x00) + } Else { + Return(0x01) + } + }Else{ + // Read ZPODD Status + if(LEqual(RDGP(86),0)){ + Return(0x01) + }Else{ + Return(0x00) + } + } + } + + Method(_ON, 0) + { + If(LNotEqual(^OFTM, Zero)) { // if OFTM != 0 => Disk was turned OFF by asl + Divide(Subtract(Timer(), ^OFTM), 10000, , Local0) //Store Elapsed time in ms + Store(Zero, ^OFTM) // Reset OFTM to zero to indicate minimum 50ms requirement does not apply when _ON called next time + If(LLess(Local0, 50)) // Do not sleep if already past the delay requirement + { + Sleep(Subtract(50, Local0)) // Sleep 50ms - time elapsed + } + } + + if(LNot(And(RCG0,1))){ + SGON(90, Zero) // VR stagger GPIO90 to low to power on device + }Else{ + + SGON(86, Zero) // VR stagger GPIO86 to low to power on device + } + } + + + Method(_OFF, 0) + { + If(LNot(And(RCG0,1))){ + Add(\_SB.PCI0.SAT0.MBR6,0x198 ,Local0) + OperationRegion(PSTS, SystemMemory, Local0, 0x18) + Field(PSTS, DWordAcc, NoLock, Preserve) + { + Offset(0x0), + CMST, 1, //PxCMD.ST + CSUD, 1, //PxCMD.SUD + , 2, + CFRE, 1, //PxCMD.FRE + Offset(0x10), + SDET, 4, //PxSSTS.DET + Offset(0x14), + CDET, 4 //PxSCTL.DET + } + // if S0Ix enabled + If(LEqual(S0ID, 1)) + { + If(LOr(LEqual(SDET, 1), LEqual(SDET, 3))) //Offline flow only if Device detected and Phy not offline + { + //Clear ST (PxCMD.ST) 198[0] + Store(0, CMST) + //Clear FRE 198[4] + Store(0, CFRE) + //Clear SUD (PxCMD.SUD) 198[1] + Store(0, CSUD) + //Set DET to 4 (PxSCTL.DET) 1ac[3:0] + Store(4, CDET) + Sleep(16) + //Wait until PxSSTS.DET == 4 + While(LNotEqual(SDET, 4)){ + Sleep(16) + } + } + // Drive GPIO90 to High to power off device + \_SB.WTGP(90,1) + } // if S0Ix enabled + }Else{ + + \_SB.WTGP(86,1) // Drive GPIO86 to low to power off device. + Store(0,\GO17) // Enable ZPODD SATA_ODD_DA_N to generate SCI + } + + Store(Timer(), ^OFTM) // Store time when Disk turned OFF(non-zero OFTM indicate minimum 50ms requirement does apply when _ON called next time) + } + } // End P1PR + } //End PRT1 + + // PRT2 . Controlled by EC pin (PF6/PWMU4A/ExCTS). + Scope(PRT2) { // Port 2- Cable Connect power + + PowerResource(P2PR, 0, 0){ + Name(OFTM, Zero) // Time returned by Timer() when the Power resource was turned OFF + + Method(_STA){ + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.ECAV)),1)) { // Read SATA_CABLE_PWR_EN from EC + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.SPT2)), Local0) + } Else { + Store(1, Local0) //This FET is ON during POST. It cannot be turned OFF until EC driver is loaded + } + If(LEqual(Local0,0)) { // Read SATA_CABLE_PWR_EN from EC + Return(0x00) + } Else { + Return(0x01) + } + + Return(0x01) + } + Method(_ON, 0) + { + If(LNotEqual(^OFTM, Zero)) { // if OFTM != 0 => Disk as turned OFF by asl + Divide(Subtract(Timer(), ^OFTM), 10000, , Local0) //Store Elapsed time in ms + Store(Zero, ^OFTM) // Reset OFTM to zero to indicate minimum 50ms requirement does not apply when _ON called next time + If(LLess(Local0, 50)) // Do not sleep if already past the delay requirement + { + Sleep(Subtract(50, Local0)) // Sleep 50ms - time elapsed + } + } + + //SET SATA_CABLE_PWR_EN and Send EC UpdateDevPwr - 0x2C + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.ECAV)),1)) { // Check If EC driver loaded + // + // Special case for EC driven device power on using VR staggering (SGON is for GPIO driven device power on) + // Marked with "//VR Staggering" at the end of line. + // //VR Staggering + // Check for VR staggering //VR Staggering + // //VR Staggering + Divide(Subtract(Timer(), \LONT), 10000, , Local0) //Store Elapsed time in ms, ignore remainder //VR Staggering + If(LLess(Local0, \VRSD)) { //Do not sleep if already past the delay requirement //VR Staggering + // Delay for power ramp using Timer Based Sleep //VR Staggering + Sleep(Subtract(\VRSD, Local0)) //VR Staggering + } //VR Staggering + + \_SB.PCI0.LPCB.H_EC.ECWT(One, RefOf(\_SB.PCI0.LPCB.H_EC.SPT2)) + \_SB.PCI0.LPCB.H_EC.ECMD (0x2E) + + Store(Timer(), \LONT) // Update the global Last ON Method Timer //VR Staggering + } + } + Method(_OFF, 0) + { + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.ECAV)),1)) { // Check If EC driver loaded + Add(\_SB.PCI0.SAT0.MBR6,0x218 ,Local0) + OperationRegion(PSTS, SystemMemory, Local0, 0x18) + Field(PSTS, DWordAcc, NoLock, Preserve) { + Offset(0x0), + CMST, 1, //PxCMD.ST + CSUD, 1, //PxCMD.SUD + , 2, + CFRE, 1, //PxCMD.FRE + Offset(0x10), + SDET, 4, + Offset(0x14), + CDET, 4 //PxSCTL.DET + } + If(LOr(LEqual(SDET, 1), LEqual(SDET, 3))){ //Offline flow only if Device detected and Phy not offline + //Clear ST (PxCMD.ST) + Store(0, CMST) + //Clear FRE + Store(0, CFRE) + //Clear SUD (PxCMD.SUD) + Store(0, CSUD) + //Set DET to 4 (PxSCTL.DET) + Store(4, CDET) + Sleep(16) + //Wait until PxSSTS.DET == 4 + While(LNotEqual(SDET, 4)){ + Sleep(16) + } + } + //Clear SATA_CABLE_PWR_EN and Send EC UpdateDevPwr - 0x2C + \_SB.PCI0.LPCB.H_EC.ECWT(Zero, RefOf(\_SB.PCI0.LPCB.H_EC.SPT2)) + \_SB.PCI0.LPCB.H_EC.ECMD (0x2E) + } + Store(Timer(), ^OFTM) // Store time when Disk turned OFF(non-zero OFTM indicate minimum 50ms requirement does apply when _ON called next time) + } + } // End P2PR + + Name(_PR0, Package(){P2PR}) + Name(_PR3, Package(){P2PR}) + + } //End PRT2 + + // PRT3 + Scope(PRT3) { + +// RCG0 : BIT2BIT3 : 00 - Disabled 01 - 1.5Minicard(GPIO83) 10:3.3Minicard(GPIO85) + PowerResource(P3PR, 0, 0){ + Method(_STA){ + if(LEqual(And(RCG0,0xC),0x04)){ // 1.5Minicard GPIO83 + Return(\_SB.RDGP(83)) + } + if(LEqual(And(RCG0,0xC),0x08)){ // 3.3Minicard GPIO85 + Return(\_SB.RDGP(85)) + } + Return(0x00) // Disabled + } + Method(_ON, 0) + { + if(LEqual(And(RCG0,0xC),0x04)){ // 1.5Minicard GPIO83 + SGON(83, One) // VR stagger GPIO83 to high to power on device + } + if(LEqual(And(RCG0,0xC),0x08)){ // 3.3Minicard GPIO85 + SGON(85, One) // VR stagger GPIO85 to high to power on device + } + } + Method(_OFF, 0) + { + Add(\_SB.PCI0.SAT0.MBR6,0x298 ,Local0) + OperationRegion(PSTS, SystemMemory, Local0, 0x18) + Field(PSTS, DWordAcc, NoLock, Preserve) { + Offset(0x0), + CMST, 1, //PxCMD.ST + CSUD, 1, //PxCMD.SUD + , 2, + CFRE, 1, //PxCMD.FRE + Offset(0x10), + SDET, 4, + Offset(0x14), + CDET, 4 //PxSCTL.DET + } + If(LOr(LEqual(SDET, 1), LEqual(SDET, 3))){ //Offline flow only if Device detected and Phy not offline + //Clear ST (PxCMD.ST) + Store(0, CMST) + //Clear FRE + Store(0, CFRE) + //Clear SUD (PxCMD.SUD) + Store(0, CSUD) + //Set DET to 4 (PxSCTL.DET) + Store(4, CDET) + Sleep(16) + //Wait until PxSSTS.DET == 4 + While(LNotEqual(SDET, 4)){ + Sleep(16) + } + } + + if(LEqual(And(RCG0,0xC),0x04)){ // 1.5Minicard GPIO83 + \_SB.WTGP(83,0) + Sleep(16) // Delay for power ramp + } + if(LEqual(And(RCG0,0xC),0x08)){ // 3.3Minicard GPIO85 + \_SB.WTGP(85,0) + Sleep(16) // Delay for power ramp + } + } + } // End P2PR + + Name(_PR0, Package(){P3PR}) + Name(_PR3, Package(){P3PR}) + + } //End PRT3 + + + // + // _DSM Device Specific Method supporting AHCI DEVSLP + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // Arg3: Package Parameters + // + Name(DRV, 0) // Storage for _DSM Arg3 parameter 0 + Name(PWR, 0) // Storage for _DSM Arg3 parameter 1 + + Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + If (LEqual(Arg0, ToUUID ("E4DB149B-FCFE-425b-A6D8-92357D78FC7F"))) { + // + // Switch by function index + // + Switch (Arg2) { + Case (0) { + // Standard query - A bitmask of functions supported + // Supports function 0-3 + Return(0x0f) + } + Case (1) { + // Query Device IDs (Addresses) of children where drive power and/or DevSleep are supported. + // LPT-LP SATA HBA provides autonomous link (DevSleep) support, return a package of 0 elements + Return( Package(){}) // SATA HBA provides native DevSleep + } + // + // Control power to device. + // + Case (2) { + Store(ToInteger(DerefOf(Index(Arg3, Zero))), DRV) + Store(ToInteger(DerefOf(Index(Arg3, One))), PWR) + + Switch(DRV){ + Case (Ones){ + // Turn on drive and link power to all drives. Note that even though + If(PWR){ // Applying Power + //^PRT0.P0PR._ON() // apply power to port 0 + \_SB.PCI0.SAT0.PRT1.P1PR._ON() // apply power to port 1 + \_SB.PCI0.SAT0.PRT2.P2PR._ON() // apply power to port 2 + } + } + } //Switch(DRV) + Return (0) + } //Case (2) + // + // Current status of Device/Link of Port + // + Case (3){ + Store(ToInteger(DerefOf(Index(Arg3, Zero))), DRV) + Switch(DRV){ + Case (0x0000FFFF){ // SATA Port 0 + // Bit0 => Device power state + Store(1, Local0) // always ON + Return (Local0) + } + Case (0x0001FFFF){ // SATA Port 1 + // Bit0 => Device power state + If(LEqual(\_SB.PCI0.SAT0.PRT1.P1PR._STA(), 0)){ + Store(0, Local0) + }Else{ + Store(1, Local0) + } + Return (Local0) + } + Case (0x0002FFFF){ // SATA Port 2 + // Bit0 => Device power state + If(LEqual(\_SB.PCI0.SAT0.PRT2.P2PR._STA(), 0)){ + Store(0, Local0) + }Else{ + Store(1, Local0) + } + Return (Local0) + } + Default { // Invalid SATA Port - error + Return (Ones) + } + } + } + Default { + Return (0) + } + } + } Else { // UUID does not match + Return (0) + } + } //Method(_DSM) + + } //Scope(\_SB.PCI0.SAT0) + +// SATA - END + +//USB - START + Scope(\_SB.PCI0.XHC){ + + Method(_S0W, 0) + { // PMEs can be generated from D3(hot) + Return(3) + } // End _S0W + } + + Scope(\_SB.PCI0.XHC.RHUB){ //USB XHCI RHUB + Method(_PS0,0,Serialized) + { + Store(0x00,USPP) + } + Method(_PS2,0,Serialized) + { + + OperationRegion (XHCM, SystemMemory, And(MEMB,0xFFFF0000), 0x600) + Field (XHCM, DWordAcc, NoLock, Preserve) + { + Offset(0x2), + XHCV,16, + Offset(0x480), + HP01, 1, // HS port 1 + Offset(0x490), + HP02, 1, // HS port 2 + Offset(0x510), + SP00, 1, // SS port 0 + Offset(0x520), + SP01, 1, // SS port 1 + } + If(LEqual(XHCV,0xFFFF)) // Controller in D3Hot(MEM_BASE not decoded) + { + Return() + } + If(LAnd(LEqual(HP01,0x00),LEqual(SP00,0x00))) // USB(HS1 : 0x480 /SS0 : 0x510) + { + Or(USPP,0x02, USPP) + } + If(LAnd(LEqual(HP02,0x00),LEqual(SP01,0x00))) // USB(HS2 : 0x490 / SS1 : 0x520) + { + Or(USPP,0x04, USPP) + } + } // End of PS2 method + Method(_PS3,0,Serialized) + { + } // End of PS3 method + } + +If(LNotEqual(And(XHPR,0xF),0x0)){ + Scope(\) { + PowerResource(PX01, 0, 0){ // power rail for USB3.0 ports 1 - GPIO 13 + Method(_STA){ + If(LEqual(\_SB.RDGP(13),1)) { //GPIO13 + Return(0x01) + } Else { + Return(0x00) + } + } + Method(_ON, 0) + { // Turn on + SGON(13, One) // VR stagger GPIO13 to high to power on device + } + + Method(_OFF, 0) + { // Turn off + \_SB.WTGP(13,0) + } + } // End PX01 + } +} +If(LNotEqual(And(XHPR,0xF0),0x0)){ + Scope(\) { + PowerResource(PX02, 0, 0){ // power rail for USB3.0 ports 2 - GPIO 43 + Method(_STA){ + If(LEqual(\_SB.RDGP(43),1)) { //GPIO43 + Return(0x01) + } Else { + Return(0x00) + } + } + Method(_ON, 0) + { // Turn on + SGON(43, One) // VR stagger GPIO43 to high to power on device + } + + Method(_OFF, 0) + { // Turn off + \_SB.WTGP(43,0) + } + } // End PX02 + + } +} + +if(LEqual(And(RCG0,2),2)) +{ + // USB Camera RTD3 support is enabled + Scope(\_SB.PCI0.XHC.RHUB.HS04){ + PowerResource(PX04, 0, 0){ // power rail for USB2.0 Port 4 - GPIO 25 + Method(_STA){ + If(LEqual(\_SB.RDGP(25),1)) { //GPIO25 + Return(0x01) + } Else { + Return(0x00) + } + } + Method(_ON, 0) + { // Turn on + SGON(25, One) // VR stagger GPIO25 to high to power on device + } + + Method(_OFF, 0) + { // Turn off + \_SB.WTGP(25,0) + } + } // End PX04 + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + Return(Package(){\_SB.PCI0.XHC.RHUB.HS04.PX04}) + } // End of Method _PR0 + Method(_PR2, Zero, NotSerialized, 0, PkgObj) + { + Return(Package(){\_SB.PCI0.XHC.RHUB.HS04.PX04}) + } // End of Method _PR2 + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + Return(Package(){\_SB.PCI0.XHC.RHUB.HS04.PX04}) + } // End of Method _PR3 + } // Scope(\_SB.PCI0.XHC.RHUB.HS04) +} + +If(LEqual(And(XHPR,0xF),0x01)) +{ + Scope(\_SB.PCI0.XHC.RHUB.HS01){ + Name(_PR0, Package(){\PX01}) + Name(_PR2, Package(){\PX01}) + Name(_PR3, Package(){\PX01}) + } +} + +If(LEqual(And(XHPR,0xF0),0x10)){ + Scope(\_SB.PCI0.XHC.RHUB.HS02){ + Name(_PR0, Package(){\PX02}) + Name(_PR2, Package(){\PX02}) + Name(_PR3, Package(){\PX02}) + } +} + +If(LEqual(And(XHPR,0xF),0x02)){ + Scope(\_SB.PCI0.XHC.RHUB.SSP1){ + Name(_PR0, Package(){\PX01}) + Name(_PR2, Package(){\PX01}) + Name(_PR3, Package(){\PX01}) + } // End of Scope(\_SB.PCI0.XHC.RHUB.SSP1) +} + +If(LEqual(And(XHPR,0xF0),0x20)){ + Scope(\_SB.PCI0.XHC.RHUB.SSP2){ + Name(_PR0, Package(){\PX02}) + Name(_PR2, Package(){\PX02}) + Name(_PR3, Package(){\PX02}) + } // End of Scope(\_SB.PCI0.XHC.RHUB.SSP2) +} +//USB - END +// Serial IO Start + +//Power Resource for Audio Codec +Scope(\_SB.PCI0) +{ + PowerResource(PAUD, 0, 0) { + + Name(PSTA, One) // Physical Power Status of Codec 0 - OFF; 1-ON + Name(ONTM, Zero) // 0 - Not in Speculative ON ; Non-Zero - elapsed time in Nanosecs after Physical ON + + Name(_STA, One) // PowerResource Logical Status 0 - OFF; 1-ON + + Method(_ON, 0){ + Store(One, _STA) // Set Logocal power state + PUAM() // Tansition Physical state to match current logical state + } // End _ON + + Method(_OFF, 0){ + Store(Zero, _STA) // Set the current power state + PUAM() // Tansition Physical state to match current logical state + } // End _OFF + + // PUAM - Power Resource User Absent Mode for onboard Audio CODEC + // Arguments: + // + // Uses: + // _STA - Variable updated by Power Resource _ON/_OFF methods + // \UAMS - Variable updated by GUAM method to show User absent/Present + // ONTM - Local variable to store ON time during Speculative ON + // ______________________________ + // | Inputs | Outputs | + // ______________________________ + // | _STA | \UAMS | GPIO | ONTM | + // ______________________________ + // | 1 | 0 | ON | !0 | + // | 1 | !0 | ON | !0 | + // | 0 | 0 | ON | !0 | + // | 0 | !0 | OFF | 0 | + // ______________________________ + + Method(PUAM, 0, Serialized) + { + If (LAnd(LEqual(^_STA, Zero), LNotEqual(\UAMS, Zero))) { //New state = OFF (_STA ==0 && \UAMS != 0) + If(LEqual(\_SB.RDGP(76), One)) { //skip if Power Resource is already in OFF + //Device OFF + // Drive GPIO 76 to Low + \_SB.WTGP(76, Zero) // Remove CODEC Power + Store(Zero, ^PSTA) + Store(Zero, ^ONTM) + } + } Else { // New state = ON (_STA=1) or (_STA=0 and \UAMS=0) + If(LNotEqual(^PSTA, One)) { //skip if Power Resource is already in ON + SGON(76, One) // VR stagger GPIO76 to High to power on device + Store(One, ^PSTA) + Store(Timer(), ^ONTM) // Start the timer for this PR + } + } // Turn power on + } //PUAM + } //PAUD +} //Scope(\_SB.PCI0) + +If(LNot(HDAD)) { // Check Funtion disable register that gets updated depending on setup option + Scope(\_SB.PCI0.HDEF) { + + Method(_PS0,0,Serialized) // D0 Method for HD-A Controller + { + If(LEqual(\_SB.PCI0.PAUD.ONTM, Zero)){ + Return() + } + + // + // Make sure "D0 delay" (AUDD) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // AUDD: Time required for device to be ready after power on + // Local1 = AUDD + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.PAUD.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(AUDD, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) { //Do not sleep if already past the delay requirement audio + // Delay for device init + Sleep(Subtract(Local1, Local0)) //Sleep (AUDD + VRRD - time elapsed) + } + } + Method(_PS3,0,Serialized) // D3 Method for HD-A Controller(Dummy routine to support D3 state) + { + } + + Name(_PR0, Package(){\_SB.PCI0.PAUD}) + } + }// IF(HDAD) + +// ADSP device +if(LNot(ADSD)){ // Check Funtion disable register that gets updated depending on setup option + Scope(\_SB.PCI0.ADSP) { + + // D0 Method for ADSP Controller + Method(_PS0,0,Serialized) // D0 Method for ADSP Controller + { + + If(LEqual(\_SB.PCI0.PAUD.ONTM, Zero)) { + Return() + } + + // + // Make sure "D0 delay" (DSPD) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // DSPD: Time required for device to be ready after power on + // Local1 = DSPD + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.PAUD.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(DSPD, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) { //Do not sleep if already past the delay requirement audio + // Delay for device init + Sleep(Subtract(Local1, Local0)) //Sleep (DSPD + VRRD - time elapsed) + } + } + Method(_PS3,0,Serialized) // D3 Method for ADSP Controller(Dummy routine to support D3 state) + { + } + + Name(_PR0, Package(){\_SB.PCI0.PAUD}) + } +}// if(ADSD) + +// I2C0 +Scope(\_SB.PCI0.I2C0) { // I2C0 + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + Store(0, Local0) // BIT0 : ADSP Disabled BIT1 : SHUB Disabled + If (LEqual(ADSD,1)){ // Update Local0 BIT0 if ADSP disabled in RCBA function disable register(implies disabled in setup) + Or(0x01,Local0,Local0) + } + If(LEqual(And(SDS0,0x01), 0x00)) { // Update Local0 BIT1 if SHUB disabled in setup + Or(0x02,Local0,Local0) + } + + If(LEqual(Local0,0x0)){ // Both SHUB and ADSP enabled + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,\_SB.PCI0.I2C1.PXTC,\_SB.PCI0.PAUD}) + } + If(LEqual(Local0,0x01)){ // Only SHUB enabled + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,\_SB.PCI0.I2C1.PXTC}) + } + If(LEqual(Local0,0x02)){ // Only ADSP codec enabled + Return(Package(){\_SB.PCI0.PAUD}) + } + Return(Package(){}) // Both SHUB and ADSP codec disabled + } + // D0 Method for I2C0 Controller(Called by _PS0) + Method(PS0X,0,Serialized) + { + Sleep(I20D) // If required add delay in controller to gurantee longest delaying device have time + // Drive GIO49 High - routed to Sensor HUB STOP mode + \_SB.WTGP(49,1) + Sleep(16) + } + + // D3 Method for I2C0 Controller(Called by _PS3) + Method(PS3X,0,Serialized) + { + + // Drive GIO49 Low - routed to Sensor HUB STOP mode + \_SB.WTGP(49,0) + Sleep(16) + } +} // \_SB.PCI0.I2C0 + +If (AND(LEqual(CODS, 0),LNot(ADSD))){ // CODEC 0 : RealTek + Scope(\_SB.PCI0.I2C0.ACD0) + { + Name(_PR0,Package(){\_SB.PCI0.PAUD}) + } +} + +If (AND(LEqual(CODS, 1),LNot(ADSD))){ // CODEC 1 : Cirrus + Scope(\_SB.PCI0.I2C0.ACD1) + { + Name(_PR0,Package(){\_SB.PCI0.PAUD}) + } +} + +If (AND(LEqual(CODS, 2),LNot(ADSD))){ // CODEC 2 : Idt + Scope(\_SB.PCI0.I2C0.ACD2) + { + Name(_PR0,Package(){\_SB.PCI0.PAUD}) + } +} + +Scope(\_SB.PCI0.I2C0.SHUB) +{ + // D0 Method Hook for I2C1 Controller(Called by _PS0) + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C0.SHUB.PSEN.ONTM,Zero)) { + Return() + } + + // Make sure "D0 delay" (IC0D) delay is elapsed before returning _PS0 + Divide(Subtract(Timer(), \_SB.PCI0.I2C0.SHUB.PSEN.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + If(LLess(Local0, IC0D)) //Do not sleep if already past the delay requirement 100ms for SensorHub + { + // Delay for power ramp + Sleep(Subtract(IC0D, Local0)) //Sleep (100 - time elapsed) + } + } + Method(_PS3,0,Serialized) + { + } + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(And(LEqual(RIC0,1),LEqual(\_SB.RDGP(44), 0x01))) { // Enabled in Setup and not in DFU mode + Return(Package(){PSEN,\_SB.PCI0.I2C1.PXTC}) + } Else { + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(And(LEqual(RIC0,1),LEqual(\_SB.RDGP(44), 0x01))) { // Enabled in Setup and not in DFU mode + Return(Package(){PSEN,\_SB.PCI0.I2C1.PXTC}) + } Else { + Return(Package(){}) + } + } + + PowerResource(PSEN, 0, 0) { + Name(ONTM, Zero) // On Timer + + Method(_STA){ + If(LEqual(SHSB, 0)){ + If(LEqual(\_SB.RDGP(46),1)) { //GPIO89 NOTE: 1=> ON; 0=> OFF + Return(0x01) + } + }Else{ + If(LEqual(\_SB.RDGP(70),1)) { //GPIO89 NOTE: 1=> ON; 0=> OFF + Return(0x01) + } + } + Return(0x00) + } + + Method(_ON, 0){ + If(And(LEqual(RIC0,1),LEqual(\_SB.RDGP(44), 0x01))) { // Enabled in Setup and not in DFU mode + // Drive GPIO 46 High + If(LEqual(SHSB, 0)){ + If(LEqual(SGON(46, One), One)) { // VR stagger GPIO46 to high to power on device + Store(Timer(), ^ONTM) // Start the timer + \_SB.GP2B(14, One) // Enable int line from sensor hub. GPIO14 is PIRQM(IOAPIC ln28) + } + }Else{ + If(LEqual(SGON(70, One), One)) { // VR stagger GPIO70 to high to power on device + Store(Timer(), ^ONTM) // Start the timer + \_SB.GP2B(14, One) // Enable int line from sensor hub. GPIO14 is PIRQM(IOAPIC ln28) + } + } + } // End if - Enabled in Setup and not in DFU mode + } // End _ON + + Method(_OFF, 0){ + If(And(LEqual(RIC0,1),LEqual(\_SB.RDGP(44), 0x01))) { // Enabled in Setup and not in DFU mode + // Mask interrupt from Sensorhub GPIPIRQ2IOXAPIC: GPI PIRQ[X:I] to IOxAPIC[39:24] Enable + \_SB.GP2B(14, Zero) // GPIO14 is PIRQM(IOAPIC ln28) + If(LEqual(SHSB, 0)){ + \_SB.WTGP(46, Zero) // Remove Device Power + }Else{ + \_SB.WTGP(70, Zero) + } + Store(Zero, ^ONTM) + Store(Zero , ^ONTM) + } // End if - Enabled in Setup and not in DFU mode + } // End _OFF + } //PSEN +} // Scope(SHUB) + + //Merge TouchPanel/Touch Pad Power control - I2C Sensors Need to Turn ON/OFF at same time + Scope(\_SB.PCI0.I2C1){ + + Method(PS0X,0,Serialized) + { + // If required add delay in controller to gurantee longest delaying device have time + Sleep(I21D) + } + + Method(PS3X,0,Serialized) + { + } + + PowerResource(PXTC, 0, 0){ // power rail for Touch Panel and Touchpad GPIO 89 + + Name(ONTM, 0) // 0 - Not in Speculative ON ; Non-Zero - elapsed time in Nanosecs after Physical ON + + Method(_STA){ + If(LOr(LEqual(And(SDS1,0x0800), 0x0800),LEqual(And(SDS1,0x1000), 0x1000))){ //Precision Enabled + If(LEqual(\_SB.RDGP(89),1)) { //GPIO89 NOTE: 1=> ON; 0=> OFF + Return(0x01) + } Else { + Return(0x00) + } + } Else{ + If(LAnd(LEqual(\_SB.RDGP(88),1), LEqual(\_SB.RDGP(89),1))) { //GPIO88/89 NOTE: 1=> ON; 0=> OFF + Return(0x01) + } Else { + Return(0x00) + } + } + } + Method(_ON, 0) + { // Turn on + If(LOr(LEqual(And(SDS1,0x0800), 0x0800),LEqual(And(SDS1,0x1000), 0x1000))){ //Precision Enabled + If(LOr(LEqual(\_SB.RDGP(89),0), LEqual(\_SB.RDGP(52),0))) { //GPIO88 NOTE: 1=> ON; 0=> OFF + \_SB.WTGP(52,1) //DeAssert GPIO RST + SGON(89, One) // VR stagger GPIO89 to high to power on device + Store(Timer(), ONTM) + //Enable int line from touch screen + \_SB.GP2A(50, One) //TPL0 + } + }Else { + If(LOr(LOr(LEqual(\_SB.RDGP(88),0), LEqual(\_SB.RDGP(89),0)), LEqual(\_SB.RDGP(52),0))) { //GPIO88/89 NOTE: 1=> ON; 0=> OFF + \_SB.WTGP(52,1) //DeAssert GPIO RST + SGON(88, One) // VR stagger GPIO88 to high to power on device + SGON(89, One) // VR stagger GPIO89 to high to power on device + Store(Timer(), ONTM) + //Enable int line from touch screen and Touch pad + \_SB.GP2A(50, One) //TPL0 + \_SB.GP2A(55, One) //TPD0/1 + } + } + } + + Method(_OFF, 0) + { // Turn off + If(LOr(LEqual(And(SDS1,0x0800), 0x0800),LEqual(And(SDS1,0x1000), 0x1000))){ //Precision Enabled + //mask interrupt from Touch Screen GPIPIRQ2IOXAPIC: GPI PIRQ[X:I] to IOxAPIC[39:24] Enable + \_SB.GP2A(50, Zero) //TPL0 + \_SB.WTGP(89,0) + \_SB.WTGP(52,0) //GPIO RST to Touch Panel + Store(Zero , ^ONTM) + } + Else{ + //mask interrupt from Touch Screen and Touch Pad GPIPIRQ2IOXAPIC: GPI PIRQ[X:I] to IOxAPIC[39:24] Enable + \_SB.GP2A(50, Zero) //TPL0 + \_SB.GP2A(55, Zero) //TPD0/1 + \_SB.WTGP(88,0) + \_SB.WTGP(89,0) + \_SB.WTGP(52,0) //GPIO RST to Touch Panel + Store(Zero , ^ONTM) + } + } + } // End PXTC + + Scope(TPL0){ + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + + // + // Make sure "D0 delay" (IC1D) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1D: Time required for device to be ready after power on + // Local1 = IC1D + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1D, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1D + VRRD - time elapsed) + } + } + + Method(_PS3,0,Serialized) + { + } + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x01), 0x01)) + { + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,PXTC}) + } Else { + Return(Package() {}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x01), 0x01)) + { + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,PXTC}) + } Else { + Return(Package() {}) + } + } + } // End of Scope(TPL0) + + Scope(TPD0){ + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x04), 0x04)) + { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0004), 0x0004)) + { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + } + + Scope(TPL1){ + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // Make sure "D0 delay" (IC1D) delay is elapsed before returning _PS0 + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + If(LLess(Local0, IC1D)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(IC1D, Local0)) //Sleep (IC1D - time elapsed) + } + } + + Method(_PS3,0,Serialized) + { + } + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0002), 0x0002)) + { + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,PXTC}) + }Else{ + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0002), 0x0002)) + { + Return(Package(){\_SB.PCI0.I2C0.SHUB.PSEN,PXTC}) + }Else{ + Return(Package(){}) + } + } + } + + Scope(TPD1){ + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // + // Make sure "D0 delay" (IC1S) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1S: Time required for device to be ready after power on + // Local1 = IC1S + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1S, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1S + VRRD - time elapsed) + } + } + + Method(_PS3,0,Serialized) + { + } + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x08), 0x08)) { + Return(Package(){PXTC}) + } Else { + Return(Package() {}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x08), 0x08)) { + Return(Package(){PXTC}) + } Else { + Return(Package() {}) + } + } + }// End of Scope(TPD1) + + //------------------------------ + // NTRIG Digitizer Touch Panel + //------------------------------ + Scope(TPL2){ + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // + // Make sure "D0 delay" (IC1D) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1D: Time required for device to be ready after power on + // Local1 = IC1D + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1D, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1D + VRRD - time elapsed) + } + } + + Method(_PS3,0,Serialized) + { + } + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0020), 0x0020)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0020), 0x0020)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + }// End of Scope(TPL2) + + //------------------------ + // EETI Touch Panel + //------------------------ + Scope(TPL3){ + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // Make sure "D0 delay" (IC1D) delay is elapsed before returning _PS0 + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + If(LLess(Local0, IC1D)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(IC1D, Local0)) //Sleep (IC1D - time elapsed) + } + } + + Method(_PS3,0,Serialized) + { + } + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0040), 0x0040)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0040), 0x0040)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + }// End of Scope(TPL3) + + + //------------------------ + // Alps touchpad + //------------------------ + Scope(TPD2){ + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // + // Make sure "D0 delay" (IC1S) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1S: Time required for device to be ready after power on + // Local1 = IC1S + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1S, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1S + VRRD - time elapsed) + } + } + + Method(_PS3,0,Serialized) + { + } + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0080), 0x0080)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0080), 0x0080)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + }// End of Scope(TPD2) + + //------------------------ + // Cypress touchpad + //------------------------ + Scope(TPD3){ + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // + // Make sure "D0 delay" (IC1S) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1S: Time required for device to be ready after power on + // Local1 = IC1S + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1S, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1S + VRRD - time elapsed) + } + } + + Method(_PS3,0,Serialized) + { + } + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0100), 0x0100)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0100), 0x0100)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + }// End of Scope(TPD3) + + //------------------------ + // Elantech Precision touchpad + //------------------------ + Scope(TPD7){ + + // + // Delay for Touchpanel & TouchPad - Both share same I2C bus + // + Method(PS0X,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // + // Make sure "D0 delay" (IC1S) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1S: Time required for device to be ready after power on + // Local1 = IC1S + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1S, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1S + VRRD - time elapsed) + } + } + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0800), 0x0800)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x0800), 0x0800)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + }// End of Scope(TPD7) + + //------------------------ + // Synaptics Precision touchpad + //------------------------ + Scope(TPD8){ + + // + // Delay for Touchpanel & TouchPad - Both share same I2C bus + // + Method(PS0X,0,Serialized) + { + If(LEqual(\_SB.PCI0.I2C1.PXTC.ONTM,Zero)) { + Return() + } + // + // Make sure "D0 delay" (IC1S) delay is elapsed before returning _PS0 + // Local0: Elapse time since the _ON method + // VRRD: VR Rampup Delay + // IC1S: Time required for device to be ready after power on + // Local1 = IC1S + VRRD: Need to incorporate VRRD since the _ON method no longer has VR Rampup Delay + // So only need sleep for (Local1 - Local0), the amount of time remaining since the _ON method + // + Divide(Subtract(Timer(), \_SB.PCI0.I2C1.PXTC.ONTM), 10000, , Local0) //Store Elapsed time in ms, ignore remainder + Add(IC1S, VRRD, Local1) // Incorporate VR Rampup Delay + If(LLess(Local0, Local1)) //Do not sleep if already past the delay requirement 100ms for Touchpanel + { + // Delay for power ramp + Sleep(Subtract(Local1, Local0)) //Sleep (IC1S + VRRD - time elapsed) + } + } + + Method(_PR0, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x1000), 0x1000)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + Method(_PR3, Zero, NotSerialized, 0, PkgObj) + { + If(LEqual(And(SDS1,0x1000), 0x1000)) { + Return(Package(){PXTC}) + }Else{ + Return(Package(){}) + } + } + }// End of Scope(TPD8) + }// Scope(\_SB.PCI0.I2C1) + +//Serial IO End + //GPE Event handling - Start + Scope(\_GPE) { + + Method(_L11) { // Zpodd GPIO handler + Store(1,\GO17) // Clear GPI ownership to stop SCI flooding + If(LEqual(\_SB.PCI0.SAT0.PRT1.UDSM, Zero)) { + Notify(\_SB.PCI0.SAT0.PRT1, 2) // Device Wake to Device (Windows) + }Else{ + Notify(\_SB.PCI0.SAT0, 0x81) //Notify Port 1 to wake from DSM method + } // \_SB.PCI0.SAT0.UDSM + } + // + // GPIO8 PCIE slot 3 wake event + // + Method(_L08) { + // PCIe WAKE# + If(\_SB.PCI0.RP03.WKEN){ + //GPIO_OWN to GPIO Driver to stop SCI flooding + Store(1, \GO08) + Notify(\_SB.PCI0.RP03, 0x02) // DeviceWake + } + } + // + // GPIO45(0x2D) PCIE slot 4 wake event + // + Method(_L2D) { + // PCIe WAKE# + If(\_SB.PCI0.RP04.WKEN){ + //GPIO_OWN to GPIO Driver to stop SCI flooding + Store(1, \GO45) + Notify(\_SB.PCI0.RP04, 0x02) // DeviceWake + } + } + + // + // GPIO51(0x33) PCIE slot 5 wake event + // + Method(_L33) { + // PCIe WAKE# + If(\_SB.PCI0.RP05.WKEN){ + //GPIO_OWN to GPIO Driver to stop SCI flooding + Store(1, \GO51) + Notify(\_SB.PCI0.RP05, 0x02) // DeviceWake + } + } + } //Scope(\_GPE) + +If(LEqual(RWAG,0)) {// standard board configuration, no W/A bue wires for slot 1 or 6 + //SDIO Reset support + Scope(\_SB.PCI0.SDHC) { + // D0 Method for SDHC + Method(PS0X,0,Serialized) + { + // Drive GPIO77 High - 1: No GPIO RST to on board mPCIe/NGFF_WIFI + \_SB.WTGP(77,1) + } + } + + Scope(\_SB.PCI0.SDHC.WI01) { + // D0 Method for WiFi + Method(PS0X,0,Serialized) + { + // Drive GPIO77 High - 1: No GPIO RST to on board mPCIe/NGFF_WIFI + \_SB.WTGP(77,1) + } + // D3 Method for WiFi + Method(PS3X,0,Serialized) + { + // Drive GPIO77 Low - 0: GPIO RST to on board mPCIe/NGFF_WIFI + \_SB.WTGP(77,0) + } + } //\_SB.PCI0.SDHC.WI01 +} + + Scope(\_SB.PCI0.XHC){ //USB XHCI + + Name(UPWR,0) + Name(USPP,0) + // Bit 0 : USB SD Card Reader + // Bit 1 : USB(HS1 : 0x480 /SS0 : 0x510) + // BIT 2 : USB(HS2 : 0x490 / SS1 : 0x520) + + + Method(DUAM,0,Serialized) + { + + OperationRegion (XHCM, SystemMemory, And(MEMB,0xFFFF0000), 0x600) + Field (XHCM, DWordAcc, NoLock, Preserve) + { + Offset(0x2), + XHCV,16, + Offset(0x480), + HP01, 1, // HS port 1 + Offset(0x490), + HP02, 1, // HS port 2 + Offset(0x510), + SP00, 1, // SS port 0 + Offset(0x520), + SP01, 1, // SS port 1 + } + + if(LNotEqual(\UAMS,0x00)) // User not present + { + Store(0x00,UPWR) + // Enterng CS, Remove power if SD card not present + + If(LEqual(XHCV,0xFFFF)) // Controller in D3Hot(MEM_BASE not decoded) + { + If(And(USPP,0x02)) // USB(HS1 : 0x480 /SS0 : 0x510) + { + \_SB.WTGP(13,0) + Or(UPWR,0x02, UPWR) + } + If(And(USPP,0x04)) // USB(HS2 : 0x490 / SS1 : 0x520) + { + \_SB.WTGP(43,0) + Or(UPWR,0x04, UPWR) + } + }Else{ // If(Lequal(XHCV,0xFFFF)) + If(LAnd(LEqual(HP01,0x00),LEqual(SP00,0x00))) // USB(HS1 : 0x480 /SS0 : 0x510) + { + \_SB.WTGP(13,0) + Or(UPWR,0x02, UPWR) + } + If(LAnd(LEqual(HP02,0x00),LEqual(SP01,0x00))) // USB(HS2 : 0x490 / SS1 : 0x520) + { + \_SB.WTGP(43,0) + Or(UPWR,0x04, UPWR) + } + }// If(Lequal(XHCV,0xFFFF)) + }Else{ //if(LNotEqual(\UAMS,0x00)) + + // Exiting CS , Apply power if power removed + if(And(UPWR,0x02)) // USB(HS1 : 0x480 /SS0 : 0x510) + { + \_SB.WTGP(13,1) + } + if(And(UPWR,0x04)) // USB(HS2 : 0x490 / SS1 : 0x520) + { + \_SB.WTGP(43,1) + } + } //if(LNotEqual(\UAMS,0x00)) // User not present + } // End of DUAM + } +} //If(LAnd(LEqual(BID,BWT1),LEqual(RTD3,1))) +} // End SSDT + diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.asl b/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.asl new file mode 100644 index 0000000..bd69431 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.asl @@ -0,0 +1,134 @@ + +DefinitionBlock ( + "SsdtZpOdd.aml", + "SSDT", + 1, + "Intel", + "zpodd", + 0x1000 + ) +{ +External(PFLV) +External(FDTP) +External(GPE3) +External(\GL00) +External(\GL08) +External(GPS3) +External(\_SB.PCI0.SAT0.PRT2, DeviceObj) +External(\GIV0) +External(RTD3, IntObj) + + If(LEqual(RTD3, Zero)) + { + Scope(\_SB.PCI0.SAT0.PRT2) + { + + // + // _DSM Device Specific Method supporting SATA ZPODD function + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // Arg3: Package Parameters + // + Method (_DSM, 4, NotSerialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + If (LEqual(Arg0, ToUUID ("bdfaef30-aebb-11de-8a39-0800200c9a66"))) { + // + // Switch by function index + // + Switch (ToInteger(Arg2)) { + // + // Standard query - A bitmask of functions supported + // Supports function 0-5 + // + Case (0) { + switch(ToInteger(Arg1)) { + case(1) { + // + // Return - 0 (No Functions supported) for Desktop Platforms + // + If(LEqual(PFLV,FDTP)) { + Return (Buffer () {0}) + } + Return (Buffer () {0xF}) + } + Default {Return (Buffer () {0})} + } + } // Case (0) + // + // Enable ZPODD feature + // + Case (1) { + Return (1) + } // Case (1) + // + // Power Off Device + // + Case (2) { + // + // Drive GPIO to low to power off device. + // + Store(0,GPE3) + If(LEqual(And(\GL00, 0x08), 0x08)) + { + Or(\GIV0, 0x08, \GIV0) + } Else { + And(\GIV0, 0xF7, \GIV0) + } + And(\GL08, 0xEF, \GL08) + Sleep(0xC8) + Store(1,GPS3) + Store(1,GPE3) + Return (1) + } // Case (2) + // + // Power ON Device + // + Case (3) { + Store(0,GPE3) + Store(1,GPS3) + Or(\GL08, 0x10, \GL08) + Return (1) + } // Case (3) + + Default { + Return (0) + } + } // Switch (ToInteger(Arg2)) + } Else { + Return (0) + } // bdfaef30-aebb-11de-8a39-0800200c9a66 + } // _DSM + } // (\_SB.PCI0.SAT0) +// +// GPE Event Handler +// +Scope(\_GPE) { + // + // SATA_ODD_DA + // + Method(_L13) { + // + // Do nothing if Desktop platform + // + If(LEqual(PFLV,FDTP)) { + Return () + } + // + // Power on drive, disable SCI on GPI + // Disable SCI on GPIO3 (PMBASE+0x28 - BIT19) + // + Store(0,GPE3) + // + // Drive GPIO68 to High to power on device. + // + Or(\GL08, 0x10, \GL08) + // + // Notify the OSPM + // + Notify(\_SB.PCI0.SAT0, 0x82) + Return () + } +} // \_GPE +} // If(LEqual(RTD3, Zero)) +} // End SSDT diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.cif b/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.cif new file mode 100644 index 0000000..02be8d2 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.cif @@ -0,0 +1,11 @@ +<component> + name = "SsdtZpOdd" + category = ModulePart + LocalRoot = "ReferenceCode\AcpiTables\SampleCode\SsdtZpOdd\" + RefName = "SsdtZpOdd" +[files] +"SsdtZpOdd.sdl" +"SsdtZpOdd.mak" +"SsdtZpOdd.asl" +"SsdtZpOddULT.asl" +<endComponent> diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.mak b/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.mak new file mode 100644 index 0000000..81eb0d1 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.mak @@ -0,0 +1,89 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: SsdtZpOdd.mak +# +# Description: MAke file to build Aptio ACPI ASL components +# +# +#<AMI_FHDR_END> +#************************************************************************* +all : BuildZPODD + +BuildZPODD : $(BUILD_DIR)\SsdtZpOdd.ffs + +#----------------------------------------------------------------------- +# ASL compiler definition +#----------------------------------------------------------------------- +!IF "$(ACPIPLATFORM_ASL_COMPILER)"=="" +!ERROR It is an invalid path, please check your ASL compiler path. +!ENDIF + +IASL = $(ACPIPLATFORM_ASL_COMPILER) +#----------------------------------------------------------------------- +$(BUILD_DIR)\SsdtZpOdd.aml $(BUILD_DIR)\SsdtZpOddult.aml: $(BUILD_DIR)\SsdtZpOdd.asl $(BUILD_DIR)\SsdtZpOddult.asl + $(SILENT)$(IASL) -p $@ $*.asl + +$(BUILD_DIR)\SsdtZpOdd.sec $(BUILD_DIR)\SsdtZpOddult.sec: $(BUILD_DIR)\SsdtZpOdd.aml $(BUILD_DIR)\SsdtZpOddult.aml + $(GENSECTION) -I $*.aml -O $@ -S EFI_SECTION_RAW + +#Note. Expand the package with ZpOdd tables. +# DXE phase will load the tables +# and update Aml contents if provided in Acpiplatform.c + +$(BUILD_DIR)\SsdtZpOdd.ffs: $(BUILD_DIR)\SsdtZpOdd.sec $(BUILD_DIR)\SsdtZpOddult.sec + $(GENFFSFILE) -B $(BUILD_DIR) -V -o $@ -P1 <<$(BUILD_DIR)\SsdtZpOdd.pkg + +PACKAGE.INF +[.] +BASE_NAME = ZpOdd +FFS_FILEGUID = E42A76A1-D4B3-4c26-A1BB-84A3502A779F + FFS_FILETYPE = EFI_FV_FILETYPE_FREEFORM +FFS_ATTRIB_CHECKSUM = TRUE + +IMAGE_SCRIPT = +{ + Compress (dummy) { + $(PROJECT_DIR)\$(BUILD_DIR)\SsdtZpOdd.sec + $(PROJECT_DIR)\$(BUILD_DIR)\SsdtZpOddult.sec + } +} +<<KEEP + +#-----------------------------------------------------------------------# +# Process SG asl files +#-----------------------------------------------------------------------# +$(BUILD_DIR)\SsdtZpOdd.asl : $(INTEL_ZPODD_ASL_FILE) + $(CP) /I$(INTEL_SSDTZPODD_DIR) /FItoken.h /C $(INTEL_ZPODD_ASL_FILE) > $(BUILD_DIR)\SsdtZpOdd.asl + +$(BUILD_DIR)\SsdtZpOddult.asl : $(INTEL_ZPODDULT_ASL_FILE) + $(CP) /I$(INTEL_SSDTZPODD_DIR) /FItoken.h /C $(INTEL_ZPODDULT_ASL_FILE) > $(BUILD_DIR)\SsdtZpOddult.asl + + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.sdl b/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.sdl new file mode 100644 index 0000000..98dbe92 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOdd.sdl @@ -0,0 +1,59 @@ +TOKEN + Name = "ZPODD_SUPPORT" + Value = "1" + Help = "Main switch to enable ZpODD support in Project" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Master = Yes + Token = "PCH_SKU" "=" "1" +End + +TOKEN + Name = "STD_ZPODD_SUPPORT" + Value = "1" + Help = "Main switch to enable Stand ZpODD support in Project" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Token = "ZPODD_SUPPORT" "=" "1" +End + +TOKEN + Name = "ULT_ZPODD_SUPPORT" + Value = "1" + Help = "Main switch to enable ULT ZpODD support in Project" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Token = "ZPODD_SUPPORT" "=" "1" +End + +PATH + Name = "INTEL_SSDTZPODD_DIR" +End + +TOKEN + Name = "INTEL_ZPODD_ASL_FILE" + Value = "$(INTEL_SSDTZPODD_DIR)\SsdtZpOdd.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_ZPODDULT_ASL_FILE" + Value = "$(INTEL_SSDTZPODD_DIR)\SsdtZpOddult.asl" + TokenType = Expression + TargetMAK = Yes +End + +MODULE + Help = "Includes SsdtZpOdd.mak to Project" + File = "SsdtZpOdd.mak" +End + +ELINK + Name = "$(BUILD_DIR)\SsdtZpOdd.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End diff --git a/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOddULT.asl b/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOddULT.asl new file mode 100644 index 0000000..dd393d4 --- /dev/null +++ b/ReferenceCode/AcpiTables/SampleCode/SsdtZpOdd/SsdtZpOddULT.asl @@ -0,0 +1,110 @@ + +DefinitionBlock ( + "SsdtZpOddult.aml", + "SSDT", + 1, + "Intel", + "zpoddult", + 0x1000 + ) +{ +External(\GO17) +External(\_SB.PCI0.SAT0.PRT1, DeviceObj) +External(RTD3, IntObj) +External(ECON, IntObj) +External(\_SB.WTGP, MethodObj) + + + If(LEqual(RTD3, Zero)) + { + Scope(\_SB.PCI0.SAT0.PRT1) + { + + // + // _DSM Device Specific Method supporting SATA ZPODD function + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index + // Arg3: Package Parameters + // + Method (_DSM, 4, NotSerialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + If (LEqual(Arg0, ToUUID ("bdfaef30-aebb-11de-8a39-0800200c9a66"))) { + // + // Switch by function index + // + Switch (ToInteger(Arg2)) { + // + // Standard query - A bitmask of functions supported + // Supports function 0-5 + // + Case (0) { + switch(ToInteger(Arg1)) { + case(1) { + // + // Return - 0 (No Functions supported) for Desktop Platforms + // + If(LEqual(ECON, Zero)) { + Return (Buffer () {0}) + } + Return (Buffer () {0xF}) + } + Default {Return (Buffer () {0})} + } + } // Case (0) + // + // Enable ZPODD feature + // + Case (1) { + Return (1) + } // Case (1) + // + // Power Off Device + // + Case (2) { + // + // Drive GPIO to low to power off device. + // + \_SB.WTGP(86,1) // Power Off the device + Store(0,\GO17) // Enable GPIO86 + Return (1) + } // Case (2) + // + // Power ON Device + // + Case (3) { + \_SB.WTGP(86,0) // Power ON Device + Store(1,\GO17) // Enable GPIO86 + Sleep(0x0A) // To turn the FET + Return (1) + } // Case (3) + + Default { + Return (0) + } + } // Switch (ToInteger(Arg2)) + } Else { + Return (0) + } // bdfaef30-aebb-11de-8a39-0800200c9a66 + } // _DSM + } // (\_SB.PCI0.SAT0) + +// +// GPE Event Handler +// +Scope(\_GPE) { + // + // GPI03 = SATA_ODD_DA + // + Method(_L11) { + If(LEqual(ECON, Zero)) { + Return () + } + + Store(1,\GO17) // Enable GPIO86 + Notify(\_SB.PCI0.SAT0, 0x81) + Return () + } +} // \_GPE +} // If(LEqual(RTD3, Zero)) +} // End SSDT diff --git a/ReferenceCode/AcpiTables/SsdtIRMT/IntelRMT.asl b/ReferenceCode/AcpiTables/SsdtIRMT/IntelRMT.asl new file mode 100644 index 0000000..a37c052 --- /dev/null +++ b/ReferenceCode/AcpiTables/SsdtIRMT/IntelRMT.asl @@ -0,0 +1,108 @@ +// +// Defined as an SSDT to be able to dynamically load based on BIOS +// setup options +// +DefinitionBlock ( + "IntelRMT.aml", + "SSDT", + 0x01, + "Intel", + "IntelRMT", + 0x1000 + ) + + +{ +External(\ADBG, MethodObj) +External(P8XH, MethodObj) +External(INSC, IntObj) + + + Scope(\_SB) + { + Device (INSD) + { + Name (_HID, "INT3398") + Name (_CID, EISAID("PNP0C02")) + Name (_UID, 0x00) + + Name (NBT1, 0) // Intel Intelr RMT Technology local variable + // Intelr RMT Modes + // 0: Exit Intelr RMT + // 1: Enter Intelr RMT Active State + // 2: Enter Intelr RMT Idle State + // 3: Enter Intelr RMT Do Not Disturb State + // 4: Enter Suspend + + Method(GNSC, 0, NotSerialized) + { + // DEBUG START // + Store(INSC, Local0) + P8XH(0,0xAA) + ADBG("GNSC: ") + ADBG(ToHexString(Local0)) + // DEBUG END // + return (INSC) + } + + Method(GNSM, 0, Serialized) + { + Store(NBT1, Local0) + // DEBUG START // + P8XH(0,0x71) + ADBG("GNSM: ") + ADBG(ToHexString(Local0)) + // DEBUG END // + Return (Local0) + } + + Method(SNSM, 1, Serialized) + { + Store(Arg0, NBT1) + Store(NBT1, Local0) + Switch(ToInteger(Local0)) + { + Case (0) + { + ADBG("case 0: ") + // 0: Exit Intelr RMT + // TODO: Add platform specific code here + } + Case (1) + { + ADBG("case 1: ") + // 1: Enter Intelr RMT Active State + // TODO: Add platform specific code here + } + Case (2) + { + ADBG("case 2: ") + // 2: Enter Intelr RMT Idle State + // TODO: Add platform specific code here + } + Case (3) + { + ADBG("case 3: ") + // 3: Enter Intelr RMT Do Not Disturb State + // TODO: Add platform specific code here + } + Case (4) + { + ADBG("case 4: ") + // 4: Enter Suspend + // TODO: Add platform specific code here + } + + } + + // DEBUG START // + P8XH(0,0x72) + ADBG("SNSM: ") + ADBG(ToHexString(Local0)) + // DEBUG END // + } + + } // Device (INSD) + + } // end \_SB scope +} // end SSDT diff --git a/ReferenceCode/AcpiTables/SsdtIRMT/SsdtIRMT.cif b/ReferenceCode/AcpiTables/SsdtIRMT/SsdtIRMT.cif new file mode 100644 index 0000000..38a2bd1 --- /dev/null +++ b/ReferenceCode/AcpiTables/SsdtIRMT/SsdtIRMT.cif @@ -0,0 +1,10 @@ +<component> + name = "SsdtIRMT" + category = ModulePart + LocalRoot = "ReferenceCode\AcpiTables\SsdtIRMT\" + RefName = "SsdtIRMT" +[files] +"SsdtIRMT.sdl" +"SsdtIRMT.mak" +"IntelRMT.asl" +<endComponent> diff --git a/ReferenceCode/AcpiTables/SsdtIRMT/SsdtIRMT.mak b/ReferenceCode/AcpiTables/SsdtIRMT/SsdtIRMT.mak new file mode 100644 index 0000000..9f2b6b7 --- /dev/null +++ b/ReferenceCode/AcpiTables/SsdtIRMT/SsdtIRMT.mak @@ -0,0 +1,80 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2014, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: SsdtIRMT.mak +# +# Description: MAke file to build Aptio ACPI ASL components +# +# +#<AMI_FHDR_END> +#************************************************************************* +all : BuildIRMT + +BuildIRMT : $(BUILD_DIR)\IntelRMT.ffs + +#----------------------------------------------------------------------- +# ASL compiler definition +#----------------------------------------------------------------------- +!IF "$(ACPIPLATFORM_ASL_COMPILER)"=="" +!ERROR It is an invalid path, please check your ASL compiler path. +!ENDIF + +IASL = $(ACPIPLATFORM_ASL_COMPILER) +#----------------------------------------------------------------------- +$(BUILD_DIR)\IntelRMT.aml : $(INTEL_IRMT_ASL_FILE) + @cl /C /EP $(INTEL_IRMT_ASL_FILE) > $(BUILD_DIR)\IntelRMT.asl + $(IASL) -p $(BUILD_DIR)\IntelRMT.aml $(BUILD_DIR)\IntelRMT.asl + +$(BUILD_DIR)\IntelRMT.sec: $(BUILD_DIR)\IntelRMT.aml + $(GENSECTION) -I $*.aml -O $@ -S EFI_SECTION_RAW + +#Note. Expand the package with PTID tables. +# DXE phase will load the tables +# and update Aml contents if provided in Acpiplatform.c + +$(BUILD_DIR)\IntelRMT.ffs: $(BUILD_DIR)\IntelRMT.sec + $(GENFFSFILE) -B $(BUILD_DIR) -V -o $@ -P1 <<$(BUILD_DIR)\IntelRMT.pkg + +PACKAGE.INF +[.] +BASE_NAME = IntelRMT +FFS_FILEGUID = CE2007C7-B389-49c5-84E3-DB36A1F0993B +FFS_FILETYPE = EFI_FV_FILETYPE_FREEFORM +FFS_ATTRIB_CHECKSUM = TRUE + +IMAGE_SCRIPT = +{ + Compress (dummy) { + $(PROJECT_DIR)\$(BUILD_DIR)\IntelRMT.sec + } +} +<<KEEP + + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2014, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/AcpiTables/SsdtIRMT/SsdtIRMT.sdl b/ReferenceCode/AcpiTables/SsdtIRMT/SsdtIRMT.sdl new file mode 100644 index 0000000..62458f6 --- /dev/null +++ b/ReferenceCode/AcpiTables/SsdtIRMT/SsdtIRMT.sdl @@ -0,0 +1,31 @@ +TOKEN + Name = "IntelRMT_SUPPORT" + Value = "1" + Help = "Main switch to enable Intel Ready Mode Technology support in Project" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Master = Yes +End + +PATH + Name = "INTEL_SSDTIRMT_DIR" +End + +TOKEN + Name = "INTEL_IRMT_ASL_FILE" + Value = "$(INTEL_SSDTIRMT_DIR)\IntelRMT.asl" + TokenType = Expression + TargetMAK = Yes +End + +MODULE + Help = "Includes SsdtIRMT.mak to Project" + File = "SsdtIRMT.mak" +End + +ELINK + Name = "$(BUILD_DIR)\IntelRMT.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End diff --git a/ReferenceCode/AcpiTables/SsdtPtid/Ptid.asl b/ReferenceCode/AcpiTables/SsdtPtid/Ptid.asl new file mode 100644 index 0000000..c05a9c3 --- /dev/null +++ b/ReferenceCode/AcpiTables/SsdtPtid/Ptid.asl @@ -0,0 +1,534 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +--*/ + + +// +// Defined as an SSDT to be able to dynamically load based on BIOS +// setup options +// +DefinitionBlock ( + "PTID.aml", + "SSDT", + 0x01, + "TrmRef", + "PtidDevc", + 0x1000 + ) + + +{ + Scope(\_SB) + { + // External References to the actual data locations that stores + // various temperature and power values (either from EC or by + // other means) + // + + // Embedded Controller Availability Flag + External(\_SB.PCI0.LPCB.H_EC.ECAV, IntObj) + // Board id checks + External(\BID, IntObj) + External(\BHB, IntObj) + External(\BFS2, IntObj) + External(\BFS3, IntObj) + External(\BFS4, IntObj) + + // externs for TSDD + External(DTS1) // DTS Core 0 Temp + External(DTS2) // DTS Core 1 Temp + External(DTS3) // DTS Core 2 Temp + External(DTS4) // DTS Core 3 Temp + External(PDTS) // Package DTS Core Temp + External(\_SB.PCI0.LPCB.H_EC.CVRT) // CPU Core VR (IMVP) Temperature + External(\_SB.PCI0.LPCB.H_EC.GTVR) // CPU GT VR (IMVP) Temperature + External(\_SB.PCI0.LPCB.H_EC.FANT) // Heat Exchanger Fan Temperature + External(\_SB.PCI0.LPCB.H_EC.SKNT) // Skin Temperature + External(\_SB.PCI0.LPCB.H_EC.AMBT) // Ambient Temperature + External(\_SB.PCI0.LPCB.H_EC.DIM0) // Channel 0 DIMM Temperature + External(\_SB.PCI0.LPCB.H_EC.DIM1) // Channel 1 DIMM Temperature + External(\_SB.PCI0.LPCB.H_EC.PMAX) // CPU, MCH & PCH Max Temperature + External(\_SB.PCI0.LPCB.H_EC.PPDT) // PCH DTS Temperature from PCH + External(\_SB.PCI0.LPCB.H_EC.PECH) // CPU PECI reading + External(\_SB.PCI0.LPCB.H_EC.PMDT) // MCH DTS Temperature from PCH + External(\_SB.PCI0.LPCB.H_EC.TSD0) // TS-on-DIMM0 Temperature + External(\_SB.PCI0.LPCB.H_EC.TSD1) // TS-on-DIMM1 Temperature + External(\_SB.PCI0.LPCB.H_EC.TSD2) // TS-on-DIMM2 Temperature + External(\_SB.PCI0.LPCB.H_EC.TSD3) // TS-on-DIMM3 Temperature + External(\_TZ.TZ00._TMP) // Thermal Zone 00 Temperature + External(\_TZ.TZ01._TMP) // Thermal Zone 01 Temperature + + // externs for PSDD + External(\_SB.PCI0.LPCB.H_EC.CPUP) // Platform Power mW + External(\_SB.PCI0.LPCB.H_EC.BPWR) // Brick Power cW(100ths) + External(\_SB.PCI0.LPCB.H_EC.PPWR) // Platform Power cW(100ths) + External(\_SB.PCI0.LPCB.H_EC.CPAP) // Platform Average Power mW + External(\_SB.PCI0.LPCB.H_EC.BKAP) // Brick average power in cW(0.01) + External(\_SB.PCI0.LPCB.H_EC.PLAP) // Platform average power in cW(0.01) + External(\_SB.PCI0.LPCB.H_EC.B1DC) // Battery 1 Design Capacity (mWh) + External(\_SB.PCI0.LPCB.H_EC.B1RC) // Battery 1 Remaining Capacity (mWh) + External(\_SB.PCI0.LPCB.H_EC.B1FC) // Battery 1 Full Charge Capacity (mWh) + External(\_SB.PCI0.LPCB.H_EC.B1FV) // Battery 1 Full Resolution Voltage (mV) + External(\_SB.PCI0.LPCB.H_EC.B1DI) // Battery 1 Full Resolution Discharge Current (mA) + External(\_SB.PCI0.LPCB.H_EC.B1CI) // Battery 1 Full Resolution Charge Current (mA) + External(\_SB.PCI0.LPCB.H_EC.B2RC) // Battery 2 Remaining Capacity (mWh) + External(\_SB.PCI0.LPCB.H_EC.B2FC) // Battery 2 Full Charge Capacity (mWh) + External(\_SB.PCI0.LPCB.H_EC.B2FV) // Battery 2 Full Resolution Voltage (mV) + External(\_SB.PCI0.LPCB.H_EC.B2DI) // Battery 2 Full Resolution Discharge Current (mA) + External(\_SB.PCI0.LPCB.H_EC.B2CI) // Battery 2 Full Resolution Charge Current (mA) + External(\_SB.PCI0.LPCB.H_EC.B1ML) // Battery Pack A maximum low byte + External(\_SB.PCI0.LPCB.H_EC.B1MH) // Battery Pack A maximum high byte + External(\_SB.PCI0.LPCB.H_EC.B2ML) // Battery Pack B maximum low byte + External(\_SB.PCI0.LPCB.H_EC.B2MH) // Battery Pack B maximum high byte + + // externs for OSDD + External(\_SB.PCI0.LPCB.H_EC.CFSP) // CPU Fan #1 speed + External(\_SB.PCI0.LPCB.H_EC.CFS2) // CPU Fan #2 speed + External(\_SB.PCI0.LPCB.H_EC.MFSP) // GMCH Fan speed + External(\_SB.PCI0.LPCB.H_EC.PAKN) // Packet sequence number + External(\_SB.PCI0.LPCB.H_EC.CPUE) // CPU energy + // STS - SMBus Turbo Status (48 bits) from EC name space + External(\_SB.PCI0.LPCB.H_EC.SMTL) // MCP Temperature Limit(MTL) + External(\_SB.PCI0.LPCB.H_EC.SGTD) // GMCH Turbo Disabled(GTD) + External(\_SB.PCI0.LPCB.H_EC.SCTD) // CPU Turbo Disabled(CTD) + External(\_SB.PCI0.LPCB.H_EC.SPOL) // Policy Preference(PP) + External(\_SB.PCI0.LPCB.H_EC.SGPL) // GMCH Power Limit(GPL) + External(\_SB.PCI0.LPCB.H_EC.SCPL) // CPU Power Limit(CPL) + External(\_SB.PCI0.LPCB.H_EC.SMPL) // MPC Power Limit(MPL) + // HTS - Host Turbo Status(TBARB offset 50h) from MMIO + External(\_SB.PCI0.LPCB.H_EC.MMTL) // MCP Temperature Limit(MTL) + External(\_SB.PCI0.LPCB.H_EC.MGTD) // GMCH Turbo Disabled(GTD) + External(\_SB.PCI0.LPCB.H_EC.MCTD) // CPU Turbo Disabled(CTD) + External(\_SB.PCI0.LPCB.H_EC.MPOL) // Policy Preference(PP) + External(\_SB.PCI0.LPCB.H_EC.MGPL) // GMCH Power Limit(GPL) + External(\_SB.PCI0.LPCB.H_EC.MCPL) // CPU Power Limit(CPL) + External(\_SB.PCI0.LPCB.H_EC.MMPL) // MPC Power Limit(MPL) + // STS - SMBus Turbo Status(TBARB offset 98h) from MMIO + External(\_SB.PCI0.LPCB.H_EC.NMTL) // MCP Temperature Limit(MTL) + External(\_SB.PCI0.LPCB.H_EC.NGTD) // GMCH Turbo Disabled(GTD) + External(\_SB.PCI0.LPCB.H_EC.NCTD) // CPU Turbo Disabled(CTD) + External(\_SB.PCI0.LPCB.H_EC.NPOL) // Policy Preference(PP) + External(\_SB.PCI0.LPCB.H_EC.NGPL) // GMCH Power Limit(GPL) + External(\_SB.PCI0.LPCB.H_EC.NCPL) // CPU Power Limit(CPL) + // TC1 - Thermal Compares 1(TBARB offset A8h) from MMIO + External(\_SB.PCI0.LPCB.H_EC.TMPL) // MPC Power Limit(MPL) + // HTS - Host Turbo Status (48 bits) from EC name space + External(\_SB.PCI0.LPCB.H_EC.HMTL) + External(\_SB.PCI0.LPCB.H_EC.HGTD) + External(\_SB.PCI0.LPCB.H_EC.HCTD) + External(\_SB.PCI0.LPCB.H_EC.HPOL) + External(\_SB.PCI0.LPCB.H_EC.HGPL) + External(\_SB.PCI0.LPCB.H_EC.HCPL) + External(\_SB.PCI0.LPCB.H_EC.HMPL) + // Thermal Device Base Address Register for BIOS use. + External(TBAB) + // EC Data Buffer for ME SMBus Write Commands + External(\_SB.PCI0.LPCB.H_EC.MPCT) + External(\_SB.PCI0.LPCB.H_EC.MDT0) + // EC Command register + External(\_SB.PCI0.LPCB.H_EC.CMDR) + // EC Buffer to for ACPIPECIPacket + External(\_SB.PCI0.LPCB.H_EC.PRCL) + External(\_SB.PCI0.LPCB.H_EC.PRC0) + External(\_SB.PCI0.LPCB.H_EC.PRC1) + External(\_SB.PCI0.LPCB.H_EC.PRCM) + External(\_SB.PCI0.LPCB.H_EC.PRIN) + External(\_SB.PCI0.LPCB.H_EC.PSTE) + External(\_SB.PCI0.LPCB.H_EC.PCAD) + External(\_SB.PCI0.LPCB.H_EC.PEWL) + External(\_SB.PCI0.LPCB.H_EC.PWRL) + External(\_SB.PCI0.LPCB.H_EC.PECD) + External(\_SB.PCI0.LPCB.H_EC.PEHI) + External(\_SB.PCI0.LPCB.H_EC.PECI) + External(\_SB.PCI0.LPCB.H_EC.PEPL) + External(\_SB.PCI0.LPCB.H_EC.PEPM) + External(\_SB.PCI0.LPCB.H_EC.PWFC) + External(\_SB.PCI0.LPCB.H_EC.PECC) + External(\_SB.PCI0.LPCB.H_EC.PDT0) + External(\_SB.PCI0.LPCB.H_EC.PDT1) + External(\_SB.PCI0.LPCB.H_EC.PDT2) + External(\_SB.PCI0.LPCB.H_EC.PDT3) + External(\_SB.PCI0.LPCB.H_EC.PRFC) + External(\_SB.PCI0.LPCB.H_EC.PRS0) + External(\_SB.PCI0.LPCB.H_EC.PRS1) + External(\_SB.PCI0.LPCB.H_EC.PRS2) + External(\_SB.PCI0.LPCB.H_EC.PRS3) + External(\_SB.PCI0.LPCB.H_EC.PRS4) + External(\_SB.PCI0.LPCB.H_EC.PRCS) + External(\_SB.PCI0.LPCB.H_EC.PEC0) + External(\_SB.PCI0.LPCB.H_EC.PEC1) + External(\_SB.PCI0.LPCB.H_EC.PEC2) + External(\_SB.PCI0.LPCB.H_EC.PEC3) + External(\_SB.PCI0.LPCB.H_EC.TER1) + External(\_SB.PCI0.LPCB.H_EC.TER2) + + External(\_SB.PCI0.LPCB.H_EC.ECMD, MethodObj) + External(\_SB.PCI0.LPCB.H_EC.ECRD, MethodObj) + External(\_SB.PCI0.LPCB.H_EC.ECWT, MethodObj) + + External(\PAMT) + + + Device(PTID) + { + Name(_HID, EISAID("INT340E")) + Name(_CID, EISAID("PNP0C02")) + + Name(IVER, 0x00030000) // Version 3 + + Method (_STA) + { + Return (0x0F) + } + + Name(TSDL, Package() + { //Device Class //Name of Temperature Value + 0x00000000, "CPU Core 0 DTS", //not from ec + 0x00000000, "CPU Core 1 DTS", //not from ec + 0x00000000, "CPU Core 2 DTS", //not from ec + 0x00000000, "CPU Core 3 DTS", //not from ec + 0x00000000, "CPU Core Package DTS", //not from ec + 0x00000003, "CPU Core VR (IMVP) Temperature", + 0x00000003, "Heat Exchanger Fan Temperature", + 0x00000003, "Skin Temperature", + 0x00000003, "Ambient Temperature", + 0x00000002, "Channel 0 DIMM Temperature", + 0x00000002, "Channel 1 DIMM Temperature", + 0x00000000, "CPU Package Temperature", + 0x00000005, "PCH DTS Temperature from PCH", + 0x00000000, "CPU PECI reading", + 0x00000005, "SA DTS Temperature from PCH", + 0x00000002, "TS-on-DIMM0 Temperature", + 0x00000002, "TS-on-DIMM1 Temperature", + 0x00000002, "TS-on-DIMM2 Temperature", + 0x00000002, "TS-on-DIMM3 Temperature", + 0x00000002, "TZ00 _TMP", // not from EC + 0x00000002, "TZ01 _TMP" // not from EC + }) + + Name(PSDL, Package() + { // Device Class //Name of Power Value + 0x0000000B, "Platform Power (mW)", + 0x0000000B, "Brick Power cW(100ths)", + 0x0000000B, "Battery Discharge Power cW(100ths)", + 0x0000000B, "Platform Average Power (mW)", + 0x0000000B, "Brick Average Power cW(0.01)", + 0x0000000B, "Battery Discharge Average Power cW(0.01)", + 0x0000000C, "Battery 1 Design Capacity (mWh)", + 0x0000000C, "Battery 1 Remaining Capacity (mWh)", + 0x0000000C, "Battery 1 Full Charge Capacity (mWh)", + 0x0000000C, "Battery 1 Full Resolution Voltage (mV)", + 0x0000000C, "Battery 1 Full Resolution Discharge Current (mA)", + 0x0000000C, "Battery 1 Full Resolution Charge Current (mA)", + 0x0000000C, "Battery 2 Remaining Capacity (mWh)", + 0x0000000C, "Battery 2 Full Charge Capacity (mWh)", + 0x0000000C, "Battery 2 Full Resolution Voltage (mV)", + 0x0000000C, "Battery 2 Full Resolution Discharge Current (mA)", + 0x0000000C, "Battery 2 Full Resolution Charge Current (mA)", + 0x0000000C, "Battery Pack 1 maximum power (mW)", + 0x0000000C, "Battery Pack 2 maximum power (mW)" + }) + + Name(OSDL, Package() + { // Device Class // Descriptive Name //Unit + 0x00000000, "CPU Fan #1 Speed", "RPM", + 0x00000000, "CPU Fan #2 Speed", "RPM", + 0x00000003, "Skin Temp 0", "RAW", + 0x00000003, "Thermistor 1 ", "RAW", + 0x00000003, "Thermistor 2 ", "RAW", + }) + + Method(TSDD, 0) + { + Name (TMPV, Package() { + 0x80000000, 0x80000000,0x80000000, 0x80000000, + 0x80000000, 0x80000000,0x80000000, 0x80000000, + 0x80000000, 0x80000000,0x80000000, 0x80000000, + 0x80000000, 0x80000000,0x80000000, 0x80000000, + 0x80000000, 0x80000000,0x80000000, 0x80000000, + 0x80000000 }) + + Store(Add(Multiply(DTS1, 10), 2732), Index(TMPV, 0)) + Store(Add(Multiply(DTS2, 10), 2732), Index(TMPV, 1)) + Store(Add(Multiply(DTS3, 10), 2732), Index(TMPV, 2)) + Store(Add(Multiply(DTS4, 10), 2732), Index(TMPV, 3)) + Store(Add(Multiply(PDTS, 10), 2732), Index(TMPV, 4)) + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECAV,1)) // check EC opregion available + { + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.CVRT)), 10), 2732), Index(TMPV, 5)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.FANT)), 10), 2732), Index(TMPV, 6)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.SKNT)), 10), 2732), Index(TMPV, 7)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.AMBT)), 10), 2732), Index(TMPV, 8)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.DIM0)), 10), 2732), Index(TMPV, 9)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.DIM1)), 10), 2732), Index(TMPV, 10)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PMAX)), 10), 2732), Index(TMPV, 11)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PPDT)), 10), 2732), Index(TMPV, 12)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PECH)), 10), 2732), Index(TMPV, 13)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PMDT)), 10), 2732), Index(TMPV, 14)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.TSD0)), 10), 2732), Index(TMPV, 15)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.TSD1)), 10), 2732), Index(TMPV, 16)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.TSD2)), 10), 2732), Index(TMPV, 17)) + Store(Add(Multiply(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.TSD3)), 10), 2732), Index(TMPV, 18)) + } + Store(\_TZ.TZ00._TMP, Index(TMPV, 19)) + If(CondRefOf(\_TZ.TZ01)){ + Store(\_TZ.TZ01._TMP, Index(TMPV, 20)) + } + Return(TMPV) + } + + Method(PSDD, 0, Serialized) + { + Name (PWRV, Package() { + 0x80000000,0x80000000,0x80000000,0x80000000,0x80000000,0x80000000, + 0x80000000,0x80000000,0x80000000,0x80000000,0x80000000,0x80000000, + 0x80000000,0x80000000,0x80000000,0x80000000,0x80000000,0x80000000,0x80000000 + }) + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.ECAV)),1)) // check EC opregion available + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.CPUP)), Index(PWRV, 0)) + Multiply(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.BPWR)), 10, Index(PWRV, 1)) + Multiply(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PPWR)), 10, Index(PWRV, 2)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.CPAP)), Index(PWRV, 3)) + Multiply(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.BKAP)), 10, Index(PWRV, 4)) + Multiply(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PLAP)), 10, Index(PWRV, 5)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1DC)), Index(PWRV, 6)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1RC)), Index(PWRV, 7)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1FC)), Index(PWRV, 8)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1FV)), Index(PWRV, 9)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1DI)), Index(PWRV, 10)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1CI)), Index(PWRV, 11)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B2RC)), Index(PWRV, 12)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B2FC)), Index(PWRV, 13)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B2FV)), Index(PWRV, 14)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B2DI)), Index(PWRV, 15)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B2CI)), Index(PWRV, 16)) + // convert PMAX from signed to unsigned integer + // PMAX Value = (NOT(OR(FFFF0000, ECValue))+1) * 10. + Add(ShiftLeft(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1MH)), 8), \_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B1ML)),Local0) // Get high and low byte from EC. + If(Local0){ // don't convert a zero + Not(Or(0xFFFF0000,Local0,Local0),Local0) // make it a 32 bit value before inverting the bits + Multiply(Add(1,Local0,Local0),10,Local0) // add 1 and multiply by 10 + } + Store(Local0,Index(PWRV, 17)) + // PMAX Value = (NOT(OR(FFFF0000, ECValue))+1) * 10. + Add(ShiftLeft(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B2MH)), 8),\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.B2ML)),Local0) // Get high and low byte from EC. + If(Local0){ // don't convert a zero + Not(Or(0xFFFF0000,Local0,Local0),Local0) // make it a 32 bit value before inverting the bits + Multiply(Add(1,Local0,Local0),10,Local0) // add 1 and multiply by 10 + } + Store(Local0,Index(PWRV, 18)) + } + Return (PWRV) + } + + Method(OSDD, 0) + { + Name (OSDV, Package () {0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}) + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.ECAV)),1)) // check EC opregion available + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.CFSP)), Index(OSDV, 0)) + If(LOr(LOr(LEqual(BID,BHB), LEqual(BID,BFS2)), LOr(LEqual(BID,BFS3), LEqual(BID,BFS4)))) //BoardIdHarrisBeachFfrd, BoardIdFfrdSku2, BoardIdFfrdSku3, BoardIdFfrdSku4 + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.CFS2)), Index(OSDV, 1)) + } + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.SKNT)), Index(OSDV, 2)) + If(LOr(LOr(LEqual(BID,BHB), LEqual(BID,BFS2)), LOr(LEqual(BID,BFS3), LEqual(BID,BFS4)))) //BoardIdHarrisBeachFfrd, BoardIdFfrdSku2, BoardIdFfrdSku3, BoardIdFfrdSku4 + { + // Thermistor values are 10 bit but EC only exposes the high 8 bits. Shift left 2 gives the real number. + Store(ShiftLeft(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.TER1)),2), Index(OSDV, 3)) + Store(ShiftLeft(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.TER2)),2), Index(OSDV, 4)) + } + } + Return(OSDV) + } + + Method (SDSP) + { + Return(10) // Sampling period . + } + + // PECI ACPI Access method + Name(PADA, Package() + { + 0x01, // Access Mode -ACPI + 0xFFFFFFFF, // Command Status port + 0xFFFFFFFF, // Data port + 26, // MailBox length + 0xFFFFFFFF, // WritePECIMailBoxDataCommand + 0xFFFFFFFF, // ReadPECIMailBoxDataCommand + 0xFFFFFFFF, // IssuePECIcommand + 0xFFFFFFFF, // EndPECICommand + 0xFFFFFFFF, // ReadStatusCommand + 0xFFFFFFFF // ReadErrorCountCommand + }) + + // PECI Direct I/O Access method + Name(PADD, Package() + { + 0x02, // Access Mode + 0x6A4, // Command Status port + 0x6A0, // Data port + 26, // MailBox length + 0x62, // WritePECIMailBoxDataCommand + 0x63, // ReadPECIMailBoxDataCommand + 0x60, // IssuePECIcommand + 0x61, // EndPECICommand + 0x65, // ReadStatusCommand + 0x64 // ReadErrorCountCommand + }) + + Method (PADT) + { + If(PAMT) { + Return (PADA) + } + Return (PADD) + } + + Method (RPMD) + { + Name (MTMP, Buffer(26) {}) + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.ECAV)),1)) // check EC opregion available + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PRCL)), Index(MTMP,0)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PRC0)), Index(MTMP,1)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PRC1)), Index(MTMP,2)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PRCM)), Index(MTMP,3)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PRIN)), Index(MTMP,4)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PSTE)), Index(MTMP,5)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PCAD)), Index(MTMP,6)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PEWL)), Index(MTMP,7)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PWRL)), Index(MTMP,8)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PECD)), Index(MTMP,9)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PEHI)), Index(MTMP,10)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PECI)), Index(MTMP,11)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PEPL)), Index(MTMP,12)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PEPM)), Index(MTMP,13)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PWFC)), Index(MTMP,14)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PECC)), Index(MTMP,15)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PDT0)), Index(MTMP,16)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PDT1)), Index(MTMP,17)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PDT2)), Index(MTMP,18)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PDT3)), Index(MTMP,19)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PRFC)), Index(MTMP,20)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PRS0)), Index(MTMP,21)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PRS1)), Index(MTMP,22)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PRS2)), Index(MTMP,23)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PRS3)), Index(MTMP,24)) + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PRS4)), Index(MTMP,25)) + } + Return (MTMP) + } + + Method (WPMD,1) + { + If (LNotEqual(Sizeof(Arg0), 26)) { + Return (0xFFFFFFFF) + } + + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.ECAV)),1)) // check EC opregion available + { + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,0)), RefOf(\_SB.PCI0.LPCB.H_EC.PRCL)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,1)), RefOf(\_SB.PCI0.LPCB.H_EC.PRC0)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,2)), RefOf(\_SB.PCI0.LPCB.H_EC.PRC1)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,3)), RefOf(\_SB.PCI0.LPCB.H_EC.PRCM)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,4)), RefOf(\_SB.PCI0.LPCB.H_EC.PRIN)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,5)), RefOf(\_SB.PCI0.LPCB.H_EC.PSTE)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,6)), RefOf(\_SB.PCI0.LPCB.H_EC.PCAD)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,7)), RefOf(\_SB.PCI0.LPCB.H_EC.PEWL)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,8)), RefOf(\_SB.PCI0.LPCB.H_EC.PWRL)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,9)), RefOf(\_SB.PCI0.LPCB.H_EC.PECD)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,10)), RefOf(\_SB.PCI0.LPCB.H_EC.PEHI)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,11)), RefOf(\_SB.PCI0.LPCB.H_EC.PECI)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,12)), RefOf(\_SB.PCI0.LPCB.H_EC.PEPL)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,13)), RefOf(\_SB.PCI0.LPCB.H_EC.PEPM)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,14)), RefOf(\_SB.PCI0.LPCB.H_EC.PWFC)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,15)), RefOf(\_SB.PCI0.LPCB.H_EC.PECC)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,16)), RefOf(\_SB.PCI0.LPCB.H_EC.PDT0)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,17)), RefOf(\_SB.PCI0.LPCB.H_EC.PDT1)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,18)), RefOf(\_SB.PCI0.LPCB.H_EC.PDT2)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,19)), RefOf(\_SB.PCI0.LPCB.H_EC.PDT3)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,20)), RefOf(\_SB.PCI0.LPCB.H_EC.PRFC)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,21)), RefOf(\_SB.PCI0.LPCB.H_EC.PRS0)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,22)), RefOf(\_SB.PCI0.LPCB.H_EC.PRS1)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,23)), RefOf(\_SB.PCI0.LPCB.H_EC.PRS2)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,24)), RefOf(\_SB.PCI0.LPCB.H_EC.PRS3)) + \_SB.PCI0.LPCB.H_EC.ECWT(DeRefOf(Index(Arg0,25)), RefOf(\_SB.PCI0.LPCB.H_EC.PRS4)) + \_SB.PCI0.LPCB.H_EC.ECMD (0x67) + } + Return (0) + } + + Method (ISPC) + { + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.ECAV)),1)) // check EC opregion available + { + \_SB.PCI0.LPCB.H_EC.ECMD (0x65) + } + Return (0) + } + + Method (ENPC) + { + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.ECAV)),1)) // check EC opregion available + { + \_SB.PCI0.LPCB.H_EC.ECMD (0x66) + } + Return (0) + } + + Method (RPCS) + { + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.ECAV)),1)) // check EC opregion available + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PRCS)), Local0) + } + Return (Local0) + } + + Method (RPEC) + { + Store(0,Local0) + If(LEqual(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.ECAV)),1)) // check EC opregion available + { + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PEC0)), Local1) + Or(Local0,Local1,Local0) + + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PEC1)), Local1) + Or(Local0,ShiftLeft(Local1,8),Local0) + + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PEC2)), Local1) + Or(Local0,ShiftLeft(Local1,16),Local0) + + Store(\_SB.PCI0.LPCB.H_EC.ECRD(RefOf(\_SB.PCI0.LPCB.H_EC.PEC3)), Local1) + Or(Local0,ShiftLeft(Local1,24),Local0) + } + return (Local0) + } + + } + } // end \_SB scope +} // end SSDT diff --git a/ReferenceCode/AcpiTables/SsdtPtid/SsdtPtid.cif b/ReferenceCode/AcpiTables/SsdtPtid/SsdtPtid.cif new file mode 100644 index 0000000..348199f --- /dev/null +++ b/ReferenceCode/AcpiTables/SsdtPtid/SsdtPtid.cif @@ -0,0 +1,10 @@ +<component> + name = "SsdtPtid" + category = ModulePart + LocalRoot = "ReferenceCode\AcpiTables\SsdtPtid\" + RefName = "SsdtPtid" +[files] +"SsdtPtid.sdl" +"SsdtPtid.mak" +"Ptid.asl" +<endComponent> diff --git a/ReferenceCode/AcpiTables/SsdtPtid/SsdtPtid.mak b/ReferenceCode/AcpiTables/SsdtPtid/SsdtPtid.mak new file mode 100644 index 0000000..b9d48fe --- /dev/null +++ b/ReferenceCode/AcpiTables/SsdtPtid/SsdtPtid.mak @@ -0,0 +1,80 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: SsdtPtid.mak +# +# Description: MAke file to build Aptio ACPI ASL components +# +# +#<AMI_FHDR_END> +#************************************************************************* +all : BuildPTID + +BuildPTID : $(BUILD_DIR)\PTID.ffs + +#----------------------------------------------------------------------- +# ASL compiler definition +#----------------------------------------------------------------------- +!IF "$(ACPIPLATFORM_ASL_COMPILER)"=="" +!ERROR It is an invalid path, please check your ASL compiler path. +!ENDIF + +IASL = $(ACPIPLATFORM_ASL_COMPILER) +#----------------------------------------------------------------------- +$(BUILD_DIR)\ptid.aml : $(INTEL_PTID_ASL_FILE) + @cl /C /EP $(INTEL_PTID_ASL_FILE) > $(BUILD_DIR)\ptid.asl + $(IASL) -p $(BUILD_DIR)\ptid.aml $(BUILD_DIR)\ptid.asl + +$(BUILD_DIR)\ptid.sec: $(BUILD_DIR)\ptid.aml + $(GENSECTION) -I $*.aml -O $@ -S EFI_SECTION_RAW + +#Note. Expand the package with PTID tables. +# DXE phase will load the tables +# and update Aml contents if provided in Acpiplatform.c + +$(BUILD_DIR)\PTID.ffs: $(BUILD_DIR)\ptid.sec + $(GENFFSFILE) -B $(BUILD_DIR) -V -o $@ -P1 <<$(BUILD_DIR)\ptid.pkg + +PACKAGE.INF +[.] +BASE_NAME = PTID +FFS_FILEGUID = 95DFCAE5-BB28-4d6b-B1E2-3AF3A6BF434F +FFS_FILETYPE = EFI_FV_FILETYPE_FREEFORM +FFS_ATTRIB_CHECKSUM = TRUE + +IMAGE_SCRIPT = +{ + Compress (dummy) { + $(PROJECT_DIR)\$(BUILD_DIR)\ptid.sec + } +} +<<KEEP + + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/AcpiTables/SsdtPtid/SsdtPtid.sdl b/ReferenceCode/AcpiTables/SsdtPtid/SsdtPtid.sdl new file mode 100644 index 0000000..d1d3a87 --- /dev/null +++ b/ReferenceCode/AcpiTables/SsdtPtid/SsdtPtid.sdl @@ -0,0 +1,32 @@ +TOKEN + Name = "PTID_SUPPORT" + Value = "1" + Help = "Main switch to enable SsdtPtid support in Project" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Master = Yes +End + +PATH + Name = "INTEL_SSDTPTID_DIR" +End + +TOKEN + Name = "INTEL_PTID_ASL_FILE" + Value = "$(INTEL_SSDTPTID_DIR)\ptid.asl" + TokenType = Expression + TargetMAK = Yes +End + +MODULE + Help = "Includes SsdtPtid.mak to Project" + File = "SsdtPtid.mak" +End + +ELINK + Name = "$(BUILD_DIR)\PTID.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent + Token = "PTID_SUPPORT" "=" "1" +End |