init. 1AQQW051HEADmaster

7 files changed, 807 insertions, 0 deletions

diff --git a/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.c b/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.c
new file mode 100644
index 0000000..720fcfc
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.c
@@ -0,0 +1,388 @@
+/** @file
+  PCH Pcie SMM Driver Entry
+
+@copyright
+  Copyright (c) 2010 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+
+**/
+#include "PchPcieSmm.h"
+
+//
+// Global variables
+//
+EFI_SMM_SYSTEM_TABLE              *mSmst;
+EFI_SMM_BASE_PROTOCOL             *mSmmBase;
+PCH_PCI_EXPRESS_CONFIG            *mPciExpressConfig;
+PCH_PWR_OPT_CONFIG                *mPchPwrOptConfig;
+UINT8                             *mRevision;
+UINT8                             mBusNumber;
+
+/**
+  Program Common Clock and ASPM of Downstream Devices
+
+  @param[in] Function             Pcie Root Port Function Number
+
+  @retval EFI_SUCCESS             Function complete successfully
+**/
+EFI_STATUS
+PchPcieSmi (
+  IN  UINT8         Function
+  )
+{
+  UINT16                               Data16;
+  UINT8                                SecBus;
+  UINT8                                SubBus;
+  BOOLEAN                              L1SubstatesSupported;
+  EFI_HANDLE                           Handle;
+  PCH_PCIE_EXPRESS_L1SUBSTATES_CONTROL L1SubVal;
+  UINT8                                RootPortNumber;
+  UINT32                               RootComplexBar;
+  UINTN                                PciD31F0RegBase;
+  BOOLEAN                              LtrSupported;
+  PCH_SERIES                           PchSeries;
+
+  Handle = NULL;
+  PchSeries         = GetPchSeries();
+  LtrSupported      = TRUE;
+  PciD31F0RegBase = MmPciAddress (
+                      0,
+                      mBusNumber,
+                      PCI_DEVICE_NUMBER_PCH_LPC,
+                      PCI_FUNCTION_NUMBER_PCH_LPC,
+                      0
+                      );
+  RootComplexBar  = MmioRead32 (PciD31F0RegBase + R_PCH_LPC_RCBA) & B_PCH_LPC_RCBA_BAR;
+  RootPortNumber = GetPchPcieRpNumber(RootComplexBar, Function);
+
+  if (RootPortNumber == 0xFF) {
+    return EFI_DEVICE_ERROR;
+  }
+  ///
+  /// Check for presense detect state
+  ///
+  Data16 = MmioRead16 (MmPciAddress (0, 0, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, Function, R_PCH_PCIE_SLSTS));
+  Data16 &= B_PCH_PCIE_SLSTS_PDS;
+  if (Data16) {
+    SecBus  = MmioRead8 (MmPciAddress (0, 0, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, Function, 0x19));
+    SubBus  = MmioRead8 (MmPciAddress (0, 0, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, Function, 0x1A));
+    PchPcieInitRootPortDownstreamDevices (0, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, Function, SecBus, SubBus, NULL);
+    MmioWrite8 (MmPciAddress (0, 0, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, Function, 0x19), SecBus);
+    MmioWrite8 (MmPciAddress (0, 0, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, Function, 0x1A), SubBus);
+    L1SubVal = PchPcieL1SubstatesL1_1_2;
+    if ((*mRevision) >= DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_2) {
+      L1SubVal = mPciExpressConfig->RootPort[RootPortNumber].L1Substates;
+    }
+    PcieSetPm (
+      0,
+      PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS,
+      Function,
+      mPciExpressConfig->RootPort[RootPortNumber].Aspm,
+      mPciExpressConfig->NumOfDevAspmOverride,
+      mPciExpressConfig->DevAspmOverride,
+      mPciExpressConfig->TempRootPortBusNumMin,
+      mPciExpressConfig->TempRootPortBusNumMax,
+      mPchPwrOptConfig->NumOfDevLtrOverride,
+      mPchPwrOptConfig->DevLtrOverride,
+      &(mPchPwrOptConfig->PchPwrOptPcie[RootPortNumber]),
+      &L1SubstatesSupported,
+      L1SubVal,
+      *mRevision,
+      FALSE,
+      FALSE,
+      FALSE,
+      &LtrSupported
+      );
+    
+    if(!LtrSupported && (PchSeries == PchLp)) { 
+      MmioAndThenOr32 ( (RootComplexBar + 0x3320), 0, 0x00010003);
+    }
+  } else {
+    ///
+    /// Clear CCC and LTSP bits when PCIe Card hot unplugged
+    ///
+    MmioAnd32 (MmPciAddress (0, 0, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, Function, R_PCH_PCIE_MPC2), (UINT32) ~BIT6);
+    MmioAnd16 (MmPciAddress (0, 0, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, Function, R_PCH_PCIE_LCTL), (UINT16) ~B_PCH_PCIE_LCTL_CCC);
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  PCIE Hotplug SMI call back function for each Root port
+
+  @param[in] DispatchHandle       Handle of this dispatch function
+  @param[in] DispatchContext      Pointer to the dispatch function's context.
+                                  The DispatchContext fields are filled in by the dispatching driver
+                                  prior to invoke this dispatch function
+**/
+VOID
+EFIAPI
+PchPcieSmiHandlerFunction (
+  IN  EFI_HANDLE                              DispatchHandle,
+  IN  EFI_SMM_ICHN_DISPATCH_EX_CONTEXT        *DispatchContext
+  )
+{
+  PchPcieSmi ((UINT8) (DispatchContext->Type - IchnExPcie0Hotplug));
+  return;
+}
+
+/**
+  PCIE Link Active State Change Hotplug SMI call back function for all Root ports
+
+  @param[in] DispatchHandle       Handle of this dispatch function
+  @param[in] DispatchContext      Pointer to the dispatch function's context.
+                                  The DispatchContext fields are filled in by the dispatching driver
+                                  prior to invoke this dispatch function
+**/
+VOID
+EFIAPI
+PchPcieLinkActiveStateChange (
+  IN  EFI_HANDLE                              DispatchHandle,
+  IN  EFI_SMM_ICHN_DISPATCH_EX_CONTEXT        *DispatchContext
+  )
+{
+  return;
+}
+
+/**
+  Register PCIE Hotplug SMI dispatch function to handle Hotplug enabling
+
+  @param[in] ImageHandle          The image handle of this module
+  @param[in] SystemTable          The EFI System Table
+
+  @retval EFI_SUCCESS             The function completes successfully
+**/
+EFI_STATUS
+EFIAPI
+InitializePchPcieSmm (
+  IN      EFI_HANDLE            ImageHandle,
+  IN      EFI_SYSTEM_TABLE      *SystemTable
+  )
+{
+  EFI_STATUS                            Status;
+  UINT8                                 Index;
+  UINT8                                 Data8;
+  UINT32                                Data32Or;
+  UINT32                                Data32And;
+  UINTN                                 RPBase;
+  EFI_HANDLE                            PcieHandle;
+  static CONST EFI_SMM_ICHN_EX_SMI_TYPE PchHPcieHandlerList[LPTH_PCIE_MAX_ROOT_PORTS * 2] = {
+    IchnExPcie0Hotplug,
+    IchnExPcie1Hotplug,
+    IchnExPcie2Hotplug,
+    IchnExPcie3Hotplug,
+    IchnExPcie4Hotplug,
+    IchnExPcie5Hotplug,
+    IchnExPcie6Hotplug,
+    IchnExPcie7Hotplug,
+    IchnExPcie0LinkActive,
+    IchnExPcie1LinkActive,
+    IchnExPcie2LinkActive,
+    IchnExPcie3LinkActive,
+    IchnExPcie4LinkActive,
+    IchnExPcie5LinkActive,
+    IchnExPcie6LinkActive,
+    IchnExPcie7LinkActive
+  };
+  static CONST EFI_SMM_ICHN_EX_SMI_TYPE PchLpPcieHandlerList[LPTLP_PCIE_MAX_ROOT_PORTS * 2] = {
+    IchnExPcie0Hotplug,
+    IchnExPcie1Hotplug,
+    IchnExPcie2Hotplug,
+    IchnExPcie3Hotplug,
+    IchnExPcie4Hotplug,
+    IchnExPcie5Hotplug,
+    IchnExPcie0LinkActive,
+    IchnExPcie1LinkActive,
+    IchnExPcie2LinkActive,
+    IchnExPcie3LinkActive,
+    IchnExPcie4LinkActive,
+    IchnExPcie5LinkActive
+  };
+  EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL     *mIchnDispatch;
+  EFI_SMM_ICHN_DISPATCH_EX_CONTEXT      PchPcieContext;
+  UINTN                                 PortIndex;
+  DXE_PCH_PLATFORM_POLICY_PROTOCOL      *PchPlatformPolicy;
+  PCH_PCIE_DEVICE_LTR_OVERRIDE          *DevLtrOverrideTbl;
+  UINT32                                TableSize;
+  PCH_SERIES                            PchSeries;
+
+  DEBUG ((EFI_D_INFO, "InitializePchPcieSmm() Start\n"));
+
+  PchSeries         = GetPchSeries();
+  DevLtrOverrideTbl = NULL;
+  ///
+  /// Locate SmmBase protocol
+  ///
+  Status = gBS->LocateProtocol (&gEfiSmmBaseProtocolGuid, NULL, (VOID **) &mSmmBase);
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Initialize our module variables
+  ///
+  Status = mSmmBase->GetSmstLocation (mSmmBase, &mSmst);
+  ASSERT_EFI_ERROR (Status);
+  ///
+  /// Locate the ICHnEx Dispatch protocol
+  ///
+  Status = gBS->LocateProtocol (&gEfiSmmIchnDispatchExProtocolGuid, NULL, (VOID **) &mIchnDispatch);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = gBS->LocateProtocol (&gDxePchPlatformPolicyProtocolGuid, NULL, (VOID **) &PchPlatformPolicy);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = mSmst->SmmAllocatePool (
+                    EfiRuntimeServicesData,
+                    sizeof (PCH_PCI_EXPRESS_CONFIG),
+                    (VOID **) &mPciExpressConfig
+                    );
+  ASSERT_EFI_ERROR (Status);
+  Status = mSmst->SmmAllocatePool (
+                    EfiRuntimeServicesData,
+                    sizeof (PCH_PWR_OPT_CONFIG),
+                    (VOID **) &mPchPwrOptConfig
+                    );
+  ASSERT_EFI_ERROR (Status);
+  mPciExpressConfig->NumOfDevAspmOverride = PchPlatformPolicy->PciExpressConfig->NumOfDevAspmOverride;
+  TableSize = PchPlatformPolicy->PciExpressConfig->NumOfDevAspmOverride * sizeof (PCH_PCIE_DEVICE_ASPM_OVERRIDE);
+
+  ///
+  /// Allocate and copy ASPM override table to SMM memory
+  ///
+  Status = mSmst->SmmAllocatePool (
+                    EfiRuntimeServicesData,
+                    TableSize,
+                    (VOID **) &mPciExpressConfig->DevAspmOverride
+                    );
+  ASSERT_EFI_ERROR (Status);
+  CopyMem (mPciExpressConfig->DevAspmOverride, PchPlatformPolicy->PciExpressConfig->DevAspmOverride, TableSize);
+
+  Status = mSmst->SmmAllocatePool (
+                    EfiRuntimeServicesData,
+                    sizeof (PchPlatformPolicy->Revision),
+                    &mRevision
+                    );
+  ASSERT_EFI_ERROR (Status);
+  *mRevision = PchPlatformPolicy->Revision;
+  mBusNumber = PchPlatformPolicy->BusNumber;
+  ///
+  /// Allocate and copy LTR override table to SMM memory
+  ///
+  mPchPwrOptConfig->NumOfDevLtrOverride = PchPlatformPolicy->PwrOptConfig->NumOfDevLtrOverride;
+  DevLtrOverrideTbl = PchPlatformPolicy->PwrOptConfig->DevLtrOverride;
+  if ((DevLtrOverrideTbl != NULL) && (PchPlatformPolicy->PwrOptConfig->NumOfDevLtrOverride != 0)) {
+    TableSize = PchPlatformPolicy->PwrOptConfig->NumOfDevLtrOverride * sizeof (PCH_PCIE_DEVICE_LTR_OVERRIDE);
+    Status = mSmst->SmmAllocatePool (
+                      EfiRuntimeServicesData,
+                      TableSize,
+                      (VOID **) &mPchPwrOptConfig->DevLtrOverride
+                      );
+    ASSERT_EFI_ERROR (Status);
+    CopyMem (mPchPwrOptConfig->DevLtrOverride, DevLtrOverrideTbl, TableSize);
+   }
+
+  for (PortIndex = 0; PortIndex < GetPchMaxPciePortNum (); PortIndex++) {
+    mPciExpressConfig->RootPort[PortIndex].Aspm                     = PchPlatformPolicy->PciExpressConfig->RootPort[PortIndex].Aspm;
+    if (PchPlatformPolicy->Revision >= DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_2) {
+      mPciExpressConfig->RootPort[PortIndex].L1Substates              = PchPlatformPolicy->PciExpressConfig->RootPort[PortIndex].L1Substates;
+    }
+    mPchPwrOptConfig->PchPwrOptPcie[PortIndex].LtrEnable            = PchPlatformPolicy->PwrOptConfig->PchPwrOptPcie[PortIndex].LtrEnable;
+    mPchPwrOptConfig->PchPwrOptPcie[PortIndex].ObffEnable           = PchPlatformPolicy->PwrOptConfig->PchPwrOptPcie[PortIndex].ObffEnable;
+    if (PchPlatformPolicy->Revision >= DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_7) {
+      mPchPwrOptConfig->PchPwrOptPcie[PortIndex].LtrMaxSnoopLatency   = PchPlatformPolicy->PwrOptConfig->PchPwrOptPcie[PortIndex].LtrMaxSnoopLatency;
+      mPchPwrOptConfig->PchPwrOptPcie[PortIndex].LtrMaxNoSnoopLatency = PchPlatformPolicy->PwrOptConfig->PchPwrOptPcie[PortIndex].LtrMaxNoSnoopLatency;
+    }
+  }
+  ///
+  /// Locate the S3 resume scripting protocol
+  ///
+  INITIALIZE_SCRIPT (ImageHandle, SystemTable);
+
+  //
+  // Throught all PCIE root port function and register the SMI Handler for enabled ports.
+  //
+  for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) {
+    RPBase = MmPciAddress (
+              0,
+              0,
+              PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS,
+              Index,
+              0
+              );
+    //
+    // Skip the root port function which is not enabled
+    //
+    if (MmioRead32 (RPBase) == 0xFFFFFFFF) {
+      continue;
+    }
+
+    Data8 = MmioRead8 (RPBase + R_PCH_PCIE_SLCAP);
+    if (Data8 & B_PCH_PCIE_SLCAP_HPC) {
+      switch (PchSeries) {
+        case PchLp:
+          PchPcieContext.Type = PchLpPcieHandlerList[Index];
+          break;
+
+        case PchH:
+          PchPcieContext.Type = PchHPcieHandlerList[Index];
+          break;
+        default:
+          break;
+      }
+      PcieHandle          = NULL;
+      Status = mIchnDispatch->Register (
+                                mIchnDispatch,
+                                PchPcieSmiHandlerFunction,
+                                &PchPcieContext,
+                                &PcieHandle
+                                );
+      ASSERT_EFI_ERROR (Status);
+
+      switch (PchSeries) {
+        case PchLp:
+          PchPcieContext.Type = PchLpPcieHandlerList[Index + LPTLP_PCIE_MAX_ROOT_PORTS];
+          break;
+
+        case PchH:
+          PchPcieContext.Type = PchHPcieHandlerList[Index + LPTH_PCIE_MAX_ROOT_PORTS];
+          break;
+        default:
+          break;
+      }
+      Status = mIchnDispatch->Register (
+                                mIchnDispatch,
+                                PchPcieLinkActiveStateChange,
+                                &PchPcieContext,
+                                &PcieHandle
+                                );
+      ASSERT_EFI_ERROR (Status);
+
+      Data32Or  = B_PCH_PCIE_MPC_HPME;
+      Data32And = (UINT32)~B_PCH_PCIE_MPC_HPME;
+      SCRIPT_MEM_READ_WRITE (
+        EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+        EfiBootScriptWidthUint32,
+        (UINTN) (RPBase + R_PCH_PCIE_MPC),
+        &Data32Or,  // Data to be ORed
+        &Data32And  // Data to be ANDed
+        );
+    }
+  }
+
+  DEBUG ((EFI_D_INFO, "InitializePchPcieSmm() End\n"));
+
+  return EFI_SUCCESS;
+}
\ No newline at end of file
diff --git a/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.cif b/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.cif
new file mode 100644
index 0000000..043b301
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.cif
@@ -0,0 +1,13 @@
+<component>
+	name = "PchPcieSmm"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\LynxPoint\Pcie\Smm"
+	RefName = "PchPcieSmm"
+[files]
+"PchPcieSmm.sdl"	
+"PchPcieSmm.mak"	
+"PchPcieSmm.h"	
+"PchPcieSmm.c"	
+"PchPcieSmm.dxs"	
+"PchPcieSmm.inf"	
+<endComponent>
diff --git a/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.dxs b/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.dxs
new file mode 100644
index 0000000..878ce6b
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.dxs
@@ -0,0 +1,52 @@
+/** @file
+  Dependency expression source file.
+
+@copyright
+  Copyright (c)  2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+
+**/
+ 
+//
+// Common for R8 and R9 codebase
+//
+#include "AutoGen.h"
+#include "DxeDepex.h"
+
+//
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase;
+// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase.
+//
+#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB)
+#include "EfiDepex.h"
+
+#include EFI_PROTOCOL_DEPENDENCY (SmmBase)
+#include EFI_PROTOCOL_DEPENDENCY (SmmIchnDispatchEx)
+#include EFI_PROTOCOL_DEPENDENCY (BootScriptSave)
+#include EFI_PROTOCOL_DEPENDENCY (PchInfo)
+#include EFI_PROTOCOL_DEPENDENCY (PchPlatformPolicy)
+#endif
+
+DEPENDENCY_START
+  EFI_SMM_BASE_PROTOCOL_GUID AND
+  EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL_GUID AND
+#ifdef EFI_S3_RESUME
+  EFI_BOOT_SCRIPT_SAVE_PROTOCOL_GUID AND
+#endif
+  EFI_PCH_INFO_PROTOCOL_GUID AND
+  DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID
+DEPENDENCY_END 
+
+
diff --git a/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.h b/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.h
new file mode 100644
index 0000000..caa0f58
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.h
@@ -0,0 +1,99 @@
+/** @file
+  PCH Pcie SMM Driver Header
+
+@copyright
+  Copyright (c) 2010 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _PCH_PCIE_SMM_H
+#define _PCH_PCIE_SMM_H
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+
+#include "EdkIIGlueDxe.h"
+#include "EfiScriptLib.h"
+#endif
+
+#include EFI_PROTOCOL_CONSUMER (PchPlatformPolicy)
+#include EFI_PROTOCOL_CONSUMER (SmmIchnDispatchEx)
+#include "PchAccess.h"
+#include "PchPlatformLib.h"
+#include "PchPciExpressHelpersLib.h"
+//
+// Prototypes
+//
+
+/**
+  Program Common Clock and ASPM of Downstream Devices
+
+  @param[in] PciePortNum          Pcie Root Port Number
+
+  @retval EFI_SUCCESS             Function complete successfully
+**/
+EFI_STATUS
+PchPcieSmi (
+  IN  UINT8         PciePortNum
+  );
+
+/**
+  PCIE Hotplug SMI call back function for each Root port
+
+  @param[in] DispatchHandle       Handle of this dispatch function
+  @param[in] DispatchContext      Pointer to the dispatch function's context.
+                                  The DispatchContext fields are filled in by the dispatching driver
+                                  prior to invoke this dispatch function
+**/
+VOID
+EFIAPI
+PchPcieSmiHandlerFunction (
+  IN  EFI_HANDLE                              DispatchHandle,
+  IN  EFI_SMM_ICHN_DISPATCH_EX_CONTEXT        *DispatchContext
+  );
+
+/**
+  PCIE Link Active State Change Hotplug SMI call back function for all Root ports
+
+  @param[in] DispatchHandle       Handle of this dispatch function
+  @param[in] DispatchContext      Pointer to the dispatch function's context.
+                                  The DispatchContext fields are filled in by the dispatching driver
+                                  prior to invoke this dispatch function
+**/
+VOID
+EFIAPI
+PchPcieLinkActiveStateChange (
+  IN  EFI_HANDLE                              DispatchHandle,
+  IN  EFI_SMM_ICHN_DISPATCH_EX_CONTEXT        *DispatchContext
+  );
+
+/**
+  Register PCIE Hotplug SMI dispatch function to handle Hotplug enabling
+
+  @param[in] ImageHandle          The image handle of this module
+  @param[in] SystemTable          The EFI System Table
+
+  @retval EFI_SUCCESS             The function completes successfully
+**/
+EFI_STATUS
+EFIAPI
+InitializePchPcieSmm (
+  IN      EFI_HANDLE            ImageHandle,
+  IN      EFI_SYSTEM_TABLE      *SystemTable
+  );
+#endif
diff --git a/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.inf b/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.inf
new file mode 100644
index 0000000..00ca70f
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.inf
@@ -0,0 +1,86 @@
+## @file
+#  Component description file for PchPcieSmm driver
+#
+#@copyright
+#  Copyright (c)  2010 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+[defines]
+BASE_NAME            = PchPcieSmm
+FILE_GUID            = acaeaa7a-c039-4424-88da-f42212ea0e55
+COMPONENT_TYPE       = BS_DRIVER
+
+[sources.common]
+  PchPcieSmm.c
+  PchPcieSmm.h
+
+#
+# Edk II Glue Driver Entry Point
+#
+  EdkIIGlueSmmDriverEntryPoint.c
+
+[includes.common]
+  $(EDK_SOURCE)/Foundation/Efi
+  .
+  ../Common
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include/Library
+#
+# EDK II Glue Library utilizes some standard headers from EDK
+#
+  $(EFI_SOURCE)
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Core/Dxe
+  $(EDK_SOURCE)/Foundation/Include/Pei
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+#
+# Typically the sample code referenced will be available in the code base already
+# So keep this include at the end to defer to the source base definition
+# and only use the sample code definition if source base does not include these files.
+#
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/SampleCode
+
+[libraries.common]
+  EdkFrameworkProtocolLib
+  $(PROJECT_PCH_FAMILY)ProtocolLib
+  PchPlatformLib
+  EdkIIGlueDxeDebugLibReportStatusCode
+  EdkIIGlueSmmRuntimeDxeReportStatusCodeLib
+  EdkIIGlueUefiBootServicesTableLib
+  EdkIIGlueUefiRuntimeServicesTableLib
+  EdkIIGlueBasePciLibPciExpress
+  EdkProtocolLib
+  PchPciExpressHelpersLib
+  EfiScriptLib
+
+[nmake.common]
+  IMAGE_ENTRY_POINT=_ModuleEntryPoint
+  DPX_SOURCE=PchPcieSmm.dxs
+#
+# Module Entry Point
+#
+  C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=InitializePchPcieSmm
+  C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \
+                       -D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \
+                       -D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \
+                       -D __EDKII_GLUE_SMM_RUNTIME_DXE_REPORT_STATUS_CODE_LIB__ \
+                       -D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__
diff --git a/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.mak b/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.mak
new file mode 100644
index 0000000..a2d4181
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.mak
@@ -0,0 +1,100 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/PchPcieSmm/PchPcieSmm.mak 2     2/24/12 2:14a Victortu $
+#
+# $Revision: 2 $
+#
+# $Date: 2/24/12 2:14a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/PchPcieSmm/PchPcieSmm.mak $
+# 
+# 2     2/24/12 2:14a Victortu
+# Updated to support 4.6.5.3_IntelEDK_1117_Patch7_00.
+# 
+# 1     2/08/12 8:57a Yurenlai
+# Intel Lynx Point/SB eChipset initially releases.
+#
+#*************************************************************************
+
+#---------------------------------------------------------------------------
+#   Create PchPcieSmm Driver
+#---------------------------------------------------------------------------
+EDK : PchPcieSmm
+PchPcieSmm : $(BUILD_DIR)\PchPcieSmm.mak PchPcieSmmBin
+
+
+$(BUILD_DIR)\PchPcieSmm.mak : $(PchPcieSmm_DIR)\$(@B).cif $(PchPcieSmm_DIR)\$(@B).mak $(BUILD_RULES)
+  $(CIF2MAK) $(PchPcieSmm_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+PchPcieSmm_INCLUDES=\
+           $(INTEL_PCH_INCLUDES)\
+            $(EdkIIGlueLib_INCLUDES)\
+            $(EDK_INCLUDES)
+
+PchPcieSmm_DEFINES = $(MY_DEFINES)\
+            /D"__EDKII_GLUE_MODULE_ENTRY_POINT__=InitializePchPcieSmm"\
+            /D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \
+            /D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \
+            /D __EDKII_GLUE_SMM_RUNTIME_DXE_REPORT_STATUS_CODE_LIB__ \
+            /D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ \
+            /D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \
+
+PchPcieSmm_LIB_LINKS =\
+!IF "$(x64_BUILD)"=="1"
+            $(EdkIIGlueBaseLibX64_LIB)\
+!ELSE
+            $(EdkIIGlueBaseLibIA32_LIB)\
+!ENDIF
+            $(EDKFRAMEWORKPROTOCOLLIB)\
+            $(INTEL_PCH_PROTOCOL_LIB)\
+            $(PchPlatformSmmLib_LIB)\
+            $(EdkIIGlueDxeDebugLibReportStatusCode_LIB)\
+            $(EdkIIGlueSmmRuntimeDxeReportStatusCodeLib_LIB)\
+            $(EdkIIGlueUefiBootServicesTableLib_LIB)\
+            $(EdkIIGlueBasePciLibPciExpress_LIB)\
+            $(EDKPROTOCOLLIB)\
+            $(PchPciExpressHelpersDxeLib_LIB)\
+            $(EFISCRIPTLIB)\
+            $(EFIPROTOCOLLIB)\
+            $(EdkIIGlueUefiRuntimeServicesTableLib_LIB)\
+
+PchPcieSmmBin: $(PchPcieSmm_LIB_LINKS)
+            $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\
+            /f  $(BUILD_DIR)\PchPcieSmm.mak all \
+            "MY_INCLUDES=$(PchPcieSmm_INCLUDES)" \
+            "MY_DEFINES=$(PchPcieSmm_DEFINES)" \
+            GUID=ACAEAA7A-C039-4424-88DA-F42212EA0E55\
+            ENTRY_POINT=_ModuleEntryPoint \
+            TYPE=BS_DRIVER\
+            EDKIIModule=SMMDRIVER\
+            DEPEX1=$(PchPcieSmm_DIR)\PchPcieSmm.dxs\
+            DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\
+            COMPRESS=1
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
diff --git a/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.sdl b/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.sdl
new file mode 100644
index 0000000..1e1f223
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Pcie/Smm/PchPcieSmm.sdl
@@ -0,0 +1,69 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/PchPcieSmm/PchPcieSmm.sdl 1     2/08/12 8:57a Yurenlai $
+#
+# $Revision: 1 $
+#
+# $Date: 2/08/12 8:57a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/PchPcieSmm/PchPcieSmm.sdl $
+# 
+# 1     2/08/12 8:57a Yurenlai
+# Intel Lynx Point/SB eChipset initially releases.
+#
+#*************************************************************************
+TOKEN
+	Name  = "PchPcieSmm_SUPPORT"
+	Value  = "1"
+	Help  = "Main switch to enable PchPcieSmm support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Master = Yes
+End
+
+PATH
+	Name  = "PchPcieSmm_DIR"
+	Help  = "PchPcieSmm file source directory"
+End
+
+MODULE
+	Help  = "Includes PchPcieSmm.mak to Project"
+	File  = "PchPcieSmm.mak"
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\PchPcieSmm.ffs"
+	Parent  = "FV_MAIN"
+	InvokeOrder = AfterParent
+End
+
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************