diff options
| author | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
|---|---|---|
| committer | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
| commit | b7c51c9cf4864df6aabb99a1ae843becd577237c (patch) | |
| tree | eebe9b0d0ca03062955223097e57da84dd618b9a /ReferenceCode/Chipset/LynxPoint/Protocol | |
| download | zprj-b7c51c9cf4864df6aabb99a1ae843becd577237c.tar.xz | |
Diffstat (limited to 'ReferenceCode/Chipset/LynxPoint/Protocol')
27 files changed, 3547 insertions, 0 deletions
diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/ActiveBios/ActiveBios.c b/ReferenceCode/Chipset/LynxPoint/Protocol/ActiveBios/ActiveBios.c new file mode 100644 index 0000000..6a23962 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/ActiveBios/ActiveBios.c @@ -0,0 +1,47 @@ +/** @file + This protocol is used to report and control what BIOS is mapped to the + BIOS address space anchored at 4GB boundary. + +@copyright + Copyright (c) 2004 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +// +// Statements that include other files +// +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) + +#include "EdkIIGlueDxe.h" +#endif + +#include "ActiveBios.h" + +// +// Protocol GUID definition +// +EFI_GUID gEfiActiveBiosProtocolGuid = EFI_ACTIVE_BIOS_PROTOCOL_GUID; + +// +// Protocol description +// +EFI_GUID_STRING + ( + &gEfiActiveBiosProtocolGuid, "Active BIOS Protocol", + "The active BIOS protocol provides services related to where BIOS address space is directed in hardware." + ); diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/ActiveBios/ActiveBios.h b/ReferenceCode/Chipset/LynxPoint/Protocol/ActiveBios/ActiveBios.h new file mode 100644 index 0000000..744be68 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/ActiveBios/ActiveBios.h @@ -0,0 +1,136 @@ +/** @file + This protocol is used to report and control what BIOS is mapped to the + BIOS address space anchored at 4GB boundary. + + This protocol is EFI compatible. + + E.G. For current generation ICH, the 4GB-16MB to 4GB range can be mapped + to PCI, SPI, or FWH. + +@copyright + Copyright (c) 2005 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _EFI_ACTIVE_BIOS_PROTOCOL_H_ +#define _EFI_ACTIVE_BIOS_PROTOCOL_H_ + +/// +/// Define the protocol GUID +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define EFI_ACTIVE_BIOS_PROTOCOL_GUID \ + { \ + 0xebbe2d1b, 0x1647, 0x4bda, 0xab, 0x9a, 0x78, 0x63, 0xe3, 0x96, 0xd4, 0x1a \ + } +#else +#define EFI_ACTIVE_BIOS_PROTOCOL_GUID \ + { \ + 0xebbe2d1b, 0x1647, 0x4bda, \ + { \ + 0xab, 0x9a, 0x78, 0x63, 0xe3, 0x96, 0xd4, 0x1a \ + } \ + } +#endif +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiActiveBiosProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _EFI_ACTIVE_BIOS_PROTOCOL EFI_ACTIVE_BIOS_PROTOCOL; + +/// +/// Protocol definitions +/// +typedef enum { + ActiveBiosStateSpi, + ActiveBiosStateLpc, + ActiveBiosStateMax +} EFI_ACTIVE_BIOS_STATE; + +/** + Change the current active BIOS settings to the requested state. + The caller is responsible for requesting a supported state from + the EFI_ACTIVE_BIOS_STATE selections. + This will fail if someone has locked the interface and the correct key is + not provided. + + @param[in] This Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance. + @param[in] DesiredState The requested state to configure the system for. + @param[in] Key If the interface is locked, Key must be the Key + returned from the LockState function call. + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_ACCESS_DENIED The interface is currently locked. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ACTIVE_BIOS_SET_ACTIVE_BIOS_STATE) ( + IN EFI_ACTIVE_BIOS_PROTOCOL * This, + IN EFI_ACTIVE_BIOS_STATE DesiredState, + IN UINTN Key + ); + +/** + Lock the current active BIOS state from further changes. This allows a + caller to implement a critical section. This is optionally supported + functionality. Size conscious implementations may choose to require + callers cooperate without support from this protocol. + + @param[in] This Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance. + @param[in] Lock TRUE to lock the current state, FALSE to unlock. + @param[in, out] Key If Lock is TRUE, then a key will be returned. If + Lock is FALSE, the key returned from the prior call + to lock the protocol must be provided to unlock the + protocol. The value of Key is undefined except that + it cannot be 0. + + @retval EFI_SUCCESS Command succeed. + @exception EFI_UNSUPPORTED The function is not supported. + @retval EFI_ACCESS_DENIED The interface is currently locked. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_ACTIVE_BIOS_LOCK_ACTIVE_BIOS_STATE) ( + IN EFI_ACTIVE_BIOS_PROTOCOL * This, + IN BOOLEAN Lock, + IN OUT UINTN *Key + ); + +/// +/// Protocol definition +/// +/// Note that some functions are optional. This means that they may be NULL. +/// Caller is required to verify that an optional function is defined by checking +/// that the value is not NULL. +/// +/// This protocol allows the PCH to be configured to map the top 16 MB of memory +/// below 4 GB to different buses, LPC, SPI, or PCI. The State reflects the current +/// setting. SetState() allows consumers to request a new state, and LockState() +/// allows consumers to prevent other consumers from changing the state. It is the +/// caller's responsibility to configure and lock the desired state to prevent issues +/// resulting from other consumers changing the state. +/// +struct _EFI_ACTIVE_BIOS_PROTOCOL { + EFI_ACTIVE_BIOS_STATE State; ///< The current state mapping that is selected. + EFI_ACTIVE_BIOS_SET_ACTIVE_BIOS_STATE SetState; ///< Change the current state to the requested state mapping. + EFI_ACTIVE_BIOS_LOCK_ACTIVE_BIOS_STATE LockState; ///< Lock the current state mapping to prevent changes to the current state. +}; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/IntelPchProtocolLib.cif b/ReferenceCode/Chipset/LynxPoint/Protocol/IntelPchProtocolLib.cif new file mode 100644 index 0000000..edc8183 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/IntelPchProtocolLib.cif @@ -0,0 +1,33 @@ +<component> + name = "IntelPchProtocolLib" + category = ModulePart + LocalRoot = "ReferenceCode\Chipset\LynxPoint\Protocol\" + RefName = "IntelPchProtocolLib" +[files] +"IntelPchProtocolLib.sdl" +"IntelPchProtocolLib.mak" +"ActiveBios\ActiveBios.h" +"ActiveBios\ActiveBios.c" +"PchPlatformPolicy\PchPlatformPolicy.h" +"PchPlatformPolicy\PchPlatformPolicy.c" +"Spi\Spi.h" +"Spi\Spi.c" +"SerialGpio\SerialGpio.h" +"SerialGpio\SerialGpio.c" +"SmmIoTrapDispatch\SmmIoTrapDispatch.h" +"SmmIoTrapDispatch\SmmIoTrapDispatch.c" +"PchInfo\PchInfo.h" +"PchInfo\PchInfo.c" +"PchInfo\UsbHcPortPrecondition.h" +"PchReset\PchReset.h" +"PchReset\PchReset.c" +"PchS3Support\PchS3Support.h" +"PchS3Support\PchS3Support.c" +"SmmIchnDispatchEx\SmmIchnDispatchEx.h" +"SmmIchnDispatchEx\SmmIchnDispatchEx.c" +"IntelPchProtocolLib.inf" +"Wdt\Wdt.h" +"Wdt\Wdt.c" +"PchSmmIoTrapControl\PchSmmIoTrapControl.c" +"PchSmmIoTrapControl\PchSmmIoTrapControl.h" +<endComponent> diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/IntelPchProtocolLib.inf b/ReferenceCode/Chipset/LynxPoint/Protocol/IntelPchProtocolLib.inf new file mode 100644 index 0000000..ebda5f7 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/IntelPchProtocolLib.inf @@ -0,0 +1,70 @@ +## @file +# Component description file for the PCH protocol library +# +#@copyright +# Copyright (c) 2004 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +[defines] +BASE_NAME = $(PROJECT_PCH_FAMILY)ProtocolLib +COMPONENT_TYPE = LIBRARY + +[sources.common] + ActiveBios/ActiveBios.h + ActiveBios/ActiveBios.c + PchPlatformPolicy/PchPlatformPolicy.h + PchPlatformPolicy/PchPlatformPolicy.c + Spi/Spi.h + Spi/Spi.c + SerialGpio/SerialGpio.h + SerialGpio/SerialGpio.c + SmmIoTrapDispatch/SmmIoTrapDispatch.h + SmmIoTrapDispatch/SmmIoTrapDispatch.c + PchSmmIoTrapControl/PchSmmIoTrapControl.h + PchSmmIoTrapControl/PchSmmIoTrapControl.c + PchInfo/PchInfo.h + PchInfo/PchInfo.c + PchReset/PchReset.h + PchReset/PchReset.c + PchS3Support/PchS3Support.h + PchS3Support/PchS3Support.c + SmmIchnDispatchEx/SmmIchnDispatchEx.h + SmmIchnDispatchEx/SmmIchnDispatchEx.c + Wdt/Wdt.h + Wdt/Wdt.c +[includes.common] + . + $(EDK_SOURCE)/Foundation/Library/Pei/Include + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT) +# +# EDK II Glue Library utilizes some standard headers from EDK +# + $(EFI_SOURCE) + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + +[nmake.common] +C_STD_INCLUDE= + diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/IntelPchProtocolLib.mak b/ReferenceCode/Chipset/LynxPoint/Protocol/IntelPchProtocolLib.mak new file mode 100644 index 0000000..1f328b5 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/IntelPchProtocolLib.mak @@ -0,0 +1,62 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/IntelPchProtocolLib/IntelPchProtocolLib.mak 1 2/08/12 9:01a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 9:01a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/IntelPchProtocolLib/IntelPchProtocolLib.mak $ +# +# 1 2/08/12 9:01a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* + +# MAK file for the ModulePart:IntelPchProtocolLib +EDK : IntelPchProtocolLib + +$(INTEL_PCH_PROTOCOL_LIB) : IntelPchProtocolLib + +IntelPchProtocolLib : $(BUILD_DIR)\IntelPchProtocolLib.mak IntelPchProtocolLibBin + +$(BUILD_DIR)\IntelPchProtocolLib.mak : $(INTEL_PCH_PROTOCOL_LIB_DIR)\$(@B).cif $(INTEL_PCH_PROTOCOL_LIB_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(INTEL_PCH_PROTOCOL_LIB_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +IntelPchProtocolLib_INCLUDES =\ + $(EDK_INCLUDES)\ + $(INTEL_PCH_INCLUDES)\ + +IntelPchProtocolLibBin : + $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\ + /f $(BUILD_DIR)\IntelPchProtocolLib.mak all\ + "MY_INCLUDES=$(IntelPchProtocolLib_INCLUDES)" \ + TYPE=LIBRARY LIBRARIES= +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/IntelPchProtocolLib.sdl b/ReferenceCode/Chipset/LynxPoint/Protocol/IntelPchProtocolLib.sdl new file mode 100644 index 0000000..0d0b35d --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/IntelPchProtocolLib.sdl @@ -0,0 +1,71 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/IntelPchProtocolLib/IntelPchProtocolLib.sdl 1 2/08/12 9:01a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 9:01a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/IntelPchProtocolLib/IntelPchProtocolLib.sdl $ +# +# 1 2/08/12 9:01a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "IntelPchProtocolLib_SUPPORT" + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable IntelPchProtocolLib support in Project" +End + +PATH + Name = "INTEL_PCH_PROTOCOL_LIB_DIR" +End + +MODULE + File = "IntelPchProtocolLib.mak" + Help = "Includes IntelPchProtocolLib.mak to Project" +End + +ELINK + Name = "INTEL_PCH_PROTOCOL_LIB" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "$(BUILD_DIR)\IntelPchProtocolLib.lib" + Parent = "INTEL_PCH_PROTOCOL_LIB" + InvokeOrder = AfterParent +End +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/PchInfo/PchInfo.c b/ReferenceCode/Chipset/LynxPoint/Protocol/PchInfo/PchInfo.c new file mode 100644 index 0000000..24f5b2e --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/PchInfo/PchInfo.c @@ -0,0 +1,41 @@ +/** @file + This file defines the Pch Info Protocol. + +@copyright + Copyright (c) 2008 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +// +// Statements that include other files +// +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGlueDxe.h" +#endif + +#include "PchInfo.h" + +// +// Protocol GUID definition +// +EFI_GUID gEfiPchInfoProtocolGuid = EFI_PCH_INFO_PROTOCOL_GUID; + +// +// Protocol description +// +EFI_GUID_STRING(&gEfiPchInfoProtocolGuid, "PCH Info Protocol", "PCH Information Protocol"); diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/PchInfo/PchInfo.h b/ReferenceCode/Chipset/LynxPoint/Protocol/PchInfo/PchInfo.h new file mode 100644 index 0000000..d03867a --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/PchInfo/PchInfo.h @@ -0,0 +1,121 @@ +/** @file + This file defines the PCH Info Protocol. + +@copyright + Copyright (c) 2008 - 2015 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _PCH_INFO_H_ +#define _PCH_INFO_H_ + +/// +/// Define PCH INFO protocol GUID +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "UsbHcPortPrecondition.h" +#define EFI_PCH_INFO_PROTOCOL_GUID \ + { \ + 0x984eb4e9, 0x5a95, 0x41de, 0xaa, 0xd0, 0x53, 0x66, 0x8c, 0xa5, 0x13, 0xc0 \ + } + +#else +#define EFI_PCH_INFO_PROTOCOL_GUID \ + { \ + 0x984eb4e9, 0x5a95, 0x41de, \ + { \ + 0xaa, 0xd0, 0x53, 0x66, 0x8c, 0xa5, 0x13, 0xc0 \ + } \ + } +#endif +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiPchInfoProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _EFI_PCH_INFO_PROTOCOL EFI_PCH_INFO_PROTOCOL; + +/// +/// Protocol revision number +/// Any backwards compatible changes to this protocol will result in an update in the revision number +/// Major changes will require publication of a new protocol +/// +/// Revision 1: Original version +/// +#define PCH_INFO_PROTOCOL_REVISION_1 1 +/// +/// Revision 2: Add Preconditioned for Usb precondition support. +/// +#define PCH_INFO_PROTOCOL_REVISION_2 2 + +/// +/// RCVersion[7:0] is the release number. +/// For example: +/// LptFramework 0.6.0-01 should be 00 06 00 01 (0x00060001) +/// LptFramework 0.6.2 should be 00 06 02 00 (0x00060200) +/// LptFramework 0.7.0 should be 00 07 00 00 (0x00070000) +/// LptFramework 0.7.1 should be 00 07 01 00 (0x00070100) +/// LptFramework 0.8.0 should be 00 08 00 00 (0x00080000) +/// LptFramework 0.8.1 should be 00 08 01 00 (0x00080100) +/// LptFramework 0.9.0 should be 00 09 00 00 (0x00090000) +/// LptFramework 1.0.0 should be 01 00 00 00 (0x01000000) +/// LptFramework 1.1.0 should be 01 01 00 00 (0x01010000) +/// LptFramework 1.2.0 should be 01 02 00 00 (0x01020000) +/// LptFramework 1.3.0 should be 01 03 00 00 (0x01030000) +/// LptFramework 1.3.1 should be 01 03 01 00 (0x01030100) +/// LptFramework 1.4.0 should be 01 04 00 00 (0x01040000) +/// LptFramework 1.5.0 should be 01 05 00 00 (0x01050000) +/// LptFramework 1.6.0 should be 01 06 00 00 (0x01060000) +/// LptFramework 1.6.1 should be 01 06 01 00 (0x01060100) +/// LptFramework 1.6.2 should be 01 06 02 00 (0x01060200) +/// LptFramework 1.7.0 should be 01 07 00 00 (0x01070000) +/// LptFramework 1.8.0 should be 01 08 00 00 (0x01080000) +/// LptFramework 1.9.0 should be 01 09 00 00 (0x01090000) +/// LptFramework 1.9.1 should be 01 09 01 00 (0x01090100) +/// +#define PCH_RC_VERSION 0x01090100 + +/// +/// Protocol definition +/// +/// This protocol is used to provide the information of PCH controller. +/// +struct _EFI_PCH_INFO_PROTOCOL { + /// + /// This member specifies the revision of the PCH Info protocol. This field is used + /// to indicate backwards compatible changes to the protocol. Platform code that + /// consumes this protocol must read the correct revision value to correctly interpret + /// the content of the protocol fields. + /// + UINT8 Revision; + /// + /// The actual bus number of the PCH devices. + /// + UINT8 BusNumber; + /// + /// The reference code package release number + /// + UINT32 RCVersion; + /// + /// Indicate the Usb precondition feature is working, and it links all the Usb HC + /// precondition structures in the list. + /// + EFI_USB_HC_PORT_PRECONDITION *Preconditioned; +}; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/PchInfo/UsbHcPortPrecondition.h b/ReferenceCode/Chipset/LynxPoint/Protocol/PchInfo/UsbHcPortPrecondition.h new file mode 100644 index 0000000..56b13cb --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/PchInfo/UsbHcPortPrecondition.h @@ -0,0 +1,53 @@ +/** @file + Header file for the PCH USB Common Driver + +@copyright + Copyright (c) 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _USB_HC_PORT_PRECONDITION_H_ +#define _USB_HC_PORT_PRECONDITION_H_ + +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#endif + +typedef struct _EFI_USB_HC_LOCATION { + UINTN SegmentNumber; + UINTN BusNumber; + UINTN DeviceNumber; + UINTN FunctionNumber; +} EFI_USB_HC_LOCATION; + +typedef struct _EFI_USB_PORT_ENUM_TIMING_TABLE { + UINTN ResetRecovery; +} EFI_USB_PORT_ENUM_TIMING_TABLE; + +EFI_FORWARD_DECLARATION (EFI_USB_HC_PORT_PRECONDITION); + +typedef +BOOLEAN +(EFIAPI *EFI_USB_HC_PORT_RESET_STATUS) ( + IN EFI_USB_HC_PORT_PRECONDITION *This, + IN UINT8 PortNumber + ); + +struct _EFI_USB_HC_PORT_PRECONDITION { + UINT8 Revision; + EFI_USB_HC_PORT_PRECONDITION *Next; + EFI_USB_HC_LOCATION Location; + EFI_USB_HC_PORT_RESET_STATUS IsRootPortReset; + EFI_USB_PORT_ENUM_TIMING_TABLE Timing; +}; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/PchPlatformPolicy/PchPlatformPolicy.c b/ReferenceCode/Chipset/LynxPoint/Protocol/PchPlatformPolicy/PchPlatformPolicy.c new file mode 100644 index 0000000..dfb9d2c --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/PchPlatformPolicy/PchPlatformPolicy.c @@ -0,0 +1,44 @@ +/** @file + PCH policy protocol produced by a platform driver specifying various + expected PCH settings. This protocol is consumed by the PCH drivers. + +@copyright + Copyright (c) 2004 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +// +// Statements that include other files +// +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) + +#include "EdkIIGlueDxe.h" +#endif + +#include "PchPlatformPolicy.h" + +// +// Protocol GUID definition +// +EFI_GUID gDxePchPlatformPolicyProtocolGuid = DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID; + +// +// Protocol description +// +EFI_GUID_STRING + (&gDxePchPlatformPolicyProtocolGuid, "PchPlatformPolicy Protocol", "Intel(R) DXE Phase PCH Platform Policy Protocol"); diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/PchPlatformPolicy/PchPlatformPolicy.h b/ReferenceCode/Chipset/LynxPoint/Protocol/PchPlatformPolicy/PchPlatformPolicy.h new file mode 100644 index 0000000..82df716 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/PchPlatformPolicy/PchPlatformPolicy.h @@ -0,0 +1,1061 @@ +/** @file + PCH policy protocol produced by a platform driver specifying various + expected PCH settings. This protocol is consumed by the PCH drivers. + +@copyright + Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ +#ifndef _PCH_PLATFORM_POLICY_H_ +#define _PCH_PLATFORM_POLICY_H_ + +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "PchAccess.h" +#include "PchUsbConfig.h" +#endif +/// +/// PCH policy provided by platform for DXE phase +/// +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID \ + { \ + 0x9797aaf8, 0xe49b, 0x4f02, 0xa3, 0x68, 0xc8, 0x14, 0x8d, 0x2b, 0xc9, 0xe7 \ + } +#else +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID \ + { \ + 0x9797aaf8, 0xe49b, 0x4f02, \ + { \ + 0xa3, 0x68, 0xc8, 0x14, 0x8d, 0x2b, 0xc9, 0xe7 \ + } \ + } +#endif + +extern EFI_GUID gDxePchPlatformPolicyProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL DXE_PCH_PLATFORM_POLICY_PROTOCOL; + +/// +/// Protocol revision number +/// Any backwards compatible changes to this protocol will result in an update in the revision number +/// Major changes will require publication of a new protocol +/// + +/// +/// Revision 1: Original version +/// +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_1 1 + +/// +/// Revision 2: Add L1Substates in PCH_PCI_EXPRESS_ROOT_PORT_CONFIG +/// for BIOS Capability to Enable/Disable L1 Substates. +/// Add override configuration for L1L2 and L1 substates. +/// +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_2 2 + +/// +/// Revision 3: Add RootPortFunctionSwapping in PCH_PCI_EXPRESS_CONFIG +/// for switching the support of RootPortFunctionSwapping. +/// +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_3 3 + +/// +/// Revision 4: Add LegacyDmaDisable in PCH_PWR_OPT_CONFIG +/// Add PchPwrCycDur in PCH_MISC_PM_CONFIG +/// +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_4 4 + +/// +/// Revision 5: Add Port30Settings in PCH_USB_CONFIG +/// Add PcieWakeFromDeepSx in PCH_WAKE_CONFIG +/// +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_5 5 + +/// +/// Revision 6: Add DciEn in PCH_MISC_CONFIG +/// Add DDR50 support in PCH_SERIAL_IO_CONFIG +/// +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_6 6 + +/// +/// Revision 7: Add LTR related policies in PCH_PCIE_PWR_OPT +/// LtrMaxSnoopLatency +/// LtrMaxNoSnoopLatency +/// SnoopLatencyOverrideMode +/// SnoopLatencyOverrideMultiplier +/// SnoopLatencyOverrideValue +/// NonSnoopLatencyOverrideMode +/// NonSnoopLatencyOverrideMultiplier +/// NonSnoopLatencyOverrideValue +/// Update SlpLanLowDc usage. +/// +#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_7 7 + +// +// Generic definitions for device enabling/disabling used by PCH code. +// +#define PCH_DEVICE_ENABLE 1 +#define PCH_DEVICE_DISABLE 0 + +// +// ---------------------------- Device Enabling ------------------------------ +// +/// +/// PCH Device enablings +/// +/// The PCH_DEVICE_ENABLING block allows platform modules to tell the PCH drivers +/// to enable/disable a set of PCH features. +/// Platform modules may need to refer Setup options, schematic, BIOS specification +/// to update these fields. +/// +typedef struct { + /// + /// This member determines if enable or disable Intel Gigabit LAN device. + /// It must be set to disable while the device is not used. + /// + UINT8 Lan : 1; ///< 0: Disable; 1: Enable + /// + /// This member describes whether or not Intel HD Audio (Azalia) should be enabled. + /// If enabled and no codec exists the reference code will automatically disable + /// the Azalia device. + /// + UINT8 Azalia : 2; ///< 0: Disable; 1: Enable; 2: Auto + /// + /// This member describes whether or not the SATA controllers should be enabled. + /// + UINT8 Sata : 1; ///< 0: Disable; 1: Enable + /// + /// This member describes whether or not the SMBus controller of PCH should be enabled. + /// + UINT8 Smbus : 1; ///< 0: Disable; 1: Enable + /// + /// This member describes whether or not the PCI ClockRun feature of PCH should + /// be enabled. + /// + UINT8 PciClockRun : 1; ///< 0: Disable; 1: Enable + /// + /// This member describes whether or not PCH display logic should be enabled. + /// PCH display logic properly decodes the Register Access that are used to communicate + /// with the North Display in the IMC. This device should be enabled or disabled + /// as defined in the BIOS specification. + /// + UINT8 Display : 1; ///< 0: Disable; 1: Enable + /// + /// This member describes whether or not the Compatibility Revision ID (CRID) feature + /// of PCH should be enabled. + /// + UINT8 Crid : 1; ///< 0: Disable; 1: Enable + /// + /// This member describes whether or not the DMA of Serial IO controllers should be enabled. + /// + UINT8 SerialIoDma : 1; ///< 0: Disable; 1: Enable + /// + /// This member describes whether or not the Serial IO I2c0 controller should be enabled. + /// + UINT8 SerialIoI2c0 : 1; ///< 0: Disable; 1: Enable + /// + /// This member describes whether or not the Serial IO I2c1 controller should be enabled. + /// + UINT8 SerialIoI2c1 : 1; ///< 0: Disable; 1: Enable + /// + /// This member describes whether or not the Serial IO Spi0 controller should be enabled. + /// + UINT8 SerialIoSpi0 : 1; ///< 0: Disable; 1: Enable + /// + /// This member describes whether or not the Serial IO Spi1 controller should be enabled. + /// + UINT8 SerialIoSpi1 : 1; ///< 0: Disable; 1: Enable + /// + /// This member describes whether or not the Serial IO Uart0 controller should be enabled. + /// + UINT8 SerialIoUart0 : 1; ///< 0: Disable; 1: Enable + /// + /// This member describes whether or not the Serial IO Uart1 controller should be enabled. + /// + UINT8 SerialIoUart1 : 1; ///< 0: Disable; 1: Enable + /// + /// This member describes whether or not the Serial IO Sdio controller should be enabled. + /// + UINT8 SerialIoSdio : 1; ///< 0: Disable; 1: Enable + /// + /// This member describes whether or not the Asdio Dsp controller should be enabled. + /// + UINT8 AudioDsp : 1; ///< 0: Disable; 1: Enable + UINT8 Rsvdbits : 7; ///< Reserved fields for future expansion w/o protocol change +} PCH_DEVICE_ENABLING; + +// +// ---------------------------- PCI Express Config ---------------------- +// +/// +/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature +/// +typedef enum { + PchPcieAspmDisabled, + PchPcieAspmL0s, + PchPcieAspmL1, + PchPcieAspmL0sL1, + PchPcieAspmAutoConfig, + PchPcieAspmMax +} PCH_PCI_EXPRESS_ASPM_CONTROL; + +/// +/// Refer to PCH EDS for the PCH implementation values corresponding +/// to below PCI-E spec defined ranges +/// +typedef enum { + PchPcieL1SubstatesDisabled, + PchPcieL1SubstatesL1_1, + PchPcieL1SubstatesL1_2, + PchPcieL1SubstatesL1_1_2, + PchPcieL1SubstatesMax +} PCH_PCIE_EXPRESS_L1SUBSTATES_CONTROL; + +typedef enum { + PchPcieCompletionTO_Default, + PchPcieCompletionTO_50_100us, + PchPcieCompletionTO_1_10ms, + PchPcieCompletionTO_16_55ms, + PchPcieCompletionTO_65_210ms, + PchPcieCompletionTO_260_900ms, + PchPcieCompletionTO_1_3P5s, + PchPcieCompletionTO_4_13s, + PchPcieCompletionTO_17_64s, + PchPcieCompletionTO_Disabled +} PCH_PCIE_COMPLETION_TIMEOUT; + +typedef enum { + PchPcieOverrideDisabled = 0x00, + PchPcieL1L2Override = 0x01, + PchPcieL1SubstatesOverride = 0x02, + PchPcieL1L2AndL1SubstatesOverride = 0x03 +} PCH_PCI_EXPRESS_ASPM_OVERRIDE_CONFIG; + +typedef struct { + UINT8 Enable : 1; ///< Root Port enabling, 0: Disable; 1: Enable. + UINT8 Hide : 1; ///< Whether or not to hide the configuration space of this port. + UINT8 SlotImplemented : 1; ///< Indicates whether the root port is connected to a slot. + UINT8 HotPlug : 1; ///< Indicate whether the root port is hot plug available. + UINT8 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled. + UINT8 ExtSync : 1; ///< Indicate whether the extended synch is enabled. + UINT8 Rsvdbits : 2; + // + // Error handlings + // + UINT8 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled. + UINT8 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled. + UINT8 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled. + UINT8 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled. + UINT8 PmeInterrupt : 1; ///< Indicate whether the PME Interrupt is enabled. + UINT8 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled. + UINT8 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled. + UINT8 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled. + + UINT8 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled + UINT8 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled. + UINT8 Reserved : 6; ///< Reserved fields for future expansion w/o protocol change + + UINT8 FunctionNumber; ///< The function number this root port is mapped to + UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port. + PCH_PCIE_COMPLETION_TIMEOUT CompletionTimeout; ///< The completion timeout configuration of the root port + PCH_PCI_EXPRESS_ASPM_CONTROL Aspm; ///< The ASPM configuration of the root port + PCH_PCIE_EXPRESS_L1SUBSTATES_CONTROL L1Substates; ///< The L1 Substates configuration of the root port +} PCH_PCI_EXPRESS_ROOT_PORT_CONFIG; + +typedef struct { + UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID + UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID + UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings + UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class + UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class + PCH_PCI_EXPRESS_ASPM_CONTROL EndPointAspm; ///< The override ASPM setting from End point + PCH_PCI_EXPRESS_ASPM_OVERRIDE_CONFIG OverrideConfig; ///< The override configuration. e.g. 0x0 means this subset is applicable to L1L2 override only. + UINT16 L1SubstatesCapOffset; ///< The L1Substates Capability Offset + UINT32 L1SubstatesCapMask; ///< The L1Substates Capability Mask +} PCH_PCIE_DEVICE_ASPM_OVERRIDE; + +typedef enum { + PchPciePort1, + PchPciePort2, + PchPciePort3, + PchPciePort4, + PchPciePort5, + PchPciePort6, + PchPciePort7, + PchPciePort8 +} PCH_PCIE_SBDE_PORTS; + +/// +/// The PCH_PCI_EXPRESS_CONFIG block describes the expected configuration of the PCH PCI Express controllers +/// +typedef struct { + /// + /// Temp Bus Number range available to be assigned to each root port and its downstream + /// devices for initialization of these devices before PCI Bus enumeration. + /// + UINT8 TempRootPortBusNumMin; + /// + /// Temp Bus Number range available to be assigned to each root port and its downstream + /// devices for initialization of these devices before PCI Bus enumeration. + /// + UINT8 TempRootPortBusNumMax; + /// + /// These members describe the configuration of each PCH PCIe root port. + /// + PCH_PCI_EXPRESS_ROOT_PORT_CONFIG RootPort[LPTH_PCIE_MAX_ROOT_PORTS]; + UINT8 NumOfDevAspmOverride; ///< Number of Pci Express card Aspm setting override + PCH_PCIE_DEVICE_ASPM_OVERRIDE *DevAspmOverride; ///< The Pointer which is point to Pci Express card Aspm setting override + /// + /// The PCIe Port that selected for enable Subtractive Decode. + /// + PCH_PCIE_SBDE_PORTS PchPcieSbdePort; + /// + /// This member describes whether the PCI Express Clock Gating for each root port + /// is enabled by platform modules. + /// + UINT8 RootPortClockGating : 1; + /// + /// This member determines if enable subtractive decode over PCIe + /// + UINT8 EnableSubDecode : 1; ///< Determines if enable subtractive decode over PCIe + UINT8 Rsvdbits : 6; ///< Reserved fields for future expansion w/o protocol change + /// + /// Support root port function number swapping if root port of function 0 is disabled. + /// When RootPortFunctionSwapping enabled, the FunctionNumber for per root port will be ignored. + /// It allows to automatically swap the function 0 to eanble root port by enabling this policy, or + /// elaborates the FunctionNumber per root port and disable this policy. + /// NOTE: When RootPortFunctionSwapping is disabled, Bios tries to force enable the root port of function 0. + /// Be careful not assign the function 0 to the port connecting to Gbe/Nand or no lane available. + /// + UINT8 RootPortFunctionSwapping; +} PCH_PCI_EXPRESS_CONFIG; + +// +// ---------------------------- SATA Config ----------------------------- +// +typedef enum { + PchSataOromDelay2sec, + PchSataOromDelay4sec, + PchSataOromDelay6sec, + PchSataOromDelay8sec +} PCH_SATA_OROM_DELAY; + +typedef enum { + PchSataSpeedSupportDefault, + PchSataSpeedSupportGen1, + PchSataSpeedSupportGen2, + PchSataSpeedSupportGen3 +} PCH_SATA_SPEED_SUPPORT; + +typedef struct { + UINT8 Enable : 1; ///< 0: Disable; 1: Enable + UINT8 HotPlug : 1; ///< 0: Disable; 1: Enable + UINT8 InterlockSw : 1; ///< 0: Disable; 1: Enable + UINT8 External : 1; ///< 0: Disable; 1: Enable + UINT8 SpinUp : 1; ///< 0: Disable; 1: Enable the COMRESET initialization Sequence to the device + UINT8 SolidStateDrive : 1; ///< 0: HDD; 1: SSD + UINT8 DevSlp : 1; ///< 0: Disable; 1: Enable DevSlp on the port + UINT8 EnableDitoConfig: 1; ///< 0: Disable; 1: Enable + UINT8 DmVal : 4; ///< DM value to be set + UINT8 Rsvdbits : 4; ///< Reserved fields for future expansion w/o protocol change + UINT16 DitoVal : 10; ///< Dito value to be set + UINT16 Rsvdbits16 : 6; ///< Reserved fields for future expansion w/o protocol change +} PCH_SATA_PORT_SETTINGS; + +/// +/// The PCH_SATA_CONFIG block describes the expected configuration of the SATA controllers. +/// +typedef struct { + PCH_SATA_PORT_SETTINGS PortSettings[LPTH_AHCI_MAX_PORTS]; + UINT8 RaidAlternateId : 1; ///< 0: Disable; 1: Enable + ///< Whether RAID Alternate ID is enabled. When disabled, the SATA controller D31:F2 + ///< in RAID mode will report Device ID 282Xh; when enabled, the SATA controller + ///< D31:F2 in RAID mode will report Device ID 292Xh. + UINT8 Raid0 : 1; ///< 0: Disable; 1: Enable RAID0 + UINT8 Raid1 : 1; ///< 0: Disable; 1: Enable RAID1 + UINT8 Raid10 : 1; ///< 0: Disable; 1: Enable RAID10 + UINT8 Raid5 : 1; ///< 0: Disable; 1: Enable RAID5 + UINT8 Irrt : 1; ///< 0: Disable; 1: Enable Intel Rapid Recovery Technology + UINT8 OromUiBanner : 1; ///< 0: Disable; 1: Enable OROM UI and BANNER + UINT8 HddUnlock : 1; ///< 0: Disable; 1: Indicates that the HDD password unlock in the OS is enabled + + UINT8 LedLocate : 1; ///< 0: Disable; 1: Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS + UINT8 IrrtOnly : 1; ///< 0: Disable; 1: Allow only IRRT drives to span internal and external ports + UINT8 TestMode : 1; ///< 0: Disable; 1: Allow entrance to the PCH SATA test modes + UINT8 SalpSupport : 1; ///< 0: Disable; 1: Enable Aggressive Link Power Management + UINT8 LegacyMode : 1; ///< 0: Native PCI mode; 1: Legacy mode when controller 1 is operating in IDE mode + UINT8 SmartStorage : 1; ///< 0: Disable; 1: Enable RST Smart Storage caching Bit + UINT8 OromUiDelay : 2; ///< 00: 2 secs; 01: 4 secs; 10: 6 secs; 11: 8 secs + + UINT8 SpeedSupport : 4; ///< Indicates the maximum speed the SATA controller can support + ///< 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2); 3h: 6 Gb/s (Gen 1) + UINT8 Rsvdbits : 4; ///< Reserved fields for future expansion w/o protocol change +} PCH_SATA_CONFIG; + +// +// --------------------------- AZALIA Config ------------------------------ +// +typedef struct { + UINT32 VendorDeviceId; ///< This is the Vendor ID (byte 3 and byte 2) and Device ID (byte 1 and byte 0) of the Azalia codec. + UINT16 SubSystemId; ///< This is the sub system ID of this codec. + UINT8 RevisionId; ///< This is the revision ID of this codec. 0xFF applies to all steppings + UINT8 FrontPanelSupport; ///< Whether or not support front panel. 1: Yes, 0: No. + UINT16 NumberOfRearJacks; ///< Number of rear jacks. + UINT16 NumberOfFrontJacks; ///< Number of front jacks. +} PCH_AZALIA_VERB_TABLE_HEADER; + +typedef struct { + PCH_AZALIA_VERB_TABLE_HEADER VerbTableHeader; ///< The header information in Azalia verb table. + UINT32 *VerbTableData; ///< Pointer to the buffer containing verb tables data provided by platform. +} PCH_AZALIA_VERB_TABLE; + + +/// +/// The AZALIA_CONFIG block describes the expected configuration of the Intel HD Audio (Azalia) feature. +/// +typedef struct { + UINT8 Pme : 1; ///< Azalia wake-on-ring, 0: Disable; 1: Enable + UINT8 DS : 1; ///< 0: Docking is not supported; 1:Docking is supported + UINT8 DA : 1; ///< 0: Docking is not attached; 1:Docking is attached + UINT8 Rsvdbits : 5; + UINT8 AzaliaVerbTableNum; ///< Number of verb tables provided by platform + PCH_AZALIA_VERB_TABLE *AzaliaVerbTable; ///< Pointer to the actual verb table(s) + UINT16 ResetWaitTimer; ///< The delay timer after Azalia reset, the value is number of microseconds +} PCH_AZALIA_CONFIG; + +// +// --------------------------- AUDIO DSP Config ------------------------------ +// +/// +/// The PCH_AUDIO_DSP_CONFIG block describes the misc power management configurations +/// of the Audio Dsp controller, and also the Acpi or Pci mode selection for the +/// Audio Dsp controller. +/// +typedef struct { + UINT8 AudioDspD3PowerGating : 1; ///< This flag enables/disables the Audio Dsp D3 power gating. + UINT8 AudioDspBluetoothSupport : 1; ///< Audio Dsp Bluetooth support enabled. + UINT8 AudioDspAcpiMode : 1; ///< If this is enabled, the Audio Dsp device is shown as ACPI device, + ///< and the PCI controller for the Audio Dsp will be hidden, and vice versa. + UINT8 AudioDspAcpiInterruptMode : 1; ///< If this is enabled, the Audio Dsp device uses ACPI interrupts + UINT8 Rsvdbits : 4; +} PCH_AUDIO_DSP_CONFIG; + +// +// --------------------------- Serial IO Config ------------------------------ +// +/// +/// The PCH_LP_SERIAL_CONFIG block provides the configurations to set the Serial IO controllers +/// to Acpi devices or Pci controllers, and also set the interrupt type to Acpi or Pci +/// through platform policy. It also provides to configure the I2c0 and I2c1 voltage +/// to 1.8v or 3.3v by platform setting. +/// +typedef struct { + UINT8 SerialIoMode : 1; ///< Set to 0 will create Acpi devices for Serial IO Controllers. Set to 1 will show the Pci devices. + UINT8 SerialIoInterruptMode : 1; ///< Configures all Serial IO Controllers in PCI or ACPI Interrupt Mode. + UINT8 I2c0VoltageSelect : 1; ///< Selects the IO voltage for I2c0 controller. It can be 1.8v or 3.3v + UINT8 I2c1VoltageSelect : 1; ///< selects the IO voltage for I2c1 controller. It can be 1.8v or 3.3v + /// + /// GpioInt Configuration + /// + UINT8 GpioIrqRoute : 1; ///< 0: IRQ14; 1: IRQ15 + UINT8 DriverModeTouchPanel : 1; ///< Driver Mode Touch Panel (ACPI=0:GPIO=1) + UINT8 DriverModeTouchPad : 1; ///< Driver Mode Touch Pad (ACPI=0:GPIO=1) + UINT8 DriverModeSensorHub : 1; ///< Driver Mode Sensor Hub (ACPI=0;GPIO=1) + + UINT8 Ddr50Support : 1; ///< enables DDR50 support in SDIO controller + UINT8 Reserved : 7; // padding +} PCH_SERIAL_IO_CONFIG; + +typedef enum { + PchSerialIoIsAcpi = 0, + PchSerialIoIsPci +} PCH_SERIAL_IO_MODE_CONFIG; + +typedef enum { + PchSerialIoIs33V = 0, + PchSerialIoIs18V +} PCH_LP_SERIAL_IO_VOLTAGE_SEL; + +// +// --------------------------- Smbus Config ------------------------------ +// + +/// +/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform. +/// +typedef struct { + UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the SmbusAddressTable. + UINT8 *RsvdSmbusAddressTable; ///< The pointer to an array of addresses reserved for non-ARP-capable SMBus devices. +} PCH_SMBUS_CONFIG; + +// +// --------------------------- Miscellaneous PM Config ------------------------------ +// +typedef struct { + UINT8 MeWakeSts : 1; ///< Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. + UINT8 MeHrstColdSts : 1; ///< Clear the ME_HRST_COLD_STS bit in the Power and Reset Status (PRSTS) register. + UINT8 MeHrstWarmSts : 1; ///< Clear the ME_HRST_WARM_STS bit in the Power and Reset Status (PRSTS) register. + UINT8 MeHostPowerDn : 1; ///< Clear the ME_HOST_PWRDN bit in the Power and Reset Status (PRSTS) register. + UINT8 WolOvrWkSts : 1; ///< Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. + UINT8 Rsvdbits : 3; +} PCH_POWER_RESET_STATUS; + +typedef struct { + UINT8 PmeB0S5Dis : 1; ///< Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration 3 (GEN_PM_CON_3) register. + UINT8 WolEnableOverride : 1; ///< Corresponds to the "MOL Enable Override" bit in the General PM Configuration 3 (GEN_PM_CON_3) register. + UINT8 Gp27WakeFromDeepSx : 1; ///< Determine if enable GP27 to wake from deep Sx. + UINT8 PcieWakeFromDeepSx : 1; ///< Determine if enable PCIe to wake from deep Sx. + UINT8 Rsvdbits : 4; +} PCH_WAKE_CONFIG; + +typedef enum { + PchDeepSxPolDisable = 0, + PchMobileDpS5En, + PchDesktopDpS5En, + PchMobileDpS4S5En, + PchDesktopDpS4S5En, + PchMobileDpS3S4S5En, + PchDesktopDpS3S4S5En +} PCH_DEEP_SX_CONFIG; + +typedef enum { + PchSlpS360us, + PchSlpS31ms, + PchSlpS350ms, + PchSlpS32s +} PCH_SLP_S3_MIN_ASSERT; + +typedef enum { + PchSlpS4PchTime, ///< The time defined in PCH EDS Power Sequencing and Reset Signal Timings table + PchSlpS41s, + PchSlpS42s, + PchSlpS43s, + PchSlpS44s +} PCH_SLP_S4_MIN_ASSERT; + +typedef enum { + PchSlpSus0ms, + PchSlpSus500ms, + PchSlpSus1s, + PchSlpSus4s +} PCH_SLP_SUS_MIN_ASSERT; + +typedef enum { + PchSlpA0ms, + PchSlpA4s, + PchSlpA98ms, + PchSlpA2s +} PCH_SLP_A_MIN_ASSERT; + +/// +/// The PCH_MISC_PM_CONFIG block describes expected miscellaneous power management settings. +/// The PowerResetStatusClear field would clear the Power/Reset status bits, please +/// set the bits if you want PCH Init driver to clear it, if you want to check the +/// status later then clear the bits. +/// +typedef struct { + /// + /// Specify which Power/Reset bits need to be cleared by + /// the PCH Init Driver. + /// Usually platform drivers take care of these bits, but if + /// not, let PCH Init driver clear the bits. + /// + PCH_POWER_RESET_STATUS PowerResetStatusClear; + PCH_WAKE_CONFIG WakeConfig; ///< Specify Wake Policy + PCH_DEEP_SX_CONFIG PchDeepSxPol; ///< Deep Sx Policy + PCH_SLP_S3_MIN_ASSERT PchSlpS3MinAssert; ///< SLP_S3 Minimum Assertion Width Policy + PCH_SLP_S4_MIN_ASSERT PchSlpS4MinAssert; ///< SLP_S4 Minimum Assertion Width Policy + PCH_SLP_SUS_MIN_ASSERT PchSlpSusMinAssert; ///< SLP_SUS Minimum Assertion Width Policy + PCH_SLP_A_MIN_ASSERT PchSlpAMinAssert; ///< SLP_A Minimum Assertion Width Policy + UINT8 SlpStrchSusUp : 1; ///< Enable/Disable SLP_X Stretching After SUS Well Power Up + /// + /// Enable/Disable SLP_LAN# Low on DC Power. + /// Configure On DC PHY Power Diable according to policy SlpLanLowDc. + /// When this is enabled, SLP_LAN# will be driven low when ACPRESENT is low. + /// This indicates that LAN PHY should be powered off on battery mode. + /// This will override the DC_PP_DIS setting by WolEnableOverride. + /// + UINT8 SlpLanLowDc : 1; + UINT8 Rsvdbits : 6; + /// + /// Reset Power Cycle Duration could be customized in the unit of second.Please refer to EDS + /// for all support settings. So far PCH supports 1~4 seconds, and PCH default is 4 seconds. + /// And make sure the setting correct, which never less than the following register. + /// - GEN_PMCON_3.SLP_S3_MIN_ASST_WDTH + /// - GEN_PMCON_3.SLP_S4_MIN_ASST_WDTH + /// - PM_CFG.SLP_A_MIN_ASST_WDTH + /// - PM_CFG.SLP_LAN_MIN_ASST_WDTH + /// + UINT8 PchPwrCycDur; ///< Reset Power Cycle Duration +} PCH_MISC_PM_CONFIG; + +// +// --------------------------- IO APIC Config ------------------------------ +// +/// +/// The PCH_IO_APIC_CONFIG block describes the expected configuration of the PCH +/// IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is +/// not TRUE. Bus:device:function fields will be programmed to the register +/// LPC_IBDF(D31:F0:R6Ch-6Dh), it's using for the following purpose: +/// As the Requester ID when initiating Interrupt Messages to the processor. +/// As the Completer ID when responding to the reads targeting the IOxAPI's +/// Memory-Mapped I/O registers. +/// This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can +/// program this field to provide a unique Bus:Device:Function number for the +/// internal IOxAPIC. +/// +typedef struct { + BOOLEAN BdfValid; ///< Whether the BDF value is valid, PCH code will not program these fields if this bit is not TRUE. + UINT8 BusNumber; ///< Bus/Device/Function used as Requestor / Completer ID. + UINT8 DeviceNumber; ///< Bus/Device/Function used as Requestor / Completer ID. + UINT8 FunctionNumber; ///< Bus/Device/Function used as Requestor / Completer ID. + UINT8 IoApicEntry24_39 :1; ///< 0: Disable; 1: Enable IOAPIC Entry 24-39. + UINT8 RsvdBits :7; +} PCH_IO_APIC_CONFIG; + +// +// --------------------------- Subsystem Vendor ID / Subsystem ID Config ----- +// +/// +/// The PCH_DEFAULT_SVID_SID block describes the default Subsystem Vendor ID and +/// Subsystem ID of the PCH devices. +/// This field will be ignored if the value of SubSystemVendorId and SubSystemId +/// are both 0. +/// If the SVID and SID registers of some PCH devices are filled before PchInit +/// driver execute then this field will be ignored because SVID and SID registers +/// are write once. +/// +typedef struct { + UINT16 SubSystemVendorId; ///< Default Subsystem Vendor ID of the PCH devices. + UINT16 SubSystemId; ///< Default Subsystem ID of the PCH devices. +} PCH_DEFAULT_SVID_SID; + +// +// --------------------------- Lock Down Config ------------------------------ +// +#define PCH_BWP_SIGNATURE EFI_SIGNATURE_32 ('P', 'B', 'W', 'P') +/// +/// The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH +/// for security requirement. +/// +typedef struct { + /// + /// Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. + /// + UINT8 GlobalSmi : 1; + /// + /// Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register + /// Top Swap bit and the General Control and Status Registers Boot BIOS Straps. + /// + UINT8 BiosInterface : 1; + /// + /// Enable GPIO Lockdown Enable bit to enables lockdown of the GPIO registers: + /// GPIO_USE_SEL, GP_IO_SEL, GP_LVL, GPIO_USE_SEL2, GP_IO_SEL2, GP_LVL2, + /// GPIO_USE_SEL3, GP_IO_SEL3, GP_LVL3, GP_RST_SEL. + /// + UINT8 GpioLockDown : 1; + /// + /// Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper + /// and lower 128-byte bank of RTC RAM. + /// + UINT8 RtcLock : 1; + /// + /// Enable the BIOS Lock Enable (BLE) feature and set SMM_BWP bit (D31:F0:RegDCh[5]) + /// for the BIOS region protection. When it is enabled, the BIOS Region can only be + /// modified from SMM after ExitPmAuth protocol is installed. + /// Note: When BiosLock is enabled, platform code also needs to update to take care + /// of BIOS modification (including SetVariable) in DXE or runtime phase after + /// ExitPmAuth protocol is installed. + /// + UINT8 BiosLock : 1; + UINT8 Rsvdbits : 3; + /// + /// Indicates the IO Address which is used to generate IO Trap SMI to register + /// IchnBiosWp callback function in PchBiosLockIoTrapCallback () to handle TCO + /// BIOSWR SMI. Please refer to the sample code of PchBiosWriteProtect driver for + /// more details about PchBiosLockIoTrapCallback().If PchBiosLockIoTrapAddress is 0, + /// BIOS will allocate available IO address with 256 byte range from GCD and pass it + /// to PchBiosLockIoTrapAddress. PCH Reference code replaces the SW SMI generated + /// by PchBiosLockSwSmiNumber with the IO Trap SMI generated by PchBiosLockIoTrapAddress. + /// + UINT16 PchBiosLockIoTrapAddress; ///< IO Trap range base address for Bios Lock +} PCH_LOCK_DOWN_CONFIG; + +// +// --------------------------- Thermal Config ------------------------------------ +// +typedef struct { + UINT8 TselLock : 1; + UINT8 TscLock : 1; + UINT8 TsmicLock : 1; + UINT8 PhlcLock : 1; + UINT8 Rsvdbits : 4; +} PCH_THERMAL_ALERT_ENABLE; + +typedef struct { + UINT32 T0Level : 9; + UINT32 T1Level : 9; + UINT32 T2Level : 9; + UINT32 TTEnable : 1; + UINT32 TTState13Enable : 1; + UINT32 TTLock : 1; + UINT32 SuggestedSetting : 1; ///< Enable/Disable suggested representative values + /// + /// ULT processors support thermal management and cross thermal throttling between the processor package + /// and LP PCH. The PMSYNC message from PCH to CPU includes specific bit fields to update the PCH + /// thermal status to the processor which is factored into the processor throttling. + /// Enable/Disable PCH Cross Throttling; 0: Disabled, 1: Enabled + /// + UINT32 PchCrossThrottling : 1; +} THERMAL_THROTTLE_LEVELS; + +typedef struct { + UINT8 DmiTsawEn : 1; ///< DMI Thermal Sensor Autonomous Width Enable + UINT8 SuggestedSetting : 1; ///< Enable/Disable suggested representative values + UINT8 Rsvdbits : 6; + + UINT8 TS0TW : 2; ///< Thermal Sensor 0 Target Width + UINT8 TS1TW : 2; ///< Thermal Sensor 1 Target Width + UINT8 TS2TW : 2; ///< Thermal Sensor 2 Target Width + UINT8 TS3TW : 2; ///< Thermal Sensor 3 Target Width +} DMI_HW_WIDTH_CONTROL; + +typedef struct { + UINT8 P0T1M : 2; ///< Port 0 T1 Multipler + UINT8 P0T2M : 2; ///< Port 0 T2 Multipler + UINT8 P0T3M : 2; ///< Port 0 T3 Multipler + UINT8 P0TDisp : 2; ///< Port 0 Tdispatch + + UINT8 P1T1M : 2; ///< Port 1 T1 Multipler + UINT8 P1T2M : 2; ///< Port 1 T2 Multipler + UINT8 P1T3M : 2; ///< Port 1 T3 Multipler + UINT8 P1TDisp : 2; ///< Port 1 Tdispatch + + UINT8 P0Tinact : 2; ///< Port 0 Tinactive + UINT8 P0TDispFinit : 1; ///< Port 0 Alternate Fast Init Tdispatch + UINT8 P1Tinact : 2; ///< Port 1 Tinactive + UINT8 P1TDispFinit : 1; ///< Port 1 Alternate Fast Init Tdispatch + UINT8 SuggestedSetting : 1; ///< Enable/Disable suggested representative values + UINT8 Rsvdbits : 1; +} SATA_THERMAL_THROTTLE; + +/// +/// If DmiIot of DmiConfig is enabled, the TTLevels and DmiHaAWC value will not be used. +/// +typedef struct { + THERMAL_THROTTLE_LEVELS TTLevels; + DMI_HW_WIDTH_CONTROL DmiHaAWC; + SATA_THERMAL_THROTTLE SataTT; +} PCH_THERMAL_THROTTLING; + +/// +/// The PCH_THERMAL_CONFIG block describes the expected configuration of the PCH for Thermal. +/// +typedef struct { + /// + /// This field determines if the PCH's TEMP_ALERT# pin will be asserted while the + /// temperature of processor core, PCH, Memory Controller/Graphics and DIMM is + /// outside the temperature limits. + /// + PCH_THERMAL_ALERT_ENABLE ThermalAlertEnable; + /// + /// This field reports the status of Thermal Device. When it reports ThermalDevice + /// is disabled, the PCI configuration space of thermal device will be hidden by + /// setting FD.TTD prior to end of POST. + /// + BOOLEAN ThermalDeviceEnable; + /// + /// This field decides the settings of Thermal throttling. When the Suggested Setting + /// is enabled, PCH RC will use the suggested representative values. + /// + PCH_THERMAL_THROTTLING ThermalThrottling; + /// + /// This field decides the temperature, 0x00 is the hottest temperature and 0x1FF + /// is the lowest temperature + /// + UINT16 PchHotLevel; +} PCH_THERMAL_CONFIG; + +// +// --------------------------- HPET Config ------------------------------ +// +typedef struct { + UINT8 BusNumber; ///< Bus Number HPETn used as Requestor / Completer ID + UINT8 DeviceNumber; ///< Device Number HPETn used as Requestor / Completer ID + UINT8 FunctionNumber; ///< Function Number HPETn used as Requestor / Completer ID +} PCH_HPET_BDF_CONFIG; + +/// +/// The PCH_LPC_HPET_CONFIG block describes the expected configuration of the PCH for HPET. +/// +typedef struct { + BOOLEAN BdfValid; ///< Whether the BDF value is valid + PCH_HPET_BDF_CONFIG Hpet[PCH_HPET_BDF_MAX]; ///< Lpc HPET n Bus:Device:Function Configuration +} PCH_LPC_HPET_CONFIG; + +// +// --------------------------- Serial IRQ Config ------------------------------ +// +typedef enum { + PchQuietMode, + PchContinuousMode +} PCH_SIRQ_MODE; +/// +/// Refer to PCH EDS for the details of Start Frame Pulse Width in Continuous and Quiet mode +/// +typedef enum { + PchSfpw4Clk, + PchSfpw6Clk, + PchSfpw8Clk +} PCH_START_FRAME_PULSE; + +/// +/// The PCH_LPC_SIRQ_CONFIG block describes the expected configuration of the PCH for Serial IRQ. +/// +typedef struct { + BOOLEAN SirqEnable; ///< Determines if enable Serial IRQ + PCH_SIRQ_MODE SirqMode; ///< Serial IRQ Mode Select. 0: quiet mode 1: continuous mode. + PCH_START_FRAME_PULSE StartFramePulse; ///< Start Frame Pulse Width +} PCH_LPC_SIRQ_CONFIG; + +// +// ---------------------------- DMI Config ----------------------------- +// +/// +/// The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI. +/// +typedef struct { + UINT8 DmiAspm : 1; ///< Enable/Disable ASPM on PCH side of the DMI Link. + ///< While DmiAspm is enabled, DMI ASPM will be set to Intel recommended value. + UINT8 DmiExtSync : 1; ///< Determines if force extended transmission of FTS ordered sets when + ///< exiting L0s prior to entering L0. + UINT8 DmiIot : 1; ///< Enable/Disable DMI IOT + UINT8 Rsvdbits : 5; +} PCH_DMI_CONFIG; + +// +// --------------------------- Power Optimizer Config ------------------------------ +// +typedef struct { + UINT8 LtrEnable :1; ///< Latency Tolerance Reporting Mechanism. + UINT8 ObffEnable :1; ///< Pcie end point Optimized Buffer Flush/Fill (OBFF) capability for the root port. + UINT8 LtrConfigLock :1; + UINT8 Rsvdbits :5; + UINT16 LtrMaxSnoopLatency; ///< Latency Tolerance Reporting, Max Snoop Latency. + UINT16 LtrMaxNoSnoopLatency; ///< Latency Tolerance Reporting, Max Non-Snoop Latency. + UINT8 SnoopLatencyOverrideMode; ///< Latency Tolerance Reporting, Snoop Latency Override Mode. + UINT8 SnoopLatencyOverrideMultiplier; ///< Latency Tolerance Reporting, Snoop Latency Override Multiplier. + UINT16 SnoopLatencyOverrideValue; ///< Latency Tolerance Reporting, Snoop Latency Override Value. + UINT8 NonSnoopLatencyOverrideMode; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Mode. + UINT8 NonSnoopLatencyOverrideMultiplier; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. + UINT16 NonSnoopLatencyOverrideValue; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Value. +} PCH_PCIE_PWR_OPT; + +typedef struct { + UINT16 VendorId; ///< PCI configuration space offset 0 + UINT16 DeviceId; ///< PCI configuration space offset 2 + UINT8 RevId; ///< PCI configuration space offset 8; 0xFF means all steppings +/** + SnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with + the scale in bits 12:10 +**/ + UINT16 SnoopLatency; +/** + NonSnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with + the scale in bits 12:10 +**/ + UINT16 NonSnoopLatency; +} PCH_PCIE_DEVICE_LTR_OVERRIDE; + +/// +/// The PCH_PWR_OPT_CONFIG block describes the expected configuration of the PCH for Power Optimizer. +/// +typedef struct { + UINT8 PchPwrOptDmi :1; ///< enable/disable DMI Power Optimizer on PCH side. + UINT8 PchPwrOptGbe :1; ///< enable/disable Gbe Power Optimizer on PCH side. + UINT8 PchPwrOptXhci :1; ///< enable/disable XHCI Power Optimizer on PCH side. + UINT8 PchPwrOptEhci :1; ///< enable/disable EHCI Power Optimizer on PCH side. + UINT8 PchPwrOptSata :1; ///< enable/disable SATA Power Optimizer on PCH side. + UINT8 MemCloseStateEn :1; ///< enable/disable MEM CLOSED State on PCH side. + UINT8 InternalObffEn :1; ///< enable/disable Optimized Buffer Flush/Fill (OBFF) protocol for internal on PCH side. + UINT8 ExternalObffEn :1; ///< enable/disable Optimized Buffer Flush/Fill (OBFF) protocol for external on PCH side. + UINT8 NumOfDevLtrOverride; ///< Number of Pci Express card listed in LTR override table + PCH_PCIE_DEVICE_LTR_OVERRIDE *DevLtrOverride; ///< Pointer to Pci Express devices LTR override table + PCH_PCIE_PWR_OPT PchPwrOptPcie[LPTH_PCIE_MAX_ROOT_PORTS]; ///< related configuration for PCIE ports power optimization. + UINT8 LegacyDmaDisable :1; ///< disable/enable legacy DMA controller (8254) and port 0x61 timer + UINT8 Rsvdbits :7; +} PCH_PWR_OPT_CONFIG; + +// +// --------------------- Miscellaneous Config ------------------------------ +// +/// +/// The PCH_MISC_CONFIG block describes the expected configuration of the PCH for Miscellaneous Configuration. +/// +typedef struct { + /// + /// This member determines the SMBIOS OEM type (0x80 to 0xFF) defined in SMBIOS + /// Type 14 - Group Associations structure - item type. + /// FVI structure uses it as SMBIOS OEM type to provide version information. + /// + UINT8 FviSmbiosType; + /// + /// This member enables/disables Direct Connect Interface (DCI) for LPT-LP. + /// When enabling DCI (through the enable bit), it's able to access JTAG and Run Control features + /// in a closed chassis situation, by using the USB3 port on a Shark Bay ULT platform. + /// + UINT8 DciEn :1; + UINT8 Rsvdbits :7; +} PCH_MISC_CONFIG; + +// +// ------------ General PCH Platform Policiy protocol definition ------------ +// +/// +/// The PCH platform policy protocol allows the platform code to publish a set of +/// configuration information that the PCH drivers will use to configure the PCH hardware. +/// The Revision field is used to accommodate backward compatible changes to the protocol. +/// The Revision should be initialized to DXE_PLATFORM_PCH_POLICY_PROTOCOL_REVISION_X +/// by the protocol producer. +/// The BusNumber field is used for platform to assign Bus number with multiple instances. +/// +struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL { + /// + /// This member specifies the revision of the PCH Policy protocol. + /// This field is used to indicate backwards compatible changes to the protocol. + /// Platform code that produces this protocol must fill with the correct revision + /// value for the PCH reference code to correctly interpret the content of the + /// protocol fields. + /// + UINT8 Revision; + /// + /// This member describes the desired bus number of the PCH controller. + /// + UINT8 BusNumber; + /// + /// This member describes which PCH devices should be enabled or disabled. + /// + PCH_DEVICE_ENABLING *DeviceEnabling; + /// + /// This member describes USB controller's related configuration. + /// + PCH_USB_CONFIG *UsbConfig; + /// + /// This member describes PCI Express controller's related configuration. + /// + PCH_PCI_EXPRESS_CONFIG *PciExpressConfig; + /// + /// This member describes SATA controller's related configuration. + /// + PCH_SATA_CONFIG *SataConfig; + /// + /// This member describes the Intel HD Audio (Azalia) related configuration. + /// + PCH_AZALIA_CONFIG *AzaliaConfig; + /// + /// This member describes SMBus related configuration. + /// + PCH_SMBUS_CONFIG *SmbusConfig; + /// + /// This member describes miscellaneous platform power management configurations. + /// + PCH_MISC_PM_CONFIG *MiscPmConfig; + /// + /// This member describes IOAPIC related configuration. + /// + PCH_IO_APIC_CONFIG *IoApicConfig; + /// + /// This member describes default SVID and Sid for PCH devices. + /// + PCH_DEFAULT_SVID_SID *DefaultSvidSid; + /// + /// This member describes LockDown related configuration. + /// + PCH_LOCK_DOWN_CONFIG *LockDownConfig; + /// + /// This member describes Thermal related configuration. + /// + PCH_THERMAL_CONFIG *ThermalConfig; + /// + /// This member describes HPET related configuration. + /// + PCH_LPC_HPET_CONFIG *HpetConfig; + /// + /// This member describes the expected configuration of the PCH for Serial IRQ. + /// + PCH_LPC_SIRQ_CONFIG *SerialIrqConfig; + /// + /// This member describes DMI related configuration. + /// + PCH_DMI_CONFIG *DmiConfig; + /// + /// This member describes the Power Optimizer configuration. + /// + PCH_PWR_OPT_CONFIG *PwrOptConfig; + /// + /// This member describes the Miscellaneous configuration. + /// + PCH_MISC_CONFIG *MiscConfig; + /// + /// This member describes the Audio Dsp related configuration + /// + PCH_AUDIO_DSP_CONFIG *AudioDspConfig; + /// + /// This member describes the Serial IO related configuration + /// + PCH_SERIAL_IO_CONFIG *SerialIoConfig; +}; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/PchReset/PchReset.c b/ReferenceCode/Chipset/LynxPoint/Protocol/PchReset/PchReset.c new file mode 100644 index 0000000..28210a6 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/PchReset/PchReset.c @@ -0,0 +1,44 @@ +/** @file + This file defines the PCH Reset Protocol + +@copyright + Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +// +// Include the protocol header file +// +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) + +#include "EdkIIGlueDxe.h" +#endif + +#include "PchReset.h" + +// +// Protocol GUID definition +// +EFI_GUID gPchResetProtocolGuid = PCH_RESET_PROTOCOL_GUID; +EFI_GUID gPchResetCallbackProtocolGuid = PCH_RESET_CALLBACK_PROTOCOL_GUID; + +// +// Protocol description +// +EFI_GUID_STRING(&gPchResetProtocolGuid, "PCH Reset Protocol", "Intel(R) PCH Reset Protocol"); +EFI_GUID_STRING(&gPchResetProtocolGuid, "PCH Reset Callback Protocol", "Intel(R) PCH Reset Callback Protocol"); diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/PchReset/PchReset.h b/ReferenceCode/Chipset/LynxPoint/Protocol/PchReset/PchReset.h new file mode 100644 index 0000000..f11a744 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/PchReset/PchReset.h @@ -0,0 +1,139 @@ +/** @file + PCH Reset Protocol + +@copyright + Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _PCH_RESET_H_ +#define _PCH_RESET_H_ + +/// +/// GUID for the PCH Reset Protocol +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define PCH_RESET_PROTOCOL_GUID \ + { \ + 0xdb63592c, 0xb8cc, 0x44c8, 0x91, 0x8c, 0x51, 0xf5, 0x34, 0x59, 0x8a, 0x5a \ + } +#define PCH_RESET_CALLBACK_PROTOCOL_GUID \ + { \ + 0x3a3300ab, 0xc929, 0x487d, 0xab, 0x34, 0x15, 0x9b, 0xc1, 0x35, 0x62, 0xc0 \ + } +#else +#define PCH_RESET_PROTOCOL_GUID \ + { \ + 0xdb63592c, 0xb8cc, 0x44c8, \ + { \ + 0x91, 0x8c, 0x51, 0xf5, 0x34, 0x59, 0x8a, 0x5a \ + } \ + } +#define PCH_RESET_CALLBACK_PROTOCOL_GUID \ + { \ + 0x3a3300ab, 0xc929, 0x487d, \ + { \ + 0xab, 0x34, 0x15, 0x9b, 0xc1, 0x35, 0x62, 0xc0 \ + } \ + } +#endif + +#define EFI_CAPSULE_VARIABLE_NAME L"CapsuleUpdateData" + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchResetProtocolGuid; +extern EFI_GUID gPchResetCallbackProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_RESET_PROTOCOL PCH_RESET_PROTOCOL; + +typedef struct _PCH_RESET_CALLBACK_PROTOCOL PCH_RESET_CALLBACK_PROTOCOL; + +// +// Related Definitions +// +/// +/// PCH Reset Types +/// +typedef enum { + ColdReset, + WarmReset, + ShutdownReset, + PowerCycleReset, + GlobalReset, + GlobalResetWithEc +} PCH_RESET_TYPE; + +// +// Member functions +// +/** + Execute Pch Reset from the host controller. + + @param[in] This Pointer to the PCH_RESET_PROTOCOL instance. + @param[in] PchResetType Pch Reset Types which includes ColdReset, WarmReset, ShutdownReset, + PowerCycleReset, GlobalReset, GlobalResetWithEc + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER If ResetType is invalid. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_RESET) ( + IN PCH_RESET_PROTOCOL * This, + IN PCH_RESET_TYPE PchResetType + ); + +/** + Execute call back function for Pch Reset. + + @param[in] PchResetType Pch Reset Types which includes PowerCycle, Globalreset. + + @retval EFI_SUCCESS The callback function has been done successfully + @retval EFI_NOT_FOUND Failed to find Pch Reset Callback protocol. Or, none of + callback protocol is installed. + @retval Others Do not do any reset from PCH +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_RESET_CALLBACK) ( + IN PCH_RESET_TYPE PchResetType + ); + +/// +/// Interface structure for the Pch Reset Protocol +/// +struct _PCH_RESET_PROTOCOL { + PCH_RESET Reset; +}; + +/// +/// PCH_RESET_CALLBACK_PROTOCOL Structure Definition +/// +/// This protocol is used to execute PCH Reset from the host controller. +/// The PCH Reset protocol and PCH Reset PPI implement the Intel (R) PCH Reset Interface +/// for DXE and PEI environments, respectively. If other drivers need to run their +/// callback function right before issuing the reset, they can install PCH Reset +/// Callback Protocol/PPI before PCH Reset DXE/PEI driver to achieve that. +/// +struct _PCH_RESET_CALLBACK_PROTOCOL { + PCH_RESET_CALLBACK ResetCallback; +}; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/PchS3Support/PchS3Support.c b/ReferenceCode/Chipset/LynxPoint/Protocol/PchS3Support/PchS3Support.c new file mode 100644 index 0000000..284ad1e --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/PchS3Support/PchS3Support.c @@ -0,0 +1,43 @@ +/** @file + This file defines the PCH S3 Support Protocol. + +@copyright + Copyright (c) 2008 - 2015 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +// +// Statements that include other files +// +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGlueDxe.h" +#endif + +#include "PchS3Support.h" + +// +// Protocol GUID definition +// +EFI_GUID gEfiPchS3SupportProtocolGuid = EFI_PCH_S3_SUPPORT_PROTOCOL_GUID; +EFI_GUID gEfiPchS3SupportSmmProtocolGuid = EFI_PCH_S3_SUPPORT_SMM_PROTOCOL_GUID; + +// +// Protocol description +// +EFI_GUID_STRING(&gEfiPchS3SupportProtocolGuid, "PCH S3 Support Protocol", "PCH S3 Support Protocol"); +EFI_GUID_STRING(&gEfiPchS3SupportSmmProtocolGuid, "PCH S3 SMM Support Protocol", "PCH S3 SMM Support Protocol"); diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/PchS3Support/PchS3Support.h b/ReferenceCode/Chipset/LynxPoint/Protocol/PchS3Support/PchS3Support.h new file mode 100644 index 0000000..5ac64a6 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/PchS3Support/PchS3Support.h @@ -0,0 +1,218 @@ +/** @file + This file defines the PCH S3 support Protocol. + +@copyright + Copyright (c) 2008 - 2015 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _PCH_S3_SUPPORT_PROTOCOL_H_ +#define _PCH_S3_SUPPORT_PROTOCOL_H_ + +/// +/// Define the PCH S3 Support protocol GUID +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define EFI_PCH_S3_SUPPORT_PROTOCOL_GUID \ + { \ + 0x2224aee3, 0x8d0b, 0x480a, 0xb2, 0x72, 0x2a, 0xbe, 0x92, 0xcd, 0x4e, 0x78 \ + } +#else +#define EFI_PCH_S3_SUPPORT_PROTOCOL_GUID \ + { \ + 0x2224aee3, 0x8d0b, 0x480a, \ + { \ + 0xb2, 0x72, 0x2a, 0xbe, 0x92, 0xcd, 0x4e, 0x78 \ + } \ + } +#endif + +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define EFI_PCH_S3_SUPPORT_SMM_PROTOCOL_GUID \ + { \ + 0xe8fe82e8, 0x7d00, 0x41ff, 0x91, 0x1e, 0xb, 0x99, 0x6f, 0x85, 0xc9, 0x57 \ + } +#else +#define EFI_PCH_S3_SUPPORT_SMM_PROTOCOL_GUID \ + { \ + 0xe8fe82e8, 0x7d00, 0x41ff, \ + { \ + 0x91, 0x1e, 0xb, 0x99, 0x6f, 0x85, 0xc9, 0x57 \ + } \ + } +#endif + +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define EFI_PCH_S3_SUPPORT_DATA_GUID \ + { 0xd5beb067, 0xc08e, 0x40fb, 0x8f, 0x27, 0x52, 0x0, 0xcf, 0xe4, 0x2c, 0x9 } +#else +#define EFI_PCH_S3_SUPPORT_DATA_GUID \ + { 0xd5beb067, 0xc08e, 0x40fb, { 0x8f, 0x27, 0x52, 0x0, 0xcf, 0xe4, 0x2c, 0x9 } } +#endif + +#include "PchPlatformPolicy/PchPlatformPolicy.h" + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiPchS3SupportProtocolGuid; +extern EFI_GUID gEfiPchS3SupportSmmProtocolGuid; +extern EFI_GUID gS3SupportSmramDataGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _EFI_PCH_S3_SUPPORT_PROTOCOL EFI_PCH_S3_SUPPORT_PROTOCOL; +typedef struct _EFI_PCH_S3_SUPPORT_SMM_PROTOCOL EFI_PCH_S3_SUPPORT_SMM_PROTOCOL; + +typedef enum { + PchS3ItemTypeSendCodecCommand, + PchS3ItemTypeInitPcieRootPortDownstream, + PchS3ItemTypePcieSetPm, + PchS3ItemTypeProgramIobp, + PchS3ItemTypeMax +} EFI_PCH_S3_DISPATCH_ITEM_TYPE; + +/// +/// In the following structures it is required that they are usable in both PEI (32-bit) and DXE (64-bit). +/// As a result, Pointers and Enumerations will be of different underlying sizes. Therefore neither should +/// appear in the middle of these structures. If done, then size adjustment will need to be explicit +/// via other mechanisms (like a union). +/// +typedef struct { + UINT32 HdaBar; + UINT32 CodecCmdData; +} EFI_PCH_S3_PARAMETER_SEND_CODEC_COMMAND; + +typedef struct { + UINT8 RootPortBus; + UINT8 RootPortDevice; + UINT8 RootPortFunc; + UINT8 TempBusNumberMin; + UINT8 TempBusNumberMax; +} EFI_PCH_S3_PARAMETER_INIT_PCIE_ROOT_PORT_DOWNSTREAM; + +typedef struct { + UINT8 RootPortBus; + UINT8 RootPortDevice; + UINT8 RootPortFunc; + PCH_PCI_EXPRESS_ASPM_CONTROL RootPortAspm; + UINT8 NumOfDevAspmOverride; + UINT32 DevAspmOverrideAddr; + UINT8 TempBusNumberMin; + UINT8 TempBusNumberMax; + UINT8 NumOfDevLtrOverride; + UINT32 DevLtrOverrideAddr; + UINT32 PchPwrOptPcie; + PCH_PCIE_EXPRESS_L1SUBSTATES_CONTROL L1SubstatesConfig; + UINT8 PolicyRevision; + BOOLEAN FirstRPToSetPm; + BOOLEAN L1SupportedInAllEnabledPorts; + BOOLEAN ClkreqSupportedInAllEnabledPorts; +} EFI_PCH_S3_PARAMETER_PCIE_SET_PM; + +typedef struct { + UINT32 RootComplexBar; + UINT32 Address; + UINT32 AndMask; + UINT32 OrMask; +} EFI_PCH_S3_PARAMETER_PROG_IOBP; + +typedef struct { + union { // The union definition is in place because this structure + EFI_PCH_S3_DISPATCH_ITEM_TYPE Value; // is used in both DXE and PEI where enumerations are + UINT64 Spacer; // different sizes. + } ItemType; + VOID *Parameter; +} EFI_PCH_S3_DISPATCH_ITEM; + +typedef struct { + EFI_GUID PchS3CustomScriptGuid; + UINT32 MaximumBufferSize; + UINT32 BufferSpaceRemaining; + UINT8 *NextDispatchItem; + //EFI_PCH_S3_DISPATCH_ITEM DispatchItemAray[] // This structure is followed in memory + // by an Array of EFI_PCH_S3_DISPATCH_ITEM structures +} EFI_PCH_S3_DISPATCH_ARRAY; + +#define QWORD_ALIGNED_SIZE(x) ((sizeof (x) + 7) / 8 * 8) // QWORD alignment is needed for the variable lengths + // of the "Parameter" field of the EFI_PCH_S3_DISPATCH_ITEM + // structure. Alignment must be maintained between + // the 32-bit PEI code and 64-bit DXE code. + +// +// Member functions +// +/** + Set an item to be dispatched at S3 resume time. At the same time, the entry point + of the PCH S3 support image is returned to be used in subsequent boot script save + call + + @param[in] This Pointer to the protocol instance. + @param[in] DispatchItem The item to be dispatched. + @param[out] S3DispatchEntryPoint The entry point of the PCH S3 support image. + + @retval EFI_STATUS Successfully completed. + @retval EFI_OUT_OF_RESOURCES Out of resources. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCH_S3_SUPPORT_SET_S3_DISPATCH_ITEM) ( + IN EFI_PCH_S3_SUPPORT_PROTOCOL * This, + IN EFI_PCH_S3_DISPATCH_ITEM * DispatchItem, + OUT EFI_PHYSICAL_ADDRESS * S3DispatchEntryPoint + ); + +/** + Perform the EFI_PCH_S3_SUPPORT_SMM_PROTOCOL IO Trap to invoke DispatchArray data copy and + IO Trap Unregister. + + @param[in] This Pointer to the protocol instance. + + @retval EFI_STATUS Successfully completed. + @retval EFI_OUT_OF_RESOURCES Out of resources. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCH_S3_SUPPORT_READY_TO_LOCK) ( + IN EFI_PCH_S3_SUPPORT_PROTOCOL *This + ); + +/// +/// Protocol definition +/// +/// This Protocol is used to set an item to be dispatched at S3 resume time. +/// At the same time, the entry point of the PCH S3 support image is returned to +/// be used in subsequent boot script save call. +/// +struct _EFI_PCH_S3_SUPPORT_PROTOCOL { + EFI_PCH_S3_SUPPORT_SET_S3_DISPATCH_ITEM SetDispatchItem; ///< Set the item to be dispatched at S3 resume time. + EFI_PCH_S3_SUPPORT_READY_TO_LOCK ReadyToLock; ///< The caller is finished using the protocol and it can be locked. +}; + + +/// +/// Protocol Definition +/// +/// This Protocol is used to communicate the location of the Boot Services copy of the EFI_PCH_S3_DISPATCH_ARRAY. +/// The pointer is then used to allow the SMM module to copy the data to the appropriate SMRAM location. The +/// ProtocolSize is communicated in # of Pages. +/// +struct _EFI_PCH_S3_SUPPORT_SMM_PROTOCOL { + UINT16 ProtocolSize; ///< Protocol size in Pages (due to Page alignment requirements in SMM) + UINT16 PchS3SupportIoTrap; ///< IO Trap port to support ExitPmAuth notification for copy and unregister + EFI_PCH_S3_DISPATCH_ARRAY *DispatchArray; ///< A pointer to the Boot Services copy of the Dispatch Array +}; +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/PchSmmIoTrapControl/PchSmmIoTrapControl.c b/ReferenceCode/Chipset/LynxPoint/Protocol/PchSmmIoTrapControl/PchSmmIoTrapControl.c new file mode 100644 index 0000000..c32e7ff --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/PchSmmIoTrapControl/PchSmmIoTrapControl.c @@ -0,0 +1,42 @@ +/** @file + This file defines the PCH SMM IO Trap Control Protocol + +@copyright + Copyright (c) 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +// +// Include the protocol header file +// +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) + +#include "EdkIIGlueDxe.h" +#endif + +#include "PchSmmIoTrapControl.h" + +// +// Protocol GUID definition +// +EFI_GUID gPchSmmIoTrapControlGuid = PCH_SMM_IO_TRAP_CONTROL_GUID; + +// +// Protocol description +// +EFI_GUID_STRING(&gPchSmmIoTrapDispatchProtocolGuid, "PCH IO Trap Control Protocol", "EFI PCH SMM IO Trap Control Protocol"); diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/PchSmmIoTrapControl/PchSmmIoTrapControl.h b/ReferenceCode/Chipset/LynxPoint/Protocol/PchSmmIoTrapControl/PchSmmIoTrapControl.h new file mode 100644 index 0000000..2e0395e --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/PchSmmIoTrapControl/PchSmmIoTrapControl.h @@ -0,0 +1,90 @@ +/** @file + PCH SMM IO Trap Control Protocol + +@copyright + Copyright (c) 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _PCH_SMM_IO_TRAP_CONTROL_H_ +#define _PCH_SMM_IO_TRAP_CONTROL_H_ + +/// +/// GUID for the SMM IO Trap Control Protocol +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define PCH_SMM_IO_TRAP_CONTROL_GUID \ + { \ + 0x514D2AFD, 0x2096, 0x4283, 0x9D, 0xA6, 0x70, 0x0C, 0xD2, 0x7D, 0xC7, 0xA5 \ + } +#else +#define PCH_SMM_IO_TRAP_CONTROL_GUID \ + { \ + 0x514D2AFD, 0x2096, 0x4283, \ + { \ + 0x9D, 0xA6, 0x70, 0x0C, 0xD2, 0x7D, 0xC7, 0xA5 \ + } \ + } +#endif + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchSmmIoTrapControlGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL PCH_SMM_IO_TRAP_CONTROL_PROTOCOL; + +// +// Related Definitions +// + +// +// Member functions +// + +/** + The Prototype of Pause and Resume IoTrap callback function. + + @param[in] This Pointer to the PCH_SMM_IO_TRAP_CONTROL_PROTOCOL instance. + @param[in] DispatchHandle Handle of the child service to change state. + + @retval EFI_SUCCESS This operation is complete. + @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid. + @retval EFI_ACCESS_DENIED The SMI status is alrady PAUSED/RESUMED. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SMM_IO_TRAP_CONTROL_FUNCTION) ( + IN PCH_SMM_IO_TRAP_CONTROL_PROTOCOL * This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for the SMM IO trap pause and resume protocol + This protocol provides the functions to runtime control the IoTrap SMI enabled/disable. + This applys the capability to the DispatchHandle which returned by IoTrap callback + registration, and the DispatchHandle which must be MergeDisable = TRUE and Address != 0. + Besides, when S3 resuem, it only restores the state of IoTrap callback registration. + The Paused/Resume state won't be restored after S3 resume. +**/ +struct _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL { + PCH_SMM_IO_TRAP_CONTROL_FUNCTION Pause; + PCH_SMM_IO_TRAP_CONTROL_FUNCTION Resume; +}; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/SerialGpio/SerialGpio.c b/ReferenceCode/Chipset/LynxPoint/Protocol/SerialGpio/SerialGpio.c new file mode 100644 index 0000000..09c40e1 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/SerialGpio/SerialGpio.c @@ -0,0 +1,34 @@ +/** @file + This file defines the EFI Serial GPIO Interface Protocol which implements the + Intel(R) Serial Data over GPIO Pin functionality Protocol Interface. + +@copyright + Copyright (c) 2004 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +// +// Include the protocol header file +// +#include "SerialGpio.h" + +// +// Protocol GUID definition +// +EFI_GUID gEfiSerialGpioProtocolGuid = EFI_SERIAL_GPIO_PROTOCOL_GUID; + +// +// Protocol description +// +EFI_GUID_STRING(&gEfiSerialGpioProtocolGuid, "Serial GPIO Protocol", "Intel(R) Serial GPIO Interface Protocol"); diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/SerialGpio/SerialGpio.h b/ReferenceCode/Chipset/LynxPoint/Protocol/SerialGpio/SerialGpio.h new file mode 100644 index 0000000..9559cb1 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/SerialGpio/SerialGpio.h @@ -0,0 +1,166 @@ +/** @file + This file defines the EFI Serial GPIO Interface Protocol which implements the + Intel(R) Serial Data over GPIO Pin functionality Protocol Interface. + +@copyright + Copyright (c) 2004 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _EFI_SERIAL_GPIO_H_ +#define _EFI_SERIAL_GPIO_H_ + +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) + +#include "EdkIIGlueDxe.h" +#endif +/// +/// Define the Serial GPIO protocol GUID +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define EFI_SERIAL_GPIO_PROTOCOL_GUID \ + { \ + 0xf52c3858, 0x5ef8, 0x4d41, 0x83, 0x4e, 0xc3, 0x9e, 0xef, 0x8a, 0x45, 0xa3 \ + } +#else +#define EFI_SERIAL_GPIO_PROTOCOL_GUID \ + { \ + 0xf52c3858, 0x5ef8, 0x4d41, \ + { \ + 0x83, 0x4e, 0xc3, 0x9e, 0xef, 0x8a, 0x45, 0xa3 \ + } \ + } +#endif +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiSerialGpioProtocolGuid; +// +// Forward reference for ANSI C compatibility +// +typedef struct _EFI_SERIAL_GPIO_PROTOCOL EFI_SERIAL_GPIO_PROTOCOL; + +// +// This is the max number of GPIO pins in this ICH chipset that support Blink feature +// 0~31 GPIO in ICH8M support blink feature +// +#define SERIAL_GPIO_MAX_PIN_NUMBER 32 +#define SERIAL_GPIO_MAX_DATA_RATE 63 +#define WAIT_TIME 100000 +#define WAIT_PERIOD 10 + +/// +/// Serial GPIO protocol data structures and definitions +/// +typedef enum { + EnumSerialGpioDataByte, + EnumSerialGpioDataWord, + EnumSerialGpioDataUndefined, + EnumSerialGpioDataDword, + EnumSerialGpioDataMax +} SERIAL_GPIO_DATA_WIDTH; + +// +// Protocol member functions +// +/** + Register for one GPIO Pin that will be used as serial GPIO. + For PCH only GPIO0~31 will have the capability to be used as serail GPIO. + The caller of this procedure need to be very clear of whPch GPIO should be used as serail GPIO, + it should not be input, native, conflict with other GPIO, or Index > 31 on the caller's platform. + + @param[in] This Pointer to the EFI_SERIAL_GPIO_PROTOCOL instance. + @param[in] SerialGpioPinIndex The GPIO pin Index that will be used as serial GPIO for data sending. + + @retval EFI_SUCCESS Opcode initialization on the SERIAL_GPIO host controller completed. + @retval EFI_ACCESS_DENIED The SERIAL_GPIO configuration interface is locked. + @retval EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device. + @retval EFI_DEVICE_ERROR Device error, operation failed. + @retval EFI_INVALID_PARAMETER SerialGpioPinIndex is out of range +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SERIAL_GPIO_REGISTER) ( + IN EFI_SERIAL_GPIO_PROTOCOL * This, + IN UINT8 SerialGpioPinIndex + ); + +/** + Unregister for one GPIO Pin that has been used as serial GPIO, and recover the registers before + registering. + + @param[in] This Pointer to the EFI_SERIAL_GPIO_PROTOCOL instance. + @param[in] SerialGpioPinIndex The GPIO pin Index that will be used as serial GPIO for data sending. + + @retval EFI_SUCCESS Opcode initialization on the SERIAL_GPIO host controller completed. + @retval EFI_ACCESS_DENIED The SERIAL_GPIO configuration interface is locked. + @retval EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device. + @retval EFI_DEVICE_ERROR Device error, operation failed. + @retval EFI_INVALID_PARAMETER Invalid function parameters +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SERIAL_GPIO_UNREGISTER) ( + IN EFI_SERIAL_GPIO_PROTOCOL * This, + IN UINT8 SerialGpioPinIndex + ); + +/** + Execute SERIAL_GPIO commands from the host controller. + + @param[in] This Pointer to the EFI_SERIAL_GPIO_PROTOCOL instance. + @param[in] GpioPinIndex Index of the GPIO pin. + @param[in] DataRate The data rate for serail data transfering. 1 ~ SERIAL_GPIO_MAX_DATA_RATE; 1: 128ns intervals; ...; 8: 8*128 = 1024ns intervals, default value;... + @param[in] DataCountInByte Number of bytes of the data will be transmitted through the GPIO pin. + @param[in, out] Buffer Pointer to caller-allocated buffer containing the dada sent through the GPIO pin. + + @retval EFI_SUCCESS Execute succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, GPIO serial data sent failed. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SERIAL_GPIO_SEND_DATA) ( + IN EFI_SERIAL_GPIO_PROTOCOL * This, + IN UINT8 GpioPinIndex, + IN UINT8 DataRate, + IN UINTN DataCountInByte, + IN OUT UINT8 *Buffer + ); + +/// +/// Protocol definition +/// +/// This Protocol allows a platform module to execute the IntelR Serial Data over +/// GPIO Pin functionality Protocol Interface. +/// The caller will first call the SerialGpioRegister() function to configure the GPIO +/// to be used. Then the caller will execute one or more calls to the SerialGpioSendData() +/// function to perform serial GPIO activities. Finally, the caller will use the +/// SerialGpioUnRegister() function to un-register and allow other consumers to utilize +/// the serial GPIO services. +/// If the serial GPIO capabilities are in use by another caller, the registration +/// function will return an error. +/// +struct _EFI_SERIAL_GPIO_PROTOCOL { + EFI_SERIAL_GPIO_REGISTER SerialGpioRegister; ///< Register for one GPIO pin that will be used as serial GPIO. + EFI_SERIAL_GPIO_SEND_DATA SerialGpioSendData; ///< Execute SERIAL_GPIO commands from the host controller. + EFI_SERIAL_GPIO_UNREGISTER SerialGpioUnRegister; ///< Un-register the current GPIO pin used for serial GPIO, and recovers the registers before registering. +}; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/SmmIchnDispatchEx/SmmIchnDispatchEx.c b/ReferenceCode/Chipset/LynxPoint/Protocol/SmmIchnDispatchEx/SmmIchnDispatchEx.c new file mode 100644 index 0000000..224e62f --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/SmmIchnDispatchEx/SmmIchnDispatchEx.c @@ -0,0 +1,46 @@ +/** @file + This file defines the SmmIchnDispatch Extended Protocol + +@copyright + Copyright (c) 2008 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +// +// Include the protocol header file +// +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) + +#include "EdkIIGlueDxe.h" +#endif + +#include "SmmIchnDispatchEx.h" + +// +// Protocol GUID definition +// +EFI_GUID gEfiSmmIchnDispatchExProtocolGuid = EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL_GUID; + +// +// Protocol description +// +EFI_GUID_STRING + ( + &gEfiSmmIchnDispatchExProtocolGuid, "SMM ICHn SMI Dispatch Extended Protocol", + "EFI 2.0 SMM ICHn SMI Dispatch Extended Protocol" + ); diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/SmmIchnDispatchEx/SmmIchnDispatchEx.h b/ReferenceCode/Chipset/LynxPoint/Protocol/SmmIchnDispatchEx/SmmIchnDispatchEx.h new file mode 100644 index 0000000..79e5ad7 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/SmmIchnDispatchEx/SmmIchnDispatchEx.h @@ -0,0 +1,177 @@ +/** @file + SmmIchnDispatch Extended Protocol + +@copyright + Copyright (c) 2008 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _EFI_SMM_ICHN_DISPATCH_EX_H_ +#define _EFI_SMM_ICHN_DISPATCH_EX_H_ + +/// +/// GUID for the SmmIchnDispatch Extended Protocol +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL_GUID \ + { \ + 0x3920405b, 0xc897, 0x44da, 0x88, 0xf3, 0x4c, 0x49, 0x8a, 0x6f, 0xf7, 0x36 \ + } +#else +#define EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL_GUID \ + { \ + 0x3920405b, 0xc897, 0x44da, \ + { \ + 0x88, 0xf3, 0x4c, 0x49, 0x8a, 0x6f, 0xf7, 0x36 \ + } \ + } + +#endif +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiSmmIchnDispatchExProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL; + +// +// Related Definitions +// +/// +/// Ichn Dispatch Extended Types +/// +typedef enum { + IchnExPciExpress = NUM_ICHN_TYPES + 1, + IchnExMonitor, + IchnExSpi, + IchnExQRT, + IchnExGpioUnlock, + IchnExTmrOverflow, + IchnExPcie0Hotplug, + IchnExPcie1Hotplug, + IchnExPcie2Hotplug, + IchnExPcie3Hotplug, + IchnExPcie4Hotplug, + IchnExPcie5Hotplug, + IchnExPcie6Hotplug, + IchnExPcie7Hotplug, + IchnExPcie0LinkActive, + IchnExPcie1LinkActive, + IchnExPcie2LinkActive, + IchnExPcie3LinkActive, + IchnExPcie4LinkActive, + IchnExPcie5LinkActive, + IchnExPcie6LinkActive, + IchnExPcie7LinkActive, + // + // INSERT NEW ITEMS JUST BEFORE THIS LINE + // + IchnExTypeMAX ///< the maximum number of items in this enumeration +} EFI_SMM_ICHN_EX_SMI_TYPE; + +typedef struct { + EFI_SMM_ICHN_EX_SMI_TYPE Type; +} EFI_SMM_ICHN_DISPATCH_EX_CONTEXT; + +// +// Member functions +// + +/** + Dispatch function for a ICH n Extended specific SMI handler. + + @param[in] DispatchHandle Handle of this dispatch function. + @param[in] DispatchContext Pointer to the dispatch function's context. + The DispatchContext fields are filled in + by the dispatching driver prior to + invoking this dispatch function. + + @retval None +**/ +typedef +VOID +(EFIAPI *EFI_SMM_ICHN_DISPATCH_EX) ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_ICHN_DISPATCH_EX_CONTEXT * DispatchContext + ); + +/** + Register a child SMI source dispatch function with a parent SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchFunction Pointer to dispatch function to be invoked for + this SMI source + @param[in] DispatchContext Pointer to the dispatch function's context. + The caller fills this context in before calling + the register function to indicate to the register + function the ICHN SMI source for which the dispatch + function should be invoked. + @param[out] DispatchHandle Handle of dispatch function, for when interfacing + with the parent SMM driver. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the SMI source has been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source. + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this + child. + @retval EFI_INVALID_PARAMETER DispatchContext is invalid. The ICHN input value + is not within valid range. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMM_ICHN_EX_REGISTER) ( + IN EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL * This, + IN EFI_SMM_ICHN_DISPATCH_EX DispatchFunction, + IN EFI_SMM_ICHN_DISPATCH_EX_CONTEXT * DispatchContext, + OUT EFI_HANDLE * DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to deregister. + + @retval EFI_SUCCESS The dispatch function has been successfully + unregistered and the SMI source has been disabled + if there are no other registered child dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval Others TBD +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMM_ICHN_EX_UNREGISTER) ( + IN EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL * This, + IN EFI_HANDLE DispatchHandle + ); + +/// +/// Interface structure for the SMM Ich n specific SMI Dispatch Protocol +/// +/// This protocol provides the ability to dispatch function for a ICHn specific SMI. +/// This protocol acts as an extension to the EFI_SMM_ICHN_DISPATCH_PROTOCOL capabilities +/// by defining several new SMI types: IchnExPciExpress, IchnExMonitor, IchnExSpi, +/// IchnExQRT, IchnGpioUnlockSmi, IchnExTmrOverflow, IchnExPcieXHotplug, IchnExPcieXLinkActive. +/// +struct _EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL { + EFI_SMM_ICHN_EX_REGISTER Register; ///< Register a child SMI source dispatch function with a parent SMM driver. + EFI_SMM_ICHN_EX_UNREGISTER UnRegister; ///< Un-register a child SMI source dispatch function with a parent SMM driver. +}; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/SmmIoTrapDispatch/SmmIoTrapDispatch.c b/ReferenceCode/Chipset/LynxPoint/Protocol/SmmIoTrapDispatch/SmmIoTrapDispatch.c new file mode 100644 index 0000000..dfd348f --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/SmmIoTrapDispatch/SmmIoTrapDispatch.c @@ -0,0 +1,42 @@ +/** @file + This file defines the PCH SMM IO Trap Dispatch Protocol + +@copyright + Copyright (c) 2005 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +// +// Include the protocol header file +// +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) + +#include "EdkIIGlueDxe.h" +#endif + +#include "SmmIoTrapDispatch.h" + +// +// Protocol GUID definition +// +EFI_GUID gEfiSmmIoTrapDispatchProtocolGuid = EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL_GUID; + +// +// Protocol description +// +EFI_GUID_STRING(&gEfiSmmIoTrapDispatchProtocolGuid, "SMM IO Trap Protocol", "EFI PCH SMM IO Trap Protocol"); diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/SmmIoTrapDispatch/SmmIoTrapDispatch.h b/ReferenceCode/Chipset/LynxPoint/Protocol/SmmIoTrapDispatch/SmmIoTrapDispatch.h new file mode 100644 index 0000000..8923d3c --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/SmmIoTrapDispatch/SmmIoTrapDispatch.h @@ -0,0 +1,182 @@ +/** @file + PCH SMM IO Trap Dispatch Protocol + +@copyright + Copyright (c) 2005 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _EFI_SMM_IO_TRAP_DISPATCH_H_ +#define _EFI_SMM_IO_TRAP_DISPATCH_H_ + +/// +/// GUID for the SMM IO Trap Dispatch Protocol +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL_GUID \ + { \ + 0xdb7f536b, 0xede4, 0x4714, 0xa5, 0xc8, 0xe3, 0x46, 0xeb, 0xaa, 0x20, 0x1d \ + } +#else +#define EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL_GUID \ + { \ + 0xdb7f536b, 0xede4, 0x4714, \ + { \ + 0xa5, 0xc8, 0xe3, 0x46, 0xeb, 0xaa, 0x20, 0x1d \ + } \ + } +#endif +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiSmmIoTrapDispatchProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL; + +// +// Related Definitions +// +/// +/// IO Trap valid types +/// +typedef enum { + WriteTrap, + ReadTrap, + ReadWriteTrap, + IoTrapTypeMaximum +} EFI_SMM_IO_TRAP_DISPATCH_TYPE; + +/// +/// IO Trap context structure containing information about the IO trap event that should invoke the callback +/// +typedef struct { + UINT16 Address; ///< IO Trap range base address (NULL means allocate) + UINT16 Length; ///< IO Trap range length + EFI_SMM_IO_TRAP_DISPATCH_TYPE Type; ///< Access types to trap on + VOID *Context; ///< Callback function context + BOOLEAN MergeDisable; ///< Determine if IoTrap needs to be merged with other registered IoTrap +} EFI_SMM_IO_TRAP_DISPATCH_REGISTER_CONTEXT; + +/// +/// IO Trap context structure containing information about the IO trap that occurred +/// +typedef struct { + UINT16 Address; ///< IO address trapped + EFI_SMM_IO_TRAP_DISPATCH_TYPE Type; ///< IO access type + UINT32 WriteData; ///< Data written (contents undefined for read trap) + VOID *Context; ///< Callback function context +} EFI_SMM_IO_TRAP_DISPATCH_CALLBACK_CONTEXT; + +// +// Member functions +// + +/** + Dispatch function for an IO Trap specific SMI handler. + + @param[in] DispatchHandle Handle of this dispatch function. + @param[in] CallbackContext Pointer to the dispatched function's context. + The CallbackContext fields are updated + by the dispatching driver prior to + invoking this callback function. + + @retval None +**/ +typedef +VOID +(EFIAPI *EFI_SMM_IO_TRAP_DISPATCH_CALLBACK) ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_IO_TRAP_DISPATCH_CALLBACK_CONTEXT * CallbackContext + ); + +/** + Register an IO trap SMI child handler for a specified SMI. + This service will register a child for a given SMI source. + The caller will provide information about the IO trap characteristics via the context. + This includes base address, length, and type (read, write, read/write). + The service will allocate the IO range if the base address is 0, and the RegisterContext + Address field will be updated and returned to the caller. + The service will allocate system resources via GCD services for the requested IO trap range and type. + An error will be returned if insufficient resources are available to fulfill the request. + The service will not perform GCD allocation if the base address is non-zero. In this case, + the caller is responsible for the existence and allocation of the specific IO range. + An error may be returned if some or all of the requested resources conflict with an existing IO trap child handler. + It is not required that implementations will allow multiple children for a single IO trap SMI source. + Some implementations may support multiple children. + + @param[in] This Pointer to the EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL instance. + @param[in] DispatchFunction Pointer to the dispatch function to be invoked for this SMI source. + @param[in, out] RegisterContext Pointer to the dispatch function's context. + The caller fills this context in before calling the register function to indicate to the + register function the IO trap SMI source for which the dispatch function should be invoked. + This may not be NULL. + @param[out] DispatchHandle Handle of the dispatch function, for when interfacing with the parent SMM driver. + Type EFI_HANDLE is defined in InstallProtocolInterface() in the EFI 1.10 Specification. + This may not be NULL. + + @retval EFI_SUCCESS The dispatch function has been successfully registered. + @retval EFI_DEVICE_ERROR The driver was unable to complete due to hardware error. + @retval EFI_OUT_OF_RESOURCES Insufficient resources are available to fulfill + the IO trap range request. + @retval EFI_INVALID_PARAMETER RegisterContext is invalid. The input value is not within a valid range. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMM_IO_TRAP_DISPATCH_REGISTER) ( + IN EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL * This, + IN EFI_SMM_IO_TRAP_DISPATCH_CALLBACK DispatchFunction, + IN OUT EFI_SMM_IO_TRAP_DISPATCH_REGISTER_CONTEXT * RegisterContext, + OUT EFI_HANDLE * DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent SMM driver + + This service removes a previously installed child dispatch handler. + This does not guarantee that the system resources will be freed from the GCD. + + @param[in] This Pointer to the EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL instance. + @param[in] DispatchHandle Handle of the child service to remove. + Type EFI_HANDLE is defined in InstallProtocolInterface() in the EFI 1.10 Specification. + + @retval EFI_SUCCESS The dispatch function has been successfully + unregistered. + @retval EFI_INVALID_PARAMETER Handle is invalid. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SMM_IO_TRAP_DISPATCH_UNREGISTER) ( + IN EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL * This, + IN EFI_HANDLE * DispatchHandle + ); + +/// +/// Interface structure for the SMM IO trap specific SMI Dispatch Protocol +/// +/// This protocol provides the ability to install child handlers for IO trap SMI. +/// These handlers will be invoked to respond to specific IO trap SMI. IO trap SMI +/// would typically be generated on reads or writes to specific processor IO space +/// addresses or ranges. This protocol will typically abstract a limited hardware +/// resource, so callers should handle errors gracefully. +/// +struct _EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL { + EFI_SMM_IO_TRAP_DISPATCH_REGISTER Register; ///< Installs a child service to be dispatched when the requested IO trap SMI occurs. + EFI_SMM_IO_TRAP_DISPATCH_UNREGISTER UnRegister; ///< Removes a previously registered child service. +}; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/Spi/Spi.c b/ReferenceCode/Chipset/LynxPoint/Protocol/Spi/Spi.c new file mode 100644 index 0000000..2df15e8 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/Spi/Spi.c @@ -0,0 +1,48 @@ +/** @file + This file defines the EFI SPI Protocol which implements the + Intel(R) SPI Host Controller Compatibility Interface. + +@copyright + Copyright (c) 2004 - 2015 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ + +// +// Statements that include other files +// +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGlueDxe.h" +#endif +// +// Include the protocol header file +// +#include "Spi.h" + +// +// Protocol GUID definition +// +EFI_GUID gEfiSpiProtocolGuid = EFI_SPI_PROTOCOL_GUID; +EFI_GUID gEfiSmmSpiProtocolGuid = EFI_SMM_SPI_PROTOCOL_GUID; +EFI_GUID gEfiSpiDataProtocolGuid = EFI_SPI_DATA_PROTOCOL_GUID; + +// +// Protocol description +// +EFI_GUID_STRING(&gEfiSpiProtocolGuid, "SPI Protocol", "Intel(R) Serial Peripheral Interface Protocol"); +EFI_GUID_STRING(&gEfiSmmSpiProtocolGuid, "SMM SPI Protocol", "Intel(R) Serial Peripheral Interface Protocol"); +EFI_GUID_STRING(&gEfiSpiDataProtocolGuid, "SPI Data Protocol", "Intel(R) Serial Peripheral Data Interface Protocol"); diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/Spi/Spi.h b/ReferenceCode/Chipset/LynxPoint/Protocol/Spi/Spi.h new file mode 100644 index 0000000..d44332b --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/Spi/Spi.h @@ -0,0 +1,346 @@ +/** @file + This file defines the EFI SPI Protocol which implements the + Intel(R) PCH SPI Host Controller Compatibility Interface. + +@copyright + Copyright (c) 2006 - 2015 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _EFI_SPI_H_ +#define _EFI_SPI_H_ + +/// +/// Define the SPI protocol GUID +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define EFI_SPI_PROTOCOL_GUID \ + { \ + 0xf8b84ae6, 0x8465, 0x4f95, 0x9f, 0xb, 0xea, 0xaa, 0x37, 0xc6, 0x15, 0x5a \ + } +#define EFI_SMM_SPI_PROTOCOL_GUID \ + { \ + 0xbd75fe35, 0xfdce, 0x49d7, 0xa9, 0xdd, 0xb2, 0x6f, 0x1f, 0xc6, 0xb4, 0x37 \ + } +#define EFI_SPI_DATA_PROTOCOL_GUID \ + { \ + 0xd617e1a8, 0x207d, 0x4544, 0xb1, 0x2d, 0x94, 0xd0, 0x96, 0x60, 0xa2, 0xd1 \ + } +#else +#define EFI_SPI_PROTOCOL_GUID \ + { \ + 0xf8b84ae6, 0x8465, 0x4f95, \ + { \ + 0x9f, 0xb, 0xea, 0xaa, 0x37, 0xc6, 0x15, 0x5a \ + } \ + } +#define EFI_SMM_SPI_PROTOCOL_GUID \ + { \ + 0xbd75fe35, 0xfdce, 0x49d7, \ + { \ + 0xa9, 0xdd, 0xb2, 0x6f, 0x1f, 0xc6, 0xb4, 0x37 \ + } \ + } +#define EFI_SPI_DATA_PROTOCOL_GUID \ + { \ + 0xd617e1a8, 0x207d, 0x4544, \ + { \ + 0xb1, 0x2d, 0x94, 0xd0, 0x96, 0x60, 0xa2, 0xd1 \ + } \ + } +#endif + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiSpiProtocolGuid; +extern EFI_GUID gEfiSmmSpiProtocolGuid; +extern EFI_GUID gEfiSpiDataProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _EFI_SPI_PROTOCOL EFI_SPI_PROTOCOL; +typedef struct _EFI_SPI_DATA_PROTOCOL EFI_SPI_DATA_PROTOCOL; + +// +// SPI protocol data structures and definitions +// +/// +/// Number of Prefix Opcodes allowed on the SPI interface +/// +#define SPI_NUM_PREFIX_OPCODE 2 + +/// +/// Number of Opcodes in the Opcode Menu +/// +#define SPI_NUM_OPCODE 8 + +/// +/// Opcode Type +/// EnumSpiOpcodeCommand: Command without address +/// EnumSpiOpcodeRead: Read with address +/// EnumSpiOpcodeWrite: Write with address +/// +typedef enum { + EnumSpiOpcodeReadNoAddr, + EnumSpiOpcodeWriteNoAddr, + EnumSpiOpcodeRead, + EnumSpiOpcodeWrite, + EnumSpiOpcodeMax +} SPI_OPCODE_TYPE; + +typedef enum { + EnumSpiCycle20MHz, + EnumSpiCycle33MHz, + EnumSpiCycle66MHz, ///< not supported by PCH + EnumSpiCycle50MHz, + EnumSpiCycleMax +} SPI_CYCLE_FREQUENCY; + +typedef enum { + EnumSpiRegionAll, + EnumSpiRegionBios, + EnumSpiRegionMe, + EnumSpiRegionGbE, + EnumSpiRegionDescriptor, + EnumSpiRegionPlatformData, + EnumSpiRegionMax +} SPI_REGION_TYPE; + +/// +/// Hardware Sequencing required operations (as listed in PCH EDS "Hardware +/// Sequencing Commands and Opcode Requirements" +/// +typedef enum { + EnumSpiOperationWriteStatus, + EnumSpiOperationProgramData_1_Byte, + EnumSpiOperationProgramData_64_Byte, + EnumSpiOperationReadData, + EnumSpiOperationWriteDisable, + EnumSpiOperationReadStatus, + EnumSpiOperationWriteEnable, + EnumSpiOperationFastRead, + EnumSpiOperationEnableWriteStatus, + EnumSpiOperationErase_256_Byte, + EnumSpiOperationErase_4K_Byte, + EnumSpiOperationErase_8K_Byte, + EnumSpiOperationErase_64K_Byte, + EnumSpiOperationFullChipErase, + EnumSpiOperationJedecId, + EnumSpiOperationDualOutputFastRead, + EnumSpiOperationDiscoveryParameters, + EnumSpiOperationOther, + EnumSpiOperationMax +} SPI_OPERATION; + +/// +/// SPI Command Configuration +/// +typedef struct _SPI_COMMAND_CONFIG { + /// + /// The expected frequency to be used (value to be programmed to the SSFC Register) + /// + SPI_CYCLE_FREQUENCY Frequency; + /// + /// Which Hardware Sequencing required operation this opcode respoinds to. + /// The required operations are listed in EDS Table 5-55: "Hardware + /// Sequencing Commands and Opcode Requirements" + /// If the opcode does not corresponds to any operation listed, use + /// EnumSpiOperationOther, and provides TYPE and Code for it in + /// SpecialOpcodeEntry. + /// + SPI_OPERATION Operation; +} SPI_COMMAND_CONFIG; + +/// +/// Special Opcode entries +/// +typedef struct _SPI_SPECIAL_OPCODE_ENTRY { + /// + /// Opcode Menu Index whose Opcode Type/Menu Configuration Register need to be + /// overrided or programmed per "Type" and "Code". Filled this field with 0xFF + /// as the end tag of SpecialOpcodeEntry. + /// + UINT8 OpcodeIndex; + /// + /// Operation Type (value to be programmed to the OPTYPE register) + /// + SPI_OPCODE_TYPE Type; + /// + /// The opcode (value to be programmed to the OPMENU register) + /// + UINT8 Code; +} SPI_SPECIAL_OPCODE_ENTRY; + +/// +/// Initialization data table loaded to the SPI host controller +/// +/// Note: Most of time, the SPI flash parts with the same vendor would have the same +/// Prefix Opcode, Opcode menu, so you can provide one table for the SPI flash parts with +/// the same vendor. +/// +typedef struct _SPI_INIT_DATA { + /// + /// Prefix opcodes which are loaded into the SPI host controller + /// + UINT8 PrefixOpcode[SPI_NUM_PREFIX_OPCODE]; + /// + /// Determines Opcode Type, Menu and Frequency of the SPI commands + /// + SPI_COMMAND_CONFIG SpiCmdConfig[SPI_NUM_OPCODE]; + /// + /// Special Opcode entry for the special operations. + /// + SPI_SPECIAL_OPCODE_ENTRY *SpecialOpcodeEntry; + /// + /// The offset of the start of the BIOS image relative to the flash device. + /// Please note this is a Flash Linear Address, NOT a memory space address. + /// This value is platform specific and depends on the system flash map. + /// This value is only used on non Descriptor mode. + /// + UINTN BiosStartOffset; + /// + /// The the BIOS Image size in flash. This value is platform specific + /// and depends on the system flash map. Please note BIOS Image size may + /// be smaller than BIOS Region size (in Descriptor Mode) or the flash size + /// (in Non Descriptor Mode), and in this case, BIOS Image is supposed to be + /// placed at the top end of the BIOS Region (in Descriptor Mode) or the flash + /// (in Non Descriptor Mode) + /// + UINTN BiosSize; +} SPI_INIT_DATA; + +// +// Protocol member functions +// + +/** + JEDEC Read IDs from SPI flash part, this function will return 1-byte Vendor ID and 2-byte Device ID + + @param[in] This Pointer to the EFI_SPI_PROTOCOL instance. + @param[in] Address This value is to determine the command is sent to SPI Component 1 or 2 + @param[in, out] Buffer Pointer to caller-allocated buffer containing the data received or sent during the SPI cycle. + + @retval EFI_SUCCESS Read Jedec Id completed. + @retval EFI_DEVICE_ERROR Device error, operation failed. + @exception EFI_UNSUPPORTED This function is unsupported after SpiProtocolInit is called +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SPI_READ_ID) ( + IN EFI_SPI_PROTOCOL * This, + IN UINTN Address, + IN OUT UINT8 * Buffer + ); + +/** + Initializes the host controller to execute SPI commands. + + @param[in] This Pointer to the EFI_SPI_PROTOCOL instance. + @param[in] InitData Pointer to caller-allocated buffer containing the SPI + interface initialization table. + + @retval EFI_SUCCESS Opcode initialization on the SPI host controller completed. + @retval EFI_ACCESS_DENIED The SPI configuration interface is locked. + @retval EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device. + @retval EFI_DEVICE_ERROR Device error, operation failed. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SPI_INIT) ( + IN EFI_SPI_PROTOCOL * This, + IN SPI_INIT_DATA * InitData + ); + +/** + Execute SPI commands from the host controller. + + @param[in] This Pointer to the EFI_SPI_PROTOCOL instance. + @param[in] OpcodeIndex Index of the command in the OpCode Menu. + @param[in] PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence. + @param[in] DataCycle TRUE if the SPI cycle contains data + @param[in] Atomic TRUE if the SPI cycle is atomic and interleave cycles are not allowed. + @param[in] ShiftOut If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in. + @param[in] Address In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform + Region, this value specifies the offset from the Region Base; for BIOS Region, + this value specifies the offset from the start of the BIOS Image. In Non + Descriptor Mode, this value specifies the offset from the start of the BIOS Image. + Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor + Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is + supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or + the flash (in Non Descriptor Mode) + @param[in] DataByteCount Number of bytes in the data portion of the SPI cycle. + @param[in, out] Buffer Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle. + @param[in] SpiRegionType SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe, + EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in + Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode + and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative + to base of the 1st flash device (i.e., it is a Flash Linear Address). + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @exception EFI_UNSUPPORTED Command not supported. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_SPI_EXECUTE) ( + IN EFI_SPI_PROTOCOL * This, + IN UINT8 OpcodeIndex, + IN UINT8 PrefixOpcodeIndex, + IN BOOLEAN DataCycle, + IN BOOLEAN Atomic, + IN BOOLEAN ShiftOut, + IN UINTN Address, + IN UINT32 DataByteCount, + IN OUT UINT8 *Buffer, + IN SPI_REGION_TYPE SpiRegionType + ); + +/// +/// EFI SPI Protocol definition +/// +/// These protocols/PPI allows a platform module to perform SPI operations through the +/// Intel PCH SPI Host Controller Interface. +/// +struct _EFI_SPI_PROTOCOL { + EFI_SPI_READ_ID ReadId; ///< JEDEC Read IDs from SPI flash part, this function will return 1-byte Vendor ID and 2-byte Device ID. + EFI_SPI_INIT Init; ///< Initialize the host controller to execute SPI commands. + EFI_SPI_EXECUTE Execute; ///< Execute SPI commands from the host controller. +}; + +/// +/// This protocol provides data about the Flash device to non-SPI modules in order to +/// allow other entities to determine if their data is coming directly from Flash or +/// if it is coming from other areas of memory. +/// +struct _EFI_SPI_DATA_PROTOCOL { + /// + /// The offset of the start of the BIOS image within memory space address. + /// + UINTN BiosStartMemoryAddress; + /// + /// The the BIOS Image size in flash. This value is platform specific + /// and depends on the system flash map. Please note BIOS Image size may + /// be smaller than BIOS Region size (in Descriptor Mode) or the flash size + /// (in Non Descriptor Mode), and in this case, BIOS Image will be placed + /// at the top end of the BIOS Region (in Descriptor Mode) or the flash + /// (in Non Descriptor Mode) + /// + UINTN BiosSize; +}; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/Wdt/Wdt.c b/ReferenceCode/Chipset/LynxPoint/Protocol/Wdt/Wdt.c new file mode 100644 index 0000000..03ec452 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/Wdt/Wdt.c @@ -0,0 +1,34 @@ +/** @file + Watchdog Timer protocol + +@copyright + Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) + +#include "EdkIIGlueDxe.h" +#endif + +#include "Wdt.h" + +// +// Protocol GUID definition +// +EFI_GUID gWdtProtocolGuid = WDT_PROTOCOL_GUID; + +// +// Protocol description +// +EFI_GUID_STRING(&gWdtProtocolGuid, "WDT Protocol", "Watchdog Timer Protocol"); diff --git a/ReferenceCode/Chipset/LynxPoint/Protocol/Wdt/Wdt.h b/ReferenceCode/Chipset/LynxPoint/Protocol/Wdt/Wdt.h new file mode 100644 index 0000000..322aa2f --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Protocol/Wdt/Wdt.h @@ -0,0 +1,157 @@ +/** @file + Watchdog Timer protocol + +@copyright + Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _DXE_WDT_H_ +#define _DXE_WDT_H_ + +/// +/// GUID for the WDT Protocol +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define WDT_PROTOCOL_GUID \ + { \ + 0xB42B8D12, 0x2ACB, 0x499a, 0xA9, 0x20, 0xDD, 0x5B, 0xE6, 0xCF, 0x09, 0xB1 \ + } + +#else + +#define WDT_PROTOCOL_GUID \ + { \ + 0xB42B8D12, 0x2ACB, 0x499a, \ + { \ + 0xA9, 0x20, 0xDD, 0x5B, 0xE6, 0xCF, 0x09, 0xB1 \ + } \ + } + +#endif +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gWdtProtocolGuid; +// +// Forward reference for ANSI C compatibility +// +typedef struct _WDT_PROTOCOL WDT_PROTOCOL; + +/** + Reloads WDT with new timeout value and starts it. Also sets Unexpected Reset bit, which + causes the next reset to be treated as watchdog expiration - unless AllowKnownReset() + function was called too. + + @param[in] TimeoutValue Time in seconds before WDT times out. Supported range = 1 - 1024. + + @retval EFI_SUCCESS if everything's OK + @retval EFI_INVALID_PARAMETER if TimeoutValue parameter is wrong +**/ +typedef +EFI_STATUS +(EFIAPI *WDT_RELOAD_AND_START) ( + UINT32 TimeoutValue + ); + +/** + Returns WDT failure status. + + @param[in] None + + @retval V_PCH_OC_WDT_CTL_STATUS_FAILURE If there was WDT expiration or unexpected reset + @retval V_PCH_OC_WDT_CTL_STATUS_OK Otherwise +**/ +typedef +UINT8 +(EFIAPI *WDT_CHECK_STATUS) ( + VOID + ); + +/** + Returns information if WDT coverage for the duration of BIOS execution + was requested by an OS application. + + @param[in] None + + @retval TRUE if WDT was requested + @retval FALSE if WDT was not requested +**/ +typedef +UINT8 +(EFIAPI *IS_WDT_REQUIRED) ( + VOID + ); + +/** + Returns WDT enabled/disabled status. + + @param[in] None + + @retval TRUE if WDT is enabled + @retval FALSE if WDT is disabled +**/ +typedef +UINT8 +(EFIAPI *IS_WDT_ENABLED) ( + VOID + ); + +/** + Disables WDT timer. + + @param[in] None + + @retval None +**/ +typedef +VOID +(EFIAPI *WDT_DISABLE) ( + VOID + ); + +/** + Normally, each reboot performed while watchdog runs is considered a failure. + This function allows platform to perform expected reboots with WDT running, + without being interpreted as failures. + In DXE phase, it is enough to call this function any time before reset. + In PEI phase, between calling this function and performing reset, ReloadAndStart() + must not be called. + + @param[in] None + + @retval None +**/ +typedef +VOID +(EFIAPI *WDT_ALLOW_KNOWN_RESET) ( + VOID + ); + +/// +/// These protocols and PPI allow a platform module to perform watch dog timer operations +/// through the Intel PCH LPC Host Controller Interface. The WDT protocol and WDT PPI +/// implement the Intel (R) Watch Dog timer for DXE, and PEI environments, respectively. +/// WDT_PROTOCOL referenced hereafter represents both WDT_PROTOCOL and WDT_PPI, as they +/// share the identical data structure. +/// +struct _WDT_PROTOCOL { + WDT_RELOAD_AND_START ReloadAndStart; ///< Reloads WDT with new timeout value and starts it. + WDT_CHECK_STATUS CheckStatus; ///< Returns WDT failure status. + WDT_DISABLE Disable; ///< Disables WDT timer. + WDT_ALLOW_KNOWN_RESET AllowKnownReset; ///< Perform expected reboots with WDT running, without being interpreted as failures. + IS_WDT_REQUIRED IsWdtRequired; ///< Returns information if WDT coverage for the duration of BIOS execution was requested by an OS application. + IS_WDT_ENABLED IsWdtEnabled; ///< Returns WDT enabled/disabled status. +}; + +#endif |