init. 1AQQW051HEADmaster

7 files changed, 648 insertions, 0 deletions

diff --git a/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpi.c b/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpi.c
new file mode 100644
index 0000000..9c041ad
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpi.c
@@ -0,0 +1,244 @@
+/** @file
+  PCH SPI SMM Driver implements the SPI Host Controller Compatibility Interface.
+
+@copyright
+  Copyright (c) 2008 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#include "PchSpi.h"
+
+//
+// Global variables
+//
+EFI_SMM_BASE_PROTOCOL *mSmmBase;
+EFI_SMM_SYSTEM_TABLE  *mSmst;
+SPI_INSTANCE          *mSpiInstance;
+
+/**
+  Entry point for the SPI host controller driver.
+
+  @param[in] ImageHandle          Image handle of this driver.
+  @param[in] SystemTable          Global system service table.
+
+  @retval EFI_SUCCESS             Initialization complete.
+  @exception EFI_UNSUPPORTED      The chipset is unsupported by this driver.
+  @retval EFI_OUT_OF_RESOURCES    Do not have enough resources to initialize the driver.
+  @retval EFI_DEVICE_ERROR        Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+InstallPchSpi (
+  IN EFI_HANDLE            ImageHandle,
+  IN EFI_SYSTEM_TABLE      *SystemTable
+  )
+{
+  EFI_STATUS  Status;
+
+  ///
+  /// Locate SMM Base Protocol
+  ///
+  Status = gBS->LocateProtocol (&gEfiSmmBaseProtocolGuid, NULL, (VOID **) &mSmmBase);
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Initialize our module variables
+  ///
+  Status = mSmmBase->GetSmstLocation (mSmmBase, &mSmst);
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Allocate pool for SPI protocol instance
+  ///
+  Status = mSmst->SmmAllocatePool (
+                    EfiRuntimeServicesData, /// MemoryType don't care
+                    sizeof (SPI_INSTANCE),
+                    (VOID **) &mSpiInstance
+                    );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  if (mSpiInstance == NULL) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  ZeroMem ((VOID *) mSpiInstance, sizeof (SPI_INSTANCE));
+  ///
+  /// Initialize the SPI protocol instance
+  ///
+  Status = SpiProtocolConstructor (mSpiInstance);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+  ///
+  /// Install the SMM EFI_SPI_PROTOCOL interface
+  ///
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &(mSpiInstance->Handle),
+                  &gEfiSmmSpiProtocolGuid,
+                  &(mSpiInstance->SpiProtocol),
+                  NULL
+                  );
+  if (EFI_ERROR (Status)) {
+    mSmst->SmmFreePool (mSpiInstance);
+    return EFI_DEVICE_ERROR;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  This function is a a hook for Spi Smm phase specific initialization
+
+  @param[in] None
+
+  @retval None
+**/
+VOID
+EFIAPI
+SpiPhaseInit (
+  VOID
+  )
+{
+  UINTN               Index;
+  static CONST UINT32 SpiRegister[] = {
+    R_PCH_SPI_SSFS,
+    R_PCH_SPI_PREOP,
+    R_PCH_SPI_OPMENU,
+    R_PCH_SPI_OPMENU + 4,
+    R_PCH_SPI_VSCC0,
+    R_PCH_SPI_VSCC1
+  };
+
+  ///
+  /// Save SPI Registers for S3 resume usage
+  ///
+  for (Index = 0; Index < sizeof (SpiRegister) / sizeof (UINT32); Index++) {
+    SCRIPT_MEM_WRITE (
+      EFI_ACPI_S3_RESUME_SCRIPT_TABLE,
+      EfiBootScriptWidthUint32,
+      (UINTN) (mSpiInstance->PchRootComplexBar + SpiRegister[Index]),
+      1,
+      (VOID *) (UINTN) (mSpiInstance->PchRootComplexBar + SpiRegister[Index])
+      );
+  }
+}
+
+/**
+  This function is a hook for Spi to disable BIOS Write Protect
+
+  @param[in] None
+
+  @retval None
+**/
+VOID
+EFIAPI
+DisableBiosWriteProtect (
+  VOID
+  )
+{
+  UINT8     Data8;
+  UINT32    Data32;
+
+  ///
+  /// Set BIOSWE bit (B0:D31:F0 Offset DCh [0]) = 1b
+  ///
+  PciOr8 (
+    PCI_LIB_ADDRESS (DEFAULT_PCI_BUS_NUMBER_PCH,
+    PCI_DEVICE_NUMBER_PCH_LPC,
+    0,
+    R_PCH_LPC_BIOS_CNTL),
+    (UINT8) (B_PCH_LPC_BIOS_CNTL_BIOSWE)
+    );
+  ///
+  /// PCH BIOS Spec Rev 0.5.0, Section 3.7 BIOS Region SMM Protection Enabling
+  /// If the following steps are implemented:
+  ///  - Set the SMM_BWP bit (B0:D31:F0 Offset DCh [5]) = 1b
+  ///  - Follow the 1st recommendation in section 3.6
+  /// the BIOS Region can only be updated by following the steps bellow:
+  ///  - Once all threads enter SMM
+  ///  - Read memory location FED30880h OR with 00000001h, place the result in EAX,
+  ///    and write data to lower 32 bits of MSR 1FEh (sample code available)
+  ///  - Set BIOSWE bit (B0:D31:F0 Offset DCh [0]) = 1b
+  ///  - Modify BIOS Region
+  ///  - Clear BIOSWE bit (B0:D31:F0 Offset DCh [0]) = 0b
+  ///  - Read memory location FED30880h AND with FFFFFFFEh, place the result in EAX,
+  ///    and write data to lower 32 bits of MSR 1FEh (sample code available)
+  ///
+  Data8 = PciRead8 (
+            PCI_LIB_ADDRESS (DEFAULT_PCI_BUS_NUMBER_PCH,
+            PCI_DEVICE_NUMBER_PCH_LPC,
+            0,
+            R_PCH_LPC_BIOS_CNTL)
+            );
+  ///
+  /// Check if SMM_BWP bit is set
+  ///
+  if ((Data8 & B_PCH_LPC_BIOS_CNTL_SMM_BWP) == B_PCH_LPC_BIOS_CNTL_SMM_BWP) {
+    ///
+    /// Read memory location FED30880h OR with 00000001h, place the result in EAX,
+    /// and write data to lower 32 bits of MSR 1FEh (sample code available)
+    ///
+    Data32 = MmioRead32 ((UINTN) (0xFED30880)) | (UINT32) (BIT0);
+    AsmWriteMsr32 (0x1FE, Data32);
+  }
+}
+
+/**
+  This function is a hook for Spi to enable BIOS Write Protect
+
+  @param[in] None
+
+  @retval None
+**/
+VOID
+EFIAPI
+EnableBiosWriteProtect (
+  VOID
+  )
+{
+  UINT8     Data8;
+  UINT32    Data32;
+
+  ///
+  /// Clear BIOSWE bit (B0:D31:F0 Offset DCh [0]) = 0b
+  ///
+  PciAnd8 (
+    PCI_LIB_ADDRESS (DEFAULT_PCI_BUS_NUMBER_PCH,
+    PCI_DEVICE_NUMBER_PCH_LPC,
+    0,
+    R_PCH_LPC_BIOS_CNTL),
+    (UINT8) (~B_PCH_LPC_BIOS_CNTL_BIOSWE)
+    );
+
+  Data8 = PciRead8 (
+            PCI_LIB_ADDRESS (DEFAULT_PCI_BUS_NUMBER_PCH,
+            PCI_DEVICE_NUMBER_PCH_LPC,
+            0,
+            R_PCH_LPC_BIOS_CNTL)
+            );
+  ///
+  /// Check if SMM_BWP bit is set
+  ///
+  if ((Data8 & B_PCH_LPC_BIOS_CNTL_SMM_BWP) == B_PCH_LPC_BIOS_CNTL_SMM_BWP) {
+    ///
+    /// Read memory location FED30880h AND with FFFFFFFEh, place the result in EAX,
+    /// and write data to lower 32 bits of MSR 1FEh (sample code available)
+    ///
+    Data32 = MmioRead32 ((UINTN) (0xFED30880)) & (UINT32) (~BIT0);
+    AsmWriteMsr32 (0x1FE, Data32);
+  }
+}
diff --git a/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpi.dxs b/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpi.dxs
new file mode 100644
index 0000000..0f2e9b0
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpi.dxs
@@ -0,0 +1,45 @@
+/** @file
+  Dependency expression source file.
+
+@copyright
+  Copyright (c)  2004 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+
+**/
+
+//
+// Common for R8 and R9 codebase
+//
+#include "AutoGen.h"
+#include "DxeDepex.h"
+
+//
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase;
+// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase.
+//
+#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB)
+#include "EfiDepex.h"
+
+#include EFI_PROTOCOL_DEFINITION  (SmmBase)
+#include EFI_PROTOCOL_DEFINITION  (BootScriptSave)
+#include EFI_PROTOCOL_DEFINITION  (Pfat)
+#endif
+
+DEPENDENCY_START
+#ifdef EFI_S3_RESUME
+  EFI_BOOT_SCRIPT_SAVE_PROTOCOL_GUID AND
+#endif
+  EFI_SMM_BASE_PROTOCOL_GUID
+DEPENDENCY_END
diff --git a/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpi.h b/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpi.h
new file mode 100644
index 0000000..1f9244e
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpi.h
@@ -0,0 +1,76 @@
+/** @file
+  Header file for the PCH SPI SMM Driver.
+
+@copyright
+  Copyright (c) 2004 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _PCH_SPI_H_
+#define _PCH_SPI_H_
+
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGlueDxe.h"
+#include EFI_PROTOCOL_PRODUCER (Spi)
+#include "SpiCommon.h"
+#include "EfiScriptLib.h"
+
+//
+// Driver Dependency Protocols
+//
+#include EFI_PROTOCOL_DEPENDENCY (SmmBase)
+#include EFI_PROTOCOL_CONSUMER (BootScriptSave)
+#endif
+
+/**
+  This function is a a hook for Spi Smm phase specific initialization
+
+  @param[in] None
+
+  @retval None
+**/
+VOID
+EFIAPI
+SpiPhaseInit (
+  VOID
+  );
+
+/**
+  This function is a hook for Spi to disable BIOS Write Protect
+
+  @param[in] None
+
+  @retval None
+**/
+VOID
+EFIAPI
+DisableBiosWriteProtect (
+  VOID
+  );
+
+/**
+  This function is a hook for Spi to enable BIOS Write Protect
+
+  @param[in] None
+
+  @retval None
+**/
+VOID
+EFIAPI
+EnableBiosWriteProtect (
+  VOID
+  );
+
+#endif
diff --git a/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpiSmm.cif b/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpiSmm.cif
new file mode 100644
index 0000000..8ae77f5
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpiSmm.cif
@@ -0,0 +1,13 @@
+<component>
+	name = "PchSpiSmm"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Chipset\LynxPoint\Spi\Smm"
+	RefName = "PchSpiSmm"
+[files]
+"PchSpiSmm.sdl"	
+"PchSpiSmm.mak"	
+"PchSpi.c"	
+"PchSpi.h"	
+"PchSpi.dxs"	
+"PchSpiSmm.inf"	
+<endComponent>
diff --git a/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpiSmm.inf b/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpiSmm.inf
new file mode 100644
index 0000000..5fe34a2
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpiSmm.inf
@@ -0,0 +1,92 @@
+## @file
+#  Component description file for the SPI SMM driver.
+#
+#@copyright
+#  Copyright (c)  2008 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+[defines]
+BASE_NAME            = PchSpiSmm
+FILE_GUID            = 27F4917B-A707-4aad-9676-26DF168CBF0D
+COMPONENT_TYPE       = BS_DRIVER
+
+[sources.common]
+  PchSpi.h
+  PchSpi.c
+  ../Common/SpiCommon.c
+
+#
+# Edk II Glue Driver Entry Point
+#
+  EdkIIGlueSmmDriverEntryPoint.c
+
+
+[includes.common]
+  .
+  ../Common
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include/Library
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)
+#
+# EDK II Glue Library utilizes some standard headers from EDK
+#
+  $(EFI_SOURCE)
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Core/Dxe
+  $(EDK_SOURCE)/Foundation/Include/Pei
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+
+[libraries.common]
+  EdkIIGlueBaseLib
+  EdkIIGlueBaseIoLibIntrinsic
+  EdkIIGlueBaseMemoryLib
+  EdkIIGlueSmmRuntimeDxeReportStatusCodeLib
+  EdkIIGlueDxeDebugLibReportStatusCode
+  EdkIIGlueDxeMemoryAllocationLib
+  EdkIIGlueUefiBootServicesTableLib
+  EdkIIGlueUefiRuntimeServicesTableLib
+  EdkIIGlueUefiDevicePathLib
+  EdkIIGlueBasePciLibPciExpress
+  EdkFrameworkProtocolLib
+  EdkProtocolLib
+  $(PROJECT_PCH_FAMILY)ProtocolLib
+  PchPlatformLib
+  EfiScriptLib
+
+[nmake.common]
+  IMAGE_ENTRY_POINT = _ModuleEntryPoint
+  DPX_SOURCE        = PchSpi.dxs
+#
+# Module Entry Point
+#
+  C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=InstallPchSpi
+  C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+                       -D __EDKII_GLUE_BASE_MEMORY_LIB__ \
+                       -D __EDKII_GLUE_DXE_MEMORY_ALLOCATION_LIB__ \
+                       -D __EDKII_GLUE_SMM_RUNTIME_DXE_REPORT_STATUS_CODE_LIB__ \
+                       -D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \
+                       -D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \
+                       -D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \
+                       -D __EDKII_GLUE_UEFI_DEVICE_PATH_LIB__ \
+                       -D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__
diff --git a/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpiSmm.mak b/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpiSmm.mak
new file mode 100644
index 0000000..9b15d4d
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpiSmm.mak
@@ -0,0 +1,112 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/PchSpiSmm/PchSpiSmm.mak 3     9/26/12 3:40a Victortu $
+#
+# $Revision: 3 $
+#
+# $Date: 9/26/12 3:40a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/PchSpiSmm/PchSpiSmm.mak $
+# 
+# 3     9/26/12 3:40a Victortu
+# Lynx Point PCH Chipset Framework Reference Code Beta 0.7.0
+# 
+# 2     2/24/12 2:26a Victortu
+# Updated to support 4.6.5.3_IntelEDK_1117_Patch7_00.
+# 
+# 1     2/08/12 9:24a Yurenlai
+# Intel Lynx Point/SB eChipset initially releases.
+#
+#*************************************************************************
+
+#---------------------------------------------------------------------------
+#   Create PchSpi SMM Driver
+#---------------------------------------------------------------------------
+EDK : PchSpiSmm
+PchSpiSmm : $(BUILD_DIR)\PchSpiSmm.mak PchSpiSmmBin
+
+
+$(BUILD_DIR)\PchSpiSmm.mak : $(PchSpiSmm_DIR)\$(@B).cif $(PchSpiSmm_DIR)\$(@B).mak $(BUILD_RULES)
+  $(CIF2MAK) $(PchSpiSmm_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+PchSpiSmm_INCLUDES=\
+      $(INTEL_PCH_INCLUDES)\
+      $(EdkIIGlueLib_INCLUDES)\
+      $(PCH_SPI_INCLUDES)\
+      $(PROJECT_CPU_INCLUDES)\
+
+PchSpiSmm_DEFINES = $(MY_DEFINES)\
+      /D"__EDKII_GLUE_MODULE_ENTRY_POINT__=InstallPchSpi"\
+      /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+      /D __EDKII_GLUE_BASE_MEMORY_LIB__ \
+      /D __EDKII_GLUE_DXE_MEMORY_ALLOCATION_LIB__ \
+      /D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \
+      /D __EDKII_GLUE_SMM_RUNTIME_DXE_REPORT_STATUS_CODE_LIB__ \
+      /D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \
+      /D __EDKII_GLUE_UEFI_DEVICE_PATH_LIB__ \
+      /D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ \
+      /D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \
+
+PchSpiSmm_LIB_LINKS =\
+!IF "$(x64_BUILD)"=="1"
+            $(EdkIIGlueBaseLibX64_LIB)\
+!ELSE
+            $(EdkIIGlueBaseLibIA32_LIB)\
+!ENDIF
+            $(EdkIIGlueBaseLib_LIB)\
+            $(EdkIIGlueBaseIoLibIntrinsic_LIB)\
+            $(EdkIIGlueBaseMemoryLib_LIB)\
+            $(EdkIIGlueDxeDebugLibReportStatusCode_LIB)\
+            $(EdkIIGlueSmmRuntimeDxeReportStatusCodeLib_LIB)\
+            $(EdkIIGlueDxeMemoryAllocationLib_LIB)\
+            $(EdkIIGlueUefiBootServicesTableLib_LIB)\
+            $(EdkIIGlueUefiDevicePathLib_LIB)\
+            $(EdkIIGlueBasePciLibPciExpress_LIB)\
+            $(EDKFRAMEWORKPROTOCOLLIB)\
+            $(EDKPROTOCOLLIB)\
+            $(INTEL_PCH_PROTOCOL_LIB)\
+            $(PchPlatformSmmLib_LIB)\
+            $(PchSpiCommonSmmLib_LIB)\
+            $(EFISCRIPTLIB)\
+            $(EdkIIGlueUefiRuntimeServicesTableLib_LIB)\
+
+PchSpiSmmBin: $(PchSpiSmm_LIB_LINKS)  
+            $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\
+            /f $(BUILD_DIR)\PchSpiSmm.mak all \
+            "MY_INCLUDES=$(PchSpiSmm_INCLUDES)"\
+            "MY_DEFINES=$(PchSpiSmm_DEFINES)"\
+            GUID=27F4917B-A707-4aad-9676-26DF168CBF0D\
+            ENTRY_POINT=_ModuleEntryPoint \
+            TYPE=BS_DRIVER\
+            EDKIIModule=SMMDRIVER\
+            DEPEX1=$(PchSpiSmm_DIR)\PchSpi.dxs\
+            DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\
+            COMPRESS=1
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
diff --git a/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpiSmm.sdl b/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpiSmm.sdl
new file mode 100644
index 0000000..5310706
--- /dev/null
+++ b/ReferenceCode/Chipset/LynxPoint/Spi/Smm/PchSpiSmm.sdl
@@ -0,0 +1,66 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/PchSpiSmm/PchSpiSmm.sdl 1     2/08/12 9:24a Yurenlai $
+#
+# $Revision: 1 $
+#
+# $Date: 2/08/12 9:24a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/PchSpiSmm/PchSpiSmm.sdl $
+# 
+# 1     2/08/12 9:24a Yurenlai
+# Intel Lynx Point/SB eChipset initially releases.
+#
+#*************************************************************************
+TOKEN
+        Name  = "PchSpiSmm_SUPPORT"
+        Value  = "1"
+        Help  = "Main switch to enable PchSpi SMM support in Project"
+        TokenType = Boolean
+        TargetEQU = Yes
+        TargetMAK = Yes
+        Master = Yes
+End
+
+PATH
+        Name  = "PchSpiSmm_DIR"
+End
+
+MODULE
+        File  = "PchSpiSmm.mak"
+        Help  = "Includes PchSpi to Project"
+End
+
+ELINK
+        Name  = "$(BUILD_DIR)\PchSpiSmm.ffs"
+        Parent  = "FV_MAIN"
+        InvokeOrder = AfterParent
+End
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************