init. 1AQQW051HEADmaster

21 files changed, 2201 insertions, 0 deletions

diff --git a/ReferenceCode/Haswell/Protocol/CpuInfo/CpuInfo.c b/ReferenceCode/Haswell/Protocol/CpuInfo/CpuInfo.c
new file mode 100644
index 0000000..01f84c5
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/CpuInfo/CpuInfo.c
@@ -0,0 +1,25 @@
+/** @file
+  Protocol used for CPU driver to provide the CPU information.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#include "Tiano.h"
+#include EFI_PROTOCOL_DEFINITION (CpuInfo)
+
+EFI_GUID gDxeCpuInfoProtocolGuid = DXE_CPU_INFO_PROTOCOL_GUID;
+
+EFI_GUID_STRING(&gDxeCpuInfoProtocolGuid, "CPU Information", "CPU information from CPU Drivers");
diff --git a/ReferenceCode/Haswell/Protocol/CpuInfo/CpuInfo.h b/ReferenceCode/Haswell/Protocol/CpuInfo/CpuInfo.h
new file mode 100644
index 0000000..394386f
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/CpuInfo/CpuInfo.h
@@ -0,0 +1,79 @@
+/** @file
+  Protocol used to report CPU information
+
+@copyright
+  Copyright (c) 1999 - 2014 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _CPU_INFO_H_
+#define _CPU_INFO_H_
+
+EFI_FORWARD_DECLARATION (DXE_CPU_INFO_PROTOCOL_GUID);
+#define DXE_CPU_INFO_PROTOCOL_GUID \
+  { \
+    0xe223cf65, 0xf6ce, 0x4122, 0xb3, 0xaf, 0x4b, 0xd1, 0x8a, 0xff, 0x40, 0xa1 \
+  }
+
+///
+/// Protocol revision number
+/// Any backwards compatible changes to this protocol will result in an update in the revision number
+/// Major changes will require publication of a new protocol
+///
+#define DXE_CPU_INFO_REVISION_1 1
+
+///
+/// RCVersion[7:0] is the release number.
+/// For example:
+/// Version 0.7.1    should be 00 07 01 00 (0x00070100)
+///
+#define CPU_RC_VERSION  0x01090000
+
+extern EFI_GUID gDxeCpuInfoProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _DXE_CPU_INFO_PROTOCOL DXE_CPU_INFO_PROTOCOL;
+
+//
+// CPU Common Feature Definition
+//
+
+///
+/// The processor Command Feature Definition is a super set and abstracts from hardware.
+///
+#define TXT_SUPPORT   1
+#define VMX_SUPPORT   (1 << 1)
+#define XD_SUPPORT    (1 << 2)
+#define DCA_SUPPORT   (1 << 3)
+#define XAPIC_SUPPORT (1 << 4)
+#define AES_SUPPORT   (1 << 5)
+#define HT_SUPPORT    (1 << 6)
+#define DEBUG_SUPPORT (1 << 7)
+#define DEBUG_LOCK_SUPPORT (1 << 8)
+
+///
+/// Interface structure for the CPU Info Protocol
+///
+struct _DXE_CPU_INFO_PROTOCOL {
+  UINT8  Revision;          ///< Revision for the protocol structure.
+  UINT32 RcVersion;         ///< Processor Features information.
+  //
+  // Bit definition for functionality enable/disable
+  //
+  UINT64 CpuCommonFeatures; ///< CPU Supported Feature. Output from CPU code.
+};
+
+#endif
diff --git a/ReferenceCode/Haswell/Protocol/CpuPlatformPolicy/CpuPlatformPolicy.c b/ReferenceCode/Haswell/Protocol/CpuPlatformPolicy/CpuPlatformPolicy.c
new file mode 100644
index 0000000..906c2e5
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/CpuPlatformPolicy/CpuPlatformPolicy.c
@@ -0,0 +1,26 @@
+/** @file
+  Protocol used for specifying platform related CPU information and policy setting.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#include "Tiano.h"
+#include EFI_PROTOCOL_DEFINITION (CpuPlatformPolicy)
+
+EFI_GUID gDxeCpuPlatformPolicyProtocolGuid = DXE_CPU_PLATFORM_POLICY_PROTOCOL_GUID;
+
+EFI_GUID_STRING
+        (&gDxeCpuPlatformPolicyProtocolGuid, "CPU Platform Policy", "Platform related CPU information and policy settings");
diff --git a/ReferenceCode/Haswell/Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h b/ReferenceCode/Haswell/Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
new file mode 100644
index 0000000..37fe5a1
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h
@@ -0,0 +1,329 @@
+/** @file
+  Protocol used for specifying platform related CPU information and policy setting.
+
+@copyright
+  Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _CPU_PLATFORM_POLICY_H_
+#define _CPU_PLATFORM_POLICY_H_
+
+#include "CpuPmConfig.h"
+
+#include EFI_PROTOCOL_DEFINITION (MpService)
+#include EFI_GUID_DEFINITION (DataHubRecords)
+
+#if (EFI_SPECIFICATION_VERSION >= 0x2000A)
+#include EFI_PROTOCOL_DEFINITION (HiiDatabase)
+#else
+#include EFI_PROTOCOL_DEFINITION (Hii)
+#endif
+
+EFI_FORWARD_DECLARATION (DXE_CPU_PLATFORM_POLICY_PROTOCOL_GUID);
+#define DXE_CPU_PLATFORM_POLICY_PROTOCOL_GUID \
+  { \
+    0x1279e288, 0x24cd, 0x47e9, 0x96, 0xba, 0xd7, 0xa3, 0x8c, 0x17, 0xbd, 0x64 \
+  }
+
+///
+/// Protocol revision number
+/// Any backwards compatible changes to this protocol will result in an update in the revision number
+/// Major changes will require publication of a new protocol
+///
+
+///
+/// Revision 1: Initial version
+///
+#define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_1 1
+///
+/// Revision 2: Added CPU_CONFIG.DebugInterfaceEnable
+///             Added CPU_CONFIG.DebugInterfaceLockEnable
+///
+#define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_2 2
+///
+/// Revision 3: Added CPU_CONFIG.ApIdleManner
+///             Added CPU_CONFIG.ApHandoffManner
+///
+#define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_3 3
+
+///
+/// Revision 4: Added POWER_MGMT_CONFIG.THERM_FUNCTION_ENABLES.Pl1ThermalControl
+///
+#define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_4 4
+///
+/// Revision 5: Added POWER_MGMT_CONFIG.PPM_TURBO_SETTINGS.PowerLimit3
+///                   POWER_MGMT_CONFIG.PPM_TURBO_SETTINGS.PowerLimit3Time
+///                   POWER_MGMT_CONFIG.PPM_TURBO_SETTINGS.PowerLimit3DutyCycle
+///                   POWER_MGMT_CONFIG.PPM_TURBO_SETTINGS.PowerLimit3Lock
+///
+#define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_5 5
+
+///
+/// Revision 6: Added POWER_MGMT_CONFIG.CustomPowerUnit .Support for user to configuration custom Power Limts in  milli watts
+/// Default Power Unit for follwing Items changes to MilliWatts
+/// POWER_MGMT_CONFIG.PPM_TURBO_SETTINGS
+///                 PowerLimit1
+///                 PowerLimit2
+///                 PowerLimit3
+/// POWER_MGMT_CONFIG.PPM_CUSTOM_CTDP
+///                 CustomPowerLimit1
+///                 CustomPowerLimit2
+///
+///
+
+#define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_6 6
+
+///
+/// Revision 7:  Added POWER_MGMT_CONFIG.THERM_FUNCTION_ENABLES.Pl1ThermalControlFloor. Changed definition of
+/// POWER_MGMT_CONFIG.THERM_FUNCTION_ENABLES.Pl1ThermalControl from 1 (enable) to 1 (enable/manual)
+/// POWER_MGMT_CONFIG.THERM_FUNCTION_ENABLES.Pl1ThermalControlFloor
+/// 
+
+#define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_7 7
+
+
+extern EFI_GUID gDxeCpuPlatformPolicyProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _DXE_CPU_PLATFORM_POLICY_PROTOCOL DXE_CPU_PLATFORM_POLICY_PROTOCOL;
+
+//
+// Prototypes for the Platform CPU Protocol
+//
+
+///
+/// This function is for platform code to provide Microcode location since different BIOS has different flash layout.
+/// Platform code need to provide a function for CPU code to call to get the Microcode location in flash or memory.
+///
+typedef
+EFI_STATUS
+(EFIAPI *PLATFORM_CPU_RETRIEVE_MICROCODE)(
+  IN DXE_CPU_PLATFORM_POLICY_PROTOCOL *This,
+  OUT UINT8                           **MicrocodeData
+  );
+
+typedef struct {
+  UINT32 Package;
+  UINT32 Die;
+  UINT32 Core;
+  UINT32 Thread;
+} CPU_PHYSICAL_LOCATION;
+
+///
+/// The platform category, Server, Desktop and Mobile are defined.
+///
+typedef enum {
+  CpuPlatformUnknown= 0,
+  CpuPlatformDesktop,
+  CpuPlatformMobile,
+  CpuPlatformServer,
+  CpuPlatformMax
+} CPU_PLATFORM_CATEGORY;
+
+///
+/// The reason for changing the state of the processor Only applies to Disabling processors.
+/// In future, we can add add/remove support
+///
+#define CPU_CAUSE_NOT_DISABLED      0x0000
+#define CPU_CAUSE_INTERNAL_ERROR    0x0001
+#define CPU_CAUSE_THERMAL_ERROR     0x0002
+#define CPU_CAUSE_SELFTEST_FAILURE  0x0004
+#define CPU_CAUSE_PREBOOT_TIMEOUT   0x0008
+#define CPU_CAUSE_FAILED_TO_START   0x0010
+#define CPU_CAUSE_CONFIG_ERROR      0x0020
+#define CPU_CAUSE_USER_SELECTION    0x0080
+#define CPU_CAUSE_BY_ASSOCIATION    0x0100
+#define CPU_CAUSE_UNSPECIFIED       0x8000
+
+typedef UINT32 CPU_STATE_CHANGE_CAUSE;
+
+typedef struct {
+  EFI_MP_PROC_CONTEXT                   *Context;
+  EFI_EXP_BASE10_DATA                   CoreFreq;
+  EFI_EXP_BASE10_DATA                   BusFreq;
+  EFI_EXP_BASE2_DATA                    CacheSize[EFI_CACHE_LMAX];
+  EFI_PROCESSOR_ID_DATA                 CpuId;
+  EFI_PROCESSOR_MICROCODE_REVISION_DATA MuData;
+  EFI_PROCESSOR_STATUS_DATA             Status;
+} EFI_DETAILED_CPU_INFO;
+
+///
+/// Platform Specific Processor Information
+///
+typedef struct {
+  UINT64                                 ApicID;                     ///< APIC ID
+  STRING_REF                             ReferenceString;            ///< Reference String
+  EFI_PROCESSOR_SOCKET_TYPE_DATA         SocketType;                 ///< Socket Type
+  EFI_PROCESSOR_SOCKET_NAME_DATA         SocketName;                 ///< Socket Name
+  EFI_PROCESSOR_MAX_CORE_FREQUENCY_DATA  MaxCoreFrequency;           ///< Maximum Core Frequency
+  EFI_PROCESSOR_MAX_FSB_FREQUENCY_DATA   MaxFsbFrequency;            ///< Maximum FSB Frequency
+  EFI_PROCESSOR_CORE_FREQUENCY_LIST_DATA PlatformCoreFrequencyList;  ///< Platform Core Frequency List
+  EFI_PROCESSOR_FSB_FREQUENCY_LIST_DATA  PlatformFsbFrequencyList;   ///< Platform FSB Frequency List
+  STRING_REF                             AssetTag;                   ///< Asset Tag
+  EFI_HII_HANDLE                         StringHandle;               ///< String Handle
+  STRING_REF                             SerialNumber;               ///< Serial Number
+  STRING_REF                             PartNumber;                 ///< Part Number
+} PLATFORM_CPU_INFORMATION;
+
+///
+/// This interface is for platform to provide processor support layout, such as how many packages we want
+/// processor code to support. If return EFI_UNSUPPORTED, processor code will assume MAXIMUM_CPU_NUMBER and
+/// allocate MAX memory for all APs.
+///
+typedef
+EFI_STATUS
+(EFIAPI *PLATFORM_CPU_GET_MAX_COUNT)(
+  IN DXE_CPU_PLATFORM_POLICY_PROTOCOL *This,
+  OUT UINT32                          *MaxThreadsPerCore,
+  OUT UINT32                          *MaxCoresPerDie,
+  OUT UINT32                          *MaxDiesPerPackage,
+  OUT UINT32                          *MaxPackages
+  );
+
+///
+/// Platform code can provide platform specific processor information, such as processor socket Name on board,
+/// processor Socket Type, and so on for SMBIOS table creation.
+///
+typedef
+EFI_STATUS
+(EFIAPI *PLATFORM_CPU_GET_CPU_INFO)(
+  IN DXE_CPU_PLATFORM_POLICY_PROTOCOL *This,
+  IN CPU_PHYSICAL_LOCATION            *Location,
+  IN OUT PLATFORM_CPU_INFORMATION     *PlatformCpuInfo
+  );
+
+//
+// Generic definitions for device enabling/disabling used by CPU code
+//
+#define CPU_FEATURE_ENABLE  1
+#define CPU_FEATURE_DISABLE 0
+
+//
+// Generic definitions for DTS
+//
+#define DTS_OUT_OF_SPEC_ONLY      2
+#define DTS_OUT_OF_SPEC_OCCURRED  3
+
+///
+/// General CPU feature Configuration for all processor features enabling bit definitions are in this field.
+/// Platform code can enable/disable features thru this field.
+///
+typedef struct {
+  //
+  // Byte 0, bit definition for functionality enable/disable
+  //
+  UINT8 HtState                : 1; ///< Enable or Disable Hyper Threading State; 0: Disable; 1: Enable
+  UINT8 LimitCpuidMaximumValue : 1; ///< Enable or Disable Limit Cpuid Maximum Value; 0: Disable; 1: Enable
+  UINT8 DcaState               : 1; ///< @deprecated Deprecated for Client (Server specific)
+  UINT8 ExecuteDisableBit      : 1; ///< Enable or Disable Execute Disable Bit; 0: Disable; 1: Enable
+  UINT8 VmxEnable              : 1; ///< Enable or Disable VMX; 0: Disable; 1: Enable
+  UINT8 SmxEnable              : 1; ///< Enable or Disable SMX; 0: Disable; 1: Enable
+  UINT8 FastString             : 1; ///< @deprecated
+  UINT8 MachineCheckEnable     : 1; ///< Enable or Disable Machine Check; 0: Disable; 1: Enable
+  //
+  // Byte 1, bit definition for functionality enable/disable
+  //
+  UINT8 MonitorMwaitEnable      : 1; ///< Enable or Disable Monitor Mwait mode; 0: Disable; 1: Enable
+  UINT8 XapicEnable             : 1; ///< Enable or Disable Xapic mode; 0: Disable; 1: Enable
+  UINT8 MachineCheckStatusClean : 1; ///< @deprecated
+  UINT8 IsColdReset             : 1; ///< Check if is Cold Reset; 0: Not Cold Reset; 1: Cold Reset
+  UINT8 MlcStreamerPrefetcher   : 1; ///< Enable or Disable MlcStreamerPrefetcher; 0: Disable; 1: Enable
+  UINT8 MlcSpatialPrefetcher    : 1; ///< Enable or Disable MlcSpatialPrefetcher; 0: Disable; 1: Enable
+  UINT8 EnableDts               : 2; ///< Enable or Disable DTS feature; 0=Disable; 1=Enable; 2=OUT_OF_SPEC;
+  //
+  // Byte 2, byte definition for addiional functionalities expected later
+  //
+  UINT8 FviReport                : 1; ///< Enable or Disable FVI report; 0: Disable; 1: Enable
+  UINT8 AesEnable                : 1; ///< Enable or Disable AES feature; 0: Disable; 1: Enable
+  UINT8 DebugInterfaceEnable     : 1; ///< Enable or Disable Debug Interface; This policy must be disabled for production BIOS. <b>0: Disable</b>; 1: Enable
+  UINT8 DebugInterfaceLockEnable : 1; ///< Enable or Disable Debug Interface Lock; This policy must be enabled on production platforms. 0: Disable; <b>1: Enable</b>
+  UINT8 ApIdleManner             : 2; ///< Settings for AP Threads Idle; 1: HALT 2:MWAIT 3:RUN
+  UINT8 ApHandoffManner          : 2; ///< Settings for AP Handoff to OS; 1: HALT 2:MWAIT32
+  //
+  // CPU feature configuration
+  //
+  UINT8  BspSelection;                ///< Select BSP
+  UINT32 DcaPrefetchDelayValue;       ///< @deprecated Deprecated for Client (Server specific)
+  UINT8  VirtualWireMode;             ///< @deprecated
+  UINT8  SmmbaseSwSmiNumber;          ///< SW SMI Number from Smbase.
+  //
+  // CPU Misc Config
+  //
+  UINT8 FviSmbiosType;                ///< Create SMBIOS Table Type for FVI
+  //
+  // Functions provided by platform code
+  //
+  ///
+  /// Platform code can provide microcode location thru this function.
+  ///
+  PLATFORM_CPU_RETRIEVE_MICROCODE RetrieveMicrocode;
+  ///
+  /// Platform to provide the processor detail about Max Thread per Core, Max Cores per Die, Max Dies per
+  /// Package and Max packages.
+  ///
+  PLATFORM_CPU_GET_MAX_COUNT      GetMaxCount;
+  ///
+  /// Platform code to provide platform specific processor information
+  ///
+  PLATFORM_CPU_GET_CPU_INFO       GetCpuInfo;
+} CPU_CONFIG;
+
+///
+/// TxT Platform Configuration
+///
+typedef struct {
+  UINT8 ResetAux : 1;    ///< Reset Auxiliary content when it is set "TRUE"
+  UINT8 Reserved : 7;    ///< Reserved for future use
+  UINT8 ByetReserved[1]; ///< Reserved for future use
+} TXT_FUNCTION_CONFIG;
+
+
+///
+/// All processor security features enabling definitions are in this field.
+/// Platform code can enable/disable features thru this field.
+///
+typedef struct {
+  TXT_FUNCTION_CONFIG *TxtFunctionConfig;
+} SECURITY_CONFIG;
+
+///
+/// The CPU platform policy protocol allows the platform code to publish a set of configuration information that the
+/// CPU drivers will use to configure the processor. Platform code needs to provide the information for processor
+/// drivers to finish the initialization.
+///
+typedef struct _DXE_CPU_PLATFORM_POLICY_PROTOCOL {
+  ///
+  /// This member specifies the revision of the CPU Policy protocol. This field is used to indicate backwards
+  /// compatible changes to the protocol. Platform code that produces this protocol must fill with the correct revision
+  /// value for the PCH reference code to correctly interpret the content of the protocol fields.
+  ///
+  UINT8             Revision;
+  ///
+  /// Processor standard features configuration.
+  ///
+  CPU_CONFIG        *CpuConfig;
+  ///
+  /// Processor power management features configuration.
+  ///
+  POWER_MGMT_CONFIG *PowerMgmtConfig;
+  ///
+  /// Processor security features configuration.
+  ///
+  SECURITY_CONFIG   *SecurityConfig;
+} DXE_CPU_PLATFORM_POLICY_PROTOCOL;
+
+#endif
diff --git a/ReferenceCode/Haswell/Protocol/CpuPlatformPolicy/CpuPmConfig.h b/ReferenceCode/Haswell/Protocol/CpuPlatformPolicy/CpuPmConfig.h
new file mode 100644
index 0000000..d84ccab
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/CpuPlatformPolicy/CpuPmConfig.h
@@ -0,0 +1,302 @@
+/** @file
+  Describes the defintions / functions visible to the rest of the PPM.
+
+@copyright
+  Copyright (c) 2011 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _CPU_PM_CONFIG_H_
+#define _CPU_PM_CONFIG_H_
+
+///
+/// Define maximum number of custom ratio states supported
+///
+#define MAX_CUSTOM_RATIO_TABLE_ENTRIES  16
+
+///
+/// Define maximum number of custom ConfigTdp entries supported
+///
+#define MAX_CUSTOM_CTDP_ENTRIES 3
+
+///
+/// This structure is used to describe the custom processor ratio table desired by the platform
+///
+typedef struct {
+  ///
+  /// The number of custom ratio state entries, it must be a value from 2 to 16 for a valid custom ratio table.
+  ///
+  UINT8  NumberOfEntries;
+  UINT32 Cpuid;            ///< The CPU ID for which this custom ratio table applies.
+  UINT16 MaxRatio;         ///< The maximum ratio of the custom ratio table.
+  UINT16 StateRatio[MAX_CUSTOM_RATIO_TABLE_ENTRIES]; ///< The processor ratios in the custom ratio table.
+} PPM_CUSTOM_RATIO_TABLE;
+
+///
+/// This structure is used to describe which of the PPM functions will be enabled by PPM implementation.
+///
+typedef struct {
+  UINT32 Eist                  : 1; ///< Enable or Disable Intel SpeedStep Technology.
+  UINT32 Cx                    : 1; ///< Enable or Disable CPU power states (C-states).
+  UINT32 C1e                   : 1; ///< Enable or Disable Enhanced C-states.
+  UINT32 C3                    : 1; ///< Enable or Disable C3.
+  UINT32 C6                    : 1; ///< Enable or Disable C6.
+  UINT32 DeepCState            : 3; ///< Enable or Disable C7/C7S.
+  UINT32 LongLatencyC6         : 1; ///< Enable or Disable C6 Long Latency.
+  UINT32 LongLatencyC7         : 1; ///< Enable or Disable C7 Long Latency.
+  UINT32 C8                    : 1; ///< Enable or Disable C8.
+  UINT32 C9                    : 1; ///< Enable or Disable C9.
+  UINT32 C10                   : 1; ///< Enable or Disable C10.
+  UINT32 C1AutoDemotion        : 1; ///< Enable or Disable C1 Auto Demotion.
+  UINT32 C3AutoDemotion        : 1; ///< Enable or Disable C3 Auto Demotion.
+  UINT32 TurboMode             : 1; ///< Enable or Disable long duration Turbo Mode.
+  UINT32 PowerLimit2           : 1; ///< Enable or Disable short duration Turbo Mode.
+  UINT32 EnergyEfficientPState : 1; ///< Enable or Disable Energy Efficient P-state will be applied in Turbo mode.
+  UINT32 BiProcHot             : 1; ///< @deprecated in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.
+  UINT32 TStates               : 1; ///< @deprecated in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.
+  UINT32 Xe                    : 1; ///< Enable or Disable Intel Extreme Edition support.
+  UINT32 C1UnDemotion          : 1; ///< Enable or Disable C1UnDemotion.
+  UINT32 C3UnDemotion          : 1; ///< Enable or Disable C3UnDemotion.
+  UINT32 PkgCStateDemotion     : 1; ///< Enable or Disable Package Cstate Demotion.
+  UINT32 PkgCStateUnDemotion   : 1; ///< Enable or Disable Package Cstate UnDemotion.
+  UINT32 DisableProcHotOut     : 1; ///< @deprecated in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.
+  UINT32 DisableVRThermalAlert : 1; ///< @deprecated in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.
+  UINT32 ProcHotResponce       : 1; ///< @deprecated in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.
+  UINT32 AutoThermalReporting  : 1; ///< @deprecated in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.
+  UINT32 CStatePreWake         : 1; ///< Enable or Disable CState-Pre wake.
+  UINT32 ThermalMonitor        : 1; ///< @deprecated in Powermgmt policy and moved to THERM_FUNCTION_ENABLES.
+  UINT32 LakeTiny              : 1; ///< Enable or Disable LakeTiny Support.
+  UINT32 TimedMwait            : 1; ///< Enable or Disable TimedMwait Support.
+  UINT32 Reserved              : 2; ///< Bits reserved for future use.
+} PPM_FUNCTION_ENABLES;
+
+///
+/// This structure is used to describe various PPM turbo settings
+///
+typedef struct _PPM_TURBO_SETTINGS {
+  UINT16 PowerLimit1;     ///< Package Long duration turbo mode power limit in 125mw or watts.
+  UINT32 PowerLimit1Time; ///< Package Long duration turbo mode time window in seconds.
+  UINT16 PowerLimit2;     ///< Package Short duration turbo mode power limit in 125mw or watts.
+  ///
+  /// Describes whether TURBO_POWER_LIMIT[63] should be set. Setting this bit will lock all Turbo settings.
+  ///
+  UINT8  TurboPowerLimitLock;
+  UINT16 DdrPowerLimit1;     ///< @deprecated in Powermgmt policy
+  UINT32 DdrPowerLimit1Time; ///< @deprecated in Powermgmt policy
+  UINT16 DdrPowerLimit2;     ///< @deprecated in Powermgmt policy
+  UINT8  DdrPowerLimitLock;  ///< @deprecated in Powermgmt policy
+  ///
+  /// Configuration for boot TDP selection, value 0 describes TDP Nominal, value 1 describes TDP Down and
+  /// value 2 describes TDP Up.
+  ///
+  UINT8  ConfigTdpLevel;
+  ///
+  /// Configurable TDP Mode Lock can be sets the to Lock ConfigTdp mode settings from runtime change.
+  ///
+  UINT8  ConfigTdpLock;
+  UINT8  ConfigTdpBios; ///< Configuration whether load Configurable TDP SSDT.
+  UINT8  EnergyPolicy;  ///< Describes the Energy efficiency policy to be set in MSR 0x1B0.
+
+  // 
+  // PL3 configuration
+  //
+  UINT16 PowerLimit3;           ///< Package PL3 power limit in 125mw or watts.
+  UINT32 PowerLimit3Time;       ///< Package PL3 time window in seconds.
+  UINT8  PowerLimit3DutyCycle;  ///< Package PL3 Duty Cycle.
+  UINT8  PowerLimit3Lock;       ///< Package PL3 MSR 615h lock.
+
+} PPM_TURBO_SETTINGS;
+
+///
+/// PPM Custom ConfigTdp Settings
+///
+typedef struct _PPM_CUSTOM_CTDP_TABLE {
+  UINT16 CustomPowerLimit1;          ///< Short term Power Limit value for custom cTDP level in 125mw or watts.
+  UINT16 CustomPowerLimit2;          ///< Long term Power Limit value for custom cTDP level in 125mw or watts.
+  UINT8  CustomPowerLimit1Time;      ///< Short term Power Limit time window value for custom cTDP level.
+  UINT8  CustomTurboActivationRatio; ///< Turbo Activation Ratio for custom cTDP level.
+  UINT8  CustomConfigTdpControl;     ///< Config Tdp Control (0/1/2) value for custom cTDP level.
+} PPM_CUSTOM_CTDP_TABLE;
+
+///
+/// This structure is used to configure custom ConfigTdp level settings.
+///
+typedef struct _PPM_CUSTOM_CTDP {
+  UINT8                 ConfigTdpCustom;     ///< Describes whether or not Custom Config Tdp should be enabled.
+  UINT8                 CustomTdpCount;      ///< Describes the number of Custom Config Tdp levels required (1/2/3).
+  UINT8                 CustomBootModeIndex; ///< Describes the Boot mode index selection from Custom Tdp levels.Index to CustomConfigTdpTable. valid values are 0,1,2.
+  ///
+  /// Describes the details of each Custom Config Tdp levels. This supports up to  MAX_CUSTOM_CTDP_ENTRIES number
+  /// of Custom ConfigTdp levels.
+  ///
+  PPM_CUSTOM_CTDP_TABLE CustomConfigTdpTable[MAX_CUSTOM_CTDP_ENTRIES];
+} PPM_CUSTOM_CTDP;
+
+///
+/// This structure is used to control enabled / disabled various PPM MSR lock settings
+///
+typedef struct _PPM_LOCK_ENABLES {
+  UINT32 PmgCstCfgCtrlLock : 1;   ///< Setting this to 1 will set MSR 0xE2[15]
+  UINT32 OverclockingLock  : 1;   ///< Setting this to 1 will set MSR 0x194[20]
+  UINT32 ProcHotLock       : 1;   ///< Setting this to 1 will set MSR 0x1FC[23]
+  UINT32 Reserved          : 29;  ///< Bits reserved for future use.
+} PPM_LOCK_ENABLES;
+///
+/// PM Deep C State Limit
+///
+typedef enum {
+  Disabled                = 0,
+  DeepC7,
+  DeepC7S
+} DEEP_C_STATE;
+///
+/// PPM Package C State Limit
+///
+typedef enum {
+  PkgC0C1                 = 0,
+  PkgC2,
+  PkgC3,
+  PkgC6,
+  PkgC7,
+  PkgC7s,
+  PkgC8,
+  PkgC9,
+  PkgC10,
+  PkgCMax,
+  PkgCpuDefault = 254,
+  PkgAuto = 255
+} MAX_PKG_C_STATE;
+///
+/// PPM Package C State Time Limit
+///
+typedef enum {
+  TimeUnit1ns             = 0,
+  TimeUnit32ns,
+  TimeUnit1024ns,
+  TimeUnit32768ns,
+  TimeUnit1048576ns,
+  TimeUnit33554432ns
+} C_STATE_TIME_UNIT;
+///
+/// Custom Power Uints.User can choose to enter in MilliWatts or Watts
+///
+typedef enum {
+  PowerUnitWatts = 0,       ///< in Watts
+  PowerUnit125MilliWatts,   ///< in 125 Milli Watts. Example 11.250 W Value to use for Power limts 90
+  PowerUnitMax
+} CUSTOM_POWER_UNIT;
+
+typedef enum {
+  Percent5  = 242,
+  Percent10 = 229,
+  Percent15 = 217,
+  Percent20 = 204,
+  Percent25 = 191,
+  Percent30 = 178,
+  Percent35 = 166,
+  Percent40 = 153,
+  Percent45 = 140,
+  Percent50 = 127,
+  Percent55 = 115,
+  Percent60 = 102,
+  Percent65 = 89,
+  Percent70 = 76,
+  Percent75 = 64,
+  Percent80 = 51,
+  Percent85 = 38,
+  Percent90 = 25,
+  Percent95 = 13,
+  Percent100 = 0
+} PL1_THERMAL_THROTTLE_FLOOR_UNIT;
+
+typedef struct {
+    PL1_THERMAL_THROTTLE_FLOOR_UNIT FloorIA;  /// < FLOOR_IA, Default: 0 (Percent100)
+    PL1_THERMAL_THROTTLE_FLOOR_UNIT FloorGT;  /// < FLOOR_GT, Default: 0 (Percent100)
+    PL1_THERMAL_THROTTLE_FLOOR_UNIT FloorPCH; /// < FLOOR_PCH, Default: 0 (Percent100)
+} PL1_THERMAL_CONTROL_FLOOR;
+
+///
+/// This structure is used to describe which of the Thermal functions will be enabled by Thermal implementation.
+///
+typedef struct {
+  UINT16 BiProcHot             : 1; ///< Enable or Disable Bi-Directional PROCHOT#.
+  UINT16 TStates               : 1; ///< Enable or Disable T states.
+  UINT16 DisableProcHotOut     : 1; ///< Enable or Disable PROCHOT# signal being driven externally.
+  UINT16 DisableVRThermalAlert : 1; ///< Enable or Disable VR Thermal Alert.
+  UINT16 ProcHotResponce       : 1; ///< Enable or Disable PROCHOT# Responce.
+  UINT16 AutoThermalReporting  : 1; ///< Enable or Disable Thermal Reporting through ACPI tables.
+  UINT16 ThermalMonitor        : 1; ///< Enable or Disable Thermal Monitor.
+  UINT16 Pl1ThermalControl     : 2; ///< Disable(0), Enable/Manual(1), Auto(2) PL1 thermal throttling features
+  UINT16 ThermReserved         : 7; ///< Reserved
+  PL1_THERMAL_CONTROL_FLOOR Pl1ThermalControlFloor;  ///< PL1 Floor Throttle Values
+} THERM_FUNCTION_ENABLES;
+
+///
+/// Power management Configuration for all processor Power Management features enabling definitions are in this field.
+/// Platform code can enable/disable features thru this field.
+///
+typedef struct {
+  ///
+  /// This structure is used to describe which of the PPM functions should be enabled. For details of this structure,
+  /// please see Related Definitions.
+  ///
+  PPM_FUNCTION_ENABLES   *pFunctionEnables;
+  ///
+  /// This structure is used to describe the custom CPU Frequency Table that should be used. For details of this
+  /// structure, please see Related Definitions.
+  ///
+  PPM_CUSTOM_RATIO_TABLE *pCustomRatioTable;
+  ///
+  /// This structure is used to describe long duration and short duration turbo settings. For details of this
+  /// structure, please see Related Definitions.
+  ///
+  PPM_TURBO_SETTINGS     *pTurboSettings;
+  UINT8                  S3RestoreMsrSwSmiNumber; ///< SW SMI number to restore the power Mgmt MSRs during S3 resume.
+  UINT8                  *pRatioLimit;         ///< This field is a pointer to Ratio Limit.
+  PPM_LOCK_ENABLES       *pPpmLockEnables;     ///< This field is a pointer to PPM_LOCK_ENABLES structure.
+  PPM_CUSTOM_CTDP        *pCustomCtdpSettings; ///< This structure is used to describe the custom config TDP settings.
+  ///
+  /// This field is used to set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state.
+  ///
+  MAX_PKG_C_STATE        PkgCStateLimit;
+  C_STATE_TIME_UNIT      CstateLatencyControl0TimeUnit; ///< TimeUnit for Latency Control0 MSR 0x60A[12:10].
+  C_STATE_TIME_UNIT      CstateLatencyControl1TimeUnit; ///< TimeUnit for Latency Control1 MSR 0x60B[12:10].
+  C_STATE_TIME_UNIT      CstateLatencyControl2TimeUnit; ///< TimeUnit for Latency Control2 MSR 0x60C[12:10].
+  C_STATE_TIME_UNIT      CstateLatencyControl3TimeUnit; ///< TimeUnit for Latency Control3 MSR 0x633[12:10].
+  C_STATE_TIME_UNIT      CstateLatencyControl4TimeUnit; ///< TimeUnit for Latency Control4 MSR 0x634[12:10].
+  C_STATE_TIME_UNIT      CstateLatencyControl5TimeUnit; ///< TimeUnit for Latency Control5 MSR 0x635[12:10].
+  UINT16                 CstateLatencyControl0Irtl; ///< Interrupt Response Time Limit of LatencyContol0 MSR 0x60A[9:0].
+  UINT16                 CstateLatencyControl1Irtl; ///< Interrupt Response Time Limit of LatencyContol1 MSR 0x60B[9:0].
+  UINT16                 CstateLatencyControl2Irtl; ///< Interrupt Response Time Limit of LatencyContol2 MSR 0x60C[9:0].
+  UINT16                 CstateLatencyControl3Irtl; ///< Interrupt Response Time Limit of LatencyContol3 MSR 0x633[9:0].
+  UINT16                 CstateLatencyControl4Irtl; ///< Interrupt Response Time Limit of LatencyContol4 MSR 0x634[9:0].
+  UINT16                 CstateLatencyControl5Irtl; ///< Interrupt Response Time Limit of LatencyContol5 MSR 0x635[9:0].
+  BOOLEAN                RfiFreqTunningOffsetIsNegative; ///< Specify RfiFreqTunningOffset is Positive or Negative.
+  UINT8                  RfiFreqTunningOffset; ///< specify the Target FIVR Frequency offset.
+  ///
+  /// Calibrate 24MHz BCLK support; 0: NO_CALIBRATE, 1: PCODE_CALIBRATE, 2: BIOS_CALIBRATE (Default :1)
+  ///
+  UINT8                  PcodeCalibration;
+  BOOLEAN                EnableRerunPcodeCalibration; ///< Calibrate C state 24MHz BCLK support.
+  ///
+  /// This structure is used to describe which of the Thermal functions should be enabled. For details of this
+  /// structure, please see Related Definitions.
+  ///
+  THERM_FUNCTION_ENABLES *ThermalFuncEnables;
+  CUSTOM_POWER_UNIT   CustomPowerUnit;      ///< Power Management Custom Power Limit Unit.
+
+} POWER_MGMT_CONFIG;
+
+#endif
diff --git a/ReferenceCode/Haswell/Protocol/CpuProtocolLib.cif b/ReferenceCode/Haswell/Protocol/CpuProtocolLib.cif
new file mode 100644
index 0000000..4a25ea6
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/CpuProtocolLib.cif
@@ -0,0 +1,27 @@
+<component>
+	name = "CpuProtocolLib"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Haswell\Protocol\"
+	RefName = "CpuProtocolLib"
+[files]
+"CpuProtocolLib.sdl"	
+"CpuProtocolLib.mak"	
+"CpuProtocolLib.inf"	
+"CpuInfo\CpuInfo.c"
+"CpuInfo\CpuInfo.h"
+"CpuPlatformPolicy\CpuPlatformPolicy.c"
+"CpuPlatformPolicy\CpuPlatformPolicy.h"
+"CpuPlatformPolicy\CpuPmConfig.h"
+"MpService\MpService.c"
+"MpService\MpService.h"
+"Pfat\Pfat.c"
+"Pfat\Pfat.h"
+"PiMpService\PiMpService.c"
+"PiMpService\PiMpService.h"
+"PowerMgmtInitDone\PowerMgmtInitDone.c"
+"PowerMgmtInitDone\PowerMgmtInitDone.h"
+"PpmGlobalNvsArea\PpmGlobalNvsArea.c"
+"PpmGlobalNvsArea\PpmGlobalNvsArea.h"
+"SmmThunk\SmmThunk.c"
+"SmmThunk\SmmThunk.h"
+<endComponent>
diff --git a/ReferenceCode/Haswell/Protocol/CpuProtocolLib.inf b/ReferenceCode/Haswell/Protocol/CpuProtocolLib.inf
new file mode 100644
index 0000000..afd4836
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/CpuProtocolLib.inf
@@ -0,0 +1,75 @@
+## @file
+#  Component description file for the CPU protocol library
+#
+#@copyright
+#  Copyright (c)  2004 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains an 'Intel Peripheral Driver' and uniquely
+#  identified as "Intel Reference Module" and is
+#  licensed for Intel CPUs and chipsets under the terms of your
+#  license agreement with Intel or your vendor.  This file may
+#  be modified by the user, subject to additional terms of the
+#  license agreement
+#
+
+
+[defines]
+BASE_NAME       =   CpuProtocolLib
+COMPONENT_TYPE  =   LIBRARY
+
+[sources.common]
+  MpService/MpService.c
+  MpService/MpService.h
+  CpuPlatformPolicy/CpuPlatformPolicy.c
+  CpuPlatformPolicy/CpuPlatformPolicy.h
+  SmmThunk/SmmThunk.c
+  SmmThunk/SmmThunk.h
+  CpuInfo/CpuInfo.c
+  CpuInfo/CpuInfo.h
+  PiMpService/PiMpService.c
+  PiMpService/PiMpService.h
+  Pfat/Pfat.c
+  Pfat/Pfat.h
+  PowerMgmtInitDone/PowerMgmtInitDone.h
+  PowerMgmtInitDone/PowerMgmtInitDone.c
+  PpmGlobalNvsArea/PpmGlobalNvsArea.h
+  PpmGlobalNvsArea/PpmGlobalNvsArea.c
+
+[includes.common]
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)
+#
+# Typically the sample code referenced will be available in the code base already
+# So keep this include at the end to defer to the source base definition
+# and only use the sample code definition if source base does not include these files.
+#  
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/SampleCode
+
+#
+# Edk II Glue Library, some hearder are included by R9 header so have to include
+#
+
+ $(EFI_SOURCE)
+ $(EFI_SOURCE)/Framework
+ $(EDK_SOURCE)/Foundation
+ $(EDK_SOURCE)/Foundation/Framework
+ $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+ $(EDK_SOURCE)/Foundation/Core/Dxe
+ $(EDK_SOURCE)/Foundation/Include/Pei
+ $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+ $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+
+[nmake.common]
+C_STD_INCLUDE=
diff --git a/ReferenceCode/Haswell/Protocol/CpuProtocolLib.mak b/ReferenceCode/Haswell/Protocol/CpuProtocolLib.mak
new file mode 100644
index 0000000..e83e201
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/CpuProtocolLib.mak
@@ -0,0 +1,28 @@
+# MAK file for the ModulePart:PpmProtocolLib
+
+all : CpuProtocolLib
+
+$(BUILD_DIR)\CpuProtocolLib.lib : CpuProtocolLib
+
+CpuProtocolLib : $(BUILD_DIR)\CpuProtocolLib.mak CpuProtocolLibBin
+
+$(BUILD_DIR)\CpuProtocolLib.mak : $(CpuProtocolLib_DIR)\$(@B).cif $(CpuProtocolLib_DIR)\$(@B).mak $(BUILD_RULES)
+	$(CIF2MAK) $(CpuProtocolLib_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+
+CpuProtocolLibDxe_DEFINES = \
+    $(CFLAGS) \
+!IF "$(x64_BUILD)"=="1" 
+    /DMDE_CPU_X64 \
+!ELSE
+    /DMDE_CPU_IA32 \
+!ENDIF
+
+
+CpuProtocolLibBin : 
+	$(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\
+		/f $(BUILD_DIR)\CpuProtocolLib.mak all\
+		"MY_INCLUDES=$(EDK_INCLUDES) $(PROJECT_CPU_INCLUDES) $(EdkIIGlueLib_INCLUDES)" \
+		"CFLAGS=$(CpuProtocolLibDxe_DEFINES)"\
+        TYPE=LIBRARY \
+        LIBRARY_NAME=$(CpuProtocolLib_LIB)
diff --git a/ReferenceCode/Haswell/Protocol/CpuProtocolLib.sdl b/ReferenceCode/Haswell/Protocol/CpuProtocolLib.sdl
new file mode 100644
index 0000000..7fb311c
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/CpuProtocolLib.sdl
@@ -0,0 +1,29 @@
+TOKEN
+	Name  = CpuProtocolLib_SUPPORT
+	Value  = "1"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Master = Yes
+	Help  = "Main switch to enable CpuProtocolLib support in Project"
+End
+
+MODULE
+	Help  = "Includes CpuProtocolLib.mak to Project"
+	File  = "CpuProtocolLib.mak"
+End
+
+PATH
+	Name  = "CpuProtocolLib_DIR"
+End
+
+ELINK
+	Name  = "CpuProtocolLib_LIB"
+	InvokeOrder = ReplaceParent
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\CpuProtocolLib.lib"
+	Parent  = "CpuProtocolLib_LIB"
+	InvokeOrder = AfterParent
+End
diff --git a/ReferenceCode/Haswell/Protocol/MpService/MpService.c b/ReferenceCode/Haswell/Protocol/MpService/MpService.c
new file mode 100644
index 0000000..bf3c0c2
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/MpService/MpService.c
@@ -0,0 +1,24 @@
+/** @file
+  This is a protocol produced by the MP DXE driver.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains 'Framework Code' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may not be modified, except as allowed by
+  additional terms of your license agreement.
+**/
+#include "Tiano.h"
+#include EFI_PROTOCOL_DEFINITION (MpService)
+
+EFI_GUID gEfiMpServiceProtocolGuid = EFI_MP_SERVICES_PROTOCOL_GUID;
+
+EFI_GUID_STRING(&gEfiMpServiceProtocolGuid, "MP SERVICE", "MP Service Protocol");
diff --git a/ReferenceCode/Haswell/Protocol/MpService/MpService.h b/ReferenceCode/Haswell/Protocol/MpService/MpService.h
new file mode 100644
index 0000000..03d3d2a
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/MpService/MpService.h
@@ -0,0 +1,216 @@
+/** @file
+  This protocol produces MP Protocol
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains 'Framework Code' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may not be modified, except as allowed by
+  additional terms of your license agreement.
+**/
+#ifndef _MP_H_
+#define _MP_H_
+
+#include "LinkedList.h"
+
+#include EFI_PROTOCOL_CONSUMER(SmmBase) // added for EFI_AP_PROCEDURE
+
+#include EFI_PROTOCOL_CONSUMER (CpuIo)
+
+#define EFI_MP_SERVICES_PROTOCOL_GUID \
+  { \
+    0xf33261e7, 0x23cb, 0x11d5, 0xbd, 0x5c, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 \
+  }
+
+EFI_FORWARD_DECLARATION (EFI_MP_SERVICES_PROTOCOL);
+
+#ifndef DELIVERY_MODE_FIXED
+#define DELIVERY_MODE_FIXED           0x0
+#define DELIVERY_MODE_LOWEST_PRIORITY 0x1
+#define DELIVERY_MODE_SMI             0x2
+#define DELIVERY_MODE_REMOTE_READ     0x3
+#define DELIVERY_MODE_NMI             0x4
+#define DELIVERY_MODE_INIT            0x5
+#define DELIVERY_MODE_SIPI            0x6
+#define DELIVERY_MODE_MAX             0x7
+
+#define TRIGGER_MODE_EDGE             0x0
+#define TRIGGER_MODE_LEVEL            0x1
+#endif
+
+typedef union {
+  struct {
+    UINT32 Status                   : 2;
+    UINT32 Tested                   : 1;
+    UINT32 Reserved1                : 13;
+    UINT32 VirtualMemoryUnavailable : 1;
+    UINT32 Ia32ExecutionUnavailable : 1;
+    UINT32 FloatingPointUnavailable : 1;
+    UINT32 MiscFeaturesUnavailable  : 1;
+    UINT32 Reserved2                : 12;
+  } Bits;
+  UINT32 Uint32;
+} EFI_MP_HEALTH_FLAGS;
+
+#define EFI_MP_HEALTH_FLAGS_STATUS_HEALTHY                  0x0
+#define EFI_MP_HEALTH_FLAGS_STATUS_PERFORMANCE_RESTRICTED   0x1
+#define EFI_MP_HEALTH_FLAGS_STATUS_FUNCTIONALLY_RESTRICTED  0x2
+
+typedef struct {
+  EFI_MP_HEALTH_FLAGS Flags;
+  UINT32              TestStatus;
+} EFI_MP_HEALTH;
+
+typedef enum {
+  EfiCpuAP                = 0,
+  EfiCpuBSP,
+  EfiCpuDesignationMaximum
+} EFI_CPU_DESIGNATION;
+
+typedef struct {
+  UINT32 Package;
+  UINT32 Die;
+  UINT32 Core;
+  UINT32 Thread;
+} PHYSICAL_LOCATION;
+
+typedef struct {
+  UINT32              ApicID;
+  BOOLEAN             Enabled;
+  EFI_CPU_DESIGNATION Designation;
+  EFI_MP_HEALTH       Health;
+  UINTN               PackageNumber;
+  UINTN               NumberOfCores;
+  UINTN               NumberOfThreads;
+  UINT64              ProcessorPALCompatibilityFlags;
+  UINT64              ProcessorTestMask;
+} EFI_MP_PROC_CONTEXT;
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MP_SERVICES_GET_GENERAL_MP_INFO)(
+  IN EFI_MP_SERVICES_PROTOCOL *This,
+  OUT UINTN                   *NumberOfCPUs,
+  OUT UINTN                   *MaximumNumberOfCPUs,
+  OUT UINTN                   *NumberOfEnabledCPUs,
+  OUT UINTN                   *RendezvousIntNumber,
+  OUT UINTN                   *RendezvousProcLength
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MP_SERVICES_GET_PROCESSOR_CONTEXT)(
+  IN EFI_MP_SERVICES_PROTOCOL *This,
+  IN UINTN                    ProcessorNumber,
+  IN OUT UINTN                *BufferLength,
+  IN OUT EFI_MP_PROC_CONTEXT  *ProcessorContextBuffer
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MP_SERVICES_STARTUP_ALL_APS)(
+  IN EFI_MP_SERVICES_PROTOCOL *This,
+  IN EFI_AP_PROCEDURE         Procedure,
+  IN BOOLEAN                  SingleThread,
+  IN EFI_EVENT WaitEvent      OPTIONAL,
+  IN UINTN TimeoutInMicroSecs OPTIONAL,
+  IN OUT VOID *ProcArguments  OPTIONAL,
+  OUT UINTN *FailedCPUList    OPTIONAL
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MP_SERVICES_STARTUP_THIS_AP)(
+  IN EFI_MP_SERVICES_PROTOCOL *This,
+  IN EFI_AP_PROCEDURE         Procedure,
+  IN UINTN                    ProcessorNumber,
+  IN EFI_EVENT WaitEvent      OPTIONAL,
+  IN UINTN TimeoutInMicroSecs OPTIONAL,
+  IN OUT VOID *ProcArguments  OPTIONAL
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MP_SERVICES_SWITCH_BSP)(
+  IN EFI_MP_SERVICES_PROTOCOL *This,
+  IN UINTN                    ProcessorNumber,
+  IN BOOLEAN                  EnableOldBSP
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MP_SERVICES_SEND_IPI)(
+  IN EFI_MP_SERVICES_PROTOCOL *This,
+  IN UINTN                    ProcessorNumber,
+  IN UINTN                    VectorNumber,
+  IN UINTN                    DeliveryMode
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MP_SERVICES_ENABLEDISABLEAP)(
+  IN EFI_MP_SERVICES_PROTOCOL *This,
+  IN UINTN                    ProcessorNumber,
+  IN BOOLEAN                  NewAPState,
+  IN EFI_MP_HEALTH            *HealthState
+  );
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MP_SERVICES_WHOAMI)(
+  IN EFI_MP_SERVICES_PROTOCOL *This,
+  OUT UINTN                   *ProcessorNumber
+  );
+
+///
+/// This information is basically from Intel Platform Innovation Framework for EFI Multiprocessor Services Protocol
+/// Specification. When installed, the MP Services Protocol produces a collection of services that are needed for MP
+/// management, such as initialization and management of application processors.
+///
+struct _EFI_MP_SERVICES_PROTOCOL {
+  ///
+  /// This service retrieves general information of multiprocessors in the system.
+  ///
+  EFI_MP_SERVICES_GET_GENERAL_MP_INFO   GetGeneralMPInfo;
+  ///
+  /// This service gets detailed MP-related information of the requested processor.
+  ///
+  EFI_MP_SERVICES_GET_PROCESSOR_CONTEXT GetProcessorContext;
+  ///
+  /// This function is used to dispatch all enabled APs to the function specified by Procedure.
+  ///
+  EFI_MP_SERVICES_STARTUP_ALL_APS       StartupAllAPs;
+  ///
+  /// This function is used to dispatch one enabled AP to the function provided by the caller.
+  ///
+  EFI_MP_SERVICES_STARTUP_THIS_AP       StartupThisAP;
+  ///
+  /// This service switches the requested AP to be the BSP from that point onward.
+  ///
+  EFI_MP_SERVICES_SWITCH_BSP            SwitchBSP;
+  ///
+  /// This service sends an IPI to a specified AP.
+  ///
+  EFI_MP_SERVICES_SEND_IPI              SendIPI;
+  ///
+  /// This service lets the caller enable or disable an AP.
+  ///
+  EFI_MP_SERVICES_ENABLEDISABLEAP       EnableDisableAP;
+  ///
+  /// This service lets the caller processor get its handle number, with which any processor in the system can be
+  /// uniquely identified.
+  ///
+  EFI_MP_SERVICES_WHOAMI                WhoAmI;
+};
+
+extern EFI_GUID gEfiMpServiceProtocolGuid;
+
+#endif
diff --git a/ReferenceCode/Haswell/Protocol/Pfat/Pfat.c b/ReferenceCode/Haswell/Protocol/Pfat/Pfat.c
new file mode 100644
index 0000000..b86e1f8
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/Pfat/Pfat.c
@@ -0,0 +1,45 @@
+/** @file
+  This file defines PFAT Abstraction Protocol
+
+@copyright
+  Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Reference Module" and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+
+///
+/// Statements that include other files
+///
+///
+/// External include files do NOT need to be explicitly specified in real EDKII
+/// environment
+///
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGlueDxe.h"
+#endif
+///
+/// Include the PFAT SMM Protocol header file
+///
+#include "Pfat.h"
+
+///
+/// PFAT SMM Protocol GUID definition
+///
+EFI_GUID gSmmPfatProtocolGuid = SMM_PFAT_PROTOCOL_GUID;
+
+///
+/// PFAT SMM Protocol description
+///
+EFI_GUID_STRING(&gSmmPfatProtocolGuid, "SMM PFAT Protocol", "Intel(R) Platform Firmware Armoring Technology Protocol");
diff --git a/ReferenceCode/Haswell/Protocol/Pfat/Pfat.h b/ReferenceCode/Haswell/Protocol/Pfat/Pfat.h
new file mode 100644
index 0000000..b78905a
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/Pfat/Pfat.h
@@ -0,0 +1,129 @@
+/** @file
+  This file defines the PFAT Protocol which implements the
+  Intel(R) PFAT Host Controller Compatibility Interface.
+
+@copyright
+  Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+**/
+#ifndef _PFAT_H_
+#define _PFAT_H_
+
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+///
+/// GUID to locate PFAT SMM Protocol
+///
+#define SMM_PFAT_PROTOCOL_GUID \
+  { \
+    0xc3e156e4, 0x27b3, 0x4dff, 0xb8, 0x96, 0xfb, 0x11, 0x3b, 0x2e, 0x68, 0xb5 \
+  }
+#else
+///
+/// GUID to locate PFAT SMM Protocol
+///
+#define SMM_PFAT_PROTOCOL_GUID \
+  { \
+    0xc3e156e4, 0x27b3, 0x4dff, \
+    { \
+      0xb8, 0x96, 0xfb, 0x11, 0x3b, 0x2e, 0x68, 0xb5 \
+    } \
+  }
+#endif
+
+///
+/// Extern the GUID for protocol users.
+///
+extern EFI_GUID gSmmPfatProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PFAT_PROTOCOL PFAT_PROTOCOL;
+
+/**
+  This service will write PFAT_DIRECTORY MSR and invoke the PFAT Module by writing to PLAT_FRMW_PROT_TRIGGER MSR for writing/erasing to flash.
+  BIOS should invoke PFAT_PROTOCOL.Write() or PFAT_PROTOCOL.Erase() function prior to calling PFAT_PROTOCOL.Execute() for flash writes/erases (except for BiosUpdate).
+  Write()/Erase() function will render PFAT script during execution.
+  Execute() function will implement the following steps:
+  1. Update PFAT directory with address of PUP.
+  2. All the AP's except the master thread are put to sleep.
+  3. PFAT module is invoked from BSP to execute desired operation.
+  If BiosUpdate flag is set to true, PUP (PUP Header + PFAT Script + Update data) is part of data that is passed to SMI Handler. SMI Handler invokes PFAT module to process the update.
+  This function would be called by runtime driver, please do not use any MMIO macro here.
+
+  @param[in] This                Pointer to the PFAT_PROTOCOL instance.
+  @param[in] BiosUpdate          Flag to indicate flash update is requested by the Tool
+
+  @retval EFI_SUCCESS            Successfully completed flash operation.
+  @retval EFI_INVALID_PARAMETER  The parameters specified are not valid.
+  @retval EFI_UNSUPPORTED        The CPU or SPI memory is not supported.
+  @retval EFI_DEVICE_ERROR       Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PFAT_EXECUTE)(
+  IN PFAT_PROTOCOL *This,
+  IN BOOLEAN       BiosUpdate
+  );
+
+/**
+  This service fills PFAT script buffer for flash writes.
+  BIOS should invoke this function prior to calling PFAT_PROTOCOL.Execute() with all the relevant data required for flash write.
+  This function will not invoke PFAT Module, only create script required for writing to flash.
+  This function would be called by runtime driver, please do not use any MMIO macro here.
+
+  @param[in] This           Pointer to the PFAT_PROTOCOL instance.
+  @param[in] Address        This value specifies the offset from the start of the SPI Flash component where BIOS Image is located.
+  @param[in] DataByteCount  Number of bytes in the data portion.
+  @param[in] Buffer         Pointer to caller-allocated buffer containing the dada sent.
+**/
+typedef
+VOID
+(EFIAPI *PFAT_WRITE)(
+  IN PFAT_PROTOCOL *This,
+  IN UINTN         Address,
+  IN UINT32        DataByteCount,
+  IN OUT UINT8     *Buffer
+  );
+
+/**
+  This service fills PFAT script buffer for erasing blocks in flash.
+  BIOS should invoke this function prior to calling PFAT_PROTOCOL.Execute() with all the relevant data required for flash erase.
+  This function will not invoke PFAT module, only create script required for erasing each block in the flash.
+  This function would be called by runtime driver, please do not use any MMIO macro here.
+
+  @param[in] This     Pointer to the PFAT_PROTOCOL instance.
+  @param[in] Address  This value specifies the offset from the start of the SPI Flash component where BIOS Image is located.
+**/
+typedef
+VOID
+(EFIAPI *PFAT_ERASE)(
+  IN PFAT_PROTOCOL *This,
+  IN UINTN         Address
+  );
+
+/**
+  This protocol provides all the services required for flash writes/erases via PFAT
+  PFAT Module can only be launched from SMM, this means that all flash writes & erases
+  that BIOS needs to do must flow thru SMI Handler and so dependency on SMM_BASE_PROTOCOL
+  for installing PFAT Protocol. Prior to PFAT SMM Protocol being installed there should
+  be no writes/erases to flash.
+**/
+struct _PFAT_PROTOCOL {
+  PFAT_WRITE   Write;   ///< Invoked to fill up PFAT script buffer for flash writes
+  PFAT_ERASE   Erase;   ///< Invoked to fill up PFAT script buffer for flash erases
+  PFAT_EXECUTE Execute; ///< Will trigger invocation of PFAT module
+};
+
+#endif
diff --git a/ReferenceCode/Haswell/Protocol/PiMpService/PiMpService.c b/ReferenceCode/Haswell/Protocol/PiMpService/PiMpService.c
new file mode 100644
index 0000000..c1a65e5
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/PiMpService/PiMpService.c
@@ -0,0 +1,24 @@
+/** @file
+  GUID Definition for the MP Services Protocol defined in the PI 1.1 spec.
+
+@copyright
+  Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains 'Framework Code' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may not be modified, except as allowed by
+  additional terms of your license agreement.
+**/
+#include "Tiano.h"
+#include EFI_PROTOCOL_DEFINITION (PiMpService)
+
+EFI_GUID gEfiPiMpServiceProtocolGuid = EFI_PI_MP_SERVICES_PROTOCOL_GUID;
+
+EFI_GUID_STRING(&gEfiPiMpServiceProtocolGuid, "PI MP SERVICE", "PI MP Service Protocol");
diff --git a/ReferenceCode/Haswell/Protocol/PiMpService/PiMpService.h b/ReferenceCode/Haswell/Protocol/PiMpService/PiMpService.h
new file mode 100644
index 0000000..1bf33b1
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/PiMpService/PiMpService.h
@@ -0,0 +1,500 @@
+/** @file
+  Definitions for the PI MP Services Protocol defined in the PI spec.
+
+@copyright
+  Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains 'Framework Code' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may not be modified, except as allowed by
+  additional terms of your license agreement.
+
+**/
+#ifndef _PI_MP_SERVICES_H_
+#define _PI_MP_SERVICES_H_
+
+///
+/// Share some definitions from Framework MP Services Protocol
+///
+#include EFI_PROTOCOL_CONSUMER (MpService)
+
+///
+/// Global ID for the EFI_PI_MP_SERVICES_PROTOCOL.
+///
+#define EFI_PI_MP_SERVICES_PROTOCOL_GUID \
+  { \
+    0x3fdda605, 0xa76e, 0x4f46, \
+    { \
+      0xad, 0x29, 0x12, 0xf4, 0x53, 0x1b, 0x3d, 0x08 \
+    } \
+  }
+
+///
+/// Forward declaration for the EFI_PI_MP_SERVICES_PROTOCOL.
+///
+typedef struct _EFI_PI_MP_SERVICES_PROTOCOL EFI_PI_MP_SERVICES_PROTOCOL;
+
+///
+/// Terminator for a list of failed CPUs returned by StartAllAPs().
+///
+#define END_OF_CPU_LIST 0xffffffff
+
+///
+/// This bit is used in the StatusFlag field of EFI_PROCESSOR_INFORMATION and
+/// indicates whether the processor is playing the role of BSP. If the bit is 1,
+/// then the processor is BSP. Otherwise, it is AP.
+///
+#define PROCESSOR_AS_BSP_BIT  0x00000001
+
+///
+/// This bit is used in the StatusFlag field of EFI_PROCESSOR_INFORMATION and
+/// indicates whether the processor is enabled. If the bit is 1, then the
+/// processor is enabled. Otherwise, it is disabled.
+///
+#define PROCESSOR_ENABLED_BIT 0x00000002
+
+///
+/// This bit is used in the StatusFlag field of EFI_PROCESSOR_INFORMATION and
+/// indicates whether the processor is healthy. If the bit is 1, then the
+/// processor is healthy. Otherwise, some fault has been detected for the processor.
+///
+#define PROCESSOR_HEALTH_STATUS_BIT 0x00000004
+
+///
+/// Structure that describes the pyhiscal location of a logical CPU.
+///
+typedef struct {
+  ///
+  /// Zero-based physical package number that identifies the cartridge of the processor.
+  ///
+  UINT32 Package;
+  ///
+  /// Zero-based physical core number within package of the processor.
+  ///
+  UINT32 Core;
+  ///
+  /// Zero-based logical thread number within core of the processor.
+  ///
+  UINT32 Thread;
+} EFI_CPU_PHYSICAL_LOCATION;
+
+///
+/// Structure that describes information about a logical CPU.
+///
+typedef struct {
+  ///
+  /// The unique processor ID determined by system hardware.  For IA32 and X64,
+  /// the processor ID is the same as the Local APIC ID. Only the lower 8 bits
+  /// are used, and higher bits are reserved.  For IPF, the lower 16 bits contains
+  /// id/eid, and higher bits are reserved.
+  ///
+  UINT64 ProcessorId;
+  ///
+  /// Flags indicating if the processor is BSP or AP, if the processor is enabled
+  /// or disabled, and if the processor is healthy. Bits 3..31 are reserved and
+  /// must be 0.
+  ///
+  /// <pre>
+  /// BSP  ENABLED  HEALTH  Description
+  /// ===  =======  ======  ===================================================
+  ///  0      0       0     Unhealthy Disabled AP.
+  ///  0      0       1     Healthy Disabled AP.
+  ///  0      1       0     Unhealthy Enabled AP.
+  ///  0      1       1     Healthy Enabled AP.
+  ///  1      0       0     Invalid. The BSP can never be in the disabled state.
+  ///  1      0       1     Invalid. The BSP can never be in the disabled state.
+  ///  1      1       0     Unhealthy Enabled BSP.
+  ///  1      1       1     Healthy Enabled BSP.
+  /// </pre>
+  ///
+  UINT32 StatusFlag;
+  ///
+  /// The physical location of the processor, including the physical package number
+  /// that identifies the cartridge, the physical core number within package, and
+  /// logical thread number within core.
+  ///
+  EFI_CPU_PHYSICAL_LOCATION Location;
+} EFI_PROCESSOR_INFORMATION;
+
+/**
+  This service retrieves the number of logical processor in the platform
+  and the number of those logical processors that are enabled on this boot.
+  This service may only be called from the BSP.
+
+  This function is used to retrieve the following information:
+    - The number of logical processors that are present in the system.
+    - The number of enabled logical processors in the system at the instant
+      this call is made.
+
+  Because MP Service Protocol provides services to enable and disable processors
+  dynamically, the number of enabled logical processors may vary during the
+  course of a boot session.
+
+  If this service is called from an AP, then EFI_DEVICE_ERROR is returned.
+  If NumberOfProcessors or NumberOfEnabledProcessors is NULL, then
+  EFI_INVALID_PARAMETER is returned. Otherwise, the total number of processors
+  is returned in NumberOfProcessors, the number of currently enabled processor
+  is returned in NumberOfEnabledProcessors, and EFI_SUCCESS is returned.
+
+  @param[in] This                      - A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
+  @param[in] NumberOfProcessors        - Pointer to the total number of logical processors in the system,
+                                         including the BSP and disabled APs.
+  @param[in] NumberOfEnabledProcessors - Pointer to the number of enabled logical processors that exist
+                                         in system, including the BSP.
+
+  @retval EFI_SUCCESS            - Number of logical processors and enabled logical processors retrieved.
+  @retval EFI_DEVICE_ERROR       - Caller processor is AP.
+  @retval EFI_INVALID_PARAMETER  - NumberOfProcessors is NULL.
+  @retval EFI_INVALID_PARAMETER  - NumberOfEnabledProcessors is NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS)(
+  IN EFI_PI_MP_SERVICES_PROTOCOL *This,
+  OUT UINTN                      *NumberOfProcessors,
+  OUT UINTN                      *NumberOfEnabledProcessors
+  );
+
+/**
+  Gets detailed MP-related information on the requested processor at the
+  instant this call is made. This service may only be called from the BSP.
+
+  This service retrieves detailed MP-related information about any processor
+  on the platform. Note the following:
+    - The processor information may change during the course of a boot session.
+    - The information presented here is entirely MP related.
+
+  Information regarding the number of caches and their sizes, frequency of operation,
+  slot numbers is all considered platform-related information and is not provided
+  by this service.
+
+  @param[in] This                - A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
+  @param[in] ProcessorNumber     -  The handle number of processor.
+  @param[in] ProcessorInfoBuffer - A pointer to the buffer where information for the requested processor is deposited.
+
+  @retval EFI_SUCCESS           - Processor information successfully returned.
+  @retval EFI_DEVICE_ERROR      - Caller processor is AP.
+  @retval EFI_INVALID_PARAMETER - ProcessorInfoBuffer is NULL
+  @retval EFI_NOT_FOUND         - Processor with the handle specified by ProcessorNumber does not exist.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PI_MP_SERVICES_GET_PROCESSOR_INFO)(
+  IN EFI_PI_MP_SERVICES_PROTOCOL *This,
+  IN UINTN                       ProcessorNumber,
+  OUT EFI_PROCESSOR_INFORMATION  *ProcessorInfoBuffer
+  );
+
+/**
+  This service executes a caller provided function on all enabled APs. APs can
+  run either simultaneously or one at a time in sequence. This service supports
+  both blocking and non-blocking requests. The non-blocking requests use EFI
+  events so the BSP can detect when the APs have finished. This service may only
+  be called from the BSP.
+
+  This function is used to dispatch all the enabled APs to the function specified
+  by Procedure.  If any enabled AP is busy, then EFI_NOT_READY is returned
+  immediately and Procedure is not started on any AP.
+
+  If SingleThread is TRUE, all the enabled APs execute the function specified by
+  Procedure one by one, in ascending order of processor handle number. Otherwise,
+  all the enabled APs execute the function specified by Procedure simultaneously.
+
+  If WaitEvent is NULL, execution is in blocking mode. The BSP waits until all
+  APs finish or TimeoutInMicroSecs expires. Otherwise, execution is in non-blocking
+  mode, and the BSP returns from this service without waiting for APs. If a
+  non-blocking mode is requested after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT
+  is signaled, then EFI_UNSUPPORTED must be returned.
+
+  If the timeout specified by TimeoutInMicroseconds expires before all APs return
+  from Procedure, then Procedure on the failed APs is terminated. All enabled APs
+  are always available for further calls to EFI_PI_MP_SERVICES_PROTOCOL.StartupAllAPs()
+  and EFI_PI_MP_SERVICES_PROTOCOL.StartupThisAP(). If FailedCpuList is not NULL, its
+  content points to the list of processor handle numbers in which Procedure was
+  terminated.
+
+  Note: It is the responsibility of the consumer of the EFI_PI_MP_SERVICES_PROTOCOL.StartupAllAPs()
+  to make sure that the nature of the code that is executed on the BSP and the
+  dispatched APs is well controlled. The MP Services Protocol does not guarantee
+  that the Procedure function is MP-safe. Hence, the tasks that can be run in
+  parallel are limited to certain independent tasks and well-controlled exclusive
+  code. EFI services and protocols may not be called by APs unless otherwise
+  specified.
+
+  In blocking execution mode, BSP waits until all APs finish or
+  TimeoutInMicroSeconds expires.
+
+  In non-blocking execution mode, BSP is freed to return to the caller and then
+  proceed to the next task without having to wait for APs. The following
+  sequence needs to occur in a non-blocking execution mode:
+
+    -# The caller that intends to use this MP Services Protocol in non-blocking
+       mode creates WaitEvent by calling the EFI CreateEvent() service.  The caller
+       invokes EFI_PI_MP_SERVICES_PROTOCOL.StartupAllAPs(). If the parameter WaitEvent
+       is not NULL, then StartupAllAPs() executes in non-blocking mode. It requests
+       the function specified by Procedure to be started on all the enabled APs,
+       and releases the BSP to continue with other tasks.
+    -# The caller can use the CheckEvent() and WaitForEvent() services to check
+       the state of the WaitEvent created in step 1.
+    -# When the APs complete their task or TimeoutInMicroSecondss expires, the MP
+       Service signals WaitEvent by calling the EFI SignalEvent() function. If
+       FailedCpuList is not NULL, its content is available when WaitEvent is
+       signaled. If all APs returned from Procedure prior to the timeout, then
+       FailedCpuList is set to NULL. If not all APs return from Procedure before
+       the timeout, then FailedCpuList is filled in with the list of the failed
+       APs. The buffer is allocated by MP Service Protocol using AllocatePool().
+       It is the caller's responsibility to free the buffer with FreePool() service.
+    -# This invocation of SignalEvent() function informs the caller that invoked
+       EFI_PI_MP_SERVICES_PROTOCOL.StartupAllAPs() that either all the APs completed
+       the specified task or a timeout occurred. The contents of FailedCpuList
+       can be examined to determine which APs did not complete the specified task
+       prior to the timeout.
+
+  @param[in] This                  - A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
+  @param[in] Procedure             - A pointer to the function to be run on enabled APs of the system.
+  @param[in] SingleThread          - Indicates whether to execute the function simultaneously or one by one..
+  @param[in] WaitEvent             - The event created by the caller.
+                                     If it is NULL, then execute in blocking mode.
+                                     If it is not NULL, then execute in non-blocking mode.
+  @param[in] TimeoutInMicrosecsond - The time limit in microseconds for this AP to finish the function.
+                                     Zero means infinity.
+  @param[in] ProcArgument          - Pointer to the optional parameter of the assigned function.
+  @param[in] FailedCpuList         - The list of processor numbers that fail to finish the function before
+                                     TimeoutInMicrosecsond expires.
+
+  @retval EFI_SUCCESS           - In blocking mode, all APs have finished before the timeout expired.
+  @retval EFI_SUCCESS           - In non-blocking mode, function has been dispatched to all enabled APs.
+  @retval EFI_DEVICE_ERROR      - Caller processor is AP.
+  @retval EFI_NOT_STARTED       - No enabled AP exists in the system.
+  @retval EFI_NOT_READY         - Any enabled AP is busy.
+  @retval EFI_TIMEOUT           - In blocking mode, The timeout expired before all enabled APs have finished.
+  @retval EFI_INVALID_PARAMETER - Procedure is NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PI_MP_SERVICES_STARTUP_ALL_APS)(
+  IN EFI_PI_MP_SERVICES_PROTOCOL *This,
+  IN EFI_AP_PROCEDURE            Procedure,
+  IN BOOLEAN                     SingleThread,
+  IN EFI_EVENT WaitEvent         OPTIONAL,
+  IN UINTN                       TimeoutInMicroSeconds,
+  IN VOID *ProcedureArgument     OPTIONAL,
+  OUT UINTN **FailedCpuList      OPTIONAL
+  );
+
+/**
+  This service lets the caller get one enabled AP to execute a caller-provided
+  function. The caller can request the BSP to either wait for the completion
+  of the AP or just proceed with the next task by using the EFI event mechanism.
+  See EFI_PI_MP_SERVICES_PROTOCOL.StartupAllAPs() for more details on non-blocking
+  execution support.  This service may only be called from the BSP.
+
+  This function is used to dispatch one enabled AP to the function specified by
+  Procedure passing in the argument specified by ProcedureArgument.  If WaitEvent
+  is NULL, execution is in blocking mode. The BSP waits until the AP finishes or
+  TimeoutInMicroSecondss expires. Otherwise, execution is in non-blocking mode.
+  BSP proceeds to the next task without waiting for the AP. If a non-blocking mode
+  is requested after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled,
+  then EFI_UNSUPPORTED must be returned.
+
+  If the timeout specified by TimeoutInMicroseconds expires before the AP returns
+  from Procedure, then execution of Procedure by the AP is terminated. The AP is
+  available for subsequent calls to EFI_PI_MP_SERVICES_PROTOCOL.StartupAllAPs() and
+  EFI_PI_MP_SERVICES_PROTOCOL.StartupThisAP().
+
+  @param[in] This                  - A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
+  @param[in] Procedure             - A pointer to the function to be run on the designated AP.
+  @param[in] ProcessorNumber       - The handle number of AP..
+  @param[in] WaitEvent             - The event created by the caller.
+                                     If it is NULL, then execute in blocking mode.
+                                     If it is not NULL, then execute in non-blocking mode.
+  @param[in] TimeoutInMicroseconds - The time limit in microseconds for this AP to finish the function.
+                                     Zero means infinity.
+  @param[in] ProcArgument          - Pointer to the optional parameter of the assigned function.
+  @param[in] Finished              - Indicates whether AP has finished assigned function.
+                                     In blocking mode, it is ignored.
+
+  @retval EFI_SUCCESS           - In blocking mode, specified AP has finished before the timeout expires.
+  @retval EFI_SUCCESS           - In non-blocking mode, function has been dispatched to specified AP.
+  @retval EFI_DEVICE_ERROR      - Caller processor is AP.
+  @retval EFI_TIMEOUT           - In blocking mode, the timeout expires before specified AP has finished.
+  @retval EFI_NOT_READY         - Specified AP is busy.
+  @retval EFI_NOT_FOUND         - Processor with the handle specified by ProcessorNumber does not exist.
+  @retval EFI_INVALID_PARAMETER - ProcessorNumber specifies the BSP or disabled AP.
+  @retval EFI_INVALID_PARAMETER - Procedure is NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PI_MP_SERVICES_STARTUP_THIS_AP)(
+  IN EFI_PI_MP_SERVICES_PROTOCOL *This,
+  IN EFI_AP_PROCEDURE            Procedure,
+  IN UINTN                       ProcessorNumber,
+  IN EFI_EVENT WaitEvent         OPTIONAL,
+  IN UINTN                       TimeoutInMicroseconds,
+  IN VOID *ProcedureArgument     OPTIONAL,
+  OUT BOOLEAN *Finished          OPTIONAL
+  );
+
+/**
+  This service switches the requested AP to be the BSP from that point onward.
+  This service changes the BSP for all purposes.   This call can only be performed
+  by the current BSP.
+
+  This service switches the requested AP to be the BSP from that point onward.
+  This service changes the BSP for all purposes. The new BSP can take over the
+  execution of the old BSP and continue seamlessly from where the old one left
+  off. This service may not be supported after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT
+  is signaled.
+
+  If the BSP cannot be switched prior to the return from this service, then
+  EFI_UNSUPPORTED must be returned.
+
+  @param[in] This                 - A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
+  @param[in] ProcessorNumber      - The handle number of processor.
+  @param[in] EnableOldBSP         - Whether to enable or disable the original BSP.
+
+  @retval EFI_SUCCESS           - BSP successfully switched.
+  @retval EFI_DEVICE_ERROR      - Caller processor is AP.
+  @retval EFI_NOT_FOUND         - Processor with the handle specified by ProcessorNumber does not exist.
+  @retval EFI_INVALID_PARAMETER - ProcessorNumber specifies the BSP or disabled AP.
+  @retval EFI_NOT_READY         - Specified AP is busy.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PI_MP_SERVICES_SWITCH_BSP)(
+  IN EFI_PI_MP_SERVICES_PROTOCOL *This,
+  IN UINTN                       ProcessorNumber,
+  IN BOOLEAN                     EnableOldBSP
+  );
+
+/**
+  This service lets the caller enable or disable an AP from this point onward.
+  This service may only be called from the BSP.
+
+  This service allows the caller enable or disable an AP from this point onward.
+  The caller can optionally specify the health status of the AP by Health. If
+  an AP is being disabled, then the state of the disabled AP is implementation
+  dependent. If an AP is enabled, then the implementation must guarantee that a
+  complete initialization sequence is performed on the AP, so the AP is in a state
+  that is compatible with an MP operating system. This service may not be supported
+  after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled.
+
+  If the enable or disable AP operation cannot be completed prior to the return
+  from this service, then EFI_UNSUPPORTED must be returned.
+
+  @param[in] This                  - A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
+  @param[in] ProcessorNumber       - The handle number of processor.
+  @param[in] EnableAP              - Indicates whether the newstate of the AP is enabled or disabled.
+  @param[in] HealthFlag            - Indicates new health state of the AP..
+
+  @retval EFI_SUCCESS            - AP successfully enabled or disabled.
+  @retval EFI_DEVICE_ERROR       - Caller processor is AP.
+  @retval EFI_NOT_FOUND          - Processor with the handle specified by ProcessorNumber does not exist.
+  @retval EFI_INVALID_PARAMETERS - ProcessorNumber specifies the BSP.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PI_MP_SERVICES_ENABLEDISABLEAP)(
+  IN EFI_PI_MP_SERVICES_PROTOCOL *This,
+  IN UINTN                       ProcessorNumber,
+  IN BOOLEAN                     EnableAP,
+  IN UINT32 *HealthFlag          OPTIONAL
+  );
+
+/**
+  This return the handle number for the calling processor.  This service may be
+  called from the BSP and APs.
+
+  This service returns the processor handle number for the calling processor.
+  The returned value is in the range from 0 to the total number of logical
+  processors minus 1. The total number of logical processors can be retrieved
+  with EFI_PI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors(). This service may be
+  called from the BSP and APs. If ProcessorNumber is NULL, then EFI_INVALID_PARAMETER
+  is returned. Otherwise, the current processors handle number is returned in
+  ProcessorNumber, and EFI_SUCCESS is returned.
+
+  @param[in] This                 - A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
+  @param[in] ProcessorNumber      - Pointer to the handle number of AP.
+
+  @retval EFI_SUCCESS           - Processor number successfully returned.
+  @retval EFI_INVALID_PARAMETER - ProcessorNumber is NULL
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PI_MP_SERVICES_WHOAMI)(
+  IN EFI_PI_MP_SERVICES_PROTOCOL *This,
+  OUT UINTN                      *ProcessorNumber
+  );
+
+///
+/// When installed, the MP Services Protocol produces a collection of services
+/// that are needed for MP management.
+///
+/// Before the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, the module
+/// that produces this protocol is required to place all APs into an idle state
+/// whenever the APs are disabled or the APs are not executing code as requested
+/// through the StartupAllAPs() or StartupThisAP() services. The idle state of
+/// an AP before the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT is signaled is
+/// implementation dependent.
+///
+/// After the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, all the APs
+/// must be placed in the OS compatible CPU state as defined by the UEFI
+/// Specification. Implementations of this protocol may use the UEFI event
+/// EFI_EVENT_GROUP_READY_TO_BOOT to force APs into the OS compatible state as
+/// defined by the UEFI Specification. Modules that use this protocol must
+/// guarantee that all non-blocking mode requests on all APs have been completed
+/// before the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT is signaled. Since the
+/// order that event notification functions in the same event group are executed
+/// is not deterministic, an event of type EFI_EVENT_GROUP_READY_TO_BOOT cannot
+/// be used to guarantee that APs have completed their non-blocking mode requests.
+///
+/// When the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, the StartAllAPs()
+/// and StartupThisAp() services must no longer support non-blocking mode requests.
+/// The support for SwitchBSP() and EnableDisableAP() may no longer be supported
+/// after this event is signaled. Since UEFI Applications and UEFI OS Loaders
+/// execute after the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, these
+/// UEFI images must be aware that the functionality of this protocol may be reduced.
+///
+struct _EFI_PI_MP_SERVICES_PROTOCOL {
+  ///
+  /// This service retrieves the number of logical processor in the platform and the number of those logical
+  /// processors that are enabled on this boot. This service may only be called from the BSP.
+  ///
+  EFI_PI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors;
+  ///
+  /// This service retrieves detailed MP-related information about any processor on the platform.
+  ///
+  EFI_PI_MP_SERVICES_GET_PROCESSOR_INFO       GetProcessorInfo;
+  ///
+  /// This service executes a caller provided function on all enabled APs.
+  ///
+  EFI_PI_MP_SERVICES_STARTUP_ALL_APS          StartupAllAPs;
+  ///
+  /// This service lets the caller get one enabled AP to execute a caller-provided function.
+  ///
+  EFI_PI_MP_SERVICES_STARTUP_THIS_AP          StartupThisAP;
+  ///
+  /// This service switches the requested AP to be the BSP from that point onward.
+  ///
+  EFI_PI_MP_SERVICES_SWITCH_BSP               SwitchBSP;
+  ///
+  /// This service lets the caller enable or disable an AP from this point onward. This service may only be
+  /// called from the BSP.
+  ///
+  EFI_PI_MP_SERVICES_ENABLEDISABLEAP          EnableDisableAP;
+  ///
+  /// This return the handle number for the calling processor.  This service may be called from the BSP and APs.
+  ///
+  EFI_PI_MP_SERVICES_WHOAMI                   WhoAmI;
+};
+
+extern EFI_GUID gEfiPiMpServiceProtocolGuid;
+
+#endif
diff --git a/ReferenceCode/Haswell/Protocol/PowerMgmtInitDone/PowerMgmtInitDone.c b/ReferenceCode/Haswell/Protocol/PowerMgmtInitDone/PowerMgmtInitDone.c
new file mode 100644
index 0000000..6849c6e
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/PowerMgmtInitDone/PowerMgmtInitDone.c
@@ -0,0 +1,42 @@
+/** @file
+  This file defines the Ppm Info Protocol.
+
+@copyright
+  Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+**/
+
+///
+/// Statements that include other files
+///
+///
+/// External include files do NOT need to be explicitly specified in real EDKII
+/// environment
+///
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGlueDxe.h"
+#endif
+
+#include "PowerMgmtInitDone.h"
+
+///
+/// Protocol GUID definition
+///
+EFI_GUID gEfiPowerMgmtInitDoneProtocolGuid = EFI_POWER_MGMT_INIT_DONE_PROTOCOL_GUID;
+
+///
+/// Protocol description
+///
+EFI_GUID_STRING
+        (&gEfiPowerMgmtInitDoneProtocolGuid, "PowerMgmtInitDone Protocol", "Power Managment Initialization done Protocol");
diff --git a/ReferenceCode/Haswell/Protocol/PowerMgmtInitDone/PowerMgmtInitDone.h b/ReferenceCode/Haswell/Protocol/PowerMgmtInitDone/PowerMgmtInitDone.h
new file mode 100644
index 0000000..5de11d1
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/PowerMgmtInitDone/PowerMgmtInitDone.h
@@ -0,0 +1,52 @@
+/** @file
+  This file defines the PowerMgmtInitDone Protocol.
+
+@copyright
+  Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+**/
+#ifndef _POWER_MGMT_INIT_DONE_H_
+#define _POWER_MGMT_INIT_DONE_H_
+
+///
+/// Define PPM INFO protocol GUID
+///
+/// EDK and EDKII have different GUID formats
+///
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#define EFI_POWER_MGMT_INIT_DONE_PROTOCOL_GUID \
+  { \
+    0xd71db106, 0xe32d, 0x4225, 0xbf, 0xf4, 0xde, 0x6d, 0x77, 0x87, 0x17, 0x61 \
+  }
+
+#else
+#define EFI_POWER_MGMT_INIT_DONE_PROTOCOL_GUID \
+  { \
+    0xd71db106, 0xe32d, 0x4225, \
+    { \
+      0xbf, 0xf4, 0xde, 0x6d, 0x77, 0x87, 0x17, 0x61 \
+    } \
+  }
+#endif
+///
+/// Extern the GUID for protocol users.
+///
+extern EFI_GUID gEfiPowerMgmtInitDoneProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _EFI_POWER_MGMT_INIT_DONE_PROTOCOL EFI_POWER_MGMT_INIT_DONE_PROTOCOL;
+
+#endif
diff --git a/ReferenceCode/Haswell/Protocol/PpmGlobalNvsArea/PpmGlobalNvsArea.c b/ReferenceCode/Haswell/Protocol/PpmGlobalNvsArea/PpmGlobalNvsArea.c
new file mode 100644
index 0000000..0c803c9
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/PpmGlobalNvsArea/PpmGlobalNvsArea.c
@@ -0,0 +1,31 @@
+/** @file
+  Processor Power Management Global NVS Area description protocol implementation.
+
+@copyright
+  Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and uniquely
+  identified as "Intel Mobile Silicon Support Module" and is
+  licensed for Intel Mobile CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#include "EdkIIGlueDxe.h"
+
+#include "PpmGlobalNvsArea.h"
+
+EFI_GUID gPpmGlobalNvsAreaProtocolGuid = EFI_PPM_GLOBAL_NVS_AREA_PROTOCOL_GUID;
+
+EFI_GUID_STRING
+(
+        &gPpmGlobalNvsAreaProtocolGuid, "PPM Global NVS Area Protocol",
+        "Protocol describing PPM ACPI NVS memory region used by ACPI subsystem."
+);
diff --git a/ReferenceCode/Haswell/Protocol/PpmGlobalNvsArea/PpmGlobalNvsArea.h b/ReferenceCode/Haswell/Protocol/PpmGlobalNvsArea/PpmGlobalNvsArea.h
new file mode 100644
index 0000000..ebae019
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/PpmGlobalNvsArea/PpmGlobalNvsArea.h
@@ -0,0 +1,129 @@
+/** @file
+  Definition of the CPU PM global NVS area protocol. This protocol
+  publishes the address and format of a global ACPI NVS buffer used as a communications
+  buffer between SMM/DXE/PEI code and ASL code.
+  @todo The format is derived from the ACPI reference code, version 0.95.
+
+  Note:  Data structures defined in this protocol are not naturally aligned.
+
+@copyright
+  Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+**/
+#ifndef _PPM_GLOBAL_NVS_AREA_H_
+#define _PPM_GLOBAL_NVS_AREA_H_
+
+///
+/// Forward reference for pure ANSI compatability
+///
+EFI_FORWARD_DECLARATION (PPM_GLOBAL_NVS_AREA_PROTOCOL);
+
+///
+/// Processor PM Global NVS Area Protocol GUID - {6C50CDCB-7F46-4dcc-8DDD-D9F0A3C61128}
+///
+#define EFI_PPM_GLOBAL_NVS_AREA_PROTOCOL_GUID \
+  { \
+    0x6c50cdcb, 0x7f46, 0x4dcc, 0x8d, 0xdd, 0xd9, 0xf0, 0xa3, 0xc6, 0x11, 0x28 \
+  }
+
+///
+/// Extern the GUID for protocol users.
+///
+extern EFI_GUID gPpmGlobalNvsAreaProtocolGuid;
+
+//
+// Processor Power Management GlobalNvs Revisions
+//
+#define PPM_GLOBAL_NVS_AREA_REVISION_1  1 ///< Initial Version
+
+#pragma pack(1)
+
+typedef struct {
+  UINT16 CtdpPowerLimit1;      ///< CTDP Power Limit1
+  UINT16 CtdpPowerLimit2;      ///< CTDP Power Limit2
+  UINT8  CtdpPowerLimitWindow; ///< CTDP Power Limit Time Window
+  UINT8  CtdpCtc;              ///< CTDP CTC
+  UINT8  CtdpTar;              ///< CTDP TAR
+  UINT8  CtdpPpc;              ///< CTDP PPC
+} PPM_CTDP_LEVEL_SETTINGS;
+
+///
+/// Global NVS Area definition
+///
+typedef struct {
+  UINT8  Revision;                 ///< (0) PPM GlobalNvs Revision
+  UINT32 PpmFlags;                 ///< (1-4) PPM Flags
+  UINT8  Reserved;                 ///< (5) Reserved
+  //
+  // Thermal Configuration Values
+  //
+  UINT8  AutoCriticalTripPoint;    ///< (6) Auto Critical Trip Point
+  UINT8  AutoPassiveTripPoint;     ///< (7) Auto Passive Trip Point
+  UINT8  AutoActiveTripPoint;      ///< (8) Auto Active Trip Point
+  UINT32 Cpuid;                    ///< (9) CPUID
+  //
+  // ConfigTDP Values
+  //
+  UINT8 ConfigurablePpc;           ///< (13) Boot Mode vlues for _PPC
+  //
+  // ConfigTDP Level settngs
+  //
+  UINT8 CustomConfigTdp;           ///< (14) ConfigTdp Enabled/Disabled
+  UINT8 CtdpLevelsSupported;       ///< (15) ConfigTdp Number Of Levels
+  UINT8 ConfigTdpBootModeIndex;    ///< (16) CTDP Boot Mode Index
+  ///
+  /// (17) CTDP Level 0 Power Limit1
+  /// (19) CTDP Level 0 Power Limit2
+  /// (21) CTDP Level 0 Power Limit1 Time Window
+  /// (22) CTDP Level 0 CTC
+  /// (23) CTDP Level 0 TAR
+  /// (24) CTDP Level 0 PPC
+  /// (25) CTDP Level 1 Power Limit1
+  /// (27) CTDP Level 1 Power Limit2
+  /// (29) CTDP Level 1 Power Limit1 Time Window
+  /// (30) CTDP Level 1 CTC
+  /// (31) CTDP Level 1 TAR
+  /// (32) CTDP Level 1 PPC
+  /// (33) CTDP Level 2 Power Limit1
+  /// (35) CTDP Level 2 Power Limit2
+  /// (37) CTDP Level 2 Power Limit1 Time Window
+  /// (38) CTDP Level 2 CTC
+  /// (39) CTDP Level 2 TAR
+  /// (40) CTDP Level 2 PPC
+  ///
+  PPM_CTDP_LEVEL_SETTINGS CtdpLevelSettings[3];
+  //
+  // Mwait Hints and Latency values for C3/C6/C7/C7S
+  //
+  UINT8  C3MwaitValue;             ///< (41) Mwait Hint value for C3
+  UINT8  C6MwaitValue;             ///< (42) Mwait Hint value for C6
+  UINT8  C7MwaitValue;             ///< (43) Mwait Hint value for C6
+  UINT8  CDMwaitValue;             ///< (44) Mwait Hint value for C7/C8/C9/C10
+  UINT16 C3Latency;                ///< (45-46) Latency value for C3
+  UINT16 C6Latency;                ///< (47-48) Latency Value for C6
+  UINT16 C7Latency;                ///< (49-50) Latency Value for C6
+  UINT16 CDLatency;                ///< (51-52) Latency Value for C7/C8/C9/C10
+  UINT16 CDIOLevel;                ///< (53-54) IO Level Value for C7/C8/C9/C10
+  UINT16 CDPowerValue;             ///< (55-56) Power Value for C7/C8/C9/C10
+  UINT8  MiscPowerManagementFlags; ///< (57) MiscPowerManagementFlags
+} PPM_GLOBAL_NVS_AREA;
+#pragma pack()
+///
+/// PPM Global NVS Area Protocol
+///
+struct _PPM_GLOBAL_NVS_AREA_PROTOCOL {
+  PPM_GLOBAL_NVS_AREA *Area;
+};
+
+#endif
diff --git a/ReferenceCode/Haswell/Protocol/SmmThunk/SmmThunk.c b/ReferenceCode/Haswell/Protocol/SmmThunk/SmmThunk.c
new file mode 100644
index 0000000..fd03cf8
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/SmmThunk/SmmThunk.c
@@ -0,0 +1,25 @@
+/** @file
+  This file defines SMM thunk abstraction protocol
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#include "Tiano.h"
+#include EFI_PROTOCOL_DEFINITION (SmmThunk)
+
+EFI_GUID gEfiSmmThunkProtocolGuid = EFI_SMM_THUNK_PROTOCOL_GUID;
+
+EFI_GUID_STRING(&gEfiSmmThunkProtocolGuid, "SMM Thunk Protocol", "SMM Thunk protocol");
diff --git a/ReferenceCode/Haswell/Protocol/SmmThunk/SmmThunk.h b/ReferenceCode/Haswell/Protocol/SmmThunk/SmmThunk.h
new file mode 100644
index 0000000..0c85718
--- /dev/null
+++ b/ReferenceCode/Haswell/Protocol/SmmThunk/SmmThunk.h
@@ -0,0 +1,64 @@
+/** @file
+  This file defines SMM Thunk abstraction protocol.
+
+@copyright
+  Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains an 'Intel Peripheral Driver' and is
+  licensed for Intel CPUs and chipsets under the terms of your
+  license agreement with Intel or your vendor.  This file may
+  be modified by the user, subject to additional terms of the
+  license agreement
+**/
+#ifndef _SMM_THUNK_H_
+#define _SMM_THUNK_H_
+
+EFI_FORWARD_DECLARATION (EFI_SMM_THUNK_PROTOCOL);
+
+///
+/// include LegacyBios Protocol for IA32_REGISTER_SET
+///
+#include EFI_PROTOCOL_DEFINITION (LegacyBios)
+
+#define EFI_SMM_THUNK_PROTOCOL_GUID \
+  { \
+    0x2a82fce6, 0x8bb6, 0x413e, 0xb9, 0xeb, 0x45, 0xdf, 0xc0, 0x52, 0x2d, 0xf3 \
+  }
+
+typedef
+BOOLEAN
+(EFIAPI *EFI_SMM_FARCALL86)(
+  IN EFI_SMM_THUNK_PROTOCOL          *This,
+  IN UINT16                          Segment,
+  IN UINT16                          Offset,
+  IN OUT EFI_IA32_REGISTER_SET *Regs OPTIONAL,
+  IN VOID *Stack                     OPTIONAL,
+  IN UINTN                           StackSize
+  );
+
+typedef
+BOOLEAN
+(EFIAPI *EFI_SMM_INTCALL86)(
+  IN EFI_SMM_THUNK_PROTOCOL          *This,
+  IN UINT16                          Segment,
+  IN UINT16                          Offset,
+  IN OUT EFI_IA32_REGISTER_SET *Regs OPTIONAL,
+  IN VOID *Stack                     OPTIONAL,
+  IN UINTN                           StackSize
+  );
+
+struct _EFI_SMM_THUNK_PROTOCOL {
+  EFI_SMM_FARCALL86 FarCall86;
+  EFI_SMM_INTCALL86 IntCall86;
+};
+
+extern EFI_GUID gEfiSmmThunkProtocolGuid;
+
+#endif