init. 1AQQW051HEADmaster

14 files changed, 1470 insertions, 0 deletions

diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyDxe.cif b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyDxe.cif
new file mode 100644
index 0000000..123e37c
--- /dev/null
+++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyDxe.cif
@@ -0,0 +1,13 @@
+<component>
+	name = "Cpu Policy DXE"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Haswell\SampleCode\CpuPolicyInit\Dxe"
+	RefName = "Cpu Policy Dxe"
+[files]
+"CpuPolicyDxe.mak"
+"CpuPolicyDxe.sdl"
+"CpuPolicyInitDxe.c"
+"CpuPolicyInitDxe.h"
+"CpuPolicyInitDxe.dxs"
+"CpuPolicyInitDxe.inf"
+<endComponent>
diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyDxe.mak b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyDxe.mak
new file mode 100644
index 0000000..da3c6dc
--- /dev/null
+++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyDxe.mak
@@ -0,0 +1,92 @@
+# MAK file for the eModule:PowerManagement
+
+EDK : CpuPolicyInitDxe
+
+BUILD_CpuPolicyInitDxe_DIR = $(BUILD_DIR)\$(CpuPolicyInitDxe_DIR)
+
+$(BUILD_DIR)\CpuPolicyDxe.mak : $(CpuPolicyInitDxe_DIR)\CpuPolicyDxe.cif $(BUILD_RULES)
+    $(CIF2MAK) $(CpuPolicyInitDxe_DIR)\CpuPolicyDxe.cif $(CIF2MAK_DEFAULTS)
+
+CpuPolicyInitDxe : $(BUILD_DIR)\CpuPolicyDxe.MAK CpuPolicyInitDxeBin 
+
+CpuInitDxe_OBJECTS = \
+    $(BUILD_CpuPolicyInitDxe_DIR)\CpuPolicyInitDxe.obj \
+
+CpuInitDxe_MY_INCLUDES= \
+    $(EDK_INCLUDES)\
+    $(PROJECT_CPU_INCLUDES)\
+    /I$(PROJECT_CPU_ROOT)\
+    /I$(UefiEfiIfrSupportLib_DIR)\
+    /I$(PROJECT_CPU_ROOT)\Include \
+
+CpuInitDxe_DEFINES = $(MY_DEFINES)\
+    /D"__EDKII_GLUE_MODULE_ENTRY_POINT__=CpuPolicyInitDxeEntryPoint"\
+    /D TXT_SUPPORT_FLAG=1 \
+    /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+    /D __EDKII_GLUE_BASE_LIB__ \
+    /D __EDKII_GLUE_BASE_MEMORY_LIB__ \
+    /D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \
+    /D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \
+    /D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \
+    /D __EDKII_GLUE_UEFI_DEVICE_PATH_LIB__ \
+    /D FV_MICROCODE_BASE=$(FV_MICROCODE_BASE) \
+    /D __EDKII_GLUE_HII_LIB__ \
+    /D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ \
+!ifdef PACK_MICROCODE
+    /D PACK_MICROCODE=$(PACK_MICROCODE) \
+!else
+    /D PACK_MICROCODE=0 \
+!endif
+    /D SMM_FROM_SMBASE_DRIVER=$(SMM_FROM_SMBASE_DRIVER) \
+    /D MICROCODE_BLOCK_SIZE=$(MICROCODE_BLOCK_SIZE) \
+
+CpuInitDxe_LIBS =\
+    $(PchPlatformLib)\
+    $(EfiRuntimeLib_LIB)\
+    $(INTEL_PCH_PROTOCOL_LIB)\
+    $(EFIRUNTIMELIB)\
+    $(CPUIA32LIB)\
+    $(EFIPROTOCOLLIB)\
+    $(EdkIIGlueUefiLib_LIB)\
+    $(EdkIIGlueDxeReportStatusCodeLib_LIB)\
+    $(EdkIIGlueDxeHobLib_LIB)\
+    $(EdkIIGlueDxeDebugLibReportStatusCode_LIB)\
+    $(EdkIIGlueBaseLib_LIB)\
+    $(EdkIIGlueBasePciLibPciExpress_LIB)\
+    $(CpuGuidLib_LIB)\
+!IF $(EFI_SPECIFICATION_VERSION) >= 0x0002000A
+    $(UEFIEFIIFRSUPPORTLIB)\
+!ELSE
+    $(EFIIFRSUPPORTLIB) \
+!ENDIF
+!IF "$(x64_BUILD)"=="1"
+    $(EdkIIGlueBaseLibX64_LIB)\
+!ELSE
+    $(EdkIIGlueBaseLibIA32_LIB)\
+!ENDIF
+    $(EdkIIGlueDxeMemoryAllocationLib_LIB)\
+    $(EdkIIGlueBaseIoLibIntrinsic_LIB)\
+    $(EdkIIGlueUefiBootServicesTableLib_LIB)\
+    $(EdkIIGlueUefiDevicePathLib_LIB)\
+    $(CpuProtocolLib_LIB)\
+    $(EFIDRIVERLIB)\
+    $(CpuPlatformLib_LIB)\
+    $(PchPlatformDxeLib_LIB)\
+    $(EFISCRIPTLIB)
+
+CpuPolicyInitDxeBin : $(CpuInitDxe_LIBS)
+    $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\
+    /f $(BUILD_DIR)\CpuPolicyDxe.mak all\
+    NAME=CpuPolicyDxe\
+    MAKEFILE=$(BUILD_DIR)\CpuPolicyDxe.mak \
+    "MY_INCLUDES=$(CpuInitDxe_MY_INCLUDES)" \
+    "MY_DEFINES=$(CpuInitDxe_DEFINES)"\
+    OBJECTS="$(CpuInitDxe_OBJECTS)" \
+    GUID=15B9B6DA-00A9-4de7-B8E8-ED7AFB88F16E\
+    ENTRY_POINT=_ModuleEntryPoint \
+    TYPE=BS_DRIVER \
+    EDKIIModule=DXEDRIVER\
+    DEPEX1=$(CpuPolicyInitDxe_DIR)\CpuPolicyInitDxe.dxs \
+    DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX  \
+    COMPRESS=1
+#-----------------------------------------------------------------------
diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyDxe.sdl b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyDxe.sdl
new file mode 100644
index 0000000..be33503
--- /dev/null
+++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyDxe.sdl
@@ -0,0 +1,58 @@
+#****************************************************************************
+#****************************************************************************
+#**                                                                        **
+#**           (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                        **
+#**                          All Rights Reserved.                          **
+#**                                                                        **
+#**           5555 Oakbrook Parkway, Suite 200, Norcross, GA 30071         **
+#**                                                                        **
+#**                          Phone (770)-246-8600                          **
+#**                                                                        **
+#****************************************************************************
+#****************************************************************************
+#****************************************************************************
+# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/Intel Haswell Cpu RC PKG/Cpu Policy DXE/CpuPolicyDxe.sdl 1     2/07/12 3:56a Davidhsieh $
+#
+# $Revision: 1 $
+#
+# $Date: 2/07/12 3:56a $
+#
+#****************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/Intel Haswell Cpu RC PKG/Cpu Policy DXE/CpuPolicyDxe.sdl $
+# 
+# 1     2/07/12 3:56a Davidhsieh
+# 
+# 1     5/06/11 6:06a Davidhsieh
+# First release
+# 
+#
+#****************************************************************************
+TOKEN
+	Name  = "CpuDxePolicy_SUPPORT"
+	Value  = "1"
+	Help  = "Main switch to enable Cpu Pei init support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Master = Yes
+End
+
+PATH
+	Name  = "CpuPolicyInitDxe_DIR"
+End
+
+MODULE
+	Help  = "Includes CpuPeiInit.mak to Project"
+	File  = "CpuPolicyDxe.mak"
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\CpuPolicyDxe.ffs"
+	Parent  = "FV_MAIN"
+	InvokeOrder = AfterParent
+End
+
diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyInitDxe.c b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyInitDxe.c
new file mode 100644
index 0000000..f78b89e
--- /dev/null
+++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyInitDxe.c
@@ -0,0 +1,461 @@
+/** @file
+  This file is SampleCode for Intel CPU DXE Platform Policy initialzation.
+
+@copyright
+  Copyright (c) 2009 - 2013 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+
+**/
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGlueDxe.h"
+
+#if (EFI_SPECIFICATION_VERSION >= 0x2000A)
+#include EFI_PROTOCOL_DEFINITION (HiiDatabase)
+#else
+#include EFI_PROTOCOL_DEFINITION (Hii)
+#endif
+#include EFI_PROTOCOL_DEFINITION (CpuInfo)
+#include "CpuPolicyInitDxe.h"
+#if (EFI_SPECIFICATION_VERSION >= 0x2000A)
+#include "UefiIfrLibrary.h"
+#endif
+
+//-#include "FlashMap.h"
+#include "CpuPlatformLib.h"
+
+#define SMM_FROM_SMBASE_DRIVER            0x55
+#define SW_SMI_FROM_SMMBASE               SMM_FROM_SMBASE_DRIVER
+
+#define PLATFORM_CPU_MAX_FSB_FREQUENCY    1066
+#endif
+
+//(AMI_CHG+)>
+VOID CallDxeCpuPolicyInitList(
+    IN EFI_SYSTEM_TABLE *SystemTable,
+    IN OUT DXE_CPU_PLATFORM_POLICY_PROTOCOL       *mCpuPolicyDataPtr);
+//<(AMI_CHG+)
+EFI_EXP_BASE10_DATA mCoreFrequencyList[] = {
+  { 0, 0}, ///< 0 Means "Auto", also, the first is the default.
+  {-1, 0} ///< End marker
+};
+
+EFI_EXP_BASE10_DATA mFsbFrequencyList[] = {
+  { 0, 0}, ///< 0 Means "Auto", also, the first is the default.
+  {-1, 0} ///< End marker
+};
+
+DXE_CPU_PLATFORM_POLICY_PROTOCOL mCpuPolicyData  = { 0 };
+CPU_CONFIG                       mCpuConfig      = { 0 };
+POWER_MGMT_CONFIG                mCpuPmConfig    = { 0 };
+SECURITY_CONFIG                  mSecurityConfig = { 0 };
+#if defined(TXT_SUPPORT_FLAG) && (TXT_SUPPORT_FLAG == 1)
+TXT_FUNCTION_CONFIG mTxtFunctionConfig = { 0 };
+#endif
+
+///
+/// Function implementations
+///
+/**
+  Platform function to get MAX CPU count
+
+  @param[in] This               - platform policy protocol
+  @param[in] MaxThreadsPerCore  - variable that will store MaxThreadsPerCore
+  @param[in] MaxCoresPerDie     - variable that will store MaxCoresPerDie
+  @param[in] MaxDiesPerPackage  - variable that will store MaxDiesPerPackage
+  @param[in] MaxPackages        - variable that will store MaxPackages
+
+  @retval EFI_SUCCESS           - Always return success
+**/
+EFI_STATUS
+EFIAPI
+PlatformCpuGetMaxCount (
+  IN DXE_CPU_PLATFORM_POLICY_PROTOCOL *This,
+  OUT UINT32                          *MaxThreadsPerCore,
+  OUT UINT32                          *MaxCoresPerDie,
+  OUT UINT32                          *MaxDiesPerPackage,
+  OUT UINT32                          *MaxPackages
+  )
+{
+  *MaxThreadsPerCore  = 2;
+  *MaxCoresPerDie     = 4;
+  *MaxDiesPerPackage  = 1;
+  *MaxPackages        = 1;
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Get CPU information
+
+  @param[in] This                - platform policy protocol
+  @param[in] Location            - structure that describe CPU location information
+  @param[in] PlatformCpuInfo     - structure that will be updated for platform CPU information
+
+  @retval EFI_INVALID_PARAMETER  - PlatformCpuInfo is NULL
+  @retval EFI_SUCCESS            - platform CPU info structure has been updated
+**/
+EFI_STATUS
+EFIAPI
+PlatformCpuGetCpuInfo (
+  IN DXE_CPU_PLATFORM_POLICY_PROTOCOL *This,
+  IN CPU_PHYSICAL_LOCATION            *Location,
+  IN OUT PLATFORM_CPU_INFORMATION     *PlatformCpuInfo
+  )
+{
+#if (EFI_SPECIFICATION_VERSION < 0x2000A)
+  EFI_HII_PROTOCOL *Hii;
+#endif
+  STRING_REF SocketNameToken;
+  STRING_REF FillByOemToken;
+  EFI_STATUS Status;
+  UINT64     MsrValue;
+  UINT8      CpuSku;
+
+  SocketNameToken = 0;
+  FillByOemToken  = 0;
+
+  ///
+  /// For Processor SocketName definition.
+  ///
+  if (PlatformCpuInfo == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+#if (EFI_SPECIFICATION_VERSION >= 0x2000A)
+  Status = IfrLibNewString (PlatformCpuInfo->StringHandle, &SocketNameToken, L"U3E1");
+  ASSERT_EFI_ERROR (Status);
+
+  Status = IfrLibNewString (PlatformCpuInfo->StringHandle, &FillByOemToken, L"To Be Filled By O.E.M.");
+  ASSERT_EFI_ERROR (Status);
+#else
+  Status = gBS->LocateProtocol (
+                  &gEfiHiiProtocolGuid,
+                  NULL,
+                  (VOID **) &Hii
+                  );
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+
+  Hii->NewString (
+          Hii,
+          NULL,
+          PlatformCpuInfo->StringHandle,
+          &SocketNameToken,
+          L"U3E1"
+          );
+
+  Hii->NewString (
+          Hii,
+          NULL,
+          PlatformCpuInfo->StringHandle,
+          &FillByOemToken,
+          L"To Be Filled By O.E.M."
+          );
+#endif
+
+  PlatformCpuInfo->ApicID           = Location->Thread;
+  PlatformCpuInfo->ReferenceString  = 0;
+  CpuSku = GetCpuSku ();
+  switch (CpuSku) {
+    case EnumCpuTrad:
+      PlatformCpuInfo->SocketType = 0x2d; // @todo EfiProcessorSocketLGA1150, pending updated SMBIOS spec release
+      break;
+
+    case EnumCpuUlt:
+      PlatformCpuInfo->SocketType = 0x2e; // @todo EfiProcessorSocketBGA1168, pending updated SMBIOS spec release
+      break;
+
+    default:
+      PlatformCpuInfo->SocketType = EfiProcessorSocketOther;
+      break;
+  }
+  PlatformCpuInfo->SocketName                 = SocketNameToken;
+
+  MsrValue = AsmReadMsr64 (MSR_PLATFORM_INFO);
+  PlatformCpuInfo->MaxCoreFrequency.Value     = (100 * (((UINT32) MsrValue >> N_PLATFORM_INFO_MAX_RATIO) & B_PLATFORM_INFO_RATIO_MASK));
+  PlatformCpuInfo->MaxCoreFrequency.Exponent  = 6;
+
+  PlatformCpuInfo->MaxFsbFrequency.Value      = PLATFORM_CPU_MAX_FSB_FREQUENCY;
+  PlatformCpuInfo->MaxFsbFrequency.Exponent   = 6;
+
+  PlatformCpuInfo->PlatformCoreFrequencyList  = mCoreFrequencyList;
+  PlatformCpuInfo->PlatformFsbFrequencyList   = mFsbFrequencyList;
+
+  PlatformCpuInfo->AssetTag                   = FillByOemToken;
+  PlatformCpuInfo->SerialNumber               = FillByOemToken;
+  PlatformCpuInfo->PartNumber                 = FillByOemToken;
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Get the microcode patch.
+
+  @param[in] This           - Driver context.
+  @param[in] MicrocodeData  - Retrieved image of the microcode.
+
+  @retval EFI_SUCCESS       - Image found.
+  @retval EFI_NOT_FOUND     - image not found.
+**/
+EFI_STATUS
+PlatformCpuRetrieveMicrocode (
+  IN DXE_CPU_PLATFORM_POLICY_PROTOCOL *This,
+  OUT UINT8                           **MicrocodeData
+  )
+{
+  /*EFI_CPU_MICROCODE_HEADER  *Microcode;
+  UINTN                     MicrocodeStart;
+  UINTN                     MicrocodeEnd;
+  UINTN                     TotalSize;
+
+  ///
+  /// Microcode binary in SEC
+  ///
+  MicrocodeStart = FLASH_REGION_MICROCODE_BASE +
+    ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FLASH_REGION_MICROCODE_BASE)->HeaderLength +
+    sizeof (EFI_FFS_FILE_HEADER);
+
+  MicrocodeEnd = FLASH_REGION_MICROCODE_BASE + FLASH_REGION_MICROCODE_SIZE;
+
+  if (*MicrocodeData == NULL) {
+    *MicrocodeData = (UINT8 *) (UINTN) MicrocodeStart;
+  } else {
+    if (*MicrocodeData < (UINT8 *) (UINTN) MicrocodeStart) {
+      return EFI_NOT_FOUND;
+    }
+
+    TotalSize = (UINTN) (((EFI_CPU_MICROCODE_HEADER *) *MicrocodeData)->TotalSize);
+    if (TotalSize == 0) {
+      TotalSize = 2048;
+    }
+    //
+    // Add alignment check - begin
+    //
+    if ((TotalSize & 0x7FF) != 0) {
+      TotalSize = (TotalSize & 0xFFFFF800) + 0x800;
+    }
+    //
+    // Add alignment check - end
+    //
+
+    *MicrocodeData += TotalSize;
+
+    Microcode = (EFI_CPU_MICROCODE_HEADER *) *MicrocodeData;
+    if (*MicrocodeData >= (UINT8 *) (UINTN) (MicrocodeEnd) || Microcode->TotalSize == (UINT32) -1) {
+      return EFI_NOT_FOUND;
+    }
+
+  }
+
+
+  return EFI_SUCCESS;*/
+  return EFI_NOT_FOUND;
+}
+
+/**
+  Initilize Intel Cpu DXE Platform Policy
+
+  @param[in] ImageHandle        Image handle of this driver.
+  @param[in] SystemTable        Global system service table.
+
+  @retval EFI_SUCCESS           Initialization complete.
+  @exception EFI_UNSUPPORTED    The chipset is unsupported by this driver.
+  @retval EFI_OUT_OF_RESOURCES  Do not have enough resources to initialize the driver.
+  @retval EFI_DEVICE_ERROR      Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+CpuPolicyInitDxeEntryPoint (
+  IN EFI_HANDLE       ImageHandle,
+  IN EFI_SYSTEM_TABLE *SystemTable
+  )
+{
+  EFI_STATUS Status;
+  CPU_FAMILY CpuFamilyId;
+
+  CpuFamilyId = GetCpuFamily();
+
+  mCpuPolicyData.Revision             = DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_7;
+  mCpuPolicyData.CpuConfig            = &mCpuConfig;
+  mCpuPolicyData.PowerMgmtConfig      = &mCpuPmConfig;
+  mCpuPolicyData.SecurityConfig       = &mSecurityConfig;
+
+  mCpuConfig.RetrieveMicrocode        = PlatformCpuRetrieveMicrocode;
+  mCpuConfig.GetMaxCount              = PlatformCpuGetMaxCount;
+  mCpuConfig.GetCpuInfo               = PlatformCpuGetCpuInfo;
+  mSecurityConfig.TxtFunctionConfig   = NULL;
+#ifdef TXT_SUPPORT_FLAG
+  mSecurityConfig.TxtFunctionConfig   = &mTxtFunctionConfig;
+#endif  // TXT_SUPPORT_FLAG
+  mCpuConfig.SmmbaseSwSmiNumber       = SW_SMI_FROM_SMMBASE;
+
+  mCpuConfig.HtState                  = CPU_FEATURE_ENABLE;
+  mCpuConfig.LimitCpuidMaximumValue   = CPU_FEATURE_DISABLE;
+  mCpuConfig.ExecuteDisableBit        = CPU_FEATURE_ENABLE;
+  mCpuConfig.VmxEnable                = CPU_FEATURE_ENABLE;
+  mCpuConfig.SmxEnable                = CPU_FEATURE_ENABLE;
+  mCpuConfig.MachineCheckEnable       = CPU_FEATURE_ENABLE;
+  mCpuConfig.MonitorMwaitEnable       = CPU_FEATURE_ENABLE;
+  mCpuConfig.XapicEnable              = CPU_FEATURE_DISABLE;
+  mCpuConfig.AesEnable                = CPU_FEATURE_ENABLE;
+  mCpuConfig.DebugInterfaceEnable     = CPU_FEATURE_DISABLE;
+  mCpuConfig.DebugInterfaceLockEnable = CPU_FEATURE_ENABLE;
+  mCpuConfig.MlcStreamerPrefetcher    = CPU_FEATURE_ENABLE;
+  mCpuConfig.MlcSpatialPrefetcher     = CPU_FEATURE_ENABLE;
+  mCpuConfig.EnableDts                = CPU_FEATURE_DISABLE;
+  mCpuConfig.BspSelection             = 0;
+  mCpuConfig.ApIdleManner             = 1;
+  mCpuConfig.ApHandoffManner          = 1;
+  ///
+  /// Virtual wire to A
+  ///
+  mCpuConfig.FviReport = 1;
+  ///
+  /// Default Enable FVI SMBIOS Report
+  ///
+  mCpuConfig.FviSmbiosType = 0xDD;
+  ///
+  /// Default SMBIOS Type 221
+  ///
+  /// Initialize Power Management Config
+  /// Allocate and set Power Management policy structure to recommended defaults
+  ///
+  mCpuPmConfig.pFunctionEnables     = AllocateZeroPool (sizeof (PPM_FUNCTION_ENABLES));
+  mCpuPmConfig.pCustomRatioTable    = AllocateZeroPool (sizeof (PPM_CUSTOM_RATIO_TABLE));
+  mCpuPmConfig.pTurboSettings       = AllocateZeroPool (sizeof (PPM_TURBO_SETTINGS));
+  mCpuPmConfig.pRatioLimit          = AllocateZeroPool ((sizeof (UINT8) * 4));
+  mCpuPmConfig.pPpmLockEnables      = AllocateZeroPool (sizeof (PPM_LOCK_ENABLES));
+  mCpuPmConfig.pCustomCtdpSettings  = AllocateZeroPool (sizeof (PPM_CUSTOM_CTDP));
+  mCpuPmConfig.ThermalFuncEnables   = AllocateZeroPool (sizeof (THERM_FUNCTION_ENABLES));
+
+  if ((mCpuPmConfig.pFunctionEnables == NULL) ||
+      (mCpuPmConfig.pCustomRatioTable == NULL) ||
+      (mCpuPmConfig.pTurboSettings == NULL) ||
+      (mCpuPmConfig.pPpmLockEnables == NULL) ||
+      (mCpuPmConfig.pCustomCtdpSettings == NULL) ||
+      (mCpuPmConfig.ThermalFuncEnables == NULL)
+      ) {
+    return EFI_OUT_OF_RESOURCES;
+  }
+
+  mCpuPmConfig.pFunctionEnables->Eist                   = PPM_ENABLE;
+  mCpuPmConfig.pFunctionEnables->Cx                     = PPM_ENABLE;
+  mCpuPmConfig.pFunctionEnables->C1e                    = PPM_ENABLE;
+  mCpuPmConfig.pFunctionEnables->C3                     = PPM_ENABLE;
+  mCpuPmConfig.pFunctionEnables->C6                     = PPM_ENABLE;
+  if (CpuFamilyId == EnumCpuHswUlt) {
+    mCpuPmConfig.pFunctionEnables->C8                   = PPM_ENABLE;
+    mCpuPmConfig.pFunctionEnables->C9                   = PPM_ENABLE;
+    mCpuPmConfig.pFunctionEnables->C10                  = PPM_ENABLE;
+  }
+  mCpuPmConfig.pFunctionEnables->DeepCState             = DeepC7S;
+  mCpuPmConfig.pFunctionEnables->C1AutoDemotion         = PPM_ENABLE;
+  mCpuPmConfig.pFunctionEnables->C3AutoDemotion         = PPM_ENABLE;
+  mCpuPmConfig.pFunctionEnables->C1UnDemotion           = PPM_ENABLE;
+  mCpuPmConfig.pFunctionEnables->C3UnDemotion           = PPM_ENABLE;
+  mCpuPmConfig.pFunctionEnables->PkgCStateDemotion      = PPM_DISABLE;
+  mCpuPmConfig.pFunctionEnables->PkgCStateUnDemotion    = PPM_DISABLE;
+  mCpuPmConfig.ThermalFuncEnables->BiProcHot            = PPM_ENABLE;
+  mCpuPmConfig.ThermalFuncEnables->DisableProcHotOut    = PPM_DISABLE;
+  mCpuPmConfig.ThermalFuncEnables->DisableVRThermalAlert= PPM_DISABLE;
+  mCpuPmConfig.ThermalFuncEnables->ProcHotResponce      = PPM_DISABLE;
+  mCpuPmConfig.ThermalFuncEnables->TStates              = PPM_DISABLE;
+  mCpuPmConfig.pFunctionEnables->Xe                     = PPM_DISABLE;
+  mCpuPmConfig.pFunctionEnables->TurboMode              = PPM_ENABLE;
+  mCpuPmConfig.pFunctionEnables->PowerLimit2            = PPM_ENABLE;
+  mCpuPmConfig.pFunctionEnables->EnergyEfficientPState  = PPM_ENABLE;
+  mCpuPmConfig.pFunctionEnables->CStatePreWake          = PPM_ENABLE;
+  mCpuPmConfig.ThermalFuncEnables->AutoThermalReporting   = PPM_ENABLE;
+
+  mCpuPmConfig.pFunctionEnables->LongLatencyC6          = PPM_DISABLE;
+  mCpuPmConfig.pFunctionEnables->LongLatencyC7          = PPM_ENABLE;
+  mCpuPmConfig.ThermalFuncEnables->ThermalMonitor       = PPM_ENABLE;
+  mCpuPmConfig.ThermalFuncEnables->Pl1ThermalControl    = 2; ///< AUTO
+  mCpuPmConfig.ThermalFuncEnables->Pl1ThermalControlFloor.FloorIA   = Percent100;
+  mCpuPmConfig.ThermalFuncEnables->Pl1ThermalControlFloor.FloorGT   = Percent100;
+  mCpuPmConfig.ThermalFuncEnables->Pl1ThermalControlFloor.FloorPCH  = Percent100;
+  mCpuPmConfig.pFunctionEnables->LakeTiny               = PPM_DISABLE;
+  mCpuPmConfig.pFunctionEnables->TimedMwait             = PPM_DISABLE;
+
+  mCpuPmConfig.CustomPowerUnit                          = PowerUnit125MilliWatts;
+  mCpuPmConfig.pTurboSettings->PowerLimit1              = AUTO;
+  mCpuPmConfig.pTurboSettings->PowerLimit2              = AUTO;
+  mCpuPmConfig.pTurboSettings->PowerLimit1Time          = AUTO;
+  mCpuPmConfig.pTurboSettings->PowerLimit3              = AUTO;
+  mCpuPmConfig.pTurboSettings->PowerLimit3Time          = AUTO;
+  mCpuPmConfig.pTurboSettings->PowerLimit3DutyCycle     = AUTO;
+  mCpuPmConfig.pTurboSettings->PowerLimit3Lock          = PPM_ENABLE;
+  mCpuPmConfig.pTurboSettings->ConfigTdpLevel           = 0;
+  mCpuPmConfig.pTurboSettings->ConfigTdpLock            = PPM_DISABLE;
+  mCpuPmConfig.pCustomCtdpSettings->ConfigTdpCustom     = PPM_DISABLE;
+
+  mCpuPmConfig.pTurboSettings->TurboPowerLimitLock      = PPM_DISABLE;
+  mCpuPmConfig.pTurboSettings->EnergyPolicy             = 0;
+
+  mCpuPmConfig.pPpmLockEnables->PmgCstCfgCtrlLock       = PPM_ENABLE;
+  mCpuPmConfig.pPpmLockEnables->OverclockingLock        = PPM_DISABLE;
+  mCpuPmConfig.pPpmLockEnables->ProcHotLock             = PPM_DISABLE;
+  mCpuPmConfig.S3RestoreMsrSwSmiNumber                  = SW_SMI_S3_RESTORE_MSR;
+  mCpuPmConfig.PkgCStateLimit = PkgAuto;
+
+  mCpuPmConfig.CstateLatencyControl0TimeUnit = TimeUnit1024ns;
+  mCpuPmConfig.CstateLatencyControl1TimeUnit = TimeUnit1024ns;
+  mCpuPmConfig.CstateLatencyControl2TimeUnit = TimeUnit1024ns;
+  mCpuPmConfig.CstateLatencyControl0Irtl = C3_LATENCY;
+  mCpuPmConfig.CstateLatencyControl1Irtl = C6_C7_SHORT_LATENCY;
+  mCpuPmConfig.CstateLatencyControl2Irtl = C6_C7_LONG_LATENCY;
+  if (CpuFamilyId == EnumCpuHswUlt) {
+    mCpuPmConfig.CstateLatencyControl3TimeUnit = TimeUnit1024ns;
+    mCpuPmConfig.CstateLatencyControl4TimeUnit = TimeUnit1024ns;
+    mCpuPmConfig.CstateLatencyControl5TimeUnit = TimeUnit1024ns;
+    mCpuPmConfig.CstateLatencyControl3Irtl = C8_LATENCY;
+    mCpuPmConfig.CstateLatencyControl4Irtl = C9_LATENCY;
+    //
+    // If PS4 is disabled, program 2750us to MSR_C_STATE_LATENCY_CONTROL_5
+    //
+    mCpuPmConfig.CstateLatencyControl5Irtl = C10_LATENCY;
+  }
+  mCpuPmConfig.RfiFreqTunningOffsetIsNegative = 0;
+  mCpuPmConfig.RfiFreqTunningOffset = 0;
+
+  if (CpuFamilyId == EnumCpuHswUlt) {
+    //
+    // Calibrate 24MHz BCLK support; 0: NO_CALIBRATE, 1: PCODE_CALIBRATE, 2: BIOS_CALIBRATE (Default :1)
+    //
+    mCpuPmConfig.PcodeCalibration                   = 1;
+    mCpuPmConfig.EnableRerunPcodeCalibration        = PPM_DISABLE;
+  }
+  ///
+  /// TxT platform config initiate
+  ///
+#if defined(TXT_SUPPORT_FLAG) && (TXT_SUPPORT_FLAG == 1)
+  mTxtFunctionConfig.ResetAux = 0;
+#endif
+
+  //AMI_REMOVE_TEMP_FOR_COMPILE
+  //UpdateDxeCpuPlatformPolicy (&mCpuPolicyData);   //(AMI_CHG)
+  CallDxeCpuPolicyInitList(SystemTable, &mCpuPolicyData);   // (AMI_CHG+)
+  ///
+  /// Install the DXE_CPU_PLATFORM_POLICY_PROTOCOL interface
+  ///
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &ImageHandle,
+                  &gDxeCpuPlatformPolicyProtocolGuid,
+                  &mCpuPolicyData,
+                  NULL
+                  );
+  ASSERT_EFI_ERROR (Status);
+  return Status;
+}
diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyInitDxe.dxs b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyInitDxe.dxs
new file mode 100644
index 0000000..7ff094a
--- /dev/null
+++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyInitDxe.dxs
@@ -0,0 +1,42 @@
+/** @file
+  Dependency expression source file.
+
+@copyright
+  Copyright (c) 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+
+**/
+
+
+//
+// Common for R8 and R9 codebase
+//
+#include "AutoGen.h"
+#include "PeimDepex.h"
+
+//
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase;
+// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase.
+//
+#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB)
+#include "EfiDepex.h"
+#endif
+
+#include EFI_ARCH_PROTOCOL_DEFINITION (Variable)
+
+
+DEPENDENCY_START
+    EFI_VARIABLE_ARCH_PROTOCOL_GUID
+DEPENDENCY_END
\ No newline at end of file
diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyInitDxe.h b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyInitDxe.h
new file mode 100644
index 0000000..8524faf
--- /dev/null
+++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyInitDxe.h
@@ -0,0 +1,50 @@
+/** @file
+  Header file for the CpuPolicyInitDxe Driver.
+
+@copyright
+  Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+**/
+#ifndef _CPU_PLATFORM_POLICY_DXE_H_
+#define _CPU_PLATFORM_POLICY_DXE_H_
+
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGlueDxe.h"
+#include "CpuAccess.h"
+#endif
+
+#include "UefiIfrLibrary.h"
+#include "PowermgmtDefinitions.h"
+#include EFI_PROTOCOL_PRODUCER (CpuPlatformPolicy)
+//AMI_REMOVE_FOR_COMPILE
+//#include "CpuPlatformPolicyUpdateDxeLib.h"
+
+/**
+  Initilize Intel CPU DXE Policy
+
+  @param[in] ImageHandle             Image handle of this driver.
+  @param[in] SystemTable             Global system service table.
+
+  @retval EFI_SUCCESS             Initialization complete.
+  @exception EFI_UNSUPPORTED         The chipset is unsupported by this driver.
+  @retval EFI_OUT_OF_RESOURCES    Do not have enough resources to initialize the driver.
+  @retval EFI_DEVICE_ERROR        Device error, driver exits abnormally.
+**/
+EFI_STATUS
+CpuPolicyInitDxeEntryPoint (
+  IN EFI_HANDLE           ImageHandle,
+  IN OUT EFI_SYSTEM_TABLE *SystemTable
+  );
+
+#endif
diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyInitDxe.inf b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyInitDxe.inf
new file mode 100644
index 0000000..b331411
--- /dev/null
+++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Dxe/CpuPolicyInitDxe.inf
@@ -0,0 +1,93 @@
+## @file
+#  Component description file for the CpuPolicyInitDxe DXE driver.
+#
+#@copyright
+#  Copyright (c)  2010 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+[defines]
+BASE_NAME            = CpuPolicyInitDxe
+FILE_GUID            = 15B9B6DA-00A9-4de7-B8E8-ED7AFB88F16E
+COMPONENT_TYPE       = BS_DRIVER
+
+[sources.common]
+  CpuPolicyInitDxe.h
+  CpuPolicyInitDxe.c
+#
+# Edk II Glue Driver Entry Point
+#
+  EdkIIGlueDxeDriverEntryPoint.c
+
+[includes.common]
+  $(DEST_DIR)
+  $(BUILD_DIR)/$(PROCESSOR)
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Pcd
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation/Core/Dxe
+  $(EDK_SOURCE)/Foundation/Cpu/Pentium/Include
+#
+# if (EFI_SPECIFICATION_VERSION < 0x0002000A), use EfiIfrSupportLib
+# if (EFI_SPECIFICATION_VERSION >= 0x0002000A), use UefiEfiIfrSupportLib
+#
+# $(EDK_SOURCE)/Foundation/Library/Dxe/EfiIfrSupportLib
+  $(EDK_SOURCE)/Foundation/Library/Dxe/UefiEfiIfrSupportLib
+  $(EFI_SOURCE)
+  $(EFI_SOURCE)/Include
+  $(EFI_SOURCE)/Library/CpuPolicyInitLib/Dxe
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include/Library
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Samplecode/Include
+  $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include
+
+[libraries.common]
+  EdkIIGlueDxeReportStatusCodeLib
+  EdkIIGlueDxeDebugLibReportStatusCode
+  EdkIIGlueDxeMemoryAllocationLib
+  EdkIIGlueUefiBootServicesTableLib
+  EdkIIGlueUefiRuntimeServicesTableLib
+  EdkFrameworkProtocolLib
+  EdkProtocolLib
+#
+# if (EFI_SPECIFICATION_VERSION < 0x0002000A), use EfiIfrSupportLib
+# if (EFI_SPECIFICATION_VERSION >= 0x0002000A), use UefiEfiIfrSupportLib, EfiDriverLib
+#
+#  EfiIfrSupportLib
+  EfiDriverLib
+  UefiEfiIfrSupportLib
+  CpuProtocolLib
+  CpuIA32Lib
+  PlatformPolicyUpdateDxeLib
+  CpuPlatformLib
+
+[nmake.common]
+  IMAGE_ENTRY_POINT = _ModuleEntryPoint
+  DPX_SOURCE        = CpuPolicyInitDxe.dxs
+#
+# Module Entry Point
+#
+  C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=CpuPolicyInitDxeEntryPoint
+  C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \
+                       -D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \
+                       -D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \
+                       -D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__
diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.c b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.c
new file mode 100644
index 0000000..c0badcf
--- /dev/null
+++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.c
@@ -0,0 +1,268 @@
+/** @file
+  This file is SampleCode for Intel CPU PEI Platform Policy initialization.
+
+@copyright
+  Copyright (c) 2010 - 2014 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+
+**/
+#include "CpuPolicyInitPei.h"
+
+//(AMI_CHG+)>
+VOID CallPeiCpuPolicyInitList(
+    IN EFI_PEI_SERVICES                 **PeiServices,
+    IN OUT PEI_CPU_PLATFORM_POLICY_PPI  *PeiCpuPolicyPpi);
+//<(AMI_CHG+)
+/**
+  This PEIM performs CPU PEI Platform Policy initialization.
+
+  @param[in] FfsHeader               Pointer to Firmware File System file header.
+  @param[in] PeiServices             General purpose services available to every PEIM.
+
+  @retval EFI_SUCCESS             The PPI is installed and initialized.
+  @retval EFI ERRORS              The PPI is not successfully installed.
+**/
+EFI_STATUS
+EFIAPI
+CpuPolicyInitPeiEntryPoint (
+  IN EFI_FFS_FILE_HEADER *FfsHeader,
+  IN EFI_PEI_SERVICES    **PeiServices
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_PEI_PPI_DESCRIPTOR      *CpuPlatformPolicyPpiDesc;
+  PEI_CPU_PLATFORM_POLICY_PPI *CpuPlatformPolicyPpi;
+  CPU_CONFIG_PPI              *CpuConfig;
+  SECURITY_CONFIG_PPI         *SecurityConfig;
+  PFAT_CONFIG                 *PfatConfig;
+  POWER_MGMT_CONFIG_PPI       *PowerMgmtConfig;
+  OVERCLOCKING_CONFIG_PPI     *OcConfig;
+  BOOT_GUARD_CONFIG           *BootGuardConfig;
+#if defined(TXT_SUPPORT_FLAG) && (TXT_SUPPORT_FLAG == 1)
+  TXT_CONFIG *TxtConfig;
+#endif
+  UINT8 PlatIdStr[] = "SHARK BAY";
+
+  ///
+  /// Allocate memory for the CPU Policy Ppi and Descriptor
+  ///
+  Status = ((*PeiServices)->AllocatePool)(PeiServices, sizeof (EFI_PEI_PPI_DESCRIPTOR), &CpuPlatformPolicyPpiDesc);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = ((*PeiServices)->AllocatePool)(PeiServices, sizeof (PEI_CPU_PLATFORM_POLICY_PPI), &CpuPlatformPolicyPpi);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = ((*PeiServices)->AllocatePool)(PeiServices, sizeof (CPU_CONFIG_PPI), &CpuConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = ((*PeiServices)->AllocatePool)(PeiServices, sizeof (SECURITY_CONFIG_PPI), &SecurityConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = ((*PeiServices)->AllocatePool)(PeiServices, sizeof (PFAT_CONFIG), &PfatConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = ((*PeiServices)->AllocatePool)(PeiServices, sizeof (POWER_MGMT_CONFIG_PPI), &PowerMgmtConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = ((*PeiServices)->AllocatePool)(PeiServices, sizeof (OVERCLOCKING_CONFIG_PPI), &OcConfig);
+  ASSERT_EFI_ERROR (Status);
+
+#if defined(TXT_SUPPORT_FLAG) && (TXT_SUPPORT_FLAG == 1)
+  Status = ((*PeiServices)->AllocatePool)(PeiServices, sizeof (TXT_CONFIG), &TxtConfig);
+  ASSERT_EFI_ERROR (Status);
+#endif
+
+  Status = ((*PeiServices)->AllocatePool) (PeiServices, sizeof (BOOT_GUARD_CONFIG), &BootGuardConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  CpuPlatformPolicyPpi->Revision                    = PEI_CPU_PLATFORM_POLICY_PPI_REVISION_8;
+  CpuPlatformPolicyPpi->CpuConfig                   = CpuConfig;
+  CpuPlatformPolicyPpi->SecurityConfig              = SecurityConfig;
+  CpuPlatformPolicyPpi->SecurityConfig->PfatConfig  = PfatConfig;
+  CpuPlatformPolicyPpi->PowerMgmtConfig             = PowerMgmtConfig;
+  CpuPlatformPolicyPpi->OverclockingConfig          = OcConfig;
+  CpuPlatformPolicyPpi->CpuPlatformPpiPtr           = (UINTN) CpuPlatformPolicyPpi;
+
+#if defined(TXT_SUPPORT_FLAG) && (TXT_SUPPORT_FLAG == 1)
+  CpuPlatformPolicyPpi->SecurityConfig->TxtConfig = TxtConfig;
+#else
+  CpuPlatformPolicyPpi->SecurityConfig->TxtConfig = NULL;
+#endif
+
+  CpuPlatformPolicyPpi->SecurityConfig->BootGuardConfig = BootGuardConfig;
+    
+  CpuConfig->CpuRatioOverride     = CPU_FEATURE_DISABLE;
+  CpuConfig->CpuRatio             = 63;
+  CpuConfig->CpuMaxNonTurboRatio  = 63;
+  CpuConfig->BistOnReset          = CPU_FEATURE_DISABLE;
+  CpuConfig->HyperThreading       = CPU_FEATURE_ENABLE;
+  CpuConfig->VmxEnable            = CPU_FEATURE_ENABLE;
+  CpuConfig->ActiveCoreCount      = 0;
+
+  ///
+  /// If CpuConfig->Pfat is set to ENABLE '1' then
+  ///   PlatformData->SmmBwp (found in PchPolicyInitPei.c file) has to be set to ENABLE '1'
+  /// This is a PFAT Security requirement that needs to be addressed
+  /// If CpuConfig->Pfat is set to DISABLE '0' then
+  ///   PlatformData->SmmBwp (found in PchPolicyInitPei.c file) value don't care, it can be
+  ///   set to either ENABLE '1' or DISABLE '0' based on customer implementation
+  ///
+  CpuConfig->Pfat = CPU_FEATURE_DISABLE;
+  ZeroMem (&PfatConfig->Ppdt, sizeof (PPDT));
+  PfatConfig->Ppdt.PpdtMajVer             = PPDT_MAJOR_VERSION;
+  PfatConfig->Ppdt.PpdtMinVer             = PPDT_MINOR_VERSION;
+  CopyMem (&PfatConfig->Ppdt.PlatId[0], &PlatIdStr[0], sizeof (PlatIdStr));
+  PfatConfig->Ppdt.PfatModSvn             = PFAT_SVN;
+  PfatConfig->Ppdt.BiosSvn                = 0x01380000;
+  PfatConfig->Ppdt.ExecLim                = 0;
+  PfatConfig->Ppdt.PlatAttr               = 0;
+  PfatConfig->Ppdt.LastSfam               = MIN_SFAM_COUNT - 1;
+  if (PfatConfig->Ppdt.LastSfam > (MAX_SFAM_COUNT - 1)) {
+    PfatConfig->Ppdt.LastSfam             = MAX_SFAM_COUNT - 1;
+  }
+  ///
+  /// SfamData [LastSfam + 1]
+  ///
+  PfatConfig->Ppdt.SfamData[0].FirstByte  = 0x00580000;
+  PfatConfig->Ppdt.SfamData[0].LastByte   = 0x0058FFFF;
+  PfatConfig->Ppdt.PpdtSize               = (sizeof (PPDT) - sizeof (PfatConfig->Ppdt.SfamData) + ((PfatConfig->Ppdt.LastSfam + 1) * sizeof (SFAM_DATA)));
+  PfatConfig->PpdtHash[0]  = 0xae7295370672663c;
+  PfatConfig->PpdtHash[1]  = 0x220375c996d23a36;
+  PfatConfig->PpdtHash[2]  = 0x73aaea0f2afded9d;
+  PfatConfig->PpdtHash[3]  = 0x707193b768a0829e;
+  ZeroMem (&PfatConfig->PupHeader, sizeof (PUP_HEADER));
+  PfatConfig->PupHeader.Version         = PUP_HDR_VERSION;
+  CopyMem (&PfatConfig->PupHeader.PlatId[0], &PlatIdStr[0], sizeof (PlatIdStr));
+  PfatConfig->PupHeader.PkgAttributes   = 0;
+  PfatConfig->PupHeader.PslMajorVer     = PSL_MAJOR_VERSION;
+  PfatConfig->PupHeader.PslMinorVer     = PSL_MINOR_VERSION;
+  PfatConfig->PupHeader.BiosSvn         = PfatConfig->Ppdt.BiosSvn;
+  PfatConfig->PupHeader.EcSvn           = 0;
+  PfatConfig->PupHeader.VendorSpecific  = 0x808655AA;
+  ZeroMem (&PfatConfig->PfatLog, sizeof (PFAT_LOG));
+  PfatConfig->PfatLog.Version         = PFAT_LOG_VERSION;
+  PfatConfig->PfatLog.LastPage        = 0;
+  if (PfatConfig->PfatLog.LastPage > (MAX_PFAT_LOG_PAGE - 1)) {
+    PfatConfig->PfatLog.LastPage      = MAX_PFAT_LOG_PAGE - 1;
+  }
+  PfatConfig->PfatLog.LoggingOptions  = 0;
+  PfatConfig->NumSpiComponents  = 2;
+  PfatConfig->ComponentSize[0]  = EnumSpiCompSize8MB;
+  PfatConfig->ComponentSize[1]  = EnumSpiCompSize8MB;
+  PfatConfig->PfatMemSize       = 0x05;
+
+  CpuConfig->MlcStreamerPrefetcher        = CPU_FEATURE_ENABLE;
+  CpuConfig->MlcSpatialPrefetcher         = CPU_FEATURE_ENABLE;
+
+  PowerMgmtConfig->RatioLimit[0]          = 0;
+  PowerMgmtConfig->RatioLimit[1]          = 0;
+  PowerMgmtConfig->RatioLimit[2]          = 0;
+  PowerMgmtConfig->RatioLimit[3]          = 0;
+  PowerMgmtConfig->TccActivationOffset    = 0;
+  PowerMgmtConfig->VrCurrentLimit         = VR_CURRENT_DEFAULT;
+  PowerMgmtConfig->VrCurrentLimitLock     = CPU_FEATURE_DISABLE;
+  PowerMgmtConfig->Xe                     = CPU_FEATURE_DISABLE;
+  PowerMgmtConfig->BootInLfm              = CPU_FEATURE_DISABLE;
+  ///
+  /// VrMiscIoutSlope      = 0x200 default
+  /// VrMiscIoutOffsetSign = 0 means it's positive offset. 1= negative offset
+  /// VrMiscIoutOffset     = 0 means it's 0%, 625 means 6.25% (range is +6.25% ~ -6.25%)
+  ///
+  PowerMgmtConfig->VrMiscIoutSlope        = 0x200;
+  PowerMgmtConfig->VrMiscIoutOffsetSign   = 0;
+  PowerMgmtConfig->VrMiscIoutOffset       = 0;
+
+  PowerMgmtConfig->VrMiscMinVid                = V_MSR_VR_MISC_CONFIG_MIN_VID_DEFAULT;
+  PowerMgmtConfig->VrMiscIdleExitRampRate      = CPU_FEATURE_ENABLE;
+  PowerMgmtConfig->VrMiscIdleEntryRampRate     = CPU_FEATURE_DISABLE;
+  PowerMgmtConfig->VrMiscIdleEntryDecayEnable  = CPU_FEATURE_ENABLE;
+  if (GetCpuFamily() == EnumCpuHswUlt) {
+    PowerMgmtConfig->VrMiscSlowSlewRateConfig  = V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_DEFAULT;
+    PowerMgmtConfig->VrMisc2FastRampVoltage    = V_MSR_VR_MISC_CONFIG2_FAST_RAMP_VOLTAGE_DEFAULT;
+    PowerMgmtConfig->VrMisc2MinC8Voltage       = V_MSR_VR_MISC_CONFIG2_MIN_C8_VOLTAGE_DEFAULT;
+    PowerMgmtConfig->VrPSI4enable              = CPU_FEATURE_ENABLE;
+  }
+  PowerMgmtConfig->Psi1Threshold        = PSI1_THRESHOLD_DEFAULT;
+  PowerMgmtConfig->Psi2Threshold        = PSI2_THRESHOLD_DEFAULT;
+  PowerMgmtConfig->Psi3Threshold        = PSI3_THRESHOLD_DEFAULT;
+
+  PowerMgmtConfig->FivrSscEnable        = 1;
+  PowerMgmtConfig->FivrSscPercent       = 62;
+
+  ///
+  /// Initiate TxT policy
+  ///
+#if defined(TXT_SUPPORT_FLAG) && (TXT_SUPPORT_FLAG == 1)
+  ZeroMem (TxtConfig, sizeof (TXT_CONFIG));
+  CpuConfig->Txt                = 0;
+  TxtConfig->SinitMemorySize    = TXT_SINIT_MEMORY_SIZE;
+  TxtConfig->TxtHeapMemorySize  = TXT_HEAP_MEMORY_SIZE;
+  TxtConfig->TxtDprMemoryBase   = 0;
+  TxtConfig->TxtDprMemorySize   = 0;
+  TxtConfig->BiosAcmBase        = 0;
+  TxtConfig->BiosAcmSize        = 0;
+  TxtConfig->McuUpdateDataAddr  = 0;
+  TxtConfig->TgaSize            = TXT_TGA_MEMORY_SIZE;
+  TxtConfig->TxtLcpPdBase       = TXT_LCP_PD_BASE;
+  TxtConfig->TxtLcpPdSize       = TXT_LCP_PD_SIZE;
+#endif
+  ///
+  /// Initialize Overclocking Data
+  ///
+  OcConfig->CoreVoltageOffset       = 0;
+  OcConfig->CoreVoltageOverride     = 0;
+  OcConfig->CoreExtraTurboVoltage   = 0;
+  OcConfig->CoreMaxOcTurboRatio     = 0;
+  OcConfig->ClrVoltageOffset        = 0;
+  OcConfig->ClrVoltageOverride      = 0;
+  OcConfig->ClrExtraTurboVoltage    = 0;
+  OcConfig->ClrMaxOcTurboRatio      = 0;
+  OcConfig->SvidVoltageOverride     = 0;
+  OcConfig->SvidEnable              = 0;
+  OcConfig->FivrFaultsEnable        = 0;
+  OcConfig->FivrEfficiencyEnable    = 0;
+  OcConfig->CoreVoltageMode         = 0;
+  OcConfig->ClrVoltageMode          = 0;
+  OcConfig->OcSupport               = 0;
+  OcConfig->BitReserved             = 0;
+
+  //
+  // Initialize Boot Guard data
+  //
+  BootGuardConfig->TpmType              = TpmTypeMax;
+  BootGuardConfig->BypassTpmInit        = FALSE;
+  BootGuardConfig->MeasuredBoot         = FALSE;
+  BootGuardConfig->BootGuardSupport     = FALSE;
+  BootGuardConfig->DisconnectAllTpms    = FALSE;
+  BootGuardConfig->ByPassTpmEventLog    = FALSE;
+
+   //AMI_CHG
+  //UpdatePeiCpuPlatformPolicy (PeiServices, CpuPlatformPolicyPpi); //(AMI_CHG)  
+  CallPeiCpuPolicyInitList(PeiServices, CpuPlatformPolicyPpi);   // (AMI_CHG+)  
+
+  ///
+  /// Update the CPU Policy Ppi Descriptor
+  ///
+  CpuPlatformPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+  CpuPlatformPolicyPpiDesc->Guid  = &gPeiCpuPlatformPolicyPpiGuid;
+  CpuPlatformPolicyPpiDesc->Ppi   = CpuPlatformPolicyPpi;
+
+  ///
+  /// Install the CPU PEI Platform Policy PPI
+  ///
+  Status = (**PeiServices).InstallPpi (PeiServices, CpuPlatformPolicyPpiDesc);
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.dxs b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.dxs
new file mode 100644
index 0000000..1e93c04
--- /dev/null
+++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.dxs
@@ -0,0 +1,41 @@
+/** @file
+  Dependency expression source file.
+
+@copyright
+  Copyright (c)  2010 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+
+**/
+
+
+//
+// Common for R8 and R9 codebase
+//
+#include "AutoGen.h"
+#include "PeimDepex.h"
+
+//
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase;
+// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version
+// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase.
+//
+#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB)
+#include "EfiDepex.h"
+#endif
+
+#include EFI_PPI_DEPENDENCY (Variable)
+
+DEPENDENCY_START
+  PEI_READ_ONLY_VARIABLE_ACCESS_PPI_GUID
+DEPENDENCY_END
diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.h b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.h
new file mode 100644
index 0000000..47a9f2b
--- /dev/null
+++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.h
@@ -0,0 +1,55 @@
+/** @file
+  Header file for the CpuPeiPolicy PEIM.
+
+@copyright
+  Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved
+  This software and associated documentation (if any) is furnished
+  under a license and may only be used or copied in accordance
+  with the terms of the license. Except as permitted by such
+  license, no part of this software or documentation may be
+  reproduced, stored in a retrieval system, or transmitted in any
+  form or by any means without the express written consent of
+  Intel Corporation.
+
+  This file contains a 'Sample Driver' and is licensed as such
+  under the terms of your license agreement with Intel or your
+  vendor.  This file may be modified by the user, subject to
+  the additional terms of the license agreement
+**/
+#ifndef _CPU_POLICY_INIT_PEI_H_
+#define _CPU_POLICY_INIT_PEI_H_
+
+///
+/// External include files do NOT need to be explicitly specified in real EDKII
+/// environment
+///
+#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000)
+#include "EdkIIGluePeim.h"
+#include "PfatDefinitions.h"
+#include EFI_PPI_PRODUCER (CpuPlatformPolicy)
+#include "CpuInitPeim.h"
+#include "CpuRegs.h"
+#include "CpuPlatformLib.h"
+#include "PowerMgmtDefinitions.h"
+#endif
+//#include "CpuPlatformPolicyUpdatePeiLib.h" //(AMI_CHG)
+
+///
+/// Functions
+///
+/**
+  This PEIM performs CPU PEI Platform Policy initialzation.
+
+  @param[in] FfsHeader               Pointer to Firmware File System file header.
+  @param[in] PeiServices             General purpose services available to every PEIM.
+
+  @retval EFI_SUCCESS             The PPI is installed and initialized.
+  @retval EFI ERRORS              The PPI is not successfully installed.
+**/
+EFI_STATUS
+EFIAPI
+CpuPolicyInitPeiEntryPoint (
+  IN EFI_FFS_FILE_HEADER *FfsHeader,
+  IN EFI_PEI_SERVICES    **PeiServices
+  );
+#endif
diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.inf b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.inf
new file mode 100644
index 0000000..1a07029
--- /dev/null
+++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyInitPei.inf
@@ -0,0 +1,87 @@
+## @file
+#  Component description file for the CpuPolicyInitPei PEIM.
+#
+#@copyright
+#  Copyright (c)  2010 - 2012 Intel Corporation. All rights reserved
+#  This software and associated documentation (if any) is furnished
+#  under a license and may only be used or copied in accordance
+#  with the terms of the license. Except as permitted by such
+#  license, no part of this software or documentation may be
+#  reproduced, stored in a retrieval system, or transmitted in any
+#  form or by any means without the express written consent of
+#  Intel Corporation.
+#
+#  This file contains a 'Sample Driver' and is licensed as such
+#  under the terms of your license agreement with Intel or your
+#  vendor.  This file may be modified by the user, subject to
+#  the additional terms of the license agreement
+#
+
+[defines]
+BASE_NAME            = CpuPolicyInitPei
+FILE_GUID            = 567F05DE-D174-48e4-A7C0-C19868A11F9B
+COMPONENT_TYPE       = PE32_PEIM
+
+[sources.common]
+  CpuPolicyInitPei.h
+  CpuPolicyInitPei.c
+#
+# Edk II Glue Driver Entry Point
+#
+  EdkIIGluePeimEntryPoint.c
+
+[includes.common]
+  .
+  $(EDK_SOURCE)/Foundation/Efi
+  $(EDK_SOURCE)/Foundation/Include
+  $(EDK_SOURCE)/Foundation/Efi/Include
+  $(EDK_SOURCE)/Foundation/Framework/Include
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include/Library
+  $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/CpuInit/Pei
+#
+# EDK II Glue Library utilizes some standard headers from EDK
+#
+  $(EFI_SOURCE)
+  $(EDK_SOURCE)/Foundation
+  $(EDK_SOURCE)/Foundation/Framework
+  $(EDK_SOURCE)/Foundation/Include/IndustryStandard
+  $(EDK_SOURCE)/Foundation/Core/Dxe
+  $(EDK_SOURCE)/Foundation/Include/Pei
+  $(EDK_SOURCE)/Foundation/Library/Pei/Include
+  $(EDK_SOURCE)/Foundation/Library/Dxe/Include
+  $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include
+  $(PLATFORM_ECP_PACKAGE)/Include
+  $(PLATFORM_ECP_PACKAGE)/Library/OpensslLib
+  $(PLATFORM_ECP_PACKAGE)/Library/PeiCryptLib
+
+[libraries.common]
+  $(PROJECT_PCH_FAMILY)PpiLib
+  EdkFrameworkPpiLib
+  EdkIIGlueBaseIoLibIntrinsic
+  EdkIIGlueBaseMemoryLib
+  EdkIIGluePeiDebugLibReportStatusCode
+  EdkIIGluePeiReportStatusCodeLib
+  EdkIIGluePeiServicesLib
+  EdkIIGluePeiMemoryAllocationLib
+  EdkPpiLib
+  CpuPpiLib
+  PlatformPolicyUpdatePeiLib
+  OpensslLib
+  PeiCryptLib
+  CpuPlatformLib
+
+[nmake.common]
+  IMAGE_ENTRY_POINT = _ModuleEntryPoint
+  DPX_SOURCE        = CpuPolicyInitPei.dxs
+#
+# Module Entry Point
+#
+  C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=CpuPolicyInitPeiEntryPoint
+  C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+                       -D __EDKII_GLUE_BASE_MEMORY_LIB__ \
+                       -D __EDKII_GLUE_PEI_DEBUG_LIB_REPORT_STATUS_CODE__ \
+                       -D __EDKII_GLUE_PEI_REPORT_STATUS_CODE_LIB__ \
+                       -D __EDKII_GLUE_PEI_SERVICES_LIB__ \
+                       -D __EDKII_GLUE_PEI_MEMORY_ALLOCATION_LIB__
diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyPei.cif b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyPei.cif
new file mode 100644
index 0000000..c241162
--- /dev/null
+++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyPei.cif
@@ -0,0 +1,13 @@
+<component>
+	name = "Cpu Policy PEI"
+	category = ModulePart
+	LocalRoot = "ReferenceCode\Haswell\SampleCode\CpuPolicyInit\Pei"
+	RefName = "Cpu Policy Pei"
+[files]
+"CpuPolicyPei.sdl"	
+"CpuPolicyPei.mak"	
+"CpuPolicyInitPei.c"	
+"CpuPolicyInitPei.h"	
+"CpuPolicyInitPei.dxs"	
+"CpuPolicyInitPei.inf"	
+<endComponent>
diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyPei.mak b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyPei.mak
new file mode 100644
index 0000000..3576f9e
--- /dev/null
+++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyPei.mak
@@ -0,0 +1,139 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2010, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+
+#**********************************************************************
+# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/Intel Haswell Cpu RC PKG/Cpu Policy PEI/CpuPolicyPei.mak 5     7/02/12 7:23a Davidhsieh $
+#
+# $Revision: 5 $
+#
+# $Date: 7/02/12 7:23a $
+#**********************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/Intel Haswell Cpu RC PKG/Cpu Policy PEI/CpuPolicyPei.mak $
+# 
+# 5     7/02/12 7:23a Davidhsieh
+# 
+# 4     5/22/12 4:36a Davidhsieh
+# Add TXT_SUPPORT_FLAG define
+# 
+# 3     5/14/12 2:20a Davidhsieh
+# 
+# 2     2/23/12 2:46a Davidhsieh
+# 
+# 1     2/07/12 3:56a Davidhsieh
+# 
+# 2     9/21/11 11:22p Davidhsieh
+# 
+# 1     5/06/11 6:06a Davidhsieh
+# First release
+#
+#**********************************************************************
+#<AMI_FHDR_START>
+#
+# Name: 
+#
+# Description: 
+#
+#<AMI_FHDR_END>
+#**********************************************************************
+EDK : CpuPolicyPei
+
+BUILD_CpuInitPei_DIR = $(BUILD_DIR)\$(CpuPolicyPei_DIR)
+
+$(BUILD_DIR)\CpuPolicyPei.mak : $(CpuPolicyPei_DIR)\CpuPolicyPei.cif $(BUILD_RULES)
+    $(CIF2MAK) $(CpuPolicyPei_DIR)\CpuPolicyPei.cif $(CIF2MAK_DEFAULTS)
+
+CpuPolicyPei : $(BUILD_DIR)\CpuPolicyPei.mak CpuPolicyPeiBin
+
+CpuPolicyPei_OBJECTS = \
+    $(BUILD_CpuInitPei_DIR)\CpuPolicyInitPei.obj
+
+CpuPolicyPei_MY_INCLUDES= \
+    $(EDK_INCLUDES) \
+    /I$(PROJECT_CPU_ROOT)\
+    /I$(PROJECT_CPU_ROOT)\Include \
+    /I$(PROJECT_CPU_ROOT)\Include\Library \
+    /I$(PROJECT_CPU_ROOT)\\Library \
+    /I$(CpuInitPei_DIR)
+
+CpuPolicyPei_DEFINES = $(MY_DEFINES)\
+    /D"__EDKII_GLUE_MODULE_ENTRY_POINT__=CpuPolicyInitPeiEntryPoint"\
+    /D TXT_SUPPORT_FLAG=1 \
+    /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \
+    /D __EDKII_GLUE_BASE_LIB__ \
+    /D __EDKII_GLUE_BASE_MEMORY_LIB__ \
+    /D __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_MM7__ \
+    /D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ \
+
+
+CpuPolicyPei_LIBS =\
+    $(PchPlatformLib)\
+    $(EfiRuntimeLib_LIB)\
+    $(INTEL_PCH_PROTOCOL_LIB)\
+    $(EFIRUNTIMELIB)\
+    $(EDKFRAMEWORKPPILIB) \
+    $(CPUIA32LIB)\
+    $(EFIPROTOCOLLIB)\
+    $(EdkIIGlueDxeReportStatusCodeLib_LIB)\
+    $(EdkIIGluePeiDebugLibReportStatusCode_LIB)\
+    $(EdkIIGlueBaseLib_LIB)\
+    $(IntelPchPpiLib_LIB)\
+    $(EdkIIGlueBaseLibIA32_LIB)\
+    $(EdkIIGluePeiHobLib_LIB) \
+    $(CpuGuidLib_LIB) \
+    $(EdkIIGluePeiServicesLib_LIB) \
+    $(EdkIIGluePeiReportStatusCodeLib_LIB) \
+    $(PEIHOBLIB) \
+    $(EdkIIGlueDxeMemoryAllocationLib_LIB)\
+    $(EdkIIGlueBaseIoLibIntrinsic_LIB)\
+    $(EdkIIGlueUefiBootServicesTableLib_LIB)\
+    $(EdkIIGlueUefiDevicePathLib_LIB)\
+    $(EdkIIGlueBasePciLibPciExpress_LIB) \
+    $(EdkIIGlueBasePciExpressLib_LIB)\
+    $(CPU_PPI_LIB)\
+    $(PchPlatformPeiLib_LIB)\
+    $(CpuPlatformLib_LIB)\
+    $(EFISCRIPTLIB)
+
+CpuPolicyPeiBin : $(CpuPolicyPei_LIBS)
+    $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\
+    /f $(BUILD_DIR)\CpuPolicyPei.mak all\
+    NAME=CpuPolicyPei\
+    MAKEFILE=$(BUILD_DIR)\CpuPolicyPei.mak \
+    "MY_INCLUDES=$(CpuPolicyPei_MY_INCLUDES)" \
+    "MY_DEFINES=$(CpuPolicyPei_DEFINES)"\
+    OBJECTS="$(CpuPolicyPei_OBJECTS)" \
+    GUID=0ac2d35d-1c77-1033-a6f8-7ca55df7d0aa\
+    ENTRY_POINT=_ModuleEntryPoint \
+    TYPE=PEIM \
+    EDKIIModule=PEIM\
+    DEPEX1=$(CpuPolicyPei_DIR)\CpuPolicyInitPei.dxs \
+    DEPEX1_TYPE=EFI_SECTION_PEI_DEPEX  \
+    COMPRESS=0
+
+#---------------------------------------------------------------------------
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2010, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
diff --git a/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyPei.sdl b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyPei.sdl
new file mode 100644
index 0000000..947bdb1
--- /dev/null
+++ b/ReferenceCode/Haswell/SampleCode/CpuPolicyInit/Pei/CpuPolicyPei.sdl
@@ -0,0 +1,58 @@
+#****************************************************************************
+#****************************************************************************
+#**                                                                        **
+#**           (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                        **
+#**                          All Rights Reserved.                          **
+#**                                                                        **
+#**           5555 Oakbrook Parkway, Suite 200, Norcross, GA 30071         **
+#**                                                                        **
+#**                          Phone (770)-246-8600                          **
+#**                                                                        **
+#****************************************************************************
+#****************************************************************************
+#****************************************************************************
+# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/Intel Haswell Cpu RC PKG/Cpu Policy PEI/CpuPolicyPei.sdl 1     2/07/12 3:56a Davidhsieh $
+#
+# $Revision: 1 $
+#
+# $Date: 2/07/12 3:56a $
+#
+#****************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/Intel Haswell Cpu RC PKG/Cpu Policy PEI/CpuPolicyPei.sdl $
+# 
+# 1     2/07/12 3:56a Davidhsieh
+# 
+# 1     5/06/11 6:06a Davidhsieh
+# First release
+# 
+#
+#****************************************************************************
+TOKEN
+	Name  = "CpuPeiPolicySupport"
+	Value  = "1"
+	Help  = "Main switch to enable Cpu Policy Pei support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Master = Yes
+End
+
+PATH
+	Name  = "CpuPolicyPei_DIR"
+End
+
+MODULE
+	Help  = "Includes CpuPeiPolicy.mak to Project"
+	File  = "CpuPolicyPei.mak"
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\CpuPolicyPei.ffs"
+	Parent  = "FV_BB"
+	InvokeOrder = AfterParent
+End
+