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Diffstat (limited to 'Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT')
9 files changed, 3145 insertions, 0 deletions
diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNVdGPU.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNVdGPU.asl new file mode 100644 index 0000000..b8f2b90 --- /dev/null +++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNVdGPU.asl @@ -0,0 +1,710 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMNVdGPU.asl 2 9/09/12 11:01p Joshchou $ +// +// $Revision: 2 $ +// +// $Date: 9/09/12 11:01p $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMNVdGPU.asl $ +// +// 2 9/09/12 11:01p Joshchou +// [TAG] None +// [Category] Improvement +// [Description] Tpv module support for sharkbay. +// [Files] OEMSSDT.mak +// OEMSSDT.asl +// OEMNVdGPU.asl +// OEMNViGPU.asl +// OEMNViGDmisc.asl +// OEMNvVentura.asl +// OEMNvGPS.asl +// OEMSSDT.cif +// +// 3 12/26/11 5:00a Alanlin +// 1.Change OperationRegion of BPCI access type from "AnyAcc" to +// "DWordAcc" for nVidia VGA. +// +// +// 1 12/12/11 9:10p Alanlin +// +// +//********************************************************************** +// PEG Endpoint PCIe Base Address. +External(EBAS) +External(NVHA) + +#ifdef OPTIMUS_DSM_GUID +Scope(PCI_SCOPE){ + + Name(OTM, "OTMACPI 2010-Mar-09 12:08:26") // OTMACPIP build time stamp. +} // end of Scope +#endif + +Scope(DGPU_SCOPE) +{ + +//<AMI_SHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: NVHM +// +// Description: Nvidia NVHG (dGPU) OperationRegion +// OpRegion address (NVHA)is defined in IDG Nvs OpRegion +// +//------------------------------------------------------------------------- +//<AMI_SHDR_END> + OperationRegion(NVHM,SystemMemory, NVHA, 0x20400) + Field(NVHM, DWordAcc, NoLock, Preserve) + { + // OpRegion Header + + NVSG, 0x80, // (000h) Signature-"NVSG". + NVSZ, 0x20, // (010h) OpRegion Size in KB. + NVVR, 0x20, // (014h) OpRegion Version. + + // NVHG data + + NVHO, 0x20, // (018h)NVHM opregion address + RVBS, 0x20, // (01Ch)NVIDIA VBIOS image size + // (020h)for _ROM + RBF1, 0x80000, // 0x10000 bytes in bits + RBF2, 0x80000, // 0x10000 bytes in bits + MXML, 0x20, // Mxm3 buffer length +#if MXM30_SUPPORT + MXM3, MXM_ROM_MAX_SIZE_bits // MXM 3.0 Data buffer +#else + MXM3, 0x640 // MXM 3.0 Data buffer +#endif + + } + + Name(OPCE, 2) // Optimus Power-Control ENABLE + // 2: The platform should not power down the GPU subsystem + // in the _PS3 method (Default) + // 3: The platform should power down the GPU subsystem + // at the end of the _PS3 ACPI method + + Name(DGPS, Zero)// Power State. dummy control field. Can be a GPIO in EC or PCH + +#ifdef OPTIMUS_DSM_GUID + +//If dGPU power control is available.... + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: _PSC +// +// Description: Curent dGPU power state, 0-D0, 3-D3, etc. +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Name(_PSC, Zero) + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: _PS0 +// +// Description: dGPU power ON control method +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + + Method(_PS0, 0, NotSerialized) + { + P8DB(0xB0, OPCE, 2000) + Store(Zero, _PSC) + If(LNotEqual(DGPS, Zero)) + { + _ON() // with Optimus w/a + Store(Zero, DGPS) + } + } + + Method(_PS1, 0x0, NotSerialized) + { + Store(One, _PSC) + } + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: _PS3 +// +// Description: dGPU power OFF control method +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + + Method(_PS3, 0, NotSerialized) + { + P8DB(0xB3, OPCE, 2000) + If(LEqual(OPCE, 0x3)) + { + If(LEqual(DGPS, Zero)) + { + _OFF() // w Optimus w/a + Store(One, DGPS) + } + Store(0x2, OPCE) // Reset NV GPU power down flag + } + Store(0x3, _PSC) + } + + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: _STA +// +// Description: dGPU power status. +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Method(_STA,0x0) + { + Return(0x0F) // Always return DGPU is powered-ON + } + +#endif // OPTIMUS_DSM_GUID + +#if HYBRID_DSM_GUID || MXM_DSM_GUID +// NON-OPTIMUS mode - MUXed + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: _IRC +// +// Description: In-rush current +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> +// Name(_IRC, 0) + Method(_IRC,0,Serialized) + { + Return(0x00) + } + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: _ON +// +// Description: dGPU power ON control method +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Method(_ON,0,Serialized) + { + SGON() // OEM Mxm Power On + + //Ask OS to do a PnP rescan + Notify(PEG_SCOPE,0) + } + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: _OFF +// +// Description: dGPU power OFF control method +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Method(_OFF,0,Serialized) + { + SGOF() // OEM Mxm Power On + + //Ask OS to do a PnP rescan + Notify(PEG_SCOPE,0) + } + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: _STA +// +// Description: Returns curent dGPU power/presence state +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Method(_STA,0,Serialized) + { + Return(SGST()) // OEM Mxm Power status + } + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: MXMX +// +// Description: Display DDC Mux Control +// +// Input: +// Arg0: Get/Set DDC/Aux Mux State +// 0- Acquire DDC/Aux Mux on this GPU +// 1- Release Mux from this GPU +// 2- Get Mux state +// +// Output: +// 0, Not Acquired. +// if Arg0 = 0 or 1, Non-Zero return indicates success acquiring MUX +// (and MUX has switched to this output) +// if Arg0 = 2, Non-Zero return indicates MUX is currently set to this output +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Method (MXMX, 1, Serialized) + { + P8DB(0x99, Arg0, 2000) + + If (LEqual (Arg0, 0)) + { + + //Acquire DDC/AUX mux + // No mutex implemented. No need to acquire mutex. + // Set mux to dGPU +// SGPO(DSEL, 1)// dGPU_SELECT# + SGPO(ESEL, 1)// use EDID_SELECT# as Mutex flag + Return(1) + } + + If (LEqual (Arg0, 1)) + { + + //Release DDC/AUX mux + // No mutex implemented. No need to release mutex. + // 2-way mux. Hence no need to do anything + Return(0x1) + + } + + If (LEqual (Arg0, 2)) + { + + //Get ddc/aux mux status for dGPU + Return(SGPI(ESEL)) + } + + Return(0x0) // mutex not acquired + } + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: MXDS +// +// Description: Display output MUX control +// +// Input: +// Arg0: +// 0 - Get Mux state +// 1 - Set Display to active on this GPU +// 2 - Set Backlight control to active on this GPU +// 3 - Set Display & Backlight to active on this GPU +// +// Output: +// If Arg0 = 0, Error = Display is not MUXed +// Else return value of the state of the MUX +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Method(MXDS, 1, Serialized) + { + P8DB(0x9A, Arg0, 2000) + + If(LEqual (Arg0, 0)) + { + //Get display mux status for dGPU + return(SGPI(DSEL)) + } else +// If(LOr(LEqual (Arg0, 1), LEqual (Arg0, 2))) + { + //Set display mux to dgpu + SGPO(DSEL, 1) // dGPU_SELECT + SGPO(PSEL, 1) // dGPU_PWM_SELECT + } + + Return (0) + } +#endif // MXM && HYBRID + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: _ROM +// +// Description: Video ROM data buffer +// +// Input: +// Arg0: Integer Offset of the graphics device ROM data +// Arg1: Integer Size of the buffer to fill in (up to 4K) +// +// Output: +// Buffer Buffer of requested video ROM bytes +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Method(_ROM,2) + { + + Store (Arg0, Local0) + Store (Arg1, Local1) + + P8DB(0x44, Local1, 100) +// CreateWordField (RBF1, 2, RVBS) // Vbios image size +// ShiftLeft(And(RVBS,0xff), 9, RVBS) // size in Bytes (* 512) + + If (LGreater (Local1, 0x1000)) + { + Store (0x1000, Local1) + } + If (LGreater (Local0, 0x20000)) + { + Return(Buffer(Local1){0}) + } +// If (LGreater (Local0, RVBS)) +// { +// Return(Buffer(Local1){0}) +// } +//// If (LGreater (Add (Local0, Local1), RVBS)) +//// { +//// Store (0x00, Local0) +//// } + + Multiply (Local1, 0x08, Local3) + Name (ROM1, Buffer (0x10000) {0}) + Name (ROM2, Buffer (Local1) {0}) + + If(LLess(Local0,0x10000)) + { + Store (RBF1, ROM1) + } + Else + { + Subtract(Local0,0x10000,Local0) + Store (RBF2, ROM1) + } + + Multiply (Local0, 0x08, Local2) + CreateField (ROM1, Local2, Local3, TMPB) + Store (TMPB, ROM2) + Return (ROM2) + } + +// +// Check for Nvidia _DSM UUIDs +// +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: HDSM +// +// Description: Device Specific Methods for Hybrid dGPU (may be invoked from iGD as well) +// Implements Mxm and SG specific callback functions +// +// Input: +// Arg0: UUID Unique function identifier. +// nVidia +// MXM dGPU GUID :9D95A0A0-0060-4D48-B34D-7E5FEA129FD4 +// +// Arg1: Integer Revision Level +// Arg2: Integer Function Index (0 = Return Supported Functions) +// Arg3: Package Parameters +// +// Output: +// Sub-function 0 and unsupported function calls always returns a buffer. +// Other subfunctions may return a buffer or a package as defined in the function. +// When a single DWord is returned the following values have special meaning, +// controlled by reserved Bit31 as follows: +// MXM_ERROR_SUCCESS 0x00000000 Success +// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code +// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not +// supported by this system +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Method(HDSM, 4, SERIALIZED) + { + +#ifdef MXM_DSM_GUID + + If(LEqual(Arg0, ToUUID("4004A400-917D-4cf2-B89C-79B62FD55665"))) + { + + P8DB(0xEE, Arg2, 1000) + + Switch(ToInteger(Arg2)) + { + // + // Function 0: MXM_FUNC_MXSS + // + case (0) + { + //Sub-Functions 0,16,24 are supported + Return(ToBuffer(0x01010001)) + } + + // + // Function 24: MXM_FUNC_MXMI + // + case (24) + { + Return(ToBuffer(0x300)) // MXM 1.101 defines revision as 0x300 + // Return(ToBuffer(0x30)) // MXM 1.101 defines revision as 0x300 + } + + // + // Function 16: MXM_FUNC_MXMS + // + case (16) + { + If(LEqual (Arg1, 0x300)) // MXM 1.101 defines revision as 0x300 + { +#if MXM30_SUPPORT + // calculate true length of MXM block + CreateWordField(MXM3, 6, MXLN) + Add(MXLN, 8, Local0) // Add length of MXM header + CreateField(MXM3, 0, Local0, MXM) + Return(ToBuffer(MXM)) +#else + // ElkCreek 4 Mxm data structure + Name(MXM3, Buffer() + { + 0x4d, 0x58, 0x4d, 0x5f, 0x03, 0x00, 0x5d, 0x00, + 0x30, 0x11, 0xb8, 0xff, 0xf9, 0x3e, 0x00, 0x00, + 0x00, 0x00, 0x0a, 0xf0, 0xf9, 0x3e, 0x00, 0x00, + 0x60, 0xe9, 0xd0, 0xfe, 0xf9, 0x3e, 0x00, 0x00, + 0x60, 0x6a, 0xda, 0xfe, 0xf9, 0x3e, 0x00, 0x00, + 0x20, 0x2b, 0xe2, 0xfe, 0xf9, 0x3e, 0x00, 0x00, + 0x60, 0x6c, 0xea, 0xfe, 0xf9, 0x3e, 0x00, 0x00, + 0x20, 0x6a, 0xda, 0xfe, 0xf9, 0x3e, 0x00, 0x00, + 0x20, 0x6c, 0xea, 0xfe, 0xf9, 0x3e, 0x00, 0x00, + 0x01, 0x90, 0x01, 0x00, 0x03, 0x00, 0x90, 0x01, + 0x13, 0x00, 0x90, 0x01, 0xe5, 0x0d, 0x01, 0x01, + 0x01, 0x00, 0x00, 0x00, 0xe5, 0x0d, 0x01, 0x03, + 0x00, 0x90, 0xd8, 0x09, 0x11, 0x0a + }) + Return(MXM3) +#endif + } + } + } // switch + Return(0x80000002) //MXM_ERROR_UNSUPPORTED - FunctionCode or SubfunctionCode not supported + } // "4004A400-917D-4cf2-B89C-79B62FD55665" + +#endif // MXM_DSM_GUID + + Return (0x80000001) //MXM_ERROR_UNSPECIFIED + } + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: _DSM Device Specific Method for dGPU device +// +// Description: Implement Mxm and SG specific callback functions +// +// Input: +// Arg0: UUID Unique function identifier. +// MXM dGPU GUID :9D95A0A0-0060-4D48-B34D-7E5FEA129FD4 +// NBCI GUID :D4A50B75-65C7-46F7-BfB7-41514CEA0244 +// Ventura GUID :95DB88FD-940A-4253-A446-70CE0504AEDF +// Optimus DSM_GUID :A486D8F8-0BDA-471B-A72B-6042A6B5BEE0 +// +// Arg1: Integer Revision Level +// Arg2: Integer Function Index (0 = Return Supported Functions) +// Arg3: Package Parameters +// +// Output: +// Sub-function 0 and unsupported function calls always returns a buffer. +// Other subfunctions may return a buffer or a package as defined in the function. +// When a single DWord is returned the following values have special meaning, +// controlled by reserved Bit31 as follows: +// MXM_ERROR_SUCCESS 0x00000000 Success +// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code +// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not +// supported by this system +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Method(_DSM,4,SERIALIZED) + { + CreateByteField (Arg0, 3, GUID) + P8DB(0xDD, GUID, 1000) + // + // Check for Nvidia _DSM UUIDs + // + // common _DSM for dGPU and iGPU: NBCI, SG DSM, Ventura + return(IGPU_SCOPE.HDSM(Arg0, Arg1, Arg2, Arg3)) + } + + +#ifdef OPTIMUS_DSM_GUID +/////////////////////////////////////////////////////////////////// +// Nvidia Optimus driver w/a. Save PCI context of PEG Video card +/////////////////////////////////////////////////////////////////// +// PEG Endpoint PCIe Base Address. + OperationRegion (BPCI, SystemMemory, EBAS, 0x1000) + Field (BPCI, DWordAcc, NoLock, Preserve) + { +// VGAR, 2048, + Offset(0x04), + //PCIC, 16, + PCIC, 32, + + Offset(0x10), + GMM1, 32, + + Offset(0x14), + GMM2, 32, + + //Offset(0x18), + //GMB1, 32, + + Offset(0x1C), + GMM3, 32, + + Offset(0x24), + GIO1, 32, + + Offset(0x3C), + //GIRQ, 8, + GIRQ, 32, + + Offset(0x40), + SID, 32, + +// Offset(0x88), +// , 5, +// RETR, 1, + + //Offset(0x114), + //VC0R, 32, + Offset(0x488), + , 25, + NHDM, 1 // HDA Enable bit. + } + +// Create the dGPU PCI Configuration data buffer for dGPU save/restore resources + Name(BUFF, Buffer(32){}) // Create dGPU PCI Configuration data buffer as BUFF + CreateDWordField(BUFF, 0x00, BUF1) // + CreateDWordField(BUFF, 0x01, BUF2) // + CreateDWordField(BUFF, 0x02, BUF3) // + CreateDWordField(BUFF, 0x03, BUF4) // + CreateDWordField(BUFF, 0x04, BUF5) // + CreateDWordField(BUFF, 0x05, BUF6) // + CreateDWordField(BUFF, 0x06, BUF7) // + CreateDWordField(BUFF, 0x07, BUF8) // + +// TEST !!! TEST !!! TEST !!!! +// NvOptimus should not be be using _ON and _OFF methods for power cycling +// Used here for testing with Intel ElkCreek Mxm interposer +// + Name(CTXT, Zero)// Save Context flag + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: _ON +// +// Description: Optimus w/a for before dGPU _ON +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + + Method(_ON, 0, Serialized) + { + P8DB(0x01, 0x11, 2000) + + // OEM Mxm Power status + SGON() + +// Nvidia Optimus driver w/a. Restore saved PCI context of PEG Video card +// Store(BUF8,VC0R) + + Store(BUF1,PCIC) + Store(BUF2,GMM1) + Store(BUF3,GMM2) + Store(BUF4,GMM3) + Store(BUF5,GIO1) + Store(BUF6,GIRQ) + Store(BUF7,SID) + +// Store(1, RETR) // retrain PCI-E bus +//+< +// doesn't look like we need delay here... +// Sleep(0x64) + + Store(SWSMI_NVOEM_CMOS_R, SSMP) // Read CMOS:AudioCodec flag to AcpiNvs:SGFL +// Clear HDA enable bit if flag not set + if(LEqual(And(SGFL, 2), 0)) + { + Store(0, NHDM) + } + + } + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: _OFF +// +// Description: Optimus w/a before dGPU _OFF +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + + Method(_OFF, 0, Serialized) + { + + P8DB(0x0F, 0xFF, 2000) + +// store PCI context only once + If(LEqual(CTXT, Zero)) + { +// Nvidia Optimus driver w/a. Save PCI context of PEG Video card +// Store(VGAR, VGAB) +//+>save dGPU resources + Store(PCIC,BUF1) + Store(GMM1,BUF2) + Store(GMM2,BUF3) + Store(GMM3,BUF4) + Store(GIO1,BUF5) + Store(GIRQ,BUF6) + Store(SID,BUF7) +// Store(VC0R,BUF8) +//+< + Store(1, CTXT) + } + SGOF() + + } +#endif +} // end Scope(DGPU_SCOPE) +//********************************************************************** +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//**********************************************************************
\ No newline at end of file diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNViGDmisc.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNViGDmisc.asl new file mode 100644 index 0000000..6e3ee2e --- /dev/null +++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNViGDmisc.asl @@ -0,0 +1,241 @@ +//**************************************************************************** +//**************************************************************************** +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone (770)-246-8600 ** +//** ** +//**************************************************************************** +//**************************************************************************** +//**************************************************************************** +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMNViGDmisc.asl 2 9/09/12 11:01p Joshchou $ +// +// $Revision: 2 $ +// +// $Date: 9/09/12 11:01p $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMNViGDmisc.asl $ +// +// 2 9/09/12 11:01p Joshchou +// [TAG] None +// [Category] Improvement +// [Description] Tpv module support for sharkbay. +// [Files] OEMSSDT.mak +// OEMSSDT.asl +// OEMNVdGPU.asl +// OEMNViGPU.asl +// OEMNViGDmisc.asl +// OEMNvVentura.asl +// OEMNvGPS.asl +// OEMSSDT.cif +// +// 1 12/12/11 9:10p Alanlin +// +// +// +//********************************************************************** + +External(DSEN) +External(IGPU_SCOPE.CDCK) +External(DGPU_SCOPE.DD02) +External(IGPU_SCOPE.IDAB, MethodObj) + +//Do not remove this function. +Method(IDAB, 0, Serialized) +{ + If (CondRefOf(IGPU_SCOPE.IDAB)) + { + IGPU_SCOPE.IDAB() + } +} + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: HGAS +// +// Description: HG Adaptor select, notify +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> +Method(HGAS) //HG Adaptor select +{ + //Stateless button/Hotkey supporting 3 states - Power Saver, Adaptive and Perf + + Increment(IGPU_SCOPE.GPSS) + Mod(IGPU_SCOPE.GPSS, 3, IGPU_SCOPE.GPSS) + + Store(1,IGPU_SCOPE.GPPO) + Store(1,IGPU_SCOPE.SGNC) //indicate 'policy select' change + + Notify(IGPU_SCOPE, 0xD0) + Notify(PCI_SCOPE.WMI1, 0xD0) // Mirror Notify on WMI1 + +} + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: HBRT +// +// Description: Send backlight notifications to the DGPU LFP device +// This is required for Win7 and is backward compatible with Vista +// +// Input: Arg0 - 4 - Brightnes Down, 3- Up +//------------------------------------------------------------------------- +//<AMI_PHDR_END> +Method(HBRT, 1 , Serialized) +{ + Store(Arg0,IGPU_SCOPE.DACE) + + If(And(4,DSEN)) //Note: DSEN variable is expected to be set by IGD miniport only. + { + If(LEqual(Arg0,4)) + { + Notify(DGPU_SCOPE.DD02,0x87) //Note: DD02 is hardcoded as the LFP device in intelgfx.asl + } + If(LEqual(Arg0,3)) + { + Notify(DGPU_SCOPE.DD02,0x86) + } + } + +} + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: HPFS +// +// Description: Panel Fitting Hot Key +// +// Input: None +//------------------------------------------------------------------------- +//<AMI_PHDR_END> +Method(HPFS, 0, Serialized) //Panel Fitting Hot Key +{ + // + // HG Handling of Panel Fitting Switch + // + + Store(5,IGPU_SCOPE.DACE) // Indicate display scaling hot key event + Store(2,IGPU_SCOPE.SGNC) // Indicate platpolicy change + + // + // Expansion Mode toggling + // + Increment(IGPU_SCOPE.GPSP) + Mod(IGPU_SCOPE.GPSP, 4 , IGPU_SCOPE.GPSP) + + Notify(IGPU_SCOPE,0xDC) + +} + + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: HNOT +// +// Description: Notification handler for Switchable graphics. Called from GNOT() +// +// Input: Arg0 = Current event type: +// 1 = display switch +// 2 = lid +// 3 = dock (!!!!!Acpi ref code, Method(GDCK)sends 4 for Dock notifications ) +//------------------------------------------------------------------------- +//<AMI_PHDR_END> +Method (HNOT, 1, Serialized) +{ + Switch(ToInteger(Arg0)) + { + case(1) //Display Switch event + { + Store(3,IGPU_SCOPE.SGNC) // indicate 'Displaystatus' change + Store(1,IGPU_SCOPE.DACE) + Notify(IGPU_SCOPE, 0x80) + Notify(PCI_SCOPE.WMI1, 0x80) // Mirror Notify on WMI1 + } + + case (2) //Lid switch event + { + //Note: NV clarified that only LDES needs to be set + Store(1,IGPU_SCOPE.LDES) + Notify(IGPU_SCOPE, 0xDB) + Notify(PCI_SCOPE.WMI1, 0xDB) // Mirror Notify on WMI1 + } +// case (3) //Dock event + case (4) //Dock event (!!!Acpi ref code, Method(GDCK)sends 4 for Dock notifications) + { + Store(IGPU_SCOPE.CDCK, IGPU_SCOPE.DKST) // Store the current dock state + Notify(IGPU_SCOPE, 0x81) + Notify(PCI_SCOPE.WMI1, 0x81) // Mirror Notify on WMI1 + } + + Default + { + Notify(IGPU_SCOPE,0x80) + } + + } + +} + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: CHPS +// +// Description: Shows current Hybrid Policy status on Port80 header +// Adaptive -> 1, Save power -> 2 and High performance -> 3 +// +// Input: None +//------------------------------------------------------------------------- +//<AMI_PHDR_END> +Method(CHPS) +{ + P8DB(0xEC, Add(IGPU_SCOPE.GPSS, 1), 2000) +} + + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: HDOS +// +// Description: Check if the _DOS flag was set during the hot key handling +// +// Input: None +//------------------------------------------------------------------------- +//<AMI_PHDR_END> +Method(HDOS, 0, Serialized) +{ + If(LEqual(IGPU_SCOPE.DOSF,1)) + { + Store(1,IGPU_SCOPE.SGNC) // indicate 'policy select' change + Notify(IGPU_SCOPE,0xD0) + Notify(PCI_SCOPE.WMI1, 0xD0) // Mirror Notify on WMI1 + Store(0, IGPU_SCOPE.DOSF) // Clear the DOSF + } +} +//********************************************************************** +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//**********************************************************************
\ No newline at end of file diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNViGPU.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNViGPU.asl new file mode 100644 index 0000000..ae569d1 --- /dev/null +++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNViGPU.asl @@ -0,0 +1,963 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMNViGPU.asl 2 9/09/12 11:01p Joshchou $ +// +// $Revision: 2 $ +// +// $Date: 9/09/12 11:01p $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMNViGPU.asl $ +// +// 2 9/09/12 11:01p Joshchou +// [TAG] None +// [Category] Improvement +// [Description] Tpv module support for sharkbay. +// [Files] OEMSSDT.mak +// OEMSSDT.asl +// OEMNVdGPU.asl +// OEMNViGPU.asl +// OEMNViGDmisc.asl +// OEMNvVentura.asl +// OEMNvGPS.asl +// OEMSSDT.cif +// +// 1 12/12/11 9:10p Alanlin +// +// +//********************************************************************** +External(NVGA) + +External(NXD1) +External(NXD2) +External(NXD3) +External(NXD4) +External(NXD5) +External(NXD6) +External(NXD7) +External(NXD8) +External(DID1) +External(DID2) +External(DID3) +External(DID4) +External(DID5) +External(DID6) +External(DID7) +External(DID8) + +Scope (IGPU_SCOPE) +{ + + Method(_INI,0) + { + //DIDx values have been changed in MxmAcpiTables.c + //Port - D to be used for eDP only and not as DFP. Hence generating a new toggle list + Store(DID1, Index(TLPK,0)) // CRT + Store(DID2, Index(TLPK,2)) // LFP + Store(DID3, Index(TLPK,4)) // DP_B + Store(DID4, Index(TLPK,6)) // HDMI_B + Store(DID5, Index(TLPK,8)) // HDMI_C + Store(DID6, Index(TLPK,10)) // DP_D + Store(DID7, Index(TLPK,12)) // HDMI_D + Store(DID2, Index(TLPK,14)) // LFP+CRT + Store(DID1, Index(TLPK,15)) + Store(DID2, Index(TLPK,17)) // LFP+DP_B + Store(DID3, Index(TLPK,18)) + Store(DID2, Index(TLPK,20)) // LFP+HDMI_B + Store(DID4, Index(TLPK,21)) + Store(DID2, Index(TLPK,23)) // LFP+HDMI_C + Store(DID5, Index(TLPK,24)) + Store(DID2, Index(TLPK,26)) // LFP+DP_D + Store(DID6, Index(TLPK,27)) + Store(DID2, Index(TLPK,29)) // LFP+HDMI_D + Store(DID7, Index(TLPK,30)) + } + +// +// MXMX method is dupplicated under GFX0 scope in INTELGFX.ASL +// need to replace it with method in this file. +// +#ifndef OPTIMUS_DSM_GUID +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: MXMX +// +// Description: Display DDC Mux Control +// +// Input: +// Arg0: Get/Set DDC/Aux Mux State +// 0- Acquire DDC/Aux Mux on this GPU +// 1- Release Mux from this GPU +// 2- Get Mux state +// +// Output: +// 0, Not Acquired. +// if Arg0 = 0 or 1, Non-Zero return indicates success acquiring MUX +// (and MUX has switched to this output) +// if Arg0 = 2, Non-Zero return indicates MUX is currently set to this output +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Method (MXMX, 1, Serialized) + { + P8DB(0x77, Arg0, 2000) + + If (LEqual (Arg0, 0)) + { + //Acquire DDC/AUX mux + // No mutex implemented. No need to acquire mutex. + // Set mux to iGPU + DGPU_SCOPE.SGPO(DSEL, 0) + DGPU_SCOPE.SGPO(ESEL, 0) // use edid_select# as mutex flag + + Return(0x1) + } + + If (LEqual (Arg0, 1)) + { + //Release DDC/AUX mux + // No mutex implemented. No need to release mutex. + // 2-way mux. Hence no need to do anything + Return(0x1) + } + + If (LEqual (Arg0, 2)) + { + + //Get ddc/aux mux status for iGPU + Return(LNot(DGPU_SCOPE.SGPI(ESEL))) + } + + Return(0x0) // mutex not acquired + } + + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: MXDS +// +// Description: Display output MUX control +// +// Input: +// Arg0: +// 0 - Get Mux state +// 1 - Set Display to active on this GPU +// 2 - Set Backlight control to active on this GPU +// 3 - Set Display & Backlight to active on this GPU +// +// Output: +// If Arg0 = 0, Error = Display is not MUXed +// Else return value of the state of the MUX +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Method(MXDS, 1, Serialized) + { + P8DB(0x7A, Arg0, 2000) + + If(LEqual (Arg0, 0)) + { + //Get display mux status for iGPU + return(LNot(DGPU_SCOPE.SGPI(DSEL))) + } else +// If(LOr(LEqual (Arg0, 1), LEqual (Arg0, 2))) + { + //Set display mux to igpu + DGPU_SCOPE.SGPO(DSEL, 0) + DGPU_SCOPE.SGPO(PSEL, 0) + } + + Return (0) + } + +#endif // OPTIMUS_DSM_GUID + +//<AMI_SHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: NVIG +// +// Description: Nvidia NVIG (iGPU) OperationRegion +// +//------------------------------------------------------------------------- +//<AMI_SHDR_END> + OperationRegion(NVIG,SystemMemory,NVGA,0x400) + Field(NVIG, DWordAcc, NoLock, Preserve) + { + // OpRegion Header + + NISG, 0x80, // (000h) Signature-"NVSG-IGD-DSM-VAR". + NISZ, 0x20, // (010h) OpRegion Size in KB. + NIVR, 0x20, // (014h) OpRegion Version. + + // OpRegion Data + GPSS, 0x20, // Policy Selection Switch Status (Policy selection) + GACD, 0x10, // Active Displays + GATD, 0x10, // Attached Displays + LDES, 0x08, // Lid Event State + DKST, 0x08, // Dock State + DACE, 0x08, // Display ACPI event + DHPE, 0x08, // Display Hot-Plug Event + DHPS, 0x08, // Display Hot-Plug Status + SGNC, 0x08, // Notify Code (Cause of Notify(..,0xD0)) + GPPO, 0x08, // Policy Override (Temporary ASL variables) + USPM, 0x08, // Update Scaling Preference Mask (Temporary ASL variable) + GPSP, 0x08, // Panel Scaling Preference + TLSN, 0x08, // Toggle List Sequence Number + DOSF, 0x08, // Flag for _DOS + ELCL, 0x10, // Endpoint Link Contol Register Value + } + + // Toggle List Package + Name(TLPK,Package() + { + //fix this toggle list. DIDx values have been changed in MxmAcpiTables.c + 0xFFFFFFFF, 0x2C, // CRT + 0xFFFFFFFF, 0x2C, // LFP + 0xFFFFFFFF, 0x2C, // DP_B + 0xFFFFFFFF, 0x2C, // HDMI_B + 0xFFFFFFFF, 0x2C, // HDMI_C + 0xFFFFFFFF, 0x2C, // DP_D + 0xFFFFFFFF, 0x2C, // HDMI_D + 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+CRT + 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+DP_B + 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+HDMI_B + 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+HDMI_C + 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+DP_D + 0xFFFFFFFF, 0xFFFFFFFF, 0x2C, // LFP+HDMI_D + + }) + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: INDL +// +// Description: Initialize Global Next active device list. +// +// Input: None +// +// Output: None +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Method(INDL, 0, Serialized) + { + Store(0, NXD1) + Store(0, NXD2) + Store(0, NXD3) + Store(0, NXD4) + Store(0, NXD5) + Store(0, NXD6) + Store(0, NXD7) + Store(0, NXD8) + } + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: SND1 +// +// Description: Set Next active device for a single device +// +// Input: +// Arg0 : Device ID of the device that's to be set as next active device. +// +// Output: None +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Method(SND1, 1, Serialized) + { + If(LEqual(Arg0, DID1)) + { + Store(1, NXD1) + } + If(LEqual(Arg0, DID2)) + { + Store(1, NXD2) + } + If(LEqual(Arg0, DID3)) + { + Store(1, NXD3) + } + If(LEqual(Arg0, DID4)) + { + Store(1, NXD4) + } + If(LEqual(Arg0, DID5)) + { + Store(1, NXD5) + } + If(LEqual(Arg0, DID6)) + { + Store(1, NXD6) + } + If(LEqual(Arg0, DID7)) + { + Store(1, NXD7) + } + If(LEqual(Arg0, DID8)) + { + Store(1, NXD8) + } + + } + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: SNXD +// +// Description: Set Next active device +// +// Input: +// Arg0 TLSN +// +// Output: None +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Method(SNXD, 1, Serialized) + { + INDL() + + // + // Locate the toggle table entry corresponding to TLSN value + // Toggle list entries are separated by 0x2C. + // + + Store(1, Local0) // Local0 to track entries. Point to the first entry (TLSN starts from 1) + Store(0, Local1) // Local1 to track elements inside the TLPK package (ACPI IDs and '0x2C') + + while(LLess(Local0, Arg0)) // TLSN start from 1!! + { + if(LEqual(DeRefOf(Index(TLPK,Local1)), 0x2C)) + { + Increment(Local0) + } + Increment(Local1) + + } + + SND1(DeRefOf(Index(TLPK, Local1))) // 1 st ACPI ID in the entry corresponding to TLSN + Increment(Local1) + if(LNotEqual(DeRefOf(Index(TLPK,Local1)), 0x2C)) // Check for separator + { + SND1(DeRefOf(Index(TLPK, Local1))) // 2 nd ACPI ID in the entry corresponding to TLSN + } + + } + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: CTOI +// +// Description: Convert _DOD indices-> MDTL index +// +// Input: +// Arg 0 is the currently active display list +// +// Output: None +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Method(CTOI,1, Serialized) + { + Switch(ToInteger(Arg0)) //Arg 0 is the currently active display list + { + //_DOD indices-> MDTL index + case(0x1) {Return(1)} //CRT + case(0x2) {Return(2)} //LFP + case(0x4) {Return(3)} //DP_B + case(0x8) {Return(4)} //HDMI_B + case(0x10) {Return(5)} //HDMI_C + case(0x20) {Return(6)} //DP_D + case(0x40) {Return(7)} //HDMI_D + case(0x3) {Return(8)} //LFP+CRT + case(0x6) {Return(9)} //LFP+DP_B + case(0xA) {Return(10)} //LFP+HDMI_B + case(0x12) {Return(11)} //LFP+HDMI_C + case(0x22) {Return(12)} //LFP+DP_D + case(0x42) {Return(13)} //LFP+HDMI_D + Default {Return(1)} + } + } + +// Check for Nvidia _DSM UUIDs +// +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: HDSM +// +// Description: Device Specific Methods for Hybrid GPU (may be invoked from dGP and iGD) +// Implements Mxm and SG specific callback functions +// +// Input: +// Arg0: UUID Unique function identifier. +// nVidia +// SG dGPU GUID :9D95A0A0-0060-4D48-B34D-7E5FEA129FD4 +// NBCI GUID :D4A50B75-65C7-46F7-BfB7-41514CEA0244 +// Ventura GUID :95DB88FD-940A-4253-A446-70CE0504AEDF +// Optimus DSM_GUID :A486D8F8-0BDA-471B-A72B-6042A6B5BEE0 +// +// Arg1: Integer Revision Level +// Arg2: Integer Function Index (0 = Return Supported Functions) +// Arg3: Package Parameters +// +// Output: +// Sub-function 0 and unsupported function calls always returns a buffer. +// Other subfunctions may return a buffer or a package as defined in the function. +// When a single DWord is returned the following values have special meaning, +// controlled by reserved Bit31 as follows: +// MXM_ERROR_SUCCESS 0x00000000 Success +// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code +// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not +// supported by this system +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Method(HDSM, 4, SERIALIZED) + { + +#if NV_VENTURA_SUPPORT == 1 + //SPB_DSM_GUID {95DB88FD-940A-4253-A446-70CE0504AEDF} +//x if(CMPB(Arg0, Buffer(){0xFD,0x88,0xDB,0x95,0x0A,0x94,0x53,0x42,0xA4,0x46,0x70,0xCE,0x05,0x04,0xAE,0xDF})) + If(LEqual(Arg0, ToUUID("95DB88FD-940A-4253-A446-70CE0504AEDF"))) + { + return ( DGPU_SCOPE.SPB(Arg0, Arg1, Arg2, Arg3)) + } +#endif + +#if NV_GPS_SUPPORT == 1 + //SPB_DSM_GUID {A3132D01-8CDA-49BA-A52E-BC9D46DF6B81} +//x if(CMPB(Arg0, Buffer(){0x01, 0x2D, 0x13, 0xA3, 0xDA, 0x8C, 0xBA, 0x49,0xA5, 0x2E, 0xBC, 0x9D, 0x46, 0xDF, 0x6B, 0x81})) + If(LEqual(Arg0, ToUUID("A3132D01-8CDA-49BA-A52E-BC9D46DF6B81"))) + { + return ( DGPU_SCOPE.GPS(Arg0, Arg1, Arg2, Arg3)) + } +#endif + +#if HYBRID_DSM_GUID || NBCI_DSM_GUID || OPTIMUS_DSM_GUID + + Name(SGCI, 0) // SG Common Interface + Name(NBCI, 0) // Notebok Common Interface + Name(OPCI, 0) // Optimus Common Interface + Name(BUFF, 0) // Buff Parameter + +// Hybrid Graphics Methods supported only if MUXed mode is selected +#ifdef HYBRID_DSM_GUID + If(LEqual(Arg0, ToUUID("9D95A0A0-0060-4D48-B34D-7E5FEA129FD4"))) + { + Store(1, SGCI) + } +#endif +// NBCI Methods can be querried in botd MUXed and MUXless modes +#ifdef NBCI_DSM_GUID + if(LEqual(Arg0, ToUUID("D4A50B75-65C7-46F7-BfB7-41514CEA0244"))) + { + Store(1, NBCI) + } +#endif +// Optimus Methods can be querried in botd MUXed and MUXless modes +#ifdef OPTIMUS_DSM_GUID + If(LEqual(Arg0, ToUUID("A486D8F8-0BDA-471B-A72B-6042A6B5BEE0"))) + { + Store(1, OPCI) + } +#endif + + If(LOr(OPCI, LOr( SGCI, NBCI)) ) + { + + P8DB(0xEE, Arg2, 1000) + + if(OPCI) { + if(LNotEqual(Arg1, 0x100)) { + Return(0x80000002) + } + } + else { // NBCI & SGCI + If(LNotEqual(Arg1,0x0102)) + { + Return(0x80000002) + } + } + // + // Function 0: NVSG_FUNC_SUPPORT - Return Supported Functions + // + // Returns: + // SGCI: Functions 0-6,18 are supported + // NBCI: Functions 0,4-6,18 are supported + // OPCI: Functions 0,5,6,12,13,16,17,26,27 + // + If(LEqual(Arg2,0)) + { + if(SGCI){ + Return(Buffer(){0x7F, 0x00, 0x04, 0x00}) + } else { + if(NBCI){ + Return(Buffer(){0x73, 0x00, 0x04, 0x00}) + } + else { + if(OPCI){ + //Sub-Functions 0,16,17,26 are supported + // Return(ToBuffer(0x04030001)) + //Sub-Functions 0,5, 6, 12, 13, 16, 17, 26,27 are supported + // Return(ToBuffer(0x0c031861)) + Return(Buffer(){0x61, 0x18, 0x03, 0x0C}) + //Sub-Functions 0,16 26,27 are supported +// Return(ToBuffer(0x0c010001)) + + } + } + } + } + + // + // Function 1: NVSG_FUNC_CAP + // + // Returns the capabilities of the Switchable Graphics + // implementation on the platform + // + If(LEqual(Arg2,1)) + { + Name (TEMP, Buffer () {0x00, 0x00, 0x00, 0x00}) + CreateDwordField(TEMP,0,STS0) + if(SGCI){ + // Return status (bit0-1 Hybrid enabled) and indicate Hybrid power On/Off + + // 0 HG Enable Status = 1 + // 1 GPU Output MUX Capabilities= 1 + // 2 GPU Policy Selector Capabilities = 1 + // 3-4 GPU Control Status = 3 + // 5 GPU Reset Control = 1 + // 6 MUX'ed Hot-Plug Capabilities = 0 + // 7 MUX'ed DDC/AUX Capabilities = 1 + // 8-10 Notify Codes + // 0= Not a Notify(0xD0) + // 1= POLICYSELECT change + // 2= PLATPOLICY change + // 3= DISPLAYSTATUS change + // 11-12 EC Notify code + // 14-15 Eject Capabilities = 0 + // 16 Mux'd backlight cap = 0 + // 17-23 Hybrid EC version = 0 + // 24-26 HG capability = 3 (Power saver & Boost performance) + // 27-28 HG switch = 1 (hot-key or stateless button) + // 29 Fasl LCD swithing = 0 + // 31 = 0 + + // Switchable caps + Or(STS0,0x0B0000BF,STS0) + + // Switchable Notify Code (Cause of Notify(..,0xD0)) + Or(STS0,ShiftLeft(SGNC,8,SGNC),STS0) + } else { + // NBCI + // 0..3 Reserved=00 + // 4 Aux Power States + // 6:5 LID State Event + // 0= Use the event List to determine support + // 1= Force use of Generic Hot-Plug Notify(0x81) + // 2= Force use of Specific Lid Event, e.g. Notify (0xDB) + // 3= Reserved for future use + // 7:8 LID State Enumeration + // 0= Use _DCS under _LCD device(default) + // 1= Provides status DISPLAYSTATUS Bit[4], for single pannel systems only(recommended) + // 2,3= Reserved + // 9 Dock State Enumerartion + // 0= Doesn't have a Dock(or _DCS under device reflects attachments-via-dock (default) + // 1= Provides dock status info via DISPLAYSTATUS Bit[5] (recommended) + // 10:30 Reserved + // 31 = 0 + + // use all defaults for now + Or(STS0,0x00000,STS0) + } + return(TEMP) + } + + // + // Function 2: NVSG_FUNC_SELECTOR + // + // Returns device preference between iGPU and dGPU + // + If(LEqual(Arg2,2)) + { + Name (TMP1, Buffer () {0x00, 0x00, 0x00, 0x00}) + CreateDwordField(TMP1,0,STS1) + + //Ignore bits[6:5] since we are not supporting Switchable enable/disable policy selection + //Only Switchable policy selection is supported via CAS+F6 hotkey + + //bugbug:Proxy is sending Arg3 as Buffer and not package! + //ToInteger(DerefOf(Index(Arg3,0)), Local0) + ToInteger(Arg3, Local0) + And(Local0, 0x1F, Local0) + + If(And(Local0,0x10)) //If Switchable policy update bit is set + { + And(Local0,0xF,Local0) + Store(Local0,GPSS) + Notify(IGPU_SCOPE,0xD9) //Broadcast "policy completed" notification + Notify(PCI_SCOPE.WMI1, 0xD9) // Mirror Notify on WMI1 + + } + Else + { + And(Local0,0xF,Local0) + If(LEqual(GPPO,1)) + { + // Retrieve the setting from NVS + Store(GPSS,Local0) + Or(Local0,0x10,Local0) + Store(0,GPPO) + } + } + + Or(STS1,Local0,STS1) + + Return(TMP1) + } + + // + // Function 3: NVSG_FUNC_POWERCONTROL + // + // Allows control of dGPU power methods from the iGPU + // + If(LEqual(Arg2,3)) + { + Name (TMP2, Buffer () {0x00, 0x00, 0x00, 0x00}) + CreateDwordField(TMP2,0,STS2) + + // GPU Power Control + //bugbug:Proxy is sending Arg3 as Buffer and not package! + //ToInteger(DerefOf(Index(Arg3,0)), Local0) + ToInteger(Arg3, Local0) + And(Local0, 0x3, Local0) + + If(LEqual(Local0,0)) + { + DGPU_SCOPE.SGST() + } + + If(LEqual(Local0,1)) + { + DGPU_SCOPE.SGON() + } + + If(LEqual(Local0,2)) + { + DGPU_SCOPE.SGOF() + } + + //dGPU_PWROK is not working. Using dGPU_PWR_EN# instead as w/a + //Or(STS2,DGPU_SCOPE.MPOK,STS2) + If(LEqual(DGPU_SCOPE.SGST(), 0xF)) + { + Or(STS2,0x1,STS2) + } + //else do nothing since STS2 is already 0 + Return(TMP2) + } + + // + // Function 4: NVSG_FUNC_PLATPOLICY + // + // Sets or Returns the current System Policy settings + // + If(LEqual(Arg2,4)) + { + +// common for SGCI and NBCI + Name (TMP3, Buffer () {0x00, 0x00, 0x00, 0x00}) + CreateDwordField(TMP3,0,STS3) + + // Panel Scaling Preference + + //bugbug:Proxy is sending Arg3 as Buffer and not package! + //ToInteger(DerefOf(Index(Arg3,0)), Local0) + ToInteger(Arg3, Local0) + Store(Local0, Local1) + ShiftRight(Local0, 16, Local0) + And(Local0, 0x1, USPM) + + ShiftRight(Local1, 13, Local1) + And(Local1, 0x3, Local1) + + + If(LNotEqual(Local1,GPSP)) + { + If(LEqual(USPM,1)) + { + Store(Local1,GPSP) + } + Else + { + // Retrieve the setting from NVS + Store(GPSP,Local1) + Or(STS3,0x8000,STS3) // Set Panel Scaling override + } + } + Or(STS3,ShiftLeft(Local1,13),STS3) + + + Return(TMP3) + } + + // + // Function 5: NVSG_FUNC_DISPLAYSTATUS + // + // Sets or Returns the current display detection, + // hot-key toggle sequence + // + If(LEqual(Arg2,5)) + { +// common for SGCI and NBCI + Name (TMP4, Buffer () {0x00, 0x00, 0x00, 0x00}) + CreateDwordField(TMP4,0,STS4) + + //bugbug:Proxy is sending Arg3 as Buffer and not package! + //ToInteger(Derefof(Index(Arg3,0)), Local0) //Store input field in local0 + ToInteger(Arg3, Local0) + + // Next Combination Sequence + + If(And(Local0,0x80000000)) //If Bit31 is set + { + Store(And(ShiftRight(Local0,25),0x1F),TLSN) + + If(And(Local0,0x40000000)) //If Bit30 is set + { + Store(1,DOSF) + } + } + + // Display Mask for Attached and Active Displays + + If(And(Local0,0x01000000)) //If Bit24 is set + { + Store(And(ShiftRight(Local0,12),0xFFF),GACD) + Store(And(Local0,0xFFF),GATD) + + //Get current toggle list index based on currently active display list + Store(CTOI(GACD),TLSN) + Increment(TLSN) + + If(LGreater(TLSN, 13)) //For Huron River ,13 is the number of entries in the toggle list + { + Store(1, TLSN) + } + + SNXD(TLSN) //This is optional for NV SG + } + + // Display Hot-Plug Event/Status + Or(STS4,ShiftLeft(DHPE,21),STS4) + Or(STS4,ShiftLeft(DHPS,20),STS4) + + // Toggle Sequence number + Or(STS4,ShiftLeft(TLSN,8),STS4) + + // Dock State + Or(STS4,ShiftLeft(DKST,5),STS4) + + // Lid Event State + Or(STS4,ShiftLeft(LDES,4),STS4) + + // Display ACPI Event(SGCI only) + Or(STS4,DACE,STS4) + + Store(0,LDES) + Store(0,DHPS) + Store(0,DHPE) + Store(0,DACE) + + Return(TMP4) + } + + // + // Function 6: NVSG_FUNC_MDTL - Returns Hot-Key display switch toggle sequence + // + // Returns: + // Returns Hot-Key display switch toggle sequence + // + If(LEqual(Arg2,6)) + { +// common for SGCI and NBCI + Return(TLPK) + } + // + // Function 16: + // + If(LEqual(Arg2,16)) + { + CreateWordField(Arg3, 2, USRG) // Object type signature passed in by driver. + Name(OPVK, Buffer() + { + // Key below is for Emerald Lake Fab2 platform + // Customer need to ask NVIDIA PM to get the key + // Customer need to put the key in between labels "// key start -" and + // "// key end -". Please consult NVIDIA PM if any issues + //148597456985Genuine NVIDIA Certified Optimus Ready Motherboard for 736019_MIRc + // Key start - + 0xE4,0x42,0x5F,0x14,0x36,0x26,0x16,0x37,0x4B,0x56,0xE6,0x00,0x00,0x00,0x01,0x00, + 0x31,0x34,0x38,0x35,0x39,0x37,0x34,0x35,0x36,0x39,0x38,0x35,0x47,0x65,0x6E,0x75, + 0x69,0x6E,0x65,0x20,0x4E,0x56,0x49,0x44,0x49,0x41,0x20,0x43,0x65,0x72,0x74,0x69, + 0x66,0x69,0x65,0x64,0x20,0x4F,0x70,0x74,0x69,0x6D,0x75,0x73,0x20,0x52,0x65,0x61, + 0x64,0x79,0x20,0x4D,0x6F,0x74,0x68,0x65,0x72,0x62,0x6F,0x61,0x72,0x64,0x20,0x66, + 0x6F,0x72,0x20,0x37,0x33,0x36,0x30,0x31,0x39,0x5F,0x4D,0x49,0x52,0x63,0x20,0x20, + 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x2D,0x20,0x3C,0x34,0x27,0x21,0x58,0x29, + 0x57,0x27,0x58,0x20,0x27,0x25,0x59,0x5D,0x31,0x29,0x3A,0x2A,0x26,0x39,0x59,0x43, + 0x56,0x3B,0x58,0x56,0x58,0x3D,0x59,0x4E,0x3B,0x3A,0x35,0x44,0x25,0x42,0x5A,0x48, + 0x55,0x3A,0x58,0x4C,0x25,0x48,0x54,0x21,0x35,0x4B,0x4D,0x37,0x2C,0x3C,0x20,0x2D, + 0x20,0x43,0x6F,0x70,0x79,0x72,0x69,0x67,0x68,0x74,0x20,0x32,0x30,0x31,0x30,0x20, + 0x4E,0x56,0x49,0x44,0x49,0x41,0x20,0x43,0x6F,0x72,0x70,0x6F,0x72,0x61,0x74,0x69, + 0x6F,0x6E,0x20,0x41,0x6C,0x6C,0x20,0x52,0x69,0x67,0x68,0x74,0x73,0x20,0x52,0x65, + 0x73,0x65,0x72,0x76,0x65,0x64,0x2D,0x31,0x34,0x38,0x35,0x39,0x37,0x34,0x35,0x36, + 0x39,0x38,0x35,0x28,0x52,0x29, + //Copyright 2010 NVIDIA Corporation All Rights Reserved-148597456985(R) + // Key end - + }) + If(LEqual(USRG, 0x564B)) { // 'VK' for Optimus Validation Key Object. + Return(OPVK) + } + Return(Zero) + } + // + // Function 17 NVOP_FUNC_GETALLOBJECTS + // + If(LEqual(Arg2,17)) + + { + Return(Zero) + } + // + // Function 18: NVSG_FUNC_GETEVENTLIST + // + // Returns: + // Returns list of notifiers and their meanings + // + If(LEqual(Arg2,18)) + { +// common for SGCI and NBCI + return(Package(){ + 0xD0, ToUUID("921A2F40-0DC4-402d-AC18-B48444EF9ED2"), // Policy request + 0xD9, ToUUID("C12AD361-9FA9-4C74-901F-95CB0945CF3E"), // Policy set + 0xDB, ToUUID("42848006-8886-490E-8C72-2BDCA93A8A09"), // Display scaling + + 0xEF, ToUUID("B3E485D2-3CC1-4B54-8F31-77BA2FDC9EBE"), // Policy change + 0xF0, ToUUID("360d6fb6-1d4e-4fa6-b848-1be33dd8ec7b"), // Display status + + // unfinished list of events. we do not need this Func18 unless event notifiers differ from standard ones defined in BWG. + }) + } + // + // Function 26: NVOP_FUNC_OPTIMUSCAPS + // + If(LEqual(Arg2,26)) + { + // On Input + //Bit25-24 Power Control Enable + // 2-Platform should not power down GPU in the _PS3 method(default) + // 3-Platform should power down GPU in the _PS3 method(default) + // Bit0 No flag upd present in this call (SBIOS returns curent status) + // + CreateField(Arg3,24,2,OMPR) + CreateField(Arg3,0,1,FLCH) + If(ToInteger(FLCH)) + { + Store(OMPR, DGPU_SCOPE.OPCE) // Optimus Power Control Enable - From DD + } + // On return + // Bit 24:26 Capabilities + // 0: No special platf cap + // 1: Platform has dynamic GPU power control + // Bit6 GPU Display Hot Plug NEW Optimus BWG v02 + // Bit4:3 Current GPU Control status + // 0: GPU is powered off + // 1: GPU is powered on and enabled + // 2: reserved + // 3: GPU Power has stabilized + // Bit0 + // 0:Optimus Disabled + // 1:Optimus Enabled + Store(Buffer(4) {0, 0, 0, 0}, Local0) + CreateField(Local0,0,1,OPEN) + CreateField(Local0,3,2,CGCS) + CreateField(Local0,6,1,SHPC) + CreateField(Local0,24,3,DGPC) // DGPC - Default: No Dynamic GPU Power Control + CreateField(Local0,27,2,HDAC) // HDAC - HD Audio Codec Cap + + Store(One, OPEN) // Optimus Enabled + + Store(One, SHPC) // GPU Display Hotplug Supported + Store(0x2, HDAC) // HDA BIOS control Supported + + Store(One, DGPC) // Dynamic GPU Power Control Available + If(LNotEqual(DGPU_SCOPE.SGST(), 0)) + { + Store(0x3, CGCS) // Current GPU Control status + } + Return(Local0) + + }//case (26) + // + // Function 27: NVOP_FUNC_OPTIMUSFLAGS + // + If(LEqual(Arg2,27)) + { + //bugbug:Proxy is sending Arg3 as Buffer and not package! + //ToInteger(Derefof(Index(Arg3,0)), Local0) //Store input field in local0 + ToInteger(Arg3, Local0) +// Store(Arg3, Local0) +// CreateField(Local0,0,1,OPFL) +// CreateField(Local0,1,1,OPVL) + If(And(Local0,0x00000002)) + { + Store(Zero, BUFF) + If(And(Local0,0x00000001)) + { + Store(One, BUFF) + } + } + And(SGFL, Not(0x2), SGFL) + Or(SGFL, ShiftLeft(BUFF,1), SGFL) + Store(SWSMI_NVOEM_CMOS_W, SSMP) // Set Audio Codec flag to CMOS + Return(Local0) + } + // FunctionCode or SubFunctionCode not supported + Return(0x80000002) // OTHER ARGUMENTS NOT SUPPORTED + } +#endif // common scope for Hybrid/Nbci/Optimus + + // Check for common with dGPU _DSM UUIDs +// return (DGPU_SCOPE.HDSM(Arg0, Arg1, Arg2, Arg3)) + Return (0x80000001) + } +} // end PCI0.GFX0 scope +//********************************************************************** +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNvGPS.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNvGPS.asl new file mode 100644 index 0000000..216f78d --- /dev/null +++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNvGPS.asl @@ -0,0 +1,337 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMNvGPS.asl 2 9/09/12 11:01p Joshchou $ +// +// $Revision: 2 $ +// +// $Date: 9/09/12 11:01p $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMNvGPS.asl $ +// +// 2 9/09/12 11:01p Joshchou +// [TAG] None +// [Category] Improvement +// [Description] Tpv module support for sharkbay. +// [Files] OEMSSDT.mak +// OEMSSDT.asl +// OEMNVdGPU.asl +// OEMNViGPU.asl +// OEMNViGDmisc.asl +// OEMNvVentura.asl +// OEMNvGPS.asl +// OEMSSDT.cif +// +// 1 12/12/11 9:10p Alanlin +// +// +// +//********************************************************************** +External(\_PR.CPU0._PSS, BuffObj) + +External(\_PR.CPU0._PPC, IntObj) +External(\_PR.CPU1._PPC, IntObj) +External(\_PR.CPU2._PPC, IntObj) +External(\_PR.CPU3._PPC, IntObj) +External(\_PR.CPU4._PPC, IntObj) +External(\_PR.CPU5._PPC, IntObj) +External(\_PR.CPU6._PPC, IntObj) +External(\_PR.CPU7._PPC, IntObj) +External(\_SB.PCI0.LPCB.H_EC.GTVR) // CPU GT VR (IMVP) Temperature +External(\_PR.CPU0._TSS, MethodObj) +External(\_PR.CPU0._PTC, MethodObj) + +#define GPS_REVISION_ID 0x00000100 // Revision number +#define GPS_ERROR_SUCCESS 0x00000000 // Generic Success +#define GPS_ERROR_UNSPECIFIED 0x00000001 // Generic unspecified error code +#define GPS_ERROR_UNSUPPORTED 0x00000002 // Sub-Function not supported + +#define GPS_FUNC_SUPPORT 0x00000000 // Bit list of supported functions +#define GPS_FUNC_GETCALLBACKS 0x00000013 // Get system requested callback +#define GPS_FUNC_PSHARESTATUS 0x00000020 // Get system requested Power Steering Setting +#define GPS_FUNC_GETPSS 0x00000021 // Get _PSS object +#define GPS_FUNC_SETPPC 0x00000022 // Set _PCC object +#define GPS_FUNC_GETPPC 0x00000023 // Get _PCC object +#define GPS_FUNC_PSHAREPARAMS 0x0000002A // Get sensor information and capabilities + +Scope(PCI_SCOPE){ + + Name(GPS, "GPSACPI 2012-Aug-12 14:56:05") // MCPACPIP build time stamp. + +} // end of Scope + +Scope (DGPU_SCOPE) +{ + +Name(PSAP, Zero) + Name(ECBF, Buffer(20) {}) + CreateDWordField(ECBF, 0, EDS1) + CreateDWordField(ECBF, 4, EDS2) + CreateDWordField(ECBF, 8, EDS3) + CreateDWordField(ECBF, 12, EDS4) + CreateDWordField(ECBF, 16, EPDT) + + Name(GPSP, Buffer(36) {}) + CreateDWordField(GPSP, 0, RETN) + CreateDWordField(GPSP, 4, VRV1) + CreateDWordField(GPSP, 8, TGPU) + CreateDWordField(GPSP, 12, PDTS) + CreateDWordField(GPSP, 16, SFAN) + CreateDWordField(GPSP, 20, SKNT) + CreateDWordField(GPSP, 24, CPUE) + CreateDWordField(GPSP, 28, TMP1) + CreateDWordField(GPSP, 32, TMP2) + +Name(NLIM, 0) //set one flag for GPS_EVENT_STATUS_CHANGE 1: will update parameter: 0 just call function 0x1c _PCONTROL + + Name(PSCP, 0) // P-State capacity, mainly for s/w debugging + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: GPS +// +// Description: Called from _DSM -Device Specific Method for dGPU device. +// Implement Ventura specific callback functions +// +// Input: +// Arg0: UUID Unique function identifier. +// Ventura DSM_GUID A3132D01-8CDA-49BA-A52E-BC9D46DF6B81 +// Arg1: Integer Revision Level +// Arg2: Integer Function Index (0 = Return Supported Functions) +// Arg3: Package Parameters +// +// Output: +// Sub-function 0 and unsupported function calls always returns a buffer. +// Other subfunctions may return a buffer or a package as defined in the function. +// When a single DWord is returned the following values have special meaning, +// controlled by reserved Bit31 as follows: +// MXM_ERROR_SUCCESS 0x00000000 Success +// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code +// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not +// supported by this system +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Method (GPS, 4, NotSerialized) + { + + Store("------- GPS DSM --------", Debug) + // Only Interface Revision 0x0100 is supported + If (LNotEqual(Arg1, 0x100)) + { + Return(0x80000002) + } + + P8DB(0xDD, Arg2, 1000) + // (Arg2) Sub-Function + Switch (ToInteger(Arg2)) + { + + case (GPS_FUNC_SUPPORT) + { + + Name(FMSK, Buffer(0x8) + { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + }) + Store(Buffer(0x8) + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }, Local0) + Divide(GPS_FUNC_SUPPORT, 0x8, Local2, Local1) + // Local1 is Quotient, Local2 is Remainder + ShiftLeft(0x01, Local2, Local2) + Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1)) + + Divide(GPS_FUNC_GETCALLBACKS, 8, Local2, Local1) + ShiftLeft(0x01, Local2, Local2) + Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1)) + + Divide(GPS_FUNC_PSHARESTATUS, 8, Local2, Local1) + ShiftLeft(0x01, Local2, Local2) + Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1)) + + Divide(GPS_FUNC_GETPSS, 8, Local2, Local1) + ShiftLeft(0x01, Local2, Local2) + Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1)) + + Divide(GPS_FUNC_SETPPC, 8, Local2, Local1) + ShiftLeft(0x01, Local2, Local2) + Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1)) + + Divide(GPS_FUNC_GETPPC, 8, Local2, Local1) + ShiftLeft(0x01, Local2, Local2) + Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1)) + + Divide(GPS_FUNC_PSHAREPARAMS, 8, Local2, Local1) + ShiftLeft(0x01, Local2, Local2) + Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1)) + + + // mask out specific functions + Store( SizeOf(Local0), Local1) + While( LNotEqual(Local1, 0) ) { + Decrement(Local1) + Store( DeRefOf(Index(FMSK, Local1)), Local2) + And( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1) ) + } + + Return(Local0) + } + // + // Function 19: GPS_FUNC_GETCALLBACKS, + // + case(GPS_FUNC_GETCALLBACKS) + { + Store("GPS fun 19", Debug) + return(arg3) + } + // + // Function 32: GPS_FUNC_PSHARESTATUS, + // + case(GPS_FUNC_PSHARESTATUS) + { + Store("GPS fun 20", Debug) + + Name(RET1, Zero) + CreateBitField(Arg3,24,NRIT) //new request new IGP turbo state(bit 24 is valid) + CreateBitField(Arg3,25,NRIS) //request new IGP turbo state + if (NRIS){ + if(NRIT){ + Or(RET1, 0x01000000, RET1) + }else + { + //help disable IGP turbo boost + And(RET1, 0xFeFFFFFF, RET1) + } + } + Or(RET1, 0x40000000, RET1) // if this machine support GPS + + if(NLIM){ + Or(RET1, 0x00000001, RET1) // if NLIM falg is set, set bit0 =1 + } + + Return(RET1) + } + // + // Function 33: GPS_FUNC_GETPSS, Get CPU _PSS structure + // + case(GPS_FUNC_GETPSS) + { + Return(\_PR.CPU0._PSS) + } + // + // Function 34: GPS_FUNC_SETPPC, Set current CPU _PPC limit + // + case(GPS_FUNC_SETPPC) + { + CreateBYTEField(Arg3, 0, PCAP) + Store(PCAP, \_PR.CPU0._PPC) + Notify(\_PR.CPU0, 0x80) + store(PCAP, PSAP) + Return(PCAP) + } + // + // Function 35: GPS_FUNC_GETPPC, Get current CPU _PPC limit + // + case(GPS_FUNC_GETPPC) + { + Return(PSAP) + } + + case(0x25) + { + Store("GPS fun 25", Debug) + return(\_PR_.CPU0._TSS) + } + case(0x26) + { + Store("GPS fun 26", Debug) + CreateDWordField(Arg3, Zero, TCAP) + Store(TCAP, \_PR_.CPU0._PTC) + Notify(\_PR_.CPU0, 0x80) + return(TCAP) } + // + // Function 42: GPS_FUNC_PSHAREPARAMS, Get Power Steering platform parameters + // + case(GPS_FUNC_PSHAREPARAMS) + { + Store("GPS fun 2a", Debug) + + CreateBYTEField(Arg3,0,PSH0) + CreateBYTEField(Arg3,1,PSH1) + CreateBitField(Arg3,8,GPUT) + CreateBitField(Arg3,9,CPUT) + CreateBitField(Arg3,10,FANS) + CreateBitField(Arg3,11,SKIN) + CreateBitField(Arg3,12,ENGR) + CreateBitField(Arg3,13,SEN1) + CreateBitField(Arg3,14,SEN2) + + switch (PSH0){ + case(0){ + if(CPUT){ + store(0x00000200, RETN) + Or(RETN, PSH0, RETN) + // Please return CPU or EC tempture to PDTS + store(\_SB.PCI0.LPCB.H_EC.GTVR,PDTS) + } + return(GPSP) + } //case(0) + + case(1){ + store(0x00000200, RETN) + Or(RETN, PSH0, RETN) + store(1000,PDTS) + return(GPSP) + } //case(1) + + case(2){ + Or(RETN, PSH0, RETN) + store(0x00000000, VRV1) + store(0x00000000, TGPU) + store(0x00000000, PDTS) + store(0x00000000, SFAN) + store(0x00000000, CPUE) + store(0x00000000, SKNT) + store(0x00000000, TMP1) + store(0x00000000, TMP2) + return(GPSP) + } //case(2) + } // PSH0 of switch + + } + } // end of switch + + Return(0x80000002) + } // end GPS + + +} // end DGPU_SCOPE scope +//********************************************************************** +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNvVentura.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNvVentura.asl new file mode 100644 index 0000000..2de6a1c --- /dev/null +++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMNvVentura.asl @@ -0,0 +1,502 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMNvVentura.asl 2 9/09/12 11:01p Joshchou $ +// +// $Revision: 2 $ +// +// $Date: 9/09/12 11:01p $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMNvVentura.asl $ +// +// 2 9/09/12 11:01p Joshchou +// [TAG] None +// [Category] Improvement +// [Description] Tpv module support for sharkbay. +// [Files] OEMSSDT.mak +// OEMSSDT.asl +// OEMNVdGPU.asl +// OEMNViGPU.asl +// OEMNViGDmisc.asl +// OEMNvVentura.asl +// OEMNvGPS.asl +// OEMSSDT.cif +// +// 1 12/12/11 9:10p Alanlin +// +// +//********************************************************************** +// (Ventura+)> +EXTERNAL(\_PR.CPU0, DeviceObj) +EXTERNAL(\_PR.CPU1, DeviceObj) +EXTERNAL(\_PR.CPU2, DeviceObj) +EXTERNAL(\_PR.CPU3, DeviceObj) +//> Andy+ for ClarksField -- 8 processors +EXTERNAL(\_PR.CPU4, DeviceObj) +EXTERNAL(\_PR.CPU5, DeviceObj) +EXTERNAL(\_PR.CPU6, DeviceObj) +EXTERNAL(\_PR.CPU7, DeviceObj) +//< +External(\_PR.CPU0._PSS, BuffObj) +External(\_PR.CPU0._TSS, BuffObj) + +External(\_PR.CPU0._PPC, IntObj) +External(\_PR.CPU1._PPC, IntObj) +External(\_PR.CPU2._PPC, IntObj) +External(\_PR.CPU3._PPC, IntObj) +//> Andy+ for ClarksField -- 8 processors +External(\_PR.CPU4._PPC, IntObj) +External(\_PR.CPU5._PPC, IntObj) +External(\_PR.CPU6._PPC, IntObj) +External(\_PR.CPU7._PPC, IntObj) +//< +External(\_PR.CPU0._TPC, IntObj) +External(\_PR.CPU1._TPC, IntObj) +External(\_PR.CPU2._TPC, IntObj) +External(\_PR.CPU3._TPC, IntObj) +//> Andy+ for ClarksField -- 8 processors +External(\_PR.CPU4._TPC, IntObj) +External(\_PR.CPU5._TPC, IntObj) +External(\_PR.CPU6._TPC, IntObj) +External(\_PR.CPU7._TPC, IntObj) +//< +Scope(PCI_SCOPE){ + + Name(VEN, "VENACPI 2009-Nov-23 14:56:05") // MCPACPIP build time stamp. + +} // end of Scope + +Scope (DGPU_SCOPE) +{ + // value used to notify iGPU + + Name(VSTS, 1) // Ventura Status + Name(THBG, 50000) // Thermal Budget + Name(PSCP, 0) // P-State capacity, mainly for s/w debugging + Name(TBUD, 0x88B8) // Thermal Budget +// Name(PBCM, 0) + + // Called by EC to notify thermal budget/status change + // Arg0 is one of SPB_EC_ values + // Arg1 is an object reference + Method (THCH, 2, NotSerialized) + { + Switch (ToInteger(Arg0)) + { + case ( 0x03) + { + // VSTS needs to be updated before notification + Store(DeRefOf(Arg1), VSTS) + Notify(DGPU_SCOPE, 0xC0) + } + case ( 0x01) + { + // THBG needs to be updated before notification + Store(DeRefOf(Arg1), THBG) + Notify(DGPU_SCOPE, 0xC1) + } + } + } + + // Wrapper to call Method(SPB) + Method (SPB2, 2, NotSerialized) + { + Store( Buffer() {0x00, 0x00, 0x00, 0x00}, Local0 ) + CreateDwordField(Local0, 0, LLLL) + Store( Arg1, LLLL ) + Return( SPB(0x00, 0x101, Arg0, Local0) ) + } + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: SPB +// +// Description: Called from _DSM -Device Specific Method for dGPU device. +// Implement Ventura specific callback functions +// +// Input: +// Arg0: UUID Unique function identifier. +// Ventura DSM_GUID 95DB88FD-940A-4253-A446-70CE0504AEDF +// Arg1: Integer Revision Level +// Arg2: Integer Function Index (0 = Return Supported Functions) +// Arg3: Package Parameters +// +// Output: +// Sub-function 0 and unsupported function calls always returns a buffer. +// Other subfunctions may return a buffer or a package as defined in the function. +// When a single DWord is returned the following values have special meaning, +// controlled by reserved Bit31 as follows: +// MXM_ERROR_SUCCESS 0x00000000 Success +// MXM_ERROR_UNSPECIFIED 0x80000001 Generic unspecified error code +// MXM_ERROR_UNSUPPORTED 0x80000002 FunctionCode or SubFunctionCode not +// supported by this system +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Method (SPB, 4, NotSerialized) + { + + Store("------- SPB DSM --------", Debug) + // Only Interface Revision 0x0101 is supported + If (LNotEqual(Arg1, 0x101)) + { + Return(0x80000002) + } + + // (Arg2) Sub-Function + Switch (ToInteger(Arg2)) + { + case (0x00) + { + Name(FMSK, Buffer(0x8) + { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + }) + Store(Buffer(0x8) + { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }, Local0) + Divide(Zero, 0x8, Local2, Local1) + // Local1 is Quotient, Local2 is Remainder + ShiftLeft(0x01, Local2, Local2) + Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1)) + + Divide(0x20, 8, Local2, Local1) + ShiftLeft(0x01, Local2, Local2) + Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1)) + + Divide(0x21, 8, Local2, Local1) + ShiftLeft(0x01, Local2, Local2) + Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1)) + + Divide(0x22, 8, Local2, Local1) + ShiftLeft(0x01, Local2, Local2) + Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1)) + + Divide(0x23, 8, Local2, Local1) + ShiftLeft(0x01, Local2, Local2) + Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1)) + + Divide(0x24, 8, Local2, Local1) + ShiftLeft(0x01, Local2, Local2) + Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1)) + + Divide(0x2A, 8, Local2, Local1) + ShiftLeft(0x01, Local2, Local2) + Or( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1)) + + // mask out specific functions + Store( SizeOf(Local0), Local1) + While( LNotEqual(Local1, 0) ) { + Decrement(Local1) + Store( DeRefOf(Index(FMSK, Local1)), Local2) + And( DeRefOf(Index(Local0, Local1)), Local2, Index(Local0, Local1) ) + } + + Return(Local0) + } + + // Unit is mWAT + case(0x20) + { + Store(TBUD, Local1) + //failsafe to clear ventura status bit + And(Local1, 0xFFFFF, Local1) + // Just return SPB status for now (bit[0]=1 SPB enabled) +// If(CondRefOf(PBCM,Local0)){ // Make sure this object is present. +// If(PBCM){ +// // Software/EC have another chance to disable ventura through VSTS +// If(LNotEqual(VSTS, 0)) { +// Or( Local1, 0x40000000, Local1 ) +// } +// } +// } + Return(Local1) + } + + case(0x21) + { + Return(\_PR.CPU0._PSS) + } + + case(0x22) + { + CreateByteField(Arg3, 0, PCAP) + + Store(PCAP, PSCP) + // \_PR.CPU0._PPC(PCAP) + Store(PCAP, \_PR.CPU0._PPC) + Notify(\_PR.CPU0, 0x80) + + If(CondRefOf(\_PR.CPU1._PPC, Local0)) { + // \_PR.CPU1._PPC(PCAP) + Store(PCAP, \_PR.CPU0._PPC) + Notify(\_PR.CPU1, 0x80) + } + + If(CondRefOf(\_PR.CPU2._PPC, Local0)) { + // \_PR.CPU2._PPC(PCAP) + Store(PCAP, \_PR.CPU0._PPC) + Notify(\_PR.CPU2, 0x80) + } + + If(CondRefOf(\_PR.CPU3._PPC, Local0)) { + // \_PR.CPU3._PPC(PCAP) + Store(PCAP, \_PR.CPU0._PPC) + Notify(\_PR.CPU3, 0x80) + } + +//> Andy+ for ClarksField -- 8 processors + If(CondRefOf(\_PR.CPU4._PPC, Local0)) { + // \_PR.CPU4._PPC(PCAP) + Store(PCAP, \_PR.CPU0._PPC) + Notify(\_PR.CPU4, 0x80) + } + + If(CondRefOf(\_PR.CPU5._PPC, Local0)) { + // \_PR.CPU5._PPC(PCAP) + Store(PCAP, \_PR.CPU0._PPC) + Notify(\_PR.CPU5, 0x80) + } + + If(CondRefOf(\_PR.CPU6._PPC, Local0)) { + // \_PR.CPU6._PPC(PCAP) + Store(PCAP, \_PR.CPU0._PPC) + Notify(\_PR.CPU6, 0x80) + } + + If(CondRefOf(\_PR.CPU7._PPC, Local0)) { + // \_PR.CPU7._PPC(PCAP) + Store(PCAP, \_PR.CPU0._PPC) + Notify(\_PR.CPU7, 0x80) + } +//< + + Return(PCAP) + } + + case( 0x23) + { + Return(PSCP) + } + + case(0x24) + { + CreateField(Arg3, 0, 20, THBG) + CreateField(Arg3, 30, 1, DDVE) + } + case(0x2a) + { + Return(SSNR(Arg3)) + } + } // end of switch + + Return(0x80000002) + } // end SPB + + // Ventura Sensor parameters header structure + Name(SBHS, Buffer(0x8) {}) + CreateDWordField(SBHS, 0, VERV) + CreateDWordField(SBHS, 4, NUMS) + + // Ventura CPU Sensor structure + Name(SSCP, Buffer(44) {}) + CreateDWordField(SSCP, 4, CSNT) + CreateDWordField(SSCP, 8, CPTI) + CreateDWordField(SSCP, 12, CICA) + CreateDWordField(SSCP, 16, CIRC) + CreateDWordField(SSCP, 20, CICV) + CreateDWordField(SSCP, 24, CIRA) + CreateDWordField(SSCP, 28, CIAV) + CreateDWordField(SSCP, 32, CIEP) + CreateDWordField(SSCP, 36, CPPF) + CreateDWordField(SSCP, 40, CSNR) + + // Ventura GPU Sensor structure + Name(SSGP, Buffer(44) {}) + CreateDWordField(SSGP, 4, GSNT) + CreateDWordField(SSGP, 8, GPTI) + CreateDWordField(SSGP, 12, GICA) + CreateDWordField(SSGP, 16, GIRC) + CreateDWordField(SSGP, 20, GICV) + CreateDWordField(SSGP, 24, GIRA) + CreateDWordField(SSGP, 28, GIAV) + CreateDWordField(SSGP, 32, GIEP) + CreateDWordField(SSGP, 36, GPPF) + CreateDWordField(SSGP, 40, GSNR) + + // Ventura CPU Parameters Structure + Name(SCPP, Buffer(72) {}) + CreateDWordField(SCPP, 0, VRV1) + CreateDWordField(SCPP, 4, VCAP) + CreateDWordField(SCPP, 8, VCCP) + CreateDWordField(SCPP, 12, VCDP) + CreateDWordField(SCPP, 16, VCEP) + CreateDWordField(SCPP, 20, VCGP) + CreateDWordField(SCPP, 24, VCHP) + CreateDWordField(SCPP, 28, VCXP) + CreateDWordField(SCPP, 32, VCYP) + CreateDWordField(SCPP, 36, VCZP) + CreateDWordField(SCPP, 40, VCKP) + CreateDWordField(SCPP, 44, VCMP) + CreateDWordField(SCPP, 48, VCNP) + CreateDWordField(SCPP, 52, VCAL) + CreateDWordField(SCPP, 56, VCBE) + CreateDWordField(SCPP, 60, VCGA) + CreateDWordField(SCPP, 64, VCPP) + CreateDWordField(SCPP, 68, VCDE) + +// Ventura GPU Parameters Structure + Name(SGPP, Buffer(40) {}) + CreateDWordField(SGPP, 0, VRV2) + CreateDWordField(SGPP, 4, VGWP) + CreateDWordField(SGPP, 8, VGPP) + CreateDWordField(SGPP, 12, VGQP) + CreateDWordField(SGPP, 16, VGRP) + CreateDWordField(SGPP, 20, VGAP) + CreateDWordField(SGPP, 24, VGBP) + CreateDWordField(SGPP, 28, VGCP) + CreateDWordField(SGPP, 32, VGDP) + CreateDWordField(SGPP, 36, VGDE) + + Method(SSNR, 1) + { + Switch (ToInteger(Arg0)) + { + case (0x00) + { + // Populate Header Structure + Store(0x00010000, VERV) + Store(0x02, NUMS) + Return(SBHS) + } + case (0x01) + { + Store(0x00010000, VRV1) + Store(0x3E8, VCAP) //VEN_CPU_PARAM_A_CK 0x3E8 + Store(0x2EE, VCCP) //VEN_CPU_PARAM_C_CK 0x2EE + Store(0x2EE, VCDP) //VEN_CPU_PARAM_D_CK 0x2EE + Store(0x2EE, VCEP) //VEN_CPU_PARAM_E_CK 0x2EE + Store(0x79e, VCGP) //VEN_CPU_PARAM_G_CK 0x79e + Store(0x2bc, VCHP) //VEN_CPU_PARAM_H_CK 0x2bc + Store(0x258, VCXP) //VEN_CPU_PARAM_X_CK 0x258 + Store(0x0fa, VCYP) //VEN_CPU_PARAM_Y_CK 0x0fa + Store(0x1f4, VCZP) //VEN_CPU_PARAM_Z_CK 0x1f4 + Store(0x000, VCKP) //VEN_CPU_PARAM_K_CK 0x000 + Store(0x000, VCMP) //VEN_CPU_PARAM_M_CK 0x000 + Store(0x000, VCNP) //VEN_CPU_PARAM_N_CK 0x000 + Store(0x000, VCPP) //VEN_CPU_PARAM_P_CK 0x000 + Store(0x421, VCAL) //VEN_CPU_PARAM_AL_CK 0x421 + Store(0x708, VCBE) //VEN_CPU_PARAM_BE_CK 0x708 + Store(0x016, VCGA) //VEN_CPU_PARAM_GA_CK 0x016 + Store(0x001, VCDE) //VEN_CPU_PARAM_DEL_CK 0x001 +/* Clarksfield 8 CPU + Store(0x3E8, VCAP) + Store(0x258, VCCP) + Store(0x258, VCDP) + Store(0x258, VCEP) + Store(0x2CF, VCGP) + Store(0x311, VCHP) + Store(0x136, VCXP) + Store(0x118, VCYP) + Store(0x19A, VCZP) + Store(0x001, VCKP) + Store(0x001, VCMP) + Store(0x001, VCNP) + Store(0x000, VCPP) + Store(0x36B, VCAL) + Store(0x13C, VCBE) + Store(0x019, VCGA) + Store(0x001, VCDE) +end Clarksfield 8CPUs*/ + + Return(SCPP) + } + case (0x02) + { + Store(0x00010000, VRV2) + Store(0x3E8, VGWP) + Store(0x2EE, VGPP) + Store(0x2EE, VGQP) + Store(0x2EE, VGRP) + Store(0x001, VGAP) + Store(0x1F4, VGBP) + Store(0x000, VGCP) + Store(0x000, VGDP) + Store(0x001, VGDE) +/* Clarksfield 8 CPU + Store(0x3E8, VGBP) + Store(0x001, VGCP) + Store(0x001, VGDP) + Store(0x000, VGDE) +end Clarksfield 8CPUs*/ + Return(SGPP) + } + case (0x03) + { + // The below sensor parameter values for GPU and CPU + // are board specific. To support for ventura, fill + // the SSCP and SSGP structures + + // Populate CPU Sensor values + Store(0x0, Index(SSCP, 0)) // Indicate CPU sensor + Store(0x00, CSNT) + Store(0x01, CPTI) + Store(0x84, CICA) // 0x80 + Store(0x00, CIRC) + Store(0x27FF, CICV) + Store(0x05, CIRA) + Store(0xA000, CIAV) + Store(0x03, CIEP) + Store(0x0F, CPPF) + Store(0x04, CSNR) + + // Populate GPU Sensor values + Store(0x1, Index(SSGP, 0)) // Indicate GPU sensor + Store(0x00, GSNT) + Store(0x01, GPTI) + Store(0x8C, GICA) // 0x8A + Store(0x00, GIRC) + Store(0x27FF, GICV) + Store(0x05, GIRA) + Store(0xA000, GIAV) + Store(0x03, GIEP) + Store(0x0F, GPPF) + Store(0x04, GSNR) + + Return(Concatenate(SSCP, SSGP)) + } + + } //switch end + + Return(0x80000002) + } +} // end DGPU_SCOPE scope + +//********************************************************************** +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//**********************************************************************
\ No newline at end of file diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.asl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.asl new file mode 100644 index 0000000..f086336 --- /dev/null +++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.asl @@ -0,0 +1,196 @@ +//**************************************************************************** +//**************************************************************************** +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone (770)-246-8600 ** +//** ** +//**************************************************************************** +//**************************************************************************** +//**************************************************************************** +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMSSDT.asl 2 9/09/12 11:01p Joshchou $ +// +// $Revision: 2 $ +// +// $Date: 9/09/12 11:01p $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMSSDT.asl $ +// +// 2 9/09/12 11:01p Joshchou +// [TAG] None +// [Category] Improvement +// [Description] Tpv module support for sharkbay. +// [Files] OEMSSDT.mak +// OEMSSDT.asl +// OEMNVdGPU.asl +// OEMNViGPU.asl +// OEMNViGDmisc.asl +// OEMNvVentura.asl +// OEMNvGPS.asl +// OEMSSDT.cif +// +// 2 12/22/11 6:38a Alanlin +// Declared "defined(SGTPV_ASL_DEBUG) && (SGTPV_ASL_DEBUG ==1)" +// +// 1 12/12/11 9:10p Alanlin +// +// +//********************************************************************** + +DefinitionBlock ( + "OEMACPI.aml", + "SSDT", + 1, + "OEMRef", + "OEMTabl", + 0x1000 + ) { + +#define OPTIMUS_DSM_GUID 1 +//#define NBCI_DSM_GUID 1 + +External(P8XH, MethodObj) +#if defined(SGTPV_ASL_DEBUG) && (SGTPV_ASL_DEBUG ==1) +#define P8DB(arg0, arg1, arg2) P8XH (0, arg1) P8XH (1, arg0) sleep(arg2) +#else +#define P8DB(arg0, arg1, arg2) +#endif + + +External(PCI_SCOPE, DeviceObj) +External(PEG_SCOPE, DeviceObj) +External(DGPU_SCOPE, DeviceObj) +External(IGPU_SCOPE, DeviceObj) +External(DGPU_SCOPE._ADR, DeviceObj) +External(IGPU_SCOPE._DSM, MethodObj) +External(DGPU_SCOPE.SGST, MethodObj) +External(DGPU_SCOPE.SGON, MethodObj) +External(DGPU_SCOPE.SGOF, MethodObj) +External(DGPU_SCOPE.SGPI, MethodObj) +External(DGPU_SCOPE.SGPO, MethodObj) +External(\DSEL) +External(\ESEL) +External(\SSEL) +External(\PSEL) +External(\HLRS) +External(\PWEN) +External(\PWOK) +External(\SGMD) +External(\SGFL) +External(\SSMP) + +#include <OEMNVdGPU.ASL> // Include DGPU device namespace +#include <OEMNViGPU.ASL> // Include NVHG DSM calls +//#include <NViGDmisc.ASL> // Include misc event callback methods +#include <OEMNvGPS.ASL> // Include GPS support + + +Scope(PEG_SCOPE) +{ + Method(_STA,0,Serialized) + { + Return(0x000F) + } +} + + Scope(PCI_SCOPE) + { +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: WMI1 +// +// Description: WMI MXM Mapper. ASL Device is used to acccess Nv Optimus native method via WMI API +// +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Device(WMI1) // placed within PCI Bus scope parallel to iGPU + { + Name(_HID, "PNP0C14") + Name(_UID, "OPT1") + + Name(_WDG, Buffer() + { + // Methods GUID {F6CB5C3C-9CAE-4ebd-B577-931EA32A2CC0} + 0x3C, 0x5C, 0xCB, 0xF6, 0xAE, 0x9C, 0xbd, 0x4e, 0xB5, 0x77, 0x93, 0x1E, + 0xA3, 0x2A, 0x2C, 0xC0, + 0x4D, 0x58, // Object ID "MX" = method "WMMX" + 1, // Instance Count + 0x02, // Flags (WMIACPI_REGFLAG_METHOD) + }) // End of _WDG + +//<AMI_PHDR_START> +//------------------------------------------------------------------------ +// +// Procedure: WMMX +// +// Description: WMI Method execution tunnel. MXM Native methods are called via WMMX index. +// +// Input: +// Arg1: Integer GPU index. 0x10-iGPU, 0x100+PCIe Bus number for the GPU +// +// Output: +// Buffer specific to the funcion being called +//------------------------------------------------------------------------- +//<AMI_PHDR_END> + Method(WMMX, 3) + { + + //Arg1 = 0x10 indicates iGPU, 0x100+PCIe Bus number for the GPU + // + CreateDwordField(Arg2, 0, FUNC) // Get the function name + + If (LEqual(FUNC, 0x534F525F)) // "_ROM" + { + If (LGreaterEqual(SizeOf(Arg2), 8)) + { + CreateDwordField(Arg2, 4, ARGS) + CreateDwordField(Arg2, 8, XARG) + Return(DGPU_SCOPE._ROM(ARGS, XARG)) + } + } + + If (LEqual(FUNC, 0x4D53445F)) // "_DSM" + { + If (LGreaterEqual(SizeOf(Arg2), 28)) + { + CreateField(Arg2, 0, 128, MUID) + CreateDwordField(Arg2, 16, REVI) + CreateDwordField(Arg2, 20, SFNC) + CreateField(Arg2, 0xe0, 0x20, XRG0) + +// If(LNotEqual(Arg1,0x10)) +// { + If (CondRefOf(IGPU_SCOPE._DSM)) // common with dGPU DSM functions + { + Return(IGPU_SCOPE._DSM(MUID, REVI, SFNC, XRG0)) + } +// } + } + } + Return(0) + } // End of WMMX + } // End of WMI1 Device + } // end scope PCI0 +} // end SSDT +//**************************************************************************** +//**************************************************************************** +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone (770)-246-8600 ** +//** ** +//**************************************************************************** +//**************************************************************************** +//**************************************************************************** diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.cif b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.cif new file mode 100644 index 0000000..764d465 --- /dev/null +++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.cif @@ -0,0 +1,15 @@ +<component> + name = "OEMSSDT" + category = ModulePart + LocalRoot = "Board\EM\SwitchableGraphics\SgTpv\AcpiTables\OEMSSDT" + RefName = "OEMSSDT" +[files] +"OEMSSDT.sdl" +"OEMSSDT.mak" +"OEMSSDT.asl" +"OEMNVdGPU.asl" +"OEMNViGPU.asl" +"OEMNViGDmisc.asl" +"OEMNvVentura.asl" +"OEMNvGPS.asl" +<endComponent> diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.mak b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.mak new file mode 100644 index 0000000..3546d35 --- /dev/null +++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.mak @@ -0,0 +1,134 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2012, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMSSDT.mak 4 6/02/13 8:15a Joshchou $ +# +# $Revision: 4 $ +# +# $Date: 6/02/13 8:15a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/SwitchableGraphics/Sg TPV/Sg Acpi Tables/OEMSSDT/OEMSSDT.mak $ +# +# 4 6/02/13 8:15a Joshchou +# [TAG] None +# [Category] Improvement +# [Description] Change IASL compiler path to +# $(ACPIPLATFORM_ASL_COMPILER) in SharkBay project. +# +# 3 11/20/12 3:48a Joshchou +# [TAG] None +# [Category] Improvement +# [Description] Create Token for OEM clone +# +# 2 9/09/12 11:01p Joshchou +# [TAG] None +# [Category] Improvement +# [Description] Tpv module support for sharkbay. +# [Files] OEMSSDT.mak +# OEMSSDT.asl +# OEMNVdGPU.asl +# OEMNViGPU.asl +# OEMNViGDmisc.asl +# OEMNvVentura.asl +# OEMNvGPS.asl +# OEMSSDT.cif +# +# 1 12/12/11 9:10p Alanlin +# +# +# +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: OEMSSDT.mak +# +# Description: MAke file to build Aptio ACPI ASL components +# +# +#<AMI_FHDR_END> +#************************************************************************* +all : BuildOEMSSDT + +BuildOEMSSDT : $(BUILD_DIR)\OEMSSDT.ffs + +#--------------------------------------------------------------------------- +# Generic AcpiPlatform dependencies +#--------------------------------------------------------------------------- +$(BUILD_DIR)\OEMSSDT.mak : $(SG_OEMSSDT_DIR)\OEMSSDT.cif $(BUILD_RULES) + $(CIF2MAK) $(SG_OEMSSDT_DIR)\OEMSSDT.cif $(CIF2MAK_DEFAULTS) + + +#----------------------------------------------------------------------- +# ASL compiler definition +#----------------------------------------------------------------------- +!IF "$(ACPIPLATFORM_ASL_COMPILER)"=="" +!ERROR It is an invalid path, please check your ASL compiler path. +!ENDIF + +IASL = $(ACPIPLATFORM_ASL_COMPILER) +#----------------------------------------------------------------------- +$(BUILD_DIR)\OEMSSDT.aml : $(BUILD_DIR)\OEMSSDT.asl +# @cl /C /EP $(AOACACPI_ASL_FILE) > $(BUILD_DIR)\AoacAcpi.asl +# $(IASL) -p $(BUILD_DIR)\OEMSSDT.aml $(SGOEMSSDT_ASL_FILE) + $(IASL) -p $@ $*.asl + +$(BUILD_DIR)\OEMSSDT.sec: $(BUILD_DIR)\OEMSSDT.aml + $(GENSECTION) -I $*.aml -O $@ -S EFI_SECTION_RAW + +#Note. Expand the package with OEMSSDT tables. +# DXE phase will load the tables +# and update Aml contents if provided in SgTpvAcpiTables.c + +$(BUILD_DIR)\OEMSSDT.ffs: $(BUILD_DIR)\OEMSSDT.sec + $(GENFFSFILE) -B $(BUILD_DIR) -V -o $@ -P1 <<$(BUILD_DIR)\OEMSSDT.pkg + +PACKAGE.INF +[.] +BASE_NAME = OEMSSDT +FFS_FILEGUID = 5B232086-350A-42c7-A70E-3497B5765D85 +FFS_FILETYPE = EFI_FV_FILETYPE_FREEFORM +FFS_ATTRIB_CHECKSUM = TRUE + +IMAGE_SCRIPT = +{ + Compress (dummy) { + $(PROJECT_DIR)\$(BUILD_DIR)\OEMSSDT.sec + } +} +<<KEEP + +#-----------------------------------------------------------------------# +# Process SG asl files +#-----------------------------------------------------------------------# +$(BUILD_DIR)\OEMSSDT.asl : $(SGOEMSSDT_ASL_FILE) + $(CP) /I$(SG_OEMSSDT_DIR) /FItoken.h /C $(SG_OEMSSDT_DIR)\$(@F) > $@ +# include the token.h if needed to check for SDL flags +# /FItoken.h + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2012, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.sdl b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.sdl new file mode 100644 index 0000000..9d79dd6 --- /dev/null +++ b/Board/EM/SwitchableGraphics/SgTpv/AcpiTables/OEMSSDT/OEMSSDT.sdl @@ -0,0 +1,47 @@ +TOKEN + Name = "SGOEMSSDT_SUPPORT" + Value = "0" + Help = "Add an OEM SSDT for discrete VGA card. When Primarydisplay = Auto or PEG, the system can report OEM SSDT talbes for AMD or nVidia dGPU VGA card." + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Master = Yes +End + +TOKEN + Name = "SGOEM_ACPI_SSDT_TABLE" + Value = "EFI_SIGNATURE_64 ('O', 'E', 'M', 'T', 'a', 'b', 'l', 0)" + Help = "SGOEM Acpi table name" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SGOEM_ACPI_SSDT_GUID" + Value = "{0x5B232086, 0x350A, 0x42c7, 0xA7, 0x0E, 0x34, 0x97, 0xB5, 0x76, 0x5D, 0x85}" + Help = "SGTpv Acpi Package" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SGOEMSSDT_ASL_FILE" + Value = "$(SG_OEMSSDT_DIR)\*.asl" + TokenType = Expression + TargetMAK = Yes +End + +PATH + Name = "SG_OEMSSDT_DIR" +End + +MODULE + Help = "Includes OEMSSDT.mak to Project" + File = "OEMSSDT.mak" +End + +ELINK + Name = "$(BUILD_DIR)\OEMSSDT.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End |