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-rw-r--r--Core/CPU/IPF/FoundationIPF.cif24
-rw-r--r--Core/CPU/IPF/FoundationIPF.mak66
-rw-r--r--Core/CPU/IPF/FoundationIPF.sdl19
-rw-r--r--Core/CPU/IPF/IpfCpuCore.i93
-rw-r--r--Core/CPU/IPF/IpfCpuCore.s196
-rw-r--r--Core/CPU/IPF/PeCoffLoaderEx.c268
-rw-r--r--Core/CPU/IPF/PeCoffLoaderEx.h87
-rw-r--r--Core/CPU/IPF/PerformancePrimitives.s61
-rw-r--r--Core/CPU/IPF/Processor.h27
-rw-r--r--Core/CPU/IPF/SwitchStack.s122
-rw-r--r--Core/CPU/IPF/SwitchToCacheMode.c77
-rw-r--r--Core/CPU/IPF/asm.h35
-rw-r--r--Core/CPU/IPF/efijump.h112
-rw-r--r--Core/CPU/IPF/ia_64gen.h214
-rw-r--r--Core/CPU/IPF/pioflush.s106
-rw-r--r--Core/CPU/IPF/processor.c118
-rw-r--r--Core/CPU/IPF/setjmp.s325
17 files changed, 1950 insertions, 0 deletions
diff --git a/Core/CPU/IPF/FoundationIPF.cif b/Core/CPU/IPF/FoundationIPF.cif
new file mode 100644
index 0000000..c6f8c63
--- /dev/null
+++ b/Core/CPU/IPF/FoundationIPF.cif
@@ -0,0 +1,24 @@
+<component>
+ name = "FoundationIPF"
+ category = ModulePart
+ LocalRoot = "Core\CPU\IPF\"
+ RefName = "FoundationIPF"
+[files]
+"FoundationIPF.sdl"
+"FoundationIPF.mak"
+"SwitchStack.s"
+"asm.h"
+"efijump.h"
+"ia_64gen.h"
+"PeCoffLoaderEx.c"
+"PeCoffLoaderEx.h"
+"PerformancePrimitives.s"
+"pioflush.s"
+"processor.c"
+"setjmp.s"
+"Processor.h"
+"SwitchToCacheMode.c"
+"IpfCpuCore.s"
+"IpfCpuCore.i"
+
+<endComponent>
diff --git a/Core/CPU/IPF/FoundationIPF.mak b/Core/CPU/IPF/FoundationIPF.mak
new file mode 100644
index 0000000..ad13ce2
--- /dev/null
+++ b/Core/CPU/IPF/FoundationIPF.mak
@@ -0,0 +1,66 @@
+#**********************************************************************
+#**********************************************************************
+#** **
+#** (C)Copyright 1985-2006, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 6145-F Northbelt Pkwy, Norcross, GA 30071 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#**********************************************************************
+#**********************************************************************
+
+#**********************************************************************
+# $Header: /Alaska/SOURCE/Core/EDK/IPF/FoundationIPF.mak 1 8/24/06 12:37p Felixp $
+#
+# $Revision: 1 $
+#
+# $Date: 8/24/06 12:37p $
+#**********************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Core/EDK/IPF/FoundationIPF.mak $
+#
+# 1 8/24/06 12:37p Felixp
+#
+#**********************************************************************
+#<AMI_FHDR_START>
+#
+# Name: FoundationIPF.mak
+#
+# Description:
+#
+#<AMI_FHDR_END>
+#**********************************************************************
+FoundationIPF : $(BUILD_DIR)\FoundationIPF.mak FoundationIPFBin
+
+$(BUILD_DIR)\FoundationIPF.mak : $(FoundationIPF_DIR)\$(@B).cif $(FoundationIPF_DIR)\$(@B).mak $(BUILD_RULES)
+ $(CIF2MAK) $(FoundationIPF_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+!IF "$(PROCESSOR)"=="IPF"
+FoundationBin : $(BUILD_DIR)\FoundationIPF.lib
+FoundationPeiBin : $(BUILD_DIR)\FoundationIPF.lib
+$(BUILD_DIR)\FoundationIPF.lib : FoundationIPF
+!ENDIF
+
+
+FoundationIPFBin :
+ $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\
+ /f $(BUILD_DIR)\FoundationIPF.mak all\
+ "CFLAGS=$(CFLAGS) /I$(Foundation_DIR)"\
+ TYPE=LIBRARY
+#**********************************************************************
+#**********************************************************************
+#** **
+#** (C)Copyright 1985-2006, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 6145-F Northbelt Pkwy, Norcross, GA 30071 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#**********************************************************************
+#********************************************************************** \ No newline at end of file
diff --git a/Core/CPU/IPF/FoundationIPF.sdl b/Core/CPU/IPF/FoundationIPF.sdl
new file mode 100644
index 0000000..32db6cc
--- /dev/null
+++ b/Core/CPU/IPF/FoundationIPF.sdl
@@ -0,0 +1,19 @@
+TOKEN
+ Name = "FoundationIPF_SUPPORT"
+ Value = "1"
+ Help = "Main switch to enable FoundationIPF support in Project"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ Master = Yes
+End
+
+PATH
+ Name = "FoundationIPF_DIR"
+End
+
+MODULE
+ Help = "Includes FoundationIPF.mak to Project"
+ File = "FoundationIPF.mak"
+End
+
diff --git a/Core/CPU/IPF/IpfCpuCore.i b/Core/CPU/IPF/IpfCpuCore.i
new file mode 100644
index 0000000..d0c6fa2
--- /dev/null
+++ b/Core/CPU/IPF/IpfCpuCore.i
@@ -0,0 +1,93 @@
+//++
+// Copyright (c) 2004, Intel Corporation
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Module Name:
+//
+// IpfCpuCore.i
+//
+// Abstract:
+// IPF CPU definitions
+//
+//--
+
+#ifndef _IPF_CPU_CORE_
+#define _IPF_CPU_CORE_
+
+#define PEI_BSP_STORE_SIZE 0x4000
+#define ResetFn 0x00
+#define MachineCheckFn 0x01
+#define InitFn 0x02
+#define RecoveryFn 0x03
+#define GuardBand 0x10
+
+//
+// Define hardware RSE Configuration Register
+//
+
+//
+// RS Configuration (RSC) bit field positions
+//
+#define RSC_MODE 0
+#define RSC_PL 2
+#define RSC_BE 4
+//
+// RSC bits 5-15 reserved
+//
+#define RSC_MBZ0 5
+#define RSC_MBZ0_V 0x3ff
+#define RSC_LOADRS 16
+#define RSC_LOADRS_LEN 14
+//
+// RSC bits 30-63 reserved
+//
+#define RSC_MBZ1 30
+#define RSC_MBZ1_V 0x3ffffffffULL
+
+//
+// RSC modes
+//
+
+//
+// Lazy
+//
+#define RSC_MODE_LY (0x0)
+//
+// Store intensive
+//
+#define RSC_MODE_SI (0x1)
+//
+// Load intensive
+//
+#define RSC_MODE_LI (0x2)
+//
+// Eager
+//
+#define RSC_MODE_EA (0x3)
+
+//
+// RSC Endian bit values
+//
+#define RSC_BE_LITTLE 0
+#define RSC_BE_BIG 1
+
+//
+// RSC while in kernel: enabled, little endian, pl = 0, eager mode
+//
+#define RSC_KERNEL ((RSC_MODE_EA<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
+//
+// Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode
+//
+#define RSC_KERNEL_LAZ ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
+//
+// RSE disabled: disabled, pl = 0, little endian, eager mode
+//
+#define RSC_KERNEL_DISABLED ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
+
+#endif
diff --git a/Core/CPU/IPF/IpfCpuCore.s b/Core/CPU/IPF/IpfCpuCore.s
new file mode 100644
index 0000000..d3b7c62
--- /dev/null
+++ b/Core/CPU/IPF/IpfCpuCore.s
@@ -0,0 +1,196 @@
+//++
+// Copyright (c) 2004, Intel Corporation
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Module Name:
+//
+// IpfCpuCore.s
+//
+// Abstract:
+// IPF Specific assembly routines
+//
+//--
+
+.file "IpfCpuCore.s"
+
+#include "IpfMacro.i"
+#include "IpfCpuCore.i"
+
+//----------------------------------------------------------------------------------
+// This module supports terminating CAR (Cache As RAM) stage. It copies all the
+// CAR data into real RAM and then makes a stack switch.
+
+// EFI_STATUS
+// SwitchCoreStacks (
+// IN VOID *EntryPoint,
+// IN UINTN CopySize,
+// IN VOID *OldBase,
+// IN VOID *NewBase
+// IN UINTN NewSP, OPTIONAL
+// IN UINTN NewBSP OPTIONAL
+// )
+// EFI_STATUS
+// SwitchCoreStacks (
+// IN VOID *EntryPointForContinuationFunction,
+// IN UINTN StartupDescriptor,
+// IN VOID PEICorePointer,
+// IN UINTN NewSP
+// )
+//----------------------------------------------------------------------------------
+PROCEDURE_ENTRY (SwitchCoreStacks)
+
+ NESTED_SETUP (4,2,0,0)
+
+ // first save all stack registers in GPRs.
+ mov r13 = in0;; // this is a pointer to the PLABEL of the continuation function.
+ ld8 r16 = [r13],8;; // r16 = address of continuation function from the PLABEL
+ ld8 gp = [r13];; // gp = gp of continuation function from the PLABEL
+ mov b1 = r16;;
+
+ // save the parameters in r5, r6. these 2 seemed to be preserved across PAL calls
+ mov r5 = in1;; // this is the parameter1 to pass to the continuation function
+ mov r6 = in2;; // this is the parameter2 to pass to the continuation function
+ dep r6=0,r6,63,1;; // zero the bit 63.
+
+ mov r8 = in3;; // new stack pointer.
+
+ // r8 has the sp, this is 128K stack size, from this we will reserve 16K for the bspstore
+ movl r15 = PEI_BSP_STORE_SIZE;;
+ sub r8 = r8, r15;;
+ add r15 = (GuardBand),r8;; // some little buffer, now r15 will be our bspstore
+
+ // save the bspstore value to r4, save sp value to r7
+ mov r4 = r15
+ mov r7 = r8
+ mov r16 = r8;; // will be the new sp in uncache mode
+
+
+ alloc r11=0,0,0,0;; // Set 0-size frame
+ flushrs;;
+
+ mov r21 = RSC_KERNEL_DISABLED;; // for rse disable
+ mov ar.rsc = r21;; // turn off RSE
+
+ add sp = r0, r16 // transfer to the EFI stack
+ mov ar.bspstore = r15 // switch to EFI BSP
+ invala // change of ar.bspstore needs invala.
+
+ mov r19 = RSC_KERNEL_LAZ;; // RSC enabled, Lazy mode
+ mov ar.rsc = r19;; // turn rse on, in kernel mode
+
+//-----------------------------------------------------------------------------------
+// Save here the meaningful stuff for next few lines and then make the PAL call.
+// Make PAL call to terminate the CAR status.
+ // AVL: do this only for recovery check call...
+
+ mov r28=ar.k3;;
+ dep r2 = r28,r0,0,8;; // Extract Function bits from GR20.
+ cmp.eq p6,p7 = RecoveryFn,r2;; // Is it Recovery check
+ (p7) br.sptk.few DoneCARTermination; // if not, don't terminate car..
+
+TerminateCAR::
+
+ mov r28 = ip;;
+ add r28 = (DoneCARTerminationPALCall - TerminateCAR),r28;;
+ mov b0 = r28
+
+ mov r8 = ar.k5;;
+ mov b6 = r8
+ mov r28 = 0x208
+
+ mov r29 = r0
+ mov r30 = r0
+ mov r31 = r0
+ mov r8 = r0;;
+ br.sptk.few b6;; // Call PAL-A call.
+
+DoneCARTerminationPALCall::
+
+// don't check error in soft sdv, it is always returning -1 for this call for some reason
+#if SOFT_SDV
+#else
+ReturnToPEIMain::
+ cmp.eq p6,p7 = r8,r0;;
+ //
+ // dead loop if the PAL call failed, we have the CAR on but the stack is now pointing to memory
+ //
+ (p7) br.sptk.few ReturnToPEIMain;;
+ //
+ // PAL call successed,now the stack are in memory so come into cache mode
+ // instead of uncache mode
+ //
+
+ alloc r11=0,0,0,0;; // Set 0-size frame
+ flushrs;;
+
+ mov r21 = RSC_KERNEL_DISABLED;; // for rse disable
+ mov ar.rsc = r21;; // turn off RSE
+
+ dep r6 = 0,r6,63,1 // zero the bit 63
+ dep r7 = 0,r7,63,1 // zero the bit 63
+ dep r4 = 0,r4,63,1;; // zero the bit 63
+ add sp = r0, r7 // transfer to the EFI stack in cache mode
+ mov ar.bspstore = r4 // switch to EFI BSP
+ invala // change of ar.bspstore needs invala.
+
+ mov r19 = RSC_KERNEL_LAZ;; // RSC enabled, Lazy mode
+ mov ar.rsc = r19;; // turn rse on, in kernel mode
+
+#endif
+
+DoneCARTermination::
+
+ // allocate a stack frame:
+ alloc r11=0,2,2,0 ;; // alloc outs going to ensuing DXE IPL service
+ // on the new stack
+ mov out0 = r5;;
+ mov out1 = r6;;
+
+ mov r16 = b1;;
+ mov b6 = r16;;
+ br.call.sptk.few b0=b6;; // Call the continuation function
+
+ NESTED_RETURN
+
+PROCEDURE_EXIT(SwitchCoreStacks)
+//-----------------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------------
+//++
+// GetHandOffStatus
+//
+// This routine is called by all processors simultaneously, to get some hand-off
+// status that has been captured by IPF dispatcher and recorded in kernel registers.
+//
+// Arguments :
+//
+// On Entry : None.
+//
+// Return Value: Lid, R20Status.
+//
+//--
+//----------------------------------------------------------------------------------
+PROCEDURE_ENTRY (GetHandOffStatus)
+
+ NESTED_SETUP (0,2+0,0,0)
+
+ mov r8 = ar.k6 // Health Status (Self test params)
+ mov r9 = ar.k4 // LID bits
+ mov r10 = ar.k3;; // SAL_E entry state
+ #if (PI_SPECIFICATION_VERSION < 0x00010000)
+ mov r11 = ar.k7 // Return address to PAL
+ #else
+ mov r11 = ar.k1 // Return address to PAL
+ #endif
+
+ NESTED_RETURN
+PROCEDURE_EXIT (GetHandOffStatus)
+//----------------------------------------------------------------------------------
+
+
diff --git a/Core/CPU/IPF/PeCoffLoaderEx.c b/Core/CPU/IPF/PeCoffLoaderEx.c
new file mode 100644
index 0000000..60018ed
--- /dev/null
+++ b/Core/CPU/IPF/PeCoffLoaderEx.c
@@ -0,0 +1,268 @@
+/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ PeCoffLoaderEx.c
+
+Abstract:
+
+ Fixes Intel Itanium(TM) specific relocation types
+
+
+Revision History
+
+--*/
+
+#include "TianoCommon.h"
+#include "EfiImage.h"
+
+#define EXT_IMM64(Value, Address, Size, InstPos, ValPos) \
+ Value |= (((UINT64)((*(Address) >> InstPos) & (((UINT64)1 << Size) - 1))) << ValPos)
+
+#define INS_IMM64(Value, Address, Size, InstPos, ValPos) \
+ *(UINT32*)Address = (*(UINT32*)Address & ~(((1 << Size) - 1) << InstPos)) | \
+ ((UINT32)((((UINT64)Value >> ValPos) & (((UINT64)1 << Size) - 1))) << InstPos)
+
+#define IMM64_IMM7B_INST_WORD_X 3
+#define IMM64_IMM7B_SIZE_X 7
+#define IMM64_IMM7B_INST_WORD_POS_X 4
+#define IMM64_IMM7B_VAL_POS_X 0
+
+#define IMM64_IMM9D_INST_WORD_X 3
+#define IMM64_IMM9D_SIZE_X 9
+#define IMM64_IMM9D_INST_WORD_POS_X 18
+#define IMM64_IMM9D_VAL_POS_X 7
+
+#define IMM64_IMM5C_INST_WORD_X 3
+#define IMM64_IMM5C_SIZE_X 5
+#define IMM64_IMM5C_INST_WORD_POS_X 13
+#define IMM64_IMM5C_VAL_POS_X 16
+
+#define IMM64_IC_INST_WORD_X 3
+#define IMM64_IC_SIZE_X 1
+#define IMM64_IC_INST_WORD_POS_X 12
+#define IMM64_IC_VAL_POS_X 21
+
+#define IMM64_IMM41a_INST_WORD_X 1
+#define IMM64_IMM41a_SIZE_X 10
+#define IMM64_IMM41a_INST_WORD_POS_X 14
+#define IMM64_IMM41a_VAL_POS_X 22
+
+#define IMM64_IMM41b_INST_WORD_X 1
+#define IMM64_IMM41b_SIZE_X 8
+#define IMM64_IMM41b_INST_WORD_POS_X 24
+#define IMM64_IMM41b_VAL_POS_X 32
+
+#define IMM64_IMM41c_INST_WORD_X 2
+#define IMM64_IMM41c_SIZE_X 23
+#define IMM64_IMM41c_INST_WORD_POS_X 0
+#define IMM64_IMM41c_VAL_POS_X 40
+
+#define IMM64_SIGN_INST_WORD_X 3
+#define IMM64_SIGN_SIZE_X 1
+#define IMM64_SIGN_INST_WORD_POS_X 27
+#define IMM64_SIGN_VAL_POS_X 63
+
+EFI_STATUS
+PeCoffLoaderRelocateImageEx (
+ IN UINT16 *Reloc,
+ IN OUT CHAR8 *Fixup,
+ IN OUT CHAR8 **FixupData,
+ IN UINT64 Adjust
+ )
+/*++
+
+Routine Description:
+
+ Performs an Itanium-based specific relocation fixup
+
+Arguments:
+
+ Reloc - Pointer to the relocation record
+
+ Fixup - Pointer to the address to fix up
+
+ FixupData - Pointer to a buffer to log the fixups
+
+ Adjust - The offset to adjust the fixup
+
+Returns:
+
+ Status code
+
+--*/
+{
+ UINT64 *F64;
+ UINT64 FixupVal;
+
+ switch ((*Reloc) >> 12) {
+
+ case EFI_IMAGE_REL_BASED_IA64_IMM64:
+
+ //
+ // Align it to bundle address before fixing up the
+ // 64-bit immediate value of the movl instruction.
+ //
+
+ Fixup = (CHAR8 *)((UINTN) Fixup & (UINTN) ~(15));
+ FixupVal = (UINT64)0;
+
+ //
+ // Extract the lower 32 bits of IMM64 from bundle
+ //
+ EXT_IMM64(FixupVal,
+ (UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X,
+ IMM64_IMM7B_SIZE_X,
+ IMM64_IMM7B_INST_WORD_POS_X,
+ IMM64_IMM7B_VAL_POS_X
+ );
+
+ EXT_IMM64(FixupVal,
+ (UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X,
+ IMM64_IMM9D_SIZE_X,
+ IMM64_IMM9D_INST_WORD_POS_X,
+ IMM64_IMM9D_VAL_POS_X
+ );
+
+ EXT_IMM64(FixupVal,
+ (UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X,
+ IMM64_IMM5C_SIZE_X,
+ IMM64_IMM5C_INST_WORD_POS_X,
+ IMM64_IMM5C_VAL_POS_X
+ );
+
+ EXT_IMM64(FixupVal,
+ (UINT32 *)Fixup + IMM64_IC_INST_WORD_X,
+ IMM64_IC_SIZE_X,
+ IMM64_IC_INST_WORD_POS_X,
+ IMM64_IC_VAL_POS_X
+ );
+
+ EXT_IMM64(FixupVal,
+ (UINT32 *)Fixup + IMM64_IMM41a_INST_WORD_X,
+ IMM64_IMM41a_SIZE_X,
+ IMM64_IMM41a_INST_WORD_POS_X,
+ IMM64_IMM41a_VAL_POS_X
+ );
+
+ //
+ // Update 64-bit address
+ //
+ FixupVal += Adjust;
+
+ //
+ // Insert IMM64 into bundle
+ //
+ INS_IMM64(FixupVal,
+ ((UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X),
+ IMM64_IMM7B_SIZE_X,
+ IMM64_IMM7B_INST_WORD_POS_X,
+ IMM64_IMM7B_VAL_POS_X
+ );
+
+ INS_IMM64(FixupVal,
+ ((UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X),
+ IMM64_IMM9D_SIZE_X,
+ IMM64_IMM9D_INST_WORD_POS_X,
+ IMM64_IMM9D_VAL_POS_X
+ );
+
+ INS_IMM64(FixupVal,
+ ((UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X),
+ IMM64_IMM5C_SIZE_X,
+ IMM64_IMM5C_INST_WORD_POS_X,
+ IMM64_IMM5C_VAL_POS_X
+ );
+
+ INS_IMM64(FixupVal,
+ ((UINT32 *)Fixup + IMM64_IC_INST_WORD_X),
+ IMM64_IC_SIZE_X,
+ IMM64_IC_INST_WORD_POS_X,
+ IMM64_IC_VAL_POS_X
+ );
+
+ INS_IMM64(FixupVal,
+ ((UINT32 *)Fixup + IMM64_IMM41a_INST_WORD_X),
+ IMM64_IMM41a_SIZE_X,
+ IMM64_IMM41a_INST_WORD_POS_X,
+ IMM64_IMM41a_VAL_POS_X
+ );
+
+ INS_IMM64(FixupVal,
+ ((UINT32 *)Fixup + IMM64_IMM41b_INST_WORD_X),
+ IMM64_IMM41b_SIZE_X,
+ IMM64_IMM41b_INST_WORD_POS_X,
+ IMM64_IMM41b_VAL_POS_X
+ );
+
+ INS_IMM64(FixupVal,
+ ((UINT32 *)Fixup + IMM64_IMM41c_INST_WORD_X),
+ IMM64_IMM41c_SIZE_X,
+ IMM64_IMM41c_INST_WORD_POS_X,
+ IMM64_IMM41c_VAL_POS_X
+ );
+
+ INS_IMM64(FixupVal,
+ ((UINT32 *)Fixup + IMM64_SIGN_INST_WORD_X),
+ IMM64_SIGN_SIZE_X,
+ IMM64_SIGN_INST_WORD_POS_X,
+ IMM64_SIGN_VAL_POS_X
+ );
+
+ F64 = (UINT64 *) Fixup;
+ if (*FixupData != NULL) {
+ *FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));
+ *(UINT64 *)(*FixupData) = *F64;
+ *FixupData = *FixupData + sizeof(UINT64);
+ }
+ break;
+
+ default:
+ return EFI_UNSUPPORTED;
+ }
+
+ return EFI_SUCCESS;
+}
+
+BOOLEAN
+PeCoffLoaderImageFormatSupported (
+ IN UINT16 Machine
+ )
+/*++
+Routine Description:
+
+ Returns TRUE if the machine type of PE/COFF image is supported. Supported
+ does not mean the image can be executed it means the PE/COFF loader supports
+ loading and relocating of the image type. It's up to the caller to support
+ the entry point.
+
+ This function implies the basic PE/COFF loader/relocator supports IPF, EBC,
+ images. Calling the entry point in a correct mannor is up to the
+ consumer of this library.
+
+Arguments:
+
+ Machine - Machine type from the PE Header.
+
+Returns:
+
+ TRUE - if this PE/COFF loader can load the image
+ FALSE - if this PE/COFF loader cannot load the image
+
+--*/
+{
+ if ((Machine == EFI_IMAGE_MACHINE_IA64) || (Machine == EFI_IMAGE_MACHINE_EBC)) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
diff --git a/Core/CPU/IPF/PeCoffLoaderEx.h b/Core/CPU/IPF/PeCoffLoaderEx.h
new file mode 100644
index 0000000..fc14551
--- /dev/null
+++ b/Core/CPU/IPF/PeCoffLoaderEx.h
@@ -0,0 +1,87 @@
+/*++
+
+Copyright (c) 2004 - 2006, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ PeCoffLoaderEx.h
+
+Abstract:
+
+ Fixes Intel Itanium(TM) specific relocation types
+
+
+Revision History
+
+--*/
+
+#ifndef _PE_COFF_LOADER_EX_H_
+#define _PE_COFF_LOADER_EX_H_
+
+
+EFI_STATUS
+PeCoffLoaderRelocateImageEx (
+ IN UINT16 *Reloc,
+ IN OUT CHAR8 *Fixup,
+ IN OUT CHAR8 **FixupData,
+ IN UINT64 Adjust
+ )
+/*++
+
+Routine Description:
+
+ Performs an Itanium-based specific relocation fixup
+
+Arguments:
+
+ Reloc - Pointer to the relocation record
+
+ Fixup - Pointer to the address to fix up
+
+ FixupData - Pointer to a buffer to log the fixups
+
+ Adjust - The offset to adjust the fixup
+
+Returns:
+
+ Status code
+
+--*/
+;
+
+BOOLEAN
+PeCoffLoaderImageFormatSupported (
+ IN UINT16 Machine
+ )
+/*++
+Routine Description:
+
+ Returns TRUE if the machine type of PE/COFF image is supported. Supported
+ does not mean the image can be executed it means the PE/COFF loader supports
+ loading and relocating of the image type. It's up to the caller to support
+ the entry point.
+
+ This function implies the basic PE/COFF loader/relocator supports IPF, EBC,
+ images. Calling the entry point in a correct mannor is up to the
+ consumer of this library.
+
+Arguments:
+
+ Machine - Machine type from the PE Header.
+
+Returns:
+
+ TRUE - if this PE/COFF loader can load the image
+ FALSE - if this PE/COFF loader cannot load the image
+
+--*/
+;
+
+#endif
diff --git a/Core/CPU/IPF/PerformancePrimitives.s b/Core/CPU/IPF/PerformancePrimitives.s
new file mode 100644
index 0000000..5aeb886
--- /dev/null
+++ b/Core/CPU/IPF/PerformancePrimitives.s
@@ -0,0 +1,61 @@
+//++
+// Copyright (c) 2004, Intel Corporation
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Module Name:
+//
+// PerformancePrimitives.s
+//
+// Abstract:
+//
+//
+// Revision History:
+//
+//--
+
+.file "PerformancePrimitives.s"
+
+#include "IpfMacro.i"
+
+//-----------------------------------------------------------------------------
+//++
+// GetTimerValue
+//
+// Implementation of CPU-based time service
+//
+// On Entry :
+// EFI_STATUS
+// GetTimerValue (
+// OUT UINT64 *TimerValue
+// )
+//
+// Return Value:
+// r8 = Status
+// r9 = 0
+// r10 = 0
+// r11 = 0
+//
+// As per static calling conventions.
+//
+//--
+//---------------------------------------------------------------------------
+PROCEDURE_ENTRY (GetTimerValue)
+
+ NESTED_SETUP (1,8,0,0)
+ mov r8 = ar.itc;;
+ st8 [r32]= r8
+ mov r8 = r0
+ mov r9 = r0
+ mov r10 = r0
+ mov r11 = r0
+ NESTED_RETURN
+
+PROCEDURE_EXIT (GetTimerValue)
+//---------------------------------------------------------------------------
+
diff --git a/Core/CPU/IPF/Processor.h b/Core/CPU/IPF/Processor.h
new file mode 100644
index 0000000..8e49d37
--- /dev/null
+++ b/Core/CPU/IPF/Processor.h
@@ -0,0 +1,27 @@
+/*++
+
+Copyright (c) 2004, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+ Processor.h
+
+Abstract:
+ This file contains the Ipf processor specific definitions
+
+--*/
+
+#ifndef _PROCESSOR_H_
+#define _PROCESSOR_H_
+
+#define EFI_ACPI_RUNTIME_PAGE_ALLOCATION_ALIGNMENT (EFI_PAGE_SIZE * 2)
+
+#define DEFAULT_PAGE_ALLOCATION (EFI_PAGE_SIZE * 2)
+
+#endif \ No newline at end of file
diff --git a/Core/CPU/IPF/SwitchStack.s b/Core/CPU/IPF/SwitchStack.s
new file mode 100644
index 0000000..5de7e18
--- /dev/null
+++ b/Core/CPU/IPF/SwitchStack.s
@@ -0,0 +1,122 @@
+//++
+// Copyright (c) 2004, Intel Corporation
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Module Name:
+//
+// SwitchStack.s
+//
+// Abstract:
+//
+// Contains an implementation of a stack switch for the Itanium-based architecture.
+//
+//
+//
+// Revision History:
+//
+//--
+
+ .file "SwitchStack.s"
+
+#include <asm.h>
+#include <ia_64gen.h>
+
+// Define hardware RSE Configuration Register
+//
+// RS Configuration (RSC) bit field positions
+
+#define RSC_MODE 0
+#define RSC_PL 2
+#define RSC_BE 4
+// RSC bits 5-15 reserved
+#define RSC_MBZ0 5
+#define RSC_MBZ0_V 0x3ff
+#define RSC_LOADRS 16
+#define RSC_LOADRS_LEN 14
+// RSC bits 30-63 reserved
+#define RSC_MBZ1 30
+#define RSC_MBZ1_V 0x3ffffffffULL
+
+// RSC modes
+// Lazy
+#define RSC_MODE_LY (0x0)
+// Store intensive
+#define RSC_MODE_SI (0x1)
+// Load intensive
+#define RSC_MODE_LI (0x2)
+// Eager
+#define RSC_MODE_EA (0x3)
+
+// RSC Endian bit values
+#define RSC_BE_LITTLE 0
+#define RSC_BE_BIG 1
+
+// RSC while in kernel: enabled, little endian, pl = 0, eager mode
+#define RSC_KERNEL ((RSC_MODE_EA<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
+// Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode
+#define RSC_KERNEL_LAZ ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
+// RSE disabled: disabled, pl = 0, little endian, eager mode
+#define RSC_KERNEL_DISABLED ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
+
+
+//VOID
+//SwitchStacks (
+// VOID *ContinuationFunction,
+// UINTN Parameter,
+// UINTN NewTopOfStack,
+// UINTN NewBSPStore OPTIONAL
+//)
+///*++
+//
+//Input Arguments
+//
+// ContinuationFunction - This is a pointer to the PLABEL of the function that should be called once the
+// new stack has been created.
+// Parameter - The parameter to pass to the continuation function
+// NewTopOfStack - This is the new top of the memory stack for ensuing code. This is mandatory and
+// should be non-zero
+// NewBSPStore - This is the new BSP store for the ensuing code. It is optional on IA-32 and mandatory on Itanium-based platform.
+//
+//--*/
+
+PROCEDURE_ENTRY(SwitchStacks)
+
+ mov r16 = -0x10;;
+ and r16 = r34, r16;; // get new stack value in R16, 0 the last nibble.
+ mov r15 = r35;; // Get new BspStore into R15
+ mov r13 = r32;; // this is a pointer to the PLABEL of the continuation function.
+ mov r17 = r33;; // this is the parameter to pass to the continuation function
+
+ alloc r11=0,0,0,0 // Set 0-size frame
+ ;;
+ flushrs;;
+
+ mov r21 = RSC_KERNEL_DISABLED // for rse disable
+ ;;
+ mov ar.rsc = r21 // turn off RSE
+
+ add sp = r0, r16;; // transfer to the EFI stack
+ mov ar.bspstore = r15 // switch to EFI BSP
+ invala // change of ar.bspstore needs invala.
+
+ mov r18 = RSC_KERNEL_LAZ // RSC enabled, Lazy mode
+ ;;
+ mov ar.rsc = r18 // turn rse on, in kernel mode
+ ;;
+ alloc r11=0,0,1,0;; // alloc 0 outs going to ensuing DXE IPL service
+ mov out0 = r17
+ ld8 r16 = [r13],8;; // r16 = address of continuation function from the PLABEL
+ ld8 gp = [r13] // gp = gp of continuation function from the PLABEL
+ mov b6 = r16
+ ;;
+ br.call.sptk.few b0=b6;; // Call the continuation function
+ ;;
+PROCEDURE_EXIT(SwitchStacks)
+
+
diff --git a/Core/CPU/IPF/SwitchToCacheMode.c b/Core/CPU/IPF/SwitchToCacheMode.c
new file mode 100644
index 0000000..9f938d4
--- /dev/null
+++ b/Core/CPU/IPF/SwitchToCacheMode.c
@@ -0,0 +1,77 @@
+/*++
+
+Copyright (c) 2004, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ SwitchToCacheMode.c
+
+Abstract:
+
+ Ipf CAR specific function used to switch to cache mode for the later memory access
+
+Revision History
+
+--*/
+#include "Tiano.h"
+#include "PeiCore.h"
+#include "IpfCpuCore.i"
+
+extern
+SAL_RETURN_REGS
+GetHandOffStatus (
+ VOID
+ );
+
+VOID
+SwitchToCacheMode (
+ IN PEI_CORE_INSTANCE *CoreData
+ )
+/*++
+
+Routine Description:
+
+ Switch the PHIT pointers to cache mode after InstallPeiMemory in CAR.
+
+Arguments:
+
+ CoreData - The PEI core Private Data
+
+Returns:
+
+--*/
+{
+ EFI_HOB_HANDOFF_INFO_TABLE *Phit;
+
+ if (CoreData == NULL) {
+ //
+ // the first call with CoreData as NULL.
+ //
+ return;
+ }
+
+ if ((GetHandOffStatus().r10 & 0xFF) == RecoveryFn) {
+ CoreData->StackBase = CoreData->StackBase & CACHE_MODE_ADDRESS_MASK;
+ CoreData->HobList.Raw = (UINT8 *)((UINTN)CoreData->HobList.Raw & CACHE_MODE_ADDRESS_MASK);
+
+ //
+ // Change the PHIT pointer value to cache mode
+ //
+ Phit = CoreData->HobList.HandoffInformationTable;
+
+ Phit->EfiMemoryTop = Phit->EfiMemoryTop & CACHE_MODE_ADDRESS_MASK;
+ Phit->EfiFreeMemoryTop = Phit->EfiFreeMemoryTop & CACHE_MODE_ADDRESS_MASK;
+ Phit->EfiMemoryBottom = Phit->EfiMemoryBottom & CACHE_MODE_ADDRESS_MASK;
+ Phit->EfiFreeMemoryBottom = Phit->EfiFreeMemoryBottom & CACHE_MODE_ADDRESS_MASK;
+ Phit->EfiEndOfHobList = Phit->EfiEndOfHobList & CACHE_MODE_ADDRESS_MASK;
+ }
+
+ return;
+} \ No newline at end of file
diff --git a/Core/CPU/IPF/asm.h b/Core/CPU/IPF/asm.h
new file mode 100644
index 0000000..2db93d6
--- /dev/null
+++ b/Core/CPU/IPF/asm.h
@@ -0,0 +1,35 @@
+//
+//
+// Copyright (c) 2004, Intel Corporation
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Module Name:
+//
+// asm.h
+//
+// Abstract:
+//
+// This module contains generic macros for an assembly writer.
+//
+//
+// Revision History
+//
+#ifndef _ASM_H
+#define _ASM_H
+
+#define TRUE 1
+#define FALSE 0
+#define PROCEDURE_ENTRY(name) .##text; \
+ .##type name, @function; \
+ .##proc name; \
+ name::
+
+#define PROCEDURE_EXIT(name) .##endp name
+
+#endif // _ASM_H
diff --git a/Core/CPU/IPF/efijump.h b/Core/CPU/IPF/efijump.h
new file mode 100644
index 0000000..4a078ce
--- /dev/null
+++ b/Core/CPU/IPF/efijump.h
@@ -0,0 +1,112 @@
+/*++
+
+Copyright (c) 2004, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ EfiJump.h
+
+Abstract:
+
+ This is the Setjump/Longjump pair for an IA32 processor.
+
+--*/
+
+#ifndef _EFI_JUMP_H_
+#define _EFI_JUMP_H_
+
+#include EFI_GUID_DEFINITION (PeiTransferControl)
+
+//
+// NOTE:Set/LongJump needs to have this buffer start
+// at 16 byte boundary. Either fix the structure
+// which call this buffer or fix inside SetJump/LongJump
+// Choosing 1K buffer storage for now
+//
+typedef struct {
+ CHAR8 Buffer[1024];
+} EFI_JUMP_BUFFER;
+
+EFI_STATUS
+SetJump (
+ IN EFI_PEI_TRANSFER_CONTROL_PROTOCOL *This,
+ IN EFI_JUMP_BUFFER *Jump
+ )
+/*++
+
+Routine Description:
+
+ SetJump stores the current register set in the area pointed to
+by "save". It returns zero. Subsequent calls to "LongJump" will
+restore the registers and return non-zero to the same location.
+ On entry, r32 contains the pointer to the jmp_buffer
+
+Arguments:
+
+ This - Calling context
+ Jump - Jump buffer
+
+Returns:
+
+ Status code
+
+--*/
+;
+
+EFI_STATUS
+LongJump (
+ IN EFI_PEI_TRANSFER_CONTROL_PROTOCOL *This,
+ IN EFI_JUMP_BUFFER *Jump
+ )
+/*++
+
+Routine Description:
+
+ LongJump initializes the register set to the values saved by a
+previous 'SetJump' and jumps to the return location saved by that
+'SetJump'. This has the effect of unwinding the stack and returning
+for a second time to the 'SetJump'.
+
+Arguments:
+
+ This - Calling context
+ Jump - Jump buffer
+
+Returns:
+
+ Status code
+
+--*/
+;
+
+VOID
+RtPioICacheFlush (
+ IN VOID *StartAddress,
+ IN UINTN SizeInBytes
+ )
+/*++
+
+Routine Description:
+
+ Flushing the CPU instruction cache.
+
+Arguments:
+
+ StartAddress - Start address to flush
+ SizeInBytes - Length in bytes to flush
+
+Returns:
+
+ None
+
+--*/
+;
+
+#endif
diff --git a/Core/CPU/IPF/ia_64gen.h b/Core/CPU/IPF/ia_64gen.h
new file mode 100644
index 0000000..8e8d1a5
--- /dev/null
+++ b/Core/CPU/IPF/ia_64gen.h
@@ -0,0 +1,214 @@
+//
+//
+//
+// Copyright (c) 2004, Intel Corporation
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//Module Name: ia_64gen.h
+//
+//
+//Abstract:
+//
+//
+//
+//
+//Revision History
+//
+//
+#ifndef _IA64GEN_H
+#define _IA64GEN_H
+
+#define TT_UNAT 0
+#define C_PSR 0
+#define J_UNAT 0
+#define T_TYPE 0
+#define T_IPSR 0x8
+#define T_ISR 0x10
+#define T_IIP 0x18
+#define T_IFA 0x20
+#define T_IIPA 0x28
+#define T_IFS 0x30
+#define T_IIM 0x38
+#define T_RSC 0x40
+#define T_BSP 0x48
+#define T_BSPSTORE 0x50
+#define T_RNAT 0x58
+#define T_PFS 0x60
+#define T_KBSPSTORE 0x68
+#define T_UNAT 0x70
+#define T_CCV 0x78
+#define T_DCR 0x80
+#define T_PREDS 0x88
+#define T_NATS 0x90
+#define T_R1 0x98
+#define T_GP 0x98
+#define T_R2 0xa0
+#define T_R3 0xa8
+#define T_R4 0xb0
+#define T_R5 0xb8
+#define T_R6 0xc0
+#define T_R7 0xc8
+#define T_R8 0xd0
+#define T_R9 0xd8
+#define T_R10 0xe0
+#define T_R11 0xe8
+#define T_R12 0xf0
+#define T_SP 0xf0
+#define T_R13 0xf8
+#define T_R14 0x100
+#define T_R15 0x108
+#define T_R16 0x110
+#define T_R17 0x118
+#define T_R18 0x120
+#define T_R19 0x128
+#define T_R20 0x130
+#define T_R21 0x138
+#define T_R22 0x140
+#define T_R23 0x148
+#define T_R24 0x150
+#define T_R25 0x158
+#define T_R26 0x160
+#define T_R27 0x168
+#define T_R28 0x170
+#define T_R29 0x178
+#define T_R30 0x180
+#define T_R31 0x188
+#define T_F2 0x1f0
+#define T_F3 0x200
+#define T_F4 0x210
+#define T_F5 0x220
+#define T_F6 0x230
+#define T_F7 0x240
+#define T_F8 0x250
+#define T_F9 0x260
+#define T_F10 0x270
+#define T_F11 0x280
+#define T_F12 0x290
+#define T_F13 0x2a0
+#define T_F14 0x2b0
+#define T_F15 0x2c0
+#define T_F16 0x2d0
+#define T_F17 0x2e0
+#define T_F18 0x2f0
+#define T_F19 0x300
+#define T_F20 0x310
+#define T_F21 0x320
+#define T_F22 0x330
+#define T_F23 0x340
+#define T_F24 0x350
+#define T_F25 0x360
+#define T_F26 0x370
+#define T_F27 0x380
+#define T_F28 0x390
+#define T_F29 0x3a0
+#define T_F30 0x3b0
+#define T_F31 0x3c0
+#define T_FPSR 0x1e0
+#define T_B0 0x190
+#define T_B1 0x198
+#define T_B2 0x1a0
+#define T_B3 0x1a8
+#define T_B4 0x1b0
+#define T_B5 0x1b8
+#define T_B6 0x1c0
+#define T_B7 0x1c8
+#define T_EC 0x1d0
+#define T_LC 0x1d8
+#define J_NATS 0x8
+#define J_PFS 0x10
+#define J_BSP 0x18
+#define J_RNAT 0x20
+#define J_PREDS 0x28
+#define J_LC 0x30
+#define J_R4 0x38
+#define J_R5 0x40
+#define J_R6 0x48
+#define J_R7 0x50
+#define J_SP 0x58
+#define J_F2 0x60
+#define J_F3 0x70
+#define J_F4 0x80
+#define J_F5 0x90
+#define J_F16 0xa0
+#define J_F17 0xb0
+#define J_F18 0xc0
+#define J_F19 0xd0
+#define J_F20 0xe0
+#define J_F21 0xf0
+#define J_F22 0x100
+#define J_F23 0x110
+#define J_F24 0x120
+#define J_F25 0x130
+#define J_F26 0x140
+#define J_F27 0x150
+#define J_F28 0x160
+#define J_F29 0x170
+#define J_F30 0x180
+#define J_F31 0x190
+#define J_FPSR 0x1a0
+#define J_B0 0x1a8
+#define J_B1 0x1b0
+#define J_B2 0x1b8
+#define J_B3 0x1c0
+#define J_B4 0x1c8
+#define J_B5 0x1d0
+#define TRAP_FRAME_LENGTH 0x3d0
+#define C_UNAT 0x28
+#define C_NATS 0x30
+#define C_PFS 0x8
+#define C_BSPSTORE 0x10
+#define C_RNAT 0x18
+#define C_RSC 0x20
+#define C_PREDS 0x38
+#define C_LC 0x40
+#define C_DCR 0x48
+#define C_R1 0x50
+#define C_GP 0x50
+#define C_R4 0x58
+#define C_R5 0x60
+#define C_R6 0x68
+#define C_R7 0x70
+#define C_SP 0x78
+#define C_R13 0x80
+#define C_F2 0x90
+#define C_F3 0xa0
+#define C_F4 0xb0
+#define C_F5 0xc0
+#define C_F16 0xd0
+#define C_F17 0xe0
+#define C_F18 0xf0
+#define C_F19 0x100
+#define C_F20 0x110
+#define C_F21 0x120
+#define C_F22 0x130
+#define C_F23 0x140
+#define C_F24 0x150
+#define C_F25 0x160
+#define C_F26 0x170
+#define C_F27 0x180
+#define C_F28 0x190
+#define C_F29 0x1a0
+#define C_F30 0x1b0
+#define C_F31 0x1c0
+#define C_FPSR 0x1d0
+#define C_B0 0x1d8
+#define C_B1 0x1e0
+#define C_B2 0x1e8
+#define C_B3 0x1f0
+#define C_B4 0x1f8
+#define C_B5 0x200
+#define TT_R2 0x8
+#define TT_R3 0x10
+#define TT_R8 0x18
+#define TT_R9 0x20
+#define TT_R10 0x28
+#define TT_R11 0x30
+#define TT_R14 0x38
+
+#endif _IA64GEN_H
diff --git a/Core/CPU/IPF/pioflush.s b/Core/CPU/IPF/pioflush.s
new file mode 100644
index 0000000..0f0d760
--- /dev/null
+++ b/Core/CPU/IPF/pioflush.s
@@ -0,0 +1,106 @@
+//++
+// Copyright (c) 2004, Intel Corporation
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Module Name:
+//
+// pioflush.s
+//
+// Abstract:
+//
+//
+// Revision History:
+//
+//--
+
+ .file "pioflush.c"
+ .radix D
+ .section .text, "ax", "progbits"
+ .align 32
+ .section .pdata, "a", "progbits"
+ .align 4
+ .section .xdata, "a", "progbits"
+ .align 8
+ .section .data, "wa", "progbits"
+ .align 16
+ .section .rdata, "a", "progbits"
+ .align 16
+ .section .bss, "wa", "nobits"
+ .align 16
+ .section .tls$, "was", "progbits"
+ .align 16
+ .section .sdata, "was", "progbits"
+ .align 16
+ .section .sbss, "was", "nobits"
+ .align 16
+ .section .srdata, "as", "progbits"
+ .align 16
+ .section .rdata, "a", "progbits"
+ .align 16
+ .section .rtcode, "ax", "progbits"
+ .align 32
+ .type RtPioICacheFlush# ,@function
+ .global RtPioICacheFlush#
+// Function compile flags: /Ogsy
+ .section .rtcode
+
+// Begin code for function: RtPioICacheFlush:
+ .proc RtPioICacheFlush#
+ .align 32
+RtPioICacheFlush:
+// File e:\tmp\pioflush.c
+ { .mii //R-Addr: 0X00
+ alloc r3=2, 0, 0, 0 //11, 00000002H
+ cmp4.leu p0,p6=32, r33;; //15, 00000020H
+ (p6) mov r33=32;; //16, 00000020H
+ }
+ { .mii //R-Addr: 0X010
+ nop.m 0
+ zxt4 r29=r33;; //21
+ dep.z r30=r29, 0, 5;; //21, 00000005H
+ }
+ { .mii //R-Addr: 0X020
+ cmp4.eq p0,p7=r0, r30 //21
+ shr.u r28=r29, 5;; //19, 00000005H
+ (p7) adds r28=1, r28;; //22, 00000001H
+ }
+ { .mii //R-Addr: 0X030
+ nop.m 0
+ shl r27=r28, 5;; //25, 00000005H
+ zxt4 r26=r27;; //25
+ }
+ { .mfb //R-Addr: 0X040
+ add r31=r26, r32 //25
+ nop.f 0
+ nop.b 0
+ }
+$L143:
+ { .mii //R-Addr: 0X050
+ fc r32 //27
+ adds r32=32, r32;; //28, 00000020H
+ cmp.ltu p14,p15=r32, r31 //29
+ }
+ { .mfb //R-Addr: 0X060
+ nop.m 0
+ nop.f 0
+ (p14) br.cond.dptk.few $L143#;; //29, 880000/120000
+ }
+ { .mmi
+ sync.i;;
+ srlz.i
+ nop.i 0;;
+ }
+ { .mfb //R-Addr: 0X070
+ nop.m 0
+ nop.f 0
+ br.ret.sptk.few b0;; //31
+ }
+// End code for function:
+ .endp RtPioICacheFlush#
+// END
diff --git a/Core/CPU/IPF/processor.c b/Core/CPU/IPF/processor.c
new file mode 100644
index 0000000..9740948
--- /dev/null
+++ b/Core/CPU/IPF/processor.c
@@ -0,0 +1,118 @@
+/*++
+
+Copyright (c) 2004, Intel Corporation
+All rights reserved. This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ Processor.c
+
+Abstract:
+
+--*/
+
+#include "Tiano.h"
+#include "EfiJump.h"
+#include "PeiHob.h"
+#include EFI_GUID_DEFINITION (PeiFlushInstructionCache)
+#include EFI_GUID_DEFINITION (PeiTransferControl)
+
+EFI_STATUS
+WinNtFlushInstructionCacheFlush (
+ IN EFI_PEI_FLUSH_INSTRUCTION_CACHE_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS Start,
+ IN UINT64 Length
+ );
+
+EFI_PEI_TRANSFER_CONTROL_PROTOCOL mTransferControl = {
+ SetJump,
+ LongJump,
+ sizeof (EFI_JUMP_BUFFER)
+};
+
+EFI_PEI_FLUSH_INSTRUCTION_CACHE_PROTOCOL mFlushInstructionCache = {
+ WinNtFlushInstructionCacheFlush
+};
+
+EFI_STATUS
+InstallEfiPeiTransferControl (
+ IN OUT EFI_PEI_TRANSFER_CONTROL_PROTOCOL **This
+ )
+/*++
+
+Routine Description:
+
+ Installs the pointer to the transfer control mechanism
+
+Arguments:
+
+ This - Pointer to transfer control mechanism.
+
+Returns:
+
+ EFI_SUCCESS - Successfully installed.
+
+--*/
+{
+ *This = &mTransferControl;
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+InstallEfiPeiFlushInstructionCache (
+ IN OUT EFI_PEI_FLUSH_INSTRUCTION_CACHE_PROTOCOL **This
+ )
+/*++
+
+Routine Description:
+
+ Installs the pointer to the flush instruction cache mechanism
+
+Arguments:
+
+ This - Pointer to flush instruction cache mechanism.
+
+Returns:
+
+ EFI_SUCCESS - Successfully installed
+
+--*/
+{
+ *This = &mFlushInstructionCache;
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+WinNtFlushInstructionCacheFlush (
+ IN EFI_PEI_FLUSH_INSTRUCTION_CACHE_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS Start,
+ IN UINT64 Length
+ )
+/*++
+
+Routine Description:
+
+ This routine would provide support for flushing the CPU instruction cache.
+
+Arguments:
+
+ This - Pointer to CPU Architectural Protocol interface
+ Start - Start adddress in memory to flush
+ Length - Length of memory to flush
+
+Returns:
+
+ Status
+ EFI_SUCCESS
+
+--*/
+{
+ RtPioICacheFlush ((UINT8 *) Start, (UINTN) Length);
+ return EFI_SUCCESS;
+}
diff --git a/Core/CPU/IPF/setjmp.s b/Core/CPU/IPF/setjmp.s
new file mode 100644
index 0000000..ee27ca7
--- /dev/null
+++ b/Core/CPU/IPF/setjmp.s
@@ -0,0 +1,325 @@
+//++
+// Copyright (c) 2004, Intel Corporation
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// Module Name:
+//
+// setjmp.s
+//
+// Abstract:
+//
+// Contains an implementation of setjmp and longjmp for the
+// Itanium-based architecture.
+//
+//
+//
+// Revision History:
+//
+//--
+
+ .file "setjmp.s"
+
+#include <asm.h>
+#include <ia_64gen.h>
+
+// int SetJump(struct jmp_buffer save)
+//
+// Setup a non-local goto.
+//
+// Description:
+//
+// SetJump stores the current register set in the area pointed to
+// by "save". It returns zero. Subsequent calls to "LongJump" will
+// restore the registers and return non-zero to the same location.
+//
+// On entry, r32 contains the pointer to the jmp_buffer
+//
+
+PROCEDURE_ENTRY(SetJump)
+ //
+ // Make sure buffer is aligned at 16byte boundary
+ //
+ mov r32 = r33
+
+ add r10 = -0x10,r0 ;; // mask the lower 4 bits
+ and r32 = r32, r10;;
+ add r32 = 0x10, r32;; // move to next 16 byte boundary
+
+ add r10 = J_PREDS, r32 // skip Unats & pfs save area
+ add r11 = J_BSP, r32
+ //
+ // save immediate context
+ //
+ mov r2 = ar.bsp // save backing store pointer
+ mov r3 = pr // save predicates
+ ;;
+ //
+ // save user Unat register
+ //
+ mov r16 = ar.lc // save loop count register
+ mov r14 = ar.unat // save user Unat register
+
+ st8 [r10] = r3, J_LC-J_PREDS
+ st8 [r11] = r2, J_R4-J_BSP
+ ;;
+ st8 [r10] = r16, J_R5-J_LC
+ st8 [r32] = r14, J_NATS // Note: Unat at the
+ // beginning of the save area
+ mov r15 = ar.pfs
+ ;;
+ //
+ // save preserved general registers & NaT's
+ //
+ st8.spill [r11] = r4, J_R6-J_R4
+ ;;
+ st8.spill [r10] = r5, J_R7-J_R5
+ ;;
+ st8.spill [r11] = r6, J_SP-J_R6
+ ;;
+ st8.spill [r10] = r7, J_F3-J_R7
+ ;;
+ st8.spill [r11] = sp, J_F2-J_SP
+ ;;
+ //
+ // save spilled Unat and pfs registers
+ //
+ mov r2 = ar.unat // save Unat register after spill
+ ;;
+ st8 [r32] = r2, J_PFS-J_NATS // save unat for spilled regs
+ ;;
+ st8 [r32] = r15 // save pfs
+ //
+ // save floating registers
+ //
+ stf.spill [r11] = f2, J_F4-J_F2
+ stf.spill [r10] = f3, J_F5-J_F3
+ ;;
+ stf.spill [r11] = f4, J_F16-J_F4
+ stf.spill [r10] = f5, J_F17-J_F5
+ ;;
+ stf.spill [r11] = f16, J_F18-J_F16
+ stf.spill [r10] = f17, J_F19-J_F17
+ ;;
+ stf.spill [r11] = f18, J_F20-J_F18
+ stf.spill [r10] = f19, J_F21-J_F19
+ ;;
+ stf.spill [r11] = f20, J_F22-J_F20
+ stf.spill [r10] = f21, J_F23-J_F21
+ ;;
+ stf.spill [r11] = f22, J_F24-J_F22
+ stf.spill [r10] = f23, J_F25-J_F23
+ ;;
+ stf.spill [r11] = f24, J_F26-J_F24
+ stf.spill [r10] = f25, J_F27-J_F25
+ ;;
+ stf.spill [r11] = f26, J_F28-J_F26
+ stf.spill [r10] = f27, J_F29-J_F27
+ ;;
+ stf.spill [r11] = f28, J_F30-J_F28
+ stf.spill [r10] = f29, J_F31-J_F29
+ ;;
+ stf.spill [r11] = f30, J_FPSR-J_F30
+ stf.spill [r10] = f31, J_B0-J_F31 // size of f31 + fpsr
+ //
+ // save FPSR register & branch registers
+ //
+ mov r2 = ar.fpsr // save fpsr register
+ mov r3 = b0
+ ;;
+ st8 [r11] = r2, J_B1-J_FPSR
+ st8 [r10] = r3, J_B2-J_B0
+ mov r2 = b1
+ mov r3 = b2
+ ;;
+ st8 [r11] = r2, J_B3-J_B1
+ st8 [r10] = r3, J_B4-J_B2
+ mov r2 = b3
+ mov r3 = b4
+ ;;
+ st8 [r11] = r2, J_B5-J_B3
+ st8 [r10] = r3
+ mov r2 = b5
+ ;;
+ st8 [r11] = r2
+ ;;
+ //
+ // return
+ //
+ mov r8 = r0 // return 0 from setjmp
+ mov ar.unat = r14 // restore unat
+ br.ret.sptk b0
+
+PROCEDURE_EXIT(SetJump)
+
+
+//
+// void LongJump(struct jmp_buffer *)
+//
+// Perform a non-local goto.
+//
+// Description:
+//
+// LongJump initializes the register set to the values saved by a
+// previous 'SetJump' and jumps to the return location saved by that
+// 'SetJump'. This has the effect of unwinding the stack and returning
+// for a second time to the 'SetJump'.
+//
+
+PROCEDURE_ENTRY(LongJump)
+ //
+ // Make sure buffer is aligned at 16byte boundary
+ //
+ mov r32 = r33
+
+ add r10 = -0x10,r0 ;; // mask the lower 4 bits
+ and r32 = r32, r10;;
+ add r32 = 0x10, r32;; // move to next 16 byte boundary
+
+ //
+ // caching the return value as we do invala in the end
+ //
+/// mov r8 = r33 // return value
+ mov r8 = 1 // For now return hard coded 1
+
+ //
+ // get immediate context
+ //
+ mov r14 = ar.rsc // get user RSC conf
+ add r10 = J_PFS, r32 // get address of pfs
+ add r11 = J_NATS, r32
+ ;;
+ ld8 r15 = [r10], J_BSP-J_PFS // get pfs
+ ld8 r2 = [r11], J_LC-J_NATS // get unat for spilled regs
+ ;;
+ mov ar.unat = r2
+ ;;
+ ld8 r16 = [r10], J_PREDS-J_BSP // get backing store pointer
+ mov ar.rsc = r0 // put RSE in enforced lazy
+ mov ar.pfs = r15
+ ;;
+
+ //
+ // while returning from longjmp the BSPSTORE and BSP needs to be
+ // same and discard all the registers allocated after we did
+ // setjmp. Also, we need to generate the RNAT register since we
+ // did not flushed the RSE on setjmp.
+ //
+ mov r17 = ar.bspstore // get current BSPSTORE
+ ;;
+ cmp.ltu p6,p7 = r17, r16 // is it less than BSP of
+(p6) br.spnt.few .flush_rse
+ mov r19 = ar.rnat // get current RNAT
+ ;;
+ loadrs // invalidate dirty regs
+ br.sptk.many .restore_rnat // restore RNAT
+
+.flush_rse:
+ flushrs
+ ;;
+ mov r19 = ar.rnat // get current RNAT
+ mov r17 = r16 // current BSPSTORE
+ ;;
+.restore_rnat:
+ //
+ // check if RNAT is saved between saved BSP and curr BSPSTORE
+ //
+ dep r18 = 1,r16,3,6 // get RNAT address
+ ;;
+ cmp.ltu p8,p9 = r18, r17 // RNAT saved on RSE
+ ;;
+(p8) ld8 r19 = [r18] // get RNAT from RSE
+ ;;
+ mov ar.bspstore = r16 // set new BSPSTORE
+ ;;
+ mov ar.rnat = r19 // restore RNAT
+ mov ar.rsc = r14 // restore RSC conf
+
+
+ ld8 r3 = [r11], J_R4-J_LC // get lc register
+ ld8 r2 = [r10], J_R5-J_PREDS // get predicates
+ ;;
+ mov pr = r2, -1
+ mov ar.lc = r3
+ //
+ // restore preserved general registers & NaT's
+ //
+ ld8.fill r4 = [r11], J_R6-J_R4
+ ;;
+ ld8.fill r5 = [r10], J_R7-J_R5
+ ld8.fill r6 = [r11], J_SP-J_R6
+ ;;
+ ld8.fill r7 = [r10], J_F2-J_R7
+ ld8.fill sp = [r11], J_F3-J_SP
+ ;;
+ //
+ // restore floating registers
+ //
+ ldf.fill f2 = [r10], J_F4-J_F2
+ ldf.fill f3 = [r11], J_F5-J_F3
+ ;;
+ ldf.fill f4 = [r10], J_F16-J_F4
+ ldf.fill f5 = [r11], J_F17-J_F5
+ ;;
+ ldf.fill f16 = [r10], J_F18-J_F16
+ ldf.fill f17 = [r11], J_F19-J_F17
+ ;;
+ ldf.fill f18 = [r10], J_F20-J_F18
+ ldf.fill f19 = [r11], J_F21-J_F19
+ ;;
+ ldf.fill f20 = [r10], J_F22-J_F20
+ ldf.fill f21 = [r11], J_F23-J_F21
+ ;;
+ ldf.fill f22 = [r10], J_F24-J_F22
+ ldf.fill f23 = [r11], J_F25-J_F23
+ ;;
+ ldf.fill f24 = [r10], J_F26-J_F24
+ ldf.fill f25 = [r11], J_F27-J_F25
+ ;;
+ ldf.fill f26 = [r10], J_F28-J_F26
+ ldf.fill f27 = [r11], J_F29-J_F27
+ ;;
+ ldf.fill f28 = [r10], J_F30-J_F28
+ ldf.fill f29 = [r11], J_F31-J_F29
+ ;;
+ ldf.fill f30 = [r10], J_FPSR-J_F30
+ ldf.fill f31 = [r11], J_B0-J_F31 ;;
+
+ //
+ // restore branch registers and fpsr
+ //
+ ld8 r16 = [r10], J_B1-J_FPSR // get fpsr
+ ld8 r17 = [r11], J_B2-J_B0 // get return pointer
+ ;;
+ mov ar.fpsr = r16
+ mov b0 = r17
+ ld8 r2 = [r10], J_B3-J_B1
+ ld8 r3 = [r11], J_B4-J_B2
+ ;;
+ mov b1 = r2
+ mov b2 = r3
+ ld8 r2 = [r10], J_B5-J_B3
+ ld8 r3 = [r11]
+ ;;
+ mov b3 = r2
+ mov b4 = r3
+ ld8 r2 = [r10]
+ ld8 r21 = [r32] // get user unat
+ ;;
+ mov b5 = r2
+ mov ar.unat = r21
+
+ //
+ // invalidate ALAT
+ //
+ invala ;;
+
+ br.ret.sptk b0
+PROCEDURE_EXIT(LongJump)
+
+
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-08 00:09:04 +0000