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-rw-r--r--MiscFramework/Ppi/AtaController/AtaController.c35
-rw-r--r--MiscFramework/Ppi/AtaController/AtaController.h62
-rw-r--r--MiscFramework/Ppi/AtaPolicy/AtaPolicy.c35
-rw-r--r--MiscFramework/Ppi/AtaPolicy/AtaPolicy.h45
-rw-r--r--MiscFramework/Ppi/Capsule/Capsule.c36
-rw-r--r--MiscFramework/Ppi/Capsule/Capsule.h69
-rw-r--r--MiscFramework/Ppi/FrameworkPpiLib.cif21
-rw-r--r--MiscFramework/Ppi/FrameworkPpiLib.mak60
-rw-r--r--MiscFramework/Ppi/FrameworkPpiLib.sdl28
-rw-r--r--MiscFramework/Ppi/PlatformMemoryRange/PlatformMemoryRange.c35
-rw-r--r--MiscFramework/Ppi/PlatformMemoryRange/PlatformMemoryRange.h156
-rw-r--r--MiscFramework/Ppi/PlatformMemorySize/PlatformMemorySize.c35
-rw-r--r--MiscFramework/Ppi/PlatformMemorySize/PlatformMemorySize.h55
-rw-r--r--MiscFramework/Ppi/SmbusPolicy/SmbusPolicy.c35
-rw-r--r--MiscFramework/Ppi/SmbusPolicy/SmbusPolicy.h48
-rw-r--r--MiscFramework/Ppi/SmmControl/SmmControl.c35
-rw-r--r--MiscFramework/Ppi/SmmControl/SmmControl.h67
-rw-r--r--MiscFramework/Ppi/SmmControlLib.cif11
-rw-r--r--MiscFramework/Ppi/SmmControlLib.mak72
-rw-r--r--MiscFramework/Ppi/SmmControlLib.sdl28
20 files changed, 968 insertions, 0 deletions
diff --git a/MiscFramework/Ppi/AtaController/AtaController.c b/MiscFramework/Ppi/AtaController/AtaController.c
new file mode 100644
index 0000000..77d1743
--- /dev/null
+++ b/MiscFramework/Ppi/AtaController/AtaController.c
@@ -0,0 +1,35 @@
+/*++
+ This file contains 'Framework Code' and is licensed as such
+ under the terms of your license agreement with Intel or your
+ vendor. This file may not be modified, except as allowed by
+ additional terms of your license agreement.
+--*/
+/*++
+
+Copyright (c) 1999 - 2002 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+ AtaController.c
+
+Abstract:
+
+ ATA Controller PPI GUID as defined in EFI 2.0
+
+--*/
+
+#include "Tiano.h"
+#include "Pei.h"
+#include EFI_PPI_DEFINITION (AtaController)
+
+EFI_GUID gPeiAtaControllerPpiGuid = PEI_ATA_CONTROLLER_PPI_GUID;
+
+EFI_GUID_STRING(&gPeiAtaControllerPpiGuid, "AtaController", "ATA Controller PPI");
diff --git a/MiscFramework/Ppi/AtaController/AtaController.h b/MiscFramework/Ppi/AtaController/AtaController.h
new file mode 100644
index 0000000..568fa71
--- /dev/null
+++ b/MiscFramework/Ppi/AtaController/AtaController.h
@@ -0,0 +1,62 @@
+//
+// This file contains 'Framework Code' and is licensed as such
+// under the terms of your license agreement with Intel or your
+// vendor. This file may not be modified, except as allowed by
+// additional terms of your license agreement.
+//
+/*++
+
+Copyright (c) 1999 - 2002 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+ AtaController.h
+
+Abstract:
+
+ ATA Controller PPI as defined in EFI 2.0
+
+ This code abstracts the PEI core to provide ATA services.
+
+--*/
+
+#ifndef _PEI_ATA_CONTROLLER_PPI_H_
+#define _PEI_ATA_CONTROLLER_PPI_H_
+
+#define PEI_ATA_CONTROLLER_PPI_GUID \
+ { \
+ 0xa1e2176f, 0xcbda, 0x4f32, 0x87, 0x56, 0x7d, 0x7a, 0xe5, 0x22, 0xd6, 0x93 \
+ }
+
+#define PEI_ICH_IDE_NONE 0x00
+#define PEI_ICH_IDE_PRIMARY 0x01
+#define PEI_ICH_IDE_SECONDARY 0x02
+#define PEI_ICH_SATA_NONE 0x04
+#define PEI_ICH_SATA_PRIMARY 0x08
+#define PEI_ICH_SATA_SECONDARY 0x010
+
+EFI_FORWARD_DECLARATION (PEI_ATA_CONTROLLER_PPI);
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_ENABLE_ATA) (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_ATA_CONTROLLER_PPI * This,
+ IN UINT8 ChannelMask
+ );
+
+typedef struct _PEI_ATA_CONTROLLER_PPI {
+ PEI_ENABLE_ATA EnableAtaChannel;
+} PEI_ATA_CONTROLLER_PPI;
+
+extern EFI_GUID gPeiAtaControllerPpiGuid;
+
+#endif
diff --git a/MiscFramework/Ppi/AtaPolicy/AtaPolicy.c b/MiscFramework/Ppi/AtaPolicy/AtaPolicy.c
new file mode 100644
index 0000000..a8e6be7
--- /dev/null
+++ b/MiscFramework/Ppi/AtaPolicy/AtaPolicy.c
@@ -0,0 +1,35 @@
+/*++
+ This file contains 'Framework Code' and is licensed as such
+ under the terms of your license agreement with Intel or your
+ vendor. This file may not be modified, except as allowed by
+ additional terms of your license agreement.
+--*/
+/*++
+
+Copyright (c) 1999 - 2002 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+ AtaPolicy.c
+
+Abstract:
+
+ ATA Policy PPI GUID as defined in EFI 2.0
+
+--*/
+
+#include "Tiano.h"
+#include "Pei.h"
+#include EFI_PPI_DEFINITION (AtaPolicy)
+
+EFI_GUID gPeiAtaPolicyPpiGuid = PEI_ATA_POLICY_PPI_GUID;
+
+EFI_GUID_STRING(&gPeiAtaPolicyPpiGuid, "AtaPolicy", "ATA Policy PPI");
diff --git a/MiscFramework/Ppi/AtaPolicy/AtaPolicy.h b/MiscFramework/Ppi/AtaPolicy/AtaPolicy.h
new file mode 100644
index 0000000..62fb8da
--- /dev/null
+++ b/MiscFramework/Ppi/AtaPolicy/AtaPolicy.h
@@ -0,0 +1,45 @@
+//
+// This file contains 'Framework Code' and is licensed as such
+// under the terms of your license agreement with Intel or your
+// vendor. This file may not be modified, except as allowed by
+// additional terms of your license agreement.
+//
+/*++
+
+Copyright (c) 1999 - 2002 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+ AtaPolicy.h
+
+Abstract:
+
+ ATA Policy PPI as defined in EFI 2.0
+
+--*/
+
+#ifndef _PEI_ATA_POLICY_PPI_H
+#define _PEI_ATA_POLICY_PPI_H
+
+#define PEI_ATA_POLICY_PPI_GUID \
+ { \
+ 0x1b8ddea4, 0xdeb2, 0x4152, 0x91, 0xc2, 0xb7, 0x3c, 0xb1, 0x6c, 0xe4, 0x64 \
+ }
+
+EFI_FORWARD_DECLARATION (PEI_ATA_POLICY_PPI);
+
+typedef struct _PEI_ATA_POLICY_PPI {
+ UINTN BaseAddress;
+} PEI_ATA_POLICY_PPI;
+
+extern EFI_GUID gPeiAtaPolicyPpiGuid;
+
+#endif
diff --git a/MiscFramework/Ppi/Capsule/Capsule.c b/MiscFramework/Ppi/Capsule/Capsule.c
new file mode 100644
index 0000000..29e18a9
--- /dev/null
+++ b/MiscFramework/Ppi/Capsule/Capsule.c
@@ -0,0 +1,36 @@
+/*++
+ This file contains 'Framework Code' and is licensed as such
+ under the terms of your license agreement with Intel or your
+ vendor. This file may not be modified, except as allowed by
+ additional terms of your license agreement.
+--*/
+/*++
+
+Copyright (c) 1999 - 2002 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+ Capsule.c
+
+Abstract:
+
+ Capsule PPI GUID declaration.
+
+--*/
+
+#include "Tiano.h"
+#include "PeiBind.h"
+#include "PeiApi.h"
+#include EFI_PPI_DEFINITION (Capsule)
+
+EFI_GUID gPeiCapsulePpiGuid = PEI_CAPSULE_PPI_GUID;
+
+EFI_GUID_STRING(&gPeiCapsulePpiGuid, "Capsule", "Capsule Update PPI");
diff --git a/MiscFramework/Ppi/Capsule/Capsule.h b/MiscFramework/Ppi/Capsule/Capsule.h
new file mode 100644
index 0000000..aea915b
--- /dev/null
+++ b/MiscFramework/Ppi/Capsule/Capsule.h
@@ -0,0 +1,69 @@
+//
+// This file contains 'Framework Code' and is licensed as such
+// under the terms of your license agreement with Intel or your
+// vendor. This file may not be modified, except as allowed by
+// additional terms of your license agreement.
+//
+/*++
+
+Copyright (c) 1999 - 2002 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+ Capsule.h
+
+Abstract:
+
+ Capsule PPI definitions.
+
+--*/
+
+#ifndef _PEI_CAPSULE_PPI_H_
+#define _PEI_CAPSULE_PPI_H_
+
+#define PEI_CAPSULE_PPI_GUID \
+ { \
+ 0x3acf33ee, 0xd892, 0x40f4, 0xa2, 0xfc, 0x38, 0x54, 0xd2, 0xe1, 0x32, 0x3d \
+ }
+
+EFI_FORWARD_DECLARATION (PEI_CAPSULE_PPI);
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_CAPSULE_COALESCE) (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN OUT VOID **MemoryBase,
+ IN OUT UINTN *MemSize
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_CAPSULE_CREATE_STATE) (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN VOID *CapsuleBase, // returned from coalesce
+ IN UINTN CapsuleSize // returned from coalesce
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_CAPSULE_CHECK_CAPSULE_UPDATE) (
+ IN EFI_PEI_SERVICES **PeiServices
+ );
+
+typedef struct _PEI_CAPSULE_PPI {
+ PEI_CAPSULE_COALESCE Coalesce;
+ PEI_CAPSULE_CHECK_CAPSULE_UPDATE CheckCapsuleUpdate;
+ PEI_CAPSULE_CREATE_STATE CreateState;
+} PEI_CAPSULE_PPI;
+
+extern EFI_GUID gPeiCapsulePpiGuid;
+
+#endif // #ifndef _PEI_CAPSULE_PPI_H_
diff --git a/MiscFramework/Ppi/FrameworkPpiLib.cif b/MiscFramework/Ppi/FrameworkPpiLib.cif
new file mode 100644
index 0000000..f8aed90
--- /dev/null
+++ b/MiscFramework/Ppi/FrameworkPpiLib.cif
@@ -0,0 +1,21 @@
+<component>
+ name = "FrameworkPpiLib"
+ category = ModulePart
+ LocalRoot = "MiscFramework\Ppi"
+ RefName = "FrameworkPpiLib"
+[files]
+"FrameworkPpiLib.sdl"
+"FrameworkPpiLib.mak"
+"PlatformMemoryRange\PlatformMemoryRange.c"
+"PlatformMemoryRange\PlatformMemoryRange.h"
+"PlatformMemorySize\PlatformMemorySize.c"
+"PlatformMemorySize\PlatformMemorySize.h"
+"Capsule\Capsule.c"
+"Capsule\Capsule.h"
+"SmbusPolicy\SmbusPolicy.h"
+"SmbusPolicy\SmbusPolicy.c"
+"AtaController\AtaController.c"
+"AtaController\AtaController.h"
+"AtaPolicy\AtaPolicy.c"
+"AtaPolicy\AtaPolicy.h"
+<endComponent>
diff --git a/MiscFramework/Ppi/FrameworkPpiLib.mak b/MiscFramework/Ppi/FrameworkPpiLib.mak
new file mode 100644
index 0000000..b292eaf
--- /dev/null
+++ b/MiscFramework/Ppi/FrameworkPpiLib.mak
@@ -0,0 +1,60 @@
+#**********************************************************************
+#**********************************************************************
+#** **
+#** (C)Copyright 1985-2006, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 6145-F Northbelt Pkwy, Norcross, GA 30071 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#**********************************************************************
+#**********************************************************************
+
+#**********************************************************************
+# $Header: /Alaska/SOURCE/Modules/MPG/Calpella/MiscFramework/FrameworkPpiLib/FrameworkPpiLib.mak 1 10/15/08 2:19p Fasihm $
+#
+# $Revision: 1 $
+#
+# $Date: 10/15/08 2:19p $
+#**********************************************************************
+# Revision History
+# ----------------
+#
+#**********************************************************************
+#<AMI_FHDR_START>
+#
+# Name: FrameworkPpiLib.mak
+#
+# Description:
+#
+#<AMI_FHDR_END>
+#**********************************************************************
+all : FrameworkPpiLib
+
+$(BUILD_DIR)\FrameworkPpiLib.lib : FrameworkPpiLib
+
+FrameworkPpiLib : $(BUILD_DIR)\FrameworkPpiLib.mak FrameworkPpiLibBin
+
+$(BUILD_DIR)\FrameworkPpiLib.mak : $(FrameworkPpiLib_DIR)\$(@B).cif $(FrameworkPpiLib_DIR)\$(@B).mak $(BUILD_RULES)
+ $(CIF2MAK) $(FrameworkPpiLib_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+FrameworkPpiLibBin :
+ $(MAKE) /$(MAKEFLAGS) $(EDK_DEFAULTS)\
+ /f $(BUILD_DIR)\FrameworkPpiLib.mak all\
+ "MY_INCLUDES=$(EDK_INCLUDES) /I$(MISCFRAMEWORK_DIR) /I$(EDK_INCLUDES) /I$(PROJECT_DIR)\Include\IndustryStandard" \
+ TYPE=PEI_LIBRARY \
+#**********************************************************************
+#**********************************************************************
+#** **
+#** (C)Copyright 1985-2006, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 6145-F Northbelt Pkwy, Norcross, GA 30071 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#**********************************************************************
+#********************************************************************** \ No newline at end of file
diff --git a/MiscFramework/Ppi/FrameworkPpiLib.sdl b/MiscFramework/Ppi/FrameworkPpiLib.sdl
new file mode 100644
index 0000000..16cb0d2
--- /dev/null
+++ b/MiscFramework/Ppi/FrameworkPpiLib.sdl
@@ -0,0 +1,28 @@
+TOKEN
+ Name = "FrameworkPpiLib_SUPPORT"
+ Value = "1"
+ Help = "Main switch to enable FrameworkPpiLib support in Project"
+ TokenType = Boolean
+ TargetMAK = Yes
+ Master = Yes
+End
+
+PATH
+ Name = "FrameworkPpiLib_DIR"
+End
+
+MODULE
+ Help = "Includes FrameworkPpiLib.mak to Project"
+ File = "FrameworkPpiLib.mak"
+End
+
+ELINK
+ Name = "FrameworkPpiLib_LIB"
+ InvokeOrder = ReplaceParent
+End
+
+ELINK
+ Name = "$(BUILD_DIR)\FrameworkPpiLib.lib"
+ Parent = "FrameworkPpiLib_LIB"
+ InvokeOrder = AfterParent
+End
diff --git a/MiscFramework/Ppi/PlatformMemoryRange/PlatformMemoryRange.c b/MiscFramework/Ppi/PlatformMemoryRange/PlatformMemoryRange.c
new file mode 100644
index 0000000..54960fa
--- /dev/null
+++ b/MiscFramework/Ppi/PlatformMemoryRange/PlatformMemoryRange.c
@@ -0,0 +1,35 @@
+/*++
+ This file contains 'Framework Code' and is licensed as such
+ under the terms of your license agreement with Intel or your
+ vendor. This file may not be modified, except as allowed by
+ additional terms of your license agreement.
+--*/
+/*++
+
+Copyright (c) 1999 - 2002 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+ PlatformMemoryRange.c
+
+Abstract:
+
+ Platform Memory Range PPI GUID as defined in EFI 2.0
+
+--*/
+
+#include "Tiano.h"
+#include "Pei.h"
+#include EFI_PPI_DEFINITION (PlatformMemoryRange)
+
+EFI_GUID gPeiPlatformMemoryRangePpiGuid = PEI_PLATFORM_MEMORY_RANGE_PPI_GUID;
+
+EFI_GUID_STRING(&gPeiPlatformMemoryRangePpiGuid, "PlatformMemoryRange", "Platform Memory Range PPI");
diff --git a/MiscFramework/Ppi/PlatformMemoryRange/PlatformMemoryRange.h b/MiscFramework/Ppi/PlatformMemoryRange/PlatformMemoryRange.h
new file mode 100644
index 0000000..6580729
--- /dev/null
+++ b/MiscFramework/Ppi/PlatformMemoryRange/PlatformMemoryRange.h
@@ -0,0 +1,156 @@
+//
+// This file contains 'Framework Code' and is licensed as such
+// under the terms of your license agreement with Intel or your
+// vendor. This file may not be modified, except as allowed by
+// additional terms of your license agreement.
+//
+/*++
+
+Copyright (c) 1999 - 2009 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+ PlatformMemoryRange.h
+
+Abstract:
+
+ Platform Memory Range PPI as defined in EFI 2.0
+
+ PPI for reserving special purpose memory ranges.
+
+--*/
+
+#ifndef _PEI_PLATFORM_MEMORY_RANGE_H_
+#define _PEI_PLATFORM_MEMORY_RANGE_H_
+
+#define PEI_PLATFORM_MEMORY_RANGE_PPI_GUID \
+ { \
+ 0x30eb2979, 0xb0f7, 0x4d60, 0xb2, 0xdc, 0x1a, 0x2c, 0x96, 0xce, 0xb1, 0xf4 \
+ }
+
+EFI_FORWARD_DECLARATION (PEI_PLATFORM_MEMORY_RANGE_PPI);
+
+#define PEI_MEMORY_RANGE_OPTION_ROM UINT32
+
+#define PEI_MR_OPTION_ROM_ALL 0xFFFFFFFF
+#define PEI_MR_OPTION_ROM_NONE 0x00000000
+#define PEI_MR_OPTION_ROM_C0000_16K 0x00000001
+#define PEI_MR_OPTION_ROM_C4000_16K 0x00000002
+#define PEI_MR_OPTION_ROM_C8000_16K 0x00000004
+#define PEI_MR_OPTION_ROM_CC000_16K 0x00000008
+#define PEI_MR_OPTION_ROM_D0000_16K 0x00000010
+#define PEI_MR_OPTION_ROM_D4000_16K 0x00000020
+#define PEI_MR_OPTION_ROM_D8000_16K 0x00000040
+#define PEI_MR_OPTION_ROM_DC000_16K 0x00000080
+#define PEI_MR_OPTION_ROM_E0000_16K 0x00000100
+#define PEI_MR_OPTION_ROM_E4000_16K 0x00000200
+#define PEI_MR_OPTION_ROM_E8000_16K 0x00000400
+#define PEI_MR_OPTION_ROM_EC000_16K 0x00000800
+#define PEI_MR_OPTION_ROM_F0000_16K 0x00001000
+#define PEI_MR_OPTION_ROM_F4000_16K 0x00002000
+#define PEI_MR_OPTION_ROM_F8000_16K 0x00004000
+#define PEI_MR_OPTION_ROM_FC000_16K 0x00008000
+
+//
+// SMRAM Memory Range
+//
+#define PEI_MEMORY_RANGE_SMRAM UINT32
+#define PEI_MR_SMRAM_ALL 0xFFFFFFFF
+#define PEI_MR_SMRAM_NONE 0x00000000
+#define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000
+#define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000
+#define PEI_MR_SMRAM_ABSEG_MASK 0x00010000
+#define PEI_MR_SMRAM_HSEG_MASK 0x00020000
+#define PEI_MR_SMRAM_TSEG_MASK 0x00040000
+//
+// If adding additional entries, SMRAM Size
+// is a multiple of 128KB.
+//
+#define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF
+#define PEI_MR_SMRAM_SIZE_128K_MASK 0x00000001
+#define PEI_MR_SMRAM_SIZE_256K_MASK 0x00000002
+#define PEI_MR_SMRAM_SIZE_512K_MASK 0x00000004
+#define PEI_MR_SMRAM_SIZE_1024K_MASK 0x00000008
+#define PEI_MR_SMRAM_SIZE_2048K_MASK 0x00000010
+#define PEI_MR_SMRAM_SIZE_4096K_MASK 0x00000020
+#define PEI_MR_SMRAM_SIZE_8192K_MASK 0x00000040
+#define PEI_MR_SMRAM_SIZE_16384K_MASK 0x00000080
+#define PEI_MR_SMRAM_SIZE_32768K_MASK 0x00000100
+
+
+#define PEI_MR_SMRAM_ABSEG_128K_NOCACHE 0x00010001
+#define PEI_MR_SMRAM_HSEG_128K_CACHE 0x80020001
+#define PEI_MR_SMRAM_HSEG_128K_NOCACHE 0x00020001
+#define PEI_MR_SMRAM_TSEG_128K_CACHE 0x80040001
+#define PEI_MR_SMRAM_TSEG_128K_NOCACHE 0x00040001
+#define PEI_MR_SMRAM_TSEG_256K_CACHE 0x80040002
+#define PEI_MR_SMRAM_TSEG_256K_NOCACHE 0x00040002
+#define PEI_MR_SMRAM_TSEG_512K_CACHE 0x80040004
+#define PEI_MR_SMRAM_TSEG_512K_NOCACHE 0x00040004
+#define PEI_MR_SMRAM_TSEG_1024K_CACHE 0x80040008
+#define PEI_MR_SMRAM_TSEG_1024K_NOCACHE 0x00040008
+
+//
+// Graphics Memory Range
+//
+#define PEI_MEMORY_RANGE_GRAPHICS_MEMORY UINT32
+#define PEI_MR_GRAPHICS_MEMORY_ALL 0xFFFFFFFF
+#define PEI_MR_GRAPHICS_MEMORY_NONE 0x00000000
+#define PEI_MR_GRAPHICS_MEMORY_CACHEABLE 0x80000000
+//
+// If adding additional entries, Graphics Memory Size
+// is a multiple of 512KB.
+//
+#define PEI_MR_GRAPHICS_MEMORY_SIZE_MASK 0x0000FFFF
+#define PEI_MR_GRAPHICS_MEMORY_512K_NOCACHE 0x00000001
+#define PEI_MR_GRAPHICS_MEMORY_512K_CACHE 0x80000001
+#define PEI_MR_GRAPHICS_MEMORY_1M_NOCACHE 0x00000002
+#define PEI_MR_GRAPHICS_MEMORY_1M_CACHE 0x80000002
+#define PEI_MR_GRAPHICS_MEMORY_4M_NOCACHE 0x00000008
+#define PEI_MR_GRAPHICS_MEMORY_4M_CACHE 0x80000008
+#define PEI_MR_GRAPHICS_MEMORY_8M_NOCACHE 0x00000010
+#define PEI_MR_GRAPHICS_MEMORY_8M_CACHE 0x80000010
+#define PEI_MR_GRAPHICS_MEMORY_16M_NOCACHE 0x00000020
+#define PEI_MR_GRAPHICS_MEMORY_16M_CACHE 0x80000020
+#define PEI_MR_GRAPHICS_MEMORY_32M_NOCACHE 0x00000040
+#define PEI_MR_GRAPHICS_MEMORY_32M_CACHE 0x80000040
+#define PEI_MR_GRAPHICS_MEMORY_48M_NOCACHE 0x00000060
+#define PEI_MR_GRAPHICS_MEMORY_48M_CACHE 0x80000060
+#define PEI_MR_GRAPHICS_MEMORY_64M_NOCACHE 0x00000080
+#define PEI_MR_GRAPHICS_MEMORY_64M_CACHE 0x80000080
+#define PEI_MR_GRAPHICS_MEMORY_128M_NOCACHE 0x00000100
+#define PEI_MR_GRAPHICS_MEMORY_128M_CACHE 0x80000100
+#define PEI_MR_GRAPHICS_MEMORY_256M_NOCACHE 0x00000200
+#define PEI_MR_GRAPHICS_MEMORY_256M_CACHE 0x80000200
+//
+// Pci Memory Hole
+//
+#define PEI_MEMORY_RANGE_PCI_MEMORY UINT32
+#define PEI_MR_PCI_MEMORY_SIZE_512M_MASK 0x00000001
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_CHOOSE_RANGES) (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_PLATFORM_MEMORY_RANGE_PPI * This,
+ IN OUT PEI_MEMORY_RANGE_OPTION_ROM * OptionRomMask,
+ IN OUT PEI_MEMORY_RANGE_SMRAM * SmramMask,
+ IN OUT PEI_MEMORY_RANGE_GRAPHICS_MEMORY * GraphicsMemoryMask,
+ IN OUT PEI_MEMORY_RANGE_PCI_MEMORY * PciMemoryMask
+ );
+
+typedef struct _PEI_PLATFORM_MEMORY_RANGE_PPI {
+ PEI_CHOOSE_RANGES ChooseRanges;
+} PEI_PLATFORM_MEMORY_RANGE_PPI;
+
+extern EFI_GUID gPeiPlatformMemoryRangePpiGuid;
+
+#endif
diff --git a/MiscFramework/Ppi/PlatformMemorySize/PlatformMemorySize.c b/MiscFramework/Ppi/PlatformMemorySize/PlatformMemorySize.c
new file mode 100644
index 0000000..90f54a4
--- /dev/null
+++ b/MiscFramework/Ppi/PlatformMemorySize/PlatformMemorySize.c
@@ -0,0 +1,35 @@
+/*++
+ This file contains 'Framework Code' and is licensed as such
+ under the terms of your license agreement with Intel or your
+ vendor. This file may not be modified, except as allowed by
+ additional terms of your license agreement.
+--*/
+/*++
+
+Copyright (c) 1999 - 2003 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+ PlatformMemorySize.c
+
+Abstract:
+
+ Platform Memory Size PPI GUID as defined in Tiano
+
+--*/
+
+#include "Tiano.h"
+#include "Pei.h"
+#include EFI_PPI_DEFINITION (PlatformMemorySize)
+
+EFI_GUID gPeiPlatformMemorySizePpiGuid = PEI_PLATFORM_MEMORY_SIZE_PPI_GUID;
+
+EFI_GUID_STRING(&gPeiPlatformMemorySizePpiGuid, "PlatformMemorySize", "Platform Memory Size PPI");
diff --git a/MiscFramework/Ppi/PlatformMemorySize/PlatformMemorySize.h b/MiscFramework/Ppi/PlatformMemorySize/PlatformMemorySize.h
new file mode 100644
index 0000000..1233ed4
--- /dev/null
+++ b/MiscFramework/Ppi/PlatformMemorySize/PlatformMemorySize.h
@@ -0,0 +1,55 @@
+//
+// This file contains 'Framework Code' and is licensed as such
+// under the terms of your license agreement with Intel or your
+// vendor. This file may not be modified, except as allowed by
+// additional terms of your license agreement.
+//
+/*++
+
+Copyright (c) 1999 - 2003 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+Module Name:
+
+ PlatformMemorySize.h
+
+Abstract:
+
+ Platform Memory Size PPI as defined in Tiano
+
+ PPI for describing the minimum platform memory size in order to successfully
+ pass control into DXE
+
+--*/
+
+#ifndef _PEI_PLATFORM_MEMORY_SIZE_H_
+#define _PEI_PLATFORM_MEMORY_SIZE_H_
+
+#define PEI_PLATFORM_MEMORY_SIZE_PPI_GUID \
+ { \
+ 0x9a7ef41e, 0xc140, 0x4bd1, 0xb8, 0x84, 0x1e, 0x11, 0x24, 0xb, 0x4c, 0xe6 \
+ }
+
+EFI_FORWARD_DECLARATION (PEI_PLATFORM_MEMORY_SIZE_PPI);
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_GET_MINIMUM_PLATFORM_MEMORY_SIZE) (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_PLATFORM_MEMORY_SIZE_PPI * This,
+ IN OUT UINT64 *MemorySize
+ );
+
+typedef struct _PEI_PLATFORM_MEMORY_SIZE_PPI {
+ PEI_GET_MINIMUM_PLATFORM_MEMORY_SIZE GetPlatformMemorySize;
+} PEI_PLATFORM_MEMORY_SIZE_PPI;
+
+extern EFI_GUID gPeiPlatformMemorySizePpiGuid;
+
+#endif
diff --git a/MiscFramework/Ppi/SmbusPolicy/SmbusPolicy.c b/MiscFramework/Ppi/SmbusPolicy/SmbusPolicy.c
new file mode 100644
index 0000000..ccaf621
--- /dev/null
+++ b/MiscFramework/Ppi/SmbusPolicy/SmbusPolicy.c
@@ -0,0 +1,35 @@
+/*++
+ This file contains 'Framework Code' and is licensed as such
+ under the terms of your license agreement with Intel or your
+ vendor. This file may not be modified, except as allowed by
+ additional terms of your license agreement.
+--*/
+/*++
+
+Copyright (c) 1999 - 2002 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+ SmbusPolicy.c
+
+Abstract:
+
+ Smbus Policy PPI GUID as defined in EFI 2.0
+
+--*/
+
+#include "Tiano.h"
+#include "Pei.h"
+#include EFI_PPI_DEFINITION (SmbusPolicy)
+
+EFI_GUID gPeiSmbusPolicyPpiGuid = PEI_SMBUS_POLICY_PPI_GUID;
+
+EFI_GUID_STRING(&gPeiSmbusPolicyPpiGuid, "SmbusPolicy", "Smbus Policy PPI");
diff --git a/MiscFramework/Ppi/SmbusPolicy/SmbusPolicy.h b/MiscFramework/Ppi/SmbusPolicy/SmbusPolicy.h
new file mode 100644
index 0000000..48cd755
--- /dev/null
+++ b/MiscFramework/Ppi/SmbusPolicy/SmbusPolicy.h
@@ -0,0 +1,48 @@
+//
+// This file contains 'Framework Code' and is licensed as such
+// under the terms of your license agreement with Intel or your
+// vendor. This file may not be modified, except as allowed by
+// additional terms of your license agreement.
+//
+/*++
+
+Copyright (c) 1999 - 2002 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+ SmbusPolicy.h
+
+Abstract:
+
+ Smbus Policy PPI as defined in EFI 2.0
+
+--*/
+
+#ifndef _PEI_SMBUS_POLICY_PPI_H
+#define _PEI_SMBUS_POLICY_PPI_H
+
+#define PEI_SMBUS_POLICY_PPI_GUID \
+ { \
+ 0x63b6e435, 0x32bc, 0x49c6, 0x81, 0xbd, 0xb7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c \
+ }
+
+EFI_FORWARD_DECLARATION (PEI_SMBUS_POLICY_PPI);
+
+typedef struct _PEI_SMBUS_POLICY_PPI {
+ UINTN BaseAddress;
+ UINT32 PciAddress;
+ UINT8 NumRsvdAddress;
+ UINT8 *RsvdAddress;
+} PEI_SMBUS_POLICY_PPI;
+
+extern EFI_GUID gPeiSmbusPolicyPpiGuid;
+
+#endif
diff --git a/MiscFramework/Ppi/SmmControl/SmmControl.c b/MiscFramework/Ppi/SmmControl/SmmControl.c
new file mode 100644
index 0000000..327821e
--- /dev/null
+++ b/MiscFramework/Ppi/SmmControl/SmmControl.c
@@ -0,0 +1,35 @@
+/*++
+ This file contains 'Framework Code' and is licensed as such
+ under the terms of your license agreement with Intel or your
+ vendor. This file may not be modified, except as allowed by
+ additional terms of your license agreement.
+--*/
+/*++
+
+Copyright (c) 1999 - 2002 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+ SmmControl.c
+
+Abstract:
+
+ Stall PPI GUID as defined in EFI 2.0
+
+--*/
+
+#include "Tiano.h"
+#include "Pei.h"
+#include EFI_PPI_DEFINITION (SmmControl)
+
+EFI_GUID gPeiSmmControlPpiGuid = PEI_SMM_CONTROL_PPI_GUID;
+
+EFI_GUID_STRING(&gPeiSmmControlPpiGuid, "SmmControl", "SMM Control PPI");
diff --git a/MiscFramework/Ppi/SmmControl/SmmControl.h b/MiscFramework/Ppi/SmmControl/SmmControl.h
new file mode 100644
index 0000000..84b45d3
--- /dev/null
+++ b/MiscFramework/Ppi/SmmControl/SmmControl.h
@@ -0,0 +1,67 @@
+//
+// This file contains 'Framework Code' and is licensed as such
+// under the terms of your license agreement with Intel or your
+// vendor. This file may not be modified, except as allowed by
+// additional terms of your license agreement.
+//
+/*++
+
+Copyright (c) 1999 - 2002 Intel Corporation. All rights reserved
+This software and associated documentation (if any) is furnished
+under a license and may only be used or copied in accordance
+with the terms of the license. Except as permitted by such
+license, no part of this software or documentation may be
+reproduced, stored in a retrieval system, or transmitted in any
+form or by any means without the express written consent of
+Intel Corporation.
+
+
+Module Name:
+
+ SmmControl.h
+
+Abstract:
+
+ Stall PPI as defined in EFI 2.0
+
+ This code abstracts the PEI core to provide SmmControl services.
+
+--*/
+
+#ifndef _PEI_SMM_CONTROL_PPI_H_
+#define _PEI_SMM_CONTROL_PPI_H_
+
+#define PEI_SMM_CONTROL_PPI_GUID \
+ { \
+ 0x61c68702, 0x4d7e, 0x4f43, 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 \
+ }
+
+EFI_FORWARD_DECLARATION (PEI_SMM_CONTROL_PPI);
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_SMM_ACTIVATE) (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SMM_CONTROL_PPI * This,
+ IN OUT INT8 *ArgumentBuffer OPTIONAL,
+ IN OUT UINTN *ArgumentBufferSize OPTIONAL,
+ IN BOOLEAN Periodic OPTIONAL,
+ IN UINTN ActivationInterval OPTIONAL
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *PEI_SMM_DEACTIVATE) (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SMM_CONTROL_PPI * This,
+ IN BOOLEAN Periodic OPTIONAL
+ );
+
+typedef struct _PEI_SMM_CONTROL_PPI {
+ PEI_SMM_ACTIVATE Trigger;
+ PEI_SMM_DEACTIVATE Clear;
+} PEI_SMM_CONTROL_PPI;
+
+extern EFI_GUID gPeiSmmControlPpiGuid;
+
+#endif
diff --git a/MiscFramework/Ppi/SmmControlLib.cif b/MiscFramework/Ppi/SmmControlLib.cif
new file mode 100644
index 0000000..6a9624c
--- /dev/null
+++ b/MiscFramework/Ppi/SmmControlLib.cif
@@ -0,0 +1,11 @@
+<component>
+ name = "SmmControlLib"
+ category = ModulePart
+ LocalRoot = "MiscFramework\Ppi"
+ RefName = "SmmControlLib"
+[files]
+"SmmControl\SmmControl.c"
+"SmmControl\SmmControl.h"
+"SmmControlLib.sdl"
+"SmmControlLib.mak"
+<endComponent>
diff --git a/MiscFramework/Ppi/SmmControlLib.mak b/MiscFramework/Ppi/SmmControlLib.mak
new file mode 100644
index 0000000..f26f8b0
--- /dev/null
+++ b/MiscFramework/Ppi/SmmControlLib.mak
@@ -0,0 +1,72 @@
+#**********************************************************************
+#**********************************************************************
+#** **
+#** (C)Copyright 1985-2006, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 6145-F Northbelt Pkwy, Norcross, GA 30071 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#**********************************************************************
+#**********************************************************************
+
+#**********************************************************************
+# $Header: /Alaska/SOURCE/Modules/MPG/Calpella/MiscFramework/SmmControlLib/SmmControlLib.mak 1 10/15/08 2:20p Fasihm $
+#
+# $Revision: 1 $
+#
+# $Date: 10/15/08 2:20p $
+#**********************************************************************
+# Revision History
+# ----------------
+#
+#**********************************************************************
+#<AMI_FHDR_START>
+#
+# Name: FrameworkPpiLib.mak
+#
+# Description:
+#
+#<AMI_FHDR_END>
+#**********************************************************************
+all : SmmControlLib
+
+$(SmmControlLib_LIB) : SmmControlLib
+
+SmmControlLib : $(BUILD_DIR)\SmmControlLib.mak SmmControlLibBin
+
+$(BUILD_DIR)\SmmControlLib.mak : $(SmmControlLib_DIR)\$(@B).cif $(SmmControlLib_DIR)\$(@B).mak $(BUILD_RULES)
+ $(CIF2MAK) $(SmmControlLib_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+SmmControlLibBin :
+ $(MAKE) /$(MAKEFLAGS) $(EDK_DEFAULTS)\
+!IF "$(x64_BUILD)"=="1"
+ /f $(BUILD_DIR)\SmmControlLib.mak all\
+ "MY_INCLUDES=$(EDK_INCLUDES) /I$(MISCFRAMEWORK_DIR) /I$(EDK_INCLUDES) /I$(PROJECT_DIR)\Include\IndustryStandard" \
+ TYPE=LIBRARY
+ $(MAKE) /$(MAKEFLAGS) $(EDK_DEFAULTS)\
+ BUILD_DIR=$(BUILD_DIR)\IA32\
+ /f $(BUILD_DIR)\SmmControlLib.mak all\
+ "MY_INCLUDES=$(EDK_INCLUDES) /I$(MISCFRAMEWORK_DIR) /I$(EDK_INCLUDES) /I$(PROJECT_DIR)\Include\IndustryStandard" \
+ TYPE=PEI_LIBRARY
+!ELSE
+ /f $(BUILD_DIR)\SmmControlLib.mak all\
+ "MY_INCLUDES=$(EDK_INCLUDES) /I$(MISCFRAMEWORK_DIR) /I$(EDK_INCLUDES) /I$(PROJECT_DIR)\Include\IndustryStandard" \
+ TYPE=PEI_LIBRARY
+!ENDIF
+
+#**********************************************************************
+#**********************************************************************
+#** **
+#** (C)Copyright 1985-2006, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 6145-F Northbelt Pkwy, Norcross, GA 30071 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#**********************************************************************
+#********************************************************************** \ No newline at end of file
diff --git a/MiscFramework/Ppi/SmmControlLib.sdl b/MiscFramework/Ppi/SmmControlLib.sdl
new file mode 100644
index 0000000..52ffc40
--- /dev/null
+++ b/MiscFramework/Ppi/SmmControlLib.sdl
@@ -0,0 +1,28 @@
+TOKEN
+ Name = "SmmControlLib_SUPPORT"
+ Value = "1"
+ Help = "Main switch to enable SmmControlLib support in Project"
+ TokenType = Boolean
+ TargetMAK = Yes
+ Master = Yes
+End
+
+PATH
+ Name = "SmmControlLib_DIR"
+End
+
+MODULE
+ Help = "Includes SmmControlLib.mak to Project"
+ File = "SmmControlLib.mak"
+End
+
+ELINK
+ Name = "SmmControlLib_LIB"
+ InvokeOrder = ReplaceParent
+End
+
+ELINK
+ Name = "$$(LIB_BUILD_DIR)\SmmControlLib.lib"
+ Parent = "SmmControlLib_LIB"
+ InvokeOrder = AfterParent
+End