diff options
Diffstat (limited to 'ReferenceCode/Chipset/LynxPoint/Include/PchRegs')
12 files changed, 4840 insertions, 0 deletions
diff --git a/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsAdsp.h b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsAdsp.h new file mode 100644 index 0000000..94198e7 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsAdsp.h @@ -0,0 +1,109 @@ +/** @file + Register names for Audio DSP block + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_CPT_" + - Registers / bits that are different between SKUs are denoted by "_<SKU_name>" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without <generation_name> inserted. + +@copyright + Copyright (c) 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _PCH_REGS_ADSP_H_ +#define _PCH_REGS_ADSP_H_ + +#ifdef ADSP_FLAG + +#define MMIO_ADDR_MASK 0xFFFFFFF0 + +// +// AUDIO DSP Registers (D19:F0) +// +#define PCI_DEVICE_NUMBER_PCH_ADSP 19 +#define PCI_FUNCTION_NUMBER_PCH_ADSP 0 +#define R_PCH_ADSP_VENDOR_ID 0x00 +#define V_PCH_ADSP_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_LPTLP_ADSP_DEVICE_ID 0x02 +#define V_PCH_LPTLP_ADSP_DEVICE_ID 0x9C36 + +// +// Audio DSP PCI Configuration space definitions +// +#define R_PCH_ADSP_COMMAND 0x04 +#define B_PCH_ADSP_COMMAND_BME BIT2 +#define B_PCH_ADSP_COMMAND_MSE BIT1 +#define R_PCH_ADSP_ADBA 0x10 +#define R_PCH_ADSP_SPCBA 0x14 +#define R_PCH_ADSP_VDRTCTL0 0xA0 +#define B_PCH_ADSP_VDRTCTL0_D3SRAMPGD BIT2 +#define B_PCH_ADSP_VDRTCTL0_D3PGD BIT1 +#define R_PCH_ADSP_VDRTCTL2 0xA8 +#define V_PCH_ADSP_VDRTCTL2 0xFFF +#define R_PCH_ADSP_PME_CTRL_STS 0x84 +#define B_PCH_ADSP_PME_CTRL_STS_PWR_ST (BIT1|BIT0) + +#define SB_DSP_ID 0xD7 + +// +// Audio DSP IOSF Sideband interface definitions +// +#define R_PCH_RCRB_IOBPIRI_IOBPIS_ADSP 0xD7000000 ///< ADSP + +#define R_PCH_ADSP_VDLDAT1 0x624 +#define V_PCH_ADSP_VDLDAT1_CCO 0x40100 + +#define R_PCH_ADSP_VDLDAT2 0x628 +#define V_PCH_ADSP_VDLDAT2_MASK 0xFFFF +#define V_PCH_ADSP_VDLDAT2_IRQ3 0xD9D8 +#define V_PCH_ADSP_VDLDAT2_IRQ3_INV 0xD8D9 +#define V_PCH_ADSP_VDLDAT2_IRQ4 0xDBDA + +#define R_PCH_ADSP_PCICFGCTL 0x500 +#define B_PCH_ADSP_PCICFGCTL_PCICD BIT0 +#define B_PCH_ADSP_PCICFGCTL_ACPIIE BIT1 +#define B_PCH_ADSP_PCICFGCTL_SPCBAD BIT7 + +#define R_PCH_ADSP_PMCTL 0x1E0 +#define V_PCH_ADSP_PMCTL 0x3F + +// +// Audio DSP Shim registers +// +#define R_PCH_ADSP_SHIM_BASE 0xE7000 +#define R_PCH_ADSP_SHIM_LTRC 0xE0 +#define V_PCH_ADSP_SHIM_LTRC 0x3003 + +// ACPI Interrupt +#define R_PCH_ADSP_SHIM_IMC 0x28 +#define V_PCH_ADSP_SHIM_IMC 0x7FFF0000 +#define R_PCH_ADSP_SHIM_IPCD 0x40 +#define V_PCH_ADSP_SHIM_IPCD_1 0x80000000 +#define V_PCH_ADSP_SHIM_IPCD_2 0x04000000 + +#endif // ADSP_FLAG +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsHda.h b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsHda.h new file mode 100644 index 0000000..45b324d --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsHda.h @@ -0,0 +1,399 @@ +/** @file + Register names for PCH High Definition Audio device. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_LPT_" + - Registers / bits that are different between SKUs are denoted by "_<SKU_name>" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without <generation_name> inserted. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _PCH_REGS_HDA_H_ +#define _PCH_REGS_HDA_H_ + +// +// Azalia Controller Registers (D27:F0) +// +#define PCI_DEVICE_NUMBER_PCH_AZALIA 27 +#define PCI_FUNCTION_NUMBER_PCH_AZALIA 0 + +#define R_PCH_HDA_VENDOR_ID 0x00 +#define V_PCH_HDA_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_HDA_DEVICE_ID 0x02 +#define V_PCH_LPTH_HDA_DEVICE_ID 0x8C20 +#define V_PCH_LPTLP_HDA_DEVICE_ID 0x9C20 ///< Azalia Device ID bit[0] fuse = 0 +#define V_PCH_LPTLP_HDA_DEVICE_ID_ALT 0x9C21 ///< Azalia Device ID bit[0] fuse = 1 +#define R_PCH_HDA_COMMAND 0x04 +#define B_PCH_HDA_COMMAND_INTR_DIS BIT10 +#define B_PCH_HDA_COMMAND_FBE BIT9 +#define B_PCH_HDA_COMMAND_SERR_EN BIT8 +#define B_PCH_HDA_COMMAND_WCC BIT7 +#define B_PCH_HDA_COMMAND_PER BIT6 +#define B_PCH_HDA_COMMAND_VPS BIT5 +#define B_PCH_HDA_COMMAND_MWIE BIT4 +#define B_PCH_HDA_COMMAND_SCE BIT3 +#define B_PCH_HDA_COMMAND_BME BIT2 +#define B_PCH_HDA_COMMAND_MSE BIT1 +#define B_PCH_HDA_COMMAND_IOSE BIT0 +#define R_PCH_HDA_STS 0x06 +#define B_PCH_HDA_STS_DPE BIT15 +#define B_PCH_HDA_STS_SSE BIT14 +#define B_PCH_HDA_STS_RMA BIT13 +#define B_PCH_HDA_STS_RTA BIT12 +#define B_PCH_HDA_STS_STA BIT11 +#define B_PCH_HDA_STS_DEV_STS (BIT10 | BIT9) +#define B_PCH_HDA_STS_DPED BIT8 +#define B_PCH_HDA_STS_FB2BC BIT7 +#define B_PCH_HDA_STS_66MHZ_CAP BIT5 +#define B_PCH_HDA_STS_CAP_LST BIT4 +#define B_PCH_HDA_STS_INTR_STS BIT3 +#define R_PCH_HDA_RID 0x08 +#define B_PCH_HDA_RID 0xFF +#define R_PCH_HDA_PI 0x09 +#define B_PCH_HDA_PI 0xFF +#define R_PCH_HDA_SCC 0x0A +#define B_PCH_HDA_SCC 0xFF +#define R_PCH_HDA_BCC 0x0B +#define B_PCH_HDA_BCC 0xFF +#define R_PCH_HDA_CLS 0x0C +#define B_PCH_HDA_CLS 0xFF +#define R_PCH_HDA_LT 0x0D +#define B_PCH_HDA_LT 0xFF +#define R_PCH_HDA_HEADTYPE 0x0E +#define B_PCH_HDA_HEADTYPE 0xFF +#define R_PCH_HDA_HDBARL 0x10 +#define B_PCH_HDA_HDBARL_LBA 0xFFFFC000 +#define B_PCH_HDA_HDBARL_PREF BIT3 +#define B_PCH_HDA_HDBARL_ADDRNG (BIT2 | BIT1) +#define B_PCH_HDA_HDBARL_SPTYP BIT0 +#define V_PCH_HDA_HDBAR_SIZE (1 << 14) +#define R_PCH_HDA_HDBARU 0x14 +#define B_PCH_HDA_HDBARU_UBA 0xFFFFFFFF +#define R_PCH_HDA_SVID 0x2C +#define B_PCH_HDA_SVID 0xFFFF +#define R_PCH_HDA_SID 0x2E +#define B_PCH_HDA_SID 0xFFFF +#define R_PCH_HDA_CAPPTR 0x34 +#define B_PCH_HDA_CAPPTR 0xFF +#define R_PCH_HDA_INTLN 0x3C +#define B_PCH_HDA_INTLN 0xFF +#define R_PCH_HDA_INTPN 0x3D +#define B_PCH_HDA_INTPN 0x0F +#define R_PCH_HDA_HDCTL 0x40 +#define B_PCH_HDA_HDCTL_BCLD BIT1 +#define B_PCH_HDA_HDCTL_MODE BIT0 +#define R_PCH_HDA_AZIOBC 0x42 +#define B_PCH_HDA_AZIOBC_OSEL (BIT7 | BIT6) +#define B_PCH_HDA_AZIOBC_AVDDIS BIT2 +#define R_PCH_HDA_TCSEL 0x44 +#define B_PCH_HDA_TCSEL (BIT2 | BIT1 | BIT0) +#define V_PCH_HDA_TCSEL_TC0 0x00 +#define V_PCH_HDA_TCSEL_TC1 0x01 +#define V_PCH_HDA_TCSEL_TC2 0x02 +#define V_PCH_HDA_TCSEL_TC3 0x03 +#define V_PCH_HDA_TCSEL_TC4 0x04 +#define V_PCH_HDA_TCSEL_TC5 0x05 +#define V_PCH_HDA_TCSEL_TC6 0x06 +#define V_PCH_HDA_TCSEL_TC7 0x07 +#define R_PCH_HDA_DCKCTL 0x4C +#define B_PCH_HDA_DCKCTL_DA BIT0 +#define R_PCH_HDA_DCKSTS 0x4D +#define B_PCH_HDA_DCKSTS_DS BIT7 +#define B_PCH_HDA_DCKSTS_DM BIT0 +#define R_PCH_HDA_PID 0x50 +#define B_PCH_HDA_PID_NEXT 0xFF00 +#define B_PCH_HDA_PID_CAP 0x00FF +#define R_PCH_HDA_PC 0x52 +#define B_PCH_HDA_PC_PME 0xF800 +#define B_PCH_HDA_PC_D2_SUP BIT10 +#define B_PCH_HDA_PC_D1_SUP BIT9 +#define B_PCH_HDA_PC_AUX (BIT8 | BIT7 | BIT6) +#define B_PCH_HDA_PC_DSI BIT5 +#define B_PCH_HDA_PC_PMEC BIT3 +#define B_PCH_HDA_PC_VER (BIT2 | BIT1 | BIT0) +#define R_PCH_HDA_PCS 0x54 +#define B_PCH_HDA_PCS_DATA 0xFF000000 +#define B_PCH_HDA_PCS_CCE BIT23 +#define B_PCH_HDA_PCS_PMES BIT15 +#define B_PCH_HDA_PCS_PMEE BIT8 +#define B_PCH_HDA_PCS_PS (BIT1 | BIT0) +#define V_PCH_HDA_PCS_PS0 0x00 +#define V_PCH_HDA_PCS_PS3 0x03 +#define R_PCH_HDA_MID 0x60 +#define B_PCH_HDA_MID_NEXT 0xFF00 +#define B_PCH_HDA_MID_CAP 0x00FF +#define R_PCH_HDA_MMC 0x62 +#define B_PCH_HDA_MMC_64ADD BIT7 +#define B_PCH_HDA_MMC_MME (BIT6 | BIT5 | BIT4) +#define B_PCH_HDA_MMC_MMC (BIT3 | BIT2 | BIT1) +#define B_PCH_HDA_MMC_ME BIT0 +#define R_PCH_HDA_MMLA 0x64 +#define B_PCH_HDA_MMLA 0xFFFFFFFC +#define R_PCH_HDA_MMUA 0x68 +#define B_PCH_HDA_MMUA 0xFFFFFFFF +#define R_PCH_HDA_MMD 0x6C +#define B_PCH_HDA_MMD 0xFFFF +#define R_PCH_HDA_PXID 0x70 +#define B_PCH_HDA_PXID_NEXT 0xFF00 +#define B_PCH_HDA_PXID_CAP 0x00FF +#define R_PCH_HDA_PXC 0x72 +#define B_PCH_HDA_PXC_IMN 0x3E00 +#define B_PCH_HDA_PXC_SI BIT8 +#define B_PCH_HDA_PXC_DPT 0x00F0 +#define B_PCH_HDA_PXC_CV 0x000F +#define R_PCH_HDA_DEVCAP 0x74 +#define B_PCH_HDA_DEVCAP_FLR BIT28 +#define B_PCH_HDA_DEVCAP_SPLS (BIT27 | BIT26) +#define B_PCH_HDA_DEVCAP_SPLV 0x03FC0000 +#define B_PCH_HDA_DEVCAP_PWRIP BIT14 +#define B_PCH_HDA_DEVCAP_ATTNIP BIT13 +#define B_PCH_HDA_DEVCAP_ATTNBP BIT12 +#define B_PCH_HDA_DEVCAP_EL1AL 0x00000E00 +#define B_PCH_HDA_DEVCAP_EL0AL 0x000001C0 +#define B_PCH_HDA_DEVCAP_ETFS BIT5 +#define B_PCH_HDA_DEVCAP_PFS (BIT4 | BIT3) +#define B_PCH_HDA_DEVCAP_MPSS 0x00000007 +#define R_PCH_HDA_DEVC 0x78 +#define B_PCH_HDA_DEVC_IF BIT15 +#define B_PCH_HDA_DEVC_MRRS (BIT13 | BIT12 | BIT11) +#define B_PCH_HDA_DEVC_NSNPEN BIT11 +#define B_PCH_HDA_DEVC_APE BIT10 +#define B_PCH_HDA_DEVC_PFE BIT9 +#define B_PCH_HDA_DEVC_ETFE BIT8 +#define B_PCH_HDA_DEVC_MPS (BIT7 | BIT6 | BIT5) +#define B_PCH_HDA_DEVC_ERO BIT4 +#define B_PCH_HDA_DEVC_URRE BIT3 +#define B_PCH_HDA_DEVC_FERE BIT2 +#define B_PCH_HDA_DEVC_NFERE BIT1 +#define B_PCH_HDA_DEVC_CERE BIT0 +#define R_PCH_HDA_DEVS 0x7A +#define B_PCH_HDA_DEVS_TP BIT5 +#define B_PCH_HDA_DEVS_AUXPD BIT4 +#define B_PCH_HDA_DEVS_URD BIT3 +#define B_PCH_HDA_DEVS_FED BIT2 +#define B_PCH_HDA_DEVS_NFED BIT1 +#define B_PCH_HDA_DEVS_CED BIT0 +#define R_PCH_HDA_VCCAP 0x100 +#define B_PCH_HDA_VCCAP_NCO 0xFFF00000 +#define B_PCH_HDA_VCCAP_CAPVER 0x000F0000 +#define B_PCH_HDA_VCCAP_PCIEEC 0x0000FFFF +#define R_PCH_HDA_PVCCAP1 0x104 +#define B_PCH_HDA_PVCCAP1_PATES 0x00000C00 +#define B_PCH_HDA_PVCCAP1_RC 0x00000300 +#define B_PCH_HDA_PVCCAP1_LPEVCC 0x00000070 +#define B_PCH_HDA_PVCCAP1_EVCC 0x00000007 +#define R_PCH_HDA_PVCCAP2 0x108 +#define B_PCH_HDA_PVCCAP2_VCATO 0xFF000000 +#define B_PCH_HDA_PVCCAP2_VCAC 0x000000FF +#define R_PCH_HDA_PVCCTL 0x10C +#define B_PCH_HDA_PVCCTL_VCAS 0x000E +#define B_PCH_HDA_PVCCTL_LVCAT 0x0001 +#define R_PCH_HDA_PVCSTS 0x10E +#define B_PCH_HDA_PVCSTS_VCATS 0x0001 +#define R_PCH_HDA_VC0CAP 0x110 +#define S_PCH_HDA_VC0CAP 4 +#define B_PCH_HDA_VC0CAP_PATO 0xFF000000 +#define B_PCH_HDA_VC0CAP_MTS 0x007F0000 +#define B_PCH_HDA_VC0CAP_RST BIT15 +#define B_PCH_HDA_VC0CAP_APS BIT14 +#define B_PCH_HDA_VC0CAP_PAC 0x000000FF +#define R_PCH_HDA_VC0CTL 0x114 +#define S_PCH_HDA_VC0CTL 4 +#define B_PCH_HDA_VC0CTL_VC0EN BIT31 +#define B_PCH_HDA_VC0CTL_VC0ID 0x07000000 +#define B_PCH_HDA_VC0CTL_PAS 0x000E0000 +#define B_PCH_HDA_VC0CTL_LPAT BIT16 +#define B_PCH_HDA_VC0CTL_TCVC0_MAP 0x000000FE +#define R_PCH_HDA_VC0STS 0x11A +#define S_PCH_HDA_VC0STS 2 +#define B_PCH_HDA_VC0STS_VC0NP BIT1 +#define B_PCH_HDA_VC0STS_PATS BIT0 +#define R_PCH_HDA_VCICAP 0x11C +#define S_PCH_HDA_VCICAP 4 +#define B_PCH_HDA_VCICAP_PATO 0xFF000000 +#define B_PCH_HDA_VCICAP_MTS 0x007F0000 +#define B_PCH_HDA_VCICAP_RST BIT15 +#define B_PCH_HDA_VCICAP_APS BIT14 +#define B_PCH_HDA_VCICAP_PAC 0x000000FF +#define R_PCH_HDA_VCICTL 0x120 +#define S_PCH_HDA_VCICTL 4 +#define B_PCH_HDA_VCICTL_EN BIT31 +#define B_PCH_HDA_VCICTL_ID (BIT26 | BIT25 | BIT24) +#define V_PCH_HDA_VCICTL_PAS 0x000E0000 +#define V_PCH_HDA_VCICTL_LPAT BIT16 +#define B_PCH_HDA_VCICTL_TCVCI_MAP 0x000000FE +#define R_PCH_HDA_VCISTS 0x126 +#define S_PCH_HDA_VCISTS 1 +#define B_PCH_HDA_VCISTS_VCINP BIT1 +#define B_PCH_HDA_VCISTS_PATS BIT0 +#define R_PCH_HDA_RCCAP 0x130 +#define B_PCH_HDA_RCCAP_NCO 0xFFF00000 +#define B_PCH_HDA_RCCAP_CV 0x000F0000 +#define B_PCH_HDA_RCCAP_PCIEECID 0x0000FFFF +#define R_PCH_HDA_ESD 0x134 +#define B_PCH_HDA_ESD_PN 0xFF000000 +#define B_PCH_HDA_ESD_CID 0x00FF0000 +#define B_PCH_HDA_ESD_NOLE 0x0000FF00 +#define B_PCH_HDA_ESD_ELTYP 0x0000000F +#define R_PCH_HDA_L1DESC 0x140 +#define S_PCH_HDA_L1DESC 4 +#define B_PCH_HDA_LIDESC_TPN 0xFF000000 +#define B_PCH_HDA_LIDESC_TCID 0x00FF0000 +#define B_PCH_HDA_LIDESC_LT BIT1 +#define B_PCH_HDA_LIDESC_LV BIT0 +#define R_PCH_HDA_L1ADDL 0x148 +#define B_PCH_HDA_L1ADDL_LNK1LA 0xFFFFC000 +#define R_PCH_HDA_L1ADDU 0x14C +#define B_PCH_HDA_L1ADDU 0xFFFFFFFF +// +// Intel High Definition Audio Memory Mapped Configuration Registers +// +#define R_HDA_GCAP 0x00 +#define S_HDA_GCAP 2 +#define B_HDA_GCAP_NOSSUP 0xF000 +#define B_HDA_GCAP_NISSUP 0x0F00 +#define B_HDA_GCAP_NBSSUP 0x00F8 +#define B_HDA_GCAP_NSDOS BIT1 +#define B_HDA_GCAP_64ADSUP BIT0 +#define R_HDA_VMIN 0x02 +#define B_HDA_VMIN_MV 0xFF +#define R_HDA_VMAJ 0x03 +#define B_HDA_VMAJ_MV 0xFF +#define R_HDA_OUTPAY 0x04 +#define B_HDA_OUTPAY_CAP 0x007F +#define R_HDA_INPAY 0x06 +#define B_HDA_INPAY_CAP 0x007F +#define R_HDA_GCTL 0x08 +#define B_HDA_GCTL_AURE BIT8 +#define B_HDA_GCTL_FC BIT1 +#define B_HDA_GCTL_CRST BIT0 +#define R_HDA_WAKEEN 0x0C +#define B_HDA_WAKEEN_SDI_3 BIT3 +#define B_HDA_WAKEEN_SDI_2 BIT2 +#define B_HDA_WAKEEN_SDI_1 BIT1 +#define B_HDA_WAKEEN_SDI_0 BIT0 +#define R_HDA_STATESTS 0x0E +#define B_HDA_STATESTS_SDIN3 BIT3 +#define B_HDA_STATESTS_SDIN2 BIT2 +#define B_HDA_STATESTS_SDIN1 BIT1 +#define B_HDA_STATESTS_SDIN0 BIT0 +#define R_HDA_GSTS 0x10 +#define B_HDA_GSTS_FS BIT1 +#define R_HDA_OUTSTRMPAY 0x18 +#define S_HDA_OUTSTRMPAY 2 +#define B_HDA_OUTSTRMPAY_OUTSTRMPAY 0xFFFF +#define R_HDA_INSTRMPAY 0x1A +#define B_HDA_INSTRMPAY_INSTRMPAY 0xFFFF +#define R_HDA_INTCTL 0x20 +#define B_HDA_INTCTL_GIE BIT31 +#define B_HDA_INTCTL_CIE BIT30 +#define B_HDA_INTCTL_SIE_OS4 BIT7 +#define B_HDA_INTCTL_SIE_OS3 BIT6 +#define B_HDA_INTCTL_SIE_OS2 BIT5 +#define B_HDA_INTCTL_SIE_OS1 BIT4 +#define B_HDA_INTCTL_SIE_IS4 BIT3 +#define B_HDA_INTCTL_SIE_IS3 BIT2 +#define B_HDA_INTCTL_SIE_IS2 BIT1 +#define B_HDA_INTCTL_SIE_IS1 BIT0 +#define R_HDA_INTSTS 0x24 +#define B_HDA_INTSTS_GIS BIT31 +#define B_HDA_INTSTS_CIS BIT30 +#define B_HDA_INTSTS_SIS_OS4 BIT7 +#define B_HDA_INTSTS_SIS_OS3 BIT6 +#define B_HDA_INTSTS_SIS_OS2 BIT5 +#define B_HDA_INTSTS_SIS_OS1 BIT4 +#define B_HDA_INTSTS_SIS_IS4 BIT3 +#define B_HDA_INTSTS_SIS_IS3 BIT2 +#define B_HDA_INTSTS_SIS_IS2 BIT1 +#define B_HDA_INTSTS_SIS_IS1 BIT0 +#define R_HDA_WALCLK 0x30 +#define B_HDA_WALCLK_WCC 0xFFFFFFFF +#define R_HDA_SSYNC 0x38 +#define S_HDA_SSYNC 4 +#define B_HDA_SSYNC_OS4 BIT7 +#define B_HDA_SSYNC_OS3 BIT6 +#define B_HDA_SSYNC_OS2 BIT5 +#define B_HDA_SSYNC_OS1 BIT4 +#define B_HDA_SSYNC_IS4 BIT3 +#define B_HDA_SSYNC_IS3 BIT2 +#define B_HDA_SSYNC_IS2 BIT1 +#define B_HDA_SSYNC_IS1 BIT0 +#define R_HDA_CORBLBASE 0x40 +#define B_HDA_CORBLBASE_BA 0xFFFFFF80 +#define B_HDA_CORBLBASE_UB 0x0000007F +#define R_HDA_CORBUBASE 0x44 +#define B_HDA_CORBUBASE_BA 0xFFFFFFFF +#define R_HDA_CORBWP 0x48 +#define B_HDA_CORBWP 0x000000FF +#define R_HDA_CORBRP 0x4A +#define B_HDA_CORBRP_PRST BIT15 +#define B_HDA_CORBRP_RP 0x00FF +#define R_HDA_CORBCTL 0x4C +#define B_HDA_CORBCTL_DMA_EN BIT1 +#define B_HDA_CORBCTL_MEMERRINTR_EN BIT0 +#define R_HDA_CORBST 0x4D +#define B_HDA_CORBST_CMEI BIT0 +#define R_HDA_CORBSIZE 0x4E +#define B_HDA_CORBSIZE_CAP 0xF0 +#define B_HDA_CORBSIZE_SIZE 0x03 +#define R_HDA_RIRBLBASE 0x50 +#define B_HDA_RIRBLBASE_BA 0xFFFFFF80 +#define B_HDA_RIRBLBASE_UB 0x0000007F +#define R_HDA_RIRBUBASE 0x54 +#define B_HDA_RIRBUBASE_BA 0xFFFFFFFF +#define R_HDA_RIRBWP 0x58 +#define B_HDA_RIRBWP_RST BIT15 +#define B_HDA_RIRBWP_WP 0x00FF +#define R_HDA_RINTCNT 0x5A +#define B_HDA_RINTCNT 0x00FF +#define R_HDA_RIRBCTL 0x5C +#define B_HDA_RIRBCTL_ROIC BIT2 +#define B_HDA_RIRBCTL_DMA BIT1 +#define B_HDA_RIRBCTL_RIC BIT0 +#define R_HDA_RIRBSTS 0x5D +#define B_HDA_RIRBSTS_ROIS BIT2 +#define B_HDA_RIRBSTS_RI BIT0 +#define R_HDA_RIRBSIZE 0x5E +#define B_HDA_RIRBSIZE_CAP 0xF0 +#define B_HDA_RIRBSIZE_SIZE 0x03 +#define R_HDA_IC 0x60 +#define B_HDA_IC 0xFFFFFFFF +#define R_HDA_IR 0x64 +#define B_HDA_IR 0xFFFFFFFF +#define R_HDA_IRS 0x68 +#define B_HDA_IRS_IRV BIT1 +#define B_HDA_IRS_ICB BIT0 +#define R_HDA_DPLBASE 0x70 +#define B_HDA_DPLBASE_LBA 0xFFFFFF80 +#define B_HDA_DPLBASE_LBU 0x0000007E +#define B_HDA_DPLBASE_BUF_EN 0x00000001 +#define R_HDA_DPUBASE 0x74 +#define B_HDA_DPUBASE_UBA 0xFFFFFFFF + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsLan.h b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsLan.h new file mode 100644 index 0000000..ff91dbf --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsLan.h @@ -0,0 +1,196 @@ +/** @file + Register names for PCH LAN device + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_LPT_" + - Registers / bits that are different between SKUs are denoted by "_<SKU_name>" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without <generation_name> inserted. + +@copyright + Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _PCH_REGS_LAN_H_ +#define _PCH_REGS_LAN_H_ + +// +// LAN Controller Registers (D25:F0) +// +#define PCI_BUS_NUMBER_PCH_LAN 0 +#define PCI_DEVICE_NUMBER_PCH_LAN 25 +#define PCI_FUNCTION_NUMBER_PCH_LAN 0 + +#define R_PCH_LAN_VENDOR_ID 0x00 +#define V_PCH_LAN_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_LAN_DEVICE_ID 0x02 +#define V_PCH_LPTH_LAN_DEVICE_ID 0x8C33 +#define V_PCH_LPTLP_LAN_DEVICE_ID 0x155A +#define R_PCH_LAN_CMD 0x04 +#define B_PCH_LAN_CMD_INTR_DIS BIT10 +#define B_PCH_LAN_CMD_FBE BIT9 +#define B_PCH_LAN_CMD_SERR_EN BIT8 +#define B_PCH_LAN_CMD_WCC BIT7 +#define B_PCH_LAN_CMD_PER BIT6 +#define B_PCH_LAN_CMD_PSE BIT5 +#define B_PCH_LAN_CMD_PMWE BIT4 +#define B_PCH_LAN_CMD_SCE BIT3 +#define B_PCH_LAN_CMD_BME BIT2 +#define B_PCH_LAN_CMD_MSE BIT1 +#define B_PCH_LAN_CMD_IOSE BIT0 +#define R_PCH_LAN_STS 0x06 +#define B_PCH_LAN_STS_DPE BIT15 +#define B_PCH_LAN_STS_SSE BIT14 +#define B_PCH_LAN_STS_RMA BIT13 +#define B_PCH_LAN_STS_RTA BIT12 +#define B_PCH_LAN_STS_STA BIT11 +#define B_PCH_LAN_STS_DEV_STS (BIT10 | BIT9) +#define B_PCH_LAN_STS_DPED BIT8 +#define B_PCH_LAN_STS_FB2BC BIT7 +#define B_PCH_LAN_STS_66MHZ_CAP BIT5 +#define B_PCH_LAN_STS_CAP_LST BIT4 +#define B_PCH_LAN_STS_INTR_STS BIT3 +#define R_PCH_LAN_RID 0x08 +#define B_PCH_LAN_RID 0xFF +#define R_PCH_LAN_CC 0x09 +#define S_PCH_LAN_CC 3 +#define B_PCH_LAN_CC 0xFFFFFF +#define R_PCH_LAN_CLS 0x0C +#define B_PCH_LAN_CLS 0xFF +#define R_PCH_LAN_PLT 0x0D +#define B_PCH_LAN_PLT 0xFF +#define R_PCH_LAN_HEADTYPE 0x0E +#define B_PCH_LAN_HEADTYPE 0xFF +#define R_PCH_LAN_MEM_BASE_A 0x10 +#define B_PCH_LAN_MBARA_BA 0xFFFF8000 +#define B_PCH_LAN_MBARA_MSIZE 0x00007FF0 +#define B_PCH_LAN_MBARA_PM BIT3 +#define B_PCH_LAN_MBARA_MT (BIT2 | BIT1) +#define B_PCH_LAN_MBARA_MIOS BIT0 +#define R_PCH_LAN_MBARB 0x14 +#define B_PCH_LAN_MBARB_BA 0xFFFFF000 +#define B_PCH_LAN_MBARB_MSIZE 0x00000FF0 +#define B_PCH_LAN_MBARB_PM BIT3 +#define B_PCH_LAN_MBARB_MT (BIT2 | BIT1) +#define B_PCH_LAN_MBARB_MIOS BIT0 +#define R_PCH_LAN_MBARC 0x18 +#define B_PCH_LAN_MBARC_BA 0xFFFFFFE0 +#define B_PCH_LAN_MBARC_IOSIZE 0x0000001E +#define B_PCH_LAN_MBARC_MIOS BIT0 +#define R_PCH_LAN_SVID 0x2C +#define B_PCH_LAN_SVID 0xFFFF +#define R_PCH_LAN_SID 0x2E +#define B_PCH_LAN_SID 0xFFFF +#define R_PCH_LAN_ERBA 0x30 +#define B_PCH_LAN_ERBA 0xFFFFFFFF +#define R_PCH_LAN_CAP_PTR 0x34 +#define B_PCH_LAN_CAP_PTR 0xFF +#define R_PCH_LAN_INTR 0x3C +#define B_PCH_LAN_INTR_IPIN 0xFF00 +#define B_PCH_LAN_INTR_ILINE 0x00FF +#define V_PCH_LAN_MEM_LENGTH 0x8000 +#define N_PCH_LAN_MEM_ALIGN 15 +#define R_PCH_LAN_LTR_CAP 0xA8 +#define R_PCH_LAN_CLIST1 0xC8 +#define B_PCH_LAN_CLIST1_NEXT 0xFF00 +#define B_PCH_LAN_CLIST1_CID 0x00FF +#define R_PCH_LAN_PMC 0xCA +#define B_PCH_LAN_PMC_PMES 0xF800 +#define B_PCH_LAN_PMC_D2S BIT10 +#define B_PCH_LAN_PMC_D1S BIT9 +#define B_PCH_LAN_PMC_AC (BIT8 | BIT7 | BIT6) +#define B_PCH_LAN_PMC_DSI BIT5 +#define B_PCH_LAN_PMC_PMEC BIT3 +#define B_PCH_LAN_PMC_VS (BIT2 | BIT1 | BIT0) +#define R_PCH_LAN_PMCS 0xCC +#define B_PCH_LAN_PMCS_PMES BIT15 +#define B_PCH_LAN_PMCS_DSC (BIT14 | BIT13) +#define B_PCH_LAN_PMCS_DSL 0x1E00 +#define V_PCH_LAN_PMCS_DSL0 0x0000 +#define V_PCH_LAN_PMCS_DSL3 0x0600 +#define V_PCH_LAN_PMCS_DSL4 0x0800 +#define V_PCH_LAN_PMCS_DSL7 0x0E00 +#define V_PCH_LAN_PMCS_DSL8 0x1000 +#define B_PCH_LAN_PMCS_PMEE BIT8 +#define B_PCH_LAN_PMCS_PS (BIT1 | BIT0) +#define V_PCH_LAN_PMCS_PS0 0x00 +#define V_PCH_LAN_PMCS_PS3 0x03 +#define R_PCH_LAN_DR 0xCF +#define B_PCH_LAN_DR 0xFF +#define R_PCH_LAN_CLIST2 0xD0 +#define B_PCH_LAN_CLIST2_NEXT 0xFF00 +#define B_PCH_LAN_CLIST2_CID 0x00FF +#define R_PCH_LAN_MCTL 0xD2 +#define B_PCH_LAN_MCTL_CID BIT7 +#define B_PCH_LAN_MCTL_MME (BIT6 | BIT5 | BIT4) +#define B_PCH_LAN_MCTL_MMC (BIT3 | BIT2 | BIT1) +#define B_PCH_LAN_MCTL_MSIE BIT0 +#define R_PCH_LAN_MADDL 0xD4 +#define B_PCH_LAN_MADDL 0xFFFFFFFF +#define R_PCH_LAN_MADDH 0xD8 +#define B_PCH_LAN_MADDH 0xFFFFFFFF +#define R_PCH_LAN_MDAT 0xDC +#define B_PCH_LAN_MDAT 0xFFFFFFFF +#define R_PCH_LAN_FLRCAP 0xE0 +#define B_PCH_LAN_FLRCAP_NEXT 0xFF00 +#define B_PCH_LAN_FLRCAP_CID 0x00FF +#define V_PCH_LAN_FLRCAP_CID_SSEL0 0x13 +#define V_PCH_LAN_FLRCAP_CID_SSEL1 0x09 +#define R_PCH_LAN_FLRCLV 0xE2 +#define B_PCH_LAN_FLRCLV_FLRC_SSEL0 BIT9 +#define B_PCH_LAN_FLRCLV_TXP_SSEL0 BIT8 +#define B_PCH_LAN_FLRCLV_VSCID_SSEL1 0xF000 +#define B_PCH_LAN_FLRCLV_CAPVER_SSEL1 0x0F00 +#define B_PCH_LAN_FLRCLV_CAPLNG 0x00FF +#define R_PCH_LAN_DEVCTRL 0xE4 +#define B_PCH_LAN_DEVCTRL BIT0 +// +// Gigabit LAN Capabilities and Status Registers (Memory space) +// +#define R_PCH_MBARA_GBECSR1 0x0000 +#define B_PCH_MBARA_GBECSR1_PHYPDN BIT24 +#define R_PCH_MBARA_GBECSR2 0x0018 +#define B_PCH_MBARA_GBECSR2_PHYPDEN BIT20 +#define R_PCH_MBARA_GBECSR3 0x0020 +#define B_PCH_MBARA_GBECSR3_RB BIT28 +#define B_PCH_MBARA_GBECSR3_MDI_TYPE (BIT27 | BIT26) +#define B_PCH_MBARA_GBECSR3_DATA 0x0000FFFF +#define R_PCH_MBARA_GBECSR4 0x002C +#define B_PCH_MBARA_GBECSR4_WIV BIT31 +#define B_PCH_MBARA_GBECSR4_WESB BIT30 +#define R_PCH_MBARA_GBECSR5 0x0F00 +#define B_PCH_MBARA_GBECSR5_SWFLAG BIT5 +#define R_PCH_MBARA_GBECSR6 0x0F10 +#define B_PCH_MBARA_GBECSR6_GGD BIT6 +#define B_PCH_MBARA_GBECSR6_GbE_DIS BIT3 +#define B_PCH_MBARA_GBECSR6_LPLUND BIT2 +#define B_PCH_MBARA_GBECSR6_LPLUD BIT1 +#define R_PCH_MBARA_GBECSR7 0x5400 +#define R_PCH_MBARA_GBECSR8 0x5404 +#define B_PCH_MBARA_GBECSR8_RAH 0x0000FFFF +#define R_PCH_MBARA_GBECSR9 0x5800 +#define B_PCH_MBARA_GBECSR9_APME BIT0 +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsLpc.h b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsLpc.h new file mode 100644 index 0000000..c922e27 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsLpc.h @@ -0,0 +1,1018 @@ +/** @file + Register names for PCH LPC device + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_LPT_" + - Registers / bits that are different between SKUs are denoted by "_<SKU_name>" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without <generation_name> inserted. + +@copyright + Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _PCH_REGS_LPC_H_ +#define _PCH_REGS_LPC_H_ + +// +// PCI to LPC Bridge Registers (D31:F0) +// +#define PCI_DEVICE_NUMBER_PCH_LPC 31 +#define PCI_FUNCTION_NUMBER_PCH_LPC 0 + +#define PCH_HPET_BDF_MAX 8 + +typedef enum { + LptHB0 = 0, + LptHC0, + LptHC1, + LptHC2, + LptLpB0, + LptLpB1, + LptLpB2, + PchSteppingMax +} PCH_STEPPING; + +#define R_PCH_LPC_VENDOR_ID 0x00 +#define V_PCH_LPC_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_LPC_DEVICE_ID 0x02 + +// +// LynxPoint Desktop LPC Device IDs +// +#define V_PCH_LPTH_LPC_DEVICE_ID_DT_SUPER_SKU 0x8C42 ///< LynxPoint Desktop Super SKU +#define V_PCH_LPTH_LPC_DEVICE_ID_DT_0 0x8C44 ///< Intel Z87 Chipset +#define V_PCH_LPTH_LPC_DEVICE_ID_DT_1 0x8C46 ///< Intel Z85 Chipset +#define V_PCH_LPTH_LPC_DEVICE_ID_DT_2 0x8C4A ///< Intel H87 Chipset +#define V_PCH_LPTH_LPC_DEVICE_ID_DT_3 0x8C4C ///< Intel Q85 Chipset +#define V_PCH_LPTH_LPC_DEVICE_ID_DT_4 0x8C4E ///< Intel Q87 Chipset +#define V_PCH_LPTH_LPC_DEVICE_ID_DT_5 0x8C50 ///< Intel B85 Chipset +#define V_PCH_LPTH_LPC_DEVICE_ID_DT_6 0x8C5C ///< Intel H81 Chipset + +// +// LynxPoint Mobile LPC Device IDs +// +#define V_PCH_LPTH_LPC_DEVICE_ID_MB_SUPER_SKU 0x8C41 ///< LynxPoint Mobile Super SKU +#define V_PCH_LPTH_LPC_DEVICE_ID_MB_0 0x8C49 ///< Intel HM86 Chipset +#define V_PCH_LPTH_LPC_DEVICE_ID_MB_1 0x8C4B ///< Intel HM87 Chipset +#define V_PCH_LPTH_LPC_DEVICE_ID_MB_2 0x8C4F ///< Intel QM87 Chipset + +// +// Lynxpoint Server/WS LPC Device IDs +// +#define V_PCH_LPTH_LPC_DEVICE_ID_SVR_0 0x8C52 ///< Server Essential SKU Intel C222 Chipset +#define V_PCH_LPTH_LPC_DEVICE_ID_SVR_1 0x8C54 ///< Server Standard SKU Intel C224 Chipset +#define V_PCH_LPTH_LPC_DEVICE_ID_SVR_2 0x8C56 ///< Server Advanced SKU Intel C226 Chipset +#define V_PCH_LPTH_LPC_DEVICE_ID_SVR_3 0x8C58 ///< WS SKU + +#define V_PCH_LPTLP_LPC_DEVICE_ID_UNFUSE 0x9C40 ///< LynxPoint LP Unfuse +#define V_PCH_LPTLP_LPC_DEVICE_ID_MB_SUPER_SKU 0x9C41 ///< LynxPoint LP Mobile Super SKU +#define V_PCH_LPTLP_LPC_DEVICE_ID_MB_0 0x9C42 ///< LynxPoint LP Mobile TBD SKU +#define V_PCH_LPTLP_LPC_DEVICE_ID_MB_1 0x9C43 ///< LynxPoint LP Mobile Premium SKU +#define V_PCH_LPTLP_LPC_DEVICE_ID_MB_2 0x9C44 ///< LynxPoint LP Mobile TBD SKU +#define V_PCH_LPTLP_LPC_DEVICE_ID_MB_3 0x9C45 ///< LynxPoint LP Mobile Mainstream SKU +#define V_PCH_LPTLP_LPC_DEVICE_ID_MB_4 0x9C46 ///< LynxPoint LP Mobile TBD SKU +#define V_PCH_LPTLP_LPC_DEVICE_ID_MB_5 0x9C47 ///< LynxPoint LP Mobile Value SKU + +#define R_PCH_LPC_COMMAND 0x04 +#define B_PCH_LPC_COMMAND_FBE 0x0200 +#define B_PCH_LPC_COMMAND_SERR_EN 0x0100 +#define B_PCH_LPC_COMMAND_WCC 0x0080 +#define B_PCH_LPC_COMMAND_PER 0x0040 +#define B_PCH_LPC_COMMAND_VPS 0x0020 +#define B_PCH_LPC_COMMAND_PMWE 0x0010 +#define B_PCH_LPC_COMMAND_SCE 0x0008 +#define B_PCH_LPC_COMMAND_BME 0x0004 +#define B_PCH_LPC_COMMAND_MSE 0x0002 +#define B_PCH_LPC_COMMAND_IOSE 0x0001 +#define R_PCH_LPC_DEV_STS 0x06 +#define B_PCH_LPC_DEV_STS_DPE 0x8000 +#define B_PCH_LPC_DEV_STS_SSE 0x4000 +#define B_PCH_LPC_DEV_STS_RMA 0x2000 +#define B_PCH_LPC_DEV_STS_RTA 0x1000 +#define B_PCH_LPC_DEV_STS_STA 0x0800 +#define B_PCH_LPC_DEV_STS_DEVT_STS 0x0600 +#define B_PCH_LPC_DEV_STS_MDPED 0x0100 +#define B_PCH_LPC_DEV_STS_FB2B 0x0080 +#define B_PCH_LPC_DEV_STS_UDF 0x0040 +#define B_PCH_LPC_DEV_STS_66MHZ_CAP 0x0020 +#define R_PCH_LPC_RID 0x08 +#define V_PCH_LPT_LPC_RID_0 0x00 +#define V_PCH_LPT_LPC_RID_1 0x01 +#define V_PCH_LPT_LPC_RID_2 0x02 +#define V_PCH_LPT_LPC_RID_3 0x03 +#define V_PCH_LPT_LPC_RID_4 0x04 +#define V_PCH_LPT_LPC_RID_5 0x05 +#define R_PCH_LPC_PI 0x09 +#define R_PCH_LPC_SCC 0x0A +#define R_PCH_LPC_BCC 0x0B +#define R_PCH_LPC_PLT 0x0D +#define R_PCH_LPC_HEADTYP 0x0E +#define B_PCH_LPC_HEADTYP_MFD BIT7 +#define B_PCH_LPC_HEADTYP_HT 0x7F +#define R_PCH_LPC_SS 0x2C +#define B_PCH_LPC_SS_SSID 0xFFFF0000 +#define B_PCH_LPC_SS_SSVID 0x0000FFFF +#define R_PCH_LPC_ACPI_BASE 0x40 +#define B_PCH_LPC_ACPI_BASE_BAR 0xFFFC +#define R_PCH_LPC_ACPI_CNT 0x44 +#define B_PCH_LPC_ACPI_CNT_ACPI_EN 0x80 +#define B_PCH_LPC_ACPI_CNT_SCI_IRG_SEL 0x07 +#define R_PCH_LPC_GPIO_BASE 0x48 +#define B_PCH_LPC_GPIO_BASE_BAR 0xFFFC +#define R_PCH_LPC_GPIO_CNT 0x4C +#define B_PCH_LPC_GPIO_CNT_GPIO_EN 0x10 +#define B_PCH_LPC_GPIO_LOCKDOWN_EN 0x01 +#define R_PCH_LPC_VLW_VBDF 0x50 +#define B_PCH_LPC_VLW_VBDF 0xFFFF +#define R_PCH_LPC_VLW_VCTRL 0x54 +#define B_PCH_LPC_VLW_VCTRL_VCLE BIT15 +#define B_PCH_LPC_VLW_VCTRL_FERRVDMDEN BIT5 +#define B_PCH_LPC_VLW_VCTRL_NMIVMEN BIT4 +#define B_PCH_LPC_VLW_VCTRL_INITVMEN BIT3 +#define B_PCH_LPC_VLW_VCTRL_SMIVMEN BIT2 +#define B_PCH_LPC_VLW_VCTRL_INTRVMEN BIT1 +#define B_PCH_LPC_VLW_VCTRL_A20VMEN BIT0 +#define R_PCH_LPC_PIRQA_ROUT 0x60 +#define R_PCH_LPC_PIRQB_ROUT 0x61 +#define R_PCH_LPC_PIRQC_ROUT 0x62 +#define R_PCH_LPC_PIRQD_ROUT 0x63 + +// +// Bit values are the same for R_PCH_LPC_PIRQA_ROUT to R_PCH_LPC_PIRQH_ROUT +// +#define B_PCH_LPC_PIRQX_ROUT_IRQEN 0x80 +#define B_PCH_LPC_PIRQX_ROUT 0x0F +#define V_PCH_LPC_PIRQX_ROUT_IRQ_3 0x03 +#define V_PCH_LPC_PIRQX_ROUT_IRQ_4 0x04 +#define V_PCH_LPC_PIRQX_ROUT_IRQ_5 0x05 +#define V_PCH_LPC_PIRQX_ROUT_IRQ_6 0x06 +#define V_PCH_LPC_PIRQX_ROUT_IRQ_7 0x07 +#define V_PCH_LPC_PIRQX_ROUT_IRQ_9 0x09 +#define V_PCH_LPC_PIRQX_ROUT_IRQ_10 0x0A +#define V_PCH_LPC_PIRQX_ROUT_IRQ_11 0x0B +#define V_PCH_LPC_PIRQX_ROUT_IRQ_12 0x0C +#define V_PCH_LPC_PIRQX_ROUT_IRQ_14 0x0E +#define V_PCH_LPC_PIRQX_ROUT_IRQ_15 0x0F +#define R_PCH_LPC_SERIRQ_CNT 0x64 +#define B_PCH_LPC_SERIRQ_CNT_SIRQEN 0x80 +#define B_PCH_LPC_SERIRQ_CNT_SIRQMD 0x40 +#define B_PCH_LPC_SERIRQ_CNT_SIRQSZ 0x3C +#define N_PCH_LPC_SERIRQ_CNT_SIRQSZ 2 +#define B_PCH_LPC_SERIRQ_CNT_SFPW 0x03 +#define N_PCH_LPC_SERIRQ_CNT_SFPW 0 +#define V_PCH_LPC_SERIRQ_CNT_SFPW_4CLK 0x00 +#define V_PCH_LPC_SERIRQ_CNT_SFPW_6CLK 0x01 +#define V_PCH_LPC_SERIRQ_CNT_SFPW_8CLK 0x02 +#define R_PCH_LPC_PIRQE_ROUT 0x68 +#define R_PCH_LPC_PIRQF_ROUT 0x69 +#define R_PCH_LPC_PIRQG_ROUT 0x6A +#define R_PCH_LPC_PIRQH_ROUT 0x6B +#define R_PCH_LPC_IOXAPIC 0x6C +#define B_PCH_LPC_IOXAPIC_BUS 0xFF00 +#define B_PCH_LPC_IOXAPIC_DEVICE 0x00F8 +#define B_PCH_LPC_IOXAPIC_FUNC 0x0007 +#define R_PCH_LPC_HPET0 0x70 +#define B_PCH_LPC_HPET0_BUS 0xFF00 +#define B_PCH_LPC_HPET0_DEVICE 0x00F8 +#define B_PCH_LPC_HPET0_FUNC 0x0007 +#define R_PCH_LPC_HPET1 0x72 +#define B_PCH_LPC_HPET1_BUS 0xFF00 +#define B_PCH_LPC_HPET1_DEVICE 0x00F8 +#define B_PCH_LPC_HPET1_FUNC 0x0007 +#define R_PCH_LPC_HPET2 0x74 +#define B_PCH_LPC_HPET2_BUS 0xFF00 +#define B_PCH_LPC_HPET2_DEVICE 0x00F8 +#define B_PCH_LPC_HPET2_FUNC 0x0007 +#define R_PCH_LPC_HPET3 0x76 +#define B_PCH_LPC_HPET3_BUS 0xFF00 +#define B_PCH_LPC_HPET3_DEVICE 0x00F8 +#define B_PCH_LPC_HPET3_FUNC 0x0007 +#define R_PCH_LPC_HPET4 0x78 +#define B_PCH_LPC_HPET4_BUS 0xFF00 +#define B_PCH_LPC_HPET4_DEVICE 0x00F8 +#define B_PCH_LPC_HPET4_FUNC 0x0007 +#define R_PCH_LPC_HPET5 0x7A +#define B_PCH_LPC_HPET5_BUS 0xFF00 +#define B_PCH_LPC_HPET5_DEVICE 0x00F8 +#define B_PCH_LPC_HPET5_FUNC 0x0007 +#define R_PCH_LPC_HPET6 0x7C +#define B_PCH_LPC_HPET6_BUS 0xFF00 +#define B_PCH_LPC_HPET6_DEVICE 0x00F8 +#define B_PCH_LPC_HPET6_FUNC 0x0007 +#define R_PCH_LPC_HPET7 0x7E +#define B_PCH_LPC_HPET7_BUS 0xFF00 +#define B_PCH_LPC_HPET7_DEVICE 0x00F8 +#define B_PCH_LPC_HPET7_FUNC 0x0007 +#define R_PCH_LPC_IO_DEC 0x80 +#define B_PCH_LPC_FDD_DEC 0x1000 +#define B_PCH_LPC_LPT_DEC 0x0300 +#define B_PCH_LPC_COMB_DEC 0x0070 +#define V_PCH_LPC_COMB_3F8 0x00 +#define V_PCH_LPC_COMB_2F8 0x10 +#define V_PCH_LPC_COMB_220 0x20 +#define V_PCH_LPC_COMB_228 0x30 +#define V_PCH_LPC_COMB_238 0x40 +#define V_PCH_LPC_COMB_2E8 0x50 +#define V_PCH_LPC_COMB_338 0x60 +#define V_PCH_LPC_COMB_3E8 0x70 +#define B_PCH_LPC_COMA_DEC 0x0007 +#define V_PCH_LPC_COMA_3F8 0x00 +#define V_PCH_LPC_COMA_2F8 0x01 +#define V_PCH_LPC_COMA_220 0x02 +#define V_PCH_LPC_COMA_228 0x03 +#define V_PCH_LPC_COMA_238 0x04 +#define V_PCH_LPC_COMA_2E8 0x05 +#define V_PCH_LPC_COMA_338 0x06 +#define V_PCH_LPC_COMA_3E8 0x07 +#define R_PCH_LPC_ENABLES 0x82 +#define B_PCH_LPC_ENABLES_CNF2_EN 0x2000 +#define B_PCH_LPC_ENABLES_CNF1_EN 0x1000 +#define B_PCH_LPC_ENABLES_MC_EN 0x0800 +#define B_PCH_LPC_ENABLES_KBC_EN 0x0400 +#define B_PCH_LPC_ENABLES_GAMEH_EN 0x0200 +#define B_PCH_LPC_ENABLES_GAMEL_EN 0x0100 +#define B_PCH_LPC_ENABLES_FDD_EN 0x0008 +#define B_PCH_LPC_ENABLES_LPT_EN 0x0004 +#define B_PCH_LPC_ENABLES_COMB_EN 0x0002 +#define B_PCH_LPC_ENABLES_COMA_EN 0x0001 +#define R_PCH_LPC_GEN1_DEC 0x84 +#define B_PCH_LPC_GEN1_DEC_IODRA 0x00FC0000 +#define B_PCH_LPC_GEN1_DEC_IOBAR 0x0000FFFC +#define B_PCH_LPC_GEN1_DEC_EN 0x00000001 +#define R_PCH_LPC_GEN2_DEC 0x88 +#define R_PCH_LPC_GEN3_DEC 0x8C +#define R_PCH_LPC_GEN4_DEC 0x90 +#define R_PCH_LPC_ULKMC 0x94 +#define B_PCH_LPC_ULKMC_SMIBYENDPS BIT15 +#define B_PCH_LPC_ULKMC_TRAPBY64W BIT11 +#define B_PCH_LPC_ULKMC_TRAPBY64R BIT10 +#define B_PCH_LPC_ULKMC_TRAPBY60W BIT9 +#define B_PCH_LPC_ULKMC_TRAPBY60R BIT8 +#define B_PCH_LPC_ULKMC_SMIATENDPS BIT7 +#define B_PCH_LPC_ULKMC_PSTATE BIT6 +#define B_PCH_LPC_ULKMC_A20PASSEN BIT5 +#define B_PCH_LPC_ULKMC_USBSMIEN BIT4 +#define B_PCH_LPC_ULKMC_64WEN BIT3 +#define B_PCH_LPC_ULKMC_64REN BIT2 +#define B_PCH_LPC_ULKMC_60WEN BIT1 +#define B_PCH_LPC_ULKMC_60REN BIT0 +#define R_PCH_LPC_LGMR 0x98 +#define B_PCH_LPC_LGMR_MA 0xFFFF0000 +#define B_PCH_LPC_LGMR_LMRD_EN BIT0 + +#define R_PCH_LPC_FWH_BIOS_SEL 0xD0 +#define B_PCH_LPC_FWH_BIOS_SEL_F8 0xF0000000 +#define B_PCH_LPC_FWH_BIOS_SEL_F0 0x0F000000 +#define B_PCH_LPC_FWH_BIOS_SEL_E8 0x00F00000 +#define B_PCH_LPC_FWH_BIOS_SEL_E0 0x000F0000 +#define B_PCH_LPC_FWH_BIOS_SEL_D8 0x0000F000 +#define B_PCH_LPC_FWH_BIOS_SEL_D0 0x00000F00 +#define B_PCH_LPC_FWH_BIOS_SEL_C8 0x000000F0 +#define B_PCH_LPC_FWH_BIOS_SEL_C0 0x0000000F +#define R_PCH_LPC_FWH_BIOS_SEL2 0xD4 +#define B_PCH_LPC_FWH_BIOS_SEL2_70 0xF000 +#define B_PCH_LPC_FWH_BIOS_SEL2_60 0x0F00 +#define B_PCH_LPC_FWH_BIOS_SEL2_50 0x00F0 +#define B_PCH_LPC_FWH_BIOS_SEL2_40 0x000F +#define R_PCH_LPC_FWH_BIOS_DEC 0xD8 +#define B_PCH_LPC_FWH_BIOS_DEC_F8 0x8000 +#define B_PCH_LPC_FWH_BIOS_DEC_F0 0x4000 +#define B_PCH_LPC_FWH_BIOS_DEC_E8 0x2000 +#define B_PCH_LPC_FWH_BIOS_DEC_E0 0x1000 +#define B_PCH_LPC_FWH_BIOS_DEC_D8 0x0800 +#define B_PCH_LPC_FWH_BIOS_DEC_D0 0x0400 +#define B_PCH_LPC_FWH_BIOS_DEC_C8 0x0200 +#define B_PCH_LPC_FWH_BIOS_DEC_C0 0x0100 +#define B_PCH_LPC_FWH_BIOS_LEG_F 0x0080 +#define B_PCH_LPC_FWH_BIOS_LEG_E 0x0040 +#define B_PCH_LPC_FWH_BIOS_DEC_70 0x0008 +#define B_PCH_LPC_FWH_BIOS_DEC_60 0x0004 +#define B_PCH_LPC_FWH_BIOS_DEC_50 0x0002 +#define B_PCH_LPC_FWH_BIOS_DEC_40 0x0001 +#define R_PCH_LPC_BIOS_CNTL 0xDC +#define S_PCH_LPC_BIOS_CNTL 1 +#define B_PCH_LPC_BIOS_CNTL_SMM_BWP 0x20 ///< SMM BIOS write protect disable +#define B_PCH_LPC_BIOS_CNTL_TSS 0x10 +#define V_PCH_LPC_BIOS_CNTL_SRC 0x0C +#define V_PCH_SRC_PREF_EN_CACHE_EN 0x08 +#define V_PCH_SRC_PREF_DIS_CACHE_DIS 0x04 +#define V_PCH_SRC_PREF_DIS_CACHE_EN 0x00 +#define B_PCH_LPC_BIOS_CNTL_BLE 0x02 +#define B_PCH_LPC_BIOS_CNTL_BIOSWE 0x01 +#define N_PCH_LPC_BIOS_CNTL_BLE 1 +#define N_PCH_LPC_BIOS_CNTL_BIOSWE 0 +#define R_PCH_LPC_FDCAP 0xE0 +#define B_PCH_LPC_FDCAP_NEXT 0xFF00 +#define B_PCH_LPC_FDCAP_CID 0x00FF +#define R_PCH_LPC_FDLEN 0xE2 +#define B_PCH_LPC_FDLEN 0xFF +#define R_PCH_LPC_FDVER 0xE3 +#define B_PCH_LPC_FDVER_VSCID 0xF0 +#define B_PCH_LPC_FDVER_CV 0x0F +#define R_PCH_LPC_FVECIDX 0xE4 +#define B_PCH_LPC_FVECIDX_IDX 0x0000003C +#define R_PCH_LPC_FVECD 0xE8 +#define R_PCH_LPC_FVEC0 0x00 +#define B_PCH_LPC_FVEC0_USB_PORT_CAP 0x00000C00 +#define V_PCH_LPC_FVEC0_USB_14_PORT 0x00000000 +#define V_PCH_LPC_FVEC0_USB_12_PORT 0x00000400 +#define V_PCH_LPC_FVEC0_USB_10_PORT 0x00000800 +#define B_PCH_LPC_FVEC0_SATA_RAID_CAP 0x00000080 +#define B_PCH_LPC_FVEC0_SATA_PORT23_CAP 0x00000040 +#define B_PCH_LPC_FVEC0_SATA_PORT1_6GB_CAP 0x00000008 +#define B_PCH_LPC_FVEC0_SATA_PORT0_6GB_CAP 0x00000004 +#define B_PCH_LPC_FVEC0_PCI_CAP 0x00000002 +#define R_PCH_LPC_FVEC1 0x01 +#define B_PCH_LPC_FVEC1_USB_R_CAP 0x00400000 +#define R_PCH_LPC_FVEC2 0x02 +#define B_PCH_LPC_FVEC2_IATT_CAP 0x00400000 ///< Intel Anti-Theft Technology Capability +#define V_PCH_LPC_FVEC2_PCIE_PORT78_CAP 0x00200000 +#define V_PCH_LPC_FVEC2_PCH_IG_SUPPORT_CAP 0x00020000 ///< PCH Integrated Graphics Support Capability +#define R_PCH_LPC_FVEC3 0x03 +#define B_PCH_LPC_FVEC3_DCMI_CAP 0x00002000 ///< Data Center Manageability Interface (DCMI) Capability +#define B_PCH_LPC_FVEC3_NM_CAP 0x00001000 ///< Node Manager Capability +#define R_PCH_LPC_RCBA 0xF0 +#define B_PCH_LPC_RCBA_BAR 0xFFFFC000 +#define B_PCH_LPC_RCBA_EN 0x00000001 + +#define R_PCH_LPC_GEN_PMCON_1 0xA0 +#define B_PCH_LPC_GEN_PMCON_PER_SMI_SEL 0x0003 +#define V_PCH_LPC_GEN_PMCON_PER_SMI_64S 0x0000 +#define V_PCH_LPC_GEN_PMCON_PER_SMI_32S 0x0001 +#define V_PCH_LPC_GEN_PMCON_PER_SMI_16S 0x0002 +#define V_PCH_LPC_GEN_PMCON_PER_SMI_8S 0x0003 +#define B_PCH_LPC_GEN_PMCON_CLKRUN_EN 0x0004 +#define B_PCH_LPC_GEN_PMCON_PSEUDO_CLKRUN_EN 0x0008 +#define B_PCH_LPC_GEN_PMCON_SMI_LOCK 0x0010 +#define B_PCH_LPC_GEN_PMCON_PWRBTN_LVL 0x0200 +#define B_PCH_LPC_GEN_PMCON_BIOS_PCI_EXP_EN 0x0400 +#define B_PCH_LPC_GEN_PMCON_REQ_CLKRUN_BBCLKGATE 0x0800 +#define B_PCH_LPC_GEN_PMCON_ALLOW_SPXB_CG_INC0 0x1000 +#define B_PCH_LPC_GEN_PMCON_ALLOW_PLL_SD_INC0 0x2000 +#define R_PCH_LPC_GEN_PMCON_2 0xA2 +#define B_PCH_LPC_GEN_PMCON_PWROK_FLR 0x01 +#define B_PCH_LPC_GEN_PMCON_SYSPWR_FLR 0x02 +#define B_PCH_LPC_GEN_PMCON_MIN_SLP_S4 0x04 +#define B_PCH_LPC_GEN_PMCON_CTS 0x08 +#define B_PCH_LPC_GEN_PMCON_SRS 0x10 +#define B_PCH_LPC_GEN_PMCON_MEM_SR 0x20 +#define B_PCH_LPC_GEN_PMCON_DRAM_INIT 0x80 +#define B_PCH_LPC_GEN_PMCON_SX_PP_EN 0x0800 +#define B_PCH_LPC_GEN_PMCON_AG3_PP_EN 0x1000 +#define B_PCH_LPC_GEN_PMCON_DSX_PP_DIS 0x2000 +#define B_PCH_LPC_GEN_PMCON_DC_PP_DIS 0x4000 +#define R_PCH_LPC_GEN_PMCON_3 0xA4 +#define B_PCH_LPC_GEN_PMCON_PME_B0_S5_DIS BIT15 +#define B_PCH_LPC_GEN_PMCON_SUS_PWR_FLR BIT14 +#define B_PCH_LPC_GEN_PMCON_WOL_ENABLE_OVERRIDE BIT13 +#define B_PCH_LPC_GEN_PMCON_DISABLE_SX_STRETCH BIT12 +#define B_PCH_LPC_GEN_PMCON_SLP_S3_MAW 0xC00 +#define V_PCH_LPC_GEN_PMCON_SLP_S3_MAW_60US 0x000 +#define V_PCH_LPC_GEN_PMCON_SLP_S3_MAW_1MS 0x400 +#define V_PCH_LPC_GEN_PMCON_SLP_S3_MAW_50MS 0x800 +#define V_PCH_LPC_GEN_PMCON_SLP_S3_MAW_2S 0xC00 +#define B_PCH_LPC_GEN_PMCON_GEN_RST_STS BIT9 +#define B_PCH_LPC_GEN_PMCON_SWSMI_RTSL 0xC0 +#define V_PCH_LPC_GEN_PMCON_SWSMI_RTSL_64MS 0xC0 +#define V_PCH_LPC_GEN_PMCON_SWSMI_RTSL_32MS 0x80 +#define V_PCH_LPC_GEN_PMCON_SWSMI_RTSL_16MS 0x40 +#define V_PCH_LPC_GEN_PMCON_SWSMI_RTSL_1_5MS 0x00 +#define B_PCH_LPC_GEN_PMCON_SLP_S4_MAW 0x30 +#define V_PCH_LPC_GEN_PMCON_SLP_S4_MAW_1S 0x30 +#define V_PCH_LPC_GEN_PMCON_SLP_S4_MAW_2S 0x20 +#define V_PCH_LPC_GEN_PMCON_SLP_S4_MAW_3S 0x10 +#define V_PCH_LPC_GEN_PMCON_SLP_S4_MAW_4S 0x00 +#define B_PCH_LPC_GEN_PMCON_SLP_S4_ASE 0x08 +#define B_PCH_LPC_GEN_PMCON_RTC_PWR_STS 0x04 +#define B_PCH_LPC_GEN_PMCON_PWR_FLR 0x02 +#define B_PCH_LPC_GEN_PMCON_AFTERG3_EN 0x01 +#define R_PCH_LPC_GEN_PMCON_LOCK 0xA6 +#define B_PCH_LPC_GEN_PMCON_LOCK_S4_STRET_LD BIT2 ///< Lock down SLP_S3/SLP_S4 Minimum Assertion width +#define B_PCH_LPC_GEN_PMCON_LOCK_ABASE_LK BIT1 ///< Lock ACPI BASE at 0x40, only cleared by reset when set +#define R_PCH_LPC_CIR4 0xA9 ///< Chipset Initialization Register 4 +#define R_PCH_LPC_BM_BREAK_EN2 0xAA +#define B_PCH_LPC_BM_BREAK_EN2_SATA3 BIT0 +#define R_PCH_LPC_BM_BREAK_EN 0xAB +#define B_PCH_LPC_BM_BREAK_EN_STORAGE BIT7 +#define B_PCH_LPC_BM_BREAK_EN_PCIE BIT6 +#define B_PCH_LPC_BM_BREAK_EN_EHCI BIT2 +#define B_PCH_LPC_BM_BREAK_EN_HDA BIT0 +#define R_PCH_LPC_PMIR 0xAC +#define B_PCH_LPC_PMIR_CF9LOCK BIT31 ///< CF9h Lockdown +#define B_PCH_LPC_PMIR_CF9GR BIT20 ///< CF9h Global Reset +#define B_PCH_LPC_PMIR_SKIP_HOST_RST_HS BIT19 + +#define R_PCH_LPC_GPI_ROUT 0xB8 +#define B_PCH_LPC_GPI_ROUT_0 (BIT1 | BIT0) +#define B_PCH_LPC_GPI_ROUT_1 (BIT3 | BIT2) +#define B_PCH_LPC_GPI_ROUT_2 (BIT5 | BIT4) +#define B_PCH_LPC_GPI_ROUT_3 (BIT7 | BIT6) +#define B_PCH_LPC_GPI_ROUT_4 (BIT9 | BIT8) +#define B_PCH_LPC_GPI_ROUT_5 (BIT11 | BIT10) +#define B_PCH_LPC_GPI_ROUT_6 (BIT13 | BIT12) +#define B_PCH_LPC_GPI_ROUT_7 (BIT15 | BIT14) +#define B_PCH_LPC_GPI_ROUT_8 (BIT17 | BIT16) +#define B_PCH_LPC_GPI_ROUT_9 (BIT19 | BIT18) +#define B_PCH_LPC_GPI_ROUT_10 (BIT21 | BIT20) +#define B_PCH_LPC_GPI_ROUT_11 (BIT23 | BIT22) +#define B_PCH_LPC_GPI_ROUT_12 (BIT25 | BIT24) +#define B_PCH_LPC_GPI_ROUT_13 (BIT27 | BIT26) +#define B_PCH_LPC_GPI_ROUT_14 (BIT29 | BIT28) +#define B_PCH_LPC_GPI_ROUT_15 (BIT31 | BIT30) + +#define R_PCH_LPC_GPI_ROUT2 0xBC +#define B_PCH_LPC_GPI_ROUT2_17 (BIT1 | BIT0) +#define B_PCH_LPC_GPI_ROUT2_19 (BIT3 | BIT2) +#define B_PCH_LPC_GPI_ROUT2_21 (BIT5 | BIT4) +#define B_PCH_LPC_GPI_ROUT2_22 (BIT7 | BIT6) +#define B_PCH_LPC_GPI_ROUT2_43 (BIT9 | BIT8) +#define B_PCH_LPC_GPI_ROUT2_56 (BIT11 | BIT10) +#define B_PCH_LPC_GPI_ROUT2_57 (BIT13 | BIT12) +#define B_PCH_LPC_GPI_ROUT2_60 (BIT15 | BIT14) + +#define R_PCH_LP_LPC_GPI_ROUT0 0x30 +#define R_PCH_LP_LPC_GPI_ROUT1 0x34 +#define R_PCH_LP_LPC_GPI_ROUT2 0x38 + +#define R_PCH_LPC_MDAP 0xC0 +#define B_PCH_LPC_MDAP_POLICY_EN BIT31 +#define B_PCH_LPC_MDAP_PDMA_EN BIT30 +#define B_PCH_LPC_MDAP_VALUE 0x0001FFFF +// +// APM Registers +// +#define R_PCH_APM_CNT 0xB2 +#define R_PCH_APM_STS 0xB3 + +// +// ACPI and legacy I/O register offsets from PMBASE +// +#define R_PCH_ACPI_PM1_STS 0x00 +#define S_PCH_ACPI_PM1_STS 2 +#define B_PCH_ACPI_PM1_STS_WAK 0x8000 +#define B_PCH_ACPI_PM1_STS_PRBTNOR 0x0800 +#define B_PCH_ACPI_PM1_STS_RTC 0x0400 +#define B_PCH_ACPI_PM1_STS_PWRBTN 0x0100 +#define B_PCH_ACPI_PM1_STS_GBL 0x0020 +#define B_PCH_ACPI_PM1_STS_BM 0x0010 +#define B_PCH_ACPI_PM1_STS_TMROF 0x0001 +#define N_PCH_ACPI_PM1_STS_WAK 15 +#define N_PCH_ACPI_PM1_STS_PRBTNOR 11 +#define N_PCH_ACPI_PM1_STS_RTC 10 +#define N_PCH_ACPI_PM1_STS_PWRBTN 8 +#define N_PCH_ACPI_PM1_STS_GBL 5 +#define N_PCH_ACPI_PM1_STS_BM 4 +#define N_PCH_ACPI_PM1_STS_TMROF 0 + +#define R_PCH_ACPI_PM1_EN 0x02 +#define S_PCH_ACPI_PM1_EN 2 +#define B_PCH_ACPI_PM1_EN_RTC 0x0400 +#define B_PCH_ACPI_PM1_EN_PWRBTN 0x0100 +#define B_PCH_ACPI_PM1_EN_GBL 0x0020 +#define B_PCH_ACPI_PM1_EN_TMROF 0X0001 +#define N_PCH_ACPI_PM1_EN_RTC 10 +#define N_PCH_ACPI_PM1_EN_PWRBTN 8 +#define N_PCH_ACPI_PM1_EN_GBL 5 +#define N_PCH_ACPI_PM1_EN_TMROF 0 + +#define R_PCH_ACPI_PM1_CNT 0x04 +#define S_PCH_ACPI_PM1_CNT 4 +#define B_PCH_ACPI_PM1_CNT_SLP_EN 0x00002000 +#define B_PCH_ACPI_PM1_CNT_SLP_TYP 0x00001C00 +#define V_PCH_ACPI_PM1_CNT_S0 0x00000000 +#define V_PCH_ACPI_PM1_CNT_S1 0x00000400 +#define V_PCH_ACPI_PM1_CNT_S3 0x00001400 +#define V_PCH_ACPI_PM1_CNT_S4 0x00001800 +#define V_PCH_ACPI_PM1_CNT_S5 0x00001C00 +#define B_PCH_ACPI_PM1_CNT_GBL_RLS 0x00000004 +#define B_PCH_ACPI_PM1_CNT_BM_RLD 0x00000002 +#define B_PCH_ACPI_PM1_CNT_SCI_EN 0x00000001 + +#define R_PCH_ACPI_PM1_TMR 0x08 +#define V_PCH_ACPI_TMR_FREQUENCY 3579545 +#define B_PCH_ACPI_PM1_TMR_VAL 0xFFFFFF +#define V_PCH_ACPI_PM1_TMR_MAX_VAL 0x1000000 ///< The timer is 24 bit overflow + +#define R_PCH_ACPI_GPE0_STS_127_96 0x8C +#define S_PCH_ACPI_GPE0_STS_127_96 4 +#define B_PCH_ACPI_GPE0_STS_127_96_WADT BIT18 +#define B_PCH_ACPI_GPE0_STS_127_96_GP27 BIT16 +#define B_PCH_ACPI_GPE0_STS_127_96_PME_B0 BIT13 +#define B_PCH_ACPI_GPE0_STS_127_96_ME_SCI BIT12 +#define B_PCH_ACPI_GPE0_STS_127_96_PME BIT11 +#define B_PCH_ACPI_GPE0_STS_127_96_BATLOW BIT10 +#define B_PCH_ACPI_GPE0_STS_127_96_PCI_EXP BIT9 +#define B_PCH_ACPI_GPE0_STS_127_96_RI BIT8 +#define B_PCH_ACPI_GPE0_STS_127_96_SMB_WAK BIT7 +#define B_PCH_ACPI_GPE0_STS_127_96_TC0SCI BIT6 +#define B_PCH_ACPI_GPE0_STS_127_96_SWGPE BIT2 +#define B_PCH_ACPI_GPE0_STS_127_96_HOT_PLUG BIT1 +#define N_PCH_ACPI_GPE0_STS_127_96_PME_B0 13 +#define N_PCH_ACPI_GPE0_STS_127_96_PME 11 +#define N_PCH_ACPI_GPE0_STS_127_96_BATLOW 10 +#define N_PCH_ACPI_GPE0_STS_127_96_PCI_EXP 9 +#define N_PCH_ACPI_GPE0_STS_127_96_RI 8 +#define N_PCH_ACPI_GPE0_STS_127_96_SMB_WAK 7 +#define N_PCH_ACPI_GPE0_STS_127_96_TC0SCI 6 +#define N_PCH_ACPI_GPE0_STS_127_96_SWGPE 2 +#define N_PCH_ACPI_GPE0_STS_127_96_HOT_PLUG 1 + +#define R_PCH_ACPI_GPE0_EN_127_96 0x9C +#define S_PCH_ACPI_GPE0_EN_127_96 4 +#define B_PCH_ACPI_GPE0_EN_127_96_WADT BIT18 +#define B_PCH_ACPI_GPE0_EN_127_96_GP27 BIT16 +#define B_PCH_ACPI_GPE0_EN_127_96_PME_B0 BIT13 +#define B_PCH_ACPI_GPE0_EN_127_96_ME_SCI BIT12 +#define B_PCH_ACPI_GPE0_EN_127_96_PME BIT11 +#define B_PCH_ACPI_GPE0_EN_127_96_BATLOW BIT10 +#define B_PCH_ACPI_GPE0_EN_127_96_PCI_EXP BIT9 +#define B_PCH_ACPI_GPE0_EN_127_96_RI BIT8 +#define B_PCH_ACPI_GPE0_EN_127_96_TC0SCI BIT6 +#define B_PCH_ACPI_GPE0_EN_127_96_SWGPE BIT2 +#define B_PCH_ACPI_GPE0_EN_127_96_HOT_PLUG BIT1 +#define N_PCH_ACPI_GPE0_EN_127_96_PME_B0 13 +#define N_PCH_ACPI_GPE0_EN_127_96_USB3 12 +#define N_PCH_ACPI_GPE0_EN_127_96_PME 11 +#define N_PCH_ACPI_GPE0_EN_127_96_BATLOW 10 +#define N_PCH_ACPI_GPE0_EN_127_96_PCI_EXP 9 +#define N_PCH_ACPI_GPE0_EN_127_96_RI 8 +#define N_PCH_ACPI_GPE0_EN_127_96_TC0SCI 6 +#define N_PCH_ACPI_GPE0_EN_127_96_SWGPE 2 +#define N_PCH_ACPI_GPE0_EN_127_96_HOT_PLUG 1 + +#define R_PCH_ACPI_GPE0a_STS 0x20 +#define S_PCH_ACPI_GPE0a_STS 4 +#define B_PCH_ACPI_GPE0a_STS_GPInn 0xFFFF0000 +#define B_PCH_ACPI_GPE0a_STS_PME_B0 BIT13 +#define B_PCH_ACPI_GPE0a_STS_PME BIT11 +#define B_PCH_ACPI_GPE0a_STS_BATLOW BIT10 +#define B_PCH_ACPI_GPE0a_STS_PCI_EXP BIT9 +#define B_PCH_ACPI_GPE0a_STS_RI BIT8 +#define B_PCH_ACPI_GPE0a_STS_SMB_WAK BIT7 +#define B_PCH_ACPI_GPE0a_STS_TC0SCI BIT6 +#define B_PCH_ACPI_GPE0a_STS_SWGPE BIT2 +#define B_PCH_ACPI_GPE0a_STS_HOT_PLUG BIT1 +#define N_PCH_ACPI_GPE0a_STS_PME_B0 13 +#define N_PCH_ACPI_GPE0a_STS_PME 11 +#define N_PCH_ACPI_GPE0a_STS_BATLOW 10 +#define N_PCH_ACPI_GPE0a_STS_PCI_EXP 9 +#define N_PCH_ACPI_GPE0a_STS_RI 8 +#define N_PCH_ACPI_GPE0a_STS_SMB_WAK 7 +#define N_PCH_ACPI_GPE0a_STS_TC0SCI 6 +#define N_PCH_ACPI_GPE0a_STS_SWGPE 2 +#define N_PCH_ACPI_GPE0a_STS_HOT_PLUG 1 + +#define R_PCH_ACPI_GPE0b_STS 0x24 +#define S_PCH_ACPI_GPE0b_STS 4 +#define B_PCH_ACPI_GPE0b_STS_GP60 BIT31 +#define B_PCH_ACPI_GPE0b_STS_GP57 BIT30 +#define B_PCH_ACPI_GPE0b_STS_GP56 BIT29 +#define B_PCH_ACPI_GPE0b_STS_GP43 BIT28 +#define B_PCH_ACPI_GPE0b_STS_GP22 BIT27 +#define B_PCH_ACPI_GPE0b_STS_GP21 BIT26 +#define B_PCH_ACPI_GPE0b_STS_GP19 BIT25 +#define B_PCH_ACPI_GPE0b_STS_GP17 BIT24 +#define B_PCH_ACPI_GPE0b_STS_WADT BIT6 +#define B_PCH_ACPI_GPE0b_STS_ME_SCI BIT4 +#define B_PCH_ACPI_GPE0b_STS_GP27 BIT3 + +#define R_PCH_ACPI_GPE0a_EN 0x28 +#define S_PCH_ACPI_GPE0a_EN 4 +#define B_PCH_ACPI_GPE0a_EN_GPInn 0xFFFF0000 +#define B_PCH_ACPI_GPE0a_EN_PME_B0 BIT13 +#define B_PCH_ACPI_GPE0a_EN_PME BIT11 +#define B_PCH_ACPI_GPE0a_EN_BATLOW BIT10 +#define B_PCH_ACPI_GPE0a_EN_PCI_EXP BIT9 +#define B_PCH_ACPI_GPE0a_EN_RI BIT8 +#define B_PCH_ACPI_GPE0a_EN_TC0SCI BIT6 +#define B_PCH_ACPI_GPE0a_EN_SWGPE BIT2 +#define B_PCH_ACPI_GPE0a_EN_HOT_PLUG BIT1 +#define N_PCH_ACPI_GPE0a_EN_USB4 14 +#define N_PCH_ACPI_GPE0a_EN_PME_B0 13 +#define N_PCH_ACPI_GPE0a_EN_USB3 12 +#define N_PCH_ACPI_GPE0a_EN_PME 11 +#define N_PCH_ACPI_GPE0a_EN_BATLOW 10 +#define N_PCH_ACPI_GPE0a_EN_PCI_EXP 9 +#define N_PCH_ACPI_GPE0a_EN_RI 8 +#define N_PCH_ACPI_GPE0a_EN_TC0SCI 6 +#define N_PCH_ACPI_GPE0a_EN_SWGPE 2 +#define N_PCH_ACPI_GPE0a_EN_HOT_PLUG 1 + +#define R_PCH_ACPI_GPE0b_EN 0x2C +#define S_PCH_ACPI_GPE0b_EN 4 +#define B_PCH_ACPI_GPE0b_EN_GP60 BIT31 +#define B_PCH_ACPI_GPE0b_EN_GP57 BIT30 +#define B_PCH_ACPI_GPE0b_EN_GP56 BIT29 +#define B_PCH_ACPI_GPE0b_EN_GP43 BIT28 +#define B_PCH_ACPI_GPE0b_EN_GP22 BIT27 +#define B_PCH_ACPI_GPE0b_EN_GP21 BIT26 +#define B_PCH_ACPI_GPE0b_EN_GP19 BIT25 +#define B_PCH_ACPI_GPE0b_EN_GP17 BIT24 +#define B_PCH_ACPI_GPE0b_EN_WADT BIT6 +#define B_PCH_ACPI_GPE0b_EN_ME_SCI BIT4 +#define B_PCH_ACPI_GPE0b_EN_GP27 BIT3 + +#define R_PCH_SMI_EN 0x30 +#define S_PCH_SMI_EN 4 +#define B_PCH_SMI_EN_LEGACY_USB3 BIT31 +#define B_PCH_SMI_EN_GPIO_UNLOCK_SMI BIT27 +#define B_PCH_SMI_EN_INTEL_USB2 BIT18 +#define B_PCH_SMI_EN_LEGACY_USB2 BIT17 +#define B_PCH_SMI_EN_PERIODIC BIT14 +#define B_PCH_SMI_EN_TCO BIT13 +#define B_PCH_SMI_EN_MCSMI BIT11 +#define B_PCH_SMI_EN_BIOS_RLS BIT7 +#define B_PCH_SMI_EN_SWSMI_TMR BIT6 +#define B_PCH_SMI_EN_APMC BIT5 +#define B_PCH_SMI_EN_ON_SLP_EN BIT4 +#define B_PCH_SMI_EN_LEGACY_USB BIT3 +#define B_PCH_SMI_EN_BIOS BIT2 +#define B_PCH_SMI_EN_EOS BIT1 +#define B_PCH_SMI_EN_GBL_SMI BIT0 +#define N_PCH_SMI_EN_LEGACY_USB3 31 +#define N_PCH_SMI_EN_GPIO_UNLOCK 27 +#define N_PCH_SMI_EN_INTEL_USB2 18 +#define N_PCH_SMI_EN_LEGACY_USB2 17 +#define N_PCH_SMI_EN_PERIODIC 14 +#define N_PCH_SMI_EN_TCO 13 +#define N_PCH_SMI_EN_MCSMI 11 +#define N_PCH_SMI_EN_BIOS_RLS 7 +#define N_PCH_SMI_EN_SWSMI_TMR 6 +#define N_PCH_SMI_EN_APMC 5 +#define N_PCH_SMI_EN_ON_SLP_EN 4 +#define N_PCH_SMI_EN_LEGACY_USB 3 +#define N_PCH_SMI_EN_BIOS 2 +#define N_PCH_SMI_EN_EOS 1 +#define N_PCH_SMI_EN_GBL_SMI 0 + +#define R_PCH_SMI_STS 0x34 +#define S_PCH_SMI_STS 4 +#define B_PCH_SMI_STS_LEGACY_USB3 BIT31 +#define B_PCH_SMI_STS_GPIO_UNLOCK BIT27 +#define B_PCH_SMI_STS_SPI BIT26 +#define B_PCH_SMI_STS_MONITOR BIT21 +#define B_PCH_SMI_STS_PCI_EXP BIT20 +#define B_PCH_SMI_STS_PATCH BIT19 +#define B_PCH_SMI_STS_INTEL_USB2 BIT18 +#define B_PCH_SMI_STS_LEGACY_USB2 BIT17 +#define B_PCH_SMI_STS_SMBUS BIT16 +#define B_PCH_SMI_STS_SERIRQ BIT15 +#define B_PCH_SMI_STS_PERIODIC BIT14 +#define B_PCH_SMI_STS_TCO BIT13 +#define B_PCH_SMI_STS_DEVMON BIT12 +#define B_PCH_SMI_STS_MCSMI BIT11 +#define B_PCH_SMI_STS_GPIO_SMI BIT10 +#define B_PCH_SMI_STS_GPE1 BIT10 +#define B_PCH_SMI_STS_GPE0 BIT9 +#define B_PCH_SMI_STS_PM1_STS_REG BIT8 +#define B_PCH_SMI_STS_SWSMI_TMR BIT6 +#define B_PCH_SMI_STS_APM BIT5 +#define B_PCH_SMI_STS_ON_SLP_EN BIT4 +#define B_PCH_SMI_STS_LEGACY_USB BIT3 +#define B_PCH_SMI_STS_BIOS BIT2 +#define N_PCH_SMI_STS_LEGACY_USB3 31 +#define N_PCH_SMI_STS_GPIO_UNLOCK 27 +#define N_PCH_SMI_STS_SPI 26 +#define N_PCH_SMI_STS_MONITOR 21 +#define N_PCH_SMI_STS_PCI_EXP 20 +#define N_PCH_SMI_STS_PATCH 19 +#define N_PCH_SMI_STS_INTEL_USB2 18 +#define N_PCH_SMI_STS_LEGACY_USB2 17 +#define N_PCH_SMI_STS_SMBUS 16 +#define N_PCH_SMI_STS_SERIRQ 15 +#define N_PCH_SMI_STS_PERIODIC 14 +#define N_PCH_SMI_STS_TCO 13 +#define N_PCH_SMI_STS_DEVMON 12 +#define N_PCH_SMI_STS_MCSMI 11 +#define N_PCH_SMI_STS_GPE1 10 +#define N_PCH_SMI_STS_GPE0 9 +#define N_PCH_SMI_STS_PM1_STS_REG 8 +#define N_PCH_SMI_STS_SWSMI_TMR 6 +#define N_PCH_SMI_STS_APM 5 +#define N_PCH_SMI_STS_ON_SLP_EN 4 +#define N_PCH_SMI_STS_LEGACY_USB 3 +#define N_PCH_SMI_STS_BIOS 2 + +#define R_PCH_LPTH_ALT_GP_SMI_EN 0x38 +#define S_PCH_LPTH_ALT_GP_SMI_EN 2 +#define R_PCH_LPTH_ALT_GP_SMI_STS 0x3A +#define S_PCH_LPTH_ALT_GP_SMI_STS 2 +#define V_PCH_LPTH_ALT_GP_SMI_GPIBASE 0 +#define S_PCH_LPTH_ALT_GP_SMI_GPISIZE 16 + +#define R_PCH_LPTLP_ALT_GP_SMI_EN 0x54 +#define S_PCH_LPTLP_ALT_GP_SMI_EN 4 +#define R_PCH_LPTLP_ALT_GP_SMI_STS 0x50 +#define S_PCH_LPTLP_ALT_GP_SMI_STS 4 +#define V_PCH_LPTLP_ALT_GP_SMI_GPIBASE 32 +#define S_PCH_LPTLP_ALT_GP_SMI_GPISIZE 16 + +// +// USB Per-Port Registers Write Control +// +#define R_PCH_UPRWC 0x3C +#define S_PCH_UPRWC 2 +#define B_PCH_UPRWC_WR_EN_SMI_STS 0x0100 +#define B_PCH_UPRWC_WR_EN 0x0002 +#define B_PCH_UPRWC_WR_EN_SMI_EN 0x0001 + +#define R_PCH_ACPI_GPE_CNTL 0x42 +#define B_PCH_ACPI_GPE_CNTL_SWGPE_CTRL BIT1 + +#define R_PCH_DEVACT_STS 0x44 +#define S_PCH_DEVACT_STS 2 +#define B_PCH_DEVACT_STS_MASK 0x13E1 +#define B_PCH_DEVACT_STS_KBC 0x1000 +#define B_PCH_DEVACT_STS_PIRQDH 0x0200 +#define B_PCH_DEVACT_STS_PIRQCG 0x0100 +#define B_PCH_DEVACT_STS_PIRQBF 0x0080 +#define B_PCH_DEVACT_STS_PIRQAE 0x0040 +#define N_PCH_DEVACT_STS_KBC 12 +#define N_PCH_DEVACT_STS_PIRQDH 9 +#define N_PCH_DEVACT_STS_PIRQCG 8 +#define N_PCH_DEVACT_STS_PIRQBF 7 +#define N_PCH_DEVACT_STS_PIRQAE 6 + +#define R_PCH_ACPI_PM2_CNT 0x50 +#define B_PCH_ACPI_PM2_CNT_ARB_DIS 0x01 + +#define R_PCH_OC_WDT_CTL 0x54 +#define B_PCH_OC_WDT_CTL_RLD BIT31 +#define B_PCH_OC_WDT_CTL_ICCSURV_STS BIT25 +#define B_PCH_OC_WDT_CTL_NO_ICCSURV_STS BIT24 +#define B_PCH_OC_WDT_CTL_FORCE_ALL BIT15 +#define B_PCH_OC_WDT_CTL_EN BIT14 +#define B_PCH_OC_WDT_CTL_ICCSURV BIT13 +#define B_PCH_OC_WDT_CTL_LCK BIT12 +#define B_PCH_OC_WDT_CTL_TOV_MASK 0x3FF +#define B_PCH_OC_WDT_CTL_FAILURE_STS BIT23 +#define B_PCH_OC_WDT_CTL_UNXP_RESET_STS BIT22 +#define B_PCH_OC_WDT_CTL_AFTER_POST 0x3F0000 +#define V_PCH_OC_WDT_CTL_STATUS_FAILURE 1 +#define V_PCH_OC_WDT_CTL_STATUS_OK 0 + +#define R_PCH_ALT_GPI_SMI_EN2 0x5C +#define B_PCH_ALT_GPI_SMI_EN2_ALT_GP60_SMI_EN BIT7 +#define B_PCH_ALT_GPI_SMI_EN2_ALT_GP57_SMI_EN BIT6 +#define B_PCH_ALT_GPI_SMI_EN2_ALT_GP56_SMI_EN BIT5 +#define B_PCH_ALT_GPI_SMI_EN2_ALT_GP43_SMI_EN BIT4 +#define B_PCH_ALT_GPI_SMI_EN2_ALT_GP22_SMI_EN BIT3 +#define B_PCH_ALT_GPI_SMI_EN2_ALT_GP21_SMI_EN BIT2 +#define B_PCH_ALT_GPI_SMI_EN2_ALT_GP19_SMI_EN BIT1 +#define B_PCH_ALT_GPI_SMI_EN2_ALT_GP17_SMI_EN BIT0 +#define R_PCH_ALT_GPI_SMI_STS2 0x5E +#define B_PCH_ALT_GPI_SMI_STS2_ALT_GP60_SMI_STS BIT7 +#define B_PCH_ALT_GPI_SMI_STS2_ALT_GP57_SMI_STS BIT6 +#define B_PCH_ALT_GPI_SMI_STS2_ALT_GP56_SMI_STS BIT5 +#define B_PCH_ALT_GPI_SMI_STS2_ALT_GP43_SMI_STS BIT4 +#define B_PCH_ALT_GPI_SMI_STS2_ALT_GP22_SMI_STS BIT3 +#define B_PCH_ALT_GPI_SMI_STS2_ALT_GP21_SMI_STS BIT2 +#define B_PCH_ALT_GPI_SMI_STS2_ALT_GP19_SMI_STS BIT1 +#define B_PCH_ALT_GPI_SMI_STS2_ALT_GP17_SMI_STS BIT0 + +// +// TCO register I/O map +// +#define PCH_TCO_BASE 0x60 + +#define R_PCH_TCO_RLD 0x0 +#define R_PCH_TCO_DAT_IN 0x2 +#define R_PCH_TCO_DAT_OUT 0x3 +#define R_PCH_TCO1_STS 0x04 +#define S_PCH_TCO1_STS 2 +#define B_PCH_TCO1_STS_DMISERR 0x1000 +#define B_PCH_TCO1_STS_DMISMI 0x0400 +#define B_PCH_TCO1_STS_DMISCI 0x0200 +#define B_PCH_TCO1_STS_BIOSWR 0x0100 +#define B_PCH_TCO1_STS_NEWCENTURY 0x0080 +#define B_PCH_TCO1_STS_TIMEOUT 0x0008 +#define B_PCH_TCO1_STS_TCO_INT 0x0004 +#define B_PCH_TCO1_STS_SW_TCO_SMI 0x0002 +#define B_PCH_TCO1_STS_NMI2SMI 0001 +#define N_PCH_TCO1_STS_DMISMI 10 +#define N_PCH_TCO1_STS_BIOSWR 8 +#define N_PCH_TCO1_STS_NEWCENTURY 7 +#define N_PCH_TCO1_STS_TIMEOUT 3 +#define N_PCH_TCO1_STS_SW_TCO_SMI 1 +#define N_PCH_TCO1_STS_NMI2SMI 0 + +#define R_PCH_TCO2_STS 0x06 +#define S_PCH_TCO2_STS 2 +#define B_PCH_TCO2_STS_SMLINK_SLV_SMI BIT4 +#define B_PCH_TCO2_STS_BAD_BIOS BIT3 +#define B_PCH_TCO2_STS_BOOT BIT2 +#define B_PCH_TCO2_STS_SECOND_TO BIT1 +#define B_PCH_TCO2_STS_INTRD_DET BIT0 +#define N_PCH_TCO2_STS_INTRD_DET 0 + +#define R_PCH_TCO1_CNT 0x08 +#define S_PCH_TCO1_CNT 2 +#define B_PCH_TCO_CNT_LOCK BIT12 +#define B_PCH_TCO_CNT_TMR_HLT BIT11 +#define B_PCH_TCO_CNT_NMI2SMI_EN BIT9 +#define B_PCH_TCO_CNT_NMI_NOW BIT8 +#define N_PCH_TCO_CNT_NMI2SMI_EN 9 + +#define R_PCH_TCO2_CNT 0x0A +#define S_PCH_TCO2_CNT 2 +#define B_PCH_TCO2_CNT_OS_POLICY 0x0030 +#define B_PCH_TCO2_CNT_GPI11_ALERT_DISABLE 0x0008 +#define B_PCH_TCO2_CNT_INTRD_SEL 0x0006 +#define N_PCH_TCO2_CNT_INTRD_SEL 2 + +#define R_PCH_TCO_MESSAGE1 0x0C +#define R_PCH_TCO_MESSAGE2 0x0D +#define R_PCH_TCO_WDCNT 0x0E +#define R_PCH_TCO_SW_IRQ_GEN 0x10 +#define B_PCH_TCO_IRQ12_CAUSE BIT1 +#define B_PCH_TCO_IRQ1_CAUSE BIT0 +#define R_PCH_TCO_TMR 0x12 + +// +// GPIO Init register offsets from GPIOBASE +// +#define R_PCH_GPIO_USE_SEL 0x00 +#define R_PCH_GPIO_IO_SEL 0x04 +#define R_PCH_GPIO_LVL 0x0C +#define R_PCH_GPIO_IOAPIC_SEL 0x10 +#define V_PCH_GPIO_IOAPIC_SEL 0xFFFF +#define R_PCH_GPIO_BLINK 0x18 +#define R_PCH_GPIO_SER_BLINK 0x1C +#define R_PCH_GPIO_SB_CMDSTS 0x20 +#define B_PCH_GPIO_SB_CMDSTS_DLS_MASK 0x00C00000 ///< Data length select +#define B_PCH_GPIO_SB_CMDSTS_DRS_MASK 0x003F0000 ///< Data rate select +#define B_PCH_GPIO_SB_CMDSTS_BUSY BIT8 +#define B_PCH_GPIO_SB_CMDSTS_GO BIT0 +#define R_PCH_GPIO_SB_DATA 0x24 +#define R_PCH_GPIO_NMI_EN 0x28 +#define B_PCH_GPIO_NMI_EN 0xFFFF +#define R_PCH_GPIO_NMI_STS 0x2A +#define B_PCH_GPIO_NMI_STS 0xFFFF +#define R_PCH_GPIO_GPI_INV 0x2C +#define R_PCH_GPIO_USE_SEL2 0x30 +#define R_PCH_GPIO_IO_SEL2 0x34 +#define R_PCH_GPIO_LVL2 0x38 +#define R_PCH_GPIO_USE_SEL3 0x40 +#define R_PCH_GPIO_IO_SEL3 0x44 +#define R_PCH_GPIO_LVL3 0x48 + +#define R_PCH_GP_RST_SEL 0x60 +#define S_PCH_GP_RST_SEL 4 +#define R_PCH_GP_RST_SEL2 0x64 +#define S_PCH_GP_RST_SEL2 4 +#define R_PCH_GP_RST_SEL3 0x68 +#define S_PCH_GP_RST_SEL3 4 + +typedef struct { + UINT16 GpioOwn : 1; + UINT16 GpiRout : 1; + UINT16 GpiIe : 1; + UINT16 GpioUseSel : 1; + UINT16 GpioIoSel : 1; + UINT16 GpiInv : 1; + UINT16 GpiLxEb : 1; + UINT16 GpoLvl : 1; + UINT16 GpiWp : 2; + UINT16 GpinDis : 1; + UINT16 Reserved : 5; +} PCH_GPIO_DEFINITION; + +#define R_PCH_GPIO_OWN0 0x00 +#define B_PCH_GPIO_OWN0_GPIO_USE_SEL BIT0 +#define B_PCH_GPIO_OWN0_GPIO_IO_SEL BIT2 +#define B_PCH_GPIO_OWN0_GPI_INV BIT3 +#define B_PCH_GPIO_OWN0_GPI_LxEB BIT4 +#define B_PCH_GPIO_OWN0_GPI_LVL BIT30 +#define B_PCH_GPIO_OWN0_GPO_LVL BIT31 + +#define V_PCH_GPIO_OWN_GPIO 0x01 +#define V_PCH_GPIO_OWN_ACPI 0x00 + +#define V_PCH_GPIO_USE_SEL_NATIVE 0x00 +#define V_PCH_GPIO_USE_SEL_GPIO 0x01 + +#define V_PCH_GPIO_IO_SEL_OUT 0x00 +#define V_PCH_GPIO_IO_SEL_IN 0x01 + +#define V_PCH_GPO_LVL_LOW 0x00 +#define V_PCH_GPO_LVL_HIGH 0x01 + +#define V_PCH_GPI_LVL_NORMAL 0x00 +#define V_PCH_GPI_LVL_INVERTED 0x01 + +#define V_PCH_GPI_LxEB_EDGE 0x00 +#define V_PCH_GPI_LxEB_LEVEL 0x01 + +#define V_PCH_GPINDIS_ENABLE 0x00 +#define V_PCH_GPINDIS_DISABLE 0x01 + +#define V_PCH_GPIWP_NONE 0x00 +#define V_PCH_GPIWP_DOWN 0x01 +#define V_PCH_GPIWP_UP 0x02 + +#define R_PCH_GPIO_ROUT0 0x30 +#define V_PCH_GPIO_ROUT0_NMI_SMI 0x01 +#define V_PCH_GPIO_ROUT0_SCI 0x00 + +#define R_PCH_GPIO_GC 0x7C +#define R_PCH_GPI_IS0 0x80 +#define R_PCH_GPI_IS1 0x84 +#define R_PCH_GPI_IS2 0x88 +#define V_PCH_GPI_IS_CLEARALL 0xFFFFFFFF + +#define R_PCH_GPI_IE0 0x90 +#define V_PCH_GPI_IE_APIC_DISABLED 0x00 +#define V_PCH_GPI_IE_APIC_ENABLED 0x01 + +#define R_PCH_GPI_IE1 0x94 +#define R_PCH_GPI_IE2 0x98 +#define V_PCH_GPI_IE_CLEARALL 0x00000000 + +#define R_PCH_GP_N_CONFIG0 0x100 +#define R_PCH_GP_X_CONFIG0(n) (R_PCH_GP_N_CONFIG0 + ((n) * 0x08)) +#define R_PCH_GP_18_CONFIG0 R_PCH_GP_X_CONFIG0(18) +#define R_PCH_GP_19_CONFIG0 R_PCH_GP_X_CONFIG0(19) +#define R_PCH_GP_20_CONFIG0 R_PCH_GP_X_CONFIG0(20) +#define R_PCH_GP_21_CONFIG0 R_PCH_GP_X_CONFIG0(21) +#define R_PCH_GP_22_CONFIG0 R_PCH_GP_X_CONFIG0(22) +#define R_PCH_GP_23_CONFIG0 R_PCH_GP_X_CONFIG0(23) +#define R_PCH_GP_29_CONFIG0 R_PCH_GP_X_CONFIG0(29) +#define R_PCH_GP_30_CONFIG0 R_PCH_GP_X_CONFIG0(30) +#define R_PCH_GP_60_CONFIG0 R_PCH_GP_X_CONFIG0(60) +#define R_PCH_GP_73_CONFIG0 R_PCH_GP_X_CONFIG0(73) +#define R_PCH_GP_83_CONFIG0 R_PCH_GP_X_CONFIG0(83) ///< SPI0 +#define R_PCH_GP_87_CONFIG0 R_PCH_GP_X_CONFIG0(87) ///< SPI1 +#define R_PCH_GP_91_CONFIG0 R_PCH_GP_X_CONFIG0(91) ///< UART0 +#define V_PCH_GPIO_PIN_MAX 95 + +// +// Processor interface registers +// +#define R_PCH_NMI_SC 0x61 +#define B_PCH_NMI_SC_SERR_NMI_STS BIT7 +#define B_PCH_NMI_SC_IOCHK_NMI_STS BIT6 +#define B_PCH_NMI_SC_TMR2_OUT_STS BIT5 +#define B_PCH_NMI_SC_REF_TOGGLE BIT4 +#define B_PCH_NMI_SC_IOCHK_NMI_EN BIT3 +#define B_PCH_NMI_SC_PCI_SERR_EN BIT2 +#define B_PCH_NMI_SC_SPKR_DAT_EN BIT1 +#define B_PCH_NMI_SC_TIM_CNT2_EN BIT0 +#define R_PCH_NMI_EN 0x70 +#define B_PCH_NMI_EN_NMI_EN BIT7 + +// +// RTC register +// +#define R_PCH_RTC_INDEX 0x70 +#define R_PCH_RTC_TARGET 0x71 +#define R_PCH_RTC_EXT_INDEX 0x72 +#define R_PCH_RTC_EXT_TARGET 0x73 +#define R_PCH_RTC_REGA 0x0A +#define B_PCH_RTC_REGA_UIP 0x80 +#define R_PCH_RTC_REGB 0x0B +#define B_PCH_RTC_REGB_SET 0x80 +#define B_PCH_RTC_REGB_PIE 0x40 +#define B_PCH_RTC_REGB_AIE 0x20 +#define B_PCH_RTC_REGB_UIE 0x10 +#define B_PCH_RTC_REGB_DM 0x04 +#define B_PCH_RTC_REGB_HOURFORM 0x02 +#define R_PCH_RTC_REGC 0x0C +#define R_PCH_RTC_REGD 0x0D + +// +// Reset Generator I/O Port +// +#define R_PCH_RST_CNT 0xCF9 +#define B_PCH_RST_CNT_FULL_RST BIT3 +#define B_PCH_RST_CNT_RST_CPU BIT2 +#define B_PCH_RST_CNT_SYS_RST BIT1 +#define V_PCH_RST_CNT_FULLRESET 0x0E +#define V_PCH_RST_CNT_HARDRESET 0x06 +#define V_PCH_RST_CNT_SOFTRESET 0x04 +#define V_PCH_RST_CNT_HARDSTARTSTATE 0x02 +#define V_PCH_RST_CNT_SOFTSTARTSTATE 0x00 +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsPcie.h b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsPcie.h new file mode 100644 index 0000000..7fb2afa --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsPcie.h @@ -0,0 +1,548 @@ +/** @file + Register names for PCH PCI-E root port devices + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_LPT_" + - Registers / bits that are different between SKUs are denoted by "_<SKU_name>" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without <generation_name> inserted. + +@copyright + Copyright (c) 1999 - 2014 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _PCH_REGS_PCIE_H_ +#define _PCH_REGS_PCIE_H_ + +#define LPTH_PCIE_MAX_ROOT_PORTS 8 +#define LPTLP_PCIE_MAX_ROOT_PORTS 6 + +// +// PCH PCI Express Root Ports (D28:F0~5) +// +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS 28 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 0 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 1 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 2 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 3 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5 4 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6 5 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7 6 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8 7 +#define R_PCH_PCIE_VENDOR_ID 0x00 +#define V_PCH_PCIE_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_PCIE_DEVICE_ID 0x02 + +#define V_PCH_LPTH_PCIE_DEVICE_ID_PORT1 0x8C10 ///< PCI Express Root Port #1, LPT +#define V_PCH_LPTH_PCIE_DEVICE_ID_PORT2 0x8C12 ///< PCI Express Root Port #2, LPT +#define V_PCH_LPTH_PCIE_DEVICE_ID_PORT3 0x8C14 ///< PCI Express Root Port #3, LPT +#define V_PCH_LPTH_PCIE_DEVICE_ID_PORT4 0x8C16 ///< PCI Express Root Port #4, LPT +#define V_PCH_LPTH_PCIE_DEVICE_ID_PORT5 0x8C18 ///< PCI Express Root Port #5, LPT +#define V_PCH_LPTH_PCIE_DEVICE_ID_PORT6 0x8C1A ///< PCI Express Root Port #6, LPT +#define V_PCH_LPTH_PCIE_DEVICE_ID_PORT7 0x8C1C ///< PCI Express Root Port #7, LPT +#define V_PCH_LPTH_PCIE_DEVICE_ID_PORT8 0x8C1E ///< PCI Express Root Port #8, LPT +#define V_PCH_LPTH_PCIE_DEVICE_ID_MB_SUBD 0x2448 ///< Mobile with subtractive decode enable +#define V_PCH_LPTH_PCIE_DEVICE_ID_DT_SUBD 0x244E ///< Desktop with subtractive decode enable + +#define V_PCH_LPTLP_PCIE_DEVICE_ID_PORT1 0x9C10 ///< PCI Express Root Port #1, LPTLP PCIe Device ID bit[0] fuse = 0 +#define V_PCH_LPTLP_PCIE_DEVICE_ID_PORT1_ALT 0x9C11 ///< PCI Express Root Port #1, LPTLP PCIe Device ID bit[0] fuse = 1 +#define V_PCH_LPTLP_PCIE_DEVICE_ID_PORT2 0x9C12 ///< PCI Express Root Port #2, LPTLP PCIe Device ID bit[0] fuse = 0 +#define V_PCH_LPTLP_PCIE_DEVICE_ID_PORT2_ALT 0x9C13 ///< PCI Express Root Port #2, LPTLP PCIe Device ID bit[0] fuse = 1 +#define V_PCH_LPTLP_PCIE_DEVICE_ID_PORT3 0x9C14 ///< PCI Express Root Port #3, LPTLP PCIe Device ID bit[0] fuse = 0 +#define V_PCH_LPTLP_PCIE_DEVICE_ID_PORT3_ALT 0x9C15 ///< PCI Express Root Port #3, LPTLP PCIe Device ID bit[0] fuse = 1 +#define V_PCH_LPTLP_PCIE_DEVICE_ID_PORT4 0x9C16 ///< PCI Express Root Port #4, LPTLP PCIe Device ID bit[0] fuse = 0 +#define V_PCH_LPTLP_PCIE_DEVICE_ID_PORT4_ALT 0x9C17 ///< PCI Express Root Port #4, LPTLP PCIe Device ID bit[0] fuse = 1 +#define V_PCH_LPTLP_PCIE_DEVICE_ID_PORT5 0x9C18 ///< PCI Express Root Port #5, LPTLP PCIe Device ID bit[0] fuse = 0 +#define V_PCH_LPTLP_PCIE_DEVICE_ID_PORT5_ALT 0x9C19 ///< PCI Express Root Port #5, LPTLP PCIe Device ID bit[0] fuse = 1 +#define V_PCH_LPTLP_PCIE_DEVICE_ID_PORT6 0x9C1A ///< PCI Express Root Port #6, LPTLP PCIe Device ID bit[0] fuse = 0 +#define V_PCH_LPTLP_PCIE_DEVICE_ID_PORT6_ALT 0x9C1B ///< PCI Express Root Port #6, LPTLP PCIe Device ID bit[0] fuse = 1 + +#define R_PCH_PCIE_PCICMD 0x04 +#define S_PCH_PCIE_PCICMD 2 +#define B_PCH_PCIE_PCICMD_ID BIT10 +#define B_PCH_PCIE_PCICMD_FBE BIT9 +#define B_PCH_PCIE_PCICMD_SEE BIT8 +#define B_PCH_PCIE_PCICMD_WCC BIT7 +#define B_PCH_PCIE_PCICMD_PER BIT6 +#define B_PCH_PCIE_PCICMD_VPS BIT5 +#define B_PCH_PCIE_PCICMD_PMWE BIT4 +#define B_PCH_PCIE_PCICMD_SCE BIT3 +#define B_PCH_PCIE_PCICMD_BME BIT2 +#define B_PCH_PCIE_PCICMD_MSE BIT1 +#define B_PCH_PCIE_PCICMD_IOSE BIT0 +#define R_PCH_PCIE_PCISTS 0x06 +#define S_PCH_PCIE_PCISTS 2 +#define B_PCH_PCIE_PCISTS_DPE BIT15 +#define B_PCH_PCIE_PCISTS_SSE BIT14 +#define B_PCH_PCIE_PCISTS_RMA BIT13 +#define B_PCH_PCIE_PCISTS_RTA BIT12 +#define B_PCH_PCIE_PCISTS_STA BIT11 +#define B_PCH_PCIE_PCISTS_DEV_STS (BIT10 | BIT9) +#define B_PCH_PCIE_PCISTS_DPED BIT8 +#define B_PCH_PCIE_PCISTS_FB2BC BIT7 +#define B_PCH_PCIE_PCISTS_66MHZ_CAP BIT5 +#define B_PCH_PCIE_PCISTS_CAP_LST BIT4 +#define B_PCH_PCIE_PCISTS_INTR_STS BIT3 +#define R_PCH_PCIE_RID 0x08 +#define B_PCH_PCIE_RID 0xFF +#define R_PCH_PCIE_PI 0x09 +#define B_PCH_PCIE_PI 0xFF +#define R_PCH_PCIE_SCC 0x0A +#define B_PCH_PCIE_SCC 0xFF +#define V_PCH_PCIE_SCC_04 0x04 +#define V_PCH_PCIE_SCC_00 0x00 +#define R_PCH_PCIE_BCC 0x0B +#define B_PCH_PCIE_BCC 0xFF +#define R_PCH_PCIE_CLS 0x0C +#define B_PCH_PCIE_CLS 0xFF +#define R_PCH_PCIE_PLT 0x0D +#define B_PCH_PCIE_PLT_LC 0xF8 +#define R_PCH_PCIE_HEADTYPE 0x0E +#define B_PCH_PCIE_HEADTYPE_MFD BIT7 +#define B_PCH_PCIE_HEADTYPE_CL 0x7F +#define V_PCH_PCIE_HEADTYPE_CL_01 0x01 +#define V_PCH_PCIE_HEADTYPE_CL_00 0x00 +#define R_PCH_PCIE_BNUM 0x18 +#define B_PCH_PCIE_BNUM_SBBN 0x00FF0000 +#define B_PCH_PCIE_BNUM_SCBN 0x0000FF00 +#define B_PCH_PCIE_BNUM_PBN 0x000000FF +#define R_PCH_PCIE_SLT 0x1B +#define B_PCH_PCIE_SLT 0xFF +#define R_PCH_PCIE_IOBL 0x1C +#define B_PCH_PCIE_IOBL_IOLA 0xF000 +#define B_PCH_PCIE_IOBL_IOLC 0x0F00 +#define B_PCH_PCIE_IOBL_IOBA 0x00F0 +#define B_PCH_PCIE_IOBL_IOBC 0x000F +#define R_PCH_PCIE_SSTS 0x1E +#define S_PCH_PCIE_SSTS 2 +#define B_PCH_PCIE_SSTS_DPE BIT15 +#define B_PCH_PCIE_SSTS_RSE BIT14 +#define B_PCH_PCIE_SSTS_RMA BIT13 +#define B_PCH_PCIE_SSTS_RTA BIT12 +#define B_PCH_PCIE_SSTS_STA BIT11 +#define B_PCH_PCIE_SSTS_SDTS (BIT10 | BIT9) +#define B_PCH_PCIE_SSTS_DPD BIT8 +#define B_PCH_PCIE_SSTS_SFBC BIT7 +#define B_PCH_PCIE_SSTS_SC66 BIT5 +#define R_PCH_PCIE_MBL 0x20 +#define B_PCH_PCIE_MBL_ML 0xFFF00000 +#define B_PCH_PCIE_MBL_MB 0x0000FFF0 +#define R_PCH_PCIE_PMBL 0x24 +#define B_PCH_PCIE_PMBL_PML 0xFFF00000 +#define B_PCH_PCIE_PMBL_I64L 0x000F0000 +#define B_PCH_PCIE_PMBL_PMB 0x0000FFF0 +#define B_PCH_PCIE_PMBL_I64B 0x0000000F +#define R_PCH_PCIE_PMBU32 0x28 +#define B_PCH_PCIE_PMBU32 0xFFFFFFFF +#define R_PCH_PCIE_PMLU32 0x2C +#define B_PCH_PCIE_PMLU32 0xFFFFFFFF +#define R_PCH_PCIE_CAPP 0x34 +#define B_PCH_PCIE_CAPP 0xFF +#define R_PCH_PCIE_INTR 0x3C +#define B_PCH_PCIE_INTR_IPIN 0xFF00 +#define B_PCH_PCIE_INTR_ILINE 0x00FF +#define R_PCH_PCIE_BCTRL 0x3E +#define S_PCH_PCIE_BCTRL 2 +#define B_PCH_PCIE_BCTRL_DTSE BIT11 +#define B_PCH_PCIE_BCTRL_DTS BIT10 +#define B_PCH_PCIE_BCTRL_SDT BIT9 +#define B_PCH_PCIE_BCTRL_PDT BIT8 +#define B_PCH_PCIE_BCTRL_FBE BIT7 +#define B_PCH_PCIE_BCTRL_SBR BIT6 +#define B_PCH_PCIE_BCTRL_MAM BIT5 +#define B_PCH_PCIE_BCTRL_V16 BIT4 +#define B_PCH_PCIE_BCTRL_VE BIT3 +#define B_PCH_PCIE_BCTRL_IE BIT2 +#define B_PCH_PCIE_BCTRL_SE BIT1 +#define B_PCH_PCIE_BCTRL_PERE BIT0 +#define R_PCH_PCIE_CLIST 0x40 +#define B_PCH_PCIE_CLIST_NEXT 0xFF00 +#define B_PCH_PCIE_CLIST_CID 0x00FF +#define R_PCH_PCIE_XCAP 0x42 +#define S_PCH_PCIE_XCAP 2 +#define B_PCH_PCIE_XCAP_IMN 0x3E00 +#define B_PCH_PCIE_XCAP_SI BIT8 +#define B_PCH_PCIE_XCAP_DT 0x00F0 +#define B_PCH_PCIE_XCAP_CV 0x000F +#define R_PCH_PCIE_DCAP 0x44 +#define S_PCH_PCIE_DCAP 4 +#define B_PCH_PCIE_DCAP_CSPS 0x0C000000 +#define B_PCH_PCIE_DCAP_CSPV 0x03FC0000 +#define B_PCH_PCIE_DCAP_RBER BIT15 +#define B_PCH_PCIE_DCAP_PIP BIT14 +#define B_PCH_PCIE_DCAP_AIP BIT13 +#define B_PCH_PCIE_DCAP_ABP BIT12 +#define B_PCH_PCIE_DCAP_E1AL 0x00000E00 +#define B_PCH_PCIE_DCAP_E0AL 0x000001C0 +#define B_PCH_PCIE_DCAP_ETFS BIT5 +#define B_PCH_PCIE_DCAP_PFS 0x00000018 +#define B_PCH_PCIE_DCAP_MPS 0x00000007 +#define R_PCH_PCIE_DCTL 0x48 +#define S_PCH_PCIE_DCTL 2 +#define B_PCH_PCIE_DCTL_MRRS 0x7000 +#define B_PCH_PCIE_DCTL_ENS BIT11 +#define B_PCH_PCIE_DCTL_APME BIT10 +#define B_PCH_PCIE_DCTL_PFE BIT9 +#define B_PCH_PCIE_DCTL_ETFE BIT8 +#define B_PCH_PCIE_DCTL_MPS (BIT7 | BIT6 | BIT5) +#define B_PCH_PCIE_DCTL_ERO BIT4 +#define B_PCH_PCIE_DCTL_URE BIT3 +#define B_PCH_PCIE_DCTL_FEE BIT2 +#define B_PCH_PCIE_DCTL_NFE BIT1 +#define B_PCH_PCIE_DCTL_CEE BIT0 +#define R_PCH_PCIE_DSTS 0x4A +#define B_PCH_PCIE_DSTS_TDP BIT5 +#define B_PCH_PCIE_DSTS_APD BIT4 +#define B_PCH_PCIE_DSTS_URD BIT3 +#define B_PCH_PCIE_DSTS_FED BIT2 +#define B_PCH_PCIE_DSTS_NFED BIT1 +#define B_PCH_PCIE_DSTS_CED BIT0 +#define R_PCH_PCIE_LCAP 0x4C +#define B_PCH_PCIE_LCAP_PN 0xFF000000 +#define V_PCH_PCIE_LCAP_PN1 (1 << 24) +#define V_PCH_PCIE_LCAP_PN2 (2 << 24) +#define V_PCH_PCIE_LCAP_PN3 (3 << 24) +#define V_PCH_PCIE_LCAP_PN4 (4 << 24) +#define V_PCH_PCIE_LCAP_PN5 (5 << 24) +#define V_PCH_PCIE_LCAP_PN6 (6 << 24) +#define V_PCH_PCIE_LCAP_PN7 (7 << 24) +#define V_PCH_PCIE_LCAP_PN8 (8 << 24) +#define B_PCH_PCIE_LCAP_LARC BIT20 +#define B_PCH_PCIE_LCAP_EL1 (BIT17 | BIT16 | BIT15) +#define B_PCH_PCIE_LCAP_EL0 (BIT14 | BIT13 | BIT12) +#define B_PCH_PCIE_LCAP_APMS (BIT11 | BIT10) +#define V_PCH_PCIE_LCAP_APMS_L0S (1 << 10) +#define V_PCH_PCIE_LCAP_APMS_L0S_L1 (3 << 10) +#define B_PCH_PCIE_LCAP_MLW 0x000003F0 +#define B_PCH_PCIE_LCAP_MLS 0x0000000F +#define R_PCH_PCIE_LCTL 0x50 +#define B_PCH_PCIE_LCTL_HAWD BIT9 +#define B_PCH_PCIE_LCTL_ES BIT7 +#define B_PCH_PCIE_LCTL_CCC BIT6 +#define B_PCH_PCIE_LCTL_RL BIT5 +#define B_PCH_PCIE_LCTL_LD BIT4 +#define B_PCH_PCIE_LCTL_RCBC BIT3 +#define B_PCH_PCIE_LCTL_APMC (BIT1 | BIT0) +#define V_PCH_PCIE_LCTL_APMC_L0S 1 +#define V_PCH_PCIE_LCTL_APMC_L1 2 +#define V_PCH_PCIE_LCTL_APMC_L0S_L1 3 +#define R_PCH_PCIE_LSTS 0x52 +#define S_PCH_PCIE_LSTS 2 +#define B_PCH_PCIE_LSTS_DLLA BIT13 +#define B_PCH_PCIE_LSTS_SCC BIT12 +#define B_PCH_PCIE_LSTS_LT BIT11 +#define B_PCH_PCIE_LSTS_LTE BIT10 +#define B_PCH_PCIE_LSTS_NLW 0x03F0 +#define V_PCH_PCIE_LSTS_NLW_1 0x0010 +#define V_PCH_PCIE_LSTS_NLW_2 0x0020 +#define V_PCH_PCIE_LSTS_NLW_4 0x0040 +#define B_PCH_PCIE_LSTS_LS 0x000F +#define R_PCH_PCIE_SLCAP 0x54 +#define S_PCH_PCIE_SLCAP 4 +#define B_PCH_PCIE_SLCAP_PSN 0xFFF80000 +#define B_PCH_PCIE_SLCAP_SLS 0x00018000 +#define B_PCH_PCIE_SLCAP_SLV 0x00007F80 +#define B_PCH_PCIE_SLCAP_HPC BIT6 +#define B_PCH_PCIE_SLCAP_HPS BIT5 +#define B_PCH_PCIE_SLCAP_PIP BIT4 +#define B_PCH_PCIE_SLCAP_AIP BIT3 +#define B_PCH_PCIE_SLCAP_MSP BIT2 +#define B_PCH_PCIE_SLCAP_PCP BIT1 +#define B_PCH_PCIE_SLCAP_ABP BIT0 +#define R_PCH_PCIE_SLCTL 0x58 +#define S_PCH_PCIE_SLCTL 2 +#define B_PCH_PCIE_SLCTL_LACE BIT12 +#define B_PCH_PCIE_SLCTL_PCC BIT10 +#define B_PCH_PCIE_SLCTL_HPE BIT5 +#define B_PCH_PCIE_SLCTL_PDE BIT3 +#define R_PCH_PCIE_SLSTS 0x5A +#define S_PCH_PCIE_SLSTS 2 +#define B_PCH_PCIE_SLSTS_LASC BIT8 +#define B_PCH_PCIE_SLSTS_PDS BIT6 +#define B_PCH_PCIE_SLSTS_MS BIT5 +#define B_PCH_PCIE_SLSTS_PDC BIT3 +#define B_PCH_PCIE_SLSTS_MSC BIT2 +#define B_PCH_PCIE_SLSTS_PFD BIT1 +#define R_PCH_PCIE_RCTL 0x5C +#define S_PCH_PCIE_RCTL 2 +#define B_PCH_PCIE_RCTL_PIE BIT3 +#define B_PCH_PCIE_RCTL_SFE BIT2 +#define B_PCH_PCIE_RCTL_SNE BIT1 +#define B_PCH_PCIE_RCTL_SCE BIT0 +#define R_PCH_PCIE_RSTS 0x60 +#define S_PCH_PCIE_RSTS 4 +#define B_PCH_PCIE_RSTS_PP BIT17 +#define B_PCH_PCIE_RSTS_PS BIT16 +#define B_PCH_PCIE_RSTS_RID 0x0000FFFF +#define R_PCH_PCIE_DCAP2 0x64 +#define B_PCH_PCIE_DCAP2_CTDS BIT4 +#define B_PCH_PCIE_DCAP2_CTRS 0xF +#define V_PCH_PCIE_DCAP2_CTRS_UNSUPPORTED 0x0 +#define V_PCH_PCIE_DCAP2_CTRS_RANGE_A 0x1 +#define V_PCH_PCIE_DCAP2_CTRS_RANGE_B 0x2 +#define V_PCH_PCIE_DCAP2_CTRS_RANGE_C 0x4 +#define V_PCH_PCIE_DCAP2_CTRS_RANGE_D 0x8 +#define R_PCH_PCIE_DCTL2 0x68 +#define B_PCH_PCIE_DCTL2_CTD BIT4 +#define B_PCH_PCIE_DCTL2_CTV 0xF +#define V_PCH_PCIE_DCTL2_CTV_DEFAULT 0x0 +#define V_PCH_PCIE_DCTL2_CTV_40MS_50MS 0x5 +#define V_PCH_PCIE_DCTL2_CTV_160MS_170MS 0x6 +#define V_PCH_PCIE_DCTL2_CTV_400MS_500MS 0x9 +#define V_PCH_PCIE_DCTL2_CTV_1P6S_1P7S 0xA +#define R_PCH_PCIE_LCTL2 0x70 +#define B_PCH_PCIE_LCTL2_TLS (BIT3 | BIT2 | BIT1 | BIT0) +#define R_PCH_PCIE_MID 0x80 +#define S_PCH_PCIE_MID 2 +#define B_PCH_PCIE_MID_NEXT 0xFF00 +#define B_PCH_PCIE_MID_CID 0x00FF +#define R_PCH_PCIE_MC 0x82 +#define S_PCH_PCIE_MC 2 +#define B_PCH_PCIE_MC_C64 BIT7 +#define B_PCH_PCIE_MC_MME (BIT6 | BIT5 | BIT4) +#define B_PCH_PCIE_MC_MMC 0x000E +#define B_PCH_PCIE_MC_MSIE BIT0 +#define R_PCH_PCIE_MA 0x84 +#define S_PCH_PCIE_MA 4 +#define B_PCH_PCIE_MA_ADDR 0xFFFFFFFC +#define R_PCH_PCIE_MD 0x88 +#define S_PCH_PCIE_MD 2 +#define B_PCH_PCIE_MD_DATA 0xFFFF +#define R_PCH_PCIE_SVCAP 0x90 +#define S_PCH_PCIE_SVCAP 2 +#define B_PCH_PCIE_SVCAP_NEXT 0xFF00 +#define B_PCH_PCIE_SVCAP_CID 0x00FF +#define R_PCH_PCIE_SVID 0x94 +#define S_PCH_PCIE_SVID 4 +#define B_PCH_PCIE_SVID_SID 0xFFFF0000 +#define B_PCH_PCIE_SVID_SVID 0x0000FFFF +#define R_PCH_PCIE_PMCAP 0xA0 +#define S_PCH_PCIE_PMCAP 2 +#define B_PCH_PCIE_PMCAP_NEXT 0xFF00 +#define B_PCH_PCIE_PMCAP_CID 0x00FF +#define R_PCH_PCIE_PMC 0xA2 +#define S_PCH_PCIE_PMC 2 +#define B_PCH_PCIE_PMC_PMES 0xF800 +#define B_PCH_PCIE_PMC_D2S BIT10 +#define B_PCH_PCIE_PMC_D1S BIT9 +#define B_PCH_PCIE_PMC_AC 0x01C0 +#define B_PCH_PCIE_PMC_DSI BIT5 +#define B_PCH_PCIE_PMC_PMEC BIT3 +#define B_PCH_PCIE_PMC_VS 0x0007 +#define R_PCH_PCIE_PMCS 0xA4 +#define S_PCH_PCIE_PMCS 4 +#define B_PCH_PCIE_PMCS_BPCE BIT23 +#define B_PCH_PCIE_PMCS_B23S BIT22 +#define B_PCH_PCIE_PMCS_PMES BIT15 +#define B_PCH_PCIE_PMCS_PMEE BIT8 +#define B_PCH_PCIE_PMCS_PS (BIT1 | BIT0) +#define V_PCH_PCIE_PMCS_D0 0x00 +#define V_PCH_PCIE_PMCS_D3H 0x03 +#define R_PCH_PCIE_CCFG 0xD0 +#define B_PCH_PCIE_CCFG_DCGEISMA BIT17 +#define R_PCH_PCIE_MPC2 0xD4 +#define S_PCH_PCIE_MPC2 4 +#define B_PCH_PCIE_MPC2_PCME BIT5 +#define B_PCH_PCIE_MPC2_ASPMCOEN BIT4 +#define B_PCH_PCIE_MPC2_ASPMCO (BIT3 | BIT2) +#define V_PCH_PCIE_MPC2_ASPMCO_DISABLED 0 +#define V_PCH_PCIE_MPC2_ASPMCO_L0S 1 << 2 +#define V_PCH_PCIE_MPC2_ASPMCO_L1 2 << 2 +#define V_PCH_PCIE_MPC2_ASPMCO_L0S_L1 3 << 2 +#define B_PCH_PCIE_MPC2_EOIFD BIT1 +#define B_PCH_PCIE_MPC2_L1CTM BIT0 +#define R_PCH_PCIE_MPC 0xD8 +#define S_PCH_PCIE_MPC 4 +#define B_PCH_PCIE_MPC_PMCE BIT31 +#define B_PCH_PCIE_MPC_HPCE BIT30 +#define B_PCH_PCIE_MPC_LHO BIT29 +#define B_PCH_PCIE_MPC_ATE BIT28 +#define B_PCH_PCIE_MPC_MMBNCE BIT27 +#define B_PCH_PCIE_MPC_IRBNCE BIT26 +#define B_PCH_PCIE_MPC_IRRCE BIT25 +#define B_PCH_PCIE_MPC_BMERCE BIT24 +#define B_PCH_PCIE_MPC_FORCEDET BIT22 +#define B_PCH_PCIE_MPC_FCDL1E BIT21 +#define B_PCH_PCIE_MPC_UCEL (BIT20 | BIT19 | BIT18) +#define B_PCH_PCIE_MPC_CCEL (BIT17 | BIT16 | BIT15) +#define B_PCH_PCIE_MPC_PAE BIT7 +#define B_PCH_PCIE_MPC_MCTPSE BIT3 +#define B_PCH_PCIE_MPC_BT BIT2 +#define B_PCH_PCIE_MPC_HPME BIT1 +#define N_PCH_PCIE_MPC_HPME 1 +#define B_PCH_PCIE_MPC_PMME BIT0 +#define R_PCH_PCIE_SMSCS 0xDC +#define S_PCH_PCIE_SMSCS 4 +#define B_PCH_PCIE_SMSCS_PMCS BIT31 +#define B_PCH_PCIE_SMSCS_HPCS BIT30 +#define B_PCH_PCIE_SMSCS_HPLAS BIT4 +#define N_PCH_PCIE_SMSCS_HPLAS 4 +#define B_PCH_PCIE_SMSCS_HPCCM BIT3 +#define B_PCH_PCIE_SMSCS_HPABM BIT2 +#define B_PCH_PCIE_SMSCS_HPPDM BIT1 +#define N_PCH_PCIE_SMSCS_HPPDM 1 +#define B_PCH_PCIE_SMSCS_PMMS BIT0 +#define R_PCH_PCIE_RPDCGEN 0xE1 +#define S_PCH_PCIE_RPDCGEN 1 +#define B_PCH_PCIE_RPDCGEN_RPSCGEN BIT7 +#define B_PCH_PCIE_RPDCGEN_POCGE BIT6 +#define B_PCH_PCIE_RPDCGEN_LCLKREQEN BIT5 +#define B_PCH_PCIE_RPDCGEN_BBCLKREQEN BIT4 +#define B_PCH_PCIE_RPDCGEN_SRDLCGEN BIT3 +#define B_PCH_PCIE_RPDCGEN_SRDBCGEN BIT2 +#define B_PCH_PCIE_RPDCGEN_RPDLCGEN BIT1 +#define B_PCH_PCIE_RPDCGEN_RPDBCGEN BIT0 +#define R_PCH_PCIE_RPPGEN 0xE2 +#define B_PCH_PCIE_RPPGEN_PTOTOP BIT6 +#define B_PCH_PCIE_RPPGEN_LMSDOCGE BIT5 +#define B_PCH_PCIE_RPPGEN_SEOCGE BIT4 +#define R_PCH_PCIE_PECR1 0xE8 +#define S_PCH_PCIE_PECR1 4 +#define B_PCH_PCIE_PECR1_FIELD_2 BIT1 +#define V_PCH_PCIE_PECR1_FIELD_3 (BIT3 | BIT2) +#define R_PCH_PCIE_PECR3 0xEC +#define B_PCH_PCIE_PECR3_SDCDID BIT1 ///< Subtractive Decode Compatibility Device ID +#define B_PCH_PCIE_PECR3_SDE BIT0 ///< Subtractive Decode Enable +#define R_PCH_PCIE_STRPFUSECFG 0xFC +#define B_PCH_PCIE_STRPFUSECFG_SATAP3_PCIEP6L0_MODE (BIT23 | BIT22) +#define B_PCH_PCIE_STRPFUSECFG_SATAP2_PCIEP6L1_MODE (BIT21 | BIT20) +#define B_PCH_PCIE_STRPFUSECFG_SATAP5_PCIEP2_MODE (BIT23 | BIT22) +#define B_PCH_PCIE_STRPFUSECFG_SATAP4_PCIEP1_MODE (BIT21 | BIT20) +#define B_PCH_PCIE_STRPFUSECFG_GBE_PCIE_PEN (BIT19) +#define B_PCH_PCIE_STRPFUSECFG_GBE_PCIEPORTSEL (BIT18 | BIT17 | BIT16) +#define N_PCH_PCIE_STRPFUSECFG_GBE_PCIEPORTSEL 16 +#define B_PCH_PCIE_STRPFUSECFG_RPC (BIT15 | BIT14) +#define V_PCH_PCIE_STRPFUSECFG_RPC_1_1_1_1 (0) +#define V_PCH_PCIE_STRPFUSECFG_RPC_2_1_1 (BIT14) +#define V_PCH_PCIE_STRPFUSECFG_RPC_2_2 (BIT15) +#define V_PCH_PCIE_STRPFUSECFG_RPC_4 (BIT15 | BIT14) +#define N_PCH_PCIE_STRPFUSECFG_RPC_4 14 +#define B_PCH_PCIE_STRPFUSECFG_SATAP3_PCIEP6L0_MODE_FUSE (BIT13 | BIT12) +#define B_PCH_PCIE_STRPFUSECFG_SATAP2_PCIEP6L1_MODE_FUSE (BIT11 | BIT10) +#define B_PCH_PCIE_STRPFUSECFG_SATAP5_PCIEP2_MODE_FUSE (BIT13 | BIT12) +#define B_PCH_PCIE_STRPFUSECFG_SATAP4_PCIEP1_MODE_FUSE (BIT11 | BIT10) +#define B_PCH_PCIE_STRPFUSECFG_mPHYIOPMDIS (BIT9) +#define B_PCH_PCIE_STRPFUSECFG_PLLSHTDWNDIS (BIT8) +#define B_PCH_PCIE_STRPFUSECFG_STPGATEDIS (BIT7) +#define B_PCH_PCIE_STRPFUSECFG_ASPMDIS (BIT6) +#define B_PCH_PCIE_STRPFUSECFG_LDCGDIS (BIT5) +#define B_PCH_PCIE_STRPFUSECFG_LTCGDIS (BIT4) +#define B_PCH_PCIE_STRPFUSECFG_BDCGDIS (BIT3) +#define B_PCH_PCIE_STRPFUSECFG_DESKTOPMOB (BIT1) +#define R_PCH_PCIE_AECH 0x100 +#define R_PCH_PCIE_UES 0x104 +#define S_PCH_PCIE_UES 4 +#define B_PCH_PCIE_UES_URE BIT20 +#define B_PCH_PCIE_UES_EE BIT19 +#define B_PCH_PCIE_UES_MT BIT18 +#define B_PCH_PCIE_UES_RO BIT17 +#define B_PCH_PCIE_UES_UC BIT16 +#define B_PCH_PCIE_UES_CA BIT15 +#define B_PCH_PCIE_UES_CT BIT14 +#define B_PCH_PCIE_UES_FCPE BIT13 +#define B_PCH_PCIE_UES_PT BIT12 +#define B_PCH_PCIE_UES_DLPE BIT4 +#define B_PCH_PCIE_UES_TE BIT0 +#define R_PCH_PCIE_UEM 0x108 +#define S_PCH_PCIE_UEM 4 +#define B_PCH_PCIE_UEM_URE BIT20 +#define B_PCH_PCIE_UEM_EE BIT19 +#define B_PCH_PCIE_UEM_MT BIT18 +#define B_PCH_PCIE_UEM_RO BIT17 +#define B_PCH_PCIE_UEM_UC BIT16 +#define B_PCH_PCIE_UEM_CA BIT15 +#define B_PCH_PCIE_UEM_CT BIT14 +#define B_PCH_PCIE_UEM_FCPE BIT13 +#define B_PCH_PCIE_UEM_PT BIT12 +#define B_PCH_PCIE_UEM_DLPE BIT4 +#define B_PCH_PCIE_UEM_TE BIT0 +#define R_PCH_PCIE_UEV 0x10C +#define S_PCH_PCIE_UEV 4 +#define B_PCH_PCIE_UEV_URE BIT20 +#define B_PCH_PCIE_UEV_EE BIT19 +#define B_PCH_PCIE_UEV_MT BIT18 +#define B_PCH_PCIE_UEV_RO BIT17 +#define B_PCH_PCIE_UEV_UC BIT16 +#define B_PCH_PCIE_UEV_CA BIT15 +#define B_PCH_PCIE_UEV_CT BIT14 +#define B_PCH_PCIE_UEV_FCPE BIT13 +#define B_PCH_PCIE_UEV_PT BIT12 +#define B_PCH_PCIE_UEV_DLPE BIT4 +#define B_PCH_PCIE_UEV_TE BIT0 +#define R_PCH_PCIE_CES 0x110 +#define S_PCH_PCIE_CES 4 +#define B_PCH_PCIE_CES_ANFES BIT13 +#define B_PCH_PCIE_CES_RTT BIT12 +#define B_PCH_PCIE_CES_RNR BIT8 +#define B_PCH_PCIE_CES_BD BIT7 +#define B_PCH_PCIE_CES_BT BIT6 +#define B_PCH_PCIE_CES_RE BIT0 +#define R_PCH_PCIE_CEM 0x114 +#define S_PCH_PCIE_CEM 4 +#define B_PCH_PCIE_CEM_ANFEM BIT13 +#define B_PCH_PCIE_CEM_RTT BIT12 +#define B_PCH_PCIE_CEM_RNR BIT8 +#define B_PCH_PCIE_CEM_BD BIT7 +#define B_PCH_PCIE_CEM_BT BIT6 +#define B_PCH_PCIE_CEM_RE BIT0 +#define R_PCH_PCIE_AECC 0x118 +#define S_PCH_PCIE_AECC 4 +#define B_PCH_PCIE_AECC_ECE BIT8 +#define B_PCH_PCIE_AECC_ECC BIT7 +#define B_PCH_PCIE_AECC_EGE BIT6 +#define B_PCH_PCIE_AECC_EGC BIT5 +#define B_PCH_PCIE_AECC_FEP 0x0000001F +#define R_PCH_PCIE_RES 0x130 +#define S_PCH_PCIE_RES 4 +#define B_PCH_PCIE_RES_AEMN 0xF8000000 +#define B_PCH_PCIE_RES_FEMR BIT6 +#define B_PCH_PCIE_RES_NFEMR BIT5 +#define B_PCH_PCIE_RES_FUF BIT4 +#define B_PCH_PCIE_RES_MENR BIT3 +#define B_PCH_PCIE_RES_ENR BIT2 +#define B_PCH_PCIE_RES_MCR BIT1 +#define B_PCH_PCIE_RES_CR BIT0 +#define R_PCH_PCIE_PECR2 0x320 +#define S_PCH_PCIE_PECR2 4 +#define B_PCH_PCIE_PECR2_FIELD_1 BIT21 +#define R_PCH_PCIE_PEETM 0x324 +#define S_PCH_PCIE_PEETM 1 +#define B_PCH_PCIE_PEETM_BAU BIT2 +#define R_PCH_PCIE_PEC1 0x330 +#define S_PCH_PCIE_PEC1 4 +#define B_PCH_PCIE_PEC1_FIELD_1 0xFF +#define R_PCH_PCIE_LTROVR 0x400 +#define R_PCH_PCIE_LTROVR2 0x404 +#define R_PCH_PCIE_L1SECH 0x200 +#define V_PCH_PCIE_L1SECH_L1SUBST_CAP_ID 0x1E +#define R_PCH_PCIE_L1SCAP 0x204 +#define R_PCH_PCIE_PCIEPMECTL 0x420 +#define B_PCH_PCIE_PCIEPMECTL_FDPGE BIT31 +#define B_PCH_PCIE_PCIEPMECTL_DLSULPGE BIT30 +#define B_PCH_PCIE_PCIEPMECTL_DLSULDLSD BIT29 +#define B_PCH_PCIE_PCIEPMECTL_L1LE BIT17 +#define V_PCH_PCIE_PCIEPMECTL_L1LTRTLV (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4) +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsRcrb.h b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsRcrb.h new file mode 100644 index 0000000..a5206e4 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsRcrb.h @@ -0,0 +1,483 @@ +/** @file + Register names for PCH Chipset Configuration Registers + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_LPT_" + - Registers / bits that are different between SKUs are denoted by "_<SKU_name>" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without <generation_name> inserted. + +@copyright + Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _PCH_REGS_RCRB_H_ +#define _PCH_REGS_RCRB_H_ + +// +// Chipset configuration registers (Memory space) +// RCBA +// +#define R_PCH_RCRB_CIR0050 0x0050 +#define B_PCH_RCRB_CIR0_TCLOCKDN BIT31 +#define R_PCH_RCRB_RPFN 0x0404 ///< Root Port Function Number & Hide for PCI Express Root Ports +#define B_PCH_RCRB_RPFN_RP8CH BIT31 ///< Root Port 8 Hide +#define B_PCH_RCRB_RPFN_RP8FN (BIT30 | BIT29 | BIT28) ///< Root Port 8 Function Number +#define B_PCH_RCRB_RPFN_RP7CH BIT27 ///< Root Port 7 Hide +#define B_PCH_RCRB_RPFN_RP7FN (BIT26 | BIT25 | BIT24) ///< Root Port 7 Function Number +#define B_PCH_RCRB_RPFN_RP6CH BIT23 ///< Root Port 6 Hide +#define B_PCH_RCRB_RPFN_RP6FN (BIT22 | BIT21 | BIT20) ///< Root Port 6 Function Number +#define B_PCH_RCRB_RPFN_RP5CH BIT19 ///< Root Port 5 Hide +#define B_PCH_RCRB_RPFN_RP5FN (BIT18 | BIT17 | BIT16) ///< Root Port 5 Function Number +#define B_PCH_RCRB_RPFN_RP4CH BIT15 ///< Root Port 4 Hide +#define B_PCH_RCRB_RPFN_RP4FN (BIT14 | BIT13 | BIT12) ///< Root Port 4 Function Number +#define B_PCH_RCRB_RPFN_RP3CH BIT11 ///< Root Port 3 Hide +#define B_PCH_RCRB_RPFN_RP3FN (BIT10 | BIT9 | BIT8) ///< Root Port 3 Function Number +#define B_PCH_RCRB_RPFN_RP2CH BIT7 ///< Root Port 2 Hide +#define B_PCH_RCRB_RPFN_RP2FN (BIT6 | BIT5 | BIT4) ///< Root Port 2 Function Number +#define B_PCH_RCRB_RPFN_RP1CH BIT3 ///< Root Port 1 Hide +#define B_PCH_RCRB_RPFN_RP1FN (BIT2 | BIT1 | BIT0) ///< Root Port 1 Function Number +#define S_PCH_RCRB_PRFN_RP_FIELD 4 ///< 4 bits per root port +#define R_PCH_RCRB_CIR0900 0x0900 +#define R_PCH_RCRB_CIR1100 0x1100 +#define R_PCH_RCRB_TRSR 0x1E00 ///< Trap Status Register +#define B_PCH_RCRB_TRSR_CTSS 0x000F ///< Cycle Trap SMI# Status mask +#define R_PCH_RCRB_TRCR 0x1E10 ///< Trapped Cycle Register +#define S_PCH_RCRB_TRCR 8 +#define B_PCH_RCRB_TRCR_RWI BIT24 +#define B_PCH_RCRB_TRCR_AHBE 0x00000000000F0000 +#define B_PCH_RCRB_TRCR_TIOA 0x000000000000FFFC +#define R_PCH_RCRB_TRWDR 0x1E18 ///< Trap Write Data Register +#define S_PCH_RCRB_TRWDR 8 +#define B_PCH_RCRB_TRWDR_TIOD 0x00000000FFFFFFFF +#define R_PCH_RCRB_IO_TRAP_0 0x1E80 ///< Trap Configuration Register +#define R_PCH_RCRB_IO_TRAP_1 0x1E88 ///< Trap Configuration Register +#define R_PCH_RCRB_IO_TRAP_2 0x1E90 ///< Trap Configuration Register +#define R_PCH_RCRB_IO_TRAP_3 0x1E98 ///< Trap Configuration Register +#define B_PCH_RCRB_IO_TRAP_RWM BIT17 ///< 49 - 32 for 32 bit access +#define B_PCH_RCRB_IO_TRAP_RWIO BIT16 ///< 48 - 32 for 32 bit access +#define N_PCH_RCRB_IO_TRAP_RWIO (48 - 32) ///< for 32 bit access +#define B_PCH_RCRB_IO_TRAP_BEM 0x000000F000000000 +#define B_PCH_RCRB_IO_TRAP_TBE 0x0000000F00000000 +#define B_PCH_RCRB_IO_TRAP_ADMA 0x0000000000FC0000 +#define B_PCH_RCRB_IO_TRAP_IOAD 0x000000000000FFFC +#define B_PCH_RCRB_IO_TRAP_TRSE BIT0 ///< Trap and SMI# Enable +#define R_PCH_RCRB_V0CTL 0x2014 ///< Virtual channel 0 resource control +#define B_PCH_RCRB_V0CTL_EN BIT31 +#define B_PCH_RCRB_V0CTL_ID (7 << 24) ///< Bit[26:24] +#define N_PCH_RCRB_V0CTL_ID 24 +#define V_PCH_RCRB_V0CTL_ETVM_MASK 0xFC00 +#define V_PCH_RCRB_V0CTL_TVM_MASK 0x7E +#define R_PCH_RCRB_V0STS 0x201A ///< Virtual channel 0 status +#define B_PCH_RCRB_V0STS_NP BIT1 +#define R_PCH_RCRB_V1CTL 0x2020 ///< Virtual channel 1 resource control +#define B_PCH_RCRB_V1CTL_EN BIT31 +#define B_PCH_RCRB_V1CTL_ID (0x0F << 24) ///< Bit[27:24] +#define N_PCH_RCRB_V1CTL_ID 24 +#define V_PCH_RCRB_V1CTL_ETVM_MASK 0xFC00 +#define V_PCH_RCRB_V1CTL_TVM_MASK 0xFE +#define R_PCH_RCRB_V1STS 0x2026 ///< Virtual channel 1 status +#define B_PCH_RCRB_V1STS_NP BIT1 +#define R_PCH_RCRB_CIR2030 0x2030 ///< Priority Virtual Channel resource control +#define R_PCH_RCRB_CIR2040 0x2040 ///< Priority Virtual Channel resource control +#define R_PCH_RCRB_CIR2088 0x2088 +#define R_PCH_RCRB_REC 0x20AC +#define B_PCH_RCRB_REC_DPDP (BIT31) +#define R_PCH_RCRB_LCAP 0x21A4 ///< Link capabilities +#define B_PCH_RCRB_LCAP_EL1 (BIT17 | BIT16 | BIT15) +#define B_PCH_RCRB_LCAP_EL0 (BIT14 | BIT13 | BIT12) +#define B_PCH_RCRB_LCAP_APMS (BIT11 | BIT10) ///< L0 is supported on DMI +#define B_PCH_RCRB_LCAP_MLW 0x000003F0 +#define B_PCH_RCRB_LCAP_MLS 0x0000000F +#define R_PCH_RCRB_LCTL 0x21A8 ///< Link control +#define B_PCH_RCRB_LCTL_ES BIT7 +#define B_PCH_RCRB_LCTL_APMC (BIT1 | BIT0) +#define V_PCH_RCRB_LCTL_APMC_DIS 0x00 +#define V_PCH_RCRB_LCTL_APMC_L0S_EN 0x01 +#define R_PCH_RCRB_LSTS 0x21AA +#define B_PCH_RCRB_LSTS_NLW 0x03F0 +#define B_PCH_RCRB_LSTS_LS 0x000F +#define R_PCH_RCRB_DMIC 0x2234 ///< DMI control register +#define B_PCH_H_RCRB_DMIC_DMICGEN (BIT3 | BIT2 | BIT1 | BIT0) ///< DMI Clock Gate Enable for PCH H +#define B_PCH_LP_RCRB_DMIC_DMICGEN (BIT3 | BIT2 | BIT1 | BIT0) ///< DMI Clock Gate Enable for PCH LP +#define R_PCH_RCRB_CIR2238 0x2238 ///< Chipset Initialization Register 2238 +#define R_PCH_RCBA_CIR228C 0x228C ///< Chipset Initialization Register 228C +#define R_PCH_RCRB_DMC 0x2304 ///< DMI Miscellaneous Control Register +#define R_PCH_RCRB_CIR2314 0x2314 +#define R_PCH_RCRB_CIR2320 0x2320 +#define R_PCH_RCRB_IOBPIRI 0x2330 ///< IOBP Indexed Register Index +#define B_PCH_RCRB_IOBPIRI_IOBPIS 0xFF000000 ///< IOBP Interface Select +#define V_PCH_RCRB_IOBPIRI_IOBPIS_SATA 0xEA000000 ///< SATA (Ports 0 and Ports 1) +#define V_PCH_RCRB_IOBPIRI_IOBPIS_DMI 0xEB000000 ///< DMI +#define V_PCH_RCRB_IOBPIRI_IOBPIS_PCIE 0xEC000000 ///< PCIe +#define B_PCH_RCRB_IOBPIRI_IOBPFS 0xFFFF ///< IOBP Function Select +#define R_PCH_RCRB_IOBPD 0x2334 ///< IOBP Indexed Register Data +#define R_PCH_RCRB_IOBPS 0x2338 ///< IOBP Status +#define B_PCH_RCRB_IOBPS_IOBPIA 0xFF00 ///< IOBP Interface Access +#define V_PCH_RCRB_IOBPS_IOBPIA_R 0x0600 ///< Read access +#define V_PCH_RCRB_IOBPS_IOBPIA_W 0x0700 ///< Write access +#define B_PCH_RCRB_IOBPS (BIT2 | BIT1) ///< Status for the transaction +#define V_PCH_RCRB_IOBPS_SUCCESS 0 ///< Successful +#define V_PCH_RCRB_IOBPS_UNSUCCESS BIT1 ///< Unsuccessful +#define V_PCH_RCRB_IOBPS_POWEREDDOWN BIT2 ///< Powered Down +#define B_PCH_RCRB_IOBPS_BUSY BIT0 +#define R_PCH_RCRB_TCTL 0x3000 ///< TCO Configuration register +#define B_PCH_RCRB_TCTL_IE BIT7 ///< TCO IRQ Enable +#define B_PCH_RCRB_TCTL_IS (BIT2 | BIT1 | BIT0) ///< TCO IRQ Select +#define V_PCH_RCRB_TCTL_IRQ_9 0x00 +#define V_PCH_RCRB_TCTL_IRQ_10 0x01 +#define V_PCH_RCRB_TCTL_IRQ_11 0x02 +#define V_PCH_RCRB_TCTL_IRQ_20 0x04 ///< only if APIC enabled +#define V_PCH_RCRB_TCTL_IRQ_21 0x05 ///< only if APIC enabled +#define V_PCH_RCRB_TCTL_IRQ_22 0x06 ///< only if APIC enabled +#define V_PCH_RCRB_TCTL_IRQ_23 0x07 ///< only if APIC enabled +#define R_PCH_RCRB_D31IP 0x3100 ///< Device 31 interrupt pin +#define B_PCH_RCRB_D31IP_TTIP (BIT27 | BIT26 | BIT25 | BIT24) +#define V_PCH_RCRB_D31IP_TTIP_INTA (1 << 24) +#define V_PCH_RCRB_D31IP_TTIP_INTB (2 << 24) +#define V_PCH_RCRB_D31IP_TTIP_INTC (3 << 24) +#define V_PCH_RCRB_D31IP_TTIP_INTD (4 << 24) +#define B_PCH_RCRB_D31IP_SIP2 (BIT23 | BIT22 | BIT21 | BIT20) +#define V_PCH_RCRB_D31IP_SIP2_INTA (1 << 20) +#define V_PCH_RCRB_D31IP_SIP2_INTB (2 << 20) +#define V_PCH_RCRB_D31IP_SIP2_INTC (3 << 20) +#define V_PCH_RCRB_D31IP_SIP2_INTD (4 << 20) +#define B_PCH_RCRB_D31IP_SMIP (BIT15 | BIT14 | BIT13 | BIT12) +#define V_PCH_RCRB_D31IP_SMIP_INTA (1 << 12) +#define V_PCH_RCRB_D31IP_SMIP_INTB (2 << 12) +#define V_PCH_RCRB_D31IP_SMIP_INTC (3 << 12) +#define V_PCH_RCRB_D31IP_SMIP_INTD (4 << 12) +#define B_PCH_RCRB_D31IP_SIP (BIT11 | BIT10 | BIT9 | BIT8) +#define V_PCH_RCRB_D31IP_SIP_INTA (1 << 8) +#define V_PCH_RCRB_D31IP_SIP_INTB (2 << 8) +#define V_PCH_RCRB_D31IP_SIP_INTC (3 << 8) +#define V_PCH_RCRB_D31IP_SIP_INTD (4 << 8) +#define B_PCH_RCRB_D31IP_LIP (BIT3 | BIT2 | BIT1 | BIT0) +#define R_PCH_RCRB_D29IP 0x3108 ///< Device 29 interrupt pin +#define B_PCH_RCRB_D29IP_E1P (BIT3 | BIT2 | BIT1 | BIT0) +#define V_PCH_RCRB_D29IP_E1P_INTA (1 << 0) +#define V_PCH_RCRB_D29IP_E1P_INTB (2 << 0) +#define V_PCH_RCRB_D29IP_E1P_INTC (3 << 0) +#define V_PCH_RCRB_D29IP_E1P_INTD (4 << 0) +#define R_PCH_RCRB_D28IP 0x310C ///< Device 28 interrupt pin +#define B_PCH_RCRB_D28IP_P8IP (BIT31 | BIT30 | BIT29 | BIT28) +#define V_PCH_RCRB_D28IP_P8IP_INTA (1 << 28) +#define V_PCH_RCRB_D28IP_P8IP_INTB (2 << 28) +#define V_PCH_RCRB_D28IP_P8IP_INTC (3 << 28) +#define V_PCH_RCRB_D28IP_P8IP_INTD (4 << 28) +#define B_PCH_RCRB_D28IP_P7IP (BIT27 | BIT26 | BIT25 | BIT24) +#define V_PCH_RCRB_D28IP_P7IP_INTA (1 << 24) +#define V_PCH_RCRB_D28IP_P7IP_INTB (2 << 24) +#define V_PCH_RCRB_D28IP_P7IP_INTC (3 << 24) +#define V_PCH_RCRB_D28IP_P7IP_INTD (4 << 24) +#define B_PCH_RCRB_D28IP_P6IP (BIT23 | BIT22 | BIT21 | BIT20) +#define V_PCH_RCRB_D28IP_P6IP_INTA (1 << 20) +#define V_PCH_RCRB_D28IP_P6IP_INTB (2 << 20) +#define V_PCH_RCRB_D28IP_P6IP_INTC (3 << 20) +#define V_PCH_RCRB_D28IP_P6IP_INTD (4 << 20) +#define B_PCH_RCRB_D28IP_P5IP (BIT19 | BIT18 | BIT17 | BIT16) +#define V_PCH_RCRB_D28IP_P5IP_INTA (1 << 16) +#define V_PCH_RCRB_D28IP_P5IP_INTB (2 << 16) +#define V_PCH_RCRB_D28IP_P5IP_INTC (3 << 16) +#define V_PCH_RCRB_D28IP_P5IP_INTD (4 << 16) +#define B_PCH_RCRB_D28IP_P4IP (BIT15 | BIT14 | BIT13 | BIT12) +#define V_PCH_RCRB_D28IP_P4IP_INTA (1 << 12) +#define V_PCH_RCRB_D28IP_P4IP_INTB (2 << 12) +#define V_PCH_RCRB_D28IP_P4IP_INTC (3 << 12) +#define V_PCH_RCRB_D28IP_P4IP_INTD (4 << 12) +#define B_PCH_RCRB_D28IP_P3IP (BIT11 | BIT10 | BIT9 | BIT8) +#define V_PCH_RCRB_D28IP_P3IP_INTA (1 << 8) +#define V_PCH_RCRB_D28IP_P3IP_INTB (2 << 8) +#define V_PCH_RCRB_D28IP_P3IP_INTC (3 << 8) +#define V_PCH_RCRB_D28IP_P3IP_INTD (4 << 8) +#define B_PCH_RCRB_D28IP_P2IP (BIT7 | BIT6 | BIT5 | BIT4) +#define V_PCH_RCRB_D28IP_P2IP_INTA (1 << 4) +#define V_PCH_RCRB_D28IP_P2IP_INTB (2 << 4) +#define V_PCH_RCRB_D28IP_P2IP_INTC (3 << 4) +#define V_PCH_RCRB_D28IP_P2IP_INTD (4 << 4) +#define B_PCH_RCRB_D28IP_P1IP (BIT3 | BIT2 | BIT1 | BIT0) +#define V_PCH_RCRB_D28IP_P1IP_INTA (1 << 0) +#define V_PCH_RCRB_D28IP_P1IP_INTB (2 << 0) +#define V_PCH_RCRB_D28IP_P1IP_INTC (3 << 0) +#define V_PCH_RCRB_D28IP_P1IP_INTD (4 << 0) +#define R_PCH_RCRB_D27IP 0x3110 ///< Device 27 interrupt pin +#define B_PCH_RCRB_D27IP_ZIP (BIT3 | BIT2 | BIT1 | BIT0) +#define V_PCH_RCRB_D27IP_ZIP_INTA (1 << 0) +#define V_PCH_RCRB_D27IP_ZIP_INTB (2 << 0) +#define V_PCH_RCRB_D27IP_ZIP_INTC (3 << 0) +#define V_PCH_RCRB_D27IP_ZIP_INTD (4 << 0) +#define R_PCH_RCRB_D26IP 0x3114 ///< Device 26 interrupt pin +#define B_PCH_RCRB_D26IP_E2P (BIT3 | BIT2 | BIT1 | BIT0) +#define V_PCH_RCRB_D26IP_E2P_INTA (1 << 0) +#define V_PCH_RCRB_D26IP_E2P_INTB (2 << 0) +#define V_PCH_RCRB_D26IP_E2P_INTC (3 << 0) +#define V_PCH_RCRB_D26IP_E2P_INTD (4 << 0) +#define R_PCH_RCRB_D25IP 0x3118 ///< Device 25 interrupt pin +#define B_PCH_RCRB_D25IP_LIP (BIT3 | BIT2 | BIT1 | BIT0) +#define V_PCH_RCRB_D25IP_LIP_INTA (1 << 0) +#define V_PCH_RCRB_D25IP_LIP_INTB (2 << 0) +#define V_PCH_RCRB_D25IP_LIP_INTC (3 << 0) +#define V_PCH_RCRB_D25IP_LIP_INTD (4 << 0) +#define R_PCH_RCRB_D22IP 0x3124 ///< Device 22 interrupt pin +#define B_PCH_RCRB_D22IP_KTIP (BIT15 | BIT14 | BIT13 | BIT12) +#define V_PCH_RCRB_D22IP_KTIP_INTA (1 << 12) +#define V_PCH_RCRB_D22IP_KTIP_INTB (2 << 12) +#define V_PCH_RCRB_D22IP_KTIP_INTC (3 << 12) +#define V_PCH_RCRB_D22IP_KTIP_INTD (4 << 12) +#define B_PCH_RCRB_D22IP_IDERIP (BIT11 | BIT10 | BIT9 | BIT8) +#define V_PCH_RCRB_D22IP_IDERIP_INTA (1 << 8) +#define V_PCH_RCRB_D22IP_IDERIP_INTB (2 << 8) +#define V_PCH_RCRB_D22IP_IDERIP_INTC (3 << 8) +#define V_PCH_RCRB_D22IP_IDERIP_INTD (4 << 8) +#define B_PCH_RCRB_D22IP_MEI2IP (BIT7 | BIT6 | BIT5 | BIT4) +#define V_PCH_RCRB_D22IP_MEI2IP_INTA (1 << 4) +#define V_PCH_RCRB_D22IP_MEI2IP_INTB (2 << 4) +#define V_PCH_RCRB_D22IP_MEI2IP_INTC (3 << 4) +#define V_PCH_RCRB_D22IP_MEI2IP_INTD (4 << 4) +#define B_PCH_RCRB_D22IP_MEI1IP (BIT3 | BIT2 | BIT1 | BIT0) +#define V_PCH_RCRB_D22IP_MEI1IP_INTA (1 << 0) +#define V_PCH_RCRB_D22IP_MEI1IP_INTB (2 << 0) +#define V_PCH_RCRB_D22IP_MEI1IP_INTC (3 << 0) +#define V_PCH_RCRB_D22IP_MEI1IP_INTD (4 << 0) +#define R_PCH_RCRB_D20IP 0x3128 ///< Device 20 interrupt pin +#define B_PCH_RCRB_D20IP_XHCIP (BIT3 | BIT2 | BIT1 | BIT0) +#define V_PCH_RCRB_D20IP_XHCIP_INTA (1 << 0) +#define V_PCH_RCRB_D20IP_XHCIP_INTB (2 << 0) +#define V_PCH_RCRB_D20IP_XHCIP_INTC (3 << 0) +#define V_PCH_RCRB_D20IP_XHCIP_INTD (4 << 0) +#define R_PCH_RCRB_D31IR 0x3140 ///< Device 31 interrupt route +#define R_PCH_RCRB_D29IR 0x3144 ///< Device 29 interrupt route +#define R_PCH_RCRB_D28IR 0x3146 ///< Device 28 interrupt route +#define R_PCH_RCRB_D27IR 0x3148 ///< Device 27 interrupt route +#define R_PCH_RCRB_D26IR 0x314C ///< Device 26 interrupt route +#define R_PCH_RCRB_D25IR 0x3150 ///< Device 25 interrupt route +#define R_PCH_RCRB_D23IR 0x3158 ///< Device 23 interrupt route +#define R_PCH_RCRB_D22IR 0x315C ///< Device 22 interrupt route +#define R_PCH_RCRB_D20IR 0x3160 ///< Device 20 interrupt route +#define R_PCH_RCRB_D21IR 0x3164 ///< Device 21 interrupt route +#define B_PCH_RCRB_D21IR_IE BIT15 +#define R_PCH_RCRB_D19IR 0x3168 ///< Device 19 interrupt route +#define B_PCH_RCRB_D19IR_IS (BIT19 | BIT18 | BIT17 | BIT16) +#define B_PCH_RCRB_D19IR_IE BIT15 +#define B_PCH_RCRB_DXXIR_IDR_MASK (BIT14 | BIT13 | BIT12) +#define V_PCH_RCRB_DXXIR_IDR_PIRQA 0 +#define V_PCH_RCRB_DXXIR_IDR_PIRQB BIT12 +#define V_PCH_RCRB_DXXIR_IDR_PIRQC BIT13 +#define V_PCH_RCRB_DXXIR_IDR_PIRQD (BIT13 | BIT12) +#define V_PCH_RCRB_DXXIR_IDR_PIRQE BIT14 +#define V_PCH_RCRB_DXXIR_IDR_PIRQF (BIT14 | BIT12) +#define V_PCH_RCRB_DXXIR_IDR_PIRQG (BIT14 | BIT13) +#define V_PCH_RCRB_DXXIR_IDR_PIRQH (BIT14 | BIT13 | BIT12) +#define V_PCH_RCRB_DXXIR_ICR_PIRQA 0 +#define V_PCH_RCRB_DXXIR_ICR_PIRQB BIT8 +#define V_PCH_RCRB_DXXIR_ICR_PIRQC BIT9 +#define V_PCH_RCRB_DXXIR_ICR_PIRQD (BIT9 | BIT8) +#define V_PCH_RCRB_DXXIR_ICR_PIRQE BIT10 +#define V_PCH_RCRB_DXXIR_ICR_PIRQF (BIT10 | BIT8) +#define V_PCH_RCRB_DXXIR_ICR_PIRQG (BIT10 | BIT9) +#define V_PCH_RCRB_DXXIR_ICR_PIRQH (BIT10 | BIT9 | BIT8) +#define V_PCH_RCRB_DXXIR_IBR_PIRQA 0 +#define V_PCH_RCRB_DXXIR_IBR_PIRQB BIT4 +#define V_PCH_RCRB_DXXIR_IBR_PIRQC BIT5 +#define V_PCH_RCRB_DXXIR_IBR_PIRQD (BIT5 | BIT4) +#define V_PCH_RCRB_DXXIR_IBR_PIRQE BIT6 +#define V_PCH_RCRB_DXXIR_IBR_PIRQF (BIT6 | BIT4) +#define V_PCH_RCRB_DXXIR_IBR_PIRQG (BIT6 | BIT5) +#define V_PCH_RCRB_DXXIR_IBR_PIRQH (BIT6 | BIT5 | BIT4) +#define V_PCH_RCRB_DXXIR_IAR_PIRQA 0 +#define V_PCH_RCRB_DXXIR_IAR_PIRQB BIT0 +#define V_PCH_RCRB_DXXIR_IAR_PIRQC BIT1 +#define V_PCH_RCRB_DXXIR_IAR_PIRQD (BIT1 | BIT0) +#define V_PCH_RCRB_DXXIR_IAR_PIRQE BIT2 +#define V_PCH_RCRB_DXXIR_IAR_PIRQF (BIT2 | BIT0) +#define V_PCH_RCRB_DXXIR_IAR_PIRQG (BIT2 | BIT1) +#define V_PCH_RCRB_DXXIR_IAR_PIRQH (BIT2 | BIT1 | BIT0) +#define R_PCH_RCRB_OIC 0x31FE ///< Other Interrupt Control +#define B_PCH_RCRB_OIC_OA24_39_D BIT11 +#define B_PCH_RCRB_OIC_CEN BIT9 ///< Coprocessor Error Enable +#define B_PCH_RCRB_OIC_AEN BIT8 ///< APIC Enable +#define V_PCH_RCRB_OIC_ASEL 0xFF +#define R_PCH_IO_APIC_INDEX 0xFEC00000 +#define R_PCH_IO_APIC_DATA 0xFEC00010 +#define N_PCH_IO_APIC_ASEL 12 +#define R_PCH_RCRB_PRSTS 0x3310 +#define B_PCH_RCRB_PRSTS_PM_WD_TMR BIT15 ///< Power Management Watchdog Timer +#define B_PCH_RCRB_PRSTS_VE_WD_TMR_STS BIT7 ///< VE Watchdog Timer Status +#define B_PCH_RCRB_PRSTS_ME_WD_TMR_STS BIT6 ///< Management Engine Watchdog Timer Status +#define B_PCH_RCRB_PRSTS_WOL_OVR_WK_STS BIT5 +#define B_PCH_RCRB_PRSTS_FIELD_1 BIT4 +#define B_PCH_RCRB_PRSTS_ME_HOST_PWRDN BIT3 +#define B_PCH_RCRB_PRSTS_ME_HRST_WARM_STS BIT2 +#define B_PCH_RCRB_PRSTS_ME_HRST_COLD_STS BIT1 +#define B_PCH_RCRB_PRSTS_ME_WAKE_STS BIT0 +#define R_PCH_RCRB_CIR3314 0x3314 +#define R_PCH_RCRB_PM_CFG 0x3318 ///< Power Management Configuration +#define R_PCH_RCRB_PM_CFG_RTC_DS_WAKE_DIS BIT21 ///< RTC Wake from Deep S4/S5 Disable +#define B_PCH_RCRB_PM_CFG_SSMAW_MASK (BIT19 | BIT18) ///< SLP_SUS# Min Assertion Width +#define V_PCH_RCRB_PM_CFG_SSMAW_4S (BIT19 | BIT18) ///< 4 seconds +#define V_PCH_RCRB_PM_CFG_SSMAW_1S BIT19 ///< 1 second +#define V_PCH_RCRB_PM_CFG_SSMAW_0_5S BIT18 ///< 0.5 second (500ms) +#define V_PCH_RCRB_PM_CFG_SSMAW_0S 0 ///< 0 second +#define B_PCH_RCRB_PM_CFG_SAMAW_MASK (BIT17 | BIT16) ///< SLP_A# Min Assertion Width +#define V_PCH_RCRB_PM_CFG_SAMAW_2S (BIT17 | BIT16) ///< 2 seconds +#define V_PCH_RCRB_PM_CFG_SAMAW_98ms BIT17 ///< 98ms +#define V_PCH_RCRB_PM_CFG_SAMAW_4S BIT16 ///< 4 seconds +#define V_PCH_RCRB_PM_CFG_SAMAW_0S 0 ///< 0 second +#define B_PCH_RCRB_PM_CFG_RPCD_MASK (BIT9 | BIT8) ///< Reset Power Cycle Duration +#define V_PCH_RCRB_PM_CFG_RPCD_1S (BIT9 | BIT8) ///< 1-2 seconds +#define V_PCH_RCRB_PM_CFG_RPCD_2S BIT9 ///< 2-3 seconds +#define V_PCH_RCRB_PM_CFG_RPCD_3S BIT8 ///< 3-4 seconds +#define V_PCH_RCRB_PM_CFG_RPCD_4S 0 ///< 4-5 seconds (Default) +#define R_PCH_RCRB_CIR3324 0x3324 +#define R_PCH_RCRB_DEEP_S3_POL 0x3328 ///< Deep S3 Power Policies +#define B_PCH_RCRB_DEEP_S3_POL_DPS3_EN_DC BIT1 ///< Deep S3 Enable in DC Mode +#define B_PCH_RCRB_DEEP_S3_POL_DPS3_EN_AC BIT0 ///< Deep S3 Enable in AC Mode +#define R_PCH_RCRB_DEEP_S4_POL 0x332C ///< Deep S4 Power Policies +#define B_PCH_RCRB_DEEP_S4_POL_DPS4_EN_DC BIT1 ///< Deep S4 Enable in DC Mode +#define B_PCH_RCRB_DEEP_S4_POL_DPS4_EN_AC BIT0 ///< Deep S4 Enable in AC Mode +#define R_PCH_RCRB_DEEP_S5_POL 0x3330 ///< Deep S5 Power Policies +#define B_PCH_RCRB_DEEP_S5_POL_DPS5_EN_DC BIT15 ///< Deep S5 Enable in DC Mode +#define B_PCH_RCRB_DEEP_S5_POL_DPS5_EN_AC BIT14 ///< Deep S5 Enable in AC Mode +#define R_PCH_RCRB_PM_CFG2 0x333C ///< Power Management Configuration Reg 2 +#define B_PCH_RCRB_PM_CFG2_DRAM_RESET_CTL (1 << 26) ///< DRAM RESET# control +#define R_PCH_RCRB_CIR3340 0x3340 +#define R_PCH_RCRB_CIR3344 0x3344 +#define R_PCH_RCRB_CIR3348 0x3348 +#define R_PCH_RCRB_CIR3350 0x3350 +#define R_PCH_RCRB_CIR3360 0x3360 +#define R_PCH_RCRB_CIR3368 0x3368 +#define R_PCH_RCRB_CIR3378 0x3378 +#define R_PCH_RCRB_CIR337C 0x337C +#define R_PCH_RCRB_CIR3388 0x3388 +#define R_PCH_RCRB_CIR3390 0x3390 +#define R_PCH_RCRB_CIR33A0 0x33A0 +#define R_PCH_RCRB_CIR33B0 0x33B0 +#define R_PCH_RCRB_CIR33C0 0x33C0 +#define PMSYNC_TPR_CONFIG 0x33C4 +#define B_PMSYNC_TPR_CONFIG_LOCK BIT31 +#define PMSYNC_TPR_CONFIG2 0x33CC +#define R_PCH_RCRB_PMSYNC 0x33C8 +#define B_PCH_RCRB_PMSYNC_GPIO_D_SEL BIT11 +#define B_PCH_RCRB_PMSYNC_GPIO_C_SEL BIT10 +#define B_PCH_RCRB_PMSYNC_GPIO_B_SEL BIT9 +#define B_PCH_RCRB_PMSYNC_GPIO_A_SEL BIT8 +#define R_PCH_RCRB_CIR33D0 0x33D0 +#define R_PCH_RCRB_CIR33D4 0x33D4 +#define R_PCH_RCRB_RTC_CONF 0x3400 ///< RTC Configuration register +#define S_PCH_RCRB_RTC_CONF 4 +#define B_PCH_RCRB_RTC_CONF_UCMOS_LOCK BIT4 +#define B_PCH_RCRB_RTC_CONF_LCMOS_LOCK BIT3 +#define B_PCH_RCRB_RTC_CONF_UCMOS_EN BIT2 ///< Upper CMOS bank enable +#define R_PCH_RCRB_HPTC 0x3404 ///< High Performance Timer Configuration +#define B_PCH_RCRB_HPTC_AE BIT7 ///< Address enable +#define B_PCH_RCRB_HPTC_AS (BIT1 | BIT0) ///< Address selection +#define R_PCH_PCH_HPET_CONFIG 0xFED00000 +#define N_PCH_HPET_ADDR_ASEL 12 +#define R_PCH_RCRB_GCS 0x3410 ///< General Control and Status +#define B_PCH_RCRB_GCS_FLRCSSEL BIT12 +#define B_PCH_H_RCRB_GCS_BBS (BIT11 | BIT10) ///< Boot BIOS straps for Pch-H +#define V_PCH_H_RCRB_GCS_BBS_SPI (3 << 10) ///< Boot BIOS strapped to SPI for Pch-H +#define V_PCH_H_RCRB_GCS_BBS_LPC (0 << 10) ///< Boot BIOS strapped to LPC for Pch-H +#define B_PCH_LP_RCRB_GCS_BBS BIT10 ///< Boot BIOS straps for Pch-Lp +#define V_PCH_LP_RCRB_GCS_BBS_SPI 0 ///< Boot BIOS strapped to SPI for Pch-Lp +#define V_PCH_LP_RCRB_GCS_BBS_LPC BIT10 ///< Boot BIOS strapped to LPC for Pch-Lp +#define B_PCH_RCRB_GCS_SERM BIT9 ///< Server Error Reporting Mode +#define B_PCH_RCRB_GCS_NR BIT5 ///< No Reboot strap +#define B_PCH_RCRB_GCS_AME BIT4 ///< Alternate Access Mode Enable +#define B_PCH_RCRB_GCS_SPS BIT3 ///< Shutdown Policy Select +#define B_PCH_RCRB_GCS_RPR BIT2 ///< Reserved Page Route +#define B_PCH_RCRB_GCS_BILD BIT0 ///< BIOS Interface Lock-Down +#define R_PCH_RCRB_BUC 0x3414 ///< Backed Up Control +#define B_PCH_RCRB_BUC_LAN_DIS BIT5 ///< LAN Disable +#define B_PCH_RCRB_BUC_SDO BIT4 ///< Daylight Savings Override +#define B_PCH_RCRB_BUC_TS BIT0 ///< Top Swap +#define R_PCH_RCRB_FUNC_DIS 0x3418 ///< Function Disable Register +#define B_PCH_RCRB_FUNC_DIS_XHCI BIT27 ///< XHCI controller disable +#define B_PCH_RCRB_FUNC_DIS_SATA2 BIT25 ///< Serial ATA 2 disable +#define B_PCH_RCRB_FUNC_DIS_THERMAL BIT24 ///< Thermal Throttle Disable +#define B_PCH_RCRB_FUNC_DIS_PCI_EX_PORT8 BIT23 ///< PCI Express port 8 disable +#define B_PCH_RCRB_FUNC_DIS_PCI_EX_PORT7 BIT22 ///< PCI Express port 7 disable +#define B_PCH_RCRB_FUNC_DIS_PCI_EX_PORT6 BIT21 ///< PCI Express port 6 disable +#define B_PCH_RCRB_FUNC_DIS_PCI_EX_PORT5 BIT20 ///< PCI Express port 5 disable +#define B_PCH_RCRB_FUNC_DIS_PCI_EX_PORT4 BIT19 ///< PCI Express port 4 disable +#define B_PCH_RCRB_FUNC_DIS_PCI_EX_PORT3 BIT18 ///< PCI Express port 3 disable +#define B_PCH_RCRB_FUNC_DIS_PCI_EX_PORT2 BIT17 ///< PCI Express port 2 disable +#define B_PCH_RCRB_FUNC_DIS_PCI_EX_PORT1 BIT16 ///< PCI Express port 1 disable +#define N_PCH_RCRB_FUNC_DIS_PCI_EX_PORT1 16 +#define B_PCH_RCRB_FUNC_DIS_EHCI1 BIT15 ///< EHCI controller 1 disable +#define B_PCH_RCRB_FUNC_DIS_LPC_BRIDGE BIT14 ///< LPC Bridge disable +#define B_PCH_RCRB_FUNC_DIS_EHCI2 BIT13 ///< EHCI controller 2 disable +#define B_PCH_RCRB_FUNC_DIS_AZALIA BIT4 ///< Azalia disable +#define B_PCH_RCRB_FUNC_DIS_SMBUS BIT3 ///< SMBUS disable +#define B_PCH_RCRB_FUNC_DIS_SATA1 BIT2 ///< Serial ATA disable +#define B_PCH_RCRB_FUNC_DIS_ADSP BIT1 ///< Audio DSP disable +#define B_PCH_RCRB_FUNC_DIS_FUNCTION_0 BIT0 ///< Function 0 disable +#define R_PCH_RCRB_CG 0x341C ///< Clock Gating +#define B_PCH_RCRB_CG_EN_DCG_BLA BIT30 ///< Platform Essential Cluster BLA unit Dynamic Clock Gate Enable +#define B_PCH_RCRB_CG_EN_SCG_GSX BIT29 ///< GSX Static Clock Gate Enable +#define B_PCH_RCRB_CG_EN_DCG_GPIO BIT28 ///< GPIO Dynamic Clock Gate Enable +#define B_PCH_RCRB_CG_EN_DCG_HPET BIT27 ///< HPET Dynamic Clock Gate Enable +#define B_PCH_RCRB_CG_EN_CG_GPEC BIT26 ///< Generic Platform Essential Clock Gate Enable +#define B_PCH_RCRB_CG_EN_SCG_8254 BIT25 ///< 8254 Static Clock Gate Enable +#define B_PCH_RCRB_CG_EN_SCG_8237 BIT24 ///< 8237 Static Clock Gate Enable + +#define B_PCH_RCRB_CG_EN_DCG_LPC BIT31 ///< Legacy(LPC) Dynamic Clock Gate Enable +#define B_PCH_RCRB_CG_EN_SCG_LAN BIT23 ///< LAN Static Clock Gate Enable +#define B_PCH_RCRB_CG_EN_DCG_HDA BIT22 ///< HDA Dynamic Clock Gate Enable +#define B_PCH_RCRB_CG_EN_SCG_HDA BIT21 ///< HDA Static Clock Gate Enable +#define B_PCH_RCRB_CG_EN_DCG_PCI BIT16 ///< PCI Dynamic Clock Gate Enable +#define B_PCH_RCRB_CG_EN_CG_SMBUS BIT5 ///< SMBUS Static Clock Gating Enable +#define R_PCH_RCRB_FDSW 0x3420 ///< Function Disable SUS well +#define B_PCH_RCRB_FDSW_FDSWL BIT7 ///< Function Disable SUS well lockdown +#define R_PCH_RCRB_DISPBDF 0x3424 ///< Display Bus, Device and Function Initialization +#define B_PCH_RCRB_DISPBDF_DBN 0xFF00 ///< Display Bus Number +#define B_PCH_RCRB_DISPBDF_DDN 0x00F8 ///< Display Device Number +#define B_PCH_RCRB_DISPBDF_DFN 0x0007 ///< Display Function Number +#define R_PCH_RCRB_FD2 0x3428 ///< Function Disable 2 +#define B_PCH_RCRB_FD2_KTD BIT4 ///< KT Disable +#define B_PCH_RCRB_FD2_IRERD BIT3 ///< IDE-R Disable +#define B_PCH_RCRB_FD2_MEI2D BIT2 ///< Intel MEI #2 Disable +#define B_PCH_RCRB_FD2_MEI1D BIT1 ///< Intel MEI #1 Disable +#define B_PCH_RCRB_FD2_DBDFEN BIT0 ///< Display BDF Enable +#define R_PCH_RCRB_CIR3A28 0x3A28 +#define R_PCH_RCRB_CIR3A2C 0x3A2C +#define R_PCH_RCRB_CIR3A6C 0x3A6C +#define R_PCH_RCRB_CIR3A80 0x3A80 +#define R_PCH_RCRB_CIR3A84 0x3A84 +#define R_PCH_RCRB_CIR3A88 0x3A88 +#define R_PCH_RCRB_GSX_CTRL 0x3454 ///< GSX Control +#define B_PCH_RCRB_GSX_BAR_ENABLE BIT4 ///< GSX BAR Enable +#define R_PCH_RCRB_INT_ACPIIRQEN 0x31E0 ///< ACPI IRQ Control + +#define B_PCH_RCRB_INT_ACPIIRQEN_A15E BIT15 ///< ACPI IRQ15 Enable +#define B_PCH_RCRB_INT_ACPIIRQEN_A14E BIT14 ///< ACPI IRQ14 Enable +#define B_PCH_RCRB_INT_ACPIIRQEN_A13E BIT13 ///< ACPI IRQ13 Enable +#define B_PCH_RCRB_INT_ACPIIRQEN_A7E BIT7 ///< ACPI IRQ7 Enable +#define B_PCH_RCRB_INT_ACPIIRQEN_A6E BIT6 ///< ACPI IRQ6 Enable +#define B_PCH_RCRB_INT_ACPIIRQEN_A5E BIT5 ///< ACPI IRQ5 Enable +#define B_PCH_RCRB_INT_ACPIIRQEN_A4E BIT4 ///< ACPI IRQ4 Enable +#define B_PCH_RCRB_INT_ACPIIRQEN_A3E BIT3 ///< ACPI IRQ3 Enable +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsSata.h b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsSata.h new file mode 100644 index 0000000..add2c1e --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsSata.h @@ -0,0 +1,703 @@ +/** @file + Register names for PCH SATA controllers + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_LPT_" + - Registers / bits that are different between SKUs are denoted by "_<SKU_name>" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without <generation_name> inserted. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _PCH_REGS_SATA_H_ +#define _PCH_REGS_SATA_H_ + +// +// SATA Controller 1 Registers (D31:F2) +// +#define PCI_DEVICE_NUMBER_PCH_SATA 31 +#define PCI_FUNCTION_NUMBER_PCH_SATA 2 +#define R_PCH_SATA_VENDOR_ID 0x00 +#define V_PCH_SATA_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_SATA_DEVICE_ID 0x02 +#define V_PCH_LPTH_SATA_DEVICE_ID_D_IDE 0x8C00 ///< Desktop IDE Mode (Ports 0,1, 2 and 3) +#define V_PCH_LPTH_SATA_DEVICE_ID_D_AHCI 0x8C02 ///< Desktop AHCI Mode (Ports 0-5) +#define V_PCH_LPTH_SATA_DEVICE_ID_D_RAID 0x8C04 ///< Desktop RAID 0/1/5/10 Mode, based on D31:F2:9Ch[7] +#define V_PCH_LPTH_SATA_DEVICE_ID_D_RAID_PREM 0x8C06 ///< Desktop RAID 0/1/5/10 Mode, based on D31:F2:9Ch[7] +#define V_PCH_LPTH_SATA_DEVICE_ID_D_RAID_ALTDIS 0x2822 ///< Desktop RAID 0/1/5/10 Mode, based on D31:F2:9Ch[9][7] +#define V_PCH_LPTH_SATA_DEVICE_ID_D_RAID_SERVER 0x2826 ///< Server RAID 0/1/5/10 Mode, based on D31:F2:9Ch[9][7] +#define V_PCH_LPTH_SATA2_DEVICE_ID_D_IDE 0x8C08 ///< Controller 2, Desktop IDE Mode, 2 ports +#define V_PCH_LPTH_SATA_DEVICE_ID_M_IDE 0x8C01 ///< Mobile IDE Mode, port 0, 1, 4, 5 +#define V_PCH_LPTH_SATA_DEVICE_ID_M_AHCI 0x8C03 ///< Mobile AHCI Mode, port 0, 1, 4 5 +#define V_PCH_LPTH_SATA_DEVICE_ID_M_RAID 0x8C05 ///< Mobile RAID 0/1/5/10 Mode, based on D31:F2:9Ch[7] +#define V_PCH_LPTH_SATA_DEVICE_ID_M_RAID_PREM 0x8C07 ///< Mobile RAID 0/1/5/10 Mode, based on D31:F2:9Ch[7] +#define V_PCH_LPTH_SATA_DEVICE_ID_M_RAID_ALTDIS 0x282A ///< Mobile RAID 0/1/5/10 Mode, based on D31:F2:9Ch[7] +#define V_PCH_LPTH_SATA2_DEVICE_ID_M_IDE 0x8C09 ///< Controller 2, Mobile IDE, 2 ports +#define V_PCH_LPTH_SATA_DEVICE_ID_D_RAID1 0x8C0E ///< SATA Controller 1 (RAID 1/RRT Only) +#define V_PCH_LPTH_SATA_DEVICE_ID_M_RAID1 0x8C0F ///< SATA Controller 1 (RAID 1/RRT Only) - Mobile + +// +// SATA Controller 2 Registers (D31:F5) +// +#define PCI_DEVICE_NUMBER_PCH_SATA2 31 +#define PCI_FUNCTION_NUMBER_PCH_SATA2 5 +#define R_PCH_SATA2_VENDOR_ID 0x00 +#define V_PCH_SATA2_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_SATA2_DEVICE_ID 0x02 + +#define V_PCH_LPTLP_SATA_DEVICE_ID_M_TEST0 0x9C00 ///< SATA Controller 1 (TEST Mode only) +#define V_PCH_LPTLP_SATA_DEVICE_ID_M_TEST1 0x9C01 ///< SATA Controller 1 (TEST Mode only) - Mobile +#define V_PCH_LPTLP_SATA_DEVICE_ID_M_AHCI0 0x9C02 ///< SATA Controller 1 (AHCI) +#define V_PCH_LPTLP_SATA_DEVICE_ID_M_AHCI1 0x9C03 ///< SATA Controller 1 (AHCI) - Mobile +#define V_PCH_LPTLP_SATA_DEVICE_ID_M_RAID0 0x9C04 ///< SATA Controller 1 (RAID 0/1/5/10) - NOT premium +#define V_PCH_LPTLP_SATA_DEVICE_ID_M_RAID_ALTDIS0 0x2822 ///< SATA Controller 1 (RAID 0/1/5/10) - NOT premium - Alternate ID +#define V_PCH_LPTLP_SATA_DEVICE_ID_M_RAID1 0x9C05 ///< SATA Controller 1 (RAID 0/1/5/10) - NOT premium - Mobile +#define V_PCH_LPTLP_SATA_DEVICE_ID_M_RAID_ALTDIS1 0x282A ///< SATA Controller 1 (RAID 0/1/5/10) - NOT premium - Mobile - Alternate ID +#define V_PCH_LPTLP_SATA_DEVICE_ID_M_RAID_PREM0 0x9C06 ///< SATA Controller 1 (RAID 0/1/5/10) - premium +#define V_PCH_LPTLP_SATA_DEVICE_ID_M_RAID_PREM1 0x9C07 ///< SATA Controller 1 (RAID 0/1/5/10) - premium - Mobile +#define V_PCH_LPTLP_SATA_DEVICE_ID_M_RAID2 0x9C0E ///< SATA Controller 1 (RAID 1/RRT Only) +#define V_PCH_LPTLP_SATA_DEVICE_ID_M_RAID3 0x9C0F ///< SATA Controller 1 (RAID 1/RRT Only) - Mobile + +// +// SATA Controller common Registers +// +#define R_PCH_SATA_COMMAND 0x04 +#define B_PCH_SATA_COMMAND_INT_DIS BIT10 +#define B_PCH_SATA_COMMAND_FBE BIT9 +#define B_PCH_SATA_COMMAND_SERR_EN BIT8 +#define B_PCH_SATA_COMMAND_WCC BIT7 +#define B_PCH_SATA_COMMAND_PER BIT6 +#define B_PCH_SATA_COMMAND_VPS BIT5 +#define B_PCH_SATA_COMMAND_PMWE BIT4 +#define B_PCH_SATA_COMMAND_SCE BIT3 +#define B_PCH_SATA_COMMAND_BME BIT2 +#define B_PCH_SATA_COMMAND_MSE BIT1 +#define B_PCH_SATA_COMMAND_IOSE BIT0 +#define R_PCH_SATA_PCISTS 0x06 +#define B_PCH_SATA_PCISTS_DPE BIT15 +#define B_PCH_SATA_PCISTS_RMA BIT13 +#define B_PCH_SATA_PCISTS_DEV_STS_MASK (BIT10 | BIT9) +#define B_PCH_SATA_PCISTS_DPED BIT8 +#define B_PCH_SATA_PCISTS_CAP_LIST BIT4 +#define B_PCH_SATA_PCISTS_ITNS BIT3 +#define R_PCH_SATA_RID 0x08 +#define R_PCH_SATA_PI_REGISTER 0x09 +#define B_PCH_SATA_PI_REGISTER_SNC BIT3 +#define B_PCH_SATA_PI_REGISTER_SNE BIT2 +#define B_PCH_SATA_PI_REGISTER_PNC BIT1 +#define B_PCH_SATA_PI_REGISTER_PNE BIT0 +#define R_PCH_SATA_SUB_CLASS_CODE 0x0A +#define V_PCH_SATA_SUB_CLASS_CODE_IDE 0x01 +#define V_PCH_SATA_SUB_CLASS_CODE_AHCI 0x06 +#define V_PCH_SATA_SUB_CLASS_CODE_RAID 0x04 +#define R_PCH_SATA_BCC 0x0B +#define B_PCH_SATA_BCC 0xFF +#define R_PCH_SATA_PMLT 0x0D +#define B_PCH_SATA_PMLT 0xFF +#define R_PCH_SATA_HTYPE 0x0E +#define B_PCH_SATA_HTYPE_MFD BIT7 +#define B_PCH_SATA_HTYPE_HL 0x7F +#define R_PCH_SATA_PCMD_BAR 0x10 +#define B_PCH_SATA_PCMD_BAR_BA 0x0000FFF8 +#define B_PCH_SATA_PCMD_BAR_RTE BIT0 +#define R_PCH_SATA_PCNL_BAR 0x14 +#define B_PCH_SATA_PCNL_BAR_BA 0x0000FFFC +#define B_PCH_SATA_PCNL_BAR_RTE BIT0 +#define R_PCH_SATA_SCMD_BAR 0x18 +#define B_PCH_SATA_SCMD_BAR_BA 0x0000FFF8 +#define B_PCH_SATA_SCMD_BAR_RTE BIT0 +#define R_PCH_SATA_SCNL_BAR 0x1C +#define B_PCH_SATA_SCNL_BAR_BA 0x0000FFFC +#define B_PCH_SATA_SCNL_BAR_RTE BIT0 +#define R_PCH_SATA_BUS_MASTER_BAR 0x20 +#define B_PCH_SATA_BUS_MASTER_BAR_BA 0x0000FFE0 +#define B_PCH_SATA_BUS_MASTER_BAR_BA4 BIT4 +#define B_PCH_SATA_BUS_MASTER_BAR_RTE BIT0 +#define R_PCH_SATA_SIDP_BAR 0x24 +#define R_PCH_SATA_AHCI_BAR 0x24 +#define B_PCH_SATA_AHCI_BAR_BA 0xFFFFF800 +#define V_PCH_SATA_AHCI_BAR_LENGTH 0x800 +#define N_PCH_SATA_AHCI_BAR_ALIGNMENT 11 +#define B_PCH_SATA_AHCI_BAR_PF BIT3 +#define B_PCH_SATA_AHCI_BAR_TP (BIT2 | BIT1) +#define B_PCH_SATA_AHCI_BAR_RTE BIT0 +#define R_PCH_SATA_AHCI_SVID 0x2C +#define B_PCH_SATA_AHCI_SVID 0xFFFF +#define R_PCH_SATA_AHCI_SID 0x2E +#define B_PCH_SATA_AHCI_SID 0xFFFF +#define R_PCH_SATA_AHCI_CAP_PTR 0x34 +#define B_PCH_SATA_AHCI_CAP_PTR 0xFF +#define R_PCH_SATA_AHCI_INTLN 0x3C +#define B_PCH_SATA_AHCI_INTLN 0xFF +#define R_PCH_SATA_AHCI_INTPN 0x3D +#define B_PCH_SATA_AHCI_INTPN 0xFF +#define R_PCH_SATA_TIMP 0x40 +#define R_PCH_SATA_TIMS 0x42 +#define B_PCH_SATA_TIM_IDE BIT15 ///< IDE Decode Enable +#define R_PCH_SATA_PID 0x70 +#define B_PCH_SATA_PID_NEXT 0xFF00 +#define V_PCH_SATA_PID_NEXT_0 0xB000 +#define V_PCH_SATA_PID_NEXT_1 0xA800 +#define B_PCH_SATA_PID_CID 0x00FF +#define R_PCH_SATA_PC 0x72 +#define S_PCH_SATA_PC 2 +#define B_PCH_SATA_PC_PME (BIT15 | BIT14 | BIT13 | BIT12 | BIT11) +#define V_PCH_SATA_PC_PME_0 0x0000 +#define V_PCH_SATA_PC_PME_1 0x4000 +#define B_PCH_SATA_PC_D2_SUP BIT10 +#define B_PCH_SATA_PC_D1_SUP BIT9 +#define B_PCH_SATA_PC_AUX_CUR (BIT8 | BIT7 | BIT6) +#define B_PCH_SATA_PC_DSI BIT5 +#define B_PCH_SATA_PC_PME_CLK BIT3 +#define B_PCH_SATA_PC_VER (BIT2 | BIT1 | BIT0) +#define R_PCH_SATA_PMCS 0x74 +#define B_PCH_SATA_PMCS_PMES BIT15 +#define B_PCH_SATA_PMCS_PMEE BIT8 +#define B_PCH_SATA_PMCS_NSFRST BIT3 +#define V_PCH_SATA_PMCS_NSFRST_1 0x01 +#define V_PCH_SATA_PMCS_NSFRST_0 0x00 +#define B_PCH_SATA_PMCS_PS (BIT1 | BIT0) +#define V_PCH_SATA_PMCS_PS_3 0x03 +#define V_PCH_SATA_PMCS_PS_0 0x00 +#define R_PCH_SATA_MID 0x80 +#define B_PCH_SATA_MID_NEXT 0xFF00 +#define B_PCH_SATA_MID_CID 0x00FF +#define R_PCH_SATA_MC 0x82 +#define B_PCH_SATA_MC_C64 BIT7 +#define B_PCH_SATA_MC_MME (BIT6 | BIT5 | BIT4) +#define V_PCH_SATA_MC_MME_4 0x04 +#define V_PCH_SATA_MC_MME_2 0x02 +#define V_PCH_SATA_MC_MME_1 0x01 +#define V_PCH_SATA_MC_MME_0 0x00 +#define B_PCH_SATA_MC_MMC (BIT3 | BIT2 | BIT1) +#define V_PCH_SATA_MC_MMC_4 0x04 +#define V_PCH_SATA_MC_MMC_0 0x00 +#define B_PCH_SATA_MC_MSIE BIT0 +#define V_PCH_SATA_MC_MSIE_1 0x01 +#define V_PCH_SATA_MC_MSIE_0 0x00 +#define R_PCH_SATA_MA 0x84 +#define B_PCH_SATA_MA 0xFFFFFFFC +#define R_PCH_SATA_MD 0x88 +#define B_PCH_SATA_MD_MSIMD 0xFFFF +#define R_PCH_SATA_MAP 0x90 +#define B_PCH_H_SATA_MAP_SPD (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) +#define B_PCH_LP_SATA_MAP_SPD (BIT11 | BIT10 | BIT9 | BIT8) +#define B_PCH_SATA_PORT5_DISABLED BIT13 +#define B_PCH_SATA_PORT4_DISABLED BIT12 +#define B_PCH_SATA_PORT3_DISABLED BIT11 +#define B_PCH_SATA_PORT2_DISABLED BIT10 +#define B_PCH_SATA_PORT1_DISABLED BIT9 +#define B_PCH_SATA_PORT0_DISABLED BIT8 +#define B_PCH_SATA2_MAP_SPD (BIT9 | BIT8) +#define B_PCH_SATA2_PORT5_DISABLED BIT9 +#define B_PCH_SATA2_PORT4_DISABLED BIT8 +#define B_PCH_SATA_MAP_SMS_MASK (BIT7 | BIT6) +#define V_PCH_SATA_MAP_SMS_LOOBACK_TESTMODE 0x00 +#define V_PCH_SATA_MAP_SMS_IDE 0x00 +#define V_PCH_SATA_MAP_SMS_AHCI 0x40 +#define V_PCH_SATA_MAP_SMS_RAID 0x80 +#define B_PCH_SATA_PORT_TO_CONTROLLER_CFG BIT5 +#define R_PCH_SATA_PCS 0x92 +#define S_PCH_SATA_PCS 0x2 +#define B_PCH_SATA_PCS_OOB_RETRY BIT15 +#define B_PCH_SATA_PCS_PORT5_DET BIT13 +#define B_PCH_SATA_PCS_PORT4_DET BIT12 +#define B_PCH_SATA_PCS_PORT3_DET BIT11 +#define B_PCH_SATA_PCS_PORT2_DET BIT10 +#define B_PCH_SATA_PCS_PORT1_DET BIT9 +#define B_PCH_SATA_PCS_PORT0_DET BIT8 +#define B_PCH_SATA_PCS_PORT5_EN BIT5 +#define B_PCH_SATA_PCS_PORT4_EN BIT4 +#define B_PCH_SATA_PCS_PORT3_EN BIT3 +#define B_PCH_SATA_PCS_PORT2_EN BIT2 +#define B_PCH_SATA_PCS_PORT1_EN BIT1 +#define B_PCH_SATA_PCS_PORT0_EN BIT0 +#define B_PCH_SATA2_PCS_PORT5_DET BIT9 +#define B_PCH_SATA2_PCS_PORT4_DET BIT8 +#define B_PCH_SATA2_PCS_PORT5_EN BIT1 +#define B_PCH_SATA2_PCS_PORT4_EN BIT0 +#define R_PCH_SATA_SCLKCG 0x94 +#define B_PCH_SATA_SCLKCG_PORT5_PCD BIT29 +#define B_PCH_SATA_SCLKCG_PORT4_PCD BIT28 +#define B_PCH_SATA_SCLKCG_PORT3_PCD BIT27 +#define B_PCH_SATA_SCLKCG_PORT2_PCD BIT26 +#define B_PCH_SATA_SCLKCG_PORT1_PCD BIT25 +#define B_PCH_SATA_SCLKCG_PORT0_PCD BIT24 +#define B_PCH_SATA_SCLKCG_POP3_DEVSLP BIT15 +#define R_PCH_SATA_SCLKGC 0x9C +#define B_PCH_SATA_SCLKGC_AIE BIT7 +#define B_PCH_SATA_SCLKGC_AIES BIT6 +#define B_PCH_SATA_SCLKGC_SATATM_MASK 0x7C +#define B_PCH_SATA_SCLKGC_SATATM_EN (BIT3 | BIT2) +#define B_PCH_SATA_SCLKGC_SATA4PMIND BIT0 +#define R_PCH_SATA_SIRI 0xA0 +#define B_PCH_SATA_SIRI_IDX 0xFC +#define R_PCH_SATA_STRD 0xA4 +#define B_PCH_SATA_STRD_DTA 0xFFFFFFFF +#define R_PCH_SATA_CR0 0xA8 +#define B_PCH_SATA_CR0_MAJREV 0x00F00000 +#define B_PCH_SATA_CR0_MINREV 0x000F0000 +#define B_PCH_SATA_CR0_NEXT 0x0000FF00 +#define B_PCH_SATA_CR0_CAP 0x000000FF +#define R_PCH_SATA_CR1 0xAC +#define B_PCH_SATA_CR1_BAROFST 0xFFF0 +#define B_PCH_SATA_CR1_BARLOC 0x000F +#define R_PCH_SATA_FLR_CID 0xB0 +#define B_PCH_SATA_FLR_CID_NEXT 0xFF00 +#define B_PCH_SATA_FLR_CID 0x00FF +#define V_PCH_SATA_FLR_CID_1 0x0009 +#define V_PCH_SATA_FLR_CID_0 0x0013 +#define R_PCH_SATA_FLR_CLV 0xB2 +#define B_PCH_SATA_FLR_CLV_FLRC_FLRCSSEL_0 BIT9 +#define B_PCH_SATA_FLR_CLV_TXPC_FLRCSSEL_0 BIT8 +#define B_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL_0 0x00FF +#define B_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL_1 0x00FF +#define V_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL 0x0006 +#define R_PCH_SATA_FLRC 0xB4 +#define B_PCH_SATA_FLRC_TXP BIT8 +#define B_PCH_SATA_FLRC_INITFLR BIT0 +#define R_PCH_SATA_ATC 0xC0 +#define B_PCH_SATA_ATC_SST BIT3 +#define B_PCH_SATA_ATC_SPT BIT2 +#define B_PCH_SATA_ATC_PST BIT1 +#define B_PCH_SATA_ATC_PMT BIT0 +#define R_PCH_SATA_ATS 0xC4 +#define B_PCH_SATA_ATS_SST BIT3 +#define B_PCH_SATA_ATS_SPT BIT2 +#define B_PCH_SATA_ATS_PST BIT1 +#define B_PCH_SATA_ATS_PMT BIT0 +#define R_PCH_SATA_SP 0xD0 +#define B_PCH_SATA_SP 0xFFFFFFFF +#define R_PCH_SATA_BFCS 0xE0 +#define B_PCH_SATA_BFCS_P5BFI BIT15 +#define B_PCH_SATA_BFCS_P4BFI BIT14 +#define B_PCH_SATA_BFCS_P3BFI BIT13 +#define B_PCH_SATA_BFCS_P2BFI BIT12 +#define B_PCH_SATA_BFCS_P2BFS BIT11 +#define B_PCH_SATA_BFCS_P2BFF BIT10 +#define B_PCH_SATA_BFCS_P1BFI BIT9 +#define B_PCH_SATA_BFCS_P0BFI BIT8 +#define B_PCH_SATA_BFCS_BIST_FIS_T BIT7 +#define B_PCH_SATA_BFCS_BIST_FIS_A BIT6 +#define B_PCH_SATA_BFCS_BIST_FIS_S BIT5 +#define B_PCH_SATA_BFCS_BIST_FIS_L BIT4 +#define B_PCH_SATA_BFCS_BIST_FIS_F BIT3 +#define B_PCH_SATA_BFCS_BIST_FIS_P BIT2 +#define R_PCH_SATA_BFTD1 0xE4 +#define B_PCH_SATA_BFTD1 0xFFFFFFFF +#define R_PCH_SATA_BFTD2 0xE8 +#define B_PCH_SATA_BFTD2 0xFFFFFFFF + +// +// Serial ATA Index/Data Pair Superset Registers +// +#define R_PCH_SATA_SIDPBA_SINDX 0x00 +#define R_PCH_SATA_SIDPBA_SDATA 0x04 +#define V_PCH_SATA_AHCI_SINDX_RIDX_SCTL 0x01 +#define V_PCH_SATA_AHCI_SINDX_PIDX_PORT0 0x0000 +#define V_PCH_SATA_AHCI_SINDX_PIDX_PORT1 0x0200 +#define V_PCH_SATA_AHCI_SINDX_PIDX_PORT2 0x0100 +#define V_PCH_SATA_AHCI_SINDX_PIDX_PORT3 0x0300 +#define V_PCH_SATA_SIDPBA_SDATA_GEN1 0x10 +#define V_PCH_SATA_SIDPBA_SDATA_GEN2 0x20 +#define V_PCH_SATA_SIDPBA_SDATA_GEN3 0x30 +#define B_PCH_SATA_SIDPBA_SCTL_DET (BIT3|BIT2|BIT1|BIT0) +#define V_PCH_SATA_SIDPBA_SCTL_DET_COMRST 0x01 +#define V_PCH_SATA_SIDPBA_SCTL_DET_NOINT 0x00 +#define V_PCH_SATA_SIDP_BAR_LENGTH 0x10 +#define N_PCH_SATA_SIDP_BAR_ALIGNMENT 0x04 + +// +// AHCI BAR Area related Registers +// +#define R_PCH_SATA_AHCI_CAP 0x0 +#define B_PCH_SATA_AHCI_CAP_S64A BIT31 +#define B_PCH_SATA_AHCI_CAP_SCQA BIT30 +#define B_PCH_SATA_AHCI_CAP_SSNTF BIT29 +#define B_PCH_SATA_AHCI_CAP_SIS BIT28 ///< Supports Interlock Switch +#define B_PCH_SATA_AHCI_CAP_SSS BIT27 ///< Supports Stagger Spin-up +#define B_PCH_SATA_AHCI_CAP_SALP BIT26 +#define B_PCH_SATA_AHCI_CAP_SAL BIT25 +#define B_PCH_SATA_AHCI_CAP_SCLO BIT24 ///< Supports Command List Override +#define B_PCH_SATA_AHCI_CAP_ISS_MASK (BIT23 | BIT22 | BIT21 | BIT20) +#define N_PCH_SATA_AHCI_CAP_ISS 20 ///< Interface Speed Support +#define V_PCH_SATA_AHCI_CAP_ISS_1_5_G 0x01 +#define V_PCH_SATA_AHCI_CAP_ISS_3_0_G 0x02 +#define V_PCH_SATA_AHCI_CAP_ISS_6_0_G 0x03 +#define B_PCH_SATA_AHCI_CAP_SNZO BIT19 +#define B_PCH_SATA_AHCI_CAP_SAM BIT18 +#define B_PCH_SATA_AHCI_CAP_PMS BIT17 ///< Supports Port Multiplier +#define B_PCH_SATA_AHCI_CAP_PMD BIT15 ///< PIO Multiple DRQ Block +#define B_PCH_SATA_AHCI_CAP_SSC BIT14 +#define B_PCH_SATA_AHCI_CAP_PSC BIT13 +#define B_PCH_SATA_AHCI_CAP_NCS 0x1F00 +#define B_PCH_SATA_AHCI_CAP_CCCS BIT7 +#define B_PCH_SATA_AHCI_CAP_EMS BIT6 +#define B_PCH_SATA_AHCI_CAP_SXS BIT5 ///< External SATA is supported +#define B_PCH_SATA_AHCI_CAP_NPS 0x001F + +#define R_PCH_SATA_AHCI_GHC 0x04 +#define B_PCH_SATA_AHCI_GHC_AE BIT31 +#define B_PCH_SATA_AHCI_GHC_MRSM BIT2 +#define B_PCH_SATA_AHCI_GHC_IE BIT1 +#define B_PCH_SATA_AHCI_GHC_HR BIT0 + +#define R_PCH_SATA_AHCI_IS 0x08 +#define B_PCH_SATA_AHCI_IS_PORT5 BIT5 +#define B_PCH_SATA_AHCI_IS_PORT4 BIT4 +#define B_PCH_SATA_AHCI_IS_PORT3 BIT3 +#define B_PCH_SATA_AHCI_IS_PORT2 BIT2 +#define B_PCH_SATA_AHCI_IS_PORT1 BIT1 +#define B_PCH_SATA_AHCI_IS_PORT0 BIT0 +#define R_PCH_SATA_AHCI_PI 0x0C +#define B_PCH_H_SATA_PORT_MASK 0x3F +#define B_PCH_LP_SATA_PORT_MASK 0x0F +#define B_PCH_SATA_PORT5_IMPLEMENTED BIT5 +#define B_PCH_SATA_PORT4_IMPLEMENTED BIT4 +#define B_PCH_SATA_PORT3_IMPLEMENTED BIT3 +#define B_PCH_SATA_PORT2_IMPLEMENTED BIT2 +#define B_PCH_SATA_PORT1_IMPLEMENTED BIT1 +#define B_PCH_SATA_PORT0_IMPLEMENTED BIT0 +#define R_PCH_SATA_AHCI_VS 0x10 +#define B_PCH_SATA_AHCI_VS_MJR 0xFFFF0000 +#define B_PCH_SATA_AHCI_VS_MNR 0x0000FFFF +#define R_PCH_SATA_AHCI_EM_LOC 0x1C +#define B_PCH_SATA_AHCI_EM_LOC_OFST 0xFFFF0000 +#define B_PCH_SATA_AHCI_EM_LOC_SZ 0x0000FFFF +#define R_PCH_SATA_AHCI_EM_CTRL 0x20 +#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_ALHD BIT26 +#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_XMT BIT25 +#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_SMB BIT24 +#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SGPIO BIT19 +#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SES2 BIT18 +#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SAFTE BIT17 +#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_LED BIT16 +#define B_PCH_SATA_AHCI_EM_CTRL_RST BIT9 +#define B_PCH_SATA_AHCI_EM_CTRL_CTL_TM BIT8 +#define B_PCH_SATA_AHCI_EM_CTRL_STS_MR BIT0 +#define R_PCH_SATA_AHCI_CAP2 0x24 +#define B_PCH_SATA_AHCI_CAP2_DESO BIT5 +#define B_PCH_SATA_AHCI_CAP2_SADM BIT4 +#define B_PCH_SATA_AHCI_CAP2_SDS BIT3 +#define B_PCH_SATA_AHCI_CAP2_APST BIT2 ///< Automatic Partial to Slumber Transitions +#define R_PCH_SATA_AHCI_VSP 0xA0 +#define B_PCH_SATA_AHCI_VSP_SLPD BIT0 +#define R_PCH_SATA_AHCI_RSTF 0xC8 ///< RST Feature Capabilities +#define B_PCH_SATA_AHCI_RSTF_OUD (BIT11 | BIT10) +#define N_PCH_SATA_AHCI_RSTF_OUD 10 +#define B_PCH_SATA_AHCI_RSTF_SEREQ BIT9 +#define B_PCH_SATA_AHCI_RSTF_IROES BIT8 +#define B_PCH_SATA_AHCI_RSTF_LEDL BIT7 +#define B_PCH_SATA_AHCI_RSTF_HDDLK BIT6 +#define B_PCH_SATA_AHCI_RSTF_IRSTOROM BIT5 +#define B_PCH_SATA_AHCI_RSTF_RSTE BIT4 +#define B_PCH_SATA_AHCI_RSTF_R5E BIT3 +#define B_PCH_SATA_AHCI_RSTF_R10E BIT2 +#define B_PCH_SATA_AHCI_RSTF_R1E BIT1 +#define B_PCH_SATA_AHCI_RSTF_R0E BIT0 +#define B_PCH_SATA_AHCI_RSTF_LOWBYTES 0x1FF +#define R_PCH_SATA_AHCI_P0CLB 0x100 +#define R_PCH_SATA_AHCI_P1CLB 0x180 +#define R_PCH_SATA_AHCI_P2CLB 0x200 +#define R_PCH_SATA_AHCI_P3CLB 0x280 +#define R_PCH_SATA_AHCI_P4CLB 0x300 +#define R_PCH_SATA_AHCI_P5CLB 0x380 +#define R_PCH_SATA_AHCI_P6CLB 0x400 +#define R_PCH_SATA_AHCI_P7CLB 0x480 +#define B_PCH_SATA_AHCI_PXCLB 0xFFFFFC00 +#define R_PCH_SATA_AHCI_P0CLBU 0x104 +#define R_PCH_SATA_AHCI_P1CLBU 0x184 +#define R_PCH_SATA_AHCI_P2CLBU 0x204 +#define R_PCH_SATA_AHCI_P3CLBU 0x284 +#define R_PCH_SATA_AHCI_P4CLBU 0x304 +#define R_PCH_SATA_AHCI_P5CLBU 0x384 +#define R_PCH_SATA_AHCI_P6CLBU 0x404 +#define B_PCH_SATA_AHCI_PXCLBU 0xFFFFFFFF +#define R_PCH_SATA_AHCI_P0FB 0x108 +#define R_PCH_SATA_AHCI_P1FB 0x188 +#define R_PCH_SATA_AHCI_P2FB 0x208 +#define R_PCH_SATA_AHCI_P3FB 0x288 +#define R_PCH_SATA_AHCI_P4FB 0x308 +#define R_PCH_SATA_AHCI_P5FB 0x388 +#define R_PCH_SATA_AHCI_P6FB 0x408 +#define B_PCH_SATA_AHCI_PXFB 0xFFFFFF00 +#define R_PCH_SATA_AHCI_P0FBU 0x10C +#define R_PCH_SATA_AHCI_P1FBU 0x18C +#define R_PCH_SATA_AHCI_P2FBU 0x20C +#define R_PCH_SATA_AHCI_P3FBU 0x28C +#define R_PCH_SATA_AHCI_P4FBU 0x30C +#define R_PCH_SATA_AHCI_P5FBU 0x38C +#define R_PCH_SATA_AHCI_P6FBU 0x40C +#define B_PCH_SATA_AHCI_PXFBU 0xFFFFFFFF +#define R_PCH_SATA_AHCI_P0IS 0x110 +#define R_PCH_SATA_AHCI_P1IS 0x190 +#define R_PCH_SATA_AHCI_P2IS 0x210 +#define R_PCH_SATA_AHCI_P3IS 0x290 +#define R_PCH_SATA_AHCI_P4IS 0x310 +#define R_PCH_SATA_AHCI_P5IS 0x390 +#define R_PCH_SATA_AHCI_P6IS 0x410 +#define B_PCH_SATA_AHCI_PXIS_CPDS BIT31 +#define B_PCH_SATA_AHCI_PXIS_TFES BIT30 +#define B_PCH_SATA_AHCI_PXIS_HBFS BIT29 +#define B_PCH_SATA_AHCI_PXIS_HBDS BIT28 +#define B_PCH_SATA_AHCI_PXIS_IFS BIT27 +#define B_PCH_SATA_AHCI_PXIS_INFS BIT26 +#define B_PCH_SATA_AHCI_PXIS_OFS BIT24 +#define B_PCH_SATA_AHCI_PXIS_IPMS BIT23 +#define B_PCH_SATA_AHCI_PXIS_PRCS BIT22 +#define B_PCH_SATA_AHCI_PXIS_DIS BIT7 +#define B_PCH_SATA_AHCI_PXIS_PCS BIT6 +#define B_PCH_SATA_AHCI_PXIS_DPS BIT5 +#define B_PCH_SATA_AHCI_PXIS_UFS BIT4 +#define B_PCH_SATA_AHCI_PXIS_SDBS BIT3 +#define B_PCH_SATA_AHCI_PXIS_DSS BIT2 +#define B_PCH_SATA_AHCI_PXIS_PSS BIT1 +#define B_PCH_SATA_AHCI_PXIS_DHRS BIT0 +#define R_PCH_SATA_AHCI_P0IE 0x114 +#define R_PCH_SATA_AHCI_P1IE 0x194 +#define R_PCH_SATA_AHCI_P2IE 0x214 +#define R_PCH_SATA_AHCI_P3IE 0x294 +#define R_PCH_SATA_AHCI_P4IE 0x314 +#define R_PCH_SATA_AHCI_P5IE 0x394 +#define R_PCH_SATA_AHCI_P6IE 0x414 +#define B_PCH_SATA_AHCI_PXIE_CPDE BIT31 +#define B_PCH_SATA_AHCI_PXIE_TFEE BIT30 +#define B_PCH_SATA_AHCI_PXIE_HBFE BIT29 +#define B_PCH_SATA_AHCI_PXIE_HBDE BIT28 +#define B_PCH_SATA_AHCI_PXIE_IFE BIT27 +#define B_PCH_SATA_AHCI_PXIE_INFE BIT26 +#define B_PCH_SATA_AHCI_PXIE_OFE BIT24 +#define B_PCH_SATA_AHCI_PXIE_IPME BIT23 +#define B_PCH_SATA_AHCI_PXIE_PRCE BIT22 +#define B_PCH_SATA_AHCI_PXIE_DIE BIT7 +#define B_PCH_SATA_AHCI_PXIE_PCE BIT6 +#define B_PCH_SATA_AHCI_PXIE_DPE BIT5 +#define B_PCH_SATA_AHCI_PXIE_UFIE BIT4 +#define B_PCH_SATA_AHCI_PXIE_SDBE BIT3 +#define B_PCH_SATA_AHCI_PXIE_DSE BIT2 +#define B_PCH_SATA_AHCI_PXIE_PSE BIT1 +#define B_PCH_SATA_AHCI_PXIE_DHRE BIT0 +#define R_PCH_SATA_AHCI_P0CMD 0x118 +#define R_PCH_SATA_AHCI_P1CMD 0x198 +#define R_PCH_SATA_AHCI_P2CMD 0x218 +#define R_PCH_SATA_AHCI_P3CMD 0x298 +#define R_PCH_SATA_AHCI_P4CMD 0x318 +#define R_PCH_SATA_AHCI_P5CMD 0x398 +#define R_PCH_SATA_AHCI_P6CMD 0x418 +#define B_PCH_SATA_AHCI_PxCMD_ICC (BIT31 | BIT30 | BIT29 | BIT28) +#define B_PCH_SATA_AHCI_PxCMD_MASK (BIT27 | BIT26 | BIT21 | BIT22 | BIT19 | BIT18) +#define B_PCH_SATA_AHCI_PxCMD_ASP BIT27 +#define B_PCH_SATA_AHCI_PxCMD_ALPE BIT26 +#define B_PCH_SATA_AHCI_PxCMD_DLAE BIT25 +#define B_PCH_SATA_AHCI_PxCMD_ATAPI BIT24 +#define B_PCH_SATA_AHCI_PxCMD_APSTE BIT23 +#define B_PCH_SATA_AHCI_PxCMD_SUD BIT1 +#define R_PCH_SATA_AHCI_P0DEVSLP 0x144 +#define R_PCH_SATA_AHCI_P1DEVSLP 0x1C4 +#define R_PCH_SATA_AHCI_P2DEVSLP 0x244 +#define R_PCH_SATA_AHCI_P3DEVSLP 0x2C4 +#define B_PCH_SATA_AHCI_PxDEVSLP_DSP BIT1 +#define B_PCH_SATA_AHCI_PxDEVSLP_ADSE BIT0 +#define B_PCH_SATA_AHCI_PxDEVSLP_DITO_MASK 0x01FF8000 +#define V_PCH_SATA_AHCI_PxDEVSLP_DITO_625 0x01388000 +#define B_PCH_SATA_AHCI_PxDEVSLP_DM_MASK 0x1E000000 +#define V_PCH_SATA_AHCI_PxDEVSLP_DM_16 0x1E000000 +#define B_PCH_SATA_AHCI_PxCMD_ESP BIT21 ///< Used with an external SATA device +#define B_PCH_SATA_AHCI_PxCMD_MPSP BIT19 ///< Mechanical Switch Attached to Port +#define B_PCH_SATA_AHCI_PxCMD_HPCP BIT18 ///< Hotplug capable +#define B_PCH_SATA_AHCI_PxCMD_CR BIT15 +#define B_PCH_SATA_AHCI_PxCMD_FR BIT14 +#define B_PCH_SATA_AHCI_PxCMD_ISS BIT13 +#define B_PCH_SATA_AHCI_PxCMD_CCS 0x00001F00 +#define B_PCH_SATA_AHCI_PxCMD_FRE BIT4 +#define B_PCH_SATA_AHCI_PxCMD_CLO BIT3 +#define B_PCH_SATA_AHCI_PxCMD_POD BIT2 +#define B_PCH_SATA_AHCI_PxCMD_SUD BIT1 +#define B_PCH_SATA_AHCI_PxCMD_ST BIT0 +#define R_PCH_SATA_AHCI_P0TFD 0x120 +#define R_PCH_SATA_AHCI_P1TFD 0x1A0 +#define R_PCH_SATA_AHCI_P2TFD 0x220 +#define R_PCH_SATA_AHCI_P3TFD 0x2A0 +#define R_PCH_SATA_AHCI_P4TFD 0x320 +#define R_PCH_SATA_AHCI_P5TFD 0x3A0 +#define R_PCH_SATA_AHCI_P6TFD 0x420 +#define B_PCH_SATA_AHCI_PXTFD_ERR 0x0000FF00 +#define B_PCH_SATA_AHCI_PXTFD_STS 0x000000FF +#define R_PCH_SATA_AHCI_P0SIG 0x124 +#define R_PCH_SATA_AHCI_P1SIG 0x1A4 +#define R_PCH_SATA_AHCI_P2SIG 0x224 +#define R_PCH_SATA_AHCI_P3SIG 0x2A4 +#define R_PCH_SATA_AHCI_P4SIG 0x324 +#define R_PCH_SATA_AHCI_P5SIG 0x3A4 +#define R_PCH_SATA_AHCI_P6SIG 0x424 +#define B_PCH_SATA_AHCI_PXSIG_LBA_HR 0xFF000000 +#define B_PCH_SATA_AHCI_PXSIG_LBA_MR 0x00FF0000 +#define B_PCH_SATA_AHCI_PXSIG_LBA_LR 0x0000FF00 +#define B_PCH_SATA_AHCI_PXSIG_SCR 0x000000FF +#define R_PCH_SATA_AHCI_P0SSTS 0x128 +#define R_PCH_SATA_AHCI_P1SSTS 0x1A8 +#define R_PCH_SATA_AHCI_P2SSTS 0x228 +#define R_PCH_SATA_AHCI_P3SSTS 0x2A8 +#define R_PCH_SATA_AHCI_P4SSTS 0x328 +#define R_PCH_SATA_AHCI_P5SSTS 0x3A8 +#define R_PCH_SATA_AHCI_P6SSTS 0x428 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_0 0x00000000 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_1 0x00000100 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_2 0x00000200 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_6 0x00000600 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_0 0x00000000 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_1 0x00000010 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_2 0x00000020 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_3 0x00000030 +#define B_PCH_SATA_AHCI_PXSSTS_DET_0 0x00000000 +#define B_PCH_SATA_AHCI_PXSSTS_DET_1 0x00000001 +#define B_PCH_SATA_AHCI_PXSSTS_DET_3 0x00000003 +#define B_PCH_SATA_AHCI_PXSSTS_DET_4 0x00000004 +#define R_PCH_SATA_AHCI_P0SCTL 0x12C +#define R_PCH_SATA_AHCI_P1SCTL 0x1AC +#define R_PCH_SATA_AHCI_P2SCTL 0x22C +#define R_PCH_SATA_AHCI_P3SCTL 0x2AC +#define R_PCH_SATA_AHCI_P4SCTL 0x32C +#define R_PCH_SATA_AHCI_P5SCTL 0x3AC +#define R_PCH_SATA_AHCI_P6SCTL 0x42C +#define B_PCH_SATA_AHCI_PXSCTL_IPM 0x00000F00 +#define V_PCH_SATA_AHCI_PXSCTL_IPM_0 0x00000000 +#define V_PCH_SATA_AHCI_PXSCTL_IPM_1 0x00000100 +#define V_PCH_SATA_AHCI_PXSCTL_IPM_2 0x00000200 +#define V_PCH_SATA_AHCI_PXSCTL_IPM_3 0x00000300 +#define B_PCH_SATA_AHCI_PXSCTL_SPD 0x000000F0 +#define V_PCH_SATA_AHCI_PXSCTL_SPD_0 0x00000000 +#define V_PCH_SATA_AHCI_PXSCTL_SPD_1 0x00000010 +#define V_PCH_SATA_AHCI_PXSCTL_SPD_2 0x00000020 +#define V_PCH_SATA_AHCI_PXSCTL_SPD_3 0x00000030 +#define B_PCH_SATA_AHCI_PXSCTL_DET 0x0000000F +#define V_PCH_SATA_AHCI_PXSCTL_DET_0 0x00000000 +#define V_PCH_SATA_AHCI_PXSCTL_DET_1 0x00000001 +#define V_PCH_SATA_AHCI_PXSCTL_DET_4 0x00000004 +#define R_PCH_SATA_AHCI_P0SERR 0x130 +#define R_PCH_SATA_AHCI_P1SERR 0x1B0 +#define R_PCH_SATA_AHCI_P2SERR 0x230 +#define R_PCH_SATA_AHCI_P3SERR 0x2B0 +#define R_PCH_SATA_AHCI_P4SERR 0x330 +#define R_PCH_SATA_AHCI_P5SERR 0x3B0 +#define R_PCH_SATA_AHCI_P6SERR 0x430 +#define B_PCH_SATA_AHCI_PXSERR_EXCHG BIT26 +#define B_PCH_SATA_AHCI_PXSERR_UN_FIS_TYPE BIT25 +#define B_PCH_SATA_AHCI_PXSERR_TRSTE_24 BIT24 +#define B_PCH_SATA_AHCI_PXSERR_TRSTE_23 BIT23 +#define B_PCH_SATA_AHCI_PXSERR_HANDSHAKE BIT22 +#define B_PCH_SATA_AHCI_PXSERR_CRC_ERROR BIT21 +#define B_PCH_SATA_AHCI_PXSERR_10B8B_DECERR BIT19 +#define B_PCH_SATA_AHCI_PXSERR_COMM_WAKE BIT18 +#define B_PCH_SATA_AHCI_PXSERR_PHY_ERROR BIT17 +#define B_PCH_SATA_AHCI_PXSERR_PHY_RDY_CHG BIT16 +#define B_PCH_SATA_AHCI_PXSERR_INTRNAL_ERR BIT11 +#define B_PCH_SATA_AHCI_PXSERR_PROTOCOL_ERR BIT10 +#define B_PCH_SATA_AHCI_PXSERR_PCDIE BIT9 +#define B_PCH_SATA_AHCI_PXSERR_TDIE BIT8 +#define B_PCH_SATA_AHCI_PXSERR_RCE BIT1 +#define B_PCH_SATA_AHCI_PXSERR_RDIE BIT0 +#define R_PCH_SATA_AHCI_P0SACT 0x134 +#define R_PCH_SATA_AHCI_P1SACT 0x1B4 +#define R_PCH_SATA_AHCI_P2SACT 0x234 +#define R_PCH_SATA_AHCI_P3SACT 0x2B4 +#define R_PCH_SATA_AHCI_P4SACT 0x334 +#define R_PCH_SATA_AHCI_P5SACT 0x3B4 +#define R_PCH_SATA_AHCI_P6SACT 0x434 +#define B_PCH_SATA_AHCI_PXSACT_DS 0xFFFFFFFF +#define R_PCH_SATA_AHCI_P0CI 0x138 +#define R_PCH_SATA_AHCI_P1CI 0x1B8 +#define R_PCH_SATA_AHCI_P2CI 0x238 +#define R_PCH_SATA_AHCI_P3CI 0x2B8 +#define R_PCH_SATA_AHCI_P4CI 0x338 +#define R_PCH_SATA_AHCI_P5CI 0x3B8 +#define R_PCH_SATA_AHCI_P6CI 0x438 +#define B_PCH_SATA_AHCI_PXCI 0xFFFFFFFF + +// +// Macros of ICH capabilities for SATA controller which are used by SATA controller driver +// +// +// +// Define the individual capabilities of each sata controller +// +#define LPTH_SATA_MAX_CONTROLLERS 2 ///< max sata controllers number supported +#define LPTLP_SATA_MAX_CONTROLLERS 1 ///< max sata controllers number supported +#define PCH_IDE_MAX_CHANNELS 2 ///< max channels number of single sata controller +#define PCH_IDE_MAX_DEVICES 2 ///< max devices number of single sata channel +#define LPTH_AHCI_MAX_PORTS 6 ///< max number of sata ports in LPTH +#define LPTLP_AHCI_MAX_PORTS 4 ///< max number of sata ports in LPTLP +#define PCH_SATA_DEVICE_ID_INVALID 0xFFFF +#define PCH_SATA_1_DEVICE_NUMBER PCI_DEVICE_NUMBER_PCH_SATA +#define PCH_SATA_1_FUNCTION_NUMBER PCI_FUNCTION_NUMBER_PCH_SATA +#define PCH_H_AHCI_1_MAX_PORTS 6 ///< max number of ports in sata in PCH +#define PCH_LP_AHCI_1_MAX_PORTS 4 ///< max number of ports in sata1 in PCH +#define PCH_IDE_1_MAX_CHANNELS 2 +#define PCH_IDE_1_MAX_DEVICES 2 +#define PCH_IDE_1_MAX_PORTS 4 + +#define PCH_SATA_2_DEVICE_NUMBER PCI_DEVICE_NUMBER_PCH_SATA2 +#define PCH_SATA_2_FUNCTION_NUMBER PCI_FUNCTION_NUMBER_PCH_SATA2 +#define PCH_AHCI_2_MAX_PORTS 2 ///< number of ports in sata2 in PCH +#define PCH_IDE_2_MAX_CHANNELS 2 +#define PCH_IDE_2_MAX_DEVICES 2 +#define PCH_IDE_2_MAX_PORTS 2 + +// +// GPIO SATA0GP is the Sata port 0 reset pin. +// +#define PCH_GPIO_SATA_PORT0_RESET 21 +#define PCH_LP_GPIO_SATA_PORT0_RESET (R_PCH_GP_N_CONFIG0 + (34 * 0x08)) +// +// GPIO SATA1GP is the Sata port 1 reset pin. +// +#define PCH_GPIO_SATA_PORT1_RESET 19 +#define PCH_LP_GPIO_SATA_PORT1_RESET (R_PCH_GP_N_CONFIG0 + (35 * 0x08)) + +// +// GPIO SATA2GP is the Sata port 2 reset pin. +// +#define PCH_GPIO_SATA_PORT2_RESET 36 +#define PCH_LP_GPIO_SATA_PORT2_RESET (R_PCH_GP_N_CONFIG0 + (36 * 0x08)) + +// +// GPIO SATA3GP is the Sata port 3 reset pin. +// +#define PCH_GPIO_SATA_PORT3_RESET 37 +#define PCH_LP_GPIO_SATA_PORT3_RESET (R_PCH_GP_N_CONFIG0 + (37 * 0x08)) + +// +// GPIO SATA4GP is the Sata port 4 reset pin. +// +#define PCH_GPIO_SATA_PORT4_RESET 16 +// +// GPIO SATA5GP is the Sata port 5 reset pin. +// +#define PCH_GPIO_SATA_PORT5_RESET 49 + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsSerialIo.h b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsSerialIo.h new file mode 100644 index 0000000..c99d758 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsSerialIo.h @@ -0,0 +1,169 @@ +/** @file + Register names for PCH Serial IO Controllers + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_CPT_" + - Registers / bits that are different between SKUs are denoted by "_<SKU_name>" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without <generation_name> inserted. + +@copyright + Copyright (c) 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _PCH_REGS_SERIAL_IO_H_ +#define _PCH_REGS_SERIAL_IO_H_ + +#ifdef SERIAL_IO_FLAG + +// +// Serial IO DMA Controller Registers (D21:F0) +// +#define PCI_DEVICE_NUMBER_PCH_LP_SERIAL_IO_DMA 21 +#define PCI_FUNCTION_NUMBER_PCH_LP_SERIAL_IO_DMA 0 +#define R_PCH_LP_SERIAL_IO_DMA_VENDOR_ID 0x00 +#define V_PCH_LP_SERIAL_IO_DMA_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_LP_SERIAL_IO_DMA_DEVICE_ID 0x02 +#define V_PCH_LP_SERIAL_IO_DMA_DEVICE_ID 0x9C60 + +// +// Serial IO I2C0 Controller Registers (D21:F1) +// +#define PCI_DEVICE_NUMBER_PCH_LP_SERIAL_IO_I2C0 21 +#define PCI_FUNCTION_NUMBER_PCH_LP_SERIAL_IO_I2C0 1 +#define R_PCH_LP_SERIAL_IO_I2C0_VENDOR_ID 0x00 +#define V_PCH_LP_SERIAL_IO_I2C0_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_LP_SERIAL_IO_I2C0_DEVICE_ID 0x02 +#define V_PCH_LP_SERIAL_IO_I2C0_DEVICE_ID 0x9C61 + +// +// Serial IO I2C0 Controller Registers (D21:F2) +// +#define PCI_DEVICE_NUMBER_PCH_LP_SERIAL_IO_I2C1 21 +#define PCI_FUNCTION_NUMBER_PCH_LP_SERIAL_IO_I2C1 2 +#define R_PCH_LP_SERIAL_IO_I2C1_VENDOR_ID 0x00 +#define V_PCH_LP_SERIAL_IO_I2C1_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_LP_SERIAL_IO_I2C1_DEVICE_ID 0x02 +#define V_PCH_LP_SERIAL_IO_I2C1_DEVICE_ID 0x9C62 + +// +// Serial IO SPI0 Controller Registers (D21:F3) +// +#define PCI_DEVICE_NUMBER_PCH_LP_SERIAL_IO_SPI0 21 +#define PCI_FUNCTION_NUMBER_PCH_LP_SERIAL_IO_SPI0 3 +#define R_PCH_LP_SERIAL_IO_SPI0_VENDOR_ID 0x00 +#define V_PCH_LP_SERIAL_IO_SPI0_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_LP_SERIAL_IO_SPI0_DEVICE_ID 0x02 +#define V_PCH_LP_SERIAL_IO_SPI0_DEVICE_ID 0x9C65 + +// +// Serial IO SPI1 Controller Registers (D21:F4) +// +#define PCI_DEVICE_NUMBER_PCH_LP_SERIAL_IO_SPI1 21 +#define PCI_FUNCTION_NUMBER_PCH_LP_SERIAL_IO_SPI1 4 +#define R_PCH_LP_SERIAL_IO_SPI1_VENDOR_ID 0x00 +#define V_PCH_LP_SERIAL_IO_SPI1_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_LP_SERIAL_IO_SPI1_DEVICE_ID 0x02 +#define V_PCH_LP_SERIAL_IO_SPI1_DEVICE_ID 0x9C66 + +// +// Serial IO UART0 Controller Registers (D21:F5) +// +#define PCI_DEVICE_NUMBER_PCH_LP_SERIAL_IO_UART0 21 +#define PCI_FUNCTION_NUMBER_PCH_LP_SERIAL_IO_UART0 5 +#define R_PCH_LP_SERIAL_IO_UART0_VENDOR_ID 0x00 +#define V_PCH_LP_SERIAL_IO_UART0_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_LP_SERIAL_IO_UART0_DEVICE_ID 0x02 +#define V_PCH_LP_SERIAL_IO_UART0_DEVICE_ID 0x9C63 + +// +// Serial IO UART1 Controller Registers (D21:F6) +// +#define PCI_DEVICE_NUMBER_PCH_LP_SERIAL_IO_UART1 21 +#define PCI_FUNCTION_NUMBER_PCH_LP_SERIAL_IO_UART1 6 +#define R_PCH_LP_SERIAL_IO_UART1_VENDOR_ID 0x00 +#define V_PCH_LP_SERIAL_IO_UART1_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_LP_SERIAL_IO_UART1_DEVICE_ID 0x02 +#define V_PCH_LP_SERIAL_IO_UART1_DEVICE_ID 0x9C64 + +// +// Serial IO SDIO Controller Registers (D23:F0) +// +#define PCI_DEVICE_NUMBER_PCH_LP_SERIAL_IO_SDIO 23 +#define PCI_FUNCTION_NUMBER_PCH_LP_SERIAL_IO_SDIO 0 +#define R_PCH_LP_SERIAL_IO_SDIO_VENDOR_ID 0x00 +#define V_PCH_LP_SERIAL_IO_SDIO_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_LP_SERIAL_IO_SDIO_DEVICE_ID 0x02 +#define V_PCH_LP_SERIAL_IO_SDIO_DEVICE_ID 0x9C35 +#define R_PCH_LP_SERIAL_IO_SDIO_PPR_CMD12 0x3C +#define R_PCH_LP_SERIAL_IO_SDIO_PPR_GEN 0x1008 +#define B_PCH_LP_SERIAL_IO_SDIO_PPR_GEN_LTR_MODE BIT2 +#define R_PCH_LP_SERIAL_IO_SDIO_PPR_SW_LTR 0x1010 + + +#define R_PCH_LP_SERIAL_IO_SDIO_SLAVE_DELAY_DDR50_MODE 0x1034 + +#define V_LP_SERIAL_IO_DEV_MIN_FUN 0 +#define V_LP_SERIAL_IO_DEV_MAX_FUN 6 + +// +// Serial IO Controllers General PCI Configuration Registers +// +#define R_PCH_LP_SERIAL_IO_VENDOR_ID 0x00 +#define R_PCH_LP_SERIAL_IO_DEVICE_ID 0x02 +#define R_PCH_LP_SERIAL_IO_COMMAND 0x04 +#define B_PCH_LP_SERIAL_IO_COMMAND_BME BIT2 +#define B_PCH_LP_SERIAL_IO_COMMAND_MSE BIT1 +#define R_PCH_LP_SERIAL_IO_BAR0 0x10 +#define B_PCH_LP_SERIAL_IO_BAR0_BAR 0xFFFFF000 +#define R_PCH_LP_SERIAL_IO_BAR1 0x14 +#define B_PCH_LP_SERIAL_IO_BAR1_BAR 0xFFFFF000 +#define V_PCH_LP_SERIAL_IO_BAR_SIZE (4 * 1024) +#define V_PCH_LP_SERIAL_SDIO_BAR_SIZE (8 * 1024) +#define N_PCH_LP_SERIAL_IO_BAR_ALIGNMENT 12 +#define R_PCH_LP_SERIAL_IO_PME_CTRL_STS 0x84 +#define B_PCH_LP_SERIAL_IO_PME_CTRL_STS_PWR_ST (BIT1| BIT0) + +// +// Serial IO Controllers Private Registers +// +#define R_PCH_LP_SERIAL_IO_PPR_RST 0x804 +#define B_PCH_LP_SERIAL_IO_PPR_RST_APB BIT0 +#define B_PCH_LP_SERIAL_IO_PPR_RST_FUNC BIT1 +#define R_PCH_LP_SERIAL_IO_PPR_GEN 0x808 +#define B_PCH_LP_SERIAL_IO_PPR_GEN_LTR_MODE BIT2 +#define B_PCH_LP_SERIAL_IO_PPR_GEN_IO_VOLTAGE_SEL BIT3 +#define R_PCH_LP_SERIAL_IO_PPR_AUTO_LTR 0x814 + +#define R_PCH_LP_SERIAL_IO_GPIODF0 0x154 +#define B_PCH_LP_SERIAL_IO_GPIODF0_SPI_IDLE_DET_EN BIT0 +#define B_PCH_LP_SERIAL_IO_GPIODF0_I2C_IDLE_DET_EN BIT1 +#define B_PCH_LP_SERIAL_IO_GPIODF0_UART_IDLE_DET_EN BIT2 +#define B_PCH_LP_SERIAL_IO_GPIODF0_DMA_IDLE_DET_EN BIT3 +#define B_PCH_LP_SERIAL_IO_GPIODF0_SDIO_IDLE_DET_EN BIT4 + +#endif // SERIAL_IO_FLAG +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsSmbus.h b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsSmbus.h new file mode 100644 index 0000000..a848108 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsSmbus.h @@ -0,0 +1,172 @@ +/** @file + Register names for PCH Smbus Device. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_LPT_" + - Registers / bits that are different between SKUs are denoted by "_<SKU_name>" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without <generation_name> inserted. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _PCH_REGS_SMBUS_H_ +#define _PCH_REGS_SMBUS_H_ + +// +// SMBus Controller Registers (D31:F3) +// +#define PCI_DEVICE_NUMBER_PCH_SMBUS 31 +#define PCI_FUNCTION_NUMBER_PCH_SMBUS 3 +#define R_PCH_SMBUS_VENDOR_ID 0x00 +#define V_PCH_SMBUS_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_SMBUS_DEVICE_ID 0x02 +#define V_PCH_LPTH_SMBUS_DEVICE_ID 0x8C22 +#define V_PCH_LPTLP_SMBUS_DEVICE_ID 0x9C22 +#define R_PCH_SMBUS_PCICMD 0x04 +#define B_PCH_SMBUS_PCICMD_INTR_DIS BIT10 +#define B_PCH_SMBUS_PCICMD_FBE BIT9 +#define B_PCH_SMBUS_PCICMD_SERR_EN BIT8 +#define B_PCH_SMBUS_PCICMD_WCC BIT7 +#define B_PCH_SMBUS_PCICMD_PER BIT6 +#define B_PCH_SMBUS_PCICMD_VPS BIT5 +#define B_PCH_SMBUS_PCICMD_PMWE BIT4 +#define B_PCH_SMBUS_PCICMD_SCE BIT3 +#define B_PCH_SMBUS_PCICMD_BME BIT2 +#define B_PCH_SMBUS_PCICMD_MSE BIT1 +#define B_PCH_SMBUS_PCICMD_IOSE BIT0 +#define R_PCH_SMBUS_PCISTS 0x06 +#define B_PCH_SMBUS_PCISTS_DPE BIT15 +#define B_PCH_SMBUS_PCISTS_SSE BIT14 +#define B_PCH_SMBUS_PCISTS_RMA BIT13 +#define B_PCH_SMBUS_PCISTS_RTA BIT12 +#define B_PCH_SMBUS_PCISTS_STA BIT11 +#define B_PCH_SMBUS_PCISTS_DEVT (BIT10 | BIT9) +#define B_PCH_SMBUS_PCISTS_DPED BIT8 +#define B_PCH_SMBUS_PCISTS_FB2BC BIT7 +#define B_PCH_SMBUS_PCISTS_UDF BIT6 +#define B_PCH_SMBUS_PCISTS_66MHZ_CAP BIT5 +#define B_PCH_SMBUS_PCISTS_CAP_LIST BIT4 +#define B_PCH_SMBUS_PCISTS_INTS BIT3 +#define R_PCH_SMBUS_RID 0x08 +#define B_PCH_SMBUS_RID 0xFF +#define R_PCH_SMBUS_SCC 0x0A +#define V_PCH_SMBUS_SCC 0x05 +#define R_PCH_SMBUS_BCC 0x0B +#define V_PCH_SMBUS_BCC 0x0C +#define R_PCH_SMBUS_BAR0 0x10 +#define B_PCH_SMBUS_BAR0_BAR 0xFFFFFF00 +#define B_PCH_SMBUS_BAR0_PREF BIT3 +#define B_PCH_SMBUS_BAR0_ADDRNG (BIT2 | BIT1) +#define B_PCH_SMBUS_BAR0_MSI BIT0 +#define R_PCH_SMBUS_BAR1 0x14 +#define B_PCH_SMBUS_BAR1_BAR 0xFFFFFFFF +#define R_PCH_SMBUS_BASE 0x20 +#define V_PCH_SMBUS_BASE_SIZE (1 << 5) +#define B_PCH_SMBUS_BASE_BAR 0x0000FFE0 +#define R_PCH_SMBUS_SVID 0x2C +#define B_PCH_SMBUS_SVID 0xFFFF +#define R_PCH_SMBUS_SID 0x2E +#define B_PCH_SMBUS_SID 0xFFFF +#define R_PCH_SMBUS_INT_LN 0x3C +#define B_PCH_SMBUS_INT_LN 0xFF +#define R_PCH_SMBUS_INT_PN 0x3D +#define B_PCH_SMBUS_INT_PN 0xFF +#define R_PCH_SMBUS_HOSTC 0x40 +#define B_PCH_SMBUS_HOSTC_SPDWD BIT4 +#define B_PCH_SMBUS_HOSTC_SSRESET BIT3 +#define B_PCH_SMBUS_HOSTC_I2C_EN BIT2 +#define B_PCH_SMBUS_HOSTC_SMI_EN BIT1 +#define B_PCH_SMBUS_HOSTC_HST_EN BIT0 + +// +// SMBus I/O Registers +// +#define R_PCH_SMBUS_HSTS 0x00 ///< Host Status Register R/W +#define B_PCH_SMBUS_HBSY 0x01 +#define B_PCH_SMBUS_INTR 0x02 +#define B_PCH_SMBUS_DERR 0x04 +#define B_PCH_SMBUS_BERR 0x08 +#define B_PCH_SMBUS_FAIL 0x10 +#define B_PCH_SMBUS_SMBALERT_STS 0x20 +#define B_PCH_SMBUS_IUS 0x40 +#define B_PCH_SMBUS_BYTE_DONE_STS 0x80 +#define B_PCH_SMBUS_ERROR (B_PCH_SMBUS_DERR | B_PCH_SMBUS_BERR | B_PCH_SMBUS_FAIL) +#define B_PCH_SMBUS_HSTS_ALL 0xFF +#define R_PCH_SMBUS_HCTL 0x02 ///< Host Control Register R/W +#define B_PCH_SMBUS_INTREN 0x01 +#define B_PCH_SMBUS_KILL 0x02 +#define B_PCH_SMBUS_SMB_CMD 0x1C +#define V_PCH_SMBUS_SMB_CMD_QUICK 0x00 +#define V_PCH_SMBUS_SMB_CMD_BYTE 0x04 +#define V_PCH_SMBUS_SMB_CMD_BYTE_DATA 0x08 +#define V_PCH_SMBUS_SMB_CMD_WORD_DATA 0x0C +#define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL 0x10 +#define V_PCH_SMBUS_SMB_CMD_BLOCK 0x14 +#define V_PCH_SMBUS_SMB_CMD_IIC_READ 0x18 +#define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS 0x1C +#define B_PCH_SMBUS_LAST_BYTE 0x20 +#define B_PCH_SMBUS_START 0x40 +#define B_PCH_SMBUS_PEC_EN 0x80 +#define R_PCH_SMBUS_HCMD 0x03 ///< Host Command Register R/W +#define R_PCH_SMBUS_TSA 0x04 ///< Transmit Slave Address Register R/W +#define B_PCH_SMBUS_RW_SEL 0x01 +#define B_PCH_SMBUS_READ 0x01 // RW +#define B_PCH_SMBUS_WRITE 0x00 // RW +#define B_PCH_SMBUS_ADDRESS 0xFE +#define R_PCH_SMBUS_HD0 0x05 ///< Data 0 Register R/W +#define R_PCH_SMBUS_HD1 0x06 ///< Data 1 Register R/W +#define R_PCH_SMBUS_HBD 0x07 ///< Host Block Data Register R/W +#define R_PCH_SMBUS_PEC 0x08 ///< Packet Error Check Data Register R/W +#define R_PCH_SMBUS_RSA 0x09 ///< Receive Slave Address Register R/W +#define B_PCH_SMBUS_SLAVE_ADDR 0x7F +#define R_PCH_SMBUS_SD 0x0A ///< Receive Slave Data Register R/W +#define R_PCH_SMBUS_AUXS 0x0C ///< Auxiliary Status Register R/WC +#define B_PCH_SMBUS_CRCE 0x01 +#define B_PCH_SMBUS_STCO 0x02 ///< SMBus TCO Mode +#define R_PCH_SMBUS_AUXC 0x0D ///< Auxiliary Control Register R/W +#define B_PCH_SMBUS_AAC 0x01 +#define B_PCH_SMBUS_E32B 0x02 +#define R_PCH_SMBUS_SMLC 0x0E ///< SMLINK Pin Control Register R/W +#define B_PCH_SMBUS_SMLINK0_CUR_STS 0x01 +#define B_PCH_SMBUS_SMLINK1_CUR_STS 0x02 +#define B_PCH_SMBUS_SMLINK_CLK_CTL 0x04 +#define R_PCH_SMBUS_SMBC 0x0F ///< SMBus Pin Control Register R/W +#define B_PCH_SMBUS_SMBCLK_CUR_STS 0x01 +#define B_PCH_SMBUS_SMBDATA_CUR_STS 0x02 +#define B_PCH_SMBUS_SMBCLK_CTL 0x04 +#define R_PCH_SMBUS_SSTS 0x10 ///< Slave Status Register R/WC +#define B_PCH_SMBUS_HOST_NOTIFY_STS 0x01 +#define R_PCH_SMBUS_SCMD 0x11 ///< Slave Command Register R/W +#define B_PCH_SMBUS_HOST_NOTIFY_INTREN 0x01 +#define B_PCH_SMBUS_HOST_NOTIFY_WKEN 0x02 +#define B_PCH_SMBUS_SMBALERT_DIS 0x04 +#define R_PCH_SMBUS_NDA 0x14 ///< Notify Device Address Register RO +#define B_PCH_SMBUS_DEVICE_ADDRESS 0xFE +#define R_PCH_SMBUS_NDLB 0x16 ///< Notify Data Low Byte Register RO +#define R_PCH_SMBUS_NDHB 0x17 ///< Notify Data High Byte Register RO +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsSpi.h b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsSpi.h new file mode 100644 index 0000000..b195e33 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsSpi.h @@ -0,0 +1,380 @@ +/** @file + Register names for PCH SPI device. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_LPT_" + - Registers / bits that are different between SKUs are denoted by "_<SKU_name>" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without <generation_name> inserted. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _PCH_REGS_SPI_H_ +#define _PCH_REGS_SPI_H_ + +// +// SPI Host Interface Registers +// +#define R_PCH_RCRB_SPI_BASE 0x3800 ///< Base address of the SPI host interface registers +#define R_PCH_SPI_BFPR (R_PCH_RCRB_SPI_BASE + 0x00) ///< BIOS Flash Primary Region Register(32bits), which is RO and contains the same value from FREG1 +#define R_PCH_SPI_HSFS (R_PCH_RCRB_SPI_BASE + 0x04) ///< Hardware Sequencing Flash Status Register(16bits) +#define B_PCH_SPI_HSFS_FLOCKDN BIT15 ///< Flash Configuration Lock-Down +#define B_PCH_SPI_HSFS_FDV BIT14 ///< Flash Descriptor Valid, once valid software can use hareware sequencing regs +#define B_PCH_SPI_HSFS_FDOPSS BIT13 ///< Flash Descriptor Override Pin-Strap Status, 0: The Flash Descriptor Security Override / Intel + ///< ME Debug Mode strap is set via external pull-up on HDA_SDO; 1: No override. +#define B_PCH_SPI_PRR3PRR4_LOCKDN BIT12 ///< PRR3 PRR4 Lock-Down +#define B_PCH_SPI_HSFS_SCIP BIT5 ///< SPI cyble in progress +#define B_PCH_SPI_HSFS_BERASE_MASK (BIT4 | BIT3) ///< Block/Sector Erase Size +#define V_PCH_SPI_HSFS_BERASE_256B 0x00 ///< Block/Sector = 256 Bytes +#define V_PCH_SPI_HSFS_BERASE_4K 0x01 ///< Block/Sector = 4K Bytes +#define V_PCH_SPI_HSFS_BERASE_8K 0x10 ///< Block/Sector = 8K Bytes +#define V_PCH_SPI_HSFS_BERASE_64K 0x11 ///< Block/Sector = 64K Bytes +#define B_PCH_SPI_HSFS_AEL BIT2 ///< Access Error Log +#define B_PCH_SPI_HSFS_FCERR BIT1 ///< Flash Cycle Error +#define B_PCH_SPI_HSFS_FDONE BIT0 ///< Flash Cycle Done +#define R_PCH_SPI_HSFC (R_PCH_RCRB_SPI_BASE + 0x06) ///< Hardware Sequencing Flash Control Register(16bits) +#define B_PCH_SPI_HSFC_FSMIE BIT15 ///< Flash SPI SMI# Enable +#define B_PCH_SPI_HSFC_FDBC_MASK 0x3F00 ///< Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1. +#define B_PCH_SPI_HSFC_FCYCLE_MASK 0x0006 ///< Flash Cycle. +#define V_PCH_SPI_HSFC_FCYCLE_READ 0 ///< Flash Cycle Read +#define V_PCH_SPI_HSFC_FCYCLE_WRITE 2 ///< Flash Cycle Write +#define V_PCH_SPI_HSFC_FCYCLE_ERASE 3 ///< Flash Cycle Block Erase +#define B_PCH_SPI_HSFC_FCYCLE_FGO BIT0 ///< Flash Cycle Go. +#define R_PCH_SPI_FADDR (R_PCH_RCRB_SPI_BASE + 0x08) ///< SPI Flash Address +#define B_PCH_SPI_FADDR_MASK 0x07FFFFFF ///< SPI Flash Address Mask (0~26bit) +#define R_PCH_SPI_FDATA00 (R_PCH_RCRB_SPI_BASE + 0x10) ///< SPI Data 00 (32 bits) +#define R_PCH_SPI_FDATA01 (R_PCH_RCRB_SPI_BASE + 0x14) ///< SPI Data 01 +#define R_PCH_SPI_FDATA02 (R_PCH_RCRB_SPI_BASE + 0x18) ///< SPI Data 02 +#define R_PCH_SPI_FDATA03 (R_PCH_RCRB_SPI_BASE + 0x1C) ///< SPI Data 03 +#define R_PCH_SPI_FDATA04 (R_PCH_RCRB_SPI_BASE + 0x20) ///< SPI Data 04 +#define R_PCH_SPI_FDATA05 (R_PCH_RCRB_SPI_BASE + 0x24) ///< SPI Data 05 +#define R_PCH_SPI_FDATA06 (R_PCH_RCRB_SPI_BASE + 0x28) ///< SPI Data 06 +#define R_PCH_SPI_FDATA07 (R_PCH_RCRB_SPI_BASE + 0x2C) ///< SPI Data 07 +#define R_PCH_SPI_FDATA08 (R_PCH_RCRB_SPI_BASE + 0x30) ///< SPI Data 08 +#define R_PCH_SPI_FDATA09 (R_PCH_RCRB_SPI_BASE + 0x34) ///< SPI Data 09 +#define R_PCH_SPI_FDATA10 (R_PCH_RCRB_SPI_BASE + 0x38) ///< SPI Data 10 +#define R_PCH_SPI_FDATA11 (R_PCH_RCRB_SPI_BASE + 0x3C) ///< SPI Data 11 +#define R_PCH_SPI_FDATA12 (R_PCH_RCRB_SPI_BASE + 0x40) ///< SPI Data 12 +#define R_PCH_SPI_FDATA13 (R_PCH_RCRB_SPI_BASE + 0x44) ///< SPI Data 13 +#define R_PCH_SPI_FDATA14 (R_PCH_RCRB_SPI_BASE + 0x48) ///< SPI Data 14 +#define R_PCH_SPI_FDATA15 (R_PCH_RCRB_SPI_BASE + 0x4C) ///< SPI Data 15 +#define R_PCH_SPI_FRAP (R_PCH_RCRB_SPI_BASE + 0x50) ///< SPI Flash Regions Access Permisions Register +#define B_PCH_SPI_FRAP_BMWAG_MASK 0xFF000000 ///< Master Write Access Grant MASK +#define B_PCH_SPI_FRAP_BMWAG_GBE BIT27 ///< Master write access grant for Host CPU/GbE +#define B_PCH_SPI_FRAP_BMWAG_ME BIT26 ///< Master write access grant for ME +#define B_PCH_SPI_FRAP_BMWAG_BIOS BIT25 ///< Master write access grant for Host CPU/BIOS +#define B_PCH_SPI_FRAP_BMRAG_MASK 0x00FF0000 ///< Master Write Access Grant MASK +#define B_PCH_SPI_FRAP_BMRAG_GBE BIT19 ///< Master write access grant for Host CPU/GbE +#define B_PCH_SPI_FRAP_BMRAG_ME BIT18 ///< Master write access grant for ME +#define B_PCH_SPI_FRAP_BMRAG_BIOS BIT17 ///< Master write access grant for Host CPU/BIOS +#define B_PCH_SPI_FRAP_BRWA_MASK 0x0000FF00 ///< BIOS Regsion Write Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: ... +#define B_PCH_SPI_FRAP_BRWA_GBE BIT11 ///< Region write access for Region3 GbE +#define B_PCH_SPI_FRAP_BRWA_ME BIT10 ///< Region write access for Region2 ME +#define B_PCH_SPI_FRAP_BRWA_BIOS BIT9 ///< Region write access for Region1 BIOS +#define B_PCH_SPI_FRAP_BRWA_FLASHD BIT8 ///< Region write access for Region0 Flash Descriptor +#define B_PCH_SPI_FRAP_BRRA_MASK 0x000000FF ///< BIOS Regsion Read Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: ... +#define B_PCH_SPI_FRAP_BRRA_GBE BIT3 ///< Region read access for Region3 GbE +#define B_PCH_SPI_FRAP_BRRA_ME BIT2 ///< Region read access for Region2 ME +#define B_PCH_SPI_FRAP_BRRA_BIOS BIT1 ///< Region read access for Region1 BIOS +#define B_PCH_SPI_FRAP_BRRA_FLASHD BIT0 ///< Region read access for Region0 Flash Descriptor +#define R_PCH_SPI_FREG0_FLASHD (R_PCH_RCRB_SPI_BASE + 0x54) ///< Flash Region 0(Flash Descriptor)(32bits) +#define B_PCH_SPI_FREG0_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12] +#define B_PCH_SPI_FREG0_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12] +#define R_PCH_SPI_FREG1_BIOS (R_PCH_RCRB_SPI_BASE + 0x58) ///< Flash Region 1(BIOS)(32bits) +#define B_PCH_SPI_FREG1_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12] +#define B_PCH_SPI_FREG1_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12] +#define R_PCH_SPI_FREG2_ME (R_PCH_RCRB_SPI_BASE + 0x5C) ///< Flash Region 2(ME)(32bits) +#define B_PCH_SPI_FREG2_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12] +#define B_PCH_SPI_FREG2_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12] +#define R_PCH_SPI_FREG3_GBE (R_PCH_RCRB_SPI_BASE + 0x60) ///< Flash Region 3(GbE)(32bits) +#define B_PCH_SPI_FREG3_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12] +#define B_PCH_SPI_FREG3_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12] +#define R_PCH_SPI_FREG4_PLATFORM_DATA (R_PCH_RCRB_SPI_BASE + 0x64) ///< Flash Region 4(Platform Data)(32bits) +#define B_PCH_SPI_FREG4_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12] +#define B_PCH_SPI_FREG4_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12] +#define R_PCH_SPI_PR0 (R_PCH_RCRB_SPI_BASE + 0x74) ///< Protected Region 0 Register +#define B_PCH_SPI_PR0_WPE BIT31 ///< Write Protection Enable +#define B_PCH_SPI_PR0_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask, [30:16] here represents upper limit of address [26:12] +#define B_PCH_SPI_PR0_RPE BIT15 ///< Read Protection Enable +#define B_PCH_SPI_PR0_PRB_MASK 0x00007FFF ///< Protected Range Base Mask, [14:0] here represents base limit of address [26:12] +#define R_PCH_SPI_PR1 (R_PCH_RCRB_SPI_BASE + 0x78) ///< Protected Region 1 Register +#define B_PCH_SPI_PR1_WPE BIT31 ///< Write Protection Enable +#define B_PCH_SPI_PR1_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask +#define B_PCH_SPI_PR1_RPE BIT15 ///< Read Protection Enable +#define B_PCH_SPI_PR1_PRB_MASK 0x00007FFF ///< Protected Range Base Mask +#define R_PCH_SPI_PR2 (R_PCH_RCRB_SPI_BASE + 0x7C) ///< Protected Region 2 Register +#define B_PCH_SPI_PR2_WPE BIT31 ///< Write Protection Enable +#define B_PCH_SPI_PR2_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask +#define B_PCH_SPI_PR2_RPE BIT15 ///< Read Protection Enable +#define B_PCH_SPI_PR2_PRB_MASK 0x00007FFF ///< Protected Range Base Mask +#define R_PCH_SPI_PR3 (R_PCH_RCRB_SPI_BASE + 0x80) ///< Protected Region 3 Register +#define B_PCH_SPI_PR3_WPE BIT31 ///< Write Protection Enable +#define B_PCH_SPI_PR3_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask +#define B_PCH_SPI_PR3_RPE BIT15 ///< Read Protection Enable +#define B_PCH_SPI_PR3_PRB_MASK 0x00007FFF ///< Protected Range Base Mask +#define R_PCH_SPI_PR4 (R_PCH_RCRB_SPI_BASE + 0x84) ///< Protected Region 4 Register +#define B_PCH_SPI_PR4_WPE BIT31 ///< Write Protection Enable +#define B_PCH_SPI_PR4_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask +#define B_PCH_SPI_PR4_RPE BIT15 ///< Read Protection Enable +#define B_PCH_SPI_PR4_PRB_MASK 0x00007FFF ///< Protected Range Base Mask +#define R_PCH_SPI_SSFS (R_PCH_RCRB_SPI_BASE + 0x90) ///< Software Sequencing Flash Status Register(8bits) +#define B_PCH_SPI_SSFS_FRS BIT7 ///< Fast Read Supported +#define B_PCH_SPI_SSFS_DOFRS BIT6 ///< Dual Output Fast Read Supported +#define B_PCH_SPI_SSFS_AEL BIT4 ///< Access Error Log +#define B_PCH_SPI_SSFS_FCERR BIT3 ///< Flash Cycle Error +#define B_PCH_SPI_SSFS_CDS BIT2 ///< Cycle Done Status +#define B_PCH_SPI_SSFS_SCIP BIT0 ///< SPI Cycle in Progress +#define R_PCH_SPI_SSFC (R_PCH_RCRB_SPI_BASE + 0x91) ///< Software Sequencing Flash Control(24bits) +#define B_PCH_SPI_SSFC_SCF_MASK (BIT18 | BIT17 | BIT16) ///< SPI Cycle Frequency +#define V_PCH_SPI_SSFC_SCF_20MHZ 0 ///< SPI Cycle Frequency = 20MHz +#define V_PCH_SPI_SSFC_SCF_33MHZ 1 ///< SPI Cycle Frequency = 33MHz +#define V_PCH_SPI_SSFC_SCF_50MHZ 4 ///< SPI Cycle Frequency = 50MHz +#define B_PCH_SPI_SSFC_SME BIT15 ///< SPI SMI# Enable +#define B_PCH_SPI_SSFC_DS BIT14 ///< SPI Data Cycle +#define B_PCH_SPI_SSFC_DBC_MASK 0x3F00 ///< SPI Data Byte Count (value here + 1 = count) +#define B_PCH_SPI_SSFC_COP 0x0070 ///< Cycle Opcode Pointer +#define B_PCH_SPI_SSFC_SPOP BIT3 ///< Sequence Prefix Opcode Pointer +#define B_PCH_SPI_SSFC_ACS BIT2 ///< Atomic Cycle Sequence +#define B_PCH_SPI_SSFC_SCGO BIT1 ///< SPI Cycle Go +#define R_PCH_SPI_PREOP (R_PCH_RCRB_SPI_BASE + 0x94) ///< Prefix Opcode Configuration Register(16 bits) +#define B_PCH_SPI_PREOP1_MASK 0xFF00 ///< Prefix Opcode 1 Mask +#define B_PCH_SPI_PREOP0_MASK 0x00FF ///< Prefix Opcode 0 Mask +#define R_PCH_SPI_OPTYPE (R_PCH_RCRB_SPI_BASE + 0x96) ///< Opcode Type Configuration +#define B_PCH_SPI_OPTYPE7_MASK (BIT15 | BIT14) ///< Opcode Type 7 Mask +#define B_PCH_SPI_OPTYPE6_MASK (BIT13 | BIT12) ///< Opcode Type 6 Mask +#define B_PCH_SPI_OPTYPE5_MASK (BIT11 | BIT10) ///< Opcode Type 5 Mask +#define B_PCH_SPI_OPTYPE4_MASK (BIT9 | BIT8) ///< Opcode Type 4 Mask +#define B_PCH_SPI_OPTYPE3_MASK (BIT7 | BIT6) ///< Opcode Type 3 Mask +#define B_PCH_SPI_OPTYPE2_MASK (BIT5 | BIT4) ///< Opcode Type 2 Mask +#define B_PCH_SPI_OPTYPE1_MASK (BIT3 | BIT2) ///< Opcode Type 1 Mask +#define B_PCH_SPI_OPTYPE0_MASK (BIT1 | BIT0) ///< Opcode Type 0 Mask +#define V_PCH_SPI_OPTYPE_RDNOADDR 0x00 ///< Read cycle type without address +#define V_PCH_SPI_OPTYPE_WRNOADDR 0x01 ///< Write cycle type without address +#define V_PCH_SPI_OPTYPE_RDADDR 0x02 ///< Address required; Read cycle type +#define V_PCH_SPI_OPTYPE_WRADDR 0x03 ///< Address required; Write cycle type +#define R_PCH_SPI_OPMENU (R_PCH_RCRB_SPI_BASE + 0x98) ///< Opcode Menu Configuration (64bits) +#define R_PCH_SPI_FDOC (R_PCH_RCRB_SPI_BASE + 0xB0) ///< Flash Descriptor Observability Control Register(32 bits) +#define B_PCH_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) ///< Flash Descritor Section Select +#define V_PCH_SPI_FDOC_FDSS_FSDM 0x0000 ///< Flash Signature and Descriptor Map +#define V_PCH_SPI_FDOC_FDSS_COMP 0x1000 ///< Component +#define V_PCH_SPI_FDOC_FDSS_REGN 0x2000 ///< Region +#define V_PCH_SPI_FDOC_FDSS_MSTR 0x3000 ///< Master +#define V_PCH_SPI_FDOC_FDSS_PCHS 0x4000 ///< PCH soft straps +#define V_PCH_SPI_FDOC_FDSS_SFDP 0x5000 ///< SFDP Parameter Table +#define B_PCH_SPI_FDOC_FDSI_MASK 0x0FFC ///< Flash Descriptor Section Index +#define R_PCH_SPI_FDOD (R_PCH_RCRB_SPI_BASE + 0xB4) ///< Flash Descriptor Observability Data Register(32 bits) +#define R_PCH_SPI_AFC (R_PCH_RCRB_SPI_BASE + 0xC0) ///< Additional Flash Control Register +#define B_PCH_SPI_AFC_INF_DCGE (BIT2 | BIT1) ///< Flash Controller Interface Dynamic Clock Gating Enable +#define B_PCH_SPI_AFC_CORE_DCGE BIT0 ///< Flash Core Dynamic Clock Gating Enable +#define R_PCH_SPI_VSCC0 (R_PCH_RCRB_SPI_BASE + 0xC4) ///< Vendor Specific Component Capabilities Register(32 bits) +#define B_PCH_SPI_VSCC0_CPPTV BIT31 ///< Component Property Parameter Table Valid +#define B_PCH_SPI_VSCC0_VCL BIT23 ///< Vendor Component Lock +#define B_PCH_SPI_VSCC0_EO_MASK 0x0000FF00 ///< Erase Opcode +#define B_PCH_SPI_VSCC0_WEWS BIT4 ///< Write Enable on Write Status +#define B_PCH_SPI_VSCC0_WSR BIT3 ///< Write Status Required +#define B_PCH_SPI_VSCC0_WG_64B BIT2 ///< Write Granularity, 0: 1 Byte; 1: 64 Bytes +#define B_PCH_SPI_VSCC0_BSES_MASK (BIT1 | BIT0) ///< Block/Sector Erase Size +#define V_PCH_SPI_VSCC0_BSES_256B 0x0 ///< Block/Sector Erase Size = 256 Bytes +#define V_PCH_SPI_VSCC0_BSES_4K 0x1 ///< Block/Sector Erase Size = 4K Bytes +#define V_PCH_SPI_VSCC0_BSES_8K 0x2 ///< Block/Sector Erase Szie = 8K Bytes +#define V_PCH_SPI_VSCC0_BSES_64K 0x3 ///< Block/Sector Erase Size = 64K Bytes +#define R_PCH_SPI_VSCC1 (R_PCH_RCRB_SPI_BASE + 0xC8) ///< Vendor Specific Component Capabilities Register(32 bits) +#define B_PCH_SPI_VSCC1_CPPTV BIT31 ///< Component Property Parameter Table Valid +#define B_PCH_SPI_VSCC1_EO_MASK 0x0000FF00 ///< Erase Opcode +#define B_PCH_SPI_VSCC1_WEWS BIT4 ///< Write Enable on Write Status +#define B_PCH_SPI_VSCC1_WSR BIT3 ///< Write Status Required +#define B_PCH_SPI_VSCC1_WG_64B BIT2 ///< Write Granularity, 0: 1 Byte; 1: 64 Bytes +#define B_PCH_SPI_VSCC1_BSES_MASK (BIT1 | BIT0) ///< Block/Sector Erase Size +#define V_PCH_SPI_VSCC1_BSES_256B 0x0 ///< Block/Sector Erase Size = 256 Bytes +#define V_PCH_SPI_VSCC1_BSES_4K 0x1 ///< Block/Sector Erase Size = 4K Bytes +#define V_PCH_SPI_VSCC1_BSES_8K 0x2 ///< Block/Sector Erase Size = 8K Bytes +#define V_PCH_SPI_VSCC1_BSES_64K 0x3 ///< Block/Sector Erase Size = 64K Bytes +#define R_PCH_SPI_PINTX (R_PCH_RCRB_SPI_BASE + 0xCC) ///< Parameter Table Index +#define N_PCH_SPI_PINTX_SPT 14 +#define V_PCH_SPI_PINTX_SPT_CPT0 0x0 ///< Component 0 Property Parameter Table +#define V_PCH_SPI_PINTX_SPT_CPT1 0x1 ///< Component 1 Property Parameter Table +#define N_PCH_SPI_PINTX_HORD 12 +#define V_PCH_SPI_PINTX_HORD_SFDP 0x0 ///< SFDP Header +#define V_PCH_SPI_PINTX_HORD_PT 0x1 ///< Parameter Table Header +#define V_PCH_SPI_PINTX_HORD_DATA 0x2 ///< Data +#define R_PCH_SPI_PTDATA (R_PCH_RCRB_SPI_BASE + 0xD0) ///< Parameter Table Data +#define R_PCH_SPI_SRDL (R_PCH_RCRB_SPI_BASE + 0xF0) ///< Soft Reset Data Lock +#define B_PCH_SPI_SRDL_SSL BIT0 ///< Set_Stap Lock +#define R_PCH_SPI_SRDC (R_PCH_RCRB_SPI_BASE + 0xF4) ///< Soft Reset Data Control +#define B_PCH_SPI_SRDC_SRDS BIT0 ///< Soft Reset Data Select +#define R_PCH_SPI_SRD (R_PCH_RCRB_SPI_BASE + 0xF8) ///< Soft Reset Data +// +// @todo Follow up with EDS owner if it should be 3FFF or FFFF. +// +#define B_PCH_SPI_SRD_SSD 0x0000FFFF ///< Set_Stap Data +// +// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0 +// +#define R_PCH_SPI_FDBAR_FLVALSIG 0x00 ///< Flash Valid Signature +#define V_PCH_SPI_FDBAR_FLVALSIG 0x0FF0A55A +#define R_PCH_SPI_FDBAR_FLASH_MAP0 0x04 +#define B_PCH_SPI_FDBAR_FCBA 0x000000FF ///< Flash Component Base Address +#define B_PCH_SPI_FDBAR_NC 0x00000300 ///< Number Of Components +#define N_PCH_SPI_FDBAR_NC 0x08 ///< Number Of Components +#define V_PCH_SPI_FDBAR_NC_1 0x00000000 +#define V_PCH_SPI_FDBAR_NC_2 0x00000100 +#define B_PCH_SPI_FDBAR_FRBA 0x00FF0000 ///< Flash Region Base Address +#define B_PCH_SPI_FDBAR_NR 0x07000000 ///< Number Of Regions +#define R_PCH_SPI_FDBAR_FLASH_MAP1 0x08 +#define B_PCH_SPI_FDBAR_FMBA 0x000000FF ///< Flash Master Base Address +#define B_PCH_SPI_FDBAR_NM 0x00000700 ///< Number Of Masters +#define B_PCH_SPI_FDBAR_FPCHSBA 0x00FF0000 ///< Flash PCH Strap Base Address +#define B_PCH_SPI_FDBAR_PCHSL 0xFF000000 ///< PCH Strap Length +#define R_PCH_SPI_FDBAR_FLASH_MAP2 0x0C +#define B_PCH_SPI_FDBAR_FPROSBA 0x000000FF ///< Flash Processor Strap Base Address +#define B_PCH_SPI_FDBAR_PROSL 0x0000FF00 ///< PROC Strap Length +// +// Flash Component Base Address (FCBA) from Flash Region 0 +// +#define R_PCH_SPI_FCBA_FLCOMP 0x00 ///< Flash Components Register +#define B_PCH_SPI_FLCOMP_RIDS_FREQ (BIT29 | BIT28 | BIT27) ///< Read ID and Read Status Clock Frequency +#define B_PCH_SPI_FLCOMP_WE_FREQ (BIT26 | BIT25 | BIT24) ///< Write and Erase Clock Frequency +#define B_PCH_SPI_FLCOMP_FRCF_FREQ (BIT23 | BIT22 | BIT21) ///< Fast Read Clock Frequency +#define B_PCH_SPI_FLCOMP_FR_SUP BIT20 ///< Fast Read Support. +#define B_PCH_SPI_FLCOMP_RC_FREQ (BIT19 | BIT18 | BIT17) ///< Read Clock Frequency. +#define V_PCH_SPI_FLCOMP_FREQ_20MHZ 0x00 +#define V_PCH_SPI_FLCOMP_FREQ_33MHZ 0x01 +#define V_PCH_SPI_FLCOMP_FREQ_50MHZ 0x04 +#define B_PCH_SPI_FLCOMP_COMP2_MASK 0xF0 ///< Flash Component 2 Size MASK +#define V_PCH_SPI_FLCOMP_COMP2_512KB 0x00 +#define V_PCH_SPI_FLCOMP_COMP2_1MB 0x10 +#define V_PCH_SPI_FLCOMP_COMP2_2MB 0x20 +#define V_PCH_SPI_FLCOMP_COMP2_4MB 0x30 +#define V_PCH_SPI_FLCOMP_COMP2_8MB 0x40 +#define V_PCH_SPI_FLCOMP_COMP2_16MB 0x50 +#define V_PCH_SPI_FLCOMP_COMP2_32MB 0x60 +#define V_PCH_SPI_FLCOMP_COMP2_64MB 0x70 +#define B_PCH_SPI_FLCOMP_COMP1_MASK 0x0F ///< Flash Component 1 Size MASK +#define V_PCH_SPI_FLCOMP_COMP1_512KB 0x00 +#define V_PCH_SPI_FLCOMP_COMP1_1MB 0x01 +#define V_PCH_SPI_FLCOMP_COMP1_2MB 0x02 +#define V_PCH_SPI_FLCOMP_COMP1_4MB 0x03 +#define V_PCH_SPI_FLCOMP_COMP1_8MB 0x04 +#define V_PCH_SPI_FLCOMP_COMP1_16MB 0x05 +#define V_PCH_SPI_FLCOMP_COMP1_32MB 0x06 +#define V_PCH_SPI_FLCOMP_COMP1_64MB 0x07 +#define V_PCH_SPI_FLCOMP_COMP_512KB 0x80000 +// +// Descriptor Upper Map Section from Flash Region 0 +// +#define R_PCH_SPI_FLASH_UMAP1 0xEFC ///< Flash Upper Map 1 +#define B_PCH_SPI_FLASH_UMAP1_VTBA 0x000000FF ///< VSCC Table Base Address +#define B_PCH_SPI_FLASH_UMAP1_VTL 0x0000FF00 ///< VSCC Table Length + +#define R_PCH_SPI_VTBA_JID0 0x00 ///< JEDEC-ID 0 Register +#define S_PCH_SPI_VTBA_JID0 0x04 +#define B_PCH_SPI_VTBA_JID0_VID 0x000000FF +#define B_PCH_SPI_VTBA_JID0_DID0 0x0000FF00 +#define B_PCH_SPI_VTBA_JID0_DID1 0x00FF0000 +#define N_PCH_SPI_VTBA_JID0_DID0 0x08 +#define N_PCH_SPI_VTBA_JID0_DID1 0x10 +#define R_PCH_SPI_VTBA_VSCC0 0x04 +#define S_PCH_SPI_VTBA_VSCC0 0x04 +#define R_PCH_SPI_STRP0 0x0 ///< PCH soft strap 0 +#define B_PCH_SPI_STRP0_BBBS (BIT31 |BIT30 | BIT29) ///< BIOS Boot-Block size +#define B_PCH_SPI_STRP0_BBBS_64KB 0x00 +#define B_PCH_SPI_STRP0_BBBS_128KB BIT29 +#define B_PCH_SPI_STRP0_BBBS_256KB BIT30 +#define B_PCH_SPI_STRP0_BBBS_512KB (BIT30 | BIT29) +#define B_PCH_SPI_STRP0_BBBS_1MB BIT31 +#define B_PCH_SPI_STRP0_DMI_REQID_DIS BIT24 ///< DMI RequesterID Check Disable +#define B_PCH_SPI_STRP0_CFG_STRP1 BIT21 ///< Chipset configuration Softstrap 1 +#define B_PCH_SPI_STRP0_LAN_GP12_SEL BIT20 ///< LAN PHY Power Control GPIO12 Select +#define B_PCH_SPI_STRP0_SML0FRQ (BIT15 | BIT14) ///< SMLink0 Frequency +#define B_PCH_SPI_STRP0_SMB0FRQ (BIT13 | BIT12) ///< Intel ME SMBus Frequency +#define B_PCH_SPI_STRP0_SML1FRQ (BIT11 | BIT10) ///< SMLink1 Frequency +#define B_PCH_SPI_STRP0_SML1_EN BIT9 ///< SMLink1 Enable +#define B_PCH_SPI_STRP0_SML0_EN BIT8 ///< SMLink0 Enable +#define B_PCH_SPI_STRP0_SMB_EN BIT7 ///< Intel ME SMBus Select +#define B_PCH_SPI_STRP0_CFG_STRP2 BIT1 ///< Chipset configuration Softstrap 2 +#define R_PCH_SPI_STRP1 0x04 ///< PCH soft strap 1 +#define B_PCH_SPI_STRP1_CFG_STRP3 0x0F ///< Chipset configuration Softstrap 3 +#define R_PCH_SPI_STRP2 0x08 ///< PCH soft strap 2 +#define B_PCH_SPI_STRP2_MESMA 0xFE000000 ///< ME SMBus Address +#define B_PCH_SPI_STRP2_MESMI2CEN BIT24 ///< ME SMBus Address Enable +#define B_PCH_SPI_STRP2_MESMASDA 0xFE00 ///< ME SMBus Alert Sending Device Address +#define B_PCH_SPI_STRP2_MESMASDEN BIT8 ///< ME SMBus Alert Sending Device Address Enable +#define R_PCH_SPI_STRP3 0x0C ///< PCH soft strap 3 +#define R_PCH_SPI_STRP4 0x10 ///< PCH soft strap 4 +#define B_PCH_SPI_STRP4_GBEPHYSMA 0xFE0000 ///< GbE PHY SMBus Address +#define B_PCH_SPI_STRP4_GBEMACSMA 0xFE00 ///< GbE MAC SMBus Address +#define B_PCH_SPI_STRP4_GBEMACSMAEN BIT8 ///< Gbe MAC SMBus Address Enable +#define B_PCH_SPI_STRP4_PHYCON (BIT1 | BIT0) ///< Intel PHY Connectivity +#define B_PCH_SPI_STRP4_NO_PHYCON 0x00 +#define B_PCH_SPI_STRP4_PHY_ON 0x02 +#define R_PCH_SPI_STRP5 0x14 ///< PCH soft strap 5 +#define R_PCH_SPI_STRP6 0x18 ///< PCH soft strap 6 +#define R_PCH_SPI_STRP7 0x1C ///< PCH soft strap 7 +#define B_PCH_SPI_STRP7_MESMASVID 0xFFFFFFFF ///< ME SMBus Subsystem Vendor and Device ID +#define R_PCH_SPI_STRP8 0x20 ///< PCH soft strap 8 +#define R_PCH_SPI_STRP9 0x24 ///< PCH soft strap 9 +#define B_PCH_SPI_STRP9_HOT_SML1_SEL BIT22 ///< PCHHOT# or SML1AlERT# Select (0:SML1ALERT#; 1:PCHHOT#) +#define B_PCH_SPI_STRP9_PCIE_SBDE_EN BIT14 ///< Subtractive Decode over PCI Express Enabling +#define N_PCH_SPI_STRP9_PCIE_SBDE_EN 14 +#define B_PCH_SPI_STRP9_GBE_PCIE_EN BIT11 ///< GbE over PCI Express Enabling +#define B_PCH_SPI_STRP9_GBE_PCIE_PSC (BIT8 | BIT9 | BIT10) ///< GbE PCI E Port Select +#define N_PCH_SPI_STRP9_GBE_PCIE_PSC 8 +#define B_PCH_SPI_STRP9_DMILR BIT6 ///< DMI Lane Reversal +#define B_PCH_SPI_STRP9_PCIELR2 BIT5 ///< PCIe Lane Reversal 2 +#define B_PCH_SPI_STRP9_PCIELR1 BIT4 ///< PCIe Lane Reversal 1 +#define B_PCH_SPI_STRP9_PCIEPCS2 BIT3 | BIT2 ///< PCI Express Port Configuration Strap 2 +#define B_PCH_SPI_STRP9_PCIEPCS1 BIT1 | BIT0 ///< PCI Express Port Configuration Strap 1 +#define V_PCH_SPI_STRP9_PCIEPCS_1x4 0x03 ///< 1x4 Port 1/5 (x4), Ports 2-4/6-8 (disabled) +#define V_PCH_SPI_STRP9_PCIEPCS_2x2 0x02 ///< 2x2 Port 1/5 (x2), Port 3/7 (x2), Ports 2,4/6,8 (disabled) +#define V_PCH_SPI_STRP9_PCIEPCS_1x2 0x01 ///< 1x2, 2x1 Port 1/5 (x2), Port 2/6 (disabled), Ports 3,4/7,8 (x1) +#define V_PCH_SPI_STRP9_PCIEPCS_4x1 0x00 ///< 4x1 Ports 1-4/5-8 (x1) +#define R_PCH_SPI_STRP10 0x28 ///< PCH soft strap 10 +#define B_PCH_SPI_STRP10_MER_CL1 BIT21 ///< ME Reset Capture on CL_RST1 +#define B_PCH_SPI_STRP10_ICC_SEL 0x1C0000 ///< Integrated Clocking Configuration Select +#define B_PCH_SPI_STRP10_CFG_STRP7 BIT16 ///< Chipset Configuration Softstrap 7 +#define B_PCH_SPI_STRP10_MMADDR 0xFE00 ///< ME Memory-attached Debug Display Device Address +#define B_PCH_SPI_STRP10_MMDDE BIT8 ///< ME Memory-attached Debug Display Device Enable +#define B_PCH_SPI_STRP10_VE_EN BIT3 ///< 0 - VE disabled; 1 - VE enabled +#define B_PCH_SPI_STRP10_CFG_STRP5 BIT2 ///< Chipset Configuration Softstrap 5 +#define B_PCH_SPI_STRP10_ME_BFlash BIT1 ///< ME from Boot Flash +#define R_PCH_SPI_STRP11 0x2C ///< PCH soft strap 11 +#define B_PCH_SPI_STRP11_SML1I2CA 0xFE000000 ///< SMLink1 I2C Target Address +#define B_PCH_SPI_STRP11_SML1I2CAEN BIT24 ///< SMLink1 I2C Target Address Enable +#define B_PCH_SPI_STRP11_SML1GPA 0xE ///< SMLink1 GP Address +#define B_PCH_SPI_STRP11_SML1GPAEN BIT0 ///< SMLink1 GP Address Enable +#define R_PCH_SPI_STRP12 0x30 +#define R_PCH_SPI_STRP13 0x34 +#define R_PCH_SPI_STRP14 0x38 +#define R_PCH_SPI_STRP15 0x3C +#define R_PCH_SPI_STRP15_SML1_THRMSEL BIT14 ///< SMLink1 Thermal Reporting Select +#define B_PCH_SPI_STRP15_T209MIN (BIT9 | BIT8) ///< T209 min Timing +#define B_PCH_SPI_STRP15_IWL_EN BIT6 ///< Intel integrated wired LAN Enable +#define B_PCH_SPI_STRP15_CFG_STRP6 (BIT4 | BIT3) ///< Chipset Configuration Softstrap 6 +#define R_PCH_SPI_STRP17 0x44 ///< PCH Soft strap 17 +#define B_PCH_SPI_STRP17_CLK_MODE BIT0 ///< Integrated Clock mode select +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsThermal.h b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsThermal.h new file mode 100644 index 0000000..b94d1ed --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsThermal.h @@ -0,0 +1,100 @@ +/** @file + Register names for PCH Thermal Device + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_LPT_" + - Registers / bits that are different between SKUs are denoted by "_<SKU_name>" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without <generation_name> inserted. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _PCH_REGS_THERMAL_H_ +#define _PCH_REGS_THERMAL_H_ + +// +// Thermal Device Registers (D31:F6) +// +#define PCI_DEVICE_NUMBER_PCH_THERMAL 31 +#define PCI_FUNCTION_NUMBER_PCH_THERMAL 6 +#define R_PCH_THERMAL_VENDOR_ID 0x00 +#define V_PCH_THERMAL_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_THERMAL_DEVICE_ID 0x02 +#define V_PCH_LPTH_THERMAL_DEVICE_ID 0x8C24 +#define V_PCH_LPTLP_THERMAL_DEVICE_ID 0x9C24 +#define R_PCH_THERMAL_COMMAND 0x04 +#define B_PCH_THERMAL_COMMAND_MSE BIT1 +#define B_PCH_THERMAL_COMMAND_BME BIT2 +#define R_PCH_THERMAL_TBAR 0x10 +#define V_PCH_THERMAL_TBAR_SIZE (4 * 1024) +#define N_PCH_THREMAL_TBAR_ALIGNMENT 12 +#define B_PCH_THERMAL_TBAR_MASK 0xFFFFF000 +#define R_PCH_THERMAL_TBARH 0x14 +#define R_PCH_THERMAL_SVID 0x2C +#define R_PCH_THERMAL_INTLN 0x3C +#define R_PCH_THERMAL_TBARB 0x40 +#define V_PCH_THERMAL_TBARB_SIZE (4 * 1024) +#define N_PCH_THREMAL_TBARB_ALIGNMENT 12 +#define B_PCH_THERMAL_SPTYPEN BIT0 +#define R_PCH_THERMAL_TBARBH 0x44 +#define B_PCH_THERMAL_TBARB_MASK 0xFFFFF000 + +#define R_PCH_TBARB_TSC 0x04 +#define B_PCH_TBARB_TSC_PLD BIT7 +#define B_PCH_TBARB_TSC_CPDE BIT0 +#define R_PCH_TBARB_TSS 0x06 +#define R_PCH_TBARB_TSEL 0x08 +#define B_PCH_TBARB_TSEL_PLD BIT7 +#define B_PCH_TBARB_TSEL_ETS BIT0 +#define R_PCH_TBARB_TSREL 0x0A +#define R_PCH_TBARB_TSMIC 0x0C +#define B_PCH_TBARB_TSMIC_PLD BIT7 +#define B_PCH_TBARB_TSMIC_SMIE BIT0 +#define R_PCH_TBARB_CTT 0x10 +#define V_PCH_TBARB_CTT_LPTH 0x154 +#define V_PCH_TBARB_CTT_LPTLP 0x14A +#define R_PCH_TBARB_TAHV 0x14 +#define R_PCH_TBARB_TALV 0x18 +#define R_PCH_TBARB_TSPM 0x1C +#define B_PCH_TBARB_TSPM_LTT (BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0) +#define V_PCH_TBARB_TSPM_LTT 0x0C8 +#define B_PCH_TBARB_TSPM_MAXTSST (BIT11 | BIT10 | BIT9) +#define V_PCH_TBARB_TSPM_MAXTSST (0x4 << 9) +#define B_PCH_TBARB_TSPM_MINTSST BIT12 +#define B_PCH_TBARB_TSPM_DTSSIC0 BIT13 +#define B_PCH_TBARB_TSPM_DTSSS0EN BIT14 +#define B_PCH_TBARB_TSPM_TSPMLOCK BIT15 +#define R_PCH_TBARB_TL 0x40 +#define B_PCH_TBARB_TL_LOCK BIT31 +#define R_PCH_TBARB_PHL 0x60 +#define B_PCH_TBARB_PHLE BIT15 +#define R_PCH_TBARB_PHLC 0x62 +#define R_PCH_TBARB_TAS 0x80 +#define R_PCH_TBARB_TSPIEN 0x82 +#define R_PCH_TBARB_TSGPEN 0x84 +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsUsb.h b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsUsb.h new file mode 100644 index 0000000..12eaa9d --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/Include/PchRegs/PchRegsUsb.h @@ -0,0 +1,563 @@ +/** @file + Register names for PCH USB devices + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values of bits within the registers + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denoted by + "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_LPT_" + - Registers / bits that are different between SKUs are denoted by "_<SKU_name>" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be just named + as "_PCH_" without <generation_name> inserted. + +@copyright + Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _PCH_REGS_USB_H_ +#define _PCH_REGS_USB_H_ + +// +// USB Definitions +// +#define LPTH_USB_MAX_PHYSICAL_PORTS 14 ///< Max Physical Connector EHCI + XHCI, not counting virtual ports like USB-R. +#define LPTH_EHCI_MAX_CONTROLLERS 2 ///< Max EHCI Controllers +#define LPTH_EHCI_MAX_PORTS 14 ///< Counting ports behind RMHs 8 from EHCI-1 and 6 from EHCI-2, not counting EHCI USB-R virtual ports. +#define LPTH_XHCI_MAX_USB2_PORTS 15 ///< 14 High Speed lanes + Including one port reserved for USBr +#define LPTH_XHCI_MAX_USB3_PORTS 6 ///< 6 Super Speed lanes +#define LPTLP_USB_MAX_PHYSICAL_PORTS 8 ///< Max Physical Connector EHCI + XHCI, not counting virtual ports like USB-R. +#define LPTLP_EHCI_MAX_PORTS 8 ///< Counting ports behind RMHs 8 from EHCI-1 and 6 from EHCI-2, not counting EHCI USB-R virtual ports. +#define LPTLP_EHCI_MAX_CONTROLLERS 1 ///< Max EHCI Controllers +#define LPTLP_XHCI_MAX_USB2_PORTS 9 ///< 8 High Speed lanes + Including one port reserved for USBr +#define LPTLP_XHCI_MAX_USB3_PORTS 4 ///< 4 Super Speed lanes + +#define R_PCH_USB_VENDOR_ID 0x00 +#define V_PCH_USB_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_USB_DEVICE_ID 0x02 +#define V_PCH_LPTH_USB_DEVICE_ID_EHCI_1 0x8C26 ///< LPT EHCI#1 +#define V_PCH_LPTH_USB_DEVICE_ID_EHCI_2 0x8C2D ///< LPT EHCI#2 +#define V_PCH_LPTH_USB_DEVICE_ID_XHCI_1 0x8C31 ///< LPT XHCI#1 +#define V_PCH_LPTLP_USB_DEVICE_ID_EHCI_1 0x9C26 ///< LPTLP EHCI#1 +#define V_PCH_LPTLP_USB_DEVICE_ID_XHCI_1 0x9C31 ///< LPTLP XHCI#1 + +// +// USB2 (EHCI) related definitions +// +typedef enum { + PchEhci1 = 0, + PchEhci2, + PchEhciControllerMax +} PCH_USB20_CONTROLLER_TYPE; + +#define PCI_DEVICE_NUMBER_PCH_USB 29 +#define PCI_FUNCTION_NUMBER_PCH_EHCI 0 + +#define PCI_DEVICE_NUMBER_PCH_USB_EXT 26 +#define PCI_FUNCTION_NUMBER_PCH_EHCI2 0 + +// +// EHCI PCI Config Space registers +// +#define R_PCH_EHCI_COMMAND_REGISTER 0x04 +#define B_PCH_EHCI_COMMAND_INTR_DIS BIT10 +#define B_PCH_EHCI_COMMAND_FBE BIT9 +#define B_PCH_EHCI_COMMAND_SERR_EN BIT8 +#define B_PCH_EHCI_COMMAND_WCC BIT7 +#define B_PCH_EHCI_COMMAND_PER BIT6 +#define B_PCH_EHCI_COMMAND_VPS BIT5 +#define B_PCH_EHCI_COMMAND_PMWE BIT4 +#define B_PCH_EHCI_COMMAND_SCE BIT3 +#define B_PCH_EHCI_COMMAND_BME BIT2 +#define B_PCH_EHCI_COMMAND_MSE BIT1 +#define B_PCH_EHCI_COMMAND_IOSE BIT0 + +#define R_PCH_EHCI_PCISTS 0x06 +#define B_PCH_EHCI_PCISTS_DPE BIT15 +#define B_PCH_EHCI_PCISTS_SSE BIT14 +#define B_PCH_EHCI_PCISTS_RMA BIT13 +#define B_PCH_EHCI_PCISTS_RTA BIT12 +#define B_PCH_EHCI_PCISTS_STA BIT11 +#define B_PCH_EHCI_PCISTS_DEV_STS (BIT10 | BIT9) +#define B_PCH_EHCI_PCISTS_DPED BIT8 +#define B_PCH_EHCI_PCISTS_FB2BC BIT7 +#define B_PCH_EHCI_PCISTS_UDF BIT6 +#define B_PCH_EHCI_PCISTS_66MHZ_CAP BIT5 +#define B_PCH_EHCI_PCISTS_CAP_LST BIT4 +#define B_PCH_EHCI_PCISTS_INTR_STS BIT3 + +#define R_PCH_EHCI_RID 0x08 +#define B_PCH_EHCI_RID 0xFF +#define R_PCH_EHCI_PI 0x09 +#define B_PCH_EHCI_PI 0xFF +#define R_PCH_EHCI_SCC 0x0A +#define B_PCH_EHCI_SCC 0xFF +#define R_PCH_EHCI_BCC 0x0B +#define B_PCH_EHCI_BCC 0xFF +#define R_PCH_EHCI_MLT 0x0D +#define B_PCH_EHCI_MLT 0xFF +#define R_PCH_EHCI_HEADTYPE 0x0E +#define B_PCH_EHCI_HEADTYPE 0xFF +#define R_PCH_EHCI_MEM_BASE 0x10 +#define V_PCH_EHCI_MEM_LENGTH 0x400 +#define N_PCH_EHCI_MEM_ALIGN 10 +#define R_PCH_EHCI_SVID 0x2C +#define B_PCH_EHCI_SVID 0xFFFF +#define R_PCH_EHCI_SID 0x2E +#define B_PCH_EHCI_SID 0xFFFF +#define R_PCH_EHCI_CAP_PTR 0x34 +#define B_PCH_EHCI_CAP_PTR 0xFF +#define R_PCH_EHCI_INT_LN 0x3C +#define B_PCH_EHCI_INT_LN 0xFF +#define R_PCH_EHCI_INT_PN 0x3D +#define B_PCH_EHCI_INT_PN 0xFF +#define R_PCH_EHCI_IHFCLK 0x44 +#define B_PCH_EHCI_IHFCLK 0xFFFFFFFF +#define R_PCH_EHCI_IHFCLKC 0x48 +#define B_PCH_EHCI_IHFCLKC 0xFFFFFFFF +#define R_PCH_EHCI_PWR_CAPID 0x50 +#define B_PCH_EHCI_PWR_CAPID 0xFF +#define R_PCH_EHCI_NXT_PTR1 0x51 +#define B_PCH_EHCI_NXT_PTR1 0xFF +#define R_PCH_EHCI_PWR_CAP 0x52 +#define B_PCH_EHCI_PWR_CAP_PME_SUP 0xF800 +#define B_PCH_EHCI_PWR_CAP_D2_SUP BIT10 +#define B_PCH_EHCI_PWR_CAP_D1_SUP BIT9 +#define B_PCH_EHCI_PWR_CAP_AUX_CUR (BIT8 | BIT7 | BIT6) +#define B_PCH_EHCI_PWR_CAP_DSI BIT5 +#define B_PCH_EHCI_PWR_CAP_PME_CLK BIT3 +#define B_PCH_EHCI_PWR_CAP_VER (BIT2 | BIT1 | BIT0) +#define R_PCH_EHCI_PWR_CNTL_STS 0x54 +#define B_PCH_EHCI_PWR_CNTL_STS_PME_STS BIT15 +#define B_PCH_EHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13) +#define B_PCH_EHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9) +#define B_PCH_EHCI_PWR_CNTL_STS_PME_EN BIT8 +#define B_PCH_EHCI_PWR_CNTL_STS_NO_SOFT_RESET BIT3 +#define B_PCH_EHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0) +#define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0) +#define R_PCH_EHCI_DBG_CAPID 0x58 +#define B_PCH_EHCI_DBG_CAPID 0xFF +#define R_PCH_EHCI_NXT_PTR2 0x59 +#define B_PCH_EHCI_NXT_PTR2 0xFF +#define R_PCH_EHCI_DBG_BASE 0x5A +#define B_PCH_EHCI_DBG_BASE_BAR_NUM 0xE000 +#define B_PCH_EHCI_DBG_BASE_PORT_OFFSET 0x1FFF +#define R_PCH_EHCI_USB_RELNUM 0x60 +#define B_PCH_EHCI_USB_RELNUM 0xFF +#define R_PCH_EHCI_FL_ADJ 0x61 +#define B_PCH_EHCI_FL_ADJ 0x3F +#define R_PCH_EHCI_PWAKE_CAP 0x62 +#define B_PCH_EHCI_PWAKE_CAP_D29_MASK 0x01FE +#define B_PCH_EHCI_PWAKE_CAP_D26_MASK 0x007E +#define B_PCH_EHCI_PWAKE_CAP_PWK_IMP BIT0 +#define R_PCH_EHCI_PDO 0x64 +#define B_PCH_EHCI_PDO_DIS_PORT0 BIT0 +#define B_PCH_EHCI_PDO_D29_MASK 0xFF +#define B_PCH_EHCI_PDO_D26_MASK 0x3F +#define R_PCH_EHCI_RMHDEVR 0x66 +#define B_PCH_EHCI_RMHDEVR_D29_MASK 0x01FE +#define B_PCH_EHCI_RMHDEVR_D26_MASK 0x007E +#define R_PCH_EHCI_LEGEXT_CAP 0x68 +#define B_PCH_EHCI_LEGEXT_CAP_HCOS BIT24 +#define B_PCH_EHCI_LEGEXT_CAP_HCBIOS BIT16 +#define B_PCH_EHCI_LEGEXT_CAP_NEXT 0x0000FF00 +#define B_PCH_EHCI_LEGEXT_CAP_CAPID 0x000000FF +#define R_PCH_EHCI_LEGEXT_CS 0x6C +#define B_PCH_EHCI_LEGEXT_CS_SMIBAR BIT31 +#define B_PCH_EHCI_LEGEXT_CS_SMIPCI BIT30 +#define B_PCH_EHCI_LEGEXT_CS_SMIOS BIT29 +#define B_PCH_EHCI_LEGEXT_CS_SMIAA BIT21 +#define B_PCH_EHCI_LEGEXT_CS_SMIHSE BIT20 +#define B_PCH_EHCI_LEGEXT_CS_SMIFLR BIT19 +#define B_PCH_EHCI_LEGEXT_CS_SMIPCD BIT18 +#define B_PCH_EHCI_LEGEXT_CS_SMIERR BIT17 +#define B_PCH_EHCI_LEGEXT_CS_SMICOMP BIT16 +#define B_PCH_EHCI_LEGEXT_CS_SMIBAR_EN BIT15 +#define B_PCH_EHCI_LEGEXT_CS_SMIPCI_EN BIT14 +#define B_PCH_EHCI_LEGEXT_CS_SMIOS_EN BIT13 +#define B_PCH_EHCI_LEGEXT_CS_SMIAA_EN BIT5 +#define B_PCH_EHCI_LEGEXT_CS_SMIHSE_EN BIT4 +#define B_PCH_EHCI_LEGEXT_CS_SMIFLR_EN BIT3 +#define B_PCH_EHCI_LEGEXT_CS_SMIPCD_EN BIT2 +#define B_PCH_EHCI_LEGEXT_CS_SMIERR_EN BIT1 +#define B_PCH_EHCI_LEGEXT_CS_SMICOMP_EN BIT0 +#define R_PCH_EHCI_SPCSMI 0x70 +#define B_PCH_EHCI_SPCSMI_D29 0x3FC00000 +#define B_PCH_EHCI_SPCSMI_D26 0x0FC00000 +#define B_PCH_EHCI_SPCSMI_PMCSR BIT21 +#define B_PCH_EHCI_SPCSMI_ASYNC BIT20 +#define B_PCH_EHCI_SPCSMI_PERIODIC BIT19 +#define B_PCH_EHCI_SPCSMI_CF BIT18 +#define B_PCH_EHCI_SPCSMI_HCHALT BIT17 +#define B_PCH_EHCI_SPCSMI_HCRESET BIT16 +#define B_PCH_EHCI_SPCSMI_PO_EN 0x00003FC0 +#define B_PCH_EHCI_SPCSMI_PMCSR_EN BIT5 +#define B_PCH_EHCI_SPCSMI_ASYNC_EN BIT4 +#define B_PCH_EHCI_SPCSMI_PERIODIC_EN BIT3 +#define B_PCH_EHCI_SPCSMI_CF_EN BIT2 +#define B_PCH_EHCI_SPCSMI_HCHALT_EN BIT1 +#define B_PCH_EHCI_SPCSMI_HCRESET_EN BIT0 +#define R_PCH_EHCI_OCMAP 0x74 +#define R_PCH_EHCI_RMHWKCTL 0x7E +#define R_PCH_EHCI_ACCESS_CNTL 0x80 +#define B_PCH_EHCI_ACCESS_CNTL_ENABLE BIT0 +#define V_PCH_EHCI_ACCESS_CNTL_ENABLE 0x01 +#define R_PCH_EHCI_FLR_CID 0x98 +#define B_PCH_EHCI_FLR_CID 0xFF +#define V_PCH_EHCI_FLR_CID_13 0x13 +#define V_PCH_EHCI_FLR_CID_09 0x09 +#define R_PCH_EHCI_FLR_NEXT 0x99 +#define B_PCH_EHCI_FLR_NEXT 0xFF +#define R_PCH_EHCI_FLR_CLV 0x9A +#define B_PCH_EHCI_FLR_CLV_CAP_SSEL0 BIT9 +#define B_PCH_EHCI_FLR_CLV_TXP_SSEL0 BIT8 +#define B_PCH_EHCI_FLR_CLV_VSCID_SSEL1 0xF000 +#define B_PCH_EHCI_FLR_CLV_CAPVER_SSEL1 0x0F00 +#define B_PCH_EHCI_FLR_CLV_LNG 0x00FF +#define R_PCH_EHCI_FLR_CTRL 0x9C +#define B_PCH_EHCI_FLR_CTRL_INITFLR BIT0 +#define R_PCH_EHCI_FLR_STS 0x9D +#define B_PCH_EHCI_FLR_STS_TXP BIT0 + +// +// EHCI MMIO registers +// +#define R_PCH_EHCI_HCSPARAMS 0x04 +#define N_PCH_EHCI_HCSPARAMS_DP_N 20 +#define N_PCH_EHCI_HCSPARAMS_N_CC 12 +#define N_PCH_EHCI_HCSPARAMS_N_PCC 8 +#define N_PCH_EHCI_HCSPARAMS_N_PORTS 0 +#define R_PCH_EHCI_USB2CMD 0x20 +#define B_PCH_EHCI_USB2CMD_ASE BIT5 +#define B_PCH_EHCI_USB2CMD_PSE BIT4 +#define B_PCH_EHCI_USB2CMD_HCRESET BIT1 +#define B_PCH_EHCI_USB2CMD_RS BIT0 +#define R_PCH_EHCI_USB2STS 0x24 +#define B_PCH_EHCI_USB2STS_HCHALTED BIT12 +#define R_PCH_EHCI_CONFIGFLAG 0x60 +#define R_PCH_EHCI_PORTSC0 0x64 +#define R_PCH_EHCI_PORTSC0_SUSPEND BIT7 +#define R_PCH_EHCI_PORTSC0_PORT_EN_DIS BIT2 +#define B_PCH_EHCI_PORTSC0_CHANGE_ENABLE_MASK (0x2A | R_PCH_EHCI_PORTSC0_PORT_EN_DIS) ///< Mask all change bits and port enabled +#define B_PCH_EHCI_PORTSC0_RESET BIT8 + +// +// USB3 (XHCI) related definitions +// +#define PCI_DEVICE_NUMBER_PCH_XHCI 20 +#define PCI_FUNCTION_NUMBER_PCH_XHCI 0 + +// +// XHCI PCI Config Space registers +// +#define R_PCH_XHCI_COMMAND_REGISTER 0x04 +#define B_PCH_XHCI_COMMAND_BME BIT2 +#define B_PCH_XHCI_COMMAND_MSE BIT1 +#define R_PCH_XHCI_MEM_BASE 0x10 +#define V_PCH_XHCI_MEM_LENGTH 0x3000 +#define N_PCH_XHCI_MEM_ALIGN 16 +#define R_PCH_XHCI_SVID 0x2C +#define B_PCH_XHCI_SVID 0xFFFF +#define R_PCH_XHCI_SID 0x2E +#define B_PCH_XHCI_SID 0xFFFF + +#define R_PCH_XHCI_XHCC1 0x40 +#define B_PCH_XHCI_XHCC1_ACCTRL BIT31 +#define B_PCH_XHCI_XHCC1_RMTASERR BIT24 +#define B_PCH_XHCI_XHCC1_URD BIT23 +#define B_PCH_XHCI_XHCC1_URRE BIT22 +#define B_PCH_XHCI_XHCC1_IIL1E (BIT21 | BIT20 | BIT19) +#define V_PCH_XHCI_XHCC1_IIL1E_DIS 0 +#define V_PCH_XHCI_XHCC1_IIL1E_32 (BIT19) +#define V_PCH_XHCI_XHCC1_IIL1E_64 (BIT20) +#define V_PCH_XHCI_XHCC1_IIL1E_128 (BIT20 | BIT19) +#define V_PCH_XHCI_XHCC1_IIL1E_256 (BIT21) +#define V_PCH_XHCI_XHCC1_IIL1E_512 (BIT21 | BIT19) +#define V_PCH_XHCI_XHCC1_IIL1E_1024 (BIT21 | BIT20) +#define V_PCH_XHCI_XHCC1_IIL1E_131072 (BIT21 | BIT20 | BIT19) +#define B_PCH_XHCI_XHCC1_XHCIL1E BIT18 +#define B_PCH_XHCI_XHCC1_D3IL1E BIT17 +#define B_PCH_XHCI_XHCC1_UNPPA (BIT16 | BIT15 | BIT14 | BIT13 | BIT12) +#define B_PCH_XHCI_XHCC1_SWAXHCI BIT11 +#define B_PCH_XHCI_XHCC1_L23HRAWC (BIT10 | BIT9 | BIT8) +#define B_PCH_XHCI_XHCC1_UTAGCP (BIT7 | BIT6) +#define B_PCH_XHCI_XHCC1_UDAGCNP (BIT5 | BIT4) +#define B_PCH_XHCI_XHCC1_UDAGCCP (BIT3 | BIT2) +#define B_PCH_XHCI_XHCC1_UDAGC (BIT1 | BIT0) + +#define R_PCH_XHCI_XHCC2 0x44 +#define B_PCH_XHCI_XHCC2_OCCFDONE BIT31 +#define B_PCH_XHCI_XHCC2_XHCUPRDROE BIT11 +#define B_PCH_XHCI_XHCC2_IOSFSRAD BIT10 +#define B_PCH_XHCI_XHCC2_SWACXIHB (BIT9 | BIT8) +#define B_PCH_XHCI_XHCC2_SWADMIL1IHB (BIT7 | BIT6) +#define B_PCH_XHCI_XHCC2_L1FP2CGWC (BIT5 | BIT4 | BIT3) +#define B_PCH_XHCI_XHCC2_RDREQSZCTRL (BIT2 | BIT1 | BIT0) + +#define R_PCH_XHCI_XHCLKGTEN 0x50 +#define B_PCH_XHCI_XHCLKGTEN_SSLSE BIT26 +#define B_PCH_XHCI_XHCLKGTEN_USB2PLLSE BIT25 +#define B_PCH_XHCI_XHCLKGTEN_IOSFSTCGE BIT24 +#define B_PCH_XHCI_XHCLKGTEN_HSTCGE (BIT23 | BIT22 | BIT21 | BIT20) +#define B_PCH_XHCI_XHCLKGTEN_SSTCGE (BIT19 | BIT18 | BIT17 | BIT16) +#define B_PCH_XHCI_XHCLKGTEN_XHCIGEU3S BIT15 +#define B_PCH_XHCI_XHCLKGTEN_XHCFTCLKSE BIT14 +#define B_PCH_XHCI_XHCLKGTEN_XHCBBTCGIPISO BIT13 +#define B_PCH_XHCI_XHCLKGTEN_XHCHSTCGU2NRWE BIT12 +#define B_PCH_XHCI_XHCLKGTEN_XHCUSB2PLLSDLE (BIT11 | BIT10) +#define B_PCH_XHCI_XHCLKGTEN_HSPLLSUE (BIT9 | BIT8) +#define B_PCH_XHCI_XHCLKGTEN_SSPLLSUE (BIT7 | BIT6 | BIT5) +#define B_PCH_XHCI_XHCLKGTEN_XHCBLCGE BIT4 +#define B_PCH_XHCI_XHCLKGTEN_HSLTCGE BIT3 +#define B_PCH_XHCI_XHCLKGTEN_SSLTCGE BIT2 +#define B_PCH_XHCI_XHCLKGTEN_IOSFBTCGE BIT1 +#define B_PCH_XHCI_XHCLKGTEN_IOSFGBLCGE BIT0 + +#define R_PCH_XHCI_USB_RELNUM 0x60 +#define B_PCH_XHCI_USB_RELNUM 0xFF +#define R_PCH_XHCI_FL_ADJ 0x61 +#define B_PCH_XHCI_FL_ADJ 0x3F +#define R_PCH_XHCI_PWR_CAPID 0x70 +#define B_PCH_XHCI_PWR_CAPID 0xFF +#define R_PCH_XHCI_NXT_PTR1 0x71 +#define B_PCH_XHCI_NXT_PTR1 0xFF +#define R_PCH_XHCI_PWR_CAP 0x72 +#define B_PCH_XHCI_PWR_CAP_PME_SUP 0xF800 +#define B_PCH_XHCI_PWR_CAP_D2_SUP BIT10 +#define B_PCH_XHCI_PWR_CAP_D1_SUP BIT9 +#define B_PCH_XHCI_PWR_CAP_AUX_CUR (BIT8 | BIT7 | BIT6) +#define B_PCH_XHCI_PWR_CAP_DSI BIT5 +#define B_PCH_XHCI_PWR_CAP_PME_CLK BIT3 +#define B_PCH_XHCI_PWR_CAP_VER (BIT2 | BIT1 | BIT0) +#define R_PCH_XHCI_PWR_CNTL_STS 0x74 +#define B_PCH_XHCI_PWR_CNTL_STS_PME_STS BIT15 +#define B_PCH_XHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13) +#define B_PCH_XHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9) +#define B_PCH_XHCI_PWR_CNTL_STS_PME_EN BIT8 +#define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0) +#define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0) + +#define R_PCH_XHCI_U2OCM1 0xC0 +#define B_PCH_XHCI_U2OCM1_OC4_MAPPING 0xFF000000 +#define B_PCH_XHCI_U2OCM1_OC3_MAPPING 0x00FF0000 +#define B_PCH_XHCI_U2OCM1_OC2_MAPPING 0x0000FF00 +#define B_PCH_XHCI_U2OCM1_OC1_MAPPING 0x000000FF + +#define R_PCH_XHCI_U2OCM2 0xC4 +#define B_PCH_XHCI_U2OCM2_OC8_MAPPING 0x3F000000 +#define B_PCH_XHCI_U2OCM2_OC7_MAPPING 0x003F0000 +#define B_PCH_XHCI_U2OCM2_OC6_MAPPING 0x00003F00 +#define B_PCH_XHCI_U2OCM2_OC5_MAPPING 0x0000003F + +#define R_PCH_XHCI_U3OCM1 0xC8 +#define B_PCH_XHCI_U3OCM1_OC4_MAPPING 0x3F000000 +#define B_PCH_XHCI_U3OCM1_OC3_MAPPING 0x003F0000 +#define B_PCH_XHCI_U3OCM1_OC2_MAPPING 0x00003F00 +#define B_PCH_XHCI_U3OCM1_OC1_MAPPING 0x0000003F + +#define R_PCH_XHCI_U3OCM2 0xCC +#define B_PCH_XHCI_U3OCM2_OC8_MAPPING 0x3F000000 +#define B_PCH_XHCI_U3OCM2_OC7_MAPPING 0x003F0000 +#define B_PCH_XHCI_U3OCM2_OC6_MAPPING 0x00003F00 +#define B_PCH_XHCI_U3OCM2_OC5_MAPPING 0x0000003F + +#define R_PCH_XHCI_USB2PR 0xD0 +#define B_PCH_XHCI_USB2PR_USB2HCSEL 0x7FFF +#define R_PCH_XHCI_USB2PRM 0xD4 +#define B_PCH_XHCI_USB2PR_USB2HCSELM 0x7FFF + +#define R_PCH_XHCI_USB3PR 0xD8 +#define B_PCH_XHCI_USB3PR_USB3SSEN 0x3F +#define R_PCH_XHCI_USB3PRM 0xDC +#define B_PCH_XHCI_USB3PR_USB3SSENM 0x3F + +#define R_PCH_XHCI_FUS 0xE0 +#define B_PCH_XHCI_FUS_USBR (BIT5) +#define V_PCH_XHCI_FUS_USBR_EN 0 +#define V_PCH_XHCI_FUS_USBR_DIS (BIT5) + +#define B_PCH_XHCI_FUS_SSPRTCNT (BIT4 | BIT3) +#define V_PCH_XHCI_FUS_SSPRTCNT_00B 0 +#define V_PCH_XHCI_FUS_SSPRTCNT_01B (BIT3) +#define V_PCH_XHCI_FUS_SSPRTCNT_10B (BIT4) +#define V_PCH_XHCI_FUS_SSPRTCNT_11B (BIT4 | BIT3) + +#define B_PCH_XHCI_FUS_HSPRTCNT (BIT2 | BIT1) +#define V_PCH_XHCI_FUS_HSPRTCNT_00B 0 +#define V_PCH_XHCI_FUS_HSPRTCNT_01B (BIT1) +#define V_PCH_XHCI_FUS_HSPRTCNT_10B (BIT2) +#define V_PCH_XHCI_FUS_HSPRTCNT_11B (BIT2 | BIT1) + +#define V_PCH_H_XHCI_FUS_SSPRTCNT_00B_CNT 6 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_01B_CNT 4 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_10B_CNT 2 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_11B_CNT 0 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_00B_MASK 0x3F +#define V_PCH_H_XHCI_FUS_SSPRTCNT_01B_MASK 0x0F +#define V_PCH_H_XHCI_FUS_SSPRTCNT_10B_MASK 0x03 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_11B_MASK 0x00 + +#define V_PCH_H_XHCI_FUS_HSPRTCNT_00B_CNT 14 +#define V_PCH_H_XHCI_FUS_HSPRTCNT_01B_CNT 12 +#define V_PCH_H_XHCI_FUS_HSPRTCNT_10B_CNT 10 +#define V_PCH_H_XHCI_FUS_HSPRTCNT_11B_CNT 8 +#define V_PCH_H_XHCI_FUS_HSPRTCNT_00B_MASK 0x3FFF +#define V_PCH_H_XHCI_FUS_HSPRTCNT_01B_MASK 0x3FFF +#define V_PCH_H_XHCI_FUS_HSPRTCNT_10B_MASK 0x0FFF +#define V_PCH_H_XHCI_FUS_HSPRTCNT_11B_MASK 0x00FF + +#define V_PCH_LP_XHCI_FIXED_SSPRTCNT 4 +#define V_PCH_LP_XHCI_FIXED_SSPRTCNT_MASK 0x0F + +#define V_PCH_LP_XHCI_FIXED_HSPRTCNT 8 +#define V_PCH_LP_XHCI_FIXED_HSPRTCNT_MASK 0x00FF + +#define R_PCH_XHCI_USB2PDO 0xE4 +#define B_PCH_XHCI_USB2PDO_MASK 0x7FFF +#define B_PCH_XHCI_USB2PDO_DIS_PORT0 BIT0 + +#define R_PCH_XHCI_USB3PDO 0xE8 +#define B_PCH_XHCI_USB3PDO_MASK 0x3F +#define B_PCH_XHCI_USB3PDO_DIS_PORT0 BIT0 + +// +// xHCI MMIO registers +// + +// +// 0x00 - 0x1F - Capability Registers +// +#define R_PCH_XHCI_CAPLENGTH 0x00 +#define R_PCH_XHCI_HCIVERSION 0x02 +#define R_PCH_XHCI_HCSPARAMS1 0x04 +#define R_PCH_XHCI_HCSPARAMS2 0x08 +#define R_PCH_XHCI_HCSPARAMS3 0x0C +#define B_PCH_XHCI_HCSPARAMS3_U2DEL 0xFFFF0000 +#define B_PCH_XHCI_HCSPARAMS3_U1DEL 0x0000FFFF +#define R_PCH_XHCI_HCCPARAMS 0x10 +#define B_PCH_XHCI_HCCPARAMS_LHRC BIT5 +#define B_PCH_XHCI_HCCPARAMS_MAXPSASIZE 0xF000 +#define R_PCH_XHCI_DBOFF 0x14 +#define R_PCH_XHCI_RTSOFF 0x18 + +// +// 0x80 - 0xBF - Operational Registers +// +#define R_PCH_XHCI_USBCMD 0x80 +#define B_PCH_XHCI_USBCMD_RS BIT0 ///< Run/Stop +#define B_PCH_XHCI_USBCMD_RST BIT1 ///< HCRST +#define R_PCH_XHCI_USBSTS 0x84 + +// +// 0x480 - 0x5CF - Port Status and Control Registers +// +#define R_PCH_XHCI_PORTSC01USB2 0x480 +#define R_PCH_XHCI_PORTSC02USB2 0x490 +#define R_PCH_XHCI_PORTSC03USB2 0x4A0 +#define R_PCH_XHCI_PORTSC04USB2 0x4B0 +#define R_PCH_XHCI_PORTSC05USB2 0x4C0 +#define R_PCH_XHCI_PORTSC06USB2 0x4D0 +#define R_PCH_XHCI_PORTSC07USB2 0x4E0 +#define R_PCH_XHCI_PORTSC08USB2 0x4F0 +#define R_PCH_XHCI_PORTSC09USB2 0x500 +#define R_PCH_H_XHCI_PORTSC10USB2 0x510 +#define R_PCH_H_XHCI_PORTSC11USB2 0x520 +#define R_PCH_H_XHCI_PORTSC12USB2 0x530 +#define R_PCH_H_XHCI_PORTSC13USB2 0x540 +#define R_PCH_H_XHCI_PORTSC14USB2 0x550 +#define R_PCH_H_XHCI_PORTSC15USB2 0x560 + +#define B_PCH_XHCI_PORTSCXUSB2_WPR BIT31 ///< Warm Port Reset +#define B_PCH_XHCI_PORTSCXUSB2_CEC BIT23 ///< Port Config Error Change +#define B_PCH_XHCI_PORTSCXUSB2_PLC BIT22 ///< Port Link State Change +#define B_PCH_XHCI_PORTSCXUSB2_PRC BIT21 ///< Port Reset Change +#define B_PCH_XHCI_PORTSCXUSB2_OCC BIT20 ///< Over-current Change +#define B_PCH_XHCI_PORTSCXUSB2_WRC BIT19 ///< Warm Port Reset Change +#define B_PCH_XHCI_PORTSCXUSB2_PEC BIT18 ///< Port Enabled Disabled Change +#define B_PCH_XHCI_PORTSCXUSB2_CSC BIT17 ///< Connect Status Change +#define B_PCH_XHCI_PORTSCXUSB2_LWS BIT16 ///< Port Link State Write Strobe +#define B_PCH_XHCI_USB2_U3_EXIT (BIT5 | BIT6 | BIT7 | BIT8) +#define B_PCH_XHCI_USB2_U0_MASK (BIT5 | BIT6 | BIT7 | BIT8) +#define B_PCH_XHCI_PORTSCXUSB2_PP BIT9 +#define B_PCH_XHCI_PORTSCXUSB2_PR BIT4 ///< Port Reset +#define B_PCH_XHCI_PORTSCXUSB2_PED BIT1 ///< Port Enable/Disabled +#define B_PCH_XHCI_PORTSCXUSB2_CCS BIT0 ///< Current Connect Status +#define B_PCH_XHCI_PORT_CHANGE_ENABLE_MASK (B_PCH_XHCI_PORTSCXUSB2_CEC | B_PCH_XHCI_PORTSCXUSB2_PLC | B_PCH_XHCI_PORTSCXUSB2_PRC | B_PCH_XHCI_PORTSCXUSB2_OCC | B_PCH_XHCI_PORTSCXUSB2_WRC | B_PCH_XHCI_PORTSCXUSB2_PEC | B_PCH_XHCI_PORTSCXUSB2_CSC | B_PCH_XHCI_PORTSCXUSB2_PED) + +#define R_PCH_H_XHCI_PORTSC1USB3 0x570 +#define R_PCH_H_XHCI_PORTSC2USB3 0x580 +#define R_PCH_H_XHCI_PORTSC3USB3 0x590 +#define R_PCH_H_XHCI_PORTSC4USB3 0x5A0 +#define R_PCH_H_XHCI_PORTSC5USB3 0x5B0 +#define R_PCH_H_XHCI_PORTSC6USB3 0x5C0 + +#define R_PCH_LP_XHCI_PORTSC1USB3 0x510 +#define R_PCH_LP_XHCI_PORTSC2USB3 0x520 +#define R_PCH_LP_XHCI_PORTSC3USB3 0x530 +#define R_PCH_LP_XHCI_PORTSC4USB3 0x540 + +#define B_PCH_XHCI_PORTSCXUSB3_WPR BIT31 ///< Warm Port Reset +#define B_PCH_XHCI_PORTSCXUSB3_CEC BIT23 ///< Port Config Error Change +#define B_PCH_XHCI_PORTSCXUSB3_PLC BIT22 ///< Port Link State Change +#define B_PCH_XHCI_PORTSCXUSB3_PRC BIT21 ///< Port Reset Change +#define B_PCH_XHCI_PORTSCXUSB3_OCC BIT20 ///< Over-current Change +#define B_PCH_XHCI_PORTSCXUSB3_WRC BIT19 ///< Warm Port Reset Change +#define B_PCH_XHCI_PORTSCXUSB3_PEC BIT18 ///< Port Enabled Disabled Change +#define B_PCH_XHCI_PORTSCXUSB3_CSC BIT17 ///< Connect Status Change +#define B_PCH_XHCI_PORTSCXUSB3_LWS BIT16 ///< Port Link State Write Strobe //AMI_OVERRITE +#define B_PCH_XHCI_PORTSCXUSB3_PLS (BIT8 | BIT7 | BIT6 | BIT5) ///< Port Link State +#define V_PCH_XHCI_PORTSCXUSB3_PLS_POLLING 0x000000E0 ///< Link is in the Polling State +#define V_PCH_XHCI_PORTSCXUSB3_PLS_RXDETECT 0x000000A0 ///< Link is in the RxDetect State +#define B_PCH_XHCI_PORTSCXUSB3_PP BIT9 ///< Port Power //AMI_OVERRITE +#define B_PCH_XHCI_PORTSCXUSB3_PR BIT4 ///< Port Reset +#define B_PCH_XHCI_PORTSCXUSB3_PED BIT1 ///< Port Enable/Disabled +#define B_PCH_XHCI_PORTSCXUSB3_CHANGE_ENABLE_MASK (B_PCH_XHCI_PORTSCXUSB3_CEC | B_PCH_XHCI_PORTSCXUSB3_PLC | B_PCH_XHCI_PORTSCXUSB3_PRC | B_PCH_XHCI_PORTSCXUSB3_OCC | B_PCH_XHCI_PORTSCXUSB3_WRC | B_PCH_XHCI_PORTSCXUSB3_PEC | B_PCH_XHCI_PORTSCXUSB3_CSC | B_PCH_XHCI_PORTSCXUSB3_PED) +// +// 0x2000 - 0x21FF - Runtime Registers +// 0x3000 - 0x307F - Doorbell Registers +// + +// +// 0x8000 - 0x833F - Extended Capabilities Registers +// +#define R_PCH_XHCI_MMIO_ECR_8058 0x8058 +#define B_PCH_XHCI_MMIO_ECR_8058_BIT8 BIT8 ///< Set 0 + +#define R_PCH_XHCI_MMIO_ECR_8090 0x8090 +#define B_PCH_XHCI_MMIO_ECR_8090_BIT14 BIT14 ///< Set 1 +#define B_PCH_XHCI_MMIO_ECR_8090_BIT8 BIT8 ///< Set 1 + +#define R_PCH_XHCI_MMIO_ECR_8094 0x8094 +#define B_PCH_XHCI_MMIO_ECR_8094_BIT23 BIT23 ///< Set 1 + +#define R_PCH_XHCI_MMIO_ECR_80E0 0x80E0 +#define B_PCH_XHCI_MMIO_ECR_80E0_BIT9 BIT9 ///< Set 1 +#define B_PCH_XHCI_MMIO_ECR_80E0_BIT6 BIT6 ///< Set 1 + +#define R_PCH_XHCI_MMIO_ECR_80EC 0x80EC +#define B_PCH_XHCI_MMIO_ECR_80EC_BIT_14_12 0x7000 ///< Set 6 +#define B_PCH_XHCI_MMIO_ECR_80EC_BIT_11_9 0x0E00 ///< Set 6 + +#define R_PCH_XHCI_MMIO_ECR_8110 0x8110 +#define B_PCH_XHCI_MMIO_ECR_8110_BIT2 BIT2 ///< Set 0 + +#endif |