diff options
Diffstat (limited to 'ReferenceCode/Chipset/LynxPoint/S3Support')
21 files changed, 2317 insertions, 0 deletions
diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.c b/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.c new file mode 100644 index 0000000..943ffd7 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.c @@ -0,0 +1,369 @@ +/** @file + This is the driver that implements the PCH S3 Support protocol + +@copyright + Copyright (c) 1999 - 2015 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement + +**/ +#include "PchS3Support.h" +#include "S3SupportHob.h" +// AMI_OVERRIDE, [ EIP217847 ] >>> +#include "token.h" +// AMI_OVERRIDE, [ EIP217847 ] <<< + +// +// Global Variables +// +EFI_HANDLE mImageHandle; +EFI_PCH_S3_SUPPORT_PROTOCOL mPchS3SupportProtocol; +EFI_PCH_S3_SUPPORT_SMM_PROTOCOL mPchS3SupportSmmProtocol; +UINT32 mPchS3ImageEntryPoint; +EFI_PCH_S3_DISPATCH_ARRAY *mPchS3CustomDispatchScript; + +// +// GUID Definitions +// +EFI_GUID gS3SupportHobGuid = S3_SUPPORT_HOB_GUID; +EFI_GUID gS3SupportSmramDataGuid = EFI_PCH_S3_SUPPORT_DATA_GUID; + +// +// Functions +// + +/** + PCH S3 support driver entry point + + @param[in] ImageHandle Handle for the image of this driver + @param[in] SystemTable Pointer to the EFI System Table + + @retval EFI_STATUS +**/ +EFI_STATUS +EFIAPI +PchS3SupportEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + DEBUG ((EFI_D_INFO, "PchS3SupportEntryPoint() Start\n")); + mImageHandle = ImageHandle; + + /// + /// Initialize the Boot Services memory for the Dispatch Script Array + /// + Status = InitializePchS3CustomScriptMemory(); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return Status; + } + + DEBUG ((EFI_D_INFO, "Dispatch Script Array Space initialized.\n")); + + /// + /// Retrieve the PCH S3 Support PEIM entry point and load it into the Module variable + /// + Status = LoadPchS3ImageEntryPoint (&mPchS3ImageEntryPoint); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return Status; + } + + DEBUG ((EFI_D_INFO, "PCH S3 Image Entry Point intialized.\n")); + + /// + /// Initialize and Install the PCH S3 Support and PCH S3 SMM Support protocols + /// + mPchS3SupportSmmProtocol.DispatchArray = mPchS3CustomDispatchScript; + mPchS3SupportSmmProtocol.ProtocolSize = 1; // Allocate one page + mPchS3SupportProtocol.SetDispatchItem = PchS3SetDispatchItem; + mPchS3SupportProtocol.ReadyToLock = S3SupportReadyToLock; + Status = gBS->InstallMultipleProtocolInterfaces ( + &mImageHandle, + &gEfiPchS3SupportProtocolGuid, + &mPchS3SupportProtocol, + &gEfiPchS3SupportSmmProtocolGuid, + &mPchS3SupportSmmProtocol, + NULL + ); + ASSERT_EFI_ERROR (Status); + + DEBUG ((EFI_D_INFO, "PchS3SupportEntryPoint() End\n")); + + return Status; +} + +/** + Set an item to be dispatched at S3 resume time. This will initially create a Script + entry in Boot Services memory. At the same time, the entry point of the PCH S3 support + image is returned to be used in subsequent boot script save calls. + + @param[in] This Pointer to the protocol instance. + @param[in] DispatchItem The item to be dispatched. + @param[out] S3DispatchEntryPoint The entry point of the PCH S3 support image. + + @retval EFI_STATUS Successfully completed. + @retval EFI_OUT_OF_RESOURCES Out of resources. +**/ +EFI_STATUS +EFIAPI +PchS3SetDispatchItem ( + IN EFI_PCH_S3_SUPPORT_PROTOCOL *This, + IN EFI_PCH_S3_DISPATCH_ITEM *InputDispatchItem, + OUT EFI_PHYSICAL_ADDRESS *S3DispatchEntryPoint + ) +{ + EFI_STATUS Status; + UINT32 TypeSize; + UINT32 ParameterSize; + UINT32 Size; + UINT8 *CurrentPos; + + DEBUG ((EFI_D_INFO, "PchS3SetDispatchItem() Start\n")); + + Status = EFI_SUCCESS; + + DEBUG ((EFI_D_INFO, "Dispatch Item Address: 0x%x; Dispatch Item Type: %x\n", (UINTN)InputDispatchItem, (UINTN)InputDispatchItem->ItemType.Value)); + + /// + /// Calculate the size required; + /// ** Always round up to be 8 byte aligned as the script is initially created from 64-bit code in DXE + /// + switch (InputDispatchItem->ItemType.Value) { + case PchS3ItemTypeSendCodecCommand: + ParameterSize = QWORD_ALIGNED_SIZE(EFI_PCH_S3_PARAMETER_SEND_CODEC_COMMAND); + break; + + case PchS3ItemTypeInitPcieRootPortDownstream: + ParameterSize = QWORD_ALIGNED_SIZE(EFI_PCH_S3_PARAMETER_INIT_PCIE_ROOT_PORT_DOWNSTREAM); + break; + + case PchS3ItemTypePcieSetPm: + ParameterSize = QWORD_ALIGNED_SIZE(EFI_PCH_S3_PARAMETER_PCIE_SET_PM); + break; + + case PchS3ItemTypeProgramIobp: + ParameterSize = QWORD_ALIGNED_SIZE(EFI_PCH_S3_PARAMETER_PROG_IOBP); + break; + + default: + ParameterSize = 0; + DEBUG ((EFI_D_INFO, "Unrecognized Custom Dispatch Type\n")); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + /// + /// Round up TypeSize to be 8 byte aligned + /// + TypeSize = QWORD_ALIGNED_SIZE (EFI_PCH_S3_DISPATCH_ITEM_TYPE); + + /// + /// Total size is TypeSize + ParameterSize + /// + Size = TypeSize + ParameterSize; + + if (mPchS3CustomDispatchScript->BufferSpaceRemaining < Size) { + DEBUG ((EFI_D_INFO, "Space remaining in Dispatch Script buffer is too small\n")); + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + if (mPchS3CustomDispatchScript->NextDispatchItem == NULL) { + DEBUG ((EFI_D_INFO, "S3 Support Protocol has been unregistered. Error.\n")); + ASSERT (FALSE); + return EFI_ACCESS_DENIED; + } + + /// + /// Store the dispatch type and dispatch parameter + /// + CurrentPos = mPchS3CustomDispatchScript->NextDispatchItem; + *(EFI_PCH_S3_DISPATCH_ITEM_TYPE *)CurrentPos = InputDispatchItem->ItemType.Value; + CurrentPos += TypeSize; + CopyMem (CurrentPos, InputDispatchItem->Parameter, ParameterSize); + + /// + /// Move the pointer to the NextDispatchItem ahead to free space in our buffer + /// and decrement the space remaining data + /// + mPchS3CustomDispatchScript->NextDispatchItem += Size; + mPchS3CustomDispatchScript->BufferSpaceRemaining -= Size; + + /// + /// Return the S3 Image's entry point + /// + *S3DispatchEntryPoint = mPchS3ImageEntryPoint; + + DEBUG ((EFI_D_INFO, "PchS3SetDispatchItem() End\n")); + + return Status; +} + + +/** + Perform the EFI_PCH_S3_SUPPORT_SMM_PROTOCOL IO Trap to invoke DispatchArray data copy and + IO Trap Unregister. + + @param[in] This Pointer to the protocol instance. + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +EFIAPI +S3SupportReadyToLock( + IN EFI_PCH_S3_SUPPORT_PROTOCOL *This + ) +{ + EFI_STATUS Status; + + + DEBUG ((EFI_D_INFO, "S3SupportExitPmAuthCallback() Start\n")); + + Status = EFI_SUCCESS; + + DEBUG ((EFI_D_INFO, "Invoke the S3 Support IO Trap: 0x%x\n", mPchS3SupportSmmProtocol.PchS3SupportIoTrap)); + + /// + /// Invoke the SMM IO Trap Handler for invoking the data copy to SMRAM and unregistration of the IO Trap + /// + IoWrite32 (mPchS3SupportSmmProtocol.PchS3SupportIoTrap, 0); + + if (mImageHandle != NULL) + { + DEBUG ((EFI_D_INFO, "Uninstall the S3 Support Protocol\n", mPchS3SupportSmmProtocol.PchS3SupportIoTrap)); + + Status = gBS->UninstallMultipleProtocolInterfaces ( + mImageHandle, + &gEfiPchS3SupportProtocolGuid, + &mPchS3SupportProtocol, + NULL + ); + ASSERT_EFI_ERROR (Status); + } + DEBUG ((EFI_D_INFO, "S3SupportExitPmAuthCallback() End\n")); + + return Status; +} + +/** + Initialize the Pch S3 Custom Script memory area. This will later be transferred to SMRAM. + + @param[in] VOID + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_OUT_OF_RESOURCES Not enough space was available to allocate for the BS memory required. +**/ +EFI_STATUS +InitializePchS3CustomScriptMemory ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS Address; + + /// + /// Allocate Boot Services memory for the initial copy of the PCH S3 Custom Dispatch Script + /// + Status = (gBS->AllocatePool)( + EfiBootServicesData, + EFI_PAGE_SIZE, + &(VOID *)Address); + if (!EFI_ERROR (Status)) { + + mPchS3CustomDispatchScript = (EFI_PCH_S3_DISPATCH_ARRAY *)(UINTN)Address; + + /// + /// Initialize the DispatchScriptArray + /// Ensure to account for the HOB space that will be needed for moving the data from SMRAM to normal + /// memory during S3 resume in the MaximumBufferSize parameter. + /// + mPchS3CustomDispatchScript->PchS3CustomScriptGuid = gS3SupportSmramDataGuid; + mPchS3CustomDispatchScript->MaximumBufferSize = EFI_PAGE_SIZE - QWORD_ALIGNED_SIZE(EFI_HOB_GUID_TYPE); + mPchS3CustomDispatchScript->BufferSpaceRemaining = mPchS3CustomDispatchScript->MaximumBufferSize - QWORD_ALIGNED_SIZE(EFI_PCH_S3_DISPATCH_ARRAY); + mPchS3CustomDispatchScript->NextDispatchItem = (UINT8*)mPchS3CustomDispatchScript + QWORD_ALIGNED_SIZE(EFI_PCH_S3_DISPATCH_ARRAY); + } + + return Status; +} + + +/** + Load the entry point address of the PCHS3Peim from the HOB that it generated during the PEI phase of POST + + @param[out] ImageEntryPoint The ImageEntryPoint after success loading + + @retval EFI_STATUS +**/ +EFI_STATUS +LoadPchS3ImageEntryPoint ( + OUT UINT32 *ImageEntryPoint + ) +{ + EFI_STATUS Status; + S3_SUPPORT_HOB *S3SupportHob; +// EFI_SPI_DATA_PROTOCOL *SpiDataInterface; + + DEBUG ((EFI_D_INFO, "LoadPchS3ImageEntryPoint() Start\n")); + + Status = EFI_SUCCESS; + S3SupportHob = NULL; + *ImageEntryPoint = 0; + + // + // Search for the S3SupportHob + // + S3SupportHob = GetFirstGuidHob(&gS3SupportHobGuid); + if (S3SupportHob == NULL) { + DEBUG ((EFI_D_INFO, "S3SupportHob not found.\n")); + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + // Find the SPI protocol and save the pointer. + // +// Status = gBS->LocateProtocol (&gEfiSpiDataProtocolGuid, NULL, &SpiDataInterface); +// if (EFI_ERROR (Status)) { +// DEBUG ((EFI_D_ERROR, "ERROR - Spi LocateProtocol failed!\n")); +// return Status; +// } + + /// + /// If the PCH S3 PEIM is not located in flash, fail + /// +// AMI_OVERRIDE, [ EIP217847 ] >>> +// if (S3SupportHob->PchS3PeimEntryPoint < SpiDataInterface->BiosStartMemoryAddress || +// S3SupportHob->PchS3PeimEntryPoint > SpiDataInterface->BiosStartMemoryAddress + SpiDataInterface->BiosSize) + if ((S3SupportHob->PchS3PeimEntryPoint < (0xFFFFFFFF - FLASH_SIZE + 1)) || (S3SupportHob->PchS3PeimEntryPoint > 0xFFFFFFFF)) +// AMI_OVERRIDE, [ EIP217847 ] <<< + { + DEBUG ((EFI_D_INFO, "PchS3Image is NOT located in Flash. Current Entry Point: %x\n", S3SupportHob->PchS3PeimEntryPoint)); + + ASSERT(FALSE); + return EFI_SECURITY_VIOLATION; + } + + // Load the HOB data from PEI execution which contains the entry point of the PCHS3Peim from Flash + *ImageEntryPoint = S3SupportHob->PchS3PeimEntryPoint; + + DEBUG ((EFI_D_INFO, "PchS3Image is Located in Flash at Entry Point: %x\n", S3SupportHob->PchS3PeimEntryPoint)); + DEBUG ((EFI_D_INFO, "LoadPchS3ImageEntryPoint() End\n")); + + return Status; +}
\ No newline at end of file diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.cif b/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.cif new file mode 100644 index 0000000..cbd8f6a --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.cif @@ -0,0 +1,13 @@ +<component> + name = "PchS3Support" + category = ModulePart + LocalRoot = "ReferenceCode\Chipset\LynxPoint\S3Support\Dxe" + RefName = "PchS3Support" +[files] +"PchS3Support.sdl" +"PchS3Support.mak" +"PchS3Support.c" +"PchS3Support.h" +"PchS3Support.dxs" +"PchS3Support.inf" +<endComponent>
\ No newline at end of file diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.dxs b/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.dxs new file mode 100644 index 0000000..8c346bd --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.dxs @@ -0,0 +1,45 @@ +/** @file + Dispatch dependency expression file for the PchS3Support driver. + +@copyright + Copyright (c) 1999 - 2015 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ + +// +// Common for R8 and R9 codebase +// +#include "AutoGen.h" +#include "DxeDepex.h" + +// +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase; +// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase. +// +#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB) +#include "EfiDepex.h" + +#include EFI_PROTOCOL_DEFINITION (BootScriptSave) +#include EFI_PROTOCOL_CONSUMER (Spi) +#endif + +//DEPENDENCY_START +// EFI_BOOT_SCRIPT_SAVE_PROTOCOL_GUID AND +// EFI_SPI_DATA_PROTOCOL_GUID +//DEPENDENCY_END +DEPENDENCY_START + EFI_BOOT_SCRIPT_SAVE_PROTOCOL_GUID +DEPENDENCY_END
\ No newline at end of file diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.h b/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.h new file mode 100644 index 0000000..817f786 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.h @@ -0,0 +1,126 @@ +/** @file + Header file for PCH S3 Support driver + +@copyright + Copyright (c) 1999 - 2015 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _PCH_S3_SUPPORT_DRIVER_H_ +#define _PCH_S3_SUPPORT_DRIVER_H_ + +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) + +#include "EdkIIGlueDxe.h" +#include "EfiScriptLib.h" + +// +// Driver Produced Protocol Prototypes +// +#include EFI_PROTOCOL_PRODUCER (PchS3Support) +#include EFI_GUID_DEFINITION (S3SupportHob) +#include EFI_PROTOCOL_CONSUMER (Spi) + +#include "PchAccess.h" +#include "PchPlatformLib.h" +#endif + +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#define EFI_PCH_S3_IMAGE_GUID \ + { \ + 0x271dd6f2, 0x54cb, 0x45e6, 0x85, 0x85, 0x8c, 0x92, 0x3c, 0x1a, 0xc7, 0x6 \ + } +#else +#define EFI_PCH_S3_IMAGE_GUID \ + { \ + 0x271dd6f2, 0x54cb, 0x45e6, \ + { \ + 0x85, 0x85, 0x8c, 0x92, 0x3c, 0x1a, 0xc7, 0x6 \ + } \ + } +#endif + +extern EFI_GUID gEfiSpiProtocolGuid; + +// +// Function prototypes +// + +/** + Set an item to be dispatched at S3 resume time. At the same time, the entry point + of the PCH S3 support image is returned to be used in subsequent boot script save + call + + @param[in] This Pointer to the protocol instance. + @param[in] InputDispatchItem The item to be dispatched. + @param[out] S3DispatchEntryPoint The entry point of the PCH S3 support image. + + @retval EFI_STATUS Successfully completed. + @retval EFI_OUT_OF_RESOURCES Out of resources. +**/ +EFI_STATUS +EFIAPI +PchS3SetDispatchItem ( + IN EFI_PCH_S3_SUPPORT_PROTOCOL *This, + IN EFI_PCH_S3_DISPATCH_ITEM *InputDispatchItem, + OUT EFI_PHYSICAL_ADDRESS *S3DispatchEntryPoint + ); + +/** + Perform the EFI_PCH_S3_SUPPORT_SMM_PROTOCOL IO Trap to invoke DispatchArray data copy and + IO Trap Unregister. + + @param[in] This Pointer to the protocol instance. + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +EFIAPI +S3SupportReadyToLock( + IN EFI_PCH_S3_SUPPORT_PROTOCOL *This + ); + +/** + Initialize the Pch S3 Custom Script memory area. This will later be transferred to SMRAM. + + @param[in] VOID + + @retval None +**/ +EFI_STATUS +InitializePchS3CustomScriptMemory ( + VOID + ); + +/** + Load the entry point address of the PCHS3Peim from the HOB that it generated during the PEI phase of POST + + @param[out] ImageEntryPoint The ImageEntryPoint after success loading + + @retval EFI_STATUS +**/ +EFI_STATUS +LoadPchS3ImageEntryPoint ( + OUT UINT32 *ImageEntryPoint + ); + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.inf b/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.inf new file mode 100644 index 0000000..c65847f --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.inf @@ -0,0 +1,103 @@ +## @file +# Component description file for Pch Initialization driver +# +#@copyright +# Copyright (c) 1999 - 2015 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +[defines] +BASE_NAME = PchS3Support +FILE_GUID = C7EA9787-CA0A-43b4-B1E5-25EF87391F8D +COMPONENT_TYPE = BS_DRIVER + +[sources.common] + PchS3Support.h + PchS3Support.c + +# +# Edk II Glue Driver Entry Point +# + EdkIIGlueDxeDriverEntryPoint.c + +[includes.common] + $(EDK_SOURCE)/Foundation/Efi + . + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EDK_SOURCE)/Foundation/Framework/Guid/Hob + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT) + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include/Library + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Guid/S3SupportHob + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Protocol + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Protocol/PchPlatformPolicy + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Protocol/PchS3Support +# +# EDK II Glue Library utilizes some standard headers from EDK +# + $(EFI_SOURCE) + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Library + +# +# Typically the sample code referenced will be available in the code base already +# So keep this include at the end to defer to the source base definition +# and only use the sample code definition if source base does not include these files. +# + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/SampleCode + +[libraries.common] + EfiScriptLib + EfiCommonLib + EdkProtocolLib + EdkFrameworkProtocolLib + $(PROJECT_PCH_FAMILY)ProtocolLib + PchPlatformLib + EdkIIGlueBaseIoLibIntrinsic + EdkIIGlueDxeReportStatusCodeLib + EdkIIGlueDxeDebugLibReportStatusCode + EdkIIGlueUefiBootServicesTableLib + EdkIIGlueUefiRuntimeServicesTableLib + EdkIIGlueDxeServicesTableLib + EdkIIGlueDxeMemoryAllocationLib + EdkIIGlueDxeHobLib + EdkIIGlueBasePciLibPciExpress + EfiDriverLib + EdkIIGlueUefiDevicePathLib + EdkIIGlueUefiLib + EfiGuidLib + +[nmake.common] + IMAGE_ENTRY_POINT = _ModuleEntryPoint + DPX_SOURCE = PchS3Support.dxs +# +# Module Entry Point +# + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=PchS3SupportEntryPoint + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \ + -D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \ + -D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \ + -D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \ + -D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \ + -D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \ + -D __EDKII_GLUE_DXE_MEMORY_ALLOCATION_LIB__ \ + -D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ \ + -D __EDKII_GLUE_DXE_HOB_LIB__ diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.mak b/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.mak new file mode 100644 index 0000000..cabc751 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.mak @@ -0,0 +1,115 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2015, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/S3Support/Dxe/PchS3Support.mak 1 5/21/15 2:53a Dennisliu $ +# +# $Revision: 1 $ +# +# $Date: 5/21/15 2:53a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/S3Support/Dxe/PchS3Support.mak $ +# +# 1 5/21/15 2:53a Dennisliu +# [TAG] EIP217847 +# [Category] Improvement +# [Description] [PCH] Shark Bay-M/DT Reference Code Production Version +# 1.9.1 +# [Files] PchS3Support.sdl +# PchS3Support.mak +# PchS3Support.c +# PchS3Support.h +# PchS3Support.dxs +# PchS3Support.inf +# +#************************************************************************* + +#--------------------------------------------------------------------------- +# Create PchS3Support Driver +#--------------------------------------------------------------------------- +EDK : PchS3Support +PchS3Support : $(BUILD_DIR)\PchS3Support.mak PchS3SupportBin + + +$(BUILD_DIR)\PchS3Support.mak : $(PchS3Support_DIR)\$(@B).cif $(PchS3Support_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(PchS3Support_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +PchS3Support_INCLUDES=\ + $(INTEL_PCH_INCLUDES)\ + $(EdkIIGlueLib_INCLUDES)\ + +PchS3Support_DEFINES = $(MY_DEFINES)\ + /D"__EDKII_GLUE_MODULE_ENTRY_POINT__=PchS3SupportEntryPoint"\ + /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \ + /D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \ + /D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \ + /D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \ + /D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \ + /D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ \ + /D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \ + /D __EDKII_GLUE_DXE_HOB_LIB__ \ + +PchS3Support_LIB_LINKS =\ + $(EDKFRAMEWORKPROTOCOLLIB)\ + $(EDKPROTOCOLLIB)\ + $(PchPlatformDxeLib_LIB)\ + $(EFISCRIPTLIB) $(EFIPROTOCOLLIB)\ + $(INTEL_PCH_PROTOCOL_LIB)\ + $(EdkIIGlueBaseLib_LIB)\ +!IF "$(x64_BUILD)"=="1" + $(EdkIIGlueBaseLibX64_LIB)\ +!ELSE + $(EdkIIGlueBaseLibIA32_LIB)\ +!ENDIF + $(EdkIIGlueBaseIoLibIntrinsic_LIB)\ + $(EdkIIGlueDxeReportStatusCodeLib_LIB)\ + $(EdkIIGlueDxeDebugLibReportStatusCode_LIB)\ + $(EdkIIGlueUefiBootServicesTableLib_LIB)\ + $(EdkIIGlueDxeServicesTableLib_LIB)\ + $(PchS3SupportCommonDxeLib_LIB)\ + $(EdkIIGlueBasePciLibPciExpress_LIB)\ + $(EdkIIGlueUefiRuntimeServicesTableLib_LIB)\ + $(EFIDRIVERLIB)\ + $(EdkIIGlueUefiDevicePathLib_LIB)\ + $(EdkIIGlueUefiLib_LIB)\ + $(EdkIIGlueDxeHobLib_LIB)\ + + +PchS3SupportBin: $(PchS3Support_LIB_LINKS) + $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\ + /f $(BUILD_DIR)\PchS3Support.mak all \ + "MY_INCLUDES=$(PchS3Support_INCLUDES)"\ + "MY_DEFINES=$(PchS3Support_DEFINES)"\ + GUID=08F2C63B-08DE-4ccd-8670-ACFE644A1C48\ + ENTRY_POINT=_ModuleEntryPoint \ + TYPE=BS_DRIVER\ + EDKIIModule=DXEDRIVER\ + DEPEX1=$(PchS3Support_DIR)\PchS3Support.dxs\ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\ + COMPRESS=1 +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2015, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.sdl b/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.sdl new file mode 100644 index 0000000..15c9702 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Dxe/PchS3Support.sdl @@ -0,0 +1,75 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2015, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/S3Support/Dxe/PchS3Support.sdl 1 5/21/15 2:53a Dennisliu $ +# +# $Revision: 1 $ +# +# $Date: 5/21/15 2:53a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/S3Support/Dxe/PchS3Support.sdl $ +# +# 1 5/21/15 2:53a Dennisliu +# [TAG] EIP217847 +# [Category] Improvement +# [Description] [PCH] Shark Bay-M/DT Reference Code Production Version +# 1.9.1 +# [Files] PchS3Support.sdl +# PchS3Support.mak +# PchS3Support.c +# PchS3Support.h +# PchS3Support.dxs +# PchS3Support.inf +# +#************************************************************************* +TOKEN + Name = "PchS3Support_SUPPORT" + Value = "1" + Help = "Main switch to enable PchS3Support support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes +End + +PATH + Name = "PchS3Support_DIR" +End + +MODULE + Help = "Includes PchS3Support.mak to Project" + File = "PchS3Support.mak" +End + +ELINK + Name = "$(BUILD_DIR)\PchS3Support.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2015, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.c b/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.c new file mode 100644 index 0000000..7e7149e --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.c @@ -0,0 +1,563 @@ +/** @file + This is the PEIM that performs the S3 resume tasks. + +@copyright + Copyright (c) 2008 - 2015 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement + +**/ +#include "PchS3Peim.h" +#include "S3SupportHob.h" + +// +// GUID Definitions +// +EFI_GUID gS3SupportHobGuid = S3_SUPPORT_HOB_GUID; +EFI_GUID gS3SupportSmramDataGuid = EFI_PCH_S3_SUPPORT_DATA_GUID; +EFI_GUID gS3DataHobGuid = S3_DATA_HOB_GUID; + +static EFI_PEI_NOTIFY_DESCRIPTOR mSmmAccessCallbackList = { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gPeiSmmAccessPpiGuid, + CreateS3DataHob +}; + + + +/** + PCH S3 PEIM entry point. This Entry Point is entered for three separate reasons. + 1. It is entered via dispatcher in standard POST in order to create a HOB for + the DXE module to find it's EntryPoint. + 2. It is entered via dispatcher in S3 Resume in order to find the Dispatch Script + in SMRAM and copy it to a HOB in Boot Services memory. + 3. It is entered in response to an invocation from the Boot Script Dispatch Opcode. + + In all three cases it is critical that this code is executed directly from Flash and + not from a location in memory. + + + @param[in] FfsHeader Header for FFS + @param[in] PeiServices PEI Services table pointer + + @retval EFI_SUCCESS Successfully completed +**/ +EFI_STATUS +EFIAPI +InitializePchS3Peim ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + UINT32 ParameterSize; + UINT32 TypeSize; + UINT32 Size; + EFI_PCH_S3_DISPATCH_ARRAY *DispatchArray; + EFI_PCH_S3_DISPATCH_ITEM *DispatchItem; + S3_SUPPORT_HOB *S3SupportHob; + S3_DATA_HOB *GuidHob; + PEI_SMM_ACCESS_PPI *SmmAccessPpi; + + DEBUG ((EFI_D_INFO, "InitializePchS3Peim() Start\n")); + + Status = EFI_SUCCESS; + + GuidHob = (S3_DATA_HOB *)GetFirstGuidHob (&gS3DataHobGuid); + + /// + /// Search for the S3 Data Hob + /// Not finding the Hob indicates that this is the initial pass through this code for any particular POST (S3, S4, S5 or other) + /// + if (GuidHob == NULL) + { + // + // If we are entering the entry point for the first time on a specific boot (regardless of mode), + // then we need to generate a HOB with the entry point information in order to pass the data to DXE + // for entry into the Boot Script. + // + DEBUG ((EFI_D_INFO, "PCH S3 Data HOB didn't exist\n")); + DEBUG ((EFI_D_INFO, "Attempt to create the PchS3Peim S3 Support Hob\n")); + + Status = (*PeiServices)->CreateHob ( + PeiServices, + EFI_HOB_TYPE_GUID_EXTENSION, + sizeof (S3_SUPPORT_HOB), + &S3SupportHob + ); + if (!EFI_ERROR (Status)) { + S3SupportHob->Header.Name = gS3SupportHobGuid; + S3SupportHob->PchS3PeimEntryPoint = (UINTN) _ModuleEntryPoint; + DEBUG ((EFI_D_INFO, "PCH S3 Hob Created - %g\n", &gS3SupportHobGuid)); + } + + DEBUG ((EFI_D_INFO, "Collect data from SMRAM for PCH S3 Data Script\n")); + + /// + /// Creation of the S3 Data Hob is only needed on S3. However, the boot mode can't be trusted + /// until after Memory Initialization has been completed because of RapidStart (FFS). + /// As a result, we will check boot mode inside of the CreateS3DataHob function after the SmmAccessPpi + /// is available. + /// + Status = PeiServicesLocatePpi ( + &gPeiSmmAccessPpiGuid, + 0, + NULL, + (VOID **)&SmmAccessPpi + ); + if (Status == EFI_SUCCESS) + { + + /// + /// Then this is our first call on S3 resume + /// Find the PCH S3 Boot Script within SMRAM and create the HOB used for executing the Script + /// + Status = CreateS3DataHob (PeiServices, NULL, SmmAccessPpi); + DEBUG ((EFI_D_INFO, "CreateS3DataHob, result=%r\n", Status)); + + } + else + { + /// + /// Register for notify if SMM_ACCESS isn't yet available. + /// We can't have a module dependency on SMM_ACCESS because the module + /// must be called on both Normal Boot and S3 resume. SMM_ACCESS + /// PPI isn't published on Normal Boot, however. + /// + DEBUG ((EFI_D_INFO, "SMM Access protocol not yet available -> Register for notification later.\n")); + + // + // Register notify to set default variable once variable service is ready. + // + Status = (**PeiServices).NotifyPpi (PeiServices, &mSmmAccessCallbackList); + ASSERT_PEI_ERROR (PeiServices, Status); + + } + return Status; + } + else + { + DEBUG ((EFI_D_INFO, "PchS3Peim S3 Data Hob located. Proceed with Dispatch.\n")); + + /// + /// Setup the DispatchArray variable to point at the Hob + /// + DispatchArray = (EFI_PCH_S3_DISPATCH_ARRAY *)(VOID *)&GuidHob->S3DispatchDataArray; + } + + DEBUG ((EFI_D_INFO, "Dispatch Array Located -> 0x%x\n", DispatchArray)); + DEBUG ((EFI_D_INFO, "Dispatch Item Located (Current NextDispatchItem entry) -> 0x%x\n", DispatchArray->NextDispatchItem)); + + DispatchItem = (EFI_PCH_S3_DISPATCH_ITEM *)DispatchArray->NextDispatchItem; + + DEBUG ((EFI_D_INFO, "Dispatch Item Type -> 0x%x\n", DispatchItem->ItemType.Value)); + + /// + /// Calculate the size required; + /// ** Always round up to be 8 byte aligned as the script is initially created from 64-bit code in DXE + /// + TypeSize = QWORD_ALIGNED_SIZE (EFI_PCH_S3_DISPATCH_ITEM_TYPE); + + switch (DispatchItem->ItemType.Value) { + case PchS3ItemTypeSendCodecCommand: + ParameterSize = QWORD_ALIGNED_SIZE(EFI_PCH_S3_PARAMETER_SEND_CODEC_COMMAND); + Status = PchS3SendCodecCommand ((EFI_PCH_S3_PARAMETER_SEND_CODEC_COMMAND *)&DispatchItem->Parameter); + break; + + case PchS3ItemTypeInitPcieRootPortDownstream: + ParameterSize = QWORD_ALIGNED_SIZE(EFI_PCH_S3_PARAMETER_INIT_PCIE_ROOT_PORT_DOWNSTREAM); + Status = PchS3InitPcieRootPortDownstream ((EFI_PCH_S3_PARAMETER_INIT_PCIE_ROOT_PORT_DOWNSTREAM *)&DispatchItem->Parameter); + if (Status == EFI_NOT_FOUND) { + /// + /// EFI_NOT_FOUND is not an error here + /// + Status = EFI_SUCCESS; + } + break; + + case PchS3ItemTypePcieSetPm: + ParameterSize = QWORD_ALIGNED_SIZE(EFI_PCH_S3_PARAMETER_PCIE_SET_PM); + Status = PchS3PcieSetPm ((EFI_PCH_S3_PARAMETER_PCIE_SET_PM *)&DispatchItem->Parameter); + if (Status == EFI_NOT_FOUND) { + /// + /// EFI_NOT_FOUND is not an error here + /// + Status = EFI_SUCCESS; + } + break; + + case PchS3ItemTypeProgramIobp: + ParameterSize = QWORD_ALIGNED_SIZE(EFI_PCH_S3_PARAMETER_PROG_IOBP); + Status = PchS3ProgramIobp ((EFI_PCH_S3_PARAMETER_PROG_IOBP *)&DispatchItem->Parameter); + break; + + default: + ParameterSize = 0; + DEBUG ((EFI_D_INFO, "Parameter not found\n")); + + ASSERT (FALSE); + break; + } + + /// + /// Advance the Execution Position + /// + Size = ParameterSize + TypeSize; + DispatchArray->NextDispatchItem += Size; + + if ((UINTN)DispatchArray->NextDispatchItem > (UINTN)((UINT8*)DispatchArray + DispatchArray->MaximumBufferSize)) { + /// + /// We are beyond end, wrap for the next S3 resume path + /// + DispatchArray->NextDispatchItem = (UINT8*)DispatchArray + QWORD_ALIGNED_SIZE(EFI_PCH_S3_DISPATCH_ARRAY); + } + + DEBUG ((EFI_D_INFO, "InitializePchS3Peim() End\n")); + + return Status; +} + +/** +This routine is used to search SMRAM and get SmramCpuData point. + +@param[in] PeiServices - PEI services global pointer +@param[in] SmmAccessPpi - SmmAccess PPI instance + +@retval SmramCpuData - The pointer of CPU information in SMRAM. +**/ +EFI_STATUS +CreateS3DataHob ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Interface + ) +{ + EFI_SMRAM_DESCRIPTOR *SmramRanges; + UINTN SmramRangeCount; + UINTN Size; + EFI_STATUS Status; + UINT32 Address; + EFI_PCH_S3_DISPATCH_ARRAY *S3DispatchArray; + PEI_SMM_ACCESS_PPI *SmmAccessPpi; + BOOLEAN Found; + UINTN Index; + S3_DATA_HOB *GuidHob; + EFI_BOOT_MODE BootMode; + + DEBUG ((EFI_D_INFO, "CreateS3DataHob() Start\n")); + + /// + /// Now that we know we have a valid Boot Mode. + /// Check it to see if we need to process the S3 Data Hob Request + /// + Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_INFO, "PchS3Peim S3 Boot Mode not available.\n")); + return Status; + } + + DEBUG ((EFI_D_INFO, "PchS3Peim S3 Boot Mode Check: %x\n", BootMode)); + + if (BootMode != BOOT_ON_S3_RESUME) { + // + // Only Create the S3 Data Hob on S3 resume + // + return Status; + } + + SmmAccessPpi = (PEI_SMM_ACCESS_PPI *)Interface; + + Found = FALSE; + S3DispatchArray = NULL; + + /// + /// Open all SMM regions + /// + Index = 0; + do { + Status = SmmAccessPpi->Open (PeiServices, SmmAccessPpi, Index); + Index++; + } while (!EFI_ERROR (Status)); + + /// + /// Get all SMRAM range + /// + Size = 0; + Status = SmmAccessPpi->GetCapabilities (PeiServices, SmmAccessPpi, &Size, NULL); + ASSERT (Status == EFI_BUFFER_TOO_SMALL); + + Status = PeiServicesAllocatePool ( + Size, + (VOID **)&SmramRanges + ); + ASSERT_EFI_ERROR (Status); + + Status = SmmAccessPpi->GetCapabilities (PeiServices, SmmAccessPpi, &Size, SmramRanges); + ASSERT_EFI_ERROR (Status); + + Size /= sizeof (*SmramRanges); + SmramRangeCount = Size; + + /// + /// Assume TSEG is the last range of SMRAM in SmramRanges + /// + SmramRanges += SmramRangeCount - 1; + + /// + /// Search SMRAM on page alignment for the SMM PCH S3 SMRAM Data signature + /// + for (Address = (UINT32)(SmramRanges->CpuStart + SmramRanges->PhysicalSize - EFI_PAGE_SIZE); + Address >= (UINT32)SmramRanges->CpuStart; + Address -= EFI_PAGE_SIZE + ) { + S3DispatchArray = (EFI_PCH_S3_DISPATCH_ARRAY *)(UINTN)Address; + if (CompareGuid (&S3DispatchArray->PchS3CustomScriptGuid, &gS3SupportSmramDataGuid)) { + /// + /// Find it + /// + Found = TRUE; + break; + } + } + + /// + /// Close all SMM regions + /// + Index = 0; + do { + Status = SmmAccessPpi->Close (PeiServices, SmmAccessPpi, Index); + Index++; + } while (!EFI_ERROR (Status)); + + + if (!Found) + { + DEBUG ((EFI_D_INFO, "S3 Dispatch Data Not Found!\n")); + return EFI_NOT_FOUND; + } + + /// + /// Generate Hob from SMRAM Data + /// + Status = (*PeiServices)->CreateHob ( + PeiServices, + EFI_HOB_TYPE_GUID_EXTENSION, + EFI_PAGE_SIZE, + &GuidHob + ); + + if (!EFI_ERROR (Status)) { + DEBUG ((EFI_D_INFO, "PchS3Peim S3 Data Hob created: Address - 0x%x\n", (UINTN)GuidHob)); + + GuidHob->Header.Name = gS3DataHobGuid; + CopyMem (&GuidHob->S3DispatchDataArray, S3DispatchArray, S3DispatchArray->MaximumBufferSize); + + /// + /// Reset the NextDispatchItem to the beginning of the buffer for playback. + /// + S3DispatchArray = (EFI_PCH_S3_DISPATCH_ARRAY *)(UINTN)&GuidHob->S3DispatchDataArray; + S3DispatchArray->NextDispatchItem = (UINT8 *)S3DispatchArray + QWORD_ALIGNED_SIZE(EFI_PCH_S3_DISPATCH_ARRAY); + + } + + DEBUG ((EFI_D_INFO, "CreateS3DataHob() End\n")); + + return EFI_SUCCESS; +} + + +#define AZALIA_MAX_LOOP_TIME 10 +#define AZALIA_WAIT_PERIOD 100 + +/** + Polling the Status bit + + @param[in] StatusReg The regsiter address to read the status + @param[in] PollingBitMap The bit mapping for polling + @param[in] PollingData The Data for polling + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_TIMEOUT Polling the bit map time out +**/ +static +EFI_STATUS +CodecStatusPolling ( + IN UINT32 StatusReg, + IN UINT16 PollingBitMap, + IN UINT16 PollingData + ) +{ + UINT32 LoopTime; + + for (LoopTime = 0; LoopTime < AZALIA_MAX_LOOP_TIME; LoopTime++) { + if ((MmioRead16 (StatusReg) & PollingBitMap) == PollingData) { + break; + } else { + PchPmTimerStall (AZALIA_WAIT_PERIOD); + } + } + + if (LoopTime >= AZALIA_MAX_LOOP_TIME) { + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +/** + Send Codec command on S3 resume + + @param[in] Parameter Parameters passed in from DXE + + @retval EFI_DEVICE_ERROR Device status error, operation failed + @retval EFI_SUCCESS The function completed successfully +**/ +EFI_STATUS +PchS3SendCodecCommand ( + EFI_PCH_S3_PARAMETER_SEND_CODEC_COMMAND *Parameter + ) +{ + UINT32 HdaBar; + UINT32 *CodecCommandData; + EFI_STATUS Status; + + HdaBar = Parameter->HdaBar; + CodecCommandData = &Parameter->CodecCmdData; + + DEBUG ((EFI_D_INFO, "Going to SendCodecCommand: %08x! \n", *CodecCommandData)); + Status = CodecStatusPolling (HdaBar + R_HDA_IRS, (UINT16) B_HDA_IRS_ICB, (UINT16) 0); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "ICB bit is not zero before SendCodecCommand! \n")); + return EFI_DEVICE_ERROR; + } + + MmioWrite32 (HdaBar + R_HDA_IC, *CodecCommandData); + MmioOr16 ((UINTN) (HdaBar + R_HDA_IRS), (UINT16) ((B_HDA_IRS_IRV | B_HDA_IRS_ICB))); + + Status = CodecStatusPolling (HdaBar + R_HDA_IRS, (UINT16) B_HDA_IRS_ICB, (UINT16) 0); + if (EFI_ERROR (Status)) { + MmioAnd16 ((UINTN) (HdaBar + R_HDA_IRS), (UINT16)~(B_HDA_IRS_ICB)); + DEBUG ((EFI_D_ERROR, "SendCodecCommand: SendCodecCommand:%08x fail! \n")); + return Status; + } + + return EFI_SUCCESS; +} + +/** + Perform Init Root Port Downstream devices on S3 resume + + @param[in] Parameter Parameters passed in from DXE + + @retval EFI_STATUS +**/ +EFI_STATUS +PchS3InitPcieRootPortDownstream ( + EFI_PCH_S3_PARAMETER_INIT_PCIE_ROOT_PORT_DOWNSTREAM *Parameter + ) +{ + EFI_STATUS Status; + + Status = PchPcieInitRootPortDownstreamDevices ( + Parameter->RootPortBus, + Parameter->RootPortDevice, + Parameter->RootPortFunc, + Parameter->TempBusNumberMin, + Parameter->TempBusNumberMax, + NULL + ); + /// + /// Not checking the error status here - downstream device not present does not + /// mean an error of this root port. Our return status of EFI_SUCCESS means this + /// port is enabled and outer function depends on this return status to do + /// subsequent initializations. + /// + return Status; +} + +/** + Perform Root Port Downstream devices PCIE ASPM and LTR override on S3 resume + + @param[in] Parameter Parameters passed in from DXE + + @retval EFI_STATUS +**/ +EFI_STATUS +PchS3PcieSetPm ( + EFI_PCH_S3_PARAMETER_PCIE_SET_PM *Parameter + ) +{ + EFI_STATUS Status; + PCH_PCIE_DEVICE_ASPM_OVERRIDE *DevAspmOverride; + PCH_PCIE_DEVICE_LTR_OVERRIDE *DevLtrOverride; + PCH_PCIE_PWR_OPT *S3PchPwrOptPcie; + BOOLEAN L1SubstatesSupported; + BOOLEAN LtrSupported; + + DevAspmOverride = (PCH_PCIE_DEVICE_ASPM_OVERRIDE *) (UINTN) Parameter->DevAspmOverrideAddr; + DevLtrOverride = (PCH_PCIE_DEVICE_LTR_OVERRIDE *) (UINTN) Parameter->DevLtrOverrideAddr; + S3PchPwrOptPcie = (PCH_PCIE_PWR_OPT *) (UINTN) Parameter->PchPwrOptPcie; + Status = PcieSetPm ( + Parameter->RootPortBus, + Parameter->RootPortDevice, + Parameter->RootPortFunc, + Parameter->RootPortAspm, + Parameter->NumOfDevAspmOverride, + DevAspmOverride, + Parameter->TempBusNumberMin, + Parameter->TempBusNumberMax, + Parameter->NumOfDevLtrOverride, + DevLtrOverride, + S3PchPwrOptPcie, + &L1SubstatesSupported, + Parameter->L1SubstatesConfig, + Parameter->PolicyRevision, + Parameter->FirstRPToSetPm, + Parameter->L1SupportedInAllEnabledPorts, + Parameter->ClkreqSupportedInAllEnabledPorts, + &LtrSupported + ); + /// + /// Not checking the error status here - downstream device not present does not + /// mean an error of this root port. Our return status of EFI_SUCCESS means this + /// port is enabled and outer function depends on this return status to do + /// subsequent initializations. + /// + return Status; +} + +/** + Perform PCH IOBP programming on S3 resume + + @param[in] Parameter Parameters passed in from DXE + + @retval EFI_STATUS +**/ +EFI_STATUS +PchS3ProgramIobp ( + EFI_PCH_S3_PARAMETER_PROG_IOBP *Parameter + ) +{ + EFI_STATUS Status; + + Status = ProgramIobp ( + Parameter->RootComplexBar, + Parameter->Address, + Parameter->AndMask, + Parameter->OrMask + ); + + return Status; +} diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.cif b/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.cif new file mode 100644 index 0000000..d19743c --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.cif @@ -0,0 +1,13 @@ +<component> + name = "PchS3Peim" + category = ModulePart + LocalRoot = "ReferenceCode\Chipset\LynxPoint\S3Support\Pei" + RefName = "PchS3Peim" +[files] +"PchS3Peim.sdl" +"PchS3Peim.mak" +"PchS3Peim.h" +"PchS3Peim.c" +"PchS3Peim.dxs" +"PchS3Peim.inf" +<endComponent>
\ No newline at end of file diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.dxs b/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.dxs new file mode 100644 index 0000000..fbeaa9b --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.dxs @@ -0,0 +1,41 @@ +/** @file + Dispatch dependency expression file for the PchS3Peim driver. + +@copyright + Copyright (c) 1999 - 2015 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ + +// +// Common for R8 and R9 codebase +// +#include "AutoGen.h" +#include "PeimDepex.h" +// +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase; +// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase. +// +#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB) +#include "EfiDepex.h" + +#include "Common/EdkIIGlueDefinitionChangesPeim.h" +#include EFI_PPI_DEFINITION (BootMode) + +#endif + +DEPENDENCY_START + PEI_MASTER_BOOT_MODE_PEIM_PPI +DEPENDENCY_END diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.h b/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.h new file mode 100644 index 0000000..133904a --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.h @@ -0,0 +1,106 @@ +/** @file + This is the PEIM that performs the S3 resume tasks. + +@copyright + Copyright (c) 2008 - 2015 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _PCH_S3_PEIM_H_ +#define _PCH_S3_PEIM_H_ + +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGluePeim.h" +#include "PchAccess.h" +#include "PchPlatformLib.h" +#include "PchPlatformPolicy.h" +#include "PchPciExpressHelpersLib.h" +#include EFI_PROTOCOL_CONSUMER (PchS3Support) +#include EFI_PPI_DEPENDENCY (Variable) +#include EFI_PPI_DEPENDENCY (SmmAccess) + +#endif + +#define EFI_PCH_S3_STALL_INTERVAL 50 ///< us + +/** +This routine is used to search SMRAM and get SmramCpuData point. + +@param[in] PeiServices - PEI services global pointer +@param[in] SmmAccessPpi - SmmAccess PPI instance + +@retval SmramCpuData - The pointer of CPU information in SMRAM. +**/ +EFI_STATUS +CreateS3DataHob ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Interface + ); + +/** + Send Codec command on S3 resume + + @param[in] Parameter Parameters passed in from DXE + + @retval EFI_DEVICE_ERROR Device status error, operation failed + @retval EFI_SUCCESS The function completed successfully +**/ +EFI_STATUS +PchS3SendCodecCommand ( + EFI_PCH_S3_PARAMETER_SEND_CODEC_COMMAND *Parameter + ); + +/** + Perform Init Root Port Downstream devices on S3 resume + + @param[in] Parameter Parameters passed in from DXE + + @retval EFI_STATUS +**/ +EFI_STATUS +PchS3InitPcieRootPortDownstream ( + EFI_PCH_S3_PARAMETER_INIT_PCIE_ROOT_PORT_DOWNSTREAM *Parameter + ); + +/** + Perform Root Port Downstream devices PCIE ASPM and LTR override on S3 resume + + @param[in] Parameter Parameters passed in from DXE + + @retval EFI_STATUS +**/ +EFI_STATUS +PchS3PcieSetPm ( + EFI_PCH_S3_PARAMETER_PCIE_SET_PM *Parameter + ); + +/** + Perform PCH IOBP programming on S3 resume + + @param[in] Parameter Parameters passed in from DXE + + @retval EFI_STATUS +**/ +EFI_STATUS +PchS3ProgramIobp ( + EFI_PCH_S3_PARAMETER_PROG_IOBP *Parameter + ); + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.inf b/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.inf new file mode 100644 index 0000000..498fde8 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.inf @@ -0,0 +1,100 @@ +## @file +# Component description file for PchS3 PEIM +# This is the PEIM that performs the S3 resume tasks as instructed by +# PCH Init DXE driver. This PEIM is NOT dispatched by PEI Core, but is rather +# dispatched by the S3 Boot Script Engine. It is the responsibility of PCH +# Init DXE driver to load this PEIM and register its entry point to the +# Boot Script engine. This PEIM consumes the PCH Init Variable. +# +#@copyright +# Copyright (c) 1999 - 2015 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +[defines] +BASE_NAME = PchS3Peim +FILE_GUID = 271DD6F2-54CB-45e6-8585-8C923C1AC706 +COMPONENT_TYPE = PE32_PEIM + +[sources.common] + PchS3Peim.h + PchS3Peim.c +# +# Edk II Glue Driver Entry Point +# + EdkIIGluePeimEntryPoint.c + +[includes.common] + . + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Pei/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT) + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include/Library + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Protocol + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Protocol/PchPlatformPolicy + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Protocol/PchS3Support + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Guid/S3SupportHob + +# +# EDK II Glue Library utilizes some standard headers from EDK +# + $(EFI_SOURCE) + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Pei/Include + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include +# +# Typically the sample code referenced will be available in the code base already +# So keep this include at the end to defer to the source base definition +# and only use the sample code definition if source base does not include these files. +# + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/SampleCode + +[libraries.common] + PchPlatformLib + PchPciExpressHelpersLib + EdkFrameworkPpiLib + EdkIIGlueBaseIoLibIntrinsic + EdkIIGluePeiDebugLibReportStatusCode + EdkIIGluePeiReportStatusCodeLib + EdkIIGluePeiServicesLib + EdkIIGluePeiMemoryAllocationLib + EdkIIGlueBasePciLibPciExpress + EdkIIGluePeiHobLib + EdkPpiLib + IntelPchSampleCodePpiLib + PeiLib + +[nmake.common] + IMAGE_ENTRY_POINT=_ModuleEntryPoint + DPX_SOURCE=PchS3Peim.dxs +# +# Module Entry Point +# + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=InitializePchS3Peim + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \ + -D __EDKII_GLUE_PEI_DEBUG_LIB_REPORT_STATUS_CODE__ \ + -D __EDKII_GLUE_PEI_REPORT_STATUS_CODE_LIB__ \ + -D __EDKII_GLUE_PEI_SERVICES_LIB__ \ + -D __EDKII_GLUE_PEI_MEMORY_ALLOCATION_LIB__ \ + -D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.mak b/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.mak new file mode 100644 index 0000000..aac60c4 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.mak @@ -0,0 +1,52 @@ +#--------------------------------------------------------------------------- +# Create PchS3Pei module +#--------------------------------------------------------------------------- +EDK : PchS3Peim +PchS3Peim : $(BUILD_DIR)\PchS3Peim.mak PchS3PeimBin + + +$(BUILD_DIR)\PchS3Peim.mak : $(PchS3Peim_DIR)\$(@B).cif $(PchS3Peim_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(PchS3Peim_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +PchS3Peim_INCLUDES=\ + $(EdkIIGlueLib_INCLUDES)\ + $(INTEL_PCH_INCLUDES)\ + +PchS3Peim_DEFINES = $(MY_DEFINES)\ + /D"__EDKII_GLUE_MODULE_ENTRY_POINT__=InitializePchS3Peim"\ + /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \ + /D __EDKII_GLUE_PEI_DEBUG_LIB_REPORT_STATUS_CODE__ \ + /D __EDKII_GLUE_PEI_REPORT_STATUS_CODE_LIB__ \ + /D __EDKII_GLUE_PEI_SERVICES_LIB__ \ + /D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ \ + /D __EDKII_GLUE_PEI_HOB_LIB__ \ + +PchS3Peim_LIB_LINKS=\ + $(IntelPchPpiLib_LIB)\ + $(EdkIIGlueBaseLib_LIB)\ + $(EdkIIGlueBaseLibIA32_LIB)\ + $(EdkIIGlueBaseIoLibIntrinsic_LIB)\ + $(EdkIIGluePeiDebugLibReportStatusCode_LIB)\ + $(EdkIIGluePeiReportStatusCodeLib_LIB)\ + $(EdkIIGluePeiServicesLib_LIB) \ + $(EdkIIGlueBasePciLibPciExpress_LIB)\ + $(WdtCommonPeiLib_LIB)\ + $(EDKFRAMEWORKPPILIB)\ + $(EdkIIGluePeiHobLib_LIB)\ + $(IntelSaSampleCodePpiLib_LIB)\ + $(PchPlatformPeiLib_LIB)\ + $(PchPciExpressHelpersPeiLib_LIB)\ + $(PEILIB)\ + +PchS3PeimBin: $(PchS3Peim_LIB_LINKS) + $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\ + /f $(BUILD_DIR)\PchS3Peim.mak all \ + "MY_INCLUDES=$(PchS3Peim_INCLUDES)"\ + "MY_DEFINES=$(PchS3Peim_DEFINES)"\ + GUID=271DD6F2-54CB-45e6-8585-8C923C1AC706\ + ENTRY_POINT=_ModuleEntryPoint \ + TYPE=PEIM \ + EDKIIModule=PEIM\ + DEPEX1=$(PchS3Peim_DIR)\PchS3Peim.dxs\ + DEPEX1_TYPE=EFI_SECTION_PEI_DEPEX\ + COMPRESS=0
\ No newline at end of file diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.sdl b/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.sdl new file mode 100644 index 0000000..13198b4 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Pei/PchS3Peim.sdl @@ -0,0 +1,75 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2015, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/S3Support/Pei/PchS3Peim.sdl 1 5/21/15 2:56a Dennisliu $ +# +# $Revision: 1 $ +# +# $Date: 5/21/15 2:56a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/S3Support/Pei/PchS3Peim.sdl $ +# +# 1 5/21/15 2:56a Dennisliu +# [TAG] EIP217847 +# [Category] Improvement +# [Description] [PCH] Shark Bay-M/DT Reference Code Production Version +# 1.9.1 +# [Files] PchS3Peim.sdl +# PchS3Peim.mak +# PchS3Peim.h +# PchS3Peim.c +# PchS3Peim.dxs +# PchS3Peim.inf +# +#************************************************************************* +TOKEN + Name = "PchS3Peim_SUPPORT" + Value = "1" + Help = "Main switch to enable PchS3Peim support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes +End + +PATH + Name = "PchS3Peim_DIR" +End + +MODULE + File = "PchS3Peim.mak" + Help = "Includes PchS3Peim.mak to Project" +End + +ELINK + Name = "$(BUILD_DIR)\PchS3Peim.ffs" + Parent = "FV_BB" + InvokeOrder = AfterParent +End +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2015, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.c b/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.c new file mode 100644 index 0000000..b08699d --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.c @@ -0,0 +1,156 @@ +/** @file + PCH S3 Support Protocol SMM Driver Entry + +@copyright + Copyright (c) 2015 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#include "S3SupportSmm.h" + + +// +// Global Variables +// +UINT16 mS3SupportIoTrapAddress; +EFI_SMM_SYSTEM_TABLE *mSmst; +EFI_SMM_BASE_PROTOCOL *mSmmBase; +EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL *mPchIoTrap; +EFI_HANDLE mImageHandle; +EFI_PCH_S3_SUPPORT_SMM_PROTOCOL *mPchS3SupportSmmProtocol; +EFI_HANDLE mPchIoTrapHandle; + +/** + An IO Trap SMI callback to copy the DispatchArray data to SMRAM and unregister the IO Trap. + + @param[in] DispatchHandle - The handle of this callback, obtained when registering + @param[in] DispatchContext - Pointer to the EFI_SMM_IO_TRAP_DISPATCH_CALLBACK_CONTEXT + + @retval None +**/ +VOID +S3SupportSmmExitPmAuthCallback ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_IO_TRAP_DISPATCH_CALLBACK_CONTEXT *CallbackContext + ) +{ + EFI_PHYSICAL_ADDRESS Address; + EFI_STATUS Status; + + DEBUG ((EFI_D_INFO, "S3SupportSmmExitPmAuthCallback() Start\n")); + + /// + /// Allocate SMRAM memory for the PCH S3 Custom Dispatch Script + /// + Status = mSmst->SmmAllocatePages ( + AllocateAnyPages, + EfiRuntimeServicesData, + mPchS3SupportSmmProtocol->ProtocolSize, + &Address + ); + DEBUG ((EFI_D_INFO, "SMRAM Memory Allocation Failed - S3SupportSmmExitPmAuthCallback()\n")); + ASSERT_EFI_ERROR (Status); + + /// + /// Copy S3 Support Data from Boot Services memory to SMRAM + /// + CopyMem ((VOID *)Address, mPchS3SupportSmmProtocol->DispatchArray, mPchS3SupportSmmProtocol->ProtocolSize * EFI_PAGE_SIZE); + + /// + /// Unregister the IO Trap as the copy to SMRAM is only allowed once + /// + Status = mPchIoTrap->UnRegister ( + mPchIoTrap, + &mPchIoTrapHandle + ); + DEBUG ((EFI_D_INFO, "IO Trap Unregister Failed - S3SupportSmmExitPmAuthCallback()\n")); + ASSERT_EFI_ERROR (Status); + + /// + /// Clear the NextDispatchItem in the Boot Services Memory so as to cause an error + /// if an entity tries to use the Protocol to add more data after the copy to SMRAM. + /// + mPchS3SupportSmmProtocol->DispatchArray->NextDispatchItem = NULL; + + DEBUG ((EFI_D_INFO, "S3SupportSmmExitPmAuthCallback() End\n")); + + return; +} + +/** + Initializes the PCH SMM handler for PCH save and restore + + @param[in] ImageHandle - Handle for the image of this driver + @param[in] SystemTable - Pointer to the EFI System Table + + @retval EFI_SUCCESS - PCH SMM handler was installed +**/ +EFI_STATUS +S3SupportSmmEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_SMM_IO_TRAP_DISPATCH_REGISTER_CONTEXT PchIoTrapContext; + + DEBUG ((EFI_D_INFO, "S3SupportSmmEntryPoint() Start\n")); + + mImageHandle = NULL; + + /// + /// Locate SmmBase protocol + /// + Status = gBS->LocateProtocol (&gEfiSmmBaseProtocolGuid, NULL, (VOID **)&mSmmBase); + ASSERT_EFI_ERROR (Status); + + /// + /// Initialize our module variables + /// + Status = mSmmBase->GetSmstLocation (mSmmBase, &mSmst); + ASSERT_EFI_ERROR (Status); + + /// + /// Locate the PCH S3 SMM Support protocol + /// + Status = gBS->LocateProtocol (&gEfiPchS3SupportSmmProtocolGuid, NULL, (void **)&mPchS3SupportSmmProtocol); + ASSERT_EFI_ERROR (Status); + + /// + /// Locate the PCH Trap dispatch protocol + /// + Status = gBS->LocateProtocol (&gEfiSmmIoTrapDispatchProtocolGuid, NULL, &mPchIoTrap); + ASSERT_EFI_ERROR (Status); + + PchIoTrapContext.Type = WriteTrap; + PchIoTrapContext.Length = 4; + PchIoTrapContext.Address = 0; + PchIoTrapContext.Context = NULL; + PchIoTrapContext.MergeDisable = FALSE; + Status = mPchIoTrap->Register ( + mPchIoTrap, + S3SupportSmmExitPmAuthCallback, + &PchIoTrapContext, + &mPchIoTrapHandle + ); + ASSERT_EFI_ERROR (Status); + + mPchS3SupportSmmProtocol->PchS3SupportIoTrap = PchIoTrapContext.Address; + + DEBUG ((EFI_D_INFO, "Pch S3 Support IO Trap Address = 0x%x\n", PchIoTrapContext.Address)); + DEBUG ((EFI_D_INFO, "S3SupportSmmEntryPoint() End\n")); + + return Status; +} diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.cif b/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.cif new file mode 100644 index 0000000..9bee2a2 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.cif @@ -0,0 +1,13 @@ +<component> + name = "S3SupportSmm" + category = ModulePart + LocalRoot = "ReferenceCode\Chipset\LynxPoint\S3Support\Smm" + RefName = "S3SupportSmm" +[files] +"S3SupportSmm.sdl" +"S3SupportSmm.mak" +"S3SupportSmm.c" +"S3SupportSmm.h" +"S3SupportSmm.dxs" +"S3SupportSmm.inf" +<endComponent>
\ No newline at end of file diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.dxs b/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.dxs new file mode 100644 index 0000000..b8218d4 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.dxs @@ -0,0 +1,46 @@ +/** @file + Dependency expression source file. + +@copyright + Copyright (c) 2015 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ + +// +// Common for R8 and R9 codebase +// +#include "AutoGen.h" +#include "DxeDepex.h" + +// +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase; +// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase. +// +#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB) +#include "EfiDepex.h" + +#include EFI_PROTOCOL_DEPENDENCY (SmmBase) +#include EFI_PROTOCOL_DEPENDENCY (SmmIoTrapDispatch) +#include EFI_PROTOCOL_DEPENDENCY (PchS3Support) + + +#endif + +DEPENDENCY_START + EFI_SMM_BASE_PROTOCOL_GUID AND + EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL_GUID AND + EFI_PCH_S3_SUPPORT_SMM_PROTOCOL_GUID +DEPENDENCY_END diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.h b/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.h new file mode 100644 index 0000000..1ac0dc7 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.h @@ -0,0 +1,60 @@ +/** @file + Header file for PCH SMM Handler + +@copyright + Copyright (c) 2015 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ + +#ifndef _PCHLATEINITSMM_H_ +#define _PCHLATEINITSMM_H_ + +/// +/// External include files do NOT need to be explicitly specified in real EDKII +/// environment +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGlueDxe.h" +#include "PchAccess.h" +#include "PchPlatformLib.h" + +/// +/// Driver Consumed Protocol Prototypes +/// +#include EFI_PROTOCOL_DEPENDENCY (PchS3Support) +#include EFI_PROTOCOL_DEPENDENCY (SmmBase) +#include EFI_PROTOCOL_DEPENDENCY (SmmIoTrapDispatch) +#include EFI_PROTOCOL_DEPENDENCY (SmmSxDispatch) +#include EFI_PROTOCOL_CONSUMER (ExitPmAuth) + + +#endif + +/** + An IO Trap SMI callback to copy the DispatchArray data to SMRAM and unregister the IO Trap. + + @param[in] DispatchHandle - The handle of this callback, obtained when registering + @param[in] DispatchContext - Pointer to the EFI_SMM_IO_TRAP_DISPATCH_CALLBACK_CONTEXT + + @retval None +**/ +VOID +S3SupportSmmExitPmAuthCallback ( + EFI_EVENT Event, + VOID *ParentImageHandle +); + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.inf b/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.inf new file mode 100644 index 0000000..b45f322 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.inf @@ -0,0 +1,95 @@ +## @file +# Component description file for Pch Initialization driver +# +#@copyright +# Copyright (c) 2015 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +[defines] +BASE_NAME = S3SupportSmm +FILE_GUID = BFBEDBD4-1B7E-42f5-A528-4351E860F120 +COMPONENT_TYPE = BS_DRIVER + +[sources.common] + S3SupportSmm.c + S3SupportSmm.h + +# +# Edk II Glue Driver Entry Point +# + EdkIIGlueSmmDriverEntryPoint.c +[includes.common] + $(EDK_SOURCE)/Foundation/Efi + . + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EDK_SOURCE)/Foundation/Framework/Guid/Hob + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT) + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include/Library + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Guid/S3SupportHob + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Protocol + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Protocol/PchPlatformPolicy + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Protocol/PchS3Support +# +# EDK II Glue Library utilizes some standard headers from EDK +# + $(EFI_SOURCE) + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + $(EDK_SOURCE)/Foundation/Framework/Protocol +# +# Typically the sample code referenced will be available in the code base already +# So keep this include at the end to defer to the source base definition +# and only use the sample code definition if source base does not include these files. +# + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/SampleCode + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/SampleCode/Include + +[libraries.common] + EdkFrameworkProtocolLib + $(PROJECT_PCH_FAMILY)ProtocolLib + PchPlatformLib + EdkIIGlueDxeDebugLibReportStatusCode + EdkIIGlueSmmRuntimeDxeReportStatusCodeLib + EdkIIGlueUefiBootServicesTableLib + EdkIIGlueUefiRuntimeServicesTableLib + EdkIIGlueDxeServicesTableLib + EdkIIGlueDxeMemoryAllocationLib + EdkIIGlueDxeHobLib + EdkProtocolLib + EfiScriptLib + EfiGuidLib + +[nmake.common] + IMAGE_ENTRY_POINT=_ModuleEntryPoint + DPX_SOURCE=S3SupportSmm.dxs +# +# Module Entry Point +# + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=S3SupportSmmEntryPoint + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \ + -D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \ + -D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \ + -D __EDKII_GLUE_SMM_RUNTIME_DXE_REPORT_STATUS_CODE_LIB__ \ + -D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \ + -D __EDKII_GLUE_DXE_MEMORY_ALLOCATION_LIB__ \ + -D __EDKII_GLUE_DXE_HOB_LIB__
\ No newline at end of file diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.mak b/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.mak new file mode 100644 index 0000000..c91012e --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.mak @@ -0,0 +1,94 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2015, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/S3Support/Smm/S3SupportSmm.mak 1 5/21/15 3:01a Dennisliu $Revision: +# +# $Date: 5/21/15 3:01a $Log: +# +#************************************************************************* + +#--------------------------------------------------------------------------- +# Create S3SupportSmm Driver +#--------------------------------------------------------------------------- +EDK : S3SupportSmm +S3SupportSmm : $(BUILD_DIR)\S3SupportSmm.mak S3SupportSmmBin + + +$(BUILD_DIR)\S3SupportSmm.mak : $(S3SupportSmm_DIR)\$(@B).cif $(S3SupportSmm_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(S3SupportSmm_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +S3SupportSmm_INCLUDES=\ + $(INTEL_PCH_INCLUDES)\ + $(EdkIIGlueLib_INCLUDES)\ + +S3SupportSmm_DEFINES = $(MY_DEFINES)\ + /D"__EDKII_GLUE_MODULE_ENTRY_POINT__=S3SupportSmmEntryPoint"\ + /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \ + /D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \ + /D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \ + /D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \ + /D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \ + /D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ \ + /D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \ + +S3SupportSmm_LIB_LINKS =\ + $(EDKFRAMEWORKPROTOCOLLIB)\ + $(EDKPROTOCOLLIB)\ + $(PchPlatformDxeLib_LIB)\ + $(EFISCRIPTLIB) $(EFIPROTOCOLLIB)\ + $(INTEL_PCH_PROTOCOL_LIB)\ + $(EdkIIGlueBaseLib_LIB)\ +!IF "$(x64_BUILD)"=="1" + $(EdkIIGlueBaseLibX64_LIB)\ +!ELSE + $(EdkIIGlueBaseLibIA32_LIB)\ +!ENDIF + $(EdkIIGlueBaseIoLibIntrinsic_LIB)\ + $(EdkIIGlueDxeReportStatusCodeLib_LIB)\ + $(EdkIIGlueDxeDebugLibReportStatusCode_LIB)\ + $(EdkIIGlueUefiBootServicesTableLib_LIB)\ + $(EdkIIGlueDxeServicesTableLib_LIB)\ + $(PchS3SupportCommonDxeLib_LIB)\ + $(EdkIIGlueBasePciLibPciExpress_LIB)\ + $(EdkIIGlueUefiRuntimeServicesTableLib_LIB)\ + $(EFIDRIVERLIB)\ + $(EdkIIGlueUefiDevicePathLib_LIB)\ + $(EdkIIGlueUefiLib_LIB)\ + +S3SupportSmmBin: $(S3SupportSmm_LIB_LINKS) + $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\ + /f $(BUILD_DIR)\S3SupportSmm.mak all \ + "MY_INCLUDES=$(S3SupportSmm_INCLUDES)"\ + "MY_DEFINES=$(S3SupportSmm_DEFINES)"\ + GUID=BFBEDBD4-1B7E-42f5-A528-4351E860F120\ + ENTRY_POINT=_ModuleEntryPoint \ + TYPE=BS_DRIVER\ + EDKIIModule=SMMDRIVER\ + DEPEX1=$(S3SupportSmm_DIR)\S3SupportSmm.dxs\ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\ + COMPRESS=1 +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2015, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.sdl b/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.sdl new file mode 100644 index 0000000..1a812ec --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/S3Support/Smm/S3SupportSmm.sdl @@ -0,0 +1,57 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2015, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/S3Support/Smm/S3SupportSmm.sdl 1 5/21/15 3:01a Dennisliu $Revision: +# +# $Date: 5/21/15 3:01a $Log: +# +#************************************************************************* +TOKEN + Name = "S3SupportSmm_SUPPORT" + Value = "1" + Help = "Main switch to enable S3SupportSmm support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes +End + +PATH + Name = "S3SupportSmm_DIR" +End + +MODULE + Help = "Includes S3SupportSmm.mak to Project" + File = "S3SupportSmm.mak" +End + +ELINK + Name = "$(BUILD_DIR)\S3SupportSmm.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2015, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file |