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Diffstat (limited to 'ReferenceCode/Chipset/LynxPoint/SampleCode')
31 files changed, 5481 insertions, 0 deletions
diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/AcpiTables/Dsdt/Sensor.asl b/ReferenceCode/Chipset/LynxPoint/SampleCode/AcpiTables/Dsdt/Sensor.asl new file mode 100644 index 0000000..3b61882 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/AcpiTables/Dsdt/Sensor.asl @@ -0,0 +1,103 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the SandyBridge *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + + //-------------------- + // Intel Sensor Solution + //-------------------- + Name (_ADR, Zero) + Name (_UID, One) + + Method (_STA, 0, NotSerialized) + { + // check for device enabled in BIOS setup, 1 = enabled + If(LNotEqual(And(SDS0,0x01), 0x01)) { + Return (0x00) // device is disabled in BIOS setup + } + + // check the GPIO mode select, 1 = Sensor Hub + // verify the Sensor Hub _HID + If(LAnd(LEqual(\_SB.RDGP(44), 0x01),LEqual(_HID, "INT33D1"))) { + Return(0xF) // device is Sensor Hub and Sensor Hub mode is selected + } + + // check the GPIO mode select, 0 = DFU + // verify the DFU _HID + If(LAnd(LEqual(\_SB.RDGP(44), 0x00),LEqual(_HID, "INT33D7"))) { + Return(0xF) // device is DFU and DFU mode is selected + } + + Return(0x00) + } + + Method(_DSM, 0x4, NotSerialized) + { + // DSM UUID for HIDI2C. Do Not change. + If(LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) + { + // Function 0 : Query Function + If(LEqual(Arg2, Zero)) + { + // Revision 1 + If(LEqual(Arg1, One)) + { + Return(Buffer(One) { 0x03 }) + } + } + // Function 1 : HID Function + If(LEqual(Arg2, One)) + { + // HID Descriptor Address (IHV Specific) + Return(0x0001) + } + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + + Method (_CRS, 0, NotSerialized) + { + Name (SBFI, ResourceTemplate () + { + I2cSerialBus ( + 0x40, //SlaveAddress: bus address + ControllerInitiated, //SlaveMode: Default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + AddressingMode7Bit, //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C0", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + + Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , ,) {28} //Route to PIRQM + }) + + Return (SBFI) + } + diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/AcpiTables/Dsdt/SerialIoDevices.asl b/ReferenceCode/Chipset/LynxPoint/SampleCode/AcpiTables/Dsdt/SerialIoDevices.asl new file mode 100644 index 0000000..b344520 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/AcpiTables/Dsdt/SerialIoDevices.asl @@ -0,0 +1,1527 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the SandyBridge *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +Scope (\_SB.PCI0) +{ + External(\_SB.PCI0.SDHC.WI01.PS0X, MethodObj) + External(\_SB.PCI0.SDHC.WI01.PS3X, MethodObj) + External(\_SB.PCI0.I2C1.TPD7.PS0X, MethodObj) + External(\_SB.PCI0.I2C1.TPD8.PS0X, MethodObj) + + +} // end scope \_SB.PCI0 + +Scope(\_SB.PCI0.I2C0) +{ + + //-------------------- + // Audio Codec device + // Realtek + //-------------------- + Device (ACD0) + { + // I2C/I2S Audio Codec (Realtek as default) + Name (_ADR, 0x1C) + Name (_HID, "INT33CA") + Name (_CID, "INT33CA") + Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec - INT33CA" ) + Name (_UID, 1) + + // Parameter values for Realtek codec + Name (MCLK, Zero) + Name (SCLK, 0x9) + Name (SSPM, Zero) + + Name (RBUF, ResourceTemplate () + { + I2CSerialBus( + 0x1C, //SlaveAddress: bus address + , //SlaveMode: default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + , //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C0", //ResourceSource: I2C bus controller name + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + + Interrupt(ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, , ,) {37} //Route to PIRQx - jack detection + }) + + Name(EOD, 1) + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + + Method (_SRS, 0x1, Serialized) + { + Store (1, EOD) + } + + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LNotEqual(CODS, Zero), LNotEqual(ADSD, Zero))) + { + Return(0x0) // Codec Selection != Realtek or ADSP disabled - Not present + } + If (AND(EOD, 0x1, EOD)) + { + Return(0xf) // Enabled 1111 + } + Else + { + Return(0xd) // Disabled 1101 + } + } + + Method (_DIS, 0x0, NotSerialized) + { + Store(0, EOD) + } + } // Device (ACD0) + + //-------------------- + // Audio Codec device + // Cirrus Logic + //-------------------- + Device (ACD1) + { + Name (_ADR, 0x4A) + Name (_HID, "INT33C9") + Name (_CID, "INT33C9") + Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec - INT33C9" ) + Name (_UID, 1) + + // Parameter values for Cirrus codec + Name (MCLK, 0x6) + Name (SCLK, Zero) + Name (SSPM, One) + + Name (RBUF, ResourceTemplate () + { + I2CSerialBus( + 0x4A, //SlaveAddress: bus address + , //SlaveMode: default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + , //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C0", //ResourceSource: I2C bus controller name + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + }) + + Name(EOD, 1) + Method (_CRS, 0x0, NotSerialized) + { + Store (1, EOD) + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LNotEqual(CODS, One), LNotEqual(ADSD, Zero))) + { + Return(0x0) // Codec Selection != Cirrus or ADSP disabled - Not present + } + If (AND(EOD, 0x1, EOD)) + { + Return(0xf) // Enabled 1111 + } + Else + { + Return(0xd) // Disabled 1101 + } + } + + Method (_DIS, 0x0, NotSerialized) + { + Store(0, EOD) + } + } // Device (ACD1) + + //-------------------- + // Audio Codec device + // IDT + //-------------------- + Device (ACD2) + { + Name (_ADR, 0x69) + Name (_HID, "INT33CB") + Name (_CID, "INT33CB") + Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec - INT33CB" ) + Name (_UID, 1) + + // Parameter values for IDT codec + Name (MCLK, 0x18) + Name (SCLK, 0x9) + Name (SSPM, Zero) + + Name (RBUF, ResourceTemplate () + { + I2CSerialBus( + 0x69, //SlaveAddress: bus address + , //SlaveMode: default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + , //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C0", //ResourceSource: I2C bus controller name + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionInputOnly, "\\_SB.PCI0.GPI0", ) {0x33} // GPIO51 for HP detection + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionInputOnly, "\\_SB.PCI0.GPI0", ) {0x35} // GPIO53 for Mic detection + + Interrupt(ResourceConsumer, Edge, ActiveHigh, ExclusiveAndWake, , ,) {35} // GPIO51 - HP jack detection + Interrupt(ResourceConsumer, Edge, ActiveHigh, ExclusiveAndWake, , ,) {37} // GPIO53 - Mic jack detection + }) + + Name(EOD, 1) + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + + Method (_SRS, 0x1, Serialized) + { + Store (1, EOD) + } + + Method (_STA, 0x0, NotSerialized) + { + If (LOr(LNotEqual(CODS, 2), LNotEqual(ADSD, Zero))) + { + Return(0x0) // Codec Selection != IDT or ADSP disabled - Not present + } + If (AND(EOD, 0x1, EOD)) + { + Return(0xf) // Enabled 1111 + } + Else + { + Return(0xd) // Disabled 1101 + } + } + + Method (_DIS, 0x0, NotSerialized) + { + Store(0, EOD) + } + } // Device (ACD2) + + //-------------------- + // Intel Sensor Hub + //-------------------- + Device (SHUB) + { + Name (_HID, "INT33D1") + Name (_CID, "PNP0C50") + Include ("Sensor.asl") + } // Device (SHUB) + + //-------------------- + // Intel DFU Device + //-------------------- + Device (DFUD) + { + Name (_HID, "INT33D7") + Include ("Sensor.asl") + } // Device DFUD + + Device (TPD4) + { + Name (_ADR, Zero) + Name (_HID, "MSFT1111") + Name (_CID, "PNP0C50") + Name (_UID, One) + + Method(_DSM, 0x4, NotSerialized) + { + // DSM UUID for HIDI2C. Do Not change. + If(LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) + { + // Function 0 : Query Function + If(LEqual(Arg2, Zero)) + { + // Revision 1 + If(LEqual(Arg1, One)) + { + Return(Buffer(One) { 0x03 }) + } + } + // Function 1 : HID Function + If(LEqual(Arg2, One)) + { + // HID Descriptor Address (IHV Specific) + Return(0x0001) + } + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + + Method (_STA, 0, NotSerialized) + { + If(LEqual(And(SDS0,0x04), 0x04)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + + Method (_CRS, 0, NotSerialized) + { + Name (SBFI, ResourceTemplate () + { + I2cSerialBus ( + 0x60, //SlaveAddress: bus address + ControllerInitiated, //SlaveMode: Default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + AddressingMode7Bit, //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C0", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + + Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , ,) {28} //Route to PIRQM + }) + + Return (SBFI) + } + + Method (_PRW, 0) { + Return(Package(){0x0E,4}) // can wakeup from S4 state + } + + Method (_S3W, 0) { + Return(3) + } + + Method (_S4W, 0) { + Return(3) + } + + Method(_PS0,0,Serialized) + { + ADBG("TPD4 Ctrlr D0") + // + // Set GPI_INV to normal + // + \_SB.WTIN(14,0) + + // + // Set GPI_OWN to GPIO + // + Store(1,\GO14) + } + + Method(_PS3,0,Serialized) + { + ADBG("TPD4 Ctrlr D3") + // + // Set GPI_INV to Inverted + // + \_SB.WTIN(14,1) + + // + // Set GPI_OWN to ACPI + // + Store(0,\GO14) + } + } // Device (TPD4) + + +} // end Scope(\_SB.PCI0.I2C0) + + + //---------------------------- + // Serial IO I2C1 Controller + //---------------------------- +Scope(\_SB.PCI0.I2C1) +{ + + + //------------------------ + // Atmel Touch Panel + //------------------------ + Device (TPL0) + { + Name (_ADR, Zero) + Name (_HID, "ATML1000") + Name (_CID, "PNP0C50") + Name (_UID, One) + + Name (_S0W, 4) // required to put the device to D3 Cold during S0 idle + + Method(_DSM, 0x4, NotSerialized) + { + // DSM UUID for HIDI2C. Do Not change. + If(LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) + { + // Function 0 : Query Function + If(LEqual(Arg2, Zero)) + { + // Revision 1 + If(LEqual(Arg1, One)) + { + Return(Buffer(One) { 0x03 }) + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + // Function 1 : HID Function + If(LEqual(Arg2, One)) + { + // HID Descriptor Address (IHV Specific) + Return(0x0000) + } + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + + Method (_STA, 0, NotSerialized) + { + // Note: _STA in ATML1000 and ATML2000 must be identical. These devices + // communicate with the same HW. + + If(LEqual(And(SDS1,0x0001), 0x0001)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + + Method (_CRS, 0, NotSerialized) + { + Name (SBFI, ResourceTemplate () + { + I2cSerialBus ( + 0x4C, //SlaveAddress: bus address + ControllerInitiated, //SlaveMode: Default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + AddressingMode7Bit, //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C1", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + + Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , ,) {34} //Interrupt from touch screen routed to GPIO50-->PIRQS + }) + + Return (SBFI) + } + } // Device (TPL0) + + //------------------------ + // Atmel Touch Panel FW Update + //------------------------ + Device (TPFU) + { + Name (_ADR, Zero) + Name (_HID, "ATML2000") + Name (_CID, "PNP0C02") + Name (_UID, 10) + + Method (_STA, 0, NotSerialized) + { + // Note: _STA in ATML1000 and ATML2000 must be identical. These devices + // communicate with the same HW. + + If(LAnd(And(SDS1,0x0001),And(APFU,0x0001))) { + Return (0x0F) + } Else { + Return (0x00) + } + } + + Method (_CRS, 0, NotSerialized) + { + Name (SBFI, ResourceTemplate () + { + I2cSerialBus ( + 0x26, //SlaveAddress: bus address + ControllerInitiated, //SlaveMode: Default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + AddressingMode7Bit, //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C1", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + + I2cSerialBus ( + 0x27, //SlaveAddress: bus address + ControllerInitiated, //SlaveMode: Default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + AddressingMode7Bit, //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C1", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + }) + + Return (SBFI) + } + } // Device (TPFU) + + //------------------------ + // ELAN Touch Panel + //------------------------ + Device (TPL1) + { + Name (_HID, "ELAN1001") + Name (_CID, "PNP0C50") + Name (_UID, One) + + Name (_S0W, 4) // required to put the device to D3 Cold during S0 idle + + Method(_DSM, 0x4, NotSerialized) + { + // DSM UUID for HIDI2C. Do Not change. + If(LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) + { + // Function 0 : Query Function + If(LEqual(Arg2, Zero)) + { + // Revision 1 + If(LEqual(Arg1, One)) + { + Return(Buffer(One) { 0x03 }) + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + // Function 1 : HID Function + If(LEqual(Arg2, One)) + { + // HID Descriptor Address (IHV Specific) + Return(0x0001) + } + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + + Method (_STA, 0, NotSerialized) + { + If(LEqual(And(SDS1,0x0002), 0x0002)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + + Method (_CRS, 0, NotSerialized) + { + Name (SBFI, ResourceTemplate () + { + I2cSerialBus ( + 0x10, //SlaveAddress: bus address + ControllerInitiated, //SlaveMode: Default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + AddressingMode7Bit, //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C1", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + + Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , ,) {34} //Interrupt from touch screen routed to GPIO50-->PIRQS + }) + + Return (SBFI) + } + } // Device (TPL1) + + + //------------------------------ + // NTRIG Digitizer Touch Panel + //------------------------------ + Device (TPL2) + { + Name (_ADR, One) + Name (_HID, "NTRG0001") + Name (_CID, "PNP0C50") + Name (_UID, One) + + Name (_S0W, 4) // required to put the device to D3 Cold during S0 idle + + Method(_DSM, 0x4, NotSerialized) + { + // DSM UUID for HIDI2C. Do Not change. + If(LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) + { + // Function 0 : Query Function + If(LEqual(Arg2, Zero)) + { + // Revision 1 + If(LEqual(Arg1, One)) + { + Return(Buffer(One) { 0x03 }) + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + // Function 1 : HID Function + If(LEqual(Arg2, One)) + { + // HID Descriptor Address (IHV Specific) + Return(0x0001) + } + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + + Method (_STA, 0, NotSerialized) + { + If(LEqual(And(SDS1,0x0020), 0x0020)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + + Method (_CRS, 0, NotSerialized) + { + Name (SBFI, ResourceTemplate () + { + I2cSerialBus ( + 0x07, //SlaveAddress: bus address + ControllerInitiated, //SlaveMode: Default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + AddressingMode7Bit, //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C1", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + + Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , ,) {34} //Interrupt from touch screen routed to GPIO50-->PIRQS + }) + + Return (SBFI) + + } + } // Device (TPL2) + + //------------------------ + // EETI Touch Panel + //------------------------ + Device (TPL3) + { + Name (_ADR, One) + Name (_HID, "EETI7900") + Name (_CID, "PNP0C50") + Name (_UID, One) + + Name (_S0W, 4) // required to put the device to D3 Cold during S0 idle + + Method(_DSM, 0x4, NotSerialized) + { + // DSM UUID for HIDI2C. Do Not change. + If(LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) + { + // Function 0 : Query Function + If(LEqual(Arg2, Zero)) + { + // Revision 1 + If(LEqual(Arg1, One)) + { + Return(Buffer(One) { 0x03 }) + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + // Function 1 : HID Function + If(LEqual(Arg2, One)) + { + // HID Descriptor Address (IHV Specific) + Return(0x000F) + } + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + + Method (_STA, 0, NotSerialized) + { + If(LEqual(And(SDS1,0x0040), 0x0040)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + + Method (_CRS, 0, NotSerialized) + { + Name (SBFI, ResourceTemplate () + { + I2cSerialBus ( + 0x2A, //SlaveAddress: bus address + ControllerInitiated, //SlaveMode: Default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + AddressingMode7Bit, //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C1", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + + Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , ,) {34} //Interrupt from touch screen routed to GPIO50-->PIRQS + }) + + + Return (SBFI) + + } + } // Device (TPL3) + + + //------------------------ + // ELAN Touch Pad + //------------------------ + Device (TPD0) + { + Name (_ADR, One) + Name (_HID, "ELAN1000") + Name (_CID, "PNP0C50") + Name (_UID, One) + + Name (_S0W, 4) // required to put the device to D3 Cold during S0 idle + + Method(_DSM, 0x4, NotSerialized) + { + // DSM UUID for HIDI2C. Do Not change. + If(LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) + { + // Function 0 : Query Function + If(LEqual(Arg2, Zero)) + { + // Revision 1 + If(LEqual(Arg1, One)) + { + Return(Buffer(One) { 0x03 }) + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + // Function 1 : HID Function + If(LEqual(Arg2, One)) + { + // HID Descriptor Address (IHV Specific) + Return(0x0001) + } + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + + Method (_STA, 0, NotSerialized) + { + If(LEqual(And(SDS1,0x0004), 0x0004)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + + Method (_CRS, 0, Serialized) + { + Name (SBFI, ResourceTemplate () + { + I2cSerialBus ( + 0x15, //SlaveAddress: bus address + ControllerInitiated, //SlaveMode: Default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + AddressingMode7Bit, //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C1", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + + Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , ,INT0) {39} //Interrupt from Touchpad routed to GPIO55 - IOxAPIC PIRQX + }) + + If(LEqual(GR13, 1)) { + CreateByteField (SBFI, INT0._INT, VAL3) // Extended Interrupt Descriptor + Store(27, VAL3) + } + + Return (SBFI) + + + } + } // Device (TPD0) + + //------------------------ + // Synaptics touchpad + //------------------------ + Device (TPD1) + { + Name (_ADR, One) + Name (_HID, "MSFT0001") + Name (_CID, "PNP0C50") + Name (_UID, One) + + Name (_S0W, 4) // required to put the device to D3 Cold during S0 idle + + Method(_DSM, 0x4, NotSerialized) + { + // DSM UUID for HIDI2C. Do Not change. + If(LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) + { + // Function 0 : Query Function + If(LEqual(Arg2, Zero)) + { + // Revision 1 + If(LEqual(Arg1, One)) + { + Return(Buffer(One) { 0x03 }) + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + // Function 1 : HID Function + If(LEqual(Arg2, One)) + { + // HID Descriptor Address (IHV Specific) + Return(0x0020) + } + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + + Method (_STA, 0, NotSerialized) + { + If(LEqual(And(SDS1,0x0008), 0x0008)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + + Method (_CRS, 0, Serialized) + { + Name (SBFI, ResourceTemplate () + { + I2cSerialBus ( + 0x20, //SlaveAddress: bus address + ControllerInitiated, //SlaveMode: Default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + AddressingMode7Bit, //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C1", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + + Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , ,INT0) {39} //Interrupt from Touchpad routed to GPIO55 - IOxAPIC PIRQX + }) + + If(LEqual(GR13, 1)) { + CreateByteField (SBFI, INT0._INT, VAL3) // Extended Interrupt Descriptor + Store(27, VAL3) + } + + Return (SBFI) + } + } // Device (TPD1) + + //------------------------ + // Alps touchpad + //------------------------ + Device (TPD2) + { + Name (_ADR, One) + Name (_HID, "ALP0001") + Name (_CID, "PNP0C50") + Name (_UID, One) + + Name (_S0W, 4) // required to put the device to D3 Cold during S0 idle + + Method(_DSM, 0x4, NotSerialized) + { + // DSM UUID for HIDI2C. Do Not change. + If(LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) + { + // Function 0 : Query Function + If(LEqual(Arg2, Zero)) + { + // Revision 1 + If(LEqual(Arg1, One)) + { + Return(Buffer(One) { 0x03 }) + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + // Function 1 : HID Function + If(LEqual(Arg2, One)) + { + // HID Descriptor Address (IHV Specific) + Return(0x0001) + } + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + + Method (_STA, 0, NotSerialized) + { + If(LEqual(And(SDS1,0x0080), 0x0080)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + + Method (_CRS, 0, Serialized) + { + Name (SBFI, ResourceTemplate () + { + I2cSerialBus ( + 0x2A, //SlaveAddress: bus address + ControllerInitiated, //SlaveMode: Default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + AddressingMode7Bit, //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C1", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + + Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , ,INT0) {39} //Interrupt from Touchpad routed to GPIO55 - IOxAPIC PIRQX + }) + + If(LEqual(GR13, 1)) { + CreateByteField (SBFI, INT0._INT, VAL3) // Extended Interrupt Descriptor + Store(27, VAL3) + } + + Return (SBFI) + } + } // Device (TPD2) + + //------------------------ + // Cypress touchpad + //------------------------ + Device (TPD3) + { + Name (_ADR, One) + Name (_HID, "CYP0001") + Name (_CID, "PNP0C50") + Name (_UID, One) + + Name (_S0W, 4) // required to put the device to D3 Cold during S0 idle + + Method(_DSM, 0x4, NotSerialized) + { + // DSM UUID for HIDI2C. Do Not change. + If(LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) + { + // Function 0 : Query Function + If(LEqual(Arg2, Zero)) + { + // Revision 1 + If(LEqual(Arg1, One)) + { + Return(Buffer(One) { 0x03 }) + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + // Function 1 : HID Function + If(LEqual(Arg2, One)) + { + // HID Descriptor Address (IHV Specific) + Return(0x0001) + } + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + + Method (_STA, 0, NotSerialized) + { + If(LEqual(And(SDS1,0x0100), 0x0100)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + + Method (_CRS, 0, Serialized) + { + Name (SBFI, ResourceTemplate () + { + I2cSerialBus ( + 0x24, //SlaveAddress: bus address + ControllerInitiated, //SlaveMode: Default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + AddressingMode7Bit, //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C1", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + + Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , ,INT0) {39} //Interrupt from Touchpad routed to GPIO55 - IOxAPIC PIRQX + }) + + If(LEqual(GR13, 1)) { + CreateByteField (SBFI, INT0._INT, VAL3) // Extended Interrupt Descriptor + Store(27, VAL3) + } + + Return (SBFI) + } + } // Device (TPD3) + + //------------------------ + // ELAN Precision Touch Pad + //------------------------ + Device (TPD7) + { + Name (_ADR, One) + Name (_HID, "ELAN1010") + Name (_CID, "PNP0C50") + Name (_UID, One) + + Name (_S0W, 3) // PTP will be in D3hot during CS, and wake capable + + Method (_S3W, 0) { + If(LEqual(S0ID, 0)) { + Return (3) + } Else { + Return (0) + } + } + + Method(_DSM, 0x4, NotSerialized) + { + // DSM UUID for HIDI2C. Do Not change. + If(LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) + { + // Function 0 : Query Function + If(LEqual(Arg2, Zero)) + { + // Revision 1 + If(LEqual(Arg1, One)) + { + Return(Buffer(One) { 0x03 }) + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + // Function 1 : HID Function + If(LEqual(Arg2, One)) + { + // HID Descriptor Address (IHV Specific) + Return(0x0001) + } + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + + // Get the right SDS value + Method (_STA, 0, NotSerialized) + { + If(LEqual(And(SDS1,0x0800), 0x0800)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + + Method (_CRS, 0, Serialized) + { + Name (SBFI, ResourceTemplate () + { + I2cSerialBus ( + 0x15, //SlaveAddress: bus address + ControllerInitiated, //SlaveMode: Default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + AddressingMode7Bit, //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C1", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + + Interrupt(ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, , ,INT0) {39} //Interrupt from Touchpad routed to GPIO55 - IOxAPIC PIRQX + }) + + If(LEqual(GR13, 1)) { + CreateByteField (SBFI, INT0._INT, VAL3) // Extended Interrupt Descriptor + Store(27, VAL3) + + If(LEqual(S0ID, 0)) { + CreateByteField (SBFI, INT0._SHR, VAL4) // Change to exclusive + And(VAL4, 0xE7, VAL4) //Exclusive + } + } + + Return (SBFI) + + + } + + Method (_PRW, 0) { + If(LAnd(LEqual(S0ID, 0),LEqual(GR13, 1))) { + Return(Package(){0x0D, 3}) // can wakeup from S4 state + } + Return(Package(){Zero, Zero}) + } + + Method(_PS0,0,Serialized) + { + ADBG("TPD7 Ctrlr D0") + If(LAnd(LEqual(S0ID, 0),LEqual(GR13, 1))) { + \_SB.WTIN(13, 0) // Set GPI_INV to normal + Store(1, \GO13) // Set GPI_OWN to GPIO + } + + If(CondRefOf(\_SB.PCI0.I2C1.TPD7.PS0X)) + { + \_SB.PCI0.I2C1.TPD7.PS0X() + } + } + + Method(_PS3,0,Serialized) + { + ADBG("TPD7 Ctrlr D3") + If(LAnd(LEqual(S0ID, 0),LEqual(GR13, 1))) { + \_SB.WTIN(13, 1) // Set GPI_INV to Inverted + Store(0, \GO13) // Set GPI_OWN to ACPI + } + } + } // Device (TPD7) + + //------------------------ + // Synaptics Precision touchpad + //------------------------ + Device (TPD8) + { + Name (_ADR, One) + Name (_HID, "SYNA2393") + Name (_CID, "PNP0C50") + Name (_UID, One) + + Name (_S0W, 3) // PTP will be in D3hot during CS, and wake capable + + Method (_S3W, 0) { + If(LEqual(S0ID, 0)) { + Return (3) + } Else { + Return (0) + } + } + + Method(_DSM, 0x4, NotSerialized) + { + // DSM UUID for HIDI2C. Do Not change. + If(LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE"))) + { + // Function 0 : Query Function + If(LEqual(Arg2, Zero)) + { + // Revision 1 + If(LEqual(Arg1, One)) + { + Return(Buffer(One) { 0x03 }) + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + // Function 1 : HID Function + If(LEqual(Arg2, One)) + { + // HID Descriptor Address (IHV Specific) + Return(0x0020) + } + } + Else + { + Return(Buffer(One) { 0x00 }) + } + } + + // Get the right SDS value + Method (_STA, 0, NotSerialized) + { + If(LEqual(And(SDS1,0x1000), 0x1000)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + + Method (_CRS, 0, Serialized) + { + Name (SBFI, ResourceTemplate () + { + I2cSerialBus ( + 0x20, //SlaveAddress: bus address + ControllerInitiated, //SlaveMode: Default to ControllerInitiated + 400000, //ConnectionSpeed: in Hz + AddressingMode7Bit, //Addressing Mode: default to 7 bit + "\\_SB.PCI0.I2C1", //ResourceSource: I2C bus controller name + , //ResourceSourceIndex: defaults to 0 + , //ResourceUsage: Defaults to ResourceConsumer + , //Descriptor Name: creates name for offset of resource descriptor + ) //VendorData + + Interrupt(ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, , ,INT0) {39} //Interrupt from Touchpad routed to GPIO55 - IOxAPIC PIRQX + }) + + If(LEqual(GR13, 1)) { + CreateByteField (SBFI, INT0._INT, VAL3) // Extended Interrupt Descriptor + Store(27, VAL3) //PIRQ + + If(LEqual(S0ID, 0)) { + CreateByteField (SBFI, INT0._SHR, VAL4) // Change to exclusive + And(VAL4, 0xE7, VAL4) //Exclusive + } + } + + Return (SBFI) + } + + Method (_PRW, 0) { + If(LAnd(LEqual(S0ID, 0),LEqual(GR13, 1))) { + Return(Package(){0x0D,3}) // can wakeup from S4 state + } + Return(Package(){Zero, Zero}) + } + + Method(_PS0,0,Serialized) + { + ADBG("TPD8 Ctrlr D0") + If(LAnd(LEqual(S0ID, 0),LEqual(GR13, 1))) { + \_SB.WTIN(13, 0) // Set GPI_INV to normal + Store(1, \GO13) // Set GPI_OWN to GPIO + } + + If(CondRefOf(\_SB.PCI0.I2C1.TPD8.PS0X)) + { + \_SB.PCI0.I2C1.TPD8.PS0X() + } + } + + Method(_PS3,0,Serialized) + { + ADBG("TPD8 Ctrlr D3") + If(LAnd(LEqual(S0ID, 0),LEqual(GR13, 1))) { + \_SB.WTIN(13, 1) // Set GPI_INV to Inverted + Store(0, \GO13) // Set GPI_OWN to ACPI + } + } + } // Device (TPD8) + } // Device (I2C1) + + //---------------------------- + // Serial IO SPI0 Controller + //---------------------------- +Scope(\_SB.PCI0.SPI0) +{ + + +} // end Scope(\_SB.PCI0.SPI0) + + //---------------------------- + // Serial IO SPI1 Controller + //---------------------------- +Scope(\_SB.PCI0.SPI1) +{ + +} // end Scope(\_SB.PCI0.SPI1) + + //----------------------------- + // Serial IO UART0 Controller + //----------------------------- +Scope(\_SB.PCI0.UA00) +{ + + // + // Bluetooth controller using serial interface + // + Device(BTH0) + { + Name(_HID, "INT33E0") + + Method(_CRS, 0x0, NotSerialized) + { + Name(UBUF, ResourceTemplate () + { + UARTSerialBus( + 115200, //InitialBaudRate: in bits per second + DataBitsEight, //BitsPerByte: default to DataBitsEight (optional) + StopBitsOne, //StopBits: defaults to StopBitsOne (optional) + 0xc0, //LinesInUse: 8 1-bit flags to declare line enabled + , //IsBigEndian: default to LittleEndian (optional) + ParityTypeNone, //Parity: defaults to ParityTypeNone (optional) + FlowControlHardware, //FlowControl: defaults to FlowControlNone (optional) + 32, //ReceiveBufferSize + 32, //TransmitBufferSize + "\\_SB.PCI0.UA00", //ResourceSource: UART bus controller name + , //ResourceSourceIndex: defaults to 0 (optional) + , //ResourceUsage: defaults to ResourceConsumer (optional) + , //DescriptorName: creates name for offset of resource descriptor + ) //VendorData + }) + + Return (UBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + If(LEqual(And(SDS4,0x01), 0x01)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + } // Device BTH0 + + } // end Scope(\_SB.PCI0.UART0) + + //----------------------------- + // Serial IO UART1 Controller + //----------------------------- +Scope(\_SB.PCI0.UA01) + { + + // + // Bluetooth controller using serial interface + // + Device(BTH1) + { + Name(_HID, "INT33E0") + + Method(_CRS, 0x0, NotSerialized) + { + Name(UBUF, ResourceTemplate () + { + UARTSerialBus( + 115200, //InitialBaudRate: in bits per second + DataBitsEight, //BitsPerByte: default to DataBitsEight (optional) + StopBitsOne, //StopBits: defaults to StopBitsOne (optional) + 0xc0, //LinesInUse: 8 1-bit flags to declare line enabled + , //IsBigEndian: default to LittleEndian (optional) + ParityTypeNone, //Parity: defaults to ParityTypeNone (optional) + FlowControlHardware, //FlowControl: defaults to FlowControlNone (optional) + 32, //ReceiveBufferSize + 32, //TransmitBufferSize + "\\_SB.PCI0.UA01", //ResourceSource: UART bus controller name + , //ResourceSourceIndex: defaults to 0 (optional) + , //ResourceUsage: defaults to ResourceConsumer (optional) + , //DescriptorName: creates name for offset of resource descriptor + ) //VendorData + Interrupt(ResourceConsumer, Level, ActiveLow, SharedAndWake, , , ) {25} // GPIO9 - PIRQ J(APIC pin 25) for BT Wake + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.PCI0.GPI0", ) {87} // for RF Kill + }) + + Return (UBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + If(LEqual(And(SDS5,0x01), 0x01)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + } // Device BTH1 + + // + // BroadCom Bluetooth controller using serial interface + // + Device(BTH2) + { + Method(_HID, 0, NotSerialized) { + if (LEqual(BCV4, 0)) { + Return("BCM2E20") + } else { + Return("BCM2E40") + } + } + + Method(_CRS, 0x0, NotSerialized) + { + Name(UBUF, ResourceTemplate () + { + UARTSerialBus( + 115200, //InitialBaudRate: in bits per second + , //BitsPerByte: default to DataBitsEight (optional) + , //StopBits: defaults to StopBitsOne (optional) + 0xc0, //LinesInUse: 8 1-bit flags to declare line enabled + , //IsBigEndian: default to LittleEndian (optional) + , //Parity: defaults to ParityTypeNone (optional) + FlowControlHardware, //FlowControl: defaults to FlowControlNone (optional) + 32, //ReceiveBufferSize + 32, //TransmitBufferSize + "\\_SB.PCI0.UA01", //ResourceSource: UART bus controller name + , //ResourceSourceIndex: defaults to 0 (optional) + , //ResourceUsage: defaults to ResourceConsumer (optional) + , //DescriptorName: creates name for offset of resource descriptor + ) //VendorData + Interrupt(ResourceConsumer, Edge, ActiveLow, Exclusive, , , ) {25} // GPIO9 - PIRQ J(APIC pin 25) for BT Wake + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.PCI0.GPI0", ) {57} // for BT_DEV_WAKE + GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.PCI0.GPI0", ) {87} // for RF Kill + }) + Return (UBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + If(LEqual(And(SDS5,0x02), 0x02)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + Name (_S0W, 2) // required to put the device to D2 during S0 idle + } // Device BTH2 + + + } // end Scope(\_SB.PCI0.UART1) + + //-------------------------------- + // Serial IO SDIO Host Controller + //-------------------------------- +Scope(\_SB.PCI0.SDHC) +{ + + Device (WI01) + { + Name (_ADR, 1) + Name (_DDN, "SDIO Wifi device Function 1" ) + + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } + + Method (_RMV, 0, NotSerialized) + { + Return (0x0) + } + + Name (_S4W, 2) // required per guidance from MS (SDIO Wifi device power states doc) + Name (_S0W, 2) // required to put the Wifi device to D2 during S0 idle + // D0 Method for WiFi + Method(_PS0,0,Serialized) + { + ADBG("WiFi1 Enter D0") + If(CondRefOf(\_SB.PCI0.SDHC.WI01.PS0X)) + { + \_SB.PCI0.SDHC.WI01.PS0X() + } + } + // D2 Method for WiFi + Method(_PS2,0,Serialized) + { + ADBG("WiFi1 Enter D2") + } + // D3 Method for WiFi + Method(_PS3,0,Serialized) + { + ADBG("WiFi1 Enter D3") + If(CondRefOf(\_SB.PCI0.SDHC.WI01.PS3X)) + { + \_SB.PCI0.SDHC.WI01.PS3X() + } + } + //Method(_DSW, 3){ + //ADBG("Wifi1 _DSW") + //} + // + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x0000000, BARC) // SW LTR Registers + Interrupt(ResourceConsumer, Level, ActiveLow, SharedAndWake, , , ) {38} + }) + + Method (_CRS, 0, NotSerialized) + { + CreateDWordField(^^RBUF, ^^BARA._BAS, AVAL) + if(LNotEqual(AVAL, 0)) { + CreateDWordField(^RBUF, ^BARC._LEN, WLN0) + Store(0xC, WLN0) + CreateDWordField(^RBUF, ^BARC._BAS, WVAL) + Add(AVAL, 0x1008, WVAL) + } + Return (RBUF) + } + } +} // end Scope(\_SB.PCI0.SDHC) + diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/BiosWriteProtect/Smm/PchBiosWriteProtect.c b/ReferenceCode/Chipset/LynxPoint/SampleCode/BiosWriteProtect/Smm/PchBiosWriteProtect.c new file mode 100644 index 0000000..020f152 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/BiosWriteProtect/Smm/PchBiosWriteProtect.c @@ -0,0 +1,188 @@ +/** @file + PCH BIOS Write Protect Driver. + +@copyright + Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#include "PchBiosWriteProtect.h" + +/// +/// Global variables +/// +EFI_SMM_ICHN_DISPATCH_PROTOCOL *mIchnDispatch; +EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL *mPchIoTrap; +UINTN mPciD31F0RegBase; + +/** + This hardware SMI handler will be run every time the BIOS Write Enable bit is set. + + @param[in] DispatchHandle Not used + @param[in] DispatchContext Not used + + @retval None +**/ +VOID +EFIAPI +PchBiosWpCallback ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_ICHN_DISPATCH_CONTEXT *DispatchContext + ) +{ + /// + /// Disable BIOSWE bit to protect BIOS + /// + MmioAnd8 ((UINTN) (mPciD31F0RegBase + R_PCH_LPC_BIOS_CNTL), (UINT8) ~B_PCH_LPC_BIOS_CNTL_BIOSWE); +} + +/** + Register an IchnBiosWp callback function to handle TCO BIOSWR SMI + SMM_BWP and BLE bits will be set here + + @param[in] DispatchHandle Not used + @param[in] CallbackContext Information about the IO trap that occurred + + @retval None +**/ +VOID +EFIAPI +PchBiosLockIoTrapCallback ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_IO_TRAP_DISPATCH_CALLBACK_CONTEXT *CallbackContext + ) +{ + EFI_STATUS Status; + EFI_SMM_ICHN_DISPATCH_CONTEXT IchnContext; + EFI_HANDLE IchnHandle; + + /// + /// Do not run the callback function if it is not Write cycle trapped or the wrtie data + /// is not PCH_BWP_SIGNATURE, + /// + if ((CallbackContext->Type != WriteTrap) || (CallbackContext->WriteData != PCH_BWP_SIGNATURE)) { + return; + } + + if (mIchnDispatch == NULL) { + return; + } + + IchnHandle = NULL; + + /// + /// Set SMM_BWP bit before registering IchnBiosWp + /// + MmioOr8 ((UINTN) (mPciD31F0RegBase + R_PCH_LPC_BIOS_CNTL), (UINT8) B_PCH_LPC_BIOS_CNTL_SMM_BWP); + + /// + /// Register an IchnBiosWp callback function to handle TCO BIOSWR SMI + /// + IchnContext.Type = IchnBiosWp; + Status = mIchnDispatch->Register ( + mIchnDispatch, + PchBiosWpCallback, + &IchnContext, + &IchnHandle + ); + ASSERT_EFI_ERROR (Status); +} + +/** + Entry point for Pch Bios Write Protect driver. + + @param[in] ImageHandle Image handle of this driver. + @param[in] SystemTable Global system service table. + + @retval EFI_SUCCESS Initialization complete. +**/ +EFI_STATUS +EFIAPI +InstallPchBiosWriteProtect ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + DXE_PCH_PLATFORM_POLICY_PROTOCOL *PchPlatformPolicy; + EFI_HANDLE PchIoTrapHandle; + EFI_SMM_IO_TRAP_DISPATCH_REGISTER_CONTEXT PchIoTrapContext; + + /// + /// Locate PCH Platform Policy protocol + /// + Status = gBS->LocateProtocol (&gDxePchPlatformPolicyProtocolGuid, NULL, (VOID **) &PchPlatformPolicy); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR | EFI_D_INFO, "Failed to locate PCH Policy protocol.\n")); + return Status; + } + + if ((PchPlatformPolicy->LockDownConfig->BiosLock == PCH_DEVICE_ENABLE)) { + mPciD31F0RegBase = MmPciAddress ( + 0, + 0, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ); + + /// + /// Get the ICHn protocol + /// + mIchnDispatch = NULL; + Status = gBS->LocateProtocol (&gEfiSmmIchnDispatchProtocolGuid, NULL, (VOID **) &mIchnDispatch); + ASSERT_EFI_ERROR (Status); + + /// + /// Locate the PCH IO TRAP Dispatch protocol + /// + PchIoTrapHandle = NULL; + Status = gBS->LocateProtocol (&gEfiSmmIoTrapDispatchProtocolGuid, NULL, (VOID **) &mPchIoTrap); + ASSERT_EFI_ERROR (Status); + + /// + /// Register BIOS Lock IO Trap SMI handler + /// + PchIoTrapContext.Type = WriteTrap; + PchIoTrapContext.Length = 4; + PchIoTrapContext.Address = PchPlatformPolicy->LockDownConfig->PchBiosLockIoTrapAddress; + PchIoTrapContext.Context = NULL; + PchIoTrapContext.MergeDisable = FALSE; + Status = mPchIoTrap->Register ( + mPchIoTrap, + PchBiosLockIoTrapCallback, + &PchIoTrapContext, + &PchIoTrapHandle + ); + ASSERT_EFI_ERROR (Status); + + DEBUG ((EFI_D_ERROR, "PchBiosLockIoTrapAddress = 0x%x\n", PchIoTrapContext.Address)); + + if ((PchPlatformPolicy->LockDownConfig->PchBiosLockIoTrapAddress == 0) && + (PchIoTrapContext.Address == 0)) { + DEBUG ((EFI_D_ERROR | EFI_D_INFO, "Invalid PchIoTrapContext.Address!!!\n")); + ASSERT (FALSE); + } else { + if ((PchPlatformPolicy->LockDownConfig->PchBiosLockIoTrapAddress != 0) && + (PchPlatformPolicy->LockDownConfig->PchBiosLockIoTrapAddress != PchIoTrapContext.Address)) { + DEBUG ((EFI_D_ERROR | EFI_D_INFO, "Invalid PchIoTrapContext.Address!!!\n")); + ASSERT (FALSE); + } else { + PchPlatformPolicy->LockDownConfig->PchBiosLockIoTrapAddress = PchIoTrapContext.Address; + } + } + } + + return EFI_SUCCESS; +} diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/BiosWriteProtect/Smm/PchBiosWriteProtect.dxs b/ReferenceCode/Chipset/LynxPoint/SampleCode/BiosWriteProtect/Smm/PchBiosWriteProtect.dxs new file mode 100644 index 0000000..47c8ea9 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/BiosWriteProtect/Smm/PchBiosWriteProtect.dxs @@ -0,0 +1,48 @@ +/** @file + Dependency expression source file. + +@copyright + Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ + + +// +// Common for R8 and R9 codebase +// +#include "AutoGen.h" +#include "DxeDepex.h" + +// +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase; +// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase. +// +#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB) +#include "EfiDepex.h" + +#include EFI_PROTOCOL_DEFINITION (PchPlatformPolicy) +#include EFI_PROTOCOL_DEFINITION (SmmBase) +#include EFI_PROTOCOL_DEPENDENCY (SmmIchnDispatch) +#include EFI_PROTOCOL_DEPENDENCY (SmmIoTrapDispatch) + +#endif + +DEPENDENCY_START + DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID AND + EFI_SMM_BASE_PROTOCOL_GUID AND + EFI_SMM_ICHN_DISPATCH_PROTOCOL_GUID AND + EFI_SMM_IO_TRAP_DISPATCH_PROTOCOL_GUID +DEPENDENCY_END diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/BiosWriteProtect/Smm/PchBiosWriteProtect.h b/ReferenceCode/Chipset/LynxPoint/SampleCode/BiosWriteProtect/Smm/PchBiosWriteProtect.h new file mode 100644 index 0000000..fedc210 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/BiosWriteProtect/Smm/PchBiosWriteProtect.h @@ -0,0 +1,36 @@ +/** @file + Header file for the Pch Bios Write Protect Driver. + +@copyright + Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _PCH_BIOS_WRITE_PROTECT_H_ +#define _PCH_BIOS_WRITE_PROTECT_H_ + +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGlueDxe.h" +#include "PchAccess.h" +#include "PchPlatformLib.h" + +// +// Driver Dependency Protocols +// +#include EFI_PROTOCOL_CONSUMER (PchPlatformPolicy) +#include EFI_PROTOCOL_CONSUMER (SmmBase) +#include EFI_PROTOCOL_CONSUMER (SmmIchnDispatch) +#include EFI_PROTOCOL_CONSUMER (SmmIoTrapDispatch) +#endif + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/BiosWriteProtect/Smm/PchBiosWriteProtect.inf b/ReferenceCode/Chipset/LynxPoint/SampleCode/BiosWriteProtect/Smm/PchBiosWriteProtect.inf new file mode 100644 index 0000000..552d188 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/BiosWriteProtect/Smm/PchBiosWriteProtect.inf @@ -0,0 +1,94 @@ +## @file +# Component description file for the PchBiosWriteProtect driver. +# +#@copyright +# Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +[defines] +BASE_NAME = PchBiosWriteProtect +FILE_GUID = 2EE81ACB-64B2-41ae-8635-7030D16C4AA8 +COMPONENT_TYPE = BS_DRIVER + +[sources.common] + PchBiosWriteProtect.h + PchBiosWriteProtect.c + +# +# Edk II Glue Driver Entry Point +# + EdkIIGlueSmmDriverEntryPoint.c + + +[includes.common] + . + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT) + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include/Library +# +# EDK II Glue Library utilizes some standard headers from EDK +# + $(EFI_SOURCE) + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include +# +# Typically the sample code referenced will be available in the code base already +# So keep this include at the end to defer to the source base definition +# and only use the sample code definition if source base does not include these files. +# + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/SampleCode + +[libraries.common] + EdkIIGlueBaseLib + EdkIIGlueBaseIoLibIntrinsic + EdkIIGlueBaseMemoryLib + EdkIIGlueDxeDebugLibReportStatusCode + EdkIIGlueSmmRuntimeDxeReportStatusCodeLib + EdkIIGlueDxeMemoryAllocationLib + EdkIIGlueUefiBootServicesTableLib + EdkIIGlueUefiRuntimeServicesTableLib + EdkIIGlueUefiDevicePathLib + EdkIIGlueBasePciLibPciExpress + EdkFrameworkProtocolLib + EdkProtocolLib + $(PROJECT_PCH_FAMILY)ProtocolLib + PchPlatformLib + +[nmake.common] + IMAGE_ENTRY_POINT = _ModuleEntryPoint + DPX_SOURCE = PchBiosWriteProtect.dxs +# +# Module Entry Point +# + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=InstallPchBiosWriteProtect + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \ + -D __EDKII_GLUE_BASE_MEMORY_LIB__ \ + -D __EDKII_GLUE_DXE_MEMORY_ALLOCATION_LIB__ \ + -D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \ + -D __EDKII_GLUE_SMM_RUNTIME_DXE_REPORT_STATUS_CODE_LIB__ \ + -D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \ + -D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \ + -D __EDKII_GLUE_UEFI_DEVICE_PATH_LIB__ \ + -D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/Guid/SmbusArpMap/SmbusArpMap.h b/ReferenceCode/Chipset/LynxPoint/SampleCode/Guid/SmbusArpMap/SmbusArpMap.h new file mode 100644 index 0000000..32f4ee0 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/Guid/SmbusArpMap/SmbusArpMap.h @@ -0,0 +1,29 @@ +/** @file + GUID for use in describing SMBus devices that were ARPed during PEI. + +@copyright + Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains 'Framework Code' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may not be modified, except as allowed by + additional terms of your license agreement. +**/ +#ifndef _EFI_SMBUS_ARP_MAP_GUID_H_ +#define _EFI_SMBUS_ARP_MAP_GUID_H_ + +#define EFI_SMBUS_ARP_MAP_GUID \ + { \ + 0x707be83e, 0x0bf6, 0x40a5, 0xbe, 0x64, 0x34, 0xc0, 0x3a, 0xa0, 0xb8, 0xe2 \ + } + +extern EFI_GUID gEfiSmbusArpMapGuid; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/Include/Acpi3_0.h b/ReferenceCode/Chipset/LynxPoint/SampleCode/Include/Acpi3_0.h new file mode 100644 index 0000000..cc5111b --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/Include/Acpi3_0.h @@ -0,0 +1,681 @@ +/** @file + ACPI 3.0 definitions from the ACPI Specification Revision 3.0 September 2, 2004 + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains 'Framework Code' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may not be modified, except as allowed by + additional terms of your license agreement. +**/ +#ifndef _ACPI_3_0_H_ +#define _ACPI_3_0_H_ + +// +// Statements that include other files +// +#include "Tiano.h" +#include "Acpi.h" + +// +// Ensure proper structure formats +// +#pragma pack(1) +// +// ACPI Specification Revision +// +#define EFI_ACPI_3_0_REVISION 0x03 // @bug: Not in spec yet. +// +// @bug: OEM values need to be moved somewhere else, probably read from data hub +// and produced by a platform specific driver. +// +// +// ACPI 3.0 Generic Address Space definition +// +typedef struct { + UINT8 AddressSpaceId; + UINT8 RegisterBitWidth; + UINT8 RegisterBitOffset; + UINT8 AccessSize; + UINT64 Address; +} EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE; + +// +// Generic Address Space Address IDs +// +#define EFI_ACPI_3_0_SYSTEM_MEMORY 0 +#define EFI_ACPI_3_0_SYSTEM_IO 1 +#define EFI_ACPI_3_0_PCI_CONFIGURATION_SPACE 2 +#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER 3 +#define EFI_ACPI_3_0_SMBUS 4 +#define EFI_ACPI_3_0_FUNCTIONAL_FIXED_HARDWARE 0x7F + +// +// Generic Address Space Access Sizes +// +#define EFI_ACPI_3_0_UNDEFINED 0 +#define EFI_ACPI_3_0_BYTE 1 +#define EFI_ACPI_3_0_WORD 2 +#define EFI_ACPI_3_0_DWORD 3 +#define EFI_ACPI_3_0_QWORD 4 + +// +// ACPI 3.0 table structures +// +// +// Root System Description Pointer Structure +// +typedef struct { + UINT64 Signature; + UINT8 Checksum; + UINT8 OemId[6]; + UINT8 Revision; + UINT32 RsdtAddress; + UINT32 Length; + UINT64 XsdtAddress; + UINT8 ExtendedChecksum; + UINT8 Reserved[3]; +} EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER; + +// +// RSD_PTR Revision (as defined in ACPI 3.0 spec.) +// +#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 // ACPISpec30 (Revision 3.0 September 2, 2004) says current value is 2 +// +// Common table header, this prefaces all ACPI tables, including FACS, but +// excluding the RSD PTR structure +// +typedef struct { + UINT32 Signature; + UINT32 Length; +} EFI_ACPI_3_0_COMMON_HEADER; + +// +// Root System Description Table +// No definition needed as it is a common description table header followed by a +// variable number of UINT32 table pointers. +// +// +// RSDT Revision (as defined in ACPI 3.0 spec.) +// +#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +// +// Extended System Description Table +// No definition needed as it is a common description table header followed by a +// variable number of UINT64 table pointers. +// +// +// XSDT Revision (as defined in ACPI 3.0 spec.) +// +#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01 + +// +// Fixed ACPI Description Table Structure (FADT) +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 FirmwareCtrl; + UINT32 Dsdt; + UINT8 Reserved0; + UINT8 PreferredPmProfile; + UINT16 SciInt; + UINT32 SmiCmd; + UINT8 AcpiEnable; + UINT8 AcpiDisable; + UINT8 S4BiosReq; + UINT8 PstateCnt; + UINT32 Pm1aEvtBlk; + UINT32 Pm1bEvtBlk; + UINT32 Pm1aCntBlk; + UINT32 Pm1bCntBlk; + UINT32 Pm2CntBlk; + UINT32 PmTmrBlk; + UINT32 Gpe0Blk; + UINT32 Gpe1Blk; + UINT8 Pm1EvtLen; + UINT8 Pm1CntLen; + UINT8 Pm2CntLen; + UINT8 PmTmrLen; + UINT8 Gpe0BlkLen; + UINT8 Gpe1BlkLen; + UINT8 Gpe1Base; + UINT8 CstCnt; + UINT16 PLvl2Lat; + UINT16 PLvl3Lat; + UINT16 FlushSize; + UINT16 FlushStride; + UINT8 DutyOffset; + UINT8 DutyWidth; + UINT8 DayAlrm; + UINT8 MonAlrm; + UINT8 Century; + UINT16 IaPcBootArch; + UINT8 Reserved1; + UINT32 Flags; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE ResetReg; + UINT8 ResetValue; + UINT8 Reserved2[3]; + UINT64 XFirmwareCtrl; + UINT64 XDsdt; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk; +} EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE; + +// +// FADT Version (as defined in ACPI 3.0 spec.) +// +#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x04 + +// +// Fixed ACPI Description Table Preferred Power Management Profile +// +#define EFI_ACPI_3_0_PM_PROFILE_UNSPECIFIED 0 +#define EFI_ACPI_3_0_PM_PROFILE_DESKTOP 1 +#define EFI_ACPI_3_0_PM_PROFILE_MOBILE 2 +#define EFI_ACPI_3_0_PM_PROFILE_WORKSTATION 3 +#define EFI_ACPI_3_0_PM_PROFILE_ENTERPRISE_SERVER 4 +#define EFI_ACPI_3_0_PM_PROFILE_SOHO_SERVER 5 +#define EFI_ACPI_3_0_PM_PROFILE_APPLIANCE_PC 6 +#define EFI_ACPI_3_0_PM_PROFILE_PERFORMANCE_SERVER 7 + +// +// Fixed ACPI Description Table Boot Architecture Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_3_0_LEGACY_DEVICES (1 << 0) +#define EFI_ACPI_3_0_8042 (1 << 1) +#define EFI_ACPI_3_0_VGA_NOT_PRESENT (1 << 2) + +// +// Fixed ACPI Description Table Fixed Feature Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_3_0_WBINVD (1 << 0) +#define EFI_ACPI_3_0_WBINVD_FLUSH (1 << 1) +#define EFI_ACPI_3_0_PROC_C1 (1 << 2) +#define EFI_ACPI_3_0_P_LVL2_UP (1 << 3) +#define EFI_ACPI_3_0_PWR_BUTTON (1 << 4) +#define EFI_ACPI_3_0_SLP_BUTTON (1 << 5) +#define EFI_ACPI_3_0_FIX_RTC (1 << 6) +#define EFI_ACPI_3_0_RTC_S4 (1 << 7) +#define EFI_ACPI_3_0_TMR_VAL_EXT (1 << 8) +#define EFI_ACPI_3_0_DCK_CAP (1 << 9) +#define EFI_ACPI_3_0_RESET_REG_SUP (1 << 10) +#define EFI_ACPI_3_0_SEALED_CASE (1 << 11) +#define EFI_ACPI_3_0_HEADLESS (1 << 12) +#define EFI_ACPI_3_0_CPU_SW_SLP (1 << 13) +#define EFI_ACPI_3_0_PCI_EXP_WAK (1 << 14) +#define EFI_ACPI_3_0_USE_PLATFORM_CLOCK (1 << 15) +#define EFI_ACPI_3_0_S4_RTC_STS_VALID (1 << 16) +#define EFI_ACPI_3_0_REMOTE_POWER_ON_CAPABLE (1 << 17) +#define EFI_ACPI_3_0_FORCE_APIC_CLUSTER_MODEL (1 << 18) +#define EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE (1 << 19) + +// +// Firmware ACPI Control Structure +// +typedef struct { + UINT32 Signature; + UINT32 Length; + UINT32 HardwareSignature; + UINT32 FirmwareWakingVector; + UINT32 GlobalLock; + UINT32 Flags; + UINT64 XFirmwareWakingVector; + UINT8 Version; + UINT8 Reserved[31]; +} EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE; + +// +// FACS Version (as defined in ACPI 3.0 spec.) +// +#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION 0x01 + +// +// Firmware Control Structure Feature Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_3_0_S4BIOS_F (1 << 0) + +// +// Differentiated System Description Table, +// Secondary System Description Table +// and Persistent System Description Table, +// no definition needed as they are common description table header followed by a +// definition block. +// +#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02 +#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02 + +// +// Multiple APIC Description Table header definition. The rest of the table +// must be defined in a platform specific manner. +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 LocalApicAddress; + UINT32 Flags; +} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER; + +// +// MADT Revision (as defined in ACPI 3.0 spec.) +// +#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x02 + +// +// Multiple APIC Flags +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_3_0_PCAT_COMPAT (1 << 0) + +// +// Multiple APIC Description Table APIC structure types +// All other values between 0x09 an 0xFF are reserved and +// will be ignored by OSPM. +// +#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC 0x00 +#define EFI_ACPI_3_0_IO_APIC 0x01 +#define EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE 0x02 +#define EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE 0x03 +#define EFI_ACPI_3_0_LOCAL_APIC_NMI 0x04 +#define EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE 0x05 +#define EFI_ACPI_3_0_IO_SAPIC 0x06 +#define EFI_ACPI_3_0_LOCAL_SAPIC 0x07 +#define EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES 0x08 + +// +// APIC Structure Definitions +// +// +// Processor Local APIC Structure Definition +// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT8 ApicId; + UINT32 Flags; +} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE; + +// +// Local APIC Flags. All other bits are reserved and must be 0. +// +#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED (1 << 0) + +// +// IO APIC Structure +// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 IoApicAddress; + UINT32 GlobalSystemInterruptBase; +} EFI_ACPI_3_0_IO_APIC_STRUCTURE; + +// +// Interrupt Source Override Structure +// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 Bus; + UINT8 Source; + UINT32 GlobalSystemInterrupt; + UINT16 Flags; +} EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE; + +// +// Platform Interrupt Sources Structure Definition +// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 PlatformInterruptSourceFlags; + UINT8 CpeiProcessorOverride; + UINT8 Reserved[31]; +} EFI_ACPI_3_0_PLATFORM_INTERRUPT_APIC_STRUCTURE; + +// +// MPS INTI flags. +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_3_0_POLARITY (3 << 0) +#define EFI_ACPI_3_0_TRIGGER_MODE (3 << 2) + +// +// Non-Maskable Interrupt Source Structure +// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT32 GlobalSystemInterrupt; +} EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE; + +// +// Local APIC NMI Structure +// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT16 Flags; + UINT8 LocalApicLint; +} EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE; + +// +// Local APIC Address Override Structure +// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Reserved; + UINT64 LocalApicAddress; +} EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE; + +// +// IO SAPIC Structure +// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 IoApicId; + UINT8 Reserved; + UINT32 GlobalSystemInterruptBase; + UINT64 IoSapicAddress; +} EFI_ACPI_3_0_IO_SAPIC_STRUCTURE; + +// +// Local SAPIC Structure +// This struct followed by a null-terminated ASCII string - ACPI Processor UID String +// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 AcpiProcessorId; + UINT8 LocalSapicId; + UINT8 LocalSapicEid; + UINT8 Reserved[3]; + UINT32 Flags; + UINT32 ACPIProcessorUIDValue; +} EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE; + +// +// Platform Interrupt Sources Structure +// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Flags; + UINT8 InterruptType; + UINT8 ProcessorId; + UINT8 ProcessorEid; + UINT8 IoSapicVector; + UINT32 GlobalSystemInterrupt; + UINT32 PlatformInterruptSourceFlags; +} EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE; + +// +// Platform Interrupt Source Flags. +// All other bits are reserved and must be set to 0. +// +#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE (1 << 0) + +// +// Smart Battery Description Table (SBST) +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 WarningEnergyLevel; + UINT32 LowEnergyLevel; + UINT32 CriticalEnergyLevel; +} EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE; + +// +// SBST Version (as defined in ACPI 3.0 spec.) +// +#define EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01 + +// +// Embedded Controller Boot Resources Table (ECDT) +// The table is followed by a null terminated ASCII string that contains +// a fully qualified reference to the name space object. +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcControl; + EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcData; + UINT32 Uid; + UINT8 GpeBit; +} EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE; + +// +// ECDT Version (as defined in ACPI 3.0 spec.) +// +#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION 0x01 + +// +// System Resource Affinity Table (SRAT. The rest of the table +// must be defined in a platform specific manner. +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Reserved1; // Must be set to 1 + UINT64 Reserved2; +} EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER; + +// +// SRAT Version (as defined in ACPI 3.0 spec.) +// +#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x02 + +// +// SRAT structure types. +// All other values between 0x02 an 0xFF are reserved and +// will be ignored by OSPM. +// +#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00 +#define EFI_ACPI_3_0_MEMORY_AFFINITY 0x01 + +// +// Processor Local APIC/SAPIC Affinity Structure Definition +// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT8 ProximityDomain7To0; + UINT8 ApicId; + UINT32 Flags; + UINT8 LocalSapicEid; + UINT8 ProximityDomain31To8[3]; + UINT8 Reserved[4]; +} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE; + +// +// Local APIC/SAPIC Flags. All other bits are reserved and must be 0. +// +#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0) + +// +// Memory Affinity Structure Definition +// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 ProximityDomain; + UINT16 Reserved1; + UINT32 AddressBaseLow; + UINT32 AddressBaseHigh; + UINT32 LengthLow; + UINT32 LengthHigh; + UINT32 Reserved2; + UINT32 Flags; + UINT64 Reserved3; +} EFI_ACPI_3_0_MEMORY_AFFINITY_STRUCTURE; + +// +// Memory Flags. All other bits are reserved and must be 0. +// +#define EFI_ACPI_3_0_MEMORY_ENABLED (1 << 0) +#define EFI_ACPI_3_0_MEMORY_HOT_PLUGGABLE (1 << 1) +#define EFI_ACPI_3_0_MEMORY_NONVOLATILE (1 << 2) + +// +// System Locality Distance Information Table (SLIT). +// The rest of the table is a matrix. +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 NumberOfSystemLocalities; +} EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER; + +// +// SLIT Version (as defined in ACPI 3.0 spec.) +// +#define EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION 0x01 + +// +// Known table signatures +// +// +// "RSD PTR " Root System Description Pointer +// +#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE 0x2052545020445352 + +// +// "APIC" Multiple APIC Description Table +// +#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE 0x43495041 + +// +// "DSDT" Differentiated System Description Table +// +#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445344 + +// +// "ECDT" Embedded Controller Boot Resources Table +// +#define EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE 0x54444345 + +// +// "FACP" Fixed ACPI Description Table +// +#define EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE 0x50434146 + +// +// "FACS" Firmware ACPI Control Structure +// +#define EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE 0x53434146 + +// +// "PSDT" Persistent System Description Table +// +#define EFI_ACPI_3_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445350 + +// +// "RSDT" Root System Description Table +// +#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445352 + +// +// "SBST" Smart Battery Specification Table +// +#define EFI_ACPI_3_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE 0x54534253 + +// +// "SLIT" System Locality Information Table +// +#define EFI_ACPI_3_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE 0x54494C53 + +// +// "SRAT" System Resource Affinity Table +// +#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE 0x54415253 + +// +// "SSDT" Secondary System Description Table +// +#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445353 + +// +// "XSDT" Extended System Description Table +// +#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE 0x54445358 + +// +// "BOOT" MS Simple Boot Spec +// +#define EFI_ACPI_3_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE 0x544F4F42 + +// +// "CPEP" Corrected Platform Error Polling Table +// See +// +#define EFI_ACPI_3_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE 0x50455043 + +// +// "DBGP" MS Debug Port Spec +// +#define EFI_ACPI_3_0_DEBUG_PORT_TABLE_SIGNATURE 0x50474244 + +// +// "ETDT" Event Timer Description Table +// +#define EFI_ACPI_3_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE 0x54445445 + +// +// "HPET" IA-PC High Precision Event Timer Table +// +#define EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE 0x54455048 + +// +// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table +// +#define EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE 0x4746434D + +// +// "SPCR" Serial Port Concole Redirection Table +// +#define EFI_ACPI_3_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE 0x52435053 + +// +// "SPMI" Server Platform Management Interface Table +// +#define EFI_ACPI_3_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE 0x494D5053 + +// +// "TCPA" Trusted Computing Platform Alliance Capabilities Table +// +#define EFI_ACPI_3_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE 0x41504354 + +// +// "WDRT" Watchdog Resource Table +// +#define EFI_ACPI_3_0_WATCHDOG_RESOURCE_TABLE_SIGNATURE 0x41504354 0x54524457 + +#pragma pack() + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/Include/PchAslUpdateLib.h b/ReferenceCode/Chipset/LynxPoint/SampleCode/Include/PchAslUpdateLib.h new file mode 100644 index 0000000..64bc613 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/Include/PchAslUpdateLib.h @@ -0,0 +1,166 @@ +/** @file + ASL dynamic update library definitions. + This library provides dymanic update to various ASL structures. + There may be different libraries for different environments (PEI, BS, RT, SMM). + Make sure you meet the requirements for the library (protocol dependencies, use + restrictions, etc). + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _ASL_UPDATE_LIB_H_ +#define _ASL_UPDATE_LIB_H_ + +// +// Include files +// +#include "Acpi3_0.h" + +#include EFI_PROTOCOL_DEPENDENCY (AcpiSupport) +#include EFI_PROTOCOL_DEPENDENCY (AcpiTable) + +// +// AML parsing definitions +// +#define AML_NAME_OP 0x08 +#define AML_BUFFER_OP 0x11 +#define AML_DMA_FIXED_DESC_OP 0x55 +#define AML_DEVICE_OP 0x825B +#define AML_MEMORY32_FIXED_OP 0x86 +#define AML_DWORD_OP 0x87 +#define AML_INTERRUPT_DESC_OP 0x89 +#define AML_RESRC_TEMP_END_TAG 0x0079 + +/** + Initialize the ASL update library state. + This must be called prior to invoking other library functions. + + @param[in] None + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +InitializePchAslUpdateLib ( + VOID + ); + +/** + This procedure will update immediate value assigned to a Name + + @param[in] AslSignature The signature of Operation Region that we want to update. + @param[in] Buffer source of data to be written over original aml + @param[in] Length length of data to be overwritten + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +UpdateNameAslCode( + IN UINT32 AslSignature, + IN VOID *Buffer, + IN UINTN Length + ); + +/** + This function locates an ACPI structure and updates it. + This function knows how to update operation regions and BUFA/BUFB resource structures. + + This function may not be implemented in all instantiations of this library. + + @param[in] AslSignature The signature of Operation Region that we want to update. + @param[in] BufferName signature of the Buffer inside OpRegion that we want to update + @param[in] MacroAmlEncoding type of entry inside Buffer. + @param[in] MacroEntryNumber number of entry of the above type + @param[in] Offset offset (in bytes) inside entry where update will be performed + @param[in] Buffer source of data to be written over original aml + @param[in] Length length of data to be overwritten + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +UpdateResourceTemplateAslCode ( + IN UINT32 AslSignature, + IN UINT32 BufferName, + IN UINT8 MacroAmlEncoding, + IN UINT8 MacroEntryNumber, + IN UINT8 Offset, + IN VOID *Buffer, + IN UINTN Length + ); + +/** + This function uses the ACPI support protocol to locate an ACPI table using the . + It is really only useful for finding tables that only have a single instance, + e.g. FADT, FACS, MADT, etc. It is not good for locating SSDT, etc. + Matches are determined by finding the table with ACPI table that has + a matching signature and version. + + @param[in] TableId Pointer to an ASCII string containing the Signature to match + @param[in out] Table Updated with a pointer to the table + @param[in out] Handle AcpiSupport protocol table handle for the table found + @param[in out] Version On input, the version of the table desired, + on output, the versions the table belongs to + (see AcpiSupport protocol for details) + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +LocateAcpiTableBySignature ( + IN UINT32 Signature, + IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table, + IN OUT UINTN *Handle, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ); + +/** + This function uses the ACPI support protocol to locate an ACPI SSDT table. + The table is located by searching for a matching OEM Table ID field. + Partial match searches are supported via the TableIdSize parameter. + + @param[in] TableId Pointer to an ASCII string containing the OEM Table ID from the ACPI table header + @param[in] TableIdSize Length of the TableId to match. Table ID are 8 bytes long, this function + will consider it a match if the first TableIdSize bytes match + @param[in out] Table Updated with a pointer to the table + @param[in out] Handle AcpiSupport protocol table handle for the table found + @param[in out] Version See AcpiSupport protocol, GetAcpiTable function for use + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +LocateAcpiTableByOemTableId ( + IN UINT8 *TableId, + IN UINT8 TableIdSize, + IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table, + IN OUT UINTN *Handle, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ); + +/** + This function calculates and updates an UINT8 checksum. + + @param[in] Buffer Pointer to buffer to checksum + @param[in] Size Number of bytes to checksum + @param[in] ChecksumOffset Offset to place the checksum result in + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +EFI_BOOTSERVICE +AcpiChecksum ( + IN VOID *Buffer, + IN UINTN Size, + IN UINTN ChecksumOffset + ); + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.c b/ReferenceCode/Chipset/LynxPoint/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.c new file mode 100644 index 0000000..919ab50 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.c @@ -0,0 +1,474 @@ +/** @file + Boot service DXE ASL update library implementation. + + These functions in this file can be called during DXE and cannot be called during runtime + or in SMM which should use a RT or SMM library. + + This library uses the ACPI Support protocol. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGlueDxe.h" +#endif +#include "PchAslUpdateLib.h" + +// +// Function implemenations +// +static EFI_ACPI_SUPPORT_PROTOCOL *mAcpiSupport = NULL; +static EFI_ACPI_TABLE_PROTOCOL *mAcpiTable = NULL; + +/** + Initialize the ASL update library state. + This must be called prior to invoking other library functions. + + @param[in] None + + @retval EFI_SUCCESS - The function completed successfully. +**/ +EFI_STATUS +InitializePchAslUpdateLib ( + VOID + ) +{ + EFI_STATUS Status; + + /// + /// Locate ACPI tables + /// + Status = gBS->LocateProtocol (&gEfiAcpiSupportGuid, NULL, (VOID **) &mAcpiSupport); + Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &mAcpiTable); + return Status; +} + +/** + This procedure will update immediate value assigned to a Name + + @param[in] AslSignature - The signature of Operation Region that we want to update. + @param[in] Buffer - source of data to be written over original aml + @param[in] Length - length of data to be overwritten + + @retval EFI_SUCCESS - The function completed successfully. +**/ +EFI_STATUS +UpdateNameAslCode( + IN UINT32 AslSignature, + IN VOID *Buffer, + IN UINTN Length + ) +{ + EFI_STATUS Status; + EFI_ACPI_DESCRIPTION_HEADER *Table; + EFI_ACPI_TABLE_VERSION Version; + UINT8 *CurrPtr; + UINT32 *Signature; + UINT8 *DsdtPointer; + UINT8 Index; + UINTN Handle; + UINT8 DataSize; + + /// + /// Locate table with matching ID + /// + Index = 0; + + do { + Status = mAcpiSupport->GetAcpiTable (mAcpiSupport, Index, (VOID **) &Table, &Version, &Handle); + if (Status == EFI_NOT_FOUND) { + break; + } + + ASSERT_EFI_ERROR (Status); + Index++; + } while (Table->Signature != EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE); + + /// + /// Point to the beginning of the DSDT table + /// + Index = 0; + CurrPtr = (UINT8 *) Table; + + /// + /// Loop through the ASL looking for values that we must fix up. + /// + for (DsdtPointer = CurrPtr; DsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length); DsdtPointer++) { + /// + /// Get a pointer to compare for signature + /// + Signature = (UINT32 *) DsdtPointer; + /// + /// Check if this is the Device Object signature we are looking for + /// + if ((*Signature) == AslSignature) { + /// + /// Look for Name Encoding + /// + if(*(DsdtPointer-1) == AML_NAME_OP){ + /// + /// Check if size of new and old data is the same + /// + DataSize = *(DsdtPointer+4); + if ((Length == 1 && DataSize == 0xA) || + (Length == 2 && DataSize == 0xB) || + (Length == 4 && DataSize == 0xC) ) { + CopyMem (DsdtPointer+5, Buffer, Length); + } else if (Length == 1 && ((*(UINT8*)Buffer) == 0 || (*(UINT8*)Buffer) == 1) && (DataSize == 0 || DataSize == 1)) { + CopyMem (DsdtPointer+4, Buffer, Length); + } else { + FreePool (Table); + return EFI_BAD_BUFFER_SIZE; + } +#ifdef AMI_OVERRIDE_FOR_ACPI + Status = mAcpiTable->UninstallAcpiTable ( + mAcpiTable, + Handle + ); + Handle = 0; +#endif //AMI_OVERRIDE_FOR_ACPI + Status = mAcpiTable->InstallAcpiTable ( + mAcpiTable, + Table, + Table->Length, + &Handle + ); + FreePool (Table); + return Status; + } + } + } + return EFI_NOT_FOUND; +} + +/** + This procedure will update a Resource Descriptor Macro in + Resrouce Template buffer list. + + @param[in] AslSignature - The signature of Operation Region that we want to update. + @param[in] BufferName - signature of the Buffer inside OpRegion that we want to update + @param[in] MacroAmlEncoding - type of entry inside Buffer. + @param[in] MacroEntryNumber - number of entry of the above type + @param[in] Offset - offset (in bytes) inside entry where update will be performed + @param[in] Buffer - source of data to be written over original aml + @param[in] Length - length of data to be overwritten + + @retval EFI_SUCCESS - The function completed successfully. +**/ +EFI_STATUS +UpdateResourceTemplateAslCode ( + IN UINT32 AslSignature, + IN UINT32 BufferName, + IN UINT8 MacroAmlEncoding, + IN UINT8 MacroEntryNumber, + IN UINT8 Offset, + IN VOID *Buffer, + IN UINTN Length + ) +{ + EFI_STATUS Status; + EFI_ACPI_DESCRIPTION_HEADER *Table; + EFI_ACPI_TABLE_VERSION Version; + UINT8 *CurrPtr; + UINT8 *Operation; + UINT32 *Signature; + UINT8 *DsdtPointer; + UINT8 Index; + UINTN Handle; + UINT32 AslLength; + BOOLEAN EntryFound; + + /// + /// Locate table with matching ID + /// + Index = 0; + AslLength = 0; + EntryFound = FALSE; + + do { + Status = mAcpiSupport->GetAcpiTable (mAcpiSupport, Index, (VOID **)&Table, &Version, &Handle); + if (Status == EFI_NOT_FOUND) { + break; + } + + ASSERT_EFI_ERROR (Status); + Index++; + } while (Table->Signature != EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE); + + /// + /// Point to the beginning of the DSDT table + /// + Index = 0; + CurrPtr = (UINT8 *) Table; + + /// + /// Loop through the ASL looking for values that we must fix up. + /// + for (DsdtPointer = CurrPtr; DsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length); DsdtPointer++) { + /// + /// Get a pointer to compare for signature + /// + Signature = (UINT32 *) DsdtPointer; + + /// + /// Check if this is the Device Object signature we are looking for + /// + if ((*Signature) == AslSignature) { + /// + /// Read the Device Object block length + /// + if (*(UINT16 *)(DsdtPointer - 3) == AML_DEVICE_OP) { + AslLength = *(DsdtPointer - 1); + } else if (*(UINT16 *)(DsdtPointer - 4) == AML_DEVICE_OP) { + AslLength = *(UINT16 *)(DsdtPointer - 2); + AslLength = (AslLength & 0x0F) + ((AslLength & 0x0FF00) >> 4); + } else if (*(UINT16 *)(DsdtPointer - 5) == AML_DEVICE_OP) { + AslLength = *(UINT32 *)(DsdtPointer - 3) & 0x00FFFFFFFF; + AslLength = (AslLength & 0x0F) + ((AslLength & 0x0000FF00) >> 4) + ((AslLength & 0x00FF0000) >> 4); + } else if (*(UINT16 *)(DsdtPointer - 6) == AML_DEVICE_OP) { + AslLength = *(UINT32 *)(DsdtPointer - 4); + AslLength = (AslLength & 0x0F) + ((AslLength & 0x0000FF00) >> 4) + ((AslLength & 0x00FF0000) >> 4) + ((AslLength & 0xFF000000) >> 4); + } else { + continue; //Search for next instance + } + + /// + /// Conditional match. Search AML Encoding in Device. + /// + for (Operation = DsdtPointer; Operation <= DsdtPointer + AslLength; Operation++) { + /// + /// Look for Name Encoding + /// + while(Operation <= DsdtPointer + AslLength) { + if(*Operation == AML_NAME_OP){ + /// + /// Found Name AML Encoding + /// + Operation++; + if(*(UINT32 *)(Operation) == BufferName) { + /// + /// Found RBUF Resource Template object name + /// + break; + } + } + Operation++; + } + + if(Operation > DsdtPointer + AslLength ){ + continue; //Search for next instance + } + + /// + /// Now look for the Resource Template Object buffer opcode + /// + while((*Operation) != AML_BUFFER_OP) { + Operation++; + if(Operation > DsdtPointer + AslLength){ + FreePool (Table); + return EFI_NOT_FOUND; + } + } + + /// + /// Now look for the Macro to be updated until + /// (1) it is found OR (2) reach end of resource template + /// + while(*(UINT16 *)(Operation) != AML_RESRC_TEMP_END_TAG) { + if((*Operation == MacroAmlEncoding)) { + /// + /// We found a matching encoding however, the buffer list may have "n" number + /// of same encoding entries. Let's narrow down to the "n"th entry. + /// + Index++; + if(Index == MacroEntryNumber) { + /// + /// Get to the starting offset & end offset + /// + Operation += Offset; + + /// + /// Fixup the value at the offset + /// + CopyMem ((VOID *) Operation, (VOID *) (Buffer), Length); + + /// + /// Update the modified ACPI table + /// +#ifdef AMI_OVERRIDE_FOR_ACPI + Status = mAcpiTable->UninstallAcpiTable ( + mAcpiTable, + Handle + ); + Handle = 0; +#endif //AMI_OVERRIDE_FOR_ACPI + Status = mAcpiTable->InstallAcpiTable ( + mAcpiTable, + Table, + Table->Length, + &Handle + ); + FreePool (Table); + return Status; + } + } + Operation++; + } + + if(Operation > DsdtPointer + AslLength) { + FreePool (Table); + return EFI_NOT_FOUND; + } + } + } + } + + return EFI_NOT_FOUND; +} + +/** + This function uses the ACPI support protocol to locate an ACPI table. + It is really only useful for finding tables that only have a single instance, + e.g. FADT, FACS, MADT, etc. It is not good for locating SSDT, etc. + + @param[in] Signature - Pointer to an ASCII string containing the OEM Table ID from the ACPI table header + @param[in, out] Table - Updated with a pointer to the table + @param[in, out] Handle - AcpiSupport protocol table handle for the table found + @param[in, out] Version - The version of the table desired + + @retval EFI_SUCCESS - The function completed successfully. +**/ +EFI_STATUS +LocateAcpiTableBySignature ( + IN UINT32 Signature, + IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table, + IN OUT UINTN *Handle, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +{ + EFI_STATUS Status; + INTN Index; + EFI_ACPI_TABLE_VERSION DesiredVersion; + + DesiredVersion = *Version; + /// + /// Locate table with matching ID + /// + Index = 0; + do { + Status = mAcpiSupport->GetAcpiTable (mAcpiSupport, Index, (VOID **)Table, Version, Handle); + if (Status == EFI_NOT_FOUND) { + break; + } + + ASSERT_EFI_ERROR (Status); + Index++; + } while ((*Table)->Signature != Signature || !(*Version & DesiredVersion)); + + /// + /// If we found the table, there will be no error. + /// + return Status; +} + +/** + This function uses the ACPI support protocol to locate an ACPI SSDT table. + + @param[in] TableId - Pointer to an ASCII string containing the OEM Table ID from the ACPI table header + @param[in] TableIdSize - Length of the TableId to match. Table ID are 8 bytes long, this function + will consider it a match if the first TableIdSize bytes match + @param[in, out] Table - Updated with a pointer to the table + @param[in, out] Handle - AcpiSupport protocol table handle for the table found + @param[in, out] Version - See AcpiSupport protocol, GetAcpiTable function for use + + @retval EFI_SUCCESS - The function completed successfully. +**/ +EFI_STATUS +LocateAcpiTableByOemTableId ( + IN UINT8 *TableId, + IN UINT8 TableIdSize, + IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table, + IN OUT UINTN *Handle, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +{ + EFI_STATUS Status; + INTN Index; + + /// + /// Locate table with matching ID + /// + Index = 0; + do { + Status = mAcpiSupport->GetAcpiTable (mAcpiSupport, Index, (VOID **)Table, Version, Handle); + if (Status == EFI_NOT_FOUND) { + break; + } + + ASSERT_EFI_ERROR (Status); + Index++; + } while (CompareMem (&(*Table)->OemTableId, TableId, TableIdSize)); + + /// + /// If we found the table, there will be no error. + /// + return Status; +} + +/** + This function calculates and updates an UINT8 checksum. + + @param[in] Buffer Pointer to buffer to checksum + @param[in] Size Number of bytes to checksum + @param[in] ChecksumOffset Offset to place the checksum result in + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +AcpiChecksum ( + IN VOID *Buffer, + IN UINTN Size, + IN UINTN ChecksumOffset + ) +{ + UINT8 Sum; + UINT8 *Ptr; + + Sum = 0; + /// + /// Initialize pointer + /// + Ptr = Buffer; + + /// + /// set checksum to 0 first + /// + Ptr[ChecksumOffset] = 0; + + /// + /// add all content of buffer + /// + while (Size--) { + Sum = (UINT8) (Sum + (*Ptr++)); + } + /// + /// set checksum + /// + Ptr = Buffer; + Ptr[ChecksumOffset] = (UINT8) (0xff - Sum + 1); + + return EFI_SUCCESS; +} diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.cif b/ReferenceCode/Chipset/LynxPoint/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.cif new file mode 100644 index 0000000..79bdb6e --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.cif @@ -0,0 +1,11 @@ +<component> + name = "PchAslUpdateLib" + category = ModulePart + LocalRoot = "ReferenceCode\Chipset\LynxPoint\SampleCode\Library\AslUpdate\Dxe\" + RefName = "PchAslUpdateLib" +[files] +"PchAslUpdateLib.sdl" +"PchAslUpdateLib.mak" +"PchAslUpdateLib.c" +"PchAslUpdateLib.inf" +<endComponent> diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.inf b/ReferenceCode/Chipset/LynxPoint/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.inf new file mode 100644 index 0000000..c0a0509 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.inf @@ -0,0 +1,66 @@ +## @file +# Provides services to update ASL tables. +# +#@copyright +# Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +[defines] +BASE_NAME = PchAslUpdateLib +COMPONENT_TYPE = LIBRARY + +[sources.common] + PchAslUpdateLib.c + +[includes.common] + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Library/Dxe/Include +# +# Typically the sample code referenced will be available in the code base already +# So keep this include at the end to defer to the source base definition +# and only use the sample code definition if source base does not include these files. +# + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/SampleCode/Include + +# +# Edk II Glue Library, some hearder are included by R9 header so have to include +# + + $(EFI_SOURCE) + $(EFI_SOURCE)/Framework + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + +[libraries.common] + EdkIIGlueBaseMemoryLib + EdkIIGlueUefiBootServicesTableLib + EdkIIGlueUefiRuntimeServicesTableLib + +[nmake.common] + + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_BASE_MEMORY_LIB__ \ + -D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \ + -D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.mak b/ReferenceCode/Chipset/LynxPoint/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.mak new file mode 100644 index 0000000..5f59035 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.mak @@ -0,0 +1,83 @@ +#********************************************************************** +#********************************************************************** +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#********************************************************************** +#********************************************************************** + +#********************************************************************** +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/PchSampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.mak 1 7/02/12 9:37a Victortu $ +# +# $Revision: 1 $ +# +# $Date: 7/02/12 9:37a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/PchSampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.mak $ +# +# 1 7/02/12 9:37a Victortu +# PchAslUpdateLib initially releases. +# +# 6 1/13/10 2:13p Felixp +# +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: PchAslUpdateLib.mak +# +# Description: +# +#<AMI_FHDR_END> +#********************************************************************** +all : PchAslUpdateLib + +$(PchAslUpdateLib_LIB) : PchAslUpdateLib + +PchAslUpdateLib : $(BUILD_DIR)\PchAslUpdateLib.mak PchAslUpdateLibBin + +$(BUILD_DIR)\PchAslUpdateLib.mak : $(PchAslUpdateLib_DIR)\$(@B).cif $(PchAslUpdateLib_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(PchAslUpdateLib_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +PchAslUpdateLib_INCLUDES=\ + $(EDK_INCLUDES) \ + $(EdkIIGlueLib_INCLUDES)\ + /I$(INTEL_PCH_DIR)\SampleCode\Include + +PchAslUpdateLib_DEFINES = \ + $(MY_DEFINES)\ + /D __EDKII_GLUE_BASE_MEMORY_LIB__\ + /D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__\ + /D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ + +PchAslUpdateLib_LIBS=\ + $(EdkIIGlueBaseMemoryLib_LIB)\ + $(EdkIIGlueUefiBootServicesTableLib_LIB)\ + $(EdkIIGlueUefiRuntimeServicesTableLib_LIB)\ + +PchAslUpdateLibBin: $(PchAslUpdateLib_LIBS) + $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS) \ + /f $(BUILD_DIR)\PchAslUpdateLib.mak all \ + "MY_INCLUDES=$(PchAslUpdateLib_INCLUDES)" \ + "MY_DEFINES=$(PchAslUpdateLib_DEFINES)"\ + TYPE=LIBRARY +#********************************************************************** +#********************************************************************** +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#********************************************************************** +#**********************************************************************
\ No newline at end of file diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.sdl b/ReferenceCode/Chipset/LynxPoint/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.sdl new file mode 100644 index 0000000..c52b5a8 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/Library/AslUpdate/Dxe/PchAslUpdateLib.sdl @@ -0,0 +1,29 @@ +TOKEN + Name = PchAslUpdateLib_SUPPORT + Value = 1 + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable PchAslUpdateLib support in Project" +End + +MODULE + Help = "Includes PchAslUpdateLib.mak to Project" + File = "PchAslUpdateLib.mak" +End + +PATH + Name = "PchAslUpdateLib_DIR" +End + +ELINK + Name = "PchAslUpdateLib_LIB" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "$(BUILD_DIR)\PchAslUpdateLib.lib" + Parent = "PchAslUpdateLib_LIB" + InvokeOrder = AfterParent +End
\ No newline at end of file diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Common/PchPolicyInitCommon.c b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Common/PchPolicyInitCommon.c new file mode 100644 index 0000000..8845a6d --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Common/PchPolicyInitCommon.c @@ -0,0 +1,427 @@ +/** @file + This file is SampleCode for Intel PCH Common Platform Policy initialzation. + +@copyright + Copyright (c) 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGlueDxe.h" +#include "EdkIIGlueBase.h" +#include "PchPlatformPolicy.h" +#include "PchPlatformLib.h" +#include "PchRegs.h" +#endif + +/** + Initilize Intel USB Common Platform Policy + + @param[in] PchUsbConfig Usb platform policy structure. + + @retval NONE +**/ +VOID +InitPchUsbConfig ( + IN PCH_USB_CONFIG *PchUsbConfig + ) +{ + UINTN PortIndex; + UINT16 LpcDeviceId; + PCH_SERIES PchSeries; + + if (PchUsbConfig == NULL) { + return; + } + + PchSeries = GetPchSeries(); + LpcDeviceId = MmioRead16 (MmPciAddress (0, 0, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC, 0) + R_PCH_LPC_DEVICE_ID); + + // + // EHCI Host Controller Enable/Disable + // + PchUsbConfig->Usb20Settings[0].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->Usb20Settings[1].Enable = PCH_DEVICE_ENABLE; + + // + // Automatically disable EHCI when XHCI Mode is Enabled to save power. + // + if (PchUsbConfig->Usb30Settings.Mode == PCH_XHCI_MODE_ON) { + PchUsbConfig->Usb20Settings[0].Enable = PCH_DEVICE_DISABLE; + if (PchSeries == PchH) { + PchUsbConfig->Usb20Settings[1].Enable = PCH_DEVICE_DISABLE; + } + } + // + // Set to Enable if BIOS has its own xHCI driver + // + PchUsbConfig->Usb30Settings.PreBootSupport = PCH_DEVICE_ENABLE; + /// + /// PCH BIOS Spec Rev 0.5.0 Section 13.1 xHCI controller options in Reference Code + /// Please refer to Table 13-1 in PCH BIOS Spec for USB Port Operation with no xHCI + /// pre-boot software. + /// Please refer to Table 13-2 in PCH BIOS Spec for USB Port Operation with xHCI + /// pre-boot software. + /// + /// The xHCI modes that available in BIOS are: + /// Disabled - forces only USB 2.0 to be supported in the OS. The xHCI controller is turned off + /// and hidden from the PCI space. + /// Enabled - allows USB 3.0 to be supported in the OS. The xHCI controller is turned on. The + /// shareable ports are routed to the xHCI controller. OS needs to provide drivers + /// to support USB 3.0. + /// Auto - This mode uses ACPI protocol to provide an option that enables the xHCI controller + /// and reroute USB ports via the _OSC ACPI method call. Note, this mode switch requires + /// special OS driver support for USB 3.0. + /// Smart Auto - This mode is similar to Auto, but it adds the capability to route the ports to xHCI + /// or EHCI according to setting used in previous boots (for non-G3 boot) in the pre-boot + /// environment. This allows the use of USB 3.0 devices prior to OS boot. Note, this mode + /// switch requires special OS driver support for USB 3.0 and USB 3.0 software available + /// in the pre-boot enviroment. + /// + /// Manual Mode - For validation and experimental purposes only. Do not create setup option for end-user BIOS. + /// + /// Recommendations: + /// - If BIOS supports xHCI pre-boot driver then use Smart Auto mode as default + /// - If BIOS does not support xHCI pre-boot driver then use AUTO mode as default + /// + if (PchUsbConfig->Usb30Settings.PreBootSupport == PCH_DEVICE_ENABLE) { + PchUsbConfig->Usb30Settings.Mode = PCH_XHCI_MODE_SMARTAUTO; + } else { + PchUsbConfig->Usb30Settings.Mode = PCH_XHCI_MODE_AUTO; + } + + // + // Manual Mode is for validation and experimental purposes only. + // Do not create setup option for end-user BIOS. + // + PchUsbConfig->Usb30Settings.ManualMode = PCH_DEVICE_DISABLE; + + // + // XhciIdleL1 can be set to disable for LPT-LP Ax stepping to workaround USB3 hot plug will fail after 1 hot plug removal. + // + PchUsbConfig->Usb30Settings.XhciIdleL1 = PCH_DEVICE_ENABLE; + + // + // Btcg is for enabling/disabling trunk clock gating. + // + PchUsbConfig->Usb30Settings.Btcg = PCH_DEVICE_ENABLE; + + for (PortIndex = 0; PortIndex < GetPchUsbMaxPhysicalPortNum (); PortIndex++) { + PchUsbConfig->Usb30Settings.ManualModeUsb20PerPinRoute[PortIndex] = 0; + } + + for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) { + PchUsbConfig->Usb30Settings.ManualModeUsb30PerPinEnable[PortIndex] = PCH_DEVICE_DISABLE; + } + + // + // Use by AMT/MEBx to enable USB-R support. + // + PchUsbConfig->Ehci1Usbr = PCH_DEVICE_DISABLE; + PchUsbConfig->Ehci2Usbr = PCH_DEVICE_DISABLE; + + // + // UsbPrecondition = Enable , Force USB Init happen in PEI as part of 2Sec Fast Boot bios optimization + // UsbPrecondition = Disable, USB Init happen in DXE just like traditionally where it happen. + // + PchUsbConfig->UsbPrecondition = PCH_DEVICE_DISABLE; + + // + // USB Per-Port Control is use to Enable/Disable individual port. + // + PchUsbConfig->UsbPerPortCtl = PCH_DEVICE_DISABLE; + + PchUsbConfig->PortSettings[0].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[1].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[2].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[3].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[4].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[5].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[6].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[7].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[8].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[9].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[10].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[11].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[12].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->PortSettings[13].Enable = PCH_DEVICE_ENABLE; + + PchUsbConfig->Port30Settings[0].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->Port30Settings[1].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->Port30Settings[2].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->Port30Settings[3].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->Port30Settings[4].Enable = PCH_DEVICE_ENABLE; + PchUsbConfig->Port30Settings[5].Enable = PCH_DEVICE_ENABLE; + + // + // USB Port Over Current Pins mapping, please set as per board layout. + // + PchUsbConfig->Usb20OverCurrentPins[ 0] = PchUsbOverCurrentPin0; + PchUsbConfig->Usb20OverCurrentPins[ 1] = PchUsbOverCurrentPin0; + PchUsbConfig->Usb20OverCurrentPins[ 2] = PchUsbOverCurrentPin1; + PchUsbConfig->Usb20OverCurrentPins[ 3] = PchUsbOverCurrentPin1; + PchUsbConfig->Usb20OverCurrentPins[ 4] = PchUsbOverCurrentPin2; + PchUsbConfig->Usb20OverCurrentPins[ 5] = PchUsbOverCurrentPin2; + PchUsbConfig->Usb20OverCurrentPins[ 6] = PchUsbOverCurrentPin3; + PchUsbConfig->Usb20OverCurrentPins[ 7] = PchUsbOverCurrentPin3; + PchUsbConfig->Usb20OverCurrentPins[ 8] = PchUsbOverCurrentPin4; + PchUsbConfig->Usb20OverCurrentPins[ 9] = PchUsbOverCurrentPin4; + PchUsbConfig->Usb20OverCurrentPins[10] = PchUsbOverCurrentPin5; + PchUsbConfig->Usb20OverCurrentPins[11] = PchUsbOverCurrentPin5; + PchUsbConfig->Usb20OverCurrentPins[12] = PchUsbOverCurrentPin6; + PchUsbConfig->Usb20OverCurrentPins[13] = PchUsbOverCurrentPin6; + + PchUsbConfig->Usb30OverCurrentPins[0] = PchUsbOverCurrentPin0; + PchUsbConfig->Usb30OverCurrentPins[1] = PchUsbOverCurrentPin0; + PchUsbConfig->Usb30OverCurrentPins[2] = PchUsbOverCurrentPin1; + PchUsbConfig->Usb30OverCurrentPins[3] = PchUsbOverCurrentPin1; + PchUsbConfig->Usb30OverCurrentPins[4] = PchUsbOverCurrentPin2; + PchUsbConfig->Usb30OverCurrentPins[5] = PchUsbOverCurrentPin2; + + // + // USB 2.0 D+/D- trace length in inchs*10 or 1000mils/10 measurement eg. 12.3" = 0x123 + // Please set as per board layout. + // + PchUsbConfig->PortSettings[ 0].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[ 1].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[ 2].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[ 3].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[ 4].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[ 5].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[ 6].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[ 7].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[ 8].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[ 9].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[10].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[11].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[12].Usb20PortLength = 0x100; + PchUsbConfig->PortSettings[13].Usb20PortLength = 0x100; + + // + // Port Location + // + PchUsbConfig->PortSettings[ 0].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[ 1].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[ 2].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[ 3].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[ 4].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[ 5].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[ 6].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[ 7].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[ 8].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[ 9].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[10].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[11].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[12].Location = PchUsbPortLocationFrontPanel; + PchUsbConfig->PortSettings[13].Location = PchUsbPortLocationFrontPanel; + +/* + Guideline: + This algorithm is move from chipset level code to board level code to allow OEM more flexibility + to tune the value for individual board layout electrical characteristics to pass the USB 2.0 Eye Diagram Test. + + IF Board=LPT-H Desktop + For BIT[10:08] Usb20EyeDiagramTuningParam1 (PERPORTTXISET) + IF Back Panel + SET to 4 + ELSE + SET to 3 + ENDIF + + For BIT[13:11] Usb20EyeDiagramTuningParam2 (PERPORTPETXISET) + IF Back Panel + IF Trace Length < 8" + SET to 2 + ELSE IF Trace Length < 13" + SET to 3 + ELSE + SET to 4 + ENDIF + ELSE + SET to 2 + ENDIF + + For BIT[14] + Always SET to 0 + + END LPT-H Desktop + + IF Board=LPT-H Mobile + For BIT[10:08] Usb20EyeDiagramTuningParam1 (PERPORTTXISET) + IF Interal Topology + SET to 5 + ELSE IF Dock + SET to 4 + ELSE + IF Trace Length < 7" + SET to 5 + ELSE + SET to 6 + ENDIF + ENDIF + + For BIT[13:11] Usb20EyeDiagramTuningParam2 (PERPORTPETXISET) + IF Interal Topology + SET to 2 + ELSE IF Dock + IF Trace Length < 5" + SET to 1 + ELSE + SET to 2 + ENDIF + ELSE + IF Trace Length < 10" + SET to 2 + ELSE + SET to 3 + ENDIF + ENDIF + + For BIT[14] + Always SET to 0 + END LPT-H Mobile + + IF Board=LPT-LP + For BIT[10:08] Usb20EyeDiagramTuningParam1 (PERPORTTXISET) + IF Back Panel OR MiniPciE + IF Trace Length < 7" + SET to 5 + ELSE + SET to 6 + ENDIF + ELSE IF Dock + SET to 4 + ELSE + SET to 5 + ENDIF + + For BIT[13:11] Usb20EyeDiagramTuningParam2 (PERPORTPETXISET) + IF Back Panel OR MiniPciE + IF Trace Length < 10" + SET to 2 + ELSE + SET to 3 + ENDIF + ELSE IF Dock + IF Trace Length < 5" + SET to 1 + ELSE + SET to 2 + ENDIF + ELSE + SET to 2 + ENDIF + + For BIT[14] + Always SET to 0 + END LPT-LP +*/ + + // + // USB 2.0 trace length signal strength + // +/* + IF Board=LPT-H Mobile + + END LPT-H Mobile +*/ + + if (PchSeries == PchH) { + if (IS_PCH_LPT_LPC_DEVICE_ID_DESKTOP (LpcDeviceId)) { + for (PortIndex = 0; PortIndex < GetPchUsbMaxPhysicalPortNum (); PortIndex++) { + if (PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationBackPanel) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 4; //Back Panel + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 3; //Front Panel + } + + if (PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationBackPanel) { + if (PchUsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x80) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Back Panel, less than 7.9" + } else if (PchUsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x130) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 3; //Back Panel, 8"-12.9" + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 4; //Back Panel, 13" onward + } + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Front Panel + } + } + } else if (IS_PCH_LPT_LPC_DEVICE_ID_MOBILE (LpcDeviceId)) { + for (PortIndex = 0; PortIndex < GetPchUsbMaxPhysicalPortNum (); PortIndex++) { + if (PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationInternalTopology) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 5; // Internal Topology + } else if (PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationDock) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 4; // Dock + } else { + if (PchUsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x70) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 5; //Back Panel, less than 7" + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 6; //Back Panel, 7" onward + } + } + + if (PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationInternalTopology) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; // Internal Topology + } else if (PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationDock) { + if (PchUsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x50) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 1; //Dock, less than 5" + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Dock, 5" onward + } + } else { + if (PchUsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x100) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Back Panel, less than 10" + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 3; //Back Panel, 10" onward + } + } + } + } + } else if (PchSeries == PchLp) { + for (PortIndex = 0; PortIndex < GetPchUsbMaxPhysicalPortNum (); PortIndex++) { + if ((PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationBackPanel) || + (PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationMiniPciE)) { + if (PchUsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x70) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 5; //Back Panel, less than 7" + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 6; //Back Panel, 7" onward + } + } else if (PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationDock) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 4; // Dock + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam1 = 5; // Internal Topology + } + + if ((PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationBackPanel) || + (PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationMiniPciE)) { + if (PchUsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x100) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Back Panel, less than 10" + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 3; //Back Panel, 10" onward + } + } else if (PchUsbConfig->PortSettings[PortIndex].Location == PchUsbPortLocationDock) { + if (PchUsbConfig->PortSettings[PortIndex].Usb20PortLength < 0x50) { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 1; //Dock, less than 5" + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; //Dock, 5" onward + } + } else { + PchUsbConfig->PortSettings[PortIndex].Usb20EyeDiagramTuningParam2 = 2; // Internal Topology + } + } + } + + return; +} diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Common/PchPolicyInitCommon.h b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Common/PchPolicyInitCommon.h new file mode 100644 index 0000000..daf1750 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Common/PchPolicyInitCommon.h @@ -0,0 +1,33 @@ +/** @file + Header file for Common PchPolicyInit Library + +@copyright + Copyright (c) 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _PCH_POLICY_INIT_COMMON_H_ +#define _PCH_POLICY_INIT_COMMON_H_ + +/** + This function performs PCH USB Platform Policy initialzation + + @param[in] UsbConfig Pointer to PCH_USB_CONFIG data buffer. + + @retval NONE +**/ +VOID +InitPchUsbConfig ( + IN PCH_USB_CONFIG *UsbConfig + ); +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.c b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.c new file mode 100644 index 0000000..5deee40 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.c @@ -0,0 +1,490 @@ +/** @file + This file is SampleCode for Intel PCH DXE Platform Policy initialzation. + +@copyright + Copyright (c) 2009 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ +#include "PchPolicyInitDxe.h" +#include "..\Common\PchPolicyInitCommon.h" + +#define SW_SMI_BIOS_LOCK 0xA9 +#define PCI_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x00 +#define PCI_CLASS_NETWORK_OTHER 0x80 + +DXE_PCH_PLATFORM_POLICY_PROTOCOL mPchPolicyData = { 0 }; +PCH_DEVICE_ENABLING mPchDeviceEnabling = { 0 }; +PCH_USB_CONFIG mPchUsbConfig = { 0 }; +PCH_PCI_EXPRESS_CONFIG mPchPciExpressConfig = { 0 }; +PCH_SATA_CONFIG mPchSataConfig = { 0 }; +PCH_AZALIA_CONFIG mPchAzaliaConfig = { 0 }; +PCH_SMBUS_CONFIG mPchSmbusConfig = { 0 }; +PCH_MISC_PM_CONFIG mPchMiscPmConfig = { 0 }; +PCH_IO_APIC_CONFIG mPchIoApicConfig = { 0 }; +PCH_DEFAULT_SVID_SID mPchDefaultSvidSid = { 0 }; +PCH_LOCK_DOWN_CONFIG mPchLockDownConfig = { 0 }; +PCH_THERMAL_CONFIG mPchThermalConfig = { 0 }; +PCH_LPC_HPET_CONFIG mPchHpetConfig = { 0 }; +PCH_LPC_SIRQ_CONFIG mSerialIrqConfig = { 0 }; +PCH_DMI_CONFIG mPchDmiConfig = { 0 }; +PCH_PWR_OPT_CONFIG mPchPwrOptConfig = { 0 }; +PCH_MISC_CONFIG mPchMiscConfig = { 0 }; +PCH_AUDIO_DSP_CONFIG mAudioDspConfig = { 0 }; +PCH_SERIAL_IO_CONFIG mSerialIoConfig = { 0 }; + +UINT8 mSmbusRsvdAddresses[4] = { + 0xA0, + 0xA2, + 0xA4, + 0xA6 +}; + +PCH_PCIE_DEVICE_ASPM_OVERRIDE mDevAspmOverride[] = { + // + // Intel PRO/Wireless + // + {0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel WiMAX/WiFi Link + // + {0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Crane Peak WLAN NIC + // + {0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Crane Peak w/BT WLAN NIC + // + {0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Kelsey Peak WiFi, WiMax + // + {0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Centrino Wireless-N 105 + // + {0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Centrino Wireless-N 135 + // + {0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Centrino Wireless-N 2200 + // + {0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Centrino Wireless-N 2230 + // + {0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel Centrino Wireless-N 6235 + // + {0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel CampPeak 2 Wifi + // + {0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + {0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF}, + // + // Intel WilkinsPeak 1 Wifi + // + {0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003}, + {0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003}, + {0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003}, + {0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003}, + // + // Intel Wilkins Peak 2 Wifi + // + {0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003}, + {0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003}, + {0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0154, 0x00000003}, + {0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1SubstatesOverride, 0x0158, 0x00000003}, + // + // Intel Wilkins Peak PF Wifi + // + {0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchPcieAspmL1, PchPcieL1L2Override, 0xFFFF, 0xFFFFFFFF} + +}; + +// +// Function implementations +// + +/** + Initilize Intel PCH DXE Platform Policy + + @param[in] ImageHandle Image handle of this driver. + @param[in] SystemTable Global system service table. + + @retval EFI_SUCCESS Initialization complete. + @exception EFI_UNSUPPORTED The chipset is unsupported by this driver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +PchPolicyInitDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_HANDLE Handle; + EFI_STATUS Status; + UINT8 PortIndex; + UINTN Index; + PCH_SERIES PchSeries; + PchSeries = GetPchSeries(); + // + // General intialization + // + mPchPolicyData.Revision = DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_7; + mPchPolicyData.BusNumber = 0; + + mPchPolicyData.DeviceEnabling = &mPchDeviceEnabling; + mPchPolicyData.UsbConfig = &mPchUsbConfig; + mPchPolicyData.PciExpressConfig = &mPchPciExpressConfig; + mPchPolicyData.SataConfig = &mPchSataConfig; + mPchPolicyData.AzaliaConfig = &mPchAzaliaConfig; + mPchPolicyData.SmbusConfig = &mPchSmbusConfig; + mPchPolicyData.MiscPmConfig = &mPchMiscPmConfig; + mPchPolicyData.IoApicConfig = &mPchIoApicConfig; + mPchPolicyData.DefaultSvidSid = &mPchDefaultSvidSid; + mPchPolicyData.LockDownConfig = &mPchLockDownConfig; + mPchPolicyData.ThermalConfig = &mPchThermalConfig; + mPchPolicyData.HpetConfig = &mPchHpetConfig; + mPchPolicyData.SerialIrqConfig = &mSerialIrqConfig; + mPchPolicyData.DmiConfig = &mPchDmiConfig; + mPchPolicyData.PwrOptConfig = &mPchPwrOptConfig; + mPchPolicyData.MiscConfig = &mPchMiscConfig; + mPchPolicyData.AudioDspConfig = &mAudioDspConfig; + mPchPolicyData.SerialIoConfig = &mSerialIoConfig; + + /// + /// PCH BIOS Spec Rev 0.5.0 Section 3.6 Flash Security Recommendations, + /// Intel strongly recommends that BIOS sets the BIOS Interface Lock Down bit. Enabling this bit + /// will mitigate malicious software attempts to replace the system BIOS option ROM with its own code. + /// We always enable this as a platform policy. + /// + mPchLockDownConfig.BiosInterface = PCH_DEVICE_ENABLE; + mPchLockDownConfig.GlobalSmi = PCH_DEVICE_ENABLE; + mPchLockDownConfig.GpioLockDown = PCH_DEVICE_DISABLE; + mPchLockDownConfig.RtcLock = PCH_DEVICE_ENABLE; + /// + /// While BiosLock is enabled, BIOS can only be modified from SMM after ExitPmAuth. + /// + mPchLockDownConfig.BiosLock = PCH_DEVICE_DISABLE; + /// + /// If PchBiosLockIoTrapAddress is 0, BIOS will allocate available IO address with + /// 256 byte range from GCD and pass it to PchBiosLockIoTrapAddress. + /// + mPchLockDownConfig.PchBiosLockIoTrapAddress = 0; + /// + /// Initialize policy to default values when variable isn't found. + /// + mPchDeviceEnabling.Lan = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.Azalia = 2; + mPchDeviceEnabling.Sata = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.Smbus = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.PciClockRun = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.Display = 1; + mPchDeviceEnabling.Crid = PCH_DEVICE_DISABLE; + mPchDeviceEnabling.SerialIoDma = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.SerialIoI2c0 = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.SerialIoI2c1 = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.SerialIoSpi0 = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.SerialIoSpi1 = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.SerialIoUart0 = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.SerialIoUart1 = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.SerialIoSdio = PCH_DEVICE_ENABLE; + mPchDeviceEnabling.AudioDsp = PCH_DEVICE_DISABLE; + + /// + /// Init USB related setting + /// + InitPchUsbConfig (&mPchUsbConfig); + + /// + /// PCI Express related settings from setup variable + /// + mPchPciExpressConfig.RootPortClockGating = PCH_DEVICE_ENABLE; + mPchPciExpressConfig.TempRootPortBusNumMin = 2; + mPchPciExpressConfig.TempRootPortBusNumMax = 4; + + for (PortIndex = 0; PortIndex < GetPchMaxPciePortNum (); PortIndex++) { + mPchPciExpressConfig.RootPort[PortIndex].Enable = PCH_DEVICE_ENABLE; + mPchPciExpressConfig.RootPort[PortIndex].FunctionNumber = PortIndex; + mPchPciExpressConfig.RootPort[PortIndex].PhysicalSlotNumber = PortIndex; + mPchPciExpressConfig.RootPort[PortIndex].Aspm = 4; + mPchPciExpressConfig.RootPort[PortIndex].SlotImplemented = 1; + mPchPciExpressConfig.RootPort[PortIndex].L1Substates = 3; + + } + mPchPciExpressConfig.RootPort[7].HotPlug = 1; + mPchPciExpressConfig.NumOfDevAspmOverride = sizeof (mDevAspmOverride) / sizeof (PCH_PCIE_DEVICE_ASPM_OVERRIDE); + mPchPciExpressConfig.DevAspmOverride = mDevAspmOverride; + mPchPciExpressConfig.EnableSubDecode = 0; + mPchPciExpressConfig.PchPcieSbdePort = 0; + mPchPciExpressConfig.RootPortFunctionSwapping = 1; + + for (PortIndex = 0; PortIndex < GetPchMaxSataPortNum (); PortIndex++) { + mPchSataConfig.PortSettings[PortIndex].Enable = PCH_DEVICE_ENABLE; + mPchSataConfig.PortSettings[PortIndex].HotPlug = PCH_DEVICE_DISABLE; + mPchSataConfig.PortSettings[PortIndex].InterlockSw = PCH_DEVICE_DISABLE; + mPchSataConfig.PortSettings[PortIndex].External = PCH_DEVICE_DISABLE; + mPchSataConfig.PortSettings[PortIndex].SpinUp = PCH_DEVICE_DISABLE; + mPchSataConfig.PortSettings[PortIndex].SolidStateDrive = PCH_DEVICE_DISABLE; + mPchSataConfig.PortSettings[PortIndex].DevSlp = PCH_DEVICE_DISABLE; + mPchSataConfig.PortSettings[PortIndex].EnableDitoConfig = PCH_DEVICE_DISABLE; + mPchSataConfig.PortSettings[PortIndex].DmVal = 15; + mPchSataConfig.PortSettings[PortIndex].DitoVal = 625; + } + + mPchSataConfig.RaidAlternateId = PCH_DEVICE_DISABLE; + mPchSataConfig.Raid0 = PCH_DEVICE_ENABLE; + mPchSataConfig.Raid1 = PCH_DEVICE_ENABLE; + mPchSataConfig.Raid10 = PCH_DEVICE_ENABLE; + mPchSataConfig.Raid5 = PCH_DEVICE_ENABLE; + mPchSataConfig.Irrt = PCH_DEVICE_ENABLE; + mPchSataConfig.OromUiBanner = PCH_DEVICE_ENABLE; + mPchSataConfig.HddUnlock = PCH_DEVICE_ENABLE; + mPchSataConfig.LedLocate = PCH_DEVICE_ENABLE; + mPchSataConfig.IrrtOnly = PCH_DEVICE_ENABLE; + mPchSataConfig.SmartStorage = PCH_DEVICE_ENABLE; + mPchSataConfig.OromUiDelay = PchSataOromDelay2sec; + mPchSataConfig.TestMode = PCH_DEVICE_DISABLE; + mPchSataConfig.SalpSupport = PCH_DEVICE_ENABLE; + mPchSataConfig.LegacyMode = PCH_DEVICE_DISABLE; + mPchSataConfig.SpeedSupport = PchSataSpeedSupportDefault; + + /// + /// AzaliaConfig + /// + mPchAzaliaConfig.Pme = PCH_DEVICE_DISABLE; + mPchAzaliaConfig.ResetWaitTimer = 300; + mPchAzaliaConfig.DS = 1; + mPchAzaliaConfig.DA = 0; + + /// + /// Reserved SMBus Address + /// + mPchSmbusConfig.NumRsvdSmbusAddresses = 4; + mPchSmbusConfig.RsvdSmbusAddressTable = mSmbusRsvdAddresses; + + /// + /// MiscPm Configuration + /// + mPchMiscPmConfig.PchDeepSxPol = PchDeepSxPolDisable; + mPchMiscPmConfig.WakeConfig.PmeB0S5Dis = PCH_DEVICE_DISABLE; + mPchMiscPmConfig.WakeConfig.WolEnableOverride = PCH_DEVICE_DISABLE; + mPchMiscPmConfig.WakeConfig.Gp27WakeFromDeepSx = PCH_DEVICE_ENABLE; + mPchMiscPmConfig.WakeConfig.PcieWakeFromDeepSx = PCH_DEVICE_DISABLE; + mPchMiscPmConfig.PowerResetStatusClear.MeWakeSts = PCH_DEVICE_ENABLE; + mPchMiscPmConfig.PowerResetStatusClear.MeHrstColdSts = PCH_DEVICE_ENABLE; + mPchMiscPmConfig.PowerResetStatusClear.MeHrstWarmSts = PCH_DEVICE_ENABLE; + + mPchMiscPmConfig.PchSlpS3MinAssert = PchSlpS350ms; + mPchMiscPmConfig.PchSlpS4MinAssert = PchSlpS44s; + mPchMiscPmConfig.PchSlpSusMinAssert = PchSlpSus4s; + mPchMiscPmConfig.PchSlpAMinAssert = PchSlpA2s; + mPchMiscPmConfig.PchPwrCycDur = 4; // 4-5 seconds (PCH default setting) + mPchMiscPmConfig.SlpStrchSusUp = PCH_DEVICE_DISABLE; + mPchMiscPmConfig.SlpLanLowDc = PCH_DEVICE_DISABLE; + + /// + /// Io Apic configuration + /// + mPchIoApicConfig.BdfValid = 1; + mPchIoApicConfig.BusNumber = 0xF0; + mPchIoApicConfig.DeviceNumber = 0x1F; + mPchIoApicConfig.FunctionNumber = 0x00; + mPchIoApicConfig.IoApicEntry24_39 = PCH_DEVICE_ENABLE; + + /// + /// Default Svid Sdid configuration + /// + mPchDefaultSvidSid.SubSystemVendorId = V_PCH_INTEL_VENDOR_ID; + mPchDefaultSvidSid.SubSystemId = V_PCH_DEFAULT_SID; + + /// + /// Thermal configuration - Initialize policy to default values when variable isn't found. + /// + mPchThermalConfig.ThermalAlertEnable.TselLock = PCH_DEVICE_ENABLE; + mPchThermalConfig.ThermalAlertEnable.TscLock = PCH_DEVICE_ENABLE; + mPchThermalConfig.ThermalAlertEnable.TsmicLock = PCH_DEVICE_ENABLE; + mPchThermalConfig.ThermalAlertEnable.PhlcLock = PCH_DEVICE_ENABLE; + mPchThermalConfig.ThermalThrottling.TTLevels.SuggestedSetting = PCH_DEVICE_ENABLE; + mPchThermalConfig.ThermalThrottling.TTLevels.PchCrossThrottling = PCH_DEVICE_ENABLE; + mPchThermalConfig.ThermalThrottling.DmiHaAWC.SuggestedSetting = PCH_DEVICE_ENABLE; + mPchThermalConfig.ThermalThrottling.SataTT.SuggestedSetting = PCH_DEVICE_ENABLE; + mPchThermalConfig.ThermalDeviceEnable = PCH_DEVICE_DISABLE; + /// + /// The value in this field is valid only if it is between 00h and 17Fh. + /// 0x17F is the hottest temperature and 0x000 is the lowest temperature + /// + mPchThermalConfig.PchHotLevel = 0x000; + + /// + /// HEPT Configuration + /// + mPchHpetConfig.BdfValid = 1; + for (Index = 0; Index < PCH_HPET_BDF_MAX; Index++) { + mPchHpetConfig.Hpet[Index].BusNumber = 0xF0; + mPchHpetConfig.Hpet[Index].DeviceNumber = 0x0F; + mPchHpetConfig.Hpet[Index].FunctionNumber = 0x00; + } + /// + /// Initialize Serial IRQ Config + /// + mSerialIrqConfig.SirqEnable = TRUE; + mSerialIrqConfig.StartFramePulse = PchSfpw4Clk; + mSerialIrqConfig.SirqMode = PchContinuousMode; + + /// + /// DMI related settings + /// + mPchDmiConfig.DmiAspm = PCH_DEVICE_ENABLE; + mPchDmiConfig.DmiExtSync = PCH_DEVICE_DISABLE; + mPchDmiConfig.DmiIot = PCH_DEVICE_DISABLE; + + /// + /// Power Optimizer related settings + /// + mPchPwrOptConfig.PchPwrOptDmi = PCH_DEVICE_ENABLE; + mPchPwrOptConfig.PchPwrOptGbe = PCH_DEVICE_ENABLE; + mPchPwrOptConfig.PchPwrOptXhci = PCH_DEVICE_DISABLE; + mPchPwrOptConfig.PchPwrOptEhci = PCH_DEVICE_DISABLE; + mPchPwrOptConfig.PchPwrOptSata = PCH_DEVICE_ENABLE; + mPchPwrOptConfig.MemCloseStateEn = PCH_DEVICE_ENABLE; + mPchPwrOptConfig.InternalObffEn = PCH_DEVICE_ENABLE; + mPchPwrOptConfig.ExternalObffEn = PCH_DEVICE_DISABLE; // De-feature OBFF from LPT-H/LPT-LP. + mPchPwrOptConfig.NumOfDevLtrOverride = 0; + mPchPwrOptConfig.DevLtrOverride = NULL; + for (PortIndex = 0; PortIndex < GetPchMaxPciePortNum (); PortIndex++) { + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].LtrEnable = PCH_DEVICE_ENABLE; + // + // De-feature OBFF from LPT-H/LPT-LP. + // Doesn't enable Obff policy anymore. + // + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].ObffEnable = PCH_DEVICE_DISABLE; + } + mPchPwrOptConfig.LegacyDmaDisable = PCH_DEVICE_DISABLE; + for (PortIndex = 0; PortIndex < GetPchMaxPciePortNum (); PortIndex++) { + if (PchSeries == PchLp) { + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].LtrMaxSnoopLatency = 0x1003; + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].LtrMaxNoSnoopLatency = 0x1003; + } + if (PchSeries == PchH) { + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].LtrMaxSnoopLatency = 0x0846; + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].LtrMaxNoSnoopLatency = 0x0846; + } + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].LtrConfigLock = PCH_DEVICE_ENABLE; + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].SnoopLatencyOverrideMode = 2; + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].SnoopLatencyOverrideMultiplier = 2; + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].SnoopLatencyOverrideValue = 60; + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].NonSnoopLatencyOverrideMode = 2; + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].NonSnoopLatencyOverrideMultiplier = 2; + mPchPwrOptConfig.PchPwrOptPcie[PortIndex].NonSnoopLatencyOverrideValue = 60; + } + + /// + /// Misc. Config + /// + /// FviSmbiosType is the SMBIOS OEM type (0x80 to 0xFF) defined in SMBIOS Type 14 - Group + /// Associations structure - item type. FVI structure uses it as SMBIOS OEM type to provide + /// version information. The default value is type 221. + /// + mPchMiscConfig.FviSmbiosType = 0xDD; + + /// + /// DCI (Direct Connect Interface) Configuration + /// + mPchMiscConfig.DciEn = PCH_DEVICE_DISABLE; + + /// + /// Audio Dsp Configuration + /// + mAudioDspConfig.AudioDspD3PowerGating = PCH_DEVICE_ENABLE; + mAudioDspConfig.AudioDspAcpiMode = 1; //1: ACPI mode, 0: PCI mode + mAudioDspConfig.AudioDspAcpiInterruptMode = 1; //1: ACPI mode, 0: PCI mode + mAudioDspConfig.AudioDspBluetoothSupport = PCH_DEVICE_DISABLE; // Bluetooth SCO disabled + + /// + /// Serial IO Configuration + /// + mSerialIoConfig.SerialIoMode = PchSerialIoIsAcpi; + switch(PchStepping()) { + default: + mSerialIoConfig.SerialIoInterruptMode = PchSerialIoIsAcpi; + break; + } + mSerialIoConfig.Ddr50Support = PCH_DEVICE_DISABLE; + + mSerialIoConfig.I2c0VoltageSelect = PchSerialIoIs18V; + mSerialIoConfig.I2c1VoltageSelect = PchSerialIoIs33V; + + + /// + /// Update policy by platform setting + /// + UpdateDxePchPlatformPolicy (&mPchPolicyData); + +#ifdef USB_PRECONDITION_ENABLE_FLAG + /// + /// Update Precondition option for S4 resume. + /// Skip Precondition for S4 resume in case this boot may not connect BIOS USB driver. + /// If BIOS USB driver will be connected always for S4, then disable below update. + /// To keep consistency during boot, must enabled or disabled below function in both PEI and DXE + /// PlatformPolicyInit driver. + /// + if (mPchUsbConfig.UsbPrecondition == TRUE) { + if (GetBootModeHob () == BOOT_ON_S4_RESUME) { + mPchUsbConfig.UsbPrecondition = FALSE; + DEBUG ((EFI_D_INFO, "BootMode is BOOT_ON_S4_RESUME, disable Precondition\n")); + } + } +#endif // USB_PRECONDITION_ENABLE_FLAG + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gDxePchPlatformPolicyProtocolGuid, + &mPchPolicyData, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; + +} diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.dxs b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.dxs new file mode 100644 index 0000000..0140fb2 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.dxs @@ -0,0 +1,44 @@ +/** @file + Dependency expression source file. + +@copyright + Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ + + +// +// Common for R8 and R9 codebase +// +#include "AutoGen.h" +#include "PeimDepex.h" + +// +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase; +// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase. +// +#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB) +#include "EfiDepex.h" +#endif +#include EFI_ARCH_PROTOCOL_DEFINITION (Variable) +#include EFI_PROTOCOL_DEFINITION (PlatformInfo) +#include EFI_PROTOCOL_DEFINITION (CpuIo) + +DEPENDENCY_START + EFI_VARIABLE_ARCH_PROTOCOL_GUID AND + PLATFORM_INFO_PROTOCOL_GUID AND + EFI_CPU_IO_PROTOCOL_GUID +DEPENDENCY_END
\ No newline at end of file diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.h b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.h new file mode 100644 index 0000000..ae0cbae --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.h @@ -0,0 +1,56 @@ +/** @file + Header file for the PchPolicyInitDxe Driver. + +@copyright + Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _PCH_PLATFORM_POLICY_DXE_H_ +#define _PCH_PLATFORM_POLICY_DXE_H_ + +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGlueDxe.h" +#include EFI_PROTOCOL_PRODUCER (PchPlatformPolicy) +#include "PchAccess.h" +#include "PchPlatformPolicyUpdateDxeLib.h" +#include "PchPlatformLib.h" +#endif + +// +// Functions +// + +/** + Initilize Intel PCH DXE Platform Policy + + @param[in] ImageHandle Image handle of this driver. + @param[in, out] SystemTable Global system service table. + + @retval EFI_SUCCESS Initialization complete. + @exception EFI_UNSUPPORTED The chipset is unsupported by this driver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +PchPolicyInitDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN OUT EFI_SYSTEM_TABLE *SystemTable + ); + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.inf b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.inf new file mode 100644 index 0000000..3b883ab --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Dxe/PchPolicyInitDxe.inf @@ -0,0 +1,82 @@ +## @file +# Component description file for the PchPolicyInitDxe DXE driver. +# +#@copyright +# Copyright (c) 2009 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +[defines] +BASE_NAME = PchPolicyInitDxe +FILE_GUID = 3BC42C6D-ABEC-41ba-8CCB-D8E0EF1CEF85 +COMPONENT_TYPE = BS_DRIVER + +[sources.common] + PchPolicyInitDxe.h + PchPolicyInitDxe.c + ../Common/PchPolicyInitCommon.c + ../Common/PchPolicyInitCommon.h +# +# Edk II Glue Driver Entry Point +# + EdkIIGlueDxeDriverEntryPoint.c + +[includes.common] + . + $(EFI_SOURCE) + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Framework/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Pcd + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include/Library + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Cpu/Pentium/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT) + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include/Library + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Protocol/PchPlatformPolicy + $(PLATFORM_ECP_PACKAGE)/Include + +[libraries.common] + EdkIIGlueDxeReportStatusCodeLib + EdkIIGlueDxeDebugLibReportStatusCode + EdkFrameworkProtocolLib + EdkIIGlueDxeHobLib + EdkProtocolLib + $(PROJECT_PCH_FAMILY)ProtocolLib + EdkIIGlueUefiBootServicesTableLib + EdkIIGlueUefiRuntimeServicesTableLib + PlatformPolicyUpdateDxeLib + EdkIIGlueDxeServicesTableLib + PchPlatformLib + +[nmake.common] + IMAGE_ENTRY_POINT = _ModuleEntryPoint + DPX_SOURCE = PchPolicyInitDxe.dxs +# +# Module Entry Point +# + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=PchPolicyInitDxeEntryPoint + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_DXE_REPORT_STATUS_CODE_LIB__ \ + -D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \ + -D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \ + -D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \ + -D __EDKII_GLUE_DXE_SERVICES_TABLE_LIB__ \ + -D __EDKII_GLUE_DXE_HOB_LIB__ diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.c b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.c new file mode 100644 index 0000000..08e0cf7 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.c @@ -0,0 +1,250 @@ +/** @file + This file is SampleCode for Intel PCH PEI Platform Policy initialzation. + +@copyright + Copyright (c) 2009 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ +#include "PchPolicyInitPei.h" +#include "..\Common\PchPolicyInitCommon.h" +#ifdef RAPID_START_FLAG +#include "RapidStartCommonLib.h" +#endif + +/** + This PEIM performs PCH PEI Platform Policy initialzation. + + @param[in] FfsHeader Pointer to Firmware File System file header. + @param[in] PeiServices General purpose services available to every PEIM. + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver +**/ +EFI_STATUS +EFIAPI +PchPolicyInitPeiEntryPoint ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *PchPlatformPolicyPpiDesc; + PCH_PLATFORM_POLICY_PPI *PchPlatformPolicyPpi; + PCH_GBE_CONFIG *GbeConfig; + PCH_THERMAL_MANAGEMENT *ThermalMgmt; + PCH_MEMORY_THROTTLING *MemoryThrottling; + PCH_HPET_CONFIG *HpetConfig; + PCH_SATA_CONTROL *SataConfig; + PCH_SATA_TRACE_CONFIG *SataTraceConfig; + PCH_PCIE_CONFIG *PcieConfig; + PCH_IOAPIC_CONFIG *IoApicConfig; + PCH_PLATFORM_DATA *PlatformData; + PCH_USB_CONFIG *UsbConfig; +#ifdef USB_PRECONDITION_ENABLE_FLAG + EFI_BOOT_MODE BootMode; +#endif // USB_PRECONDITION_ENABLE_FLAG + UINT8 PortIndex; + + PchPlatformPolicyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR)); + ASSERT (PchPlatformPolicyPpiDesc != NULL); + if (PchPlatformPolicyPpiDesc == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + PchPlatformPolicyPpi = (PCH_PLATFORM_POLICY_PPI *) AllocateZeroPool (sizeof (PCH_PLATFORM_POLICY_PPI)); + ASSERT (PchPlatformPolicyPpi != NULL); + if (PchPlatformPolicyPpi == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + GbeConfig = (PCH_GBE_CONFIG *) AllocateZeroPool (sizeof (PCH_GBE_CONFIG)); + ASSERT (GbeConfig != NULL); + if (GbeConfig == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + ThermalMgmt = (PCH_THERMAL_MANAGEMENT *) AllocateZeroPool (sizeof (PCH_THERMAL_MANAGEMENT)); + ASSERT (ThermalMgmt != NULL); + if (ThermalMgmt == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + MemoryThrottling = (PCH_MEMORY_THROTTLING *) AllocateZeroPool (sizeof (PCH_MEMORY_THROTTLING)); + ASSERT (MemoryThrottling != NULL); + if (MemoryThrottling == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + HpetConfig = (PCH_HPET_CONFIG *) AllocateZeroPool (sizeof (PCH_HPET_CONFIG)); + ASSERT (HpetConfig != NULL); + if (HpetConfig == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + SataConfig = (PCH_SATA_CONTROL *) AllocateZeroPool (sizeof (PCH_SATA_CONTROL)); + ASSERT (SataConfig != NULL); + if (SataConfig == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + SataTraceConfig = (PCH_SATA_TRACE_CONFIG *) AllocateZeroPool (sizeof (PCH_SATA_TRACE_CONFIG)); + ASSERT (SataTraceConfig != NULL); + if (SataTraceConfig == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + PcieConfig = (PCH_PCIE_CONFIG *) AllocateZeroPool (sizeof (PCH_PCIE_CONFIG)); + ASSERT (PcieConfig != NULL); + if (PcieConfig == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + IoApicConfig = (PCH_IOAPIC_CONFIG *) AllocateZeroPool (sizeof (PCH_IOAPIC_CONFIG)); + ASSERT (IoApicConfig != NULL); + if (IoApicConfig == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + PlatformData = (PCH_PLATFORM_DATA *) AllocateZeroPool (sizeof (PCH_PLATFORM_DATA)); + ASSERT (PlatformData != NULL); + if (PlatformData == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + UsbConfig = (PCH_USB_CONFIG *) AllocateZeroPool (sizeof (PCH_USB_CONFIG)); + ASSERT (UsbConfig != NULL); + if (UsbConfig == NULL) { + return EFI_OUT_OF_RESOURCES; + } + PchPlatformPolicyPpi->Revision = PCH_PLATFORM_POLICY_PPI_REVISION_4; + PchPlatformPolicyPpi->BusNumber = 0; + PchPlatformPolicyPpi->Rcba = PCH_LPC_RCBA_BASE_ADDRESS; + PchPlatformPolicyPpi->PmBase = PCH_LPC_ACPI_BASE_ADDRESS; + PchPlatformPolicyPpi->GpioBase = PCH_LPC_GPIO_BASE_ADDRESS; + PchPlatformPolicyPpi->Port80Route = 0; + + PchPlatformPolicyPpi->GbeConfig = GbeConfig; + PchPlatformPolicyPpi->ThermalMgmt = ThermalMgmt; + PchPlatformPolicyPpi->HpetConfig = HpetConfig; + PchPlatformPolicyPpi->SataConfig = SataConfig; + PchPlatformPolicyPpi->PcieConfig = PcieConfig; + PchPlatformPolicyPpi->IoApicConfig = IoApicConfig; + PchPlatformPolicyPpi->PlatformData = PlatformData; + PchPlatformPolicyPpi->UsbConfig = UsbConfig; + + GbeConfig->EnableGbe = 1; + ThermalMgmt->MemoryThrottling = MemoryThrottling; + MemoryThrottling->Enable = PCH_DEVICE_DISABLE; + MemoryThrottling->TsGpioPinSetting[TsGpioC].PmsyncEnable = PCH_DEVICE_ENABLE; + MemoryThrottling->TsGpioPinSetting[TsGpioD].PmsyncEnable = PCH_DEVICE_ENABLE; + MemoryThrottling->TsGpioPinSetting[TsGpioC].C0TransmitEnable = PCH_DEVICE_ENABLE; + MemoryThrottling->TsGpioPinSetting[TsGpioD].C0TransmitEnable = PCH_DEVICE_ENABLE; + MemoryThrottling->TsGpioPinSetting[TsGpioC].PinSelection = 1; + MemoryThrottling->TsGpioPinSetting[TsGpioD].PinSelection = 0; + + HpetConfig->Enable = 1; + HpetConfig->Base = PCH_HPET_BASE_ADDRESS; + + SataConfig->SataMode = PchSataModeAhci; + SataConfig->SataTraceConfig = SataTraceConfig; + + SataTraceConfig->TestMode = PCH_DEVICE_DISABLE; + for( PortIndex = 0; PortIndex < 6; PortIndex++ ) { + SataTraceConfig->PortRxEq[PortIndex].GenSpeed[0].Enable = PCH_DEVICE_DISABLE; + SataTraceConfig->PortRxEq[PortIndex].GenSpeed[1].Enable = PCH_DEVICE_DISABLE; + SataTraceConfig->PortRxEq[PortIndex].GenSpeed[2].Enable = PCH_DEVICE_DISABLE; + SataTraceConfig->PortRxEq[PortIndex].GenSpeed[0].RxEq = 0x0; + SataTraceConfig->PortRxEq[PortIndex].GenSpeed[1].RxEq = 0x0; + SataTraceConfig->PortRxEq[PortIndex].GenSpeed[2].RxEq = 0x0; + } + + PcieConfig->PcieSpeed[0] = PchPcieAuto; + PcieConfig->PcieSpeed[1] = PchPcieAuto; + PcieConfig->PcieSpeed[2] = PchPcieAuto; + PcieConfig->PcieSpeed[3] = PchPcieAuto; + PcieConfig->PcieSpeed[4] = PchPcieAuto; + PcieConfig->PcieSpeed[5] = PchPcieAuto; + PcieConfig->PcieSpeed[6] = PchPcieAuto; + PcieConfig->PcieSpeed[7] = PchPcieAuto; + + IoApicConfig->IoApicId = 0x02; + IoApicConfig->ApicRangeSelect = 0x00; + IoApicConfig->IoApicEntry24_39 = PCH_DEVICE_ENABLE; + + PlatformData->EcPresent = 0; + /// + /// PlatformData->SmmBwp value directly depends on the value of CpuConfig->Pfat + /// (found in CpuPolicyInitPei.c file) + /// If CpuConfig->Pfat is set to 1 (enabled) then + /// PlatformData->SmmBwp has to be set to 1 (enabled) + /// This is a PFAT Security requirement that needs to be addressed + /// If CpuConfig->Pfat is set to 0 (disabled) then + /// PlatformData->SmmBwp value don't care, it can be set to either + /// 1 (enabled) or 0 (disabled) based on customer implementation + /// + PlatformData->SmmBwp = 0; + + /// + /// Temporary Memory Base Address for PCI devices to be used to initialize MMIO registers. + /// Minimum size is 64KB bytes. + /// + PlatformData->TempMemBaseAddr = PCH_TEMP_MEM_BASE_ADDRESS; + + /// + /// Init USB related setting + /// + InitPchUsbConfig (UsbConfig); + + PchPlatformPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + PchPlatformPolicyPpiDesc->Guid = &gPchPlatformPolicyPpiGuid; + + UpdatePeiPchPlatformPolicy (PeiServices, PchPlatformPolicyPpi); +#ifdef RAPID_START_FLAG + if (RapidStartResumeCheck () == TRUE) { + /// + /// This is RapidStart resume, skip the UsbPrecondition feature in PEI phase + /// + PchPlatformPolicyPpi->UsbConfig->UsbPrecondition = 0; + } +#endif + + + PchPlatformPolicyPpiDesc->Ppi = PchPlatformPolicyPpi; +#ifdef USB_PRECONDITION_ENABLE_FLAG + /// + /// Update Precondition option for S4 resume. + /// Skip Precondition for S4 resume in case this boot may not connect BIOS USB driver. + /// If BIOS USB driver will be connected always for S4, then disable below update. + /// To keep consistency during boot, must enabled or disabled below function in both PEI and DXE + /// PlatformPolicyInit driver. + /// + if (UsbConfig->UsbPrecondition == TRUE) { + (*PeiServices)->GetBootMode (PeiServices, &BootMode); + if (BootMode == BOOT_ON_S4_RESUME) { + UsbConfig->UsbPrecondition = FALSE; + DEBUG ((EFI_D_INFO, "BootMode is BOOT_ON_S4_RESUME, disable Precondition\n")); + } + } +#endif // USB_PRECONDITION_ENABLE_FLAG + + /// + /// Install PCH Platform Policy PPI + /// + Status = (**PeiServices).InstallPpi (PeiServices, PchPlatformPolicyPpiDesc); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.dxs b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.dxs new file mode 100644 index 0000000..806a8d6 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.dxs @@ -0,0 +1,40 @@ +/** @file + Dependency expression source file. + +@copyright + Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ + + +// +// Common for R8 and R9 codebase +// +#include "AutoGen.h" +#include "PeimDepex.h" + +// +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase; +// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase. +// +#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB) +#include "EfiDepex.h" +#include EFI_PPI_DEPENDENCY (Variable) +#endif + +DEPENDENCY_START + PEI_READ_ONLY_VARIABLE_ACCESS_PPI_GUID +DEPENDENCY_END diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.h b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.h new file mode 100644 index 0000000..3d155b3 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.h @@ -0,0 +1,60 @@ +/** @file + Header file for the PchPeiPolicy PEIM. + +@copyright + Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef _PCH_POLICY_INIT_PEI_H_ +#define _PCH_POLICY_INIT_PEI_H_ + +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGluePeim.h" +#include EFI_PPI_PRODUCER (PchPlatformPolicy) +#include "PchAccess.h" +#include "PchPlatformPolicyUpdatePeiLib.h" +#endif + +#define PCH_LPC_RCBA_BASE_ADDRESS 0xFED1C000 +#define PCH_LPC_ACPI_BASE_ADDRESS 0x1800 +#define PCH_LPC_GPIO_BASE_ADDRESS 0x800 + +#define PCH_TEMP_MEM_BASE_ADDRESS 0xDFFF0000 +#define PCH_HPET_BASE_ADDRESS 0xFED00000 + +// +// Functions +// + +/** + This PEIM performs PCH PEI Platform Policy initialzation. + + @param[in] FfsHeader Pointer to Firmware File System file header. + @param[in] PeiServices General purpose services available to every PEIM. + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver +**/ +EFI_STATUS +EFIAPI +PchPolicyInitPeiEntryPoint ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices + ); +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.inf b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.inf new file mode 100644 index 0000000..37ab29d --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchPolicyInit/Pei/PchPolicyInitPei.inf @@ -0,0 +1,87 @@ +## @file +# Component description file for the PchPolicyInitPei PEIM. +# +#@copyright +# Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +[defines] +BASE_NAME = PchPolicyInitPei +FILE_GUID = 20596BCC-EF0D-4772-AB71-C5102620A013 +COMPONENT_TYPE = PE32_PEIM + +[sources.common] + PchPolicyInitPei.h + PchPolicyInitPei.c + ../Common/PchPolicyInitCommon.c + ../Common/PchPolicyInitCommon.h +# +# Edk II Glue Driver Entry Point +# + EdkIIGluePeimEntryPoint.c + +[includes.common] + . + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT) + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include/Library + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Ppi/PchPlatformPolicy + $(EFI_SOURCE)/$(PROJECT_RAPID_START_ROOT) + $(EFI_SOURCE)/$(PROJECT_RAPID_START_ROOT)/Include + $(EFI_SOURCE)/$(PROJECT_RAPID_START_ROOT)/Samplecode/Library/RapidStartCommonLib +# +# EDK II Glue Library utilizes some standard headers from EDK +# + $(EFI_SOURCE) + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Pei/Include + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + $(PLATFORM_ECP_PACKAGE)/Include + +[libraries.common] + $(PROJECT_PCH_FAMILY)PpiLib + EdkFrameworkPpiLib + EdkIIGlueBaseIoLibIntrinsic + EdkIIGlueBaseMemoryLib + EdkIIGluePeiDebugLibReportStatusCode + EdkIIGluePeiReportStatusCodeLib + EdkIIGluePeiServicesLib + EdkIIGluePeiMemoryAllocationLib + EdkPpiLib + PlatformPolicyUpdatePeiLib + RapidStartCommonLib + +[nmake.common] + IMAGE_ENTRY_POINT = _ModuleEntryPoint + DPX_SOURCE = PchPolicyInitPei.dxs +# +# Module Entry Point +# + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=PchPolicyInitPeiEntryPoint + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \ + -D __EDKII_GLUE_BASE_MEMORY_LIB__ \ + -D __EDKII_GLUE_PEI_DEBUG_LIB_REPORT_STATUS_CODE__ \ + -D __EDKII_GLUE_PEI_REPORT_STATUS_CODE_LIB__ \ + -D __EDKII_GLUE_PEI_SERVICES_LIB__ \ + -D __EDKII_GLUE_PEI_MEMORY_ALLOCATION_LIB__ diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/PchSampleCode.cif b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchSampleCode.cif new file mode 100644 index 0000000..f3282bf --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/PchSampleCode.cif @@ -0,0 +1,34 @@ +<component> + name = "PchSampleCode" + category = ModulePart + LocalRoot = "ReferenceCode\Chipset\LynxPoint\SampleCode\" + RefName = "PchSampleCode" +[files] +"Ppi\SmbusPolicy\SmbusPolicy.h" +"Ppi\UsbController\UsbController.h" +"Guid\SmbusArpMap\SmbusArpMap.h" +"Protocol\SmmSmbus\SmmSmbus.h" +"PchPolicyInit\Pei\PchPolicyInitPei.dxs" +"PchPolicyInit\Pei\PchPolicyInitPei.c" +"PchPolicyInit\Pei\PchPolicyInitPei.h" +"PchPolicyInit\Pei\PchPolicyInitPei.inf" +"PchPolicyInit\Dxe\PchPolicyInitDxe.dxs" +"PchPolicyInit\Dxe\PchPolicyInitDxe.c" +"PchPolicyInit\Dxe\PchPolicyInitDxe.h" +"PchPolicyInit\Dxe\PchPolicyInitDxe.inf" +"BiosWriteProtect\Smm\PchBiosWriteProtect.c" +"BiosWriteProtect\Smm\PchBiosWriteProtect.dxs" +"BiosWriteProtect\Smm\PchBiosWriteProtect.h" +"BiosWriteProtect\Smm\PchBiosWriteProtect.inf" +"Include\Acpi3_0.h" +"Include\PchAslUpdateLib.h" +"PchPolicyInit\Common\PchPolicyInitCommon.c" +"PchPolicyInit\Common\PchPolicyInitCommon.h" +"AcpiTables\Dsdt\SerialIoDevices.asl" +"AcpiTables\Dsdt\Sensor.asl" +"Ppi\IntelPchSampleCodePpiLib.inf" +"Ppi\SmmAccess\SmmAccess.c" +"Ppi\SmmAccess\SmmAccess.h" +[parts] +"PchAslUpdateLib" +<endComponent> diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/Ppi/IntelPchSampleCodePpiLib.inf b/ReferenceCode/Chipset/LynxPoint/SampleCode/Ppi/IntelPchSampleCodePpiLib.inf new file mode 100644 index 0000000..b72ede5 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/Ppi/IntelPchSampleCodePpiLib.inf @@ -0,0 +1,45 @@ +## @file +# Component description file for the PEI protocol library +# +#@copyright +# Copyright (c) 2015 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + + +[defines] +BASE_NAME = IntelPchSampleCodePpiLib +COMPONENT_TYPE = LIBRARY + +[sources.common] + SmmAccess/SmmAccess.h + SmmAccess/SmmAccess.c + +[includes.common] + $(EFI_SOURCE) + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Framework/Include + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Pei/Include + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT) + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/SampleCode + +[nmake.common] +C_STD_INCLUDE= diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/Ppi/SmbusPolicy/SmbusPolicy.h b/ReferenceCode/Chipset/LynxPoint/SampleCode/Ppi/SmbusPolicy/SmbusPolicy.h new file mode 100644 index 0000000..b43803b --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/Ppi/SmbusPolicy/SmbusPolicy.h @@ -0,0 +1,38 @@ +/** @file + Smbus Policy PPI as defined in EFI 2.0 + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains 'Framework Code' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may not be modified, except as allowed by + additional terms of your license agreement. +**/ +#ifndef _PEI_SMBUS_POLICY_PPI_H +#define _PEI_SMBUS_POLICY_PPI_H + +#define PEI_SMBUS_POLICY_PPI_GUID \ + { \ + 0x63b6e435, 0x32bc, 0x49c6, 0x81, 0xbd, 0xb7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c \ + } + +EFI_FORWARD_DECLARATION (PEI_SMBUS_POLICY_PPI); + +struct _PEI_SMBUS_POLICY_PPI { + UINTN BaseAddress; + UINT32 PciAddress; + UINT8 NumRsvdAddress; + UINT8 *RsvdAddress; +}; + +extern EFI_GUID gPeiSmbusPolicyPpiGuid; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/Ppi/SmmAccess/SmmAccess.c b/ReferenceCode/Chipset/LynxPoint/SampleCode/Ppi/SmmAccess/SmmAccess.c new file mode 100644 index 0000000..85ab194 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/Ppi/SmmAccess/SmmAccess.c @@ -0,0 +1,25 @@ +/** @file + SmmAccess PPI GUID + +@copyright + Copyright (c) 2015 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains 'Framework Code' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may not be modified, except as allowed by + additional terms of your license agreement. +**/ +#include "Tiano.h" +#include "Pei.h" +#include EFI_PPI_DEFINITION (SmmAccess) + +EFI_GUID gPeiSmmAccessPpiGuid = PEI_SMM_ACCESS_PPI_GUID; + +EFI_GUID_STRING(&gPeiSmmAccessPpiGuid, "SmmAccess", "SMM Access PPI"); diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/Ppi/SmmAccess/SmmAccess.h b/ReferenceCode/Chipset/LynxPoint/SampleCode/Ppi/SmmAccess/SmmAccess.h new file mode 100644 index 0000000..4873b1a --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/Ppi/SmmAccess/SmmAccess.h @@ -0,0 +1,136 @@ +/** @file + This code abstracts the PEI core to provide SmmAccess services. + +@copyright + Copyright (c) 2015 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains 'Framework Code' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may not be modified, except as allowed by + additional terms of your license agreement. +**/ +#ifndef _PEI_SMM_ACCESS_PPI_H_ +#define _PEI_SMM_ACCESS_PPI_H_ + +#include EFI_GUID_DEFINITION (SmramMemoryReserve) + +#define PEI_SMM_ACCESS_PPI_GUID \ + { \ + 0x268f33a9, 0xcccd, 0x48be, 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 \ + } + +EFI_FORWARD_DECLARATION (PEI_SMM_ACCESS_PPI); + +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_OPEN) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_ACCESS_PPI * This, + IN UINTN DescriptorIndex + ) +/** + This routine accepts a request to "open" a region of SMRAM. The + region could be legacy ABSEG, HSEG, or TSEG near top of physical memory. + The use of "open" means that the memory is visible from all PEIM + and SMM agents. + + @param[in] This - Pointer to the SMM Access Interface. + @param[in] DescriptorIndex - Region of SMRAM to Open. + + @retval EFI_SUCCESS - The region was successfully opened. + @retval EFI_DEVICE_ERROR - The region could not be opened because locked by + chipset. + @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds. +**/ +; + +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_CLOSE) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_ACCESS_PPI * This, + IN UINTN DescriptorIndex + ) +/** + This routine accepts a request to "close" a region of SMRAM. The + region could be legacy AB or TSEG near top of physical memory. + The use of "close" means that the memory is only visible from SMM agents, + not from PEIM. + + @param[in] This - Pointer to the SMM Access Interface. + @param[in] DescriptorIndex - Region of SMRAM to Close. + + @retval EFI_SUCCESS - The region was successfully closed. + @retval EFI_DEVICE_ERROR - The region could not be closed because locked by + chipset. + @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds. +**/ +; + +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_LOCK) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_ACCESS_PPI * This, + IN UINTN DescriptorIndex + ) +/** + This routine accepts a request to "lock" SMRAM. The + region could be legacy AB or TSEG near top of physical memory. + The use of "lock" means that the memory can no longer be opened + to PEIM. + + @param[in] This - Pointer to the SMM Access Interface. + @param[in] DescriptorIndex - Region of SMRAM to Lock. + + @retval EFI_SUCCESS - The region was successfully locked. + @retval EFI_DEVICE_ERROR - The region could not be locked because at least + one range is still open. + @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds. +**/ +; + +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_CAPABILITIES) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_ACCESS_PPI * This, + IN OUT UINTN *SmramMapSize, + IN OUT EFI_SMRAM_DESCRIPTOR * SmramMap + ) +/** + This routine services a user request to discover the SMRAM + capabilities of this platform. This will report the possible + ranges that are possible for SMRAM access, based upon the + memory controller capabilities. + + @param[in] This - Pointer to the SMRAM Access Interface. + @param[in] SmramMapSize - Pointer to the variable containing size of the + buffer to contain the description information. + @param[in] SmramMap - Buffer containing the data describing the Smram + region descriptors. + + @retval EFI_BUFFER_TOO_SMALL - The user did not provide a sufficient buffer. + @retval EFI_SUCCESS - The user provided a sufficiently-sized buffer. +**/ +; + +struct _PEI_SMM_ACCESS_PPI { + PEI_SMM_OPEN Open; + PEI_SMM_CLOSE Close; + PEI_SMM_LOCK Lock; + PEI_SMM_CAPABILITIES GetCapabilities; + BOOLEAN LockState; + BOOLEAN OpenState; +}; + +extern EFI_GUID gPeiSmmAccessPpiGuid; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/Ppi/UsbController/UsbController.h b/ReferenceCode/Chipset/LynxPoint/SampleCode/Ppi/UsbController/UsbController.h new file mode 100644 index 0000000..2fec82f --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/Ppi/UsbController/UsbController.h @@ -0,0 +1,49 @@ +/** @file + Usb Controller PPI as defined in EFI 2.0 + + This code abstracts the PEI core to provide Usb Controller Info from Chipset. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains 'Framework Code' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may not be modified, except as allowed by + additional terms of your license agreement. +**/ +#ifndef _PEI_USB_CONTROLLER_PPI_H_ +#define _PEI_USB_CONTROLLER_PPI_H_ + +#define PEI_USB_CONTROLLER_PPI_GUID \ + { \ + 0x3bc1f6de, 0x693e, 0x4547, 0xa3, 0x0, 0x21, 0x82, 0x3c, 0xa4, 0x20, 0xb2 \ + } + +#define PEI_EHCI_CONTROLLER 0x03 + +EFI_FORWARD_DECLARATION (PEI_USB_CONTROLLER_PPI); + +typedef +EFI_STATUS +(EFIAPI *PEI_GET_USB_CONTROLLER) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_USB_CONTROLLER_PPI *This, + IN UINT8 UsbControllerId, + OUT UINTN *ControllerType, + OUT UINTN *BaseAddress + ); + +struct _PEI_USB_CONTROLLER_PPI { + PEI_GET_USB_CONTROLLER GetUsbController; +}; + +extern EFI_GUID gPeiUsbControllerPpiGuid; + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/SampleCode/Protocol/SmmSmbus/SmmSmbus.h b/ReferenceCode/Chipset/LynxPoint/SampleCode/Protocol/SmmSmbus/SmmSmbus.h new file mode 100644 index 0000000..8b792ac --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SampleCode/Protocol/SmmSmbus/SmmSmbus.h @@ -0,0 +1,50 @@ +/** @file + SmmSmbus Protocol + +@copyright + Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement +**/ +#ifndef __EFI_SMM_SMBUS_PROTOCOL_H__ +#define __EFI_SMM_SMBUS_PROTOCOL_H__ + +/// +/// GUID for the SmmSmbus Protocol +/// +/// EDK and EDKII have different GUID formats +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) + +#define EFI_SMM_SMBUS_PROTOCOL_GUID \ + { \ + 0x72e40094, 0x2ee1, 0x497a, 0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0xc \ + } +#else +#define EFI_SMM_SMBUS_PROTOCOL_GUID \ + { \ + 0x72e40094, 0x2ee1, 0x497a, \ + { \ + 0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0xc \ + } \ + } + +#endif +// +// Resuse the DXE definition, and use another GUID. +// +typedef EFI_SMBUS_HC_PROTOCOL SMM_SMBUS_HC_PROTOCOL; + +extern EFI_GUID gEfiSmmSmbusProtocolGuid; + +#endif |