diff options
Diffstat (limited to 'ReferenceCode/Chipset/LynxPoint/SmmControl')
14 files changed, 1566 insertions, 0 deletions
diff --git a/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/PeiSmmControl.cif b/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/PeiSmmControl.cif new file mode 100644 index 0000000..4d83025 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/PeiSmmControl.cif @@ -0,0 +1,13 @@ +<component> + name = "PeiSmmControl" + category = ModulePart + LocalRoot = "ReferenceCode\Chipset\LynxPoint\SmmControl\Pei\" + RefName = "PeiSmmControl" +[files] +"PeiSmmControl.sdl" +"PeiSmmControl.mak" +"SmmControl.dxs" +"SmmControl.inf" +"SmmControlDriver.c" +"SmmControlDriver.h" +<endComponent> diff --git a/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/PeiSmmControl.mak b/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/PeiSmmControl.mak new file mode 100644 index 0000000..5199538 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/PeiSmmControl.mak @@ -0,0 +1,93 @@ +#********************************************************************** +#********************************************************************** +#** ** +#** (C)Copyright 1985-2010, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#********************************************************************** +#********************************************************************** + +#********************************************************************** +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/PeiSmmControl/PeiSmmControl.mak 1 9/26/12 3:34a Victortu $ +# +# $Revision: 1 $ +# +# $Date: 9/26/12 3:34a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/PeiSmmControl/PeiSmmControl.mak $ +# +# 1 9/26/12 3:34a Victortu +# Lynx Point PCH Chipset Framework Reference Code Beta 0.7.0 +# +# 6 1/13/10 2:13p Felixp +# +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: PeiSmmControl.mak +# +# Description: +# +#<AMI_FHDR_END> +#********************************************************************** +EDK : PeiSmmControl + +PeiSmmControl : $(BUILD_DIR)\PeiSmmControl.mak PeiSmmControlBin + +$(BUILD_DIR)\PeiSmmControl.mak : $(PeiSmmControl_DIR)\$(@B).cif $(PeiSmmControl_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(PeiSmmControl_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +PeiSmmControl_INCLUDES=\ + $(EDK_INCLUDES)\ + $(EdkIIGlueLib_INCLUDES)\ + $(INTEL_PCH_INCLUDES)\ + +PeiSmmControl_DEFINES = $(MY_DEFINES)\ + /D"__EDKII_GLUE_MODULE_ENTRY_POINT__=SmmControlPeiDriverEntryInit"\ + /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \ + /D __EDKII_GLUE_BASE_MEMORY_LIB__ \ + /D __EDKII_GLUE_PEI_REPORT_STATUS_CODE_LIB__ \ + /D __EDKII_GLUE_PEI_DEBUG_LIB_REPORT_STATUS_CODE__ \ + /D __EDKII_GLUE_PEI_SERVICES_LIB__ \ + /D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ + +PeiSmmControl_LIB_LINKS =\ + $(EdkIIGlueBaseIoLibIntrinsic_LIB)\ + $(EdkIIGlueBaseMemoryLib_LIB)\ + $(EdkIIGluePeiDebugLibReportStatusCode_LIB)\ + $(EdkIIGluePeiReportStatusCodeLib_LIB)\ + $(EdkIIGluePeiServicesLib_LIB)\ + $(EdkIIGlueBasePciLibPciExpress_LIB)\ + +PeiSmmControlBin : $(PeiSmmControl_LIB_LINKS) + $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\ + /f $(BUILD_DIR)\PeiSmmControl.mak all\ + "MY_INCLUDES=$(PeiSmmControl_INCLUDES)" \ + "MY_DEFINES=$(PeiSmmControl_DEFINES)" \ + GUID=FF456B9C-0DC7-4682-9E92-0DE84B6E4067\ + ENTRY_POINT=_ModuleEntryPoint \ + TYPE=PEIM \ + EDKIIModule=PEIM\ + DEPEX1=$(PeiSmmControl_DIR)\SmmControl.dxs\ + DEPEX1_TYPE=EFI_SECTION_PEI_DEPEX\ + COMPRESS=0 +#********************************************************************** +#********************************************************************** +#** ** +#** (C)Copyright 1985-2010, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#********************************************************************** +#**********************************************************************
\ No newline at end of file diff --git a/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/PeiSmmControl.sdl b/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/PeiSmmControl.sdl new file mode 100644 index 0000000..8470880 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/PeiSmmControl.sdl @@ -0,0 +1,24 @@ +TOKEN + Name = PeiSmmControl_SUPPORT + Value = 1 + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable PeiSmmControl support in Project" +End + +MODULE + Help = "Includes PeiSmmControl.mak to Project" + File = "PeiSmmControl.mak" +End + +PATH + Name = "PeiSmmControl_DIR" +End + +ELINK + Name = "$(BUILD_DIR)\PeiSmmControl.ffs" + Parent = "FV_BB" + InvokeOrder = AfterParent +End
\ No newline at end of file diff --git a/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/SmmControl.dxs b/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/SmmControl.dxs new file mode 100644 index 0000000..2ff2cf2 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/SmmControl.dxs @@ -0,0 +1,35 @@ +/** @file + @todo ADD DESCRIPTION + +@copyright + Copyright (c) 2005 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ + +// +// Same for R8 and R9 codebase +// +#include "AutoGen.h" +#include "PeimDepex.h" +// +// For R8 only +// +#ifdef BUILD_WITH_EDKII_GLUE_LIB +#include "EfiDepex.h" + +#endif +DEPENDENCY_START + TRUE +DEPENDENCY_END diff --git a/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/SmmControl.inf b/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/SmmControl.inf new file mode 100644 index 0000000..f65db70 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/SmmControl.inf @@ -0,0 +1,76 @@ +## @file +# Component description file for SmmControl module +# +#@copyright +# Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +[defines] +BASE_NAME = SmmControl +FILE_GUID = FF456B9C-0DC7-4682-9E92-0DE84B6E4067 +COMPONENT_TYPE = PE32_PEIM + +[sources.common] + SmmControlDriver.h + SmmControlDriver.c +# +# Edk II Glue Driver Entry Point +# + EdkIIGluePeimEntryPoint.c + +[includes.common] + . + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Pei/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT) + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include/Library + $(EFI_SOURCE)/Library/Include + $(EFI_SOURCE)/Include +# +# EDK II Glue Library utilizes some standard headers from EDK +# + $(EFI_SOURCE) + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + +[libraries.common] + EdkIIGlueBaseIoLibIntrinsic + EdkIIGlueBaseMemoryLib + EdkIIGluePeiDebugLibReportStatusCode + EdkIIGluePeiReportStatusCodeLib + EdkIIGluePeiServicesLib + EdkIIGlueBasePciLibPciExpress + +[nmake.common] + IMAGE_ENTRY_POINT=_ModuleEntryPoint + DPX_SOURCE=SmmControl.dxs +# +# Module Entry Point +# + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=SmmControlPeiDriverEntryInit + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \ + -D __EDKII_GLUE_BASE_MEMORY_LIB__ \ + -D __EDKII_GLUE_PEI_REPORT_STATUS_CODE_LIB__ \ + -D __EDKII_GLUE_PEI_DEBUG_LIB_REPORT_STATUS_CODE__ \ + -D __EDKII_GLUE_PEI_SERVICES_LIB__ \ + -D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ diff --git a/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/SmmControlDriver.c b/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/SmmControlDriver.c new file mode 100644 index 0000000..a4638e8 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/SmmControlDriver.c @@ -0,0 +1,282 @@ +/** @file + This is the driver that publishes the SMM Control Ppi. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#include "SmmControlDriver.h" + +EFI_GUID mPeiSmmControlPpiGuid = PEI_SMM_CONTROL_PPI_GUID; + +STATIC PEI_SMM_CONTROL_PPI mSmmControlPpi = { + PeiActivate, + PeiDeactivate +}; + +STATIC EFI_PEI_PPI_DESCRIPTOR mPpiList = { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &mPeiSmmControlPpiGuid, + &mSmmControlPpi +}; + +EFI_PEIM_ENTRY_POINT (SmmControlPeiDriverEntryInit) + +/** + This is the constructor for the SMM Control ppi + + @param[in] FfsHeader FfsHeader. + @param[in] PeiServices General purpose services available to every PEIM. + + @retval EFI_STATUS Results of the installation of the SMM Control Ppi +**/ +EFI_STATUS +EFIAPI +SmmControlPeiDriverEntryInit ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + + Status = (**PeiServices).InstallPpi (PeiServices, &mPpiList); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + Trigger the software SMI + + @param[in] Data The value to be set on the software SMI data port + + @retval EFI_SUCCESS Function completes successfully +**/ +EFI_STATUS +EFIAPI +SmmTrigger ( + IN UINT8 Data + ) +{ + UINT32 OutputData; + UINT32 OutputPort; + UINT32 PmBase; + + PmBase = MmioRead32 ( + MmPciAddress (0, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + R_PCH_LPC_ACPI_BASE) + ) & B_PCH_LPC_ACPI_BASE_BAR; + + /// + /// Enable the APMC SMI + /// + OutputPort = PmBase + R_PCH_SMI_EN; + OutputData = IoRead32 ((UINTN) OutputPort); + OutputData |= (B_PCH_SMI_EN_APMC | B_PCH_SMI_EN_GBL_SMI); + DEBUG ( + (EFI_D_INFO, + "The SMI Control Port at address %x will be written to %x.\n", + OutputPort, + OutputData) + ); + IoWrite32 ( + (UINTN) OutputPort, + (UINT32) (OutputData) + ); + + OutputPort = R_PCH_APM_CNT; + OutputData = Data; + + /// + /// Generate the APMC SMI + /// + IoWrite8 ( + (UINTN) OutputPort, + (UINT8) (OutputData) + ); + + return EFI_SUCCESS; +} + +/** + Clear the SMI status + + @param[in] None + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_DEVICE_ERROR Something error occurred +**/ +EFI_STATUS +EFIAPI +SmmClear ( + VOID + ) +{ + UINT32 OutputData; + UINT32 OutputPort; + UINT32 PmBase; + + PmBase = MmioRead32 ( + MmPciAddress (0, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + R_PCH_LPC_ACPI_BASE) + ) & B_PCH_LPC_ACPI_BASE_BAR; + + /// + /// Clear the Power Button Override Status Bit, it gates EOS from being set. + /// + OutputPort = PmBase + R_PCH_ACPI_PM1_STS; + OutputData = B_PCH_ACPI_PM1_STS_PRBTNOR; + DEBUG ( + (EFI_D_INFO, + "The PM1 Status Port at address %x will be written to %x.\n", + OutputPort, + OutputData) + ); + IoWrite16 ( + (UINTN) OutputPort, + (UINT16) (OutputData) + ); + + /// + /// Clear the APM SMI Status Bit + /// + OutputPort = PmBase + R_PCH_SMI_STS; + OutputData = B_PCH_SMI_STS_APM; + DEBUG ( + (EFI_D_INFO, + "The SMI Status Port at address %x will be written to %x.\n", + OutputPort, + OutputData) + ); + IoWrite32 ( + (UINTN) OutputPort, + (UINT32) (OutputData) + ); + + /// + /// Set the EOS Bit + /// + OutputPort = PmBase + R_PCH_SMI_EN; + OutputData = IoRead32 ((UINTN) OutputPort); + OutputData |= B_PCH_SMI_EN_EOS; + DEBUG ( + (EFI_D_INFO, + "The SMI Control Port at address %x will be written to %x.\n", + OutputPort, + OutputData) + ); + IoWrite32 ( + (UINTN) OutputPort, + (UINT32) (OutputData) + ); + + /// + /// If the EOS bit did not get set, then we've got a problem. + /// + DEBUG_CODE ( + OutputData = IoRead32 ((UINTN) OutputPort); + if ((OutputData & B_PCH_SMI_EN_EOS) != B_PCH_SMI_EN_EOS) { + DEBUG ((EFI_D_ERROR, "Bugger, EOS did not get set!\n")); + return EFI_DEVICE_ERROR; + } + ); + + return EFI_SUCCESS; +} + +/** + This routine generates an SMI + + @param[in] PeiServices General purpose services available to every PEIM. + @param[in] This The EFI SMM Control ppi instance + @param[in, out] ArgumentBuffer The buffer of argument + @param[in, out] ArgumentBufferSize The size of the argument buffer + @param[in] Periodic Periodic or not + @param[in] ActivationInterval Interval of periodic SMI + + @retval EFI Status Describing the result of the operation + @retval EFI_INVALID_PARAMETER Some parameter value passed is not supported +**/ +EFI_STATUS +EFIAPI +PeiActivate ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_CONTROL_PPI *This, + IN OUT INT8 *ArgumentBuffer OPTIONAL, + IN OUT UINTN *ArgumentBufferSize OPTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OPTIONAL + ) +{ + EFI_STATUS Status; + UINT8 Data; + + if (Periodic) { + DEBUG ((EFI_D_WARN, "Invalid parameter\n")); + return EFI_INVALID_PARAMETER; + } + + if (ArgumentBuffer == NULL) { + Data = 0xFF; + } else { + if (ArgumentBufferSize == NULL || *ArgumentBufferSize != 1) { + return EFI_INVALID_PARAMETER; + } + + Data = *ArgumentBuffer; + } + /// + /// Clear any pending the APM SMI + /// + Status = SmmClear (); + if (EFI_ERROR (Status)) { + return Status; + } + + return SmmTrigger (Data); +} + +/** + This routine clears an SMI + + @param[in] PeiServices General purpose services available to every PEIM. + @param[in] This The EFI SMM Control ppi instance + @param[in] Periodic Periodic or not + + @retval EFI Status Describing the result of the operation + @retval EFI_INVALID_PARAMETER Some parameter value passed is not supported +**/ +EFI_STATUS +EFIAPI +PeiDeactivate ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_CONTROL_PPI *This, + IN BOOLEAN Periodic OPTIONAL + ) +{ + if (Periodic) { + return EFI_INVALID_PARAMETER; + } + + return SmmClear (); +} + diff --git a/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/SmmControlDriver.h b/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/SmmControlDriver.h new file mode 100644 index 0000000..1cc28b3 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SmmControl/Pei/SmmControlDriver.h @@ -0,0 +1,95 @@ +/** @file + Header file for SMM Control Driver. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _EFI_PEI_SMM_CONTROL_DRIVER_H_ +#define _EFI_PEI_SMM_CONTROL_DRIVER_H_ + +#include "EdkIIGluePeim.h" +#include "Pci22.h" + +// +// Driver private data +// +#include EFI_PPI_DEFINITION (SmmControl) +#include "PchAccess.h" +#include "PchPlatformLib.h" + +// +// Prototypes +// + +/** + This is the constructor for the SMM Control ppi + + @param[in] FfsHeader FfsHeader. + @param[in] PeiServices General purpose services available to every PEIM. + + @retval EFI_STATUS Results of the installation of the SMM Control Ppi +**/ +EFI_STATUS +EFIAPI +SmmControlPeiDriverEntryInit ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices + ); + +/** + This routine generates an SMI + + @param[in] PeiServices General purpose services available to every PEIM. + @param[in] This The EFI SMM Control ppi instance + @param[in, out] ArgumentBuffer The buffer of argument + @param[in, out] ArgumentBufferSize The size of the argument buffer + @param[in] Periodic Periodic or not + @param[in] ActivationInterval Interval of periodic SMI + + @retval EFI Status Describing the result of the operation + @retval EFI_INVALID_PARAMETER Some parameter value passed is not supported +**/ +EFI_STATUS +EFIAPI +PeiActivate ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_CONTROL_PPI *This, + IN OUT INT8 *ArgumentBuffer OPTIONAL, + IN OUT UINTN *ArgumentBufferSize OPTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OPTIONAL + ); + +/** + This routine clears an SMI + + @param[in] PeiServices General purpose services available to every PEIM. + @param[in] This The EFI SMM Control ppi instance + @param[in] Periodic Periodic or not + + @retval EFI Status Describing the result of the operation + @retval EFI_INVALID_PARAMETER Some parameter value passed is not supported +**/ +EFI_STATUS +EFIAPI +PeiDeactivate ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_CONTROL_PPI *This, + IN BOOLEAN Periodic OPTIONAL + ); + +#endif diff --git a/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControl.cif b/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControl.cif new file mode 100644 index 0000000..f683a24 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControl.cif @@ -0,0 +1,13 @@ +<component> + name = "SmmControl" + category = ModulePart + LocalRoot = "ReferenceCode\Chipset\LynxPoint\SmmControl\RuntimeDxe" + RefName = "SmmControl" +[files] +"SmmControl.sdl" +"SmmControl.mak" +"SmmControlDriver.h" +"SmmControlDriver.c" +"SmmControl.dxs" +"SmmControl.inf" +<endComponent> diff --git a/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControl.dxs b/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControl.dxs new file mode 100644 index 0000000..994ee96 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControl.dxs @@ -0,0 +1,36 @@ +/** @file + Dispatch dependency expression file for the SmmControl driver. + +@copyright + Copyright (c) 2004 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ + +// +// Same for R8 and R9 codebase +// +#include "AutoGen.h" +#include "DxeDepex.h" + +// +// For R8 only +// +#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB) +#include "EfiDepex.h" +#endif + +DEPENDENCY_START + TRUE +DEPENDENCY_END diff --git a/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControl.inf b/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControl.inf new file mode 100644 index 0000000..5d9d647 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControl.inf @@ -0,0 +1,85 @@ +## @file +# Component description file for SmmControl module +# +#@copyright +# Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +[defines] +BASE_NAME = SmmControl +FILE_GUID = A0BAD9F7-AB78-491b-B583-C52B7F84B9E0 +COMPONENT_TYPE = RT_DRIVER + +[sources.common] + SmmControlDriver.h + SmmControlDriver.c +# +# Edk II Glue Driver Entry Point +# + EdkIIGlueDxeDriverEntryPoint.c + +[includes.common] + . + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT) + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include/Library +# +# EDK II Glue Library utilizes some standard headers from EDK +# + $(EFI_SOURCE) + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + +[libraries.common] + EdkIIGlueBaseIoLibIntrinsic + EdkIIGlueBaseMemoryLib + EdkIIGlueSmmRuntimeDxeReportStatusCodeLib + EdkIIGlueDxeDebugLibReportStatusCode + EdkIIGlueUefiDevicePathLib + EdkIIGlueUefiBootServicesTableLib + EdkIIGlueUefiRuntimeServicesTableLib + EdkIIGlueDxeMemoryAllocationLib + EdkIIGlueEdkDxeRuntimeDriverLib + EdkIIGlueBasePciLibPciExpress + EdkFrameworkProtocolLib + EdkProtocolLib + PchPlatformLib + +[nmake.common] + IMAGE_ENTRY_POINT = _ModuleEntryPoint + DPX_SOURCE = SmmControl.dxs +# +# Module Entry Point +# + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=SmmControlDriverEntryInit + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_SET_VIRTUAL_ADDRESS_MAP_EVENT_HANDLER__=SmmControlVirtualAddressChangeEvent + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \ + -D __EDKII_GLUE_BASE_MEMORY_LIB__ \ + -D __EDKII_GLUE_SMM_RUNTIME_DXE_REPORT_STATUS_CODE_LIB__ \ + -D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \ + -D __EDKII_GLUE_UEFI_DEVICE_PATH_LIB__ \ + -D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \ + -D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \ + -D __EDKII_GLUE_EDK_DXE_RUNTIME_DRIVER_LIB__ \ + -D __EDKII_GLUE_DXE_MEMORY_ALLOCATION_LIB__ \ + -D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ diff --git a/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControl.mak b/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControl.mak new file mode 100644 index 0000000..802fa7f --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControl.mak @@ -0,0 +1,105 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/SmmControl/SmmControl.mak 2 2/24/12 2:24a Victortu $ +# +# $Revision: 2 $ +# +# $Date: 2/24/12 2:24a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/SmmControl/SmmControl.mak $ +# +# 2 2/24/12 2:24a Victortu +# Updated to support 4.6.5.3_IntelEDK_1117_Patch7_00. +# +# 1 2/08/12 9:21a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +#--------------------------------------------------------------------------- +# Create SmmControl Driver +#--------------------------------------------------------------------------- +EDK : SmmControl +SmmControl : $(BUILD_DIR)\SmmControl.mak SmmControlBin + + +$(BUILD_DIR)\SmmControl.mak : $(SmmControl_DIR)\$(@B).cif $(SmmControl_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(SmmControl_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +SmmControl_INCLUDES=\ + $(INTEL_PCH_INCLUDES)\ + $(EdkIIGlueLib_INCLUDES)\ + +SmmControl_DEFINES = $(MY_DEFINES)\ + /D"__EDKII_GLUE_MODULE_ENTRY_POINT__=SmmControlDriverEntryInit"\ + /D __EDKII_GLUE_BASE_IO_LIB_INTRINSIC__ \ + /D __EDKII_GLUE_BASE_MEMORY_LIB__ \ + /D __EDKII_GLUE_DXE_DEBUG_LIB_REPORT_STATUS_CODE__ \ + /D __EDKII_GLUE_UEFI_DEVICE_PATH_LIB__ \ + /D __EDKII_GLUE_UEFI_BOOT_SERVICES_TABLE_LIB__ \ + /D __EDKII_GLUE_EDK_DXE_RUNTIME_DRIVER_LIB__ \ + /D __EDKII_GLUE_DXE_MEMORY_ALLOCATION_LIB__ \ + /D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ \ + /D __EDKII_GLUE_SMM_RUNTIME_DXE_REPORT_STATUS_CODE_LIB__ \ + /D __EDKII_GLUE_UEFI_RUNTIME_SERVICES_TABLE_LIB__ \ + +SmmControl_LIB_LINKS =\ +!IF "$(x64_BUILD)"=="1" + $(EdkIIGlueBaseLibX64_LIB)\ +!ELSE + $(EdkIIGlueBaseLibIA32_LIB)\ +!ENDIF + $(EdkIIGlueBaseIoLibIntrinsic_LIB)\ + $(EdkIIGlueBaseMemoryLib_LIB)\ + $(EdkIIGlueDxeDebugLibReportStatusCode_LIB)\ + $(EdkIIGlueUefiDevicePathLib_LIB)\ + $(EdkIIGlueUefiBootServicesTableLib_LIB)\ + $(EdkIIGlueDxeMemoryAllocationLib_LIB)\ + $(EdkIIGlueEdkDxeRuntimeDriverLib_LIB)\ + $(EdkIIGlueBasePciLibPciExpress_LIB)\ + $(EDKFRAMEWORKPROTOCOLLIB)\ + $(EDKPROTOCOLLIB)\ + $(PchPlatformDxeLib_LIB)\ + $(SmmControlLib_LIB)\ + $(EdkIIGlueSmmRuntimeDxeReportStatusCodeLib_LIB)\ + $(EdkIIGlueUefiRuntimeServicesTableLib_LIB)\ + +SmmControlBin: $(SmmControl_LIB_LINKS) + $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\ + /f $(BUILD_DIR)\SmmControl.mak all \ + "MY_INCLUDES=$(SmmControl_INCLUDES)" \ + "MY_DEFINES=$(SmmControl_DEFINES)" \ + GUID=A0BAD9F7-AB78-491b-B583-C52B7F84B9E0\ + ENTRY_POINT=_ModuleEntryPoint \ + TYPE=RT_DRIVER\ + EDKIIModule=DXEDRIVER\ + DEPEX1=$(SmmControl_DIR)\SmmControl.dxs\ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + COMPRESS=1 +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControl.sdl b/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControl.sdl new file mode 100644 index 0000000..9809183 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControl.sdl @@ -0,0 +1,67 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/SmmControl/SmmControl.sdl 1 2/08/12 9:21a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 9:21a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Refcode/SmmControl/SmmControl.sdl $ +# +# 1 2/08/12 9:21a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "SmmControl_SUPPORT" + Value = "1" + Help = "Main switch to enable SmmControl support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Token = "SMM_SUPPORT" "=" "1" +End + +PATH + Name = "SmmControl_DIR" +End + +MODULE + File = "SmmControl.mak" + Help = "Includes SmmControl to Project" +End + +ELINK + Name = "$(BUILD_DIR)\SmmControl.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControlDriver.c b/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControlDriver.c new file mode 100644 index 0000000..1220cf2 --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControlDriver.c @@ -0,0 +1,478 @@ +/** @file + This is the driver that publishes the SMM Control Protocol. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement + +**/ +#include "SmmControlDriver.h" + +STATIC SMM_CONTROL_PRIVATE_DATA mSmmControl; +UINT32 mPmBase; +UINT32 mGpioBase; + +VOID +EFIAPI +DisablePendingSmis ( + VOID + ); + +/** + Fixup internal data pointers so that the services can be called in virtual mode. + + @param[in] Event The event registered. + @param[in] Context Event context. + + @retval None. +**/ +VOID +EFIAPI +SmmControlVirtualAddressChangeEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mSmmControl.SmmControl.Trigger)); + gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mSmmControl.SmmControl.Clear)); + gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mSmmControl.SmmControl.GetRegisterInfo)); +} + +/** + This is the constructor for the SMM Control protocol + + @param[in] ImageHandle Handle for the image of this driver + @param[in] SystemTable Pointer to the EFI System Table + + @retval EFI_STATUS Results of the installation of the SMM Control Protocol +**/ +EFI_STATUS +EFIAPI +SmmControlDriverEntryInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + if (!IsPchSupported ()) { + DEBUG ((EFI_D_ERROR, "SMM Control Protocol not supported due to no proper PCH LPC found!\n")); + Status = EFI_UNSUPPORTED; + } + + DEBUG ((EFI_D_INFO, "SmmControlDriverEntryInit() Start\n")); + + /// + /// Get the Power Management I/O space base address. We assume that + /// this base address has already been programmed if this driver is + /// being run. + /// + mGpioBase = MmioRead32 ( + MmPciAddress (0, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + R_PCH_LPC_GPIO_BASE) + ) & B_PCH_LPC_GPIO_BASE_BAR ; + ASSERT (mGpioBase != 0); + + mPmBase = MmioRead32 ( + MmPciAddress (0, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + R_PCH_LPC_ACPI_BASE) + ) & B_PCH_LPC_ACPI_BASE_BAR; + + Status = EFI_SUCCESS; + if (mPmBase != 0) { + /// + /// Install the instance of the protocol + /// + mSmmControl.Signature = SMM_CONTROL_PRIVATE_DATA_SIGNATURE; + mSmmControl.Handle = ImageHandle; + + mSmmControl.SmmControl.Trigger = Activate; + mSmmControl.SmmControl.Clear = Deactivate; + mSmmControl.SmmControl.GetRegisterInfo = GetRegisterInfo; + mSmmControl.SmmControl.MinimumTriggerPeriod = 0; + + /// + /// Install our protocol interfaces on the device's handle + /// + Status = gBS->InstallMultipleProtocolInterfaces ( + &mSmmControl.Handle, + &gEfiSmmControlProtocolGuid, + &mSmmControl.SmmControl, + NULL + ); + } else { + Status = EFI_DEVICE_ERROR; + } + /// + /// Disable any PCH SMIs that, for whatever reason, are asserted after the boot. + /// + DisablePendingSmis (); + + DEBUG ((EFI_D_INFO, "SmmControlDriverEntryInit() End\n")); + + return Status; +} + +/** + Trigger the software SMI + + @param[in] Data The value to be set on the software SMI data port + + @retval EFI_SUCCESS Function completes successfully +**/ +EFI_STATUS +EFIAPI +SmmTrigger ( + IN UINT8 Data + ) +{ + UINT32 OutputData; + UINT32 OutputPort; + + /// + /// Enable the APMC SMI + /// + OutputPort = mPmBase + R_PCH_SMI_EN; + OutputData = IoRead32 ((UINTN) OutputPort); + OutputData |= (B_PCH_SMI_EN_APMC | B_PCH_SMI_EN_GBL_SMI); + DEBUG ( + (EFI_D_VERBOSE, + "The SMI Control Port at address %x will be written to %x.\n", + OutputPort, + OutputData) + ); + IoWrite32 ( + (UINTN) OutputPort, + (UINT32) (OutputData) + ); + + OutputPort = R_PCH_APM_CNT; + OutputData = Data; + + /// + /// Generate the APMC SMI + /// + IoWrite8 ( + (UINTN) OutputPort, + (UINT8) (OutputData) + ); + + return EFI_SUCCESS; +} + +/** + Clear the SMI status + + @param[in] None + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_DEVICE_ERROR Something error occurred +**/ +EFI_STATUS +EFIAPI +SmmClear ( + VOID + ) +{ + EFI_STATUS Status; + UINT32 OutputData; + UINT32 OutputPort; + + Status = EFI_SUCCESS; + + /// + /// Clear the Power Button Override Status Bit, it gates EOS from being set. + /// + OutputPort = mPmBase + R_PCH_ACPI_PM1_STS; + OutputData = B_PCH_ACPI_PM1_STS_PRBTNOR; + DEBUG ( + (EFI_D_VERBOSE, + "The PM1 Status Port at address %x will be written to %x.\n", + OutputPort, + OutputData) + ); + IoWrite16 ( + (UINTN) OutputPort, + (UINT16) (OutputData) + ); + + /// + /// Clear the APM SMI Status Bit + /// + OutputPort = mPmBase + R_PCH_SMI_STS; + OutputData = B_PCH_SMI_STS_APM; + DEBUG ( + (EFI_D_VERBOSE, + "The SMI Status Port at address %x will be written to %x.\n", + OutputPort, + OutputData) + ); + IoWrite32 ( + (UINTN) OutputPort, + (UINT32) (OutputData) + ); + + /// + /// Set the EOS Bit + /// + OutputPort = mPmBase + R_PCH_SMI_EN; + OutputData = IoRead32 ((UINTN) OutputPort); + OutputData |= B_PCH_SMI_EN_EOS; + DEBUG ( + (EFI_D_VERBOSE, + "The SMI Control Port at address %x will be written to %x.\n", + OutputPort, + OutputData) + ); + IoWrite32 ( + (UINTN) OutputPort, + (UINT32) (OutputData) + ); + + /// + /// There is no need to read EOS back and check if it is set. + /// This can lead to a reading of zero if an SMI occurs right after the SMI_EN port read + /// but before the data is returned to the CPU. + /// SMM Dispatcher should make sure that EOS is set after all SMI sources are processed. + /// + return Status; +} + +/** + This routine generates an SMI + + @param[in] This The EFI SMM Control protocol instance + @param[in, out] ArgumentBuffer The buffer of argument + @param[in, out] ArgumentBufferSize The size of the argument buffer + @param[in] Periodic Periodic or not + @param[in] ActivationInterval Interval of periodic SMI + + @retval EFI Status Describing the result of the operation + @retval EFI_INVALID_PARAMETER Some parameter value passed is not supported +**/ +EFI_STATUS +EFIAPI +Activate ( + IN EFI_SMM_CONTROL_PROTOCOL * This, + IN OUT INT8 *ArgumentBuffer OPTIONAL, + IN OUT UINTN *ArgumentBufferSize OPTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OPTIONAL + ) +{ + EFI_STATUS Status; + UINT8 Data; + + if (Periodic) { + DEBUG ((EFI_D_WARN, "Invalid parameter\n")); + return EFI_INVALID_PARAMETER; + } + + if (ArgumentBuffer == NULL) { + Data = 0xFF; + } else { + if (ArgumentBufferSize == NULL || *ArgumentBufferSize != 1) { + return EFI_INVALID_PARAMETER; + } + + Data = *ArgumentBuffer; + } + /// + /// Clear any pending the APM SMI + /// + Status = SmmClear (); + if (EFI_ERROR (Status)) { + return Status; + } + + return SmmTrigger (Data); +} + +/** + This routine clears an SMI + + @param[in] This The EFI SMM Control protocol instance + @param[in] Periodic Periodic or not + + @retval EFI Status Describing the result of the operation + @retval EFI_INVALID_PARAMETER Some parameter value passed is not supported +**/ +EFI_STATUS +EFIAPI +Deactivate ( + IN EFI_SMM_CONTROL_PROTOCOL *This, + IN BOOLEAN Periodic OPTIONAL + ) +{ + if (Periodic) { + return EFI_INVALID_PARAMETER; + } + + return SmmClear (); +} + +/** + This routine gets SMM control register information + + @param[in] This The SMM Control protocol instance + @param[in, out] SmiRegister Output parameter: the SMI control register information is returned + + @retval EFI_INVALID_PARAMETER Parameter SmiRegister is NULL + @retval EFI_SUCCESS Function completes successfully +**/ +EFI_STATUS +EFIAPI +GetRegisterInfo ( + IN EFI_SMM_CONTROL_PROTOCOL *This, + IN OUT EFI_SMM_CONTROL_REGISTER *SmiRegister + ) +{ + if (SmiRegister == NULL) { + return EFI_INVALID_PARAMETER; + } + + SmiRegister->SmiTriggerRegister = R_PCH_APM_CNT; + SmiRegister->SmiDataRegister = R_PCH_APM_STS; + return EFI_SUCCESS; +} + +/** + Disable all pending SMIs + + @param[in] None + + @retval None +**/ +VOID +EFIAPI +DisablePendingSmis ( + VOID + ) +{ + UINT32 Data; + UINT32 Port; + BOOLEAN SciEn; + PCH_SERIES PchSeries; + + /// + /// Determine whether an ACPI OS is present (via the SCI_EN bit) + /// + Port = mPmBase + R_PCH_ACPI_PM1_CNT; + Data = IoRead16 ((UINTN) Port); + SciEn = (BOOLEAN) ((Data & B_PCH_ACPI_PM1_CNT_SCI_EN) == B_PCH_ACPI_PM1_CNT_SCI_EN); + PchSeries = GetPchSeries(); + + if (!SciEn) { + /// + /// Clear any SMIs that double as SCIs (when SCI_EN==0) + /// + Port = mPmBase + R_PCH_ACPI_PM1_STS; + Data = 0xFFFF; + IoWrite16 ((UINTN) Port, (UINT16) (Data)); + + Port = mPmBase + R_PCH_ACPI_PM1_EN; + Data = 0x0000; + IoWrite16 ((UINTN) Port, (UINT16) (Data)); + + Port = mPmBase + R_PCH_ACPI_PM1_CNT; + Data = 0x0000; + IoWrite16 ((UINTN) Port, (UINT16) (Data)); + + if (PchSeries == PchLp) { + Port = mPmBase + R_PCH_ACPI_GPE0_STS_127_96; + Data = 0xFFFBFFFF; + } else if (PchSeries == PchH) { + Port = mPmBase + R_PCH_ACPI_GPE0a_STS; + Data = 0xFFFFFFFF; + } + IoWrite32 ((UINTN) Port, (UINT32) (Data)); + + if (PchSeries == PchLp) { + Port = mPmBase + R_PCH_ACPI_GPE0_EN_127_96; + Data = 0x00040000; + } else if (PchSeries == PchH) { + Port = mPmBase + R_PCH_ACPI_GPE0a_EN; + Data = 0x00000000; + } + IoWrite32 ((UINTN) Port, (UINT32) (Data)); + + if (PchSeries == PchH) { + Port = mPmBase + R_PCH_ACPI_GPE0b_STS; + Data = IoRead32 (Port); + Data |= 0x1F; + IoWrite32 ((UINTN) Port, (UINT32) (Data)); + + Port = mPmBase + R_PCH_ACPI_GPE0b_EN; + Data = IoRead32 (Port); + Data &= 0xFFFFFFE0; + IoWrite32 ((UINTN) Port, (UINT32) (Data)); + } + } + /// + /// Clear and disable all SMIs that are unaffected by SCI_EN + /// + if (PchSeries == PchH) { + Port = mPmBase + R_PCH_LPTH_ALT_GP_SMI_EN; + Data = 0x0000; + IoWrite16 ((UINTN) Port, (UINT16) (Data)); + + Port = mPmBase + R_PCH_LPTH_ALT_GP_SMI_STS; + Data = 0xFFFF; + IoWrite16 ((UINTN) Port, (UINT16) (Data)); + } else if (PchSeries == PchLp) { + Port = mGpioBase + R_PCH_LPTLP_ALT_GP_SMI_EN; + Data = IoRead32 ((UINTN) Port) & 0x0000; + IoWrite32 ((UINTN) Port, Data); + + Port = mGpioBase + R_PCH_LPTLP_ALT_GP_SMI_STS; + Data = IoRead32 ((UINTN) Port) | 0xFFFF; + IoWrite32 ((UINTN) Port, Data); + } + + Port = mPmBase + R_PCH_DEVACT_STS; + Data = 0xFFFF; + IoWrite32 ((UINTN) Port, (UINT32) (Data)); + + Port = mPmBase + R_PCH_SMI_STS; + Data = 0xFFFFFFFF; + IoWrite32 ((UINTN) Port, (UINT32) (Data)); + + /// + /// (Make sure to write this register last -- EOS re-enables SMIs for the PCH) + /// + Port = mPmBase + R_PCH_SMI_EN; + Data = IoRead32 ((UINTN) Port); + /// + /// clear all bits except those tied to SCI_EN + /// + Data &= B_PCH_SMI_EN_BIOS_RLS; + /// + /// enable SMIs and specifically enable writes to APM_CNT. + /// + Data |= B_PCH_SMI_EN_GBL_SMI | B_PCH_SMI_EN_APMC; + /// + /// NOTE: Default value of EOS is set in PCH, it will be automatically cleared Once the PCH asserts SMI# low, + /// we don't need to do anything to clear it + /// + IoWrite32 ((UINTN) Port, (UINT32) (Data)); + +} diff --git a/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControlDriver.h b/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControlDriver.h new file mode 100644 index 0000000..79effdb --- /dev/null +++ b/ReferenceCode/Chipset/LynxPoint/SmmControl/RuntimeDxe/SmmControlDriver.h @@ -0,0 +1,164 @@ +/** @file + Header file for SMM Control Driver. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _SMM_CONTROL_DRIVER_H_ +#define _SMM_CONTROL_DRIVER_H_ + +// +// External include files do NOT need to be explicitly specified in real EDKII +// environment +// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) + +#include "EdkIIGlueDxe.h" +#include "Pci22.h" + +// +// Driver private data +// +#include EFI_PROTOCOL_DEFINITION (SmmControl) +#include "PchAccess.h" +#include "PchPlatformLib.h" +#endif + +#define SMM_CONTROL_PRIVATE_DATA_SIGNATURE EFI_SIGNATURE_32 ('i', '4', 's', 'c') + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; + EFI_SMM_CONTROL_PROTOCOL SmmControl; +} SMM_CONTROL_PRIVATE_DATA; + +#define SMM_CONTROL_PRIVATE_DATA_FROM_THIS(a) CR (a, SMM_CONTROL_PRIVATE_DATA, SmmControl, SMM_CONTROL_DEV_SIGNATURE) + +// +// Prototypes +// + +/** + This is the constructor for the SMM Control protocol + + @param[in] ImageHandle Handle for the image of this driver + @param[in] SystemTable Pointer to the EFI System Table + + @retval EFI_STATUS Results of the installation of the SMM Control Protocol +**/ +EFI_STATUS +EFIAPI +SmmControlDriverEntryInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +/** + Trigger the software SMI + + @param[in] Data The value to be set on the software SMI data port + + @retval EFI_SUCCESS Function completes successfully +**/ +EFI_STATUS +EFIAPI +SmmTrigger ( + UINT8 Data + ); + +/** + Clear the SMI status + + @param[in] None + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_DEVICE_ERROR Something error occurred +**/ +EFI_STATUS +EFIAPI +SmmClear ( + VOID + ); + +/** + This routine generates an SMI + + @param[in] This The EFI SMM Control protocol instance + @param[in, out] ArgumentBuffer The buffer of argument + @param[in, out] ArgumentBufferSize The size of the argument buffer + @param[in] Periodic Periodic or not + @param[in] ActivationInterval Interval of periodic SMI + + @retval EFI Status Describing the result of the operation + @retval EFI_INVALID_PARAMETER Some parameter value passed is not supported +**/ +EFI_STATUS +EFIAPI +Activate ( + IN EFI_SMM_CONTROL_PROTOCOL * This, + IN OUT INT8 *ArgumentBuffer OPTIONAL, + IN OUT UINTN *ArgumentBufferSize OPTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OPTIONAL + ); + +/** + This routine clears an SMI + + @param[in] This The EFI SMM Control protocol instance + @param[in] Periodic Periodic or not + + @retval EFI Status Describing the result of the operation + @retval EFI_INVALID_PARAMETER Some parameter value passed is not supported +**/ +EFI_STATUS +EFIAPI +Deactivate ( + IN EFI_SMM_CONTROL_PROTOCOL *This, + IN BOOLEAN Periodic OPTIONAL + ); + +/** + This routine gets SMM control register information + + @param[in] This The SMM Control protocol instance + @param[in, out] SmiRegister Output parameter: the SMI control register information is returned + + @retval EFI_INVALID_PARAMETER Parameter SmiRegister is NULL + @retval EFI_SUCCESS Function completes successfully +**/ +EFI_STATUS +EFIAPI +GetRegisterInfo ( + IN EFI_SMM_CONTROL_PROTOCOL *This, + IN OUT EFI_SMM_CONTROL_REGISTER *SmiRegister + ); + +/** + Disable all pending SMIs + + @param[in] None + + @retval None +**/ +VOID +EFIAPI +DisablePendingSmis ( + VOID + ); + +#endif |