diff options
Diffstat (limited to 'ReferenceCode/Chipset/SystemAgent/AcpiTables')
33 files changed, 8653 insertions, 0 deletions
diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/Dmar/Dmar.act b/ReferenceCode/Chipset/SystemAgent/AcpiTables/Dmar/Dmar.act new file mode 100644 index 0000000..122a3cc --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/Dmar/Dmar.act @@ -0,0 +1,340 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + + +Module Name: + + Dmar.act + +Abstract: + + This file describes the contents of the ACPI DMA address Remapping + +--*/ + +#include "Dmar.h" + +EFI_ACPI_DMAR_TABLE DmarTable = { + + EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE, + sizeof (EFI_ACPI_DMAR_TABLE), + EFI_ACPI_DMAR_TABLE_REVISION, + + // + // Checksum will be updated at runtime + // + 0x00, + + // + // It is expected that these values will be programmed at runtime + // + 'I', 'N', 'T', 'E', 'L', ' ', + EFI_ACPI_DMAR_OEM_TABLE_ID, + 0x1, + EFI_ACPI_DMAR_OEM_CREATOR_ID, + 1, + + // + // DMAR table specific entries below: + // + + // + // 39-bit addressing Host Address Width + // + 38, + + // + // Flags + // + 0, + + // + // Reserved fields + // + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + // + // First DRHD structure, VT-d Engine #1 + // + { + 0, // Type = 0 (DRHD) + sizeof (EFI_ACPI_DRHD_ENGINE1_STRUCT), // Length of structure + 0, // Flag - Do not include all - bugbug - not clear what this means + 0, // Reserved fields + 0, // Segment + 0x00000000, // Base address of DMA-remapping hardware - Updated at boot time + + // + // Device Scopes + // + { + 1, // Type + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Segment number + 0, // Reserved + 0, // Start bus number + {2, 0} // PCI path + } + }, + + //Second DRHD structure VT-d Engine# 2 + { + 0, // Type = 0 (DRHD) + sizeof(EFI_ACPI_DRHD_ENGINE2_STRUCT), // Length of strucure. + 1, // Flag - Include all + 0, // Reserved + 0, // Segment Number + 0x00000000, // Base address of DMA-remapping hardware. + + { + // + // Device Scopes + // + { + 3, // Type=IO APIC + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 2, // Enumeration ID + 0xF0, // Start bus number + {31, 0} // PCI path + }, + // + // Device Scopes + // + { + 4, // Type=HPET + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 0, // Enumeration ID + 0xF0, // Start bus number + {15, 0} // PCI path + } + , + // + // Device Scopes - I2C0 + // + { + 5, // Type=ACPI_NAMESPACE_DEVICE + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 1, // Enumeration ID + 0, // Start bus number + {21, 1} // PCI path + }, + // + // Device Scopes - I2C1 + // + { + 5, // Type=ACPI_NAMESPACE_DEVICE + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 2, // Enumeration ID + 0, // Start bus number + {21, 2} // PCI path + }, + // + // Device Scopes - SPI0 + // + { + 5, // Type=ACPI_NAMESPACE_DEVICE + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 3, // Enumeration ID + 0, // Start bus number + {21, 3} // PCI path + }, + // + // Device Scopes - SPI1 + // + { + 5, // Type=ACPI_NAMESPACE_DEVICE + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 4, // Enumeration ID + 0, // Start bus number + {21, 4} // PCI path + }, + // + // Device Scopes - UART0 + // + { + 5, // Type=ACPI_NAMESPACE_DEVICE + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 5, // Enumeration ID + 0, // Start bus number + {21, 5} // PCI path + }, + // + // Device Scopes - UART1 + // + { + 5, // Type=ACPI_NAMESPACE_DEVICE + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 6, // Enumeration ID + 0, // Start bus number + {21, 6} // PCI path + }, + // + // Device Scopes - SDIO + // + { + 5, // Type=ACPI_NAMESPACE_DEVICE + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 7, // Enumeration ID + 0, // Start bus number + {23, 0} // PCI path + } + } + }, + + //RMRR structure for USB devices. + { + 0x1, // Type 1 - RMRR structure + sizeof(EFI_ACPI_RMRR_USB_STRUC), // Length + 0x0000, // Reserved + 0x0000, // Segment Num + 0x00000000000E0000, // RMRR Base address - Updated in runtime. + 0x00000000000EFFFF, // RMRR Limit address - Updated in runtime. + { + { + 1, // Type + sizeof(EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 0, // Enum ID + 0, // Start bus number + {29, 0} // PCI path + }, + { + 1, // Type + sizeof(EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 0, // Enum ID + 0, // Start bus number + {26, 0} // PCI path + }, + { + 1, // Type + sizeof(EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 0, // Enum ID + 0, // Start bus number + {20, 0} // PCI path + } + } + }, + + //RMRR structure for IGD device. + { + 1, // Type 1 - RMRR structure + sizeof(EFI_ACPI_RMRR_IGD_STRUC), // Length + 0x0000, // Reserved + 0x0000, // Segment Num + 0x0000000000000000, // RMRR Base address - Updated in runtime. + 0x0000000000000000, // RMRR Limit address - Updated in runtime. + { + { + 1, // Type + sizeof(EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 0, // Enum ID + 0, // Start bus number + {2, 0} // PCI path + } + } + } + , + + // ANDD structure. + { + 4, // Type 4 - ANDD structure + sizeof(EFI_ACPI_ANDD_STRUC), // Length + 0, 0, 0, // Reserved [3] + 1, + "\\_SB.PCI0.I2C0" + }, + + // ANDD structure. + { + 4, // Type 4 - ANDD structure + sizeof(EFI_ACPI_ANDD_STRUC), // Length + 0, 0, 0, // Reserved [3] + 2, + "\\_SB.PCI0.I2C1" + }, + + // ANDD structure. + { + 4, // Type 4 - ANDD structure + sizeof(EFI_ACPI_ANDD_STRUC), // Length + 0, 0, 0, // Reserved [3] + 3, + "\\_SB.PCI0.SPI0" + }, + + // ANDD structure. + { + 4, // Type 4 - ANDD structure + sizeof(EFI_ACPI_ANDD_STRUC), // Length + 0, 0, 0, // Reserved [3] + 4, + "\\_SB.PCI0.SPI1" + }, + + // ANDD structure. + { + 4, // Type 4 - ANDD structure + sizeof(EFI_ACPI_ANDD_STRUC), // Length + 0, 0, 0, // Reserved [3] + 5, + "\\_SB.PCI0.UA00" + }, + + // ANDD structure. + { + 4, // Type 4 - ANDD structure + sizeof(EFI_ACPI_ANDD_STRUC), // Length + 0, 0, 0, // Reserved [3] + 6, + "\\_SB.PCI0.UA01" + }, + + // ANDD structure. + { + 4, // Type 4 - ANDD structure + sizeof(EFI_ACPI_ANDD_STRUC), // Length + 0, 0, 0, // Reserved [3] + 7, + "\\_SB.PCI0.SDHC" + } +}; + +// +// Dummy function required for build tools +// +int +main ( + VOID + ) +{ + return 0; +}
\ No newline at end of file diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/Dmar/Dmar.h b/ReferenceCode/Chipset/SystemAgent/AcpiTables/Dmar/Dmar.h new file mode 100644 index 0000000..0025a02 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/Dmar/Dmar.h @@ -0,0 +1,39 @@ +/** @file + This file describes the contents of the ACPI DMA address Remapping + Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _SA_DMAR_H_ +#define _SA_DMAR_H_ + +/// +/// Include standard ACPI table definitions +/// +#include "Acpi1_0.h" +#include "Acpi2_0.h" +#include "Acpi3_0.h" +#include "DmaRemappingTable.h" + +#pragma pack(1) + +#define EFI_ACPI_DMAR_OEM_TABLE_ID 0x20575348 ///< "HSW " +#define EFI_ACPI_DMAR_OEM_CREATOR_ID 0x4C544E49 ///< "INTL" +#pragma pack() + +#endif diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/HOST_BUS.ASL b/ReferenceCode/Chipset/SystemAgent/AcpiTables/HOST_BUS.ASL new file mode 100644 index 0000000..439736e --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/HOST_BUS.ASL @@ -0,0 +1,770 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + + +Module Name: + + HOST_BUS.ASL + +Abstract: + + SystemAgent PCI configuration space definition. + +--*/ + + + // + // Define various System Agent (SA) PCI Configuration Space + // registers which will be used to dynamically produce all + // resources in the Host Bus _CRS. + // +OperationRegion (HBUS, PCI_Config, 0x00, 0x100) +Field (HBUS, DWordAcc, NoLock, Preserve) +{ + Offset(0x40), // EPBAR (0:0:0:40) + EPEN, 1, // Enable + , 11, + EPBR, 20, // EPBAR [31:12] + + Offset(0x48), // MCHBAR (0:0:0:48) + MHEN, 1, // Enable + , 14, + MHBR, 17, // MCHBAR [31:15] + + Offset(0x50), // GGC (0:0:0:50) + GCLK, 1, // GGCLCK + + Offset(0x54), // DEVEN (0:0:0:54) + D0EN, 1, // DEV0 Enable + D1F2, 1, // DEV1 FUN2 Enable + D1F1, 1, // DEV1 FUN1 Enable + D1F0, 1, // DEV1 FUN0 Enable + + Offset(0x60), // PCIEXBAR (0:0:0:60) + PXEN, 1, // Enable + PXSZ, 2, // PCI Express Size + , 23, + PXBR, 6, // PCI Express BAR [31:26] + + Offset(0x68), // DMIBAR (0:0:0:68) + DIEN, 1, // Enable + , 11, + DIBR, 20, // DMIBAR [31:12] + + Offset(0x70), // MESEG_BASE (0:0:0:70) + , 20, + MEBR, 12, // MESEG_BASE [31:20] + + Offset(0x80), // PAM0 Register (0:0:0:80) + , 4, + PM0H, 2, // PAM 0, High Nibble + , 2, + + Offset(0x81), // PAM1 Register (0:0:0:81) + PM1L, 2, // PAM1, Low Nibble + , 2, + PM1H, 2, // PAM1, High Nibble + , 2, + + Offset(0x82), // PAM2 Register (0:0:0:82) + PM2L, 2, // PAM2, Low Nibble + , 2, + PM2H, 2, // PAM2, High Nibble + , 2, + + Offset(0x83), // PAM3 Register (0:0:0:83) + PM3L, 2, // PAM3, Low Nibble + , 2, + PM3H, 2, // PAM3, High Nibble + , 2, + + Offset(0x84), // PAM4 Register (0:0:0:84) + PM4L, 2, // PAM4, Low Nibble + , 2, + PM4H, 2, // PAM4, High Nibble + , 2, + + Offset(0x85), // PAM5 Register (0:0:0:85) + PM5L, 2, // PAM5, Low Nibble + , 2, + PM5H, 2, // PAM5, High Nibble + , 2, + + Offset(0x86), // PAM6 Register (0:0:0:86) + PM6L, 2, // PAM6, Low Nibble + , 2, + PM6H, 2, // PAM6, High Nibble + , 2, + + Offset(0xA8), // Top of Upper Usable DRAM Register (0:0:0:A8) + , 20, + TUUD, 19, // TOUUD [38:20] + + Offset(0xBC), // Top of Lower Usable DRAM Register (0:0:0:BC) + , 20, + TLUD, 12, // TOLUD [31:20] + + Offset(0xC8), // ERRSTS register (0:0:0:C8) + , 7, + HTSE, 1 // Host Thermal Sensor Event for SMI/SCI/SERR +} + +OperationRegion (MCHT, SystemMemory, 0xFED10000, 0x1100) + +// Define a buffer that will store all the bus, memory, and IO information +// relating to the Host Bus. This buffer will be dynamically altered in +// the _CRS and passed back to the OS. + +Name(BUF0,ResourceTemplate() +{ + // Bus Number Allocation: Bus 0 to 0xFF + + WORDBusNumber(ResourceProducer,MinFixed,MaxFixed,PosDecode,0x00, + 0x0000,0x00FF,0x00,0x0100,,,PB00) + + // I/O Region Allocation 0 ( 0x0000 - 0x0CF7 ) + + DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange, + 0x00,0x0000,0x0CF7,0x00,0x0CF8,,,PI00) + + // PCI Configuration Registers ( 0x0CF8 - 0x0CFF ) + + Io(Decode16,0x0CF8,0x0CF8,1,0x08) + + // I/O Region Allocation 1 ( 0x0D00 - 0xFFFF ) + + DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange, + 0x00,0x0D00,0xFFFF,0x00,0xF300,,,PI01) + + // Video Buffer Area ( 0xA0000 - 0xBFFFF ) + + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xA0000,0xBFFFF,0x00,0x20000,,,A000) + + // ISA Add-on BIOS Area ( 0xC0000 - 0xC3FFF ) + + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xC0000,0xC3FFF,0x00,0x4000,,,C000) + + // ISA Add-on BIOS Area ( 0xC4000 - 0xC7FFF ) + + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xC4000,0xC7FFF,0x00,0x4000,,,C400) + + // ISA Add-on BIOS Area ( 0xC8000 - 0xCBFFF ) + + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xC8000,0xCBFFF,0x00,0x4000,,,C800) + + // ISA Add-on BIOS Area ( 0xCC000 - 0xCFFFF ) + + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xCC000,0xCFFFF,0x00,0x4000,,,CC00) + + // ISA Add-on BIOS Area ( 0xD0000 - 0xD3FFF ) + + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xD0000,0xD3FFF,0x00,0x4000,,,D000) + + // ISA Add-on BIOS Area ( 0xD4000 - 0xD7FFF ) + + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xD4000,0xD7FFF,0x00,0x4000,,,D400) + + // ISA Add-on BIOS Area ( 0xD8000 - 0xDBFFF ) + + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xD8000,0xDBFFF,0x00,0x4000,,,D800) + + // ISA Add-on BIOS Area ( 0xDC000 - 0xDFFFF ) + + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xDC000,0xDFFFF,0x00,0x4000,,,DC00) + + // BIOS Extension Area ( 0xE0000 - 0xE3FFF ) + + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xE0000,0xE3FFF,0x00,0x4000,,,E000) + + // BIOS Extension Area ( 0xE4000 - 0xE7FFF ) + + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xE4000,0xE7FFF,0x00,0x4000,,,E400) + + // BIOS Extension Area ( 0xE8000 - 0xEBFFF ) + + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xE8000,0xEBFFF,0x00,0x4000,,,E800) + + // BIOS Extension Area ( 0xEC000 - 0xEFFFF ) + + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xEC000,0xEFFFF,0x00,0x4000,,,EC00) + + // BIOS Area ( 0xF0000 - 0xFFFFF ) + + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xF0000,0xFFFFF,0x00,0x10000,,,F000) + +// // Memory Hole Region ( 0xF00000 - 0xFFFFFF ) +// +// DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, +// ReadWrite,0x00,0xF00000,0xFFFFFF,0x00,0x100000,,,HOLE) + + // PCI Memory Region ( TOLUD - 0xFEAFFFFF ) + + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0x00000000,0xFEAFFFFF,0x00,0xFEB00000,,,PM01) +}) + +Method(_CRS,0,Serialized) +{ + // Fix up Max Bus Number and Length + CreateWordField(BUF0, ^PB00._MAX, PBMX) + Store(Subtract(ShiftRight(\PELN,20),2), PBMX) + CreateWordField(BUF0, ^PB00._LEN, PBLN) + Store(Subtract(ShiftRight(\PELN,20),1), PBLN) + // Fix up all of the Option ROM areas from 0xC0000-0xFFFFF. + // + + If(PM1L) // \_SB.PCI0 + { + // PAMx != 0. Set length = 0. + + CreateDwordField(BUF0, ^C000._LEN,C0LN) + Store(Zero,C0LN) + } + + If(LEqual(PM1L,1)) + { + CreateBitField(BUF0, ^C000._RW,C0RW) + Store(Zero,C0RW) + } + + If(PM1H) + { + CreateDwordField(BUF0, ^C400._LEN,C4LN) + Store(Zero,C4LN) + } + + If(LEqual(PM1H,1)) + { + CreateBitField(BUF0, ^C400._RW,C4RW) + Store(Zero,C4RW) + } + + If(PM2L) + { + CreateDwordField(BUF0, ^C800._LEN,C8LN) + Store(Zero,C8LN) + } + + If(LEqual(PM2L,1)) + { + CreateBitField(BUF0, ^C800._RW,C8RW) + Store(Zero,C8RW) + } + + If(PM2H) + { + CreateDwordField(BUF0, ^CC00._LEN,CCLN) + Store(Zero,CCLN) + } + + If(LEqual(PM2H,1)) + { + CreateBitField(BUF0, ^CC00._RW,CCRW) + Store(Zero,CCRW) + } + + If(PM3L) + { + CreateDwordField(BUF0, ^D000._LEN,D0LN) + Store(Zero,D0LN) + } + + If(LEqual(PM3L,1)) + { + CreateBitField(BUF0, ^D000._RW,D0RW) + Store(Zero,D0RW) + } + + If(PM3H) + { + CreateDwordField(BUF0, ^D400._LEN,D4LN) + Store(Zero,D4LN) + } + + If(LEqual(PM3H,1)) + { + CreateBitField(BUF0, ^D400._RW,D4RW) + Store(Zero,D4RW) + } + + If(PM4L) + { + CreateDwordField(BUF0, ^D800._LEN,D8LN) + Store(Zero,D8LN) + } + + If(LEqual(PM4L,1)) + { + CreateBitField(BUF0, ^D800._RW,D8RW) + Store(Zero,D8RW) + } + + If(PM4H) + { + CreateDwordField(BUF0, ^DC00._LEN,DCLN) + Store(Zero,DCLN) + } + + If(LEqual(PM4H,1)) + { + CreateBitField(BUF0, ^DC00._RW,DCRW) + Store(Zero,DCRW) + } + + If(PM5L) + { + CreateDwordField(BUF0, ^E000._LEN,E0LN) + Store(Zero,E0LN) + } + + If(LEqual(PM5L,1)) + { + CreateBitField(BUF0, ^E000._RW,E0RW) + Store(Zero,E0RW) + } + + If(PM5H) + { + CreateDwordField(BUF0, ^E400._LEN,E4LN) + Store(Zero,E4LN) + } + + If(LEqual(PM5H,1)) + { + CreateBitField(BUF0, ^E400._RW,E4RW) + Store(Zero,E4RW) + } + + If(PM6L) + { + CreateDwordField(BUF0, ^E800._LEN,E8LN) + Store(Zero,E8LN) + } + + If(LEqual(PM6L,1)) + { + CreateBitField(BUF0, ^E800._RW,E8RW) + Store(Zero,E8RW) + } + + If(PM6H) + { + CreateDwordField(BUF0, ^EC00._LEN,ECLN) + Store(Zero,ECLN) + } + + If(LEqual(PM6H,1)) + { + CreateBitField(BUF0, ^EC00._RW,ECRW) + Store(Zero,ECRW) + } + + If(PM0H) + { + CreateDwordField(BUF0, ^F000._LEN,F0LN) + Store(Zero,F0LN) + } + + If(LEqual(PM0H,1)) + { + CreateBitField(BUF0, ^F000._RW,F0RW) + Store(Zero,F0RW) + } + +// // Enable the 1MB region between 15-16MB if HENA = 1. +// +// If( MCHC.HENA) +// { +// CreateDwordField(BUF0, HOLE._LEN,H0LN) +// Store(0x100000,H0LN) +// } + + // Create pointers to Memory Sizing values. + + CreateDwordField(BUF0, ^PM01._MIN,M1MN) + CreateDwordField(BUF0, ^PM01._MAX,M1MX) + CreateDwordField(BUF0, ^PM01._LEN,M1LN) + + // Set Memory Size Values. TLUD represents bits 31:20 of phyical + // TOM, so shift these bits into the correct position and fix up + // the Memory Region available to PCI. + + ShiftLeft( TLUD,20,M1MN) + Add(Subtract(M1MX,M1MN),1,M1LN) + + Return(BUF0) +} + +//Name(GUID,UUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) +Name(GUID,Buffer(){0x5b, 0x4d, 0xdb, 0x33, + 0xf7, 0x1f, + 0x1c, 0x40, + 0x96, 0x57, + 0x74, 0x41, 0xc0, 0x3d, 0xd7, 0x66}) + + +Name(SUPP,0) // PCI _OSC Support Field value +Name(CTRL,0) // PCI _OSC Control Field value +Name(XCNT, 0) // Variable used in _OSC for counting + +Method(_OSC,4,Serialized) +{ // Check for proper UUID + // Save the capabilities buffer + Store(Arg3,Local0) + + // Create DWord-adressable fields from the Capabilties Buffer + CreateDWordField(Local0,0,CDW1) + CreateDWordField(Local0,4,CDW2) + CreateDWordField(Local0,8,CDW3) + + + // + // This provides a facility for the PCH reference code to expose USB XHCI controllers to the OS. + // Refer to Intel PCH reference code for further details. + // + if (\_SB.PCI0.XHC.CUID(Arg0)) { + Return (\_SB.PCI0.XHC.POSC(Arg1, Arg2, Arg3)) + } else { + If (LGreaterEqual(OSYS,2012)) { + If(LEqual(XCNT, 0)) { + \_SB.PCI0.XHC.XSEL() + Increment(XCNT) + } + } + } + + // Check for proper UUID +#ifdef AMI_ORIGINAL_FOR_FIX_UUID_INVALID + If(LAnd(LEqual(Arg0,GUID),NEXP)) +#else // AMI_ORIGINAL_FOR_FIX_UUID_INVALID + If(LEqual(Arg0,GUID)) +#endif // AMI_ORIGINAL_FOR_FIX_UUID_INVALID + { + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // You can clear bits in CTRL here if you don't want OS to take + // control + +// And(CTRL, 0xFFFFFFF8, CTRL) // disable Native hot plug, PME + +#ifdef AMI_ORIGINAL_FOR_FIX_UUID_INVALID + If(Not(And(CDW1,1))) // Query flag clear? + { // Disable GPEs for features granted native control. + If(And(CTRL,0x01)) + { + NHPG() + } + If(And(CTRL,0x04)) // PME control granted? + { + NPME() + } + } +#else // AMI_ORIGINAL_FOR_FIX_UUID_INVALID + If (LEqual(NEXP,0)) + { + And(CTRL, 0xFFFFFFF8, CTRL) // disable Native hot plug, PME + } + + If (NEXP) + { + If(Not(And(CDW1,1))) // Query flag clear? + { // Disable GPEs for features granted native control. + If(And(CTRL,0x01)) + { + NHPG() + } + If(And(CTRL,0x04)) // PME control granted? + { + NPME() + } + } + } + +#endif // AMI_ORIGINAL_FOR_FIX_UUID_INVALID + + If(LNotEqual(Arg1,One)) + { // Unknown revision + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) + { // Capabilities bits were masked + Or(CDW1,0x10,CDW1) + } + // Update DWORD3 in the buffer + Store(CTRL,CDW3) + Store(CTRL,OSCC) + Return(Local0) + } Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Local0) + } +} // End _OSC + +// Added code for Dual IRQ support. Two set of ACPI IRQ tables were generated. +// Code has been added to select the appropriate IRQ table by checking the CPUID. +Scope(\_SB.PCI0) +{ + Method(AR00) { + Return(\_SB.AR00) + + } + + Method(PR00) { + Return(\_SB.PR00) + } + +#if defined(ASL_PCI_BRIDGE_DISABLE) && (ASL_PCI_BRIDGE_DISABLE == 0) + Method(AR01) { + Return(\_SB.AR01) + } + + Method(PR01) { + Return(\_SB.PR01) + } +#endif + +#ifdef AMI_ORIGINAL_FOR_DISABLE_PCIE_SLOT + Method(AR02) { + Return(\_SB.AR02) + } + + Method(PR02) { + Return(\_SB.PR02) + } + + Method(AR04) { + Return(\_SB.AR04) + } + + Method(PR04) { + Return(\_SB.PR04) + } + + Method(AR05) { + Return(\_SB.AR05) + } + + Method(PR05) { + Return(\_SB.PR05) + } + + Method(AR06) { + Return(\_SB.AR06) + } + + Method(PR06) { + Return(\_SB.PR06) + } + + Method(AR07) { + Return(\_SB.AR07) + } + + Method(PR07) { + Return(\_SB.PR07) + } + + Method(AR08) { + Return(\_SB.AR08) + } + + Method(PR08) { + Return(\_SB.PR08) + } + + Method(AR09) { + Return(\_SB.AR09) + } + + Method(PR09) { + Return(\_SB.PR09) + } + + Method(AR0A) { + Return(\_SB.AR0A) + } + + Method(PR0A) { + Return(\_SB.PR0A) + } + + Method(AR0B) { + Return(\_SB.AR0B) + } + + Method(PR0B) { + Return(\_SB.PR0B) + } +#else // AMI_ORIGINAL_FOR_DISABLE_PCIE_SLOT +#if defined(ASL_RC_PEG_0) && (ASL_RC_PEG_0 == 1) + Method(AR02) { + Return(\_SB.AR02) + } + + Method(PR02) { + Return(\_SB.PR02) + } +#endif + +#if defined (ASL_RC_PORT_0) && (ASL_RC_PORT_0 == 1) + Method(AR04) { + Return(\_SB.AR04) + } + + Method(PR04) { + Return(\_SB.PR04) + } + +#if defined (ASL_RC_PORT_1) && (ASL_RC_PORT_1 == 1) + Method(AR05) { + Return(\_SB.AR05) + } + + Method(PR05) { + Return(\_SB.PR05) + } +#endif + +#if defined (ASL_RC_PORT_2) && (ASL_RC_PORT_2 == 1) + Method(AR06) { + Return(\_SB.AR06) + } + + Method(PR06) { + Return(\_SB.PR06) + } +#endif + +#if defined (ASL_RC_PORT_3) && (ASL_RC_PORT_3 == 1) + Method(AR07) { + Return(\_SB.AR07) + } + + Method(PR07) { + Return(\_SB.PR07) + } +#endif + +#if defined (ASL_RC_PORT_4) && (ASL_RC_PORT_4 == 1) + Method(AR08) { + Return(\_SB.AR08) + } + + Method(PR08) { + Return(\_SB.PR08) + } +#endif + +#if defined (ASL_RC_PORT_5) && (ASL_RC_PORT_5 == 1) + Method(AR09) { + Return(\_SB.AR09) + } + + Method(PR09) { + Return(\_SB.PR09) + } +#endif + +#if defined (ASL_RC_PORT_6) && (ASL_RC_PORT_6 == 1) + Method(AR0E) { + Return(\_SB.AR0E) + } + + Method(PR0E) { + Return(\_SB.PR0E) + } +#endif + +#if defined (ASL_RC_PORT_7) && (ASL_RC_PORT_7 == 1) + Method(AR0F) { + Return(\_SB.AR0F) + } + + Method(PR0F) { + Return(\_SB.PR0F) + } +#endif +#endif + +#if defined(ASL_RC_PEG_1) && (ASL_RC_PEG_1 == 1) + Method(AR0A) { + Return(\_SB.AR0A) + } + + Method(PR0A) { + Return(\_SB.PR0A) + } + +#if defined(ASL_RC_PEG_2) && (ASL_RC_PEG_2 == 1) + Method(AR0B) { + Return(\_SB.AR0B) + } + + Method(PR0B) { + Return(\_SB.PR0B) + } +#endif +#endif +#endif // AMI_ORIGINAL_FOR_DISABLE_PCIE_SLOT +} + +#ifndef AMI_OVERRIDE_FOR_TPM_AREA_REPORT +Device(TPMX) +{ + Name(_HID, EISAID("PNP0C01")) // Hardware Device ID + Name(_UID, 1) + + Name(CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xFED40000, 0x5000, TPMR) //Non-writeable + }) + + Method (_CRS, 0) + { + Return(CRS) + } + // if TPM is active, TPM module will report TPM area to OS. + Method (_STA, 0) + { + If(TPMF) + { + Return(0x00) + } + Return(0x0F) + } +} +#endif // AMI_OVERRIDE_FOR_TPM_AREA_REPORT diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.cif b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.cif new file mode 100644 index 0000000..3dc05f6 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.cif @@ -0,0 +1,18 @@ +<component> + name = "SaAcpiTables" + category = ModulePart + LocalRoot = "ReferenceCode\Chipset\SystemAgent\AcpiTables" + RefName = "SaAcpiTables" +[files] +"SaAcpiTables.sdl" +"SaAcpiTables.mak" +"HOST_BUS.ASL" +"Dmar\Dmar.act" +"Dmar\Dmar.h" +"SaAcpiTables.inf" +"SaAcpiTables_Edk.inf" +[parts] +"SaSsdtTables" +"SgAcpiTablesPeg" +"SgAcpiTablesPch" +<endComponent> diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.inf b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.inf new file mode 100644 index 0000000..3439079 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.inf @@ -0,0 +1,54 @@ +## @file +# Component description file for the ACPI tables +# +#@copyright +# Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +[defines] +BASE_NAME = SaAcpiTables +FILE_GUID = 27E569D5-0AFC-4D8F-8C90-783AC4A318AB +COMPONENT_TYPE = ACPITABLE +FFS_EXT = .ffs + +[sources.common] + Dmar/Dmar.act + Dmar/Dmar.h + +[libraries.common] + +[includes.common] + . + $(EFI_SOURCE) + $(EFI_SOURCE)/Include + $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EFI_SOURCE)/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + +# +# Typically the sample code referenced will be available in the code base already +# So keep this include at the end to defer to the source base definition +# and only use the sample code definition if source base does not include these files. +# + $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode/Include + +[nmake.common] diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.mak b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.mak new file mode 100644 index 0000000..c4cd7e7 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.mak @@ -0,0 +1,41 @@ +all : SaAcpiTables + +SaAcpiTables : $(BUILD_DIR)\SaAcpiTables.ffS + +SaAcpiTables_Includes = \ + $(EDK_INCLUDES)\ + $(INTEL_MCH_INCLUDES)\ + +SaAcpiTables_Defines = \ + /D"TIANO_RELEASE_VERSION=0x00080006"\ + +SaAcpiTables_ACPIS = \ + $(BUILD_DIR)\Dmar.acpi\ + +$(BUILD_DIR)\SaAcpiTables.asl: $(BUILD_DIR)\token.mak $(SaAcpiTables_DIR)\SaAcpiTables.mak + copy << $@ +!IF "$(TCG2Support)" == "0" || "$(TCG2Support)" == "" +!IF "$(TCG_SUPPORT)" != "1" +Name(TPMF, 0x0) +!ENDIF +!ENDIF +<< + +$(BUILD_DIR)\Dmar.exe : $(SaAcpiTables_DIR)\Dmar\Dmar.act $(SaAcpiTables_DIR)\Dmar\Dmar.h + @CL $(CFLAGS) $(SaAcpiTables_Defines) /Fo$(BUILD_DIR)\ $(SaAcpiTables_Includes) /TC $(SaAcpiTables_DIR)\Dmar\Dmar.act + @Link /OUT:$(BUILD_DIR)\Dmar.exe /NODEFAULTLIB /ENTRY:main $(BUILD_DIR)\Dmar.obj + +$(BUILD_DIR)\Dmar.acpi : $(BUILD_DIR)\Dmar.exe + $(GENACPITABLE) $(BUILD_DIR)\Dmar.exe $(BUILD_DIR)\Dmar.acpi + +$(BUILD_DIR)\SaAcpiTables.sec : $(SaAcpiTables_ACPIS) + $(GENSECTION) -I $** -O $@ -S EFI_SECTION_RAW + +$(BUILD_DIR)\SaAcpiTables.ffs: $(BUILD_DIR)\SaAcpiTables.sec $(SaAcpiTables_DIR)\SaAcpiTables.mak + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=27E569D5-0AFC-4D8F-8C90-783AC4A318AB\ + TYPE=EFI_FV_FILETYPE_FREEFORM \ + FFS_CHECKSUM=1\ + RAWFILE=$(BUILD_DIR)\SaAcpiTables.sec FFSFILE=$(BUILD_DIR)\SaAcpiTables.ffs COMPRESS=0 NAME=SaAcpiTables + diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.sdl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.sdl new file mode 100644 index 0000000..e122ec8 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables.sdl @@ -0,0 +1,41 @@ +TOKEN + Name = "SaAcpiTables_SUPPORT" + Value = "1" + Help = "Main switch to enable SaAcpiTables support in Project" + TokenType = Boolean + Master = Yes +End + +PATH + Name = "SaAcpiTables_DIR" +End + +TOKEN + Name = "GENACPITABLE" + Value = "$(INTEL_SYSTEM_AGENT_DIR)\SampleCode\Tools\GenAcpiTable" + TokenType = Expression + TargetMAK = Yes +End + +MODULE + Help = "Includes SaAcpiTables.mak to Project" + File = "SaAcpiTables.mak" +End + +ELINK + Name = "/I$(SaAcpiTables_DIR)\Dmar" + Parent = "INTEL_MCH_INCLUDES" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(BUILD_DIR)\SaAcpiTables.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(BUILD_DIR)\SaAcpiTables.asl" + Parent = "GENERIC_ASL" + InvokeOrder = AfterParent +End diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables_Edk.inf b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables_Edk.inf new file mode 100644 index 0000000..b47548a --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaAcpiTables_Edk.inf @@ -0,0 +1,54 @@ +## @file +# Component description file for the ACPI tables (for EDK1117) +# +#@copyright +# Copyright (c) 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + +[defines] +BASE_NAME = SaAcpiTables +FILE_GUID = 27E569D5-0AFC-4D8F-8C90-783AC4A318AB +COMPONENT_TYPE = SA_DMAR_ACPITABLE +FFS_EXT = .ffs + +[sources.common] + Dmar/Dmar.act + Dmar/Dmar.h + +[libraries.common] + +[includes.common] + . + $(EFI_SOURCE) + $(EFI_SOURCE)/Include + $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EFI_SOURCE)/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + +# +# Typically the sample code referenced will be available in the code base already +# So keep this include at the end to defer to the source base definition +# and only use the sample code definition if source base does not include these files. +# + $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode/Include + +[nmake.common] diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/INTELGFX.ASL b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/INTELGFX.ASL new file mode 100644 index 0000000..153afd5 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/INTELGFX.ASL @@ -0,0 +1,1731 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + + +Module Name: + + INTELGFX.ASL + +Abstract: + + IGD OpRegion/Software ACPI Reference Code. + +--*/ + + + External(\_SB.PCI0.GFX0.IDAB, MethodObj) + External(\_SB.PCI0.GFX0.HWID, MethodObj) + External(\ECST, MethodObj) + External(HDOS, MethodObj) +#if !defined(ASL_Remove_SaSsdt_Data_To_Dsdt) || (ASL_Remove_SaSsdt_Data_To_Dsdt == 0) + External(\ECON, IntObj) + External(\PNHM, IntObj) +#endif // AMI_OVERRIDE + External(OSYS, IntObj) + External(SCIS) + External(\GUAM, MethodObj) + External(DSEN) + External(BID) + External(BHB) + External(BFS2) + External(BFS3) + External(BFS4) + + + External(S0ID) + External(\ADBG, MethodObj) + External(\_SB.PEPD, DeviceObj) + + Method(_DEP){ + ADBG("GFX0 DEP Call") + If(LEqual(S0ID, 1)){ + ADBG("GFX0 DEP") + Return(Package() {\_SB.PEPD}) + }Else{ + ADBG("GFX0 DEP NULL") + Return(Package(){}) + } + } + + // Enable/Disable Output Switching. In WIN2K/WINXP, _DOS = 0 will + // get called during initialization to prepare for an ACPI Display + // Switch Event. During an ACPI Display Switch, the OS will call + // _DOS = 2 immediately after a Notify=0x80 to temporarily disable + // all Display Switching. After ACPI Display Switching is complete, + // the OS will call _DOS = 0 to re-enable ACPI Display Switching. + + Method(_DOS,1) + { + // Store Display Switching and LCD brightness BIOS control bit + Store(And(Arg0,7),DSEN) + + If(LEqual(And(Arg0, 0x3), 0)) // If _DOS[1:0]=0 + { + If(CondRefOf(HDOS)) + { + HDOS() + } + } + } + + // Enumerate the Display Environment. This method will return + // valid addresses for all display device encoders present in the + // system. The Miniport Driver will reject the addresses for every + // encoder that does not have an attached display device. After + // enumeration is complete, the OS will call the _DGS methods + // during a display switch only for the addresses accepted by the + // Miniport Driver. For hot-insertion and removal of display + // devices, a re-enumeration notification will be required so the + // address of the newly present display device will be accepted by + // the Miniport Driver. + + Method(_DOD,0) + { + + If (CondRefOf(IDAB)) + { + IDAB() + } + Else + { + Store(0, NDID) + + If(LNotEqual(DIDL, Zero)) + { + Store(SDDL(DIDL),DID1) + } + If(LNotEqual(DDL2, Zero)) + { + Store(SDDL(DDL2),DID2) + } + If(LNotEqual(DDL3, Zero)) + { + Store(SDDL(DDL3),DID3) + } + If(LNotEqual(DDL4, Zero)) + { + Store(SDDL(DDL4),DID4) + } + If(LNotEqual(DDL5, Zero)) + { + Store(SDDL(DDL5),DID5) + } + If(LNotEqual(DDL6, Zero)) + { + Store(SDDL(DDL6),DID6) + } + If(LNotEqual(DDL7, Zero)) + { + Store(SDDL(DDL7),DID7) + } + If(LNotEqual(DDL8, Zero)) + { + Store(SDDL(DDL8),DID8) + } + If(LNotEqual(DDL9, Zero)) + { + Store(SDDL(DDL9),DID9) + } + If(LNotEqual(DD10, Zero)) + { + Store(SDDL(DD10),DIDA) + } + If(LNotEqual(DD11, Zero)) + { + Store(SDDL(DD11),DIDB) + } + If(LNotEqual(DD12, Zero)) + { + Store(SDDL(DD12),DIDC) + } + If(LNotEqual(DD13, Zero)) + { + Store(SDDL(DD13),DIDD) + } + If(LNotEqual(DD14, Zero)) + { + Store(SDDL(DD14),DIDE) + } + If(LNotEqual(DD15, Zero)) + { + Store(SDDL(DD15),DIDF) + } + } + + // @todo - This level of flexibility is not needed for a true + // OEM design. Simply determine the greatest number of + // encoders the platform will suppport then remove all + // return packages beyond that value. Note that for + // current silicon, the maximum number of encoders + // possible is 8. + + If(LEqual(NDID,1)) + { + Name(TMP1,Package() {0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP1,0)) + Return(TMP1) + } + + If(LEqual(NDID,2)) + { + Name(TMP2,Package() {0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP2,0)) + Store(Or(0x10000,DID2),Index(TMP2,1)) + Return(TMP2) + } + + If(LEqual(NDID,3)) + { + Name(TMP3,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP3,0)) + Store(Or(0x10000,DID2),Index(TMP3,1)) + Store(Or(0x10000,DID3),Index(TMP3,2)) + Return(TMP3) + } + + If(LEqual(NDID,4)) + { + Name(TMP4,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP4,0)) + Store(Or(0x10000,DID2),Index(TMP4,1)) + Store(Or(0x10000,DID3),Index(TMP4,2)) + Store(Or(0x10000,DID4),Index(TMP4,3)) + Return(TMP4) + } + + If(LEqual(NDID,5)) + { + Name(TMP5,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP5,0)) + Store(Or(0x10000,DID2),Index(TMP5,1)) + Store(Or(0x10000,DID3),Index(TMP5,2)) + Store(Or(0x10000,DID4),Index(TMP5,3)) + Store(Or(0x10000,DID5),Index(TMP5,4)) + Return(TMP5) + } + + If(LEqual(NDID,6)) + { + Name(TMP6,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP6,0)) + Store(Or(0x10000,DID2),Index(TMP6,1)) + Store(Or(0x10000,DID3),Index(TMP6,2)) + Store(Or(0x10000,DID4),Index(TMP6,3)) + Store(Or(0x10000,DID5),Index(TMP6,4)) + Store(Or(0x10000,DID6),Index(TMP6,5)) + Return(TMP6) + } + + If(LEqual(NDID,7)) + { + Name(TMP7,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP7,0)) + Store(Or(0x10000,DID2),Index(TMP7,1)) + Store(Or(0x10000,DID3),Index(TMP7,2)) + Store(Or(0x10000,DID4),Index(TMP7,3)) + Store(Or(0x10000,DID5),Index(TMP7,4)) + Store(Or(0x10000,DID6),Index(TMP7,5)) + Store(Or(0x10000,DID7),Index(TMP7,6)) + Return(TMP7) + } + + If(LEqual(NDID,8)) + { + Name(TMP8,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP8,0)) + Store(Or(0x10000,DID2),Index(TMP8,1)) + Store(Or(0x10000,DID3),Index(TMP8,2)) + Store(Or(0x10000,DID4),Index(TMP8,3)) + Store(Or(0x10000,DID5),Index(TMP8,4)) + Store(Or(0x10000,DID6),Index(TMP8,5)) + Store(Or(0x10000,DID7),Index(TMP8,6)) + Store(Or(0x10000,DID8),Index(TMP8,7)) + Return(TMP8) + } + + If(LEqual(NDID,9)) + { + Name(TMP9,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMP9,0)) + Store(Or(0x10000,DID2),Index(TMP9,1)) + Store(Or(0x10000,DID3),Index(TMP9,2)) + Store(Or(0x10000,DID4),Index(TMP9,3)) + Store(Or(0x10000,DID5),Index(TMP9,4)) + Store(Or(0x10000,DID6),Index(TMP9,5)) + Store(Or(0x10000,DID7),Index(TMP9,6)) + Store(Or(0x10000,DID8),Index(TMP9,7)) + Store(Or(0x10000,DID9),Index(TMP9,8)) + Return(TMP9) + } + + If(LEqual(NDID,0x0A)) + { + Name(TMPA,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMPA,0)) + Store(Or(0x10000,DID2),Index(TMPA,1)) + Store(Or(0x10000,DID3),Index(TMPA,2)) + Store(Or(0x10000,DID4),Index(TMPA,3)) + Store(Or(0x10000,DID5),Index(TMPA,4)) + Store(Or(0x10000,DID6),Index(TMPA,5)) + Store(Or(0x10000,DID7),Index(TMPA,6)) + Store(Or(0x10000,DID8),Index(TMPA,7)) + Store(Or(0x10000,DID9),Index(TMPA,8)) + Store(Or(0x10000,DIDA),Index(TMPA,9)) + Return(TMPA) + } + + If(LEqual(NDID,0x0B)) + { + Name(TMPB,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMPB,0)) + Store(Or(0x10000,DID2),Index(TMPB,1)) + Store(Or(0x10000,DID3),Index(TMPB,2)) + Store(Or(0x10000,DID4),Index(TMPB,3)) + Store(Or(0x10000,DID5),Index(TMPB,4)) + Store(Or(0x10000,DID6),Index(TMPB,5)) + Store(Or(0x10000,DID7),Index(TMPB,6)) + Store(Or(0x10000,DID8),Index(TMPB,7)) + Store(Or(0x10000,DID9),Index(TMPB,8)) + Store(Or(0x10000,DIDA),Index(TMPB,9)) + Store(Or(0x10000,DIDB),Index(TMPB,10)) + Return(TMPB) + } + + If(LEqual(NDID,0x0C)) + { + Name(TMPC,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMPC,0)) + Store(Or(0x10000,DID2),Index(TMPC,1)) + Store(Or(0x10000,DID3),Index(TMPC,2)) + Store(Or(0x10000,DID4),Index(TMPC,3)) + Store(Or(0x10000,DID5),Index(TMPC,4)) + Store(Or(0x10000,DID6),Index(TMPC,5)) + Store(Or(0x10000,DID7),Index(TMPC,6)) + Store(Or(0x10000,DID8),Index(TMPC,7)) + Store(Or(0x10000,DID9),Index(TMPC,8)) + Store(Or(0x10000,DIDA),Index(TMPC,9)) + Store(Or(0x10000,DIDB),Index(TMPC,10)) + Store(Or(0x10000,DIDC),Index(TMPC,11)) + Return(TMPC) + } + + If(LEqual(NDID,0x0D)) + { + Name(TMPD,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMPD,0)) + Store(Or(0x10000,DID2),Index(TMPD,1)) + Store(Or(0x10000,DID3),Index(TMPD,2)) + Store(Or(0x10000,DID4),Index(TMPD,3)) + Store(Or(0x10000,DID5),Index(TMPD,4)) + Store(Or(0x10000,DID6),Index(TMPD,5)) + Store(Or(0x10000,DID7),Index(TMPD,6)) + Store(Or(0x10000,DID8),Index(TMPD,7)) + Store(Or(0x10000,DID9),Index(TMPD,8)) + Store(Or(0x10000,DIDA),Index(TMPD,9)) + Store(Or(0x10000,DIDB),Index(TMPD,10)) + Store(Or(0x10000,DIDC),Index(TMPD,11)) + Store(Or(0x10000,DIDD),Index(TMPD,12)) + Return(TMPD) + } + + If(LEqual(NDID,0x0E)) + { + Name(TMPE,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMPE,0)) + Store(Or(0x10000,DID2),Index(TMPE,1)) + Store(Or(0x10000,DID3),Index(TMPE,2)) + Store(Or(0x10000,DID4),Index(TMPE,3)) + Store(Or(0x10000,DID5),Index(TMPE,4)) + Store(Or(0x10000,DID6),Index(TMPE,5)) + Store(Or(0x10000,DID7),Index(TMPE,6)) + Store(Or(0x10000,DID8),Index(TMPE,7)) + Store(Or(0x10000,DID9),Index(TMPE,8)) + Store(Or(0x10000,DIDA),Index(TMPE,9)) + Store(Or(0x10000,DIDB),Index(TMPE,10)) + Store(Or(0x10000,DIDC),Index(TMPE,11)) + Store(Or(0x10000,DIDD),Index(TMPE,12)) + Store(Or(0x10000,DIDE),Index(TMPE,13)) + Return(TMPE) + } + + If(LEqual(NDID,0x0F)) + { + + Name(TMPF,Package() {0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF}) + Store(Or(0x10000,DID1),Index(TMPF,0)) + Store(Or(0x10000,DID2),Index(TMPF,1)) + Store(Or(0x10000,DID3),Index(TMPF,2)) + Store(Or(0x10000,DID4),Index(TMPF,3)) + Store(Or(0x10000,DID5),Index(TMPF,4)) + Store(Or(0x10000,DID6),Index(TMPF,5)) + Store(Or(0x10000,DID7),Index(TMPF,6)) + Store(Or(0x10000,DID8),Index(TMPF,7)) + Store(Or(0x10000,DID9),Index(TMPF,8)) + Store(Or(0x10000,DIDA),Index(TMPF,9)) + Store(Or(0x10000,DIDB),Index(TMPF,10)) + Store(Or(0x10000,DIDC),Index(TMPF,11)) + Store(Or(0x10000,DIDD),Index(TMPF,12)) + Store(Or(0x10000,DIDE),Index(TMPF,13)) + Store(Or(0x10000,DIDF),Index(TMPF,14)) + Return(TMPF) + } + + // If nothing else, return Unknown LFP. + // (Prevents compiler warning.) + + Return(Package() {0x00000400}) + } + + Device(DD01) + { + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID1),0x400)) + { + Store(0x1, EDPV) + Store(NXD1, NXDX) + Store(DID1, DIDX) + Return(1) + } + If(LEqual(DID1,0)) + { + Return(1) + } + Else + { + Return(And(0xFFFF,DID1)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + Return(CDDS(DID1)) + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD1) + } + Return(NDDS(DID1)) + } + + // Device Set State. + + // _DSS Table: + // + // BIT31 BIT30 Execution + // 0 0 Don't implement. + // 0 1 Cache change. Nothing to Implement. + // 1 0 Don't Implement. + // 1 1 Display Switch Complete. Implement. + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + + Device(DD02) + { + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID2),0x400)) + { + Store(0x2, EDPV) + Store(NXD2, NXDX) + Store(DID2, DIDX) + Return(2) + } + If(LEqual(DID2,0)) + { + Return(2) + } + Else + { + Return(And(0xFFFF,DID2)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(LIDS,0)) + { + Return(0x0) + } + + Return(CDDS(DID2)) + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + // Return the Next State. + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD2) + } + Return(NDDS(DID2)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + + Device(DD03) + { + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID3),0x400)) + { + Store(0x3, EDPV) + Store(NXD3, NXDX) + Store(DID3, DIDX) + Return(3) + } + If(LEqual(DID3,0)) + { + Return(3) + } + Else + { + Return(And(0xFFFF,DID3)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID3,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID3)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD3) + } + Return(NDDS(DID3)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + + Device(DD04) + { + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID4),0x400)) + { + Store(0x4, EDPV) + Store(NXD4, NXDX) + Store(DID4, DIDX) + Return(4) + } + If(LEqual(DID4,0)) + { + Return(4) + } + Else + { + Return(And(0xFFFF,DID4)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID4,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID4)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD4) + } + Return(NDDS(DID4)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + + + Device(DD05) + { + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID5),0x400)) + { + Store(0x5, EDPV) + Store(NXD5, NXDX) + Store(DID5, DIDX) + Return(5) + } + If(LEqual(DID5,0)) + { + Return(5) + } + Else + { + Return(And(0xFFFF,DID5)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID5,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID5)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD5) + } + Return(NDDS(DID5)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + + + Device(DD06) + { + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID6),0x400)) + { + Store(0x6, EDPV) + Store(NXD6, NXDX) + Store(DID6, DIDX) + Return(6) + } + If(LEqual(DID6,0)) + { + Return(6) + } + Else + { + Return(And(0xFFFF,DID6)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID6,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID6)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD6) + } + Return(NDDS(DID6)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + + + Device(DD07) + { + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID7),0x400)) + { + Store(0x7, EDPV) + Store(NXD7, NXDX) + Store(DID7, DIDX) + Return(7) + } + If(LEqual(DID7,0)) + { + Return(7) + } + Else + { + Return(And(0xFFFF,DID7)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID7,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID7)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD7) + } + Return(NDDS(DID7)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + + + Device(DD08) + { + + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID8),0x400)) + { + Store(0x8, EDPV) + Store(NXD8, NXDX) + Store(DID8, DIDX) + Return(8) + } + If(LEqual(DID8,0)) + { + Return(8) + } + Else + { + Return(And(0xFFFF,DID8)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID8,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID8)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DID8)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + + Store(NSTE,CSTE) + } + } + } + + Device(DD09) + { + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID9),0x400)) + { + Store(0x9, EDPV) + Store(NXD8, NXDX) + Store(DID9, DIDX) + Return(9) + } + If(LEqual(DID9,0)) + { + Return(9) + } + Else + { + Return(And(0xFFFF,DID9)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DID9,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID9)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DID9)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + Store(NSTE,CSTE) + } + } + } + + Device(DD0A) + { + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DIDA),0x400)) + { + Store(0xA, EDPV) + Store(NXD8, NXDX) + Store(DIDA, DIDX) + Return(0x0A) + } + If(LEqual(DIDA,0)) + { + Return(0x0A) + } + Else + { + Return(And(0xFFFF,DIDA)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DIDA,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DIDA)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DIDA)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + Store(NSTE,CSTE) + } + } + } + + Device(DD0B) + { + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DIDB),0x400)) + { + Store(0xB, EDPV) + Store(NXD8, NXDX) + Store(DIDB, DIDX) + Return(0X0B) + } + If(LEqual(DIDB,0)) + { + Return(0x0B) + } + Else + { + Return(And(0xFFFF,DIDB)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DIDB,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DIDB)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DIDB)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + Store(NSTE,CSTE) + } + } + } + + Device(DD0C) + { + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DIDC),0x400)) + { + Store(0xC, EDPV) + Store(NXD8, NXDX) + Store(DIDC, DIDX) + Return(0X0C) + } + If(LEqual(DIDC,0)) + { + Return(0x0C) + } + Else + { + Return(And(0xFFFF,DIDC)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DIDC,0)) + { + Return(0x0C) + } + Else + { + Return(CDDS(DIDC)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DIDC)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + Store(NSTE,CSTE) + } + } + } + + Device(DD0D) + { + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DIDD),0x400)) + { + Store(0xD, EDPV) + Store(NXD8, NXDX) + Store(DIDD, DIDX) + Return(0X0D) + } + If(LEqual(DIDD,0)) + { + Return(0x0D) + } + Else + { + Return(And(0xFFFF,DIDD)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DIDD,0)) + { + Return(0x0D) + } + Else + { + Return(CDDS(DIDD)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DIDD)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + Store(NSTE,CSTE) + } + } + } + + Device(DD0E) + { + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DIDE),0x400)) + { + Store(0xE, EDPV) + Store(NXD8, NXDX) + Store(DIDE, DIDX) + Return(0X0E) + } + If(LEqual(DIDE,0)) + { + Return(0x0E) + } + Else + { + Return(And(0xFFFF,DIDE)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DIDE,0)) + { + Return(0x0E) + } + Else + { + Return(CDDS(DIDE)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DIDE)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + Store(NSTE,CSTE) + } + } + } + + Device(DD0F) + { + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DIDF),0x400)) + { + Store(0xF, EDPV) + Store(NXD8, NXDX) + Store(DIDF, DIDX) + Return(0X0F) + } + If(LEqual(DIDF,0)) + { + Return(0x0F) + } + Else + { + Return(And(0xFFFF,DIDF)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(DIDC,0)) + { + Return(0x0F) + } + Else + { + Return(CDDS(DIDF)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DIDF)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + Store(NSTE,CSTE) + } + } + } + +//device for eDP + Device(DD1F) + { + // Return Unique ID. + + Method(_ADR,0,Serialized) + { + If(LEqual(EDPV, 0x0)) + { + Return(0x1F) + } + Else + { + Return(And(0xFFFF,DIDX)) + } + } + + // Return the Current Status. + + Method(_DCS,0) + { + If(LEqual(EDPV, 0x0)) + { + Return(0x00) + } + Else + { + Return(CDDS(DIDX)) + } + } + + // Query Graphics State (active or inactive). + + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXDX) + } + Return(NDDS(DIDX)) + } + + // Device Set State. (See table above.) + + Method(_DSS,1) + { + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // State change was performed by the + // Video Drivers. Simply update the + // New State. + Store(NSTE,CSTE) + } + } + // Query List of Brightness Control Levels Supported. + + Method(_BCL,0) + { + // List of supported brightness levels in the following sequence. + + // Level when machine has full power. + // Level when machine is on batteries. + // Other supported levels. + Return(Package(){80, 50, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100}) + } + + // Set the Brightness Level. + + Method (_BCM,1) + { + // Set the requested level if it is between 0 and 100%. + + If(LAnd(LGreaterEqual(Arg0,0),LLessEqual(Arg0,100))) + { + \_SB.PCI0.GFX0.AINT(1, Arg0) + Store(Arg0,BRTL) // Store Brightness Level. + } + } + + // Brightness Query Current level. + + Method (_BQC,0) + { + Return(BRTL) + } + } + + Method(SDDL,1) + { + Increment(NDID) + Store(And(Arg0,0xF0F),Local0) + Or(0x80000000,Local0, Local1) + If(LEqual(DIDL,Local0)) + { + Return(Local1) + } + If(LEqual(DDL2,Local0)) + { + Return(Local1) + } + If(LEqual(DDL3,Local0)) + { + Return(Local1) + } + If(LEqual(DDL4,Local0)) + { + Return(Local1) + } + If(LEqual(DDL5,Local0)) + { + Return(Local1) + } + If(LEqual(DDL6,Local0)) + { + Return(Local1) + } + If(LEqual(DDL7,Local0)) + { + Return(Local1) + } + If(LEqual(DDL8,Local0)) + { + Return(Local1) + } + If(LEqual(DDL9,Local0)) + { + Return(Local1) + } + If(LEqual(DD10,Local0)) + { + Return(Local1) + } + If(LEqual(DD11,Local0)) + { + Return(Local1) + } + If(LEqual(DD12,Local0)) + { + Return(Local1) + } + If(LEqual(DD13,Local0)) + { + Return(Local1) + } + If(LEqual(DD14,Local0)) + { + Return(Local1) + } + If(LEqual(DD15,Local0)) + { + Return(Local1) + } + Decrement(NDID) // AMI_OVERRIDE + Return(0) + } + + Method(CDDS,1) + { + Store(And(Arg0,0xF0F),Local0) + + If(LEqual(0, Local0)) + { + Return(0x1D) + } + If(LEqual(CADL, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL2, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL3, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL4, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL5, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL6, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL7, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL8, Local0)) + { + Return(0x1F) + } + Return(0x1D) + } + + Method(NDDS,1) + { + Store(And(Arg0,0xF0F),Local0) + + If(LEqual(0, Local0)) + { + Return(0) + } + If(LEqual(NADL, Local0)) + { + Return(1) + } + If(LEqual(NDL2, Local0)) + { + Return(1) + } + If(LEqual(NDL3, Local0)) + { + Return(1) + } + If(LEqual(NDL4, Local0)) + { + Return(1) + } + If(LEqual(NDL5, Local0)) + { + Return(1) + } + If(LEqual(NDL6, Local0)) + { + Return(1) + } + If(LEqual(NDL7, Local0)) + { + Return(1) + } + If(LEqual(NDL8, Local0)) + { + Return(1) + } + Return(0) + } + + // Include IGD OpRegion/Software SCI interrupt handler which is use by + // the graphics drivers to request data from system BIOS. + + include ("IgdOpRn.ASL") +// +// iGfx WA for HSW. Exclude the memory range 20000000-201FFFFF (2MB) and 0x40004000-0x40004FFF (4KB +// +Device(\_SB.MEM2) +{ + Name(_HID, EISAID("PNP0C01")) // Hardware Device ID + Name(_UID, 2) + + Name(CRS2, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0x20000000, 0x00200000) + Memory32Fixed (ReadWrite, 0x40004000, 0x00001000) + }) + + Method(_STA,0) + { + If(IGDS) + { + If (LEqual(PNHM,0x000306C1)) + { + Return(0xF) // then enabled + } + } + Return(0) // then disabled + } + + Method (_CRS, 0) + { + Return(CRS2) + } + +} diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOGBDA.ASL b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOGBDA.ASL new file mode 100644 index 0000000..e28ce5c --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOGBDA.ASL @@ -0,0 +1,164 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + + +Module Name: + + IgdOGBDA.ASL + +Abstract: + + IGD OpRegion/Software SCI Reference Code. + This file contains Get BIOS Data Area funciton support for + the Integrated Graphics Device (IGD) OpRegion/Software SCI mechanism. + +--*/ + + +Method (GBDA, 0, Serialized) +{ + + // Supported calls: Sub-function 0 + + If (LEqual(GESF, 0)) + { + //<TODO> Update implementation specific supported calls. Reference + // code is set to Intel's validated implementation. + + Store(0x0000659, PARM) + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Success + } + + // Requested callbacks: Sub-function 1 + + If (LEqual(GESF, 1)) + { + + //<TODO> Update implementation specific system BIOS requested call + // back functions. Call back functions are where the driver calls the + // system BIOS at function indicated event. + + Store(0x300482, PARM) + If(LEqual(S0ID, One)){ + Or(PARM, 0x100, PARM) //Request Fn 8 callback in CS systems + } + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Success + } + + // Get Boot display Preferences: Sub-function 4 + + If (LEqual(GESF, 4)) + { + + //<TODO> Update the implementation specific Get Boot Display + // Preferences function. + + And(PARM, 0xEFFF0000, PARM) // PARM[30:16] = Boot device ports + And(PARM, ShiftLeft(DeRefOf(Index(DBTB, IBTT)), 16), PARM) + Or(IBTT, PARM, PARM) // PARM[7:0] = Boot device type + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Success + } + + // Panel details: Sub-function 5 + + If (LEqual(GESF, 5)) + { + + //<TODO> Update the implementation specific Get Panel Details + // function. + + Store(IPSC, PARM) // Report the scaling setting + Or(PARM, ShiftLeft(IPAT, 8), PARM) + Add(PARM, 0x100, PARM) // Adjust panel type, 0 = VBT default + Or(PARM, ShiftLeft(LIDS, 16), PARM) // Report the lid state + Add(PARM, 0x10000, PARM) // Adjust the lid state, 0 = Unknown + Or(PARM, ShiftLeft(IBIA, 20), PARM) // Report the BIA setting + Store(Zero, GESF) + Return(SUCC) + } + + // Internal graphics: Sub-function 7 + + If (LEqual(GESF, 7)) + { + Store(GIVD, PARM) // PARM[0] - VGA mode(1=VGA) + Xor(PARM, 1, PARM) // Invert the VGA mode polarity + Or(PARM, ShiftLeft(GMFN, 1), PARM) // PARM[1] - # IGD PCI functions-1 + // PARM[3:2] - Reserved + // PARM[4] - IGD D3 support(0=cold) + // PARM[10:5] - Reserved + Or(PARM, ShiftLeft(3, 11), PARM) // PARM[12:11] - DVMT mode(11b = 5.0) + + // + // Report DVMT 5.0 Total Graphics memory size. + // + Or(PARM, ShiftLeft(IDMS, 17), PARM) // Bits 20:17 are for Gfx total memory size + + // If the "Set Internal Graphics" call is supported, the modified + // settings flag must be programmed per the specification. This means + // that the flag must be set to indicate that system BIOS requests + // these settings. Once "Set Internal Graphics" is called, the + // modified settings flag must be cleared on all subsequent calls to + // this function. + + // Report the graphics frequency based on B0:D2:F0:RF0h[12]. Must + // take into account the current VCO. + + Or(ShiftLeft(Derefof(Index(Derefof(Index(CDCT, HVCO)), CDVL)), 21),PARM, PARM) + + Store(1, GESF) // Set the modified settings flag + Return(SUCC) + } + + // Spread spectrum clocks: Sub-function 10 + + If (LEqual(GESF, 10)) + { + + Store(0, PARM) // Assume SSC is disabled + + If(ISSC) + { + Or(PARM, 3, PARM) // If SSC enabled, return SSC1+Enabled + } + + Store(0, GESF) // Set the modified settings flag + Return(SUCC) // Success + } + + + If (LEqual(GESF, 11)) + { + Store(KSV0, PARM) // First four bytes of AKSV + Store(KSV1, GESF) // Fifth byte of AKSV + + Return(SUCC) // Success + } + + // A call to a reserved "Get BIOS data" function was received. + + Store(Zero, GESF) // Clear the exit parameter + Return(CRIT) // Reserved, "Critical failure" +} diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOMOBF.ASL b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOMOBF.ASL new file mode 100644 index 0000000..07a716b --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOMOBF.ASL @@ -0,0 +1,560 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + + +Module Name: + + IgdOMOBF.ASL + +Abstract: + + IGD OpRegion/Software SCI Reference Code. + This file contains ASL code with the purpose of handling events + i.e. hotkeys and other system interrupts. + +--*/ + + +// Notes: +// 1. The following routines are to be called from the appropriate event +// handlers. +// 2. This code cannot comprehend the exact implementation in the OEM's BIOS. +// Therefore, an OEM must call these methods from the existing event +// handler infrastructure. Details on when/why to call each method is +// included in the method header under the "usage" section. + + +/************************************************************************; +;* ACPI Notification Methods +;************************************************************************/ + + +/************************************************************************; +;* +;* Name: PDRD +;* +;* Description: Check if the graphics driver is ready to process +;* notifications and video extensions. +;* +;* Usage: This method is to be called prior to performing any +;* notifications or handling video extensions. +;* Ex: If (PDRD()) {Return (FAIL)} +;* +;* Input: None +;* +;* Output: None +;* +;* References: DRDY (Driver ready status), ASLP (Driver recommended +;* sleep timeout value). +;* +;************************************************************************/ + +External(HNOT, MethodObj) + +Method(PDRD) +{ + + // Sleep for ASLP milliseconds if the driver is not ready. + + + // If DRDY is clear, the driver is not ready. If the return value is + // !=0, do not perform any notifications or video extension handling. + + Return(LNot(DRDY)) +} + + +/************************************************************************; +;* +;* Name: PSTS +;* +;* Description: Check if the graphics driver has completed the previous +;* "notify" command. +;* +;* Usage: This method is called before every "notify" command. A +;* "notify" should only be set if the driver has completed the +;* previous command. Else, ignore the event and exit the parent +;* method. +;* Ex: If (PSTS()) {Return (FAIL)} +;* +;* Input: None +;* +;* Output: None +;* +;* References: CSTS (Notification status), ASLP (Driver recommended sleep +;* timeout value). +;* +;************************************************************************/ + +Method(PSTS) +{ + If(LGreater(CSTS, 2)) + { + // Sleep for ASLP milliseconds if the status is not "success, + // failure, or pending" + // + Sleep(ASLP) + } + + Return(LEqual(CSTS, 3)) // Return True if still Dispatched +} + + +/************************************************************************; +;* +;* Name: GNOT +;* +;* Description: Call the appropriate methods to query the graphics driver +;* status. If all methods return success, do a notification of +;* the graphics device. +;* +;* Usage: This method is to be called when a graphics device +;* notification is required (display switch hotkey, etc). +;* +;* Input: Arg0 = Current event type: +;* 1 = display switch +;* 2 = lid +;* 3 = dock +;* Arg1 = Notification type: +;* 0 = Re-enumeration +;* 0x80 = Display switch +;* +;* Output: Returns 0 = success, 1 = failure +;* +;* References: PDRD and PSTS methods. OSYS (OS version) +;* +;************************************************************************/ + +Method(GNOT, 2) +{ + // Check for 1. Driver loaded, 2. Driver ready. + // If any of these cases is not met, skip this event and return failure. + // + If(PDRD()) + { + Return(0x1) // Return failure if driver not loaded. + } + + Store(Arg0, CEVT) // Set up the current event value + Store(3, CSTS) // CSTS=BIOS dispatched an event + + If(LAnd(LEqual(CHPD, 0), LEqual(Arg1, 0))) // Do not re-enum if driver supports hotplug + { + If(LOr(LGreater(OSYS, 2000), LLess(OSYS, 2006))) + { + // + // WINXP requires that the entire PCI Bridge be re-enumerated. + // + Notify(\_SB.PCI0, Arg1) + } + Else + { + // + // Re-enumerate the Graphics Device for non-XP operating systems. + // + Notify(\_SB.PCI0.GFX0, Arg1) + } + } + + If(CondRefOf(HNOT)) + { + HNOT(Arg0) //Notification handler for Switchable graphics + } + Else + { + Notify(\_SB.PCI0.GFX0,0x80) + } + + Return(0x0) // Return success +} + + +/************************************************************************; +;* +;* Name: GHDS +;* +;* Description: Handle a hotkey display switching event (performs a +;* Notify(GFX0, 0). +;* +;* Usage: This method must be called when a hotkey event occurs and the +;* purpose of that hotkey is to do a display switch. +;* +;* Input: Arg0 = Toggle table number. +;* +;* Output: Returns 0 = success, 1 = failure. +;* CEVT and TIDX are indirect outputs. +;* +;* References: TIDX, GNOT +;* +;************************************************************************/ + +Method(GHDS, 1) +{ + Store(Arg0, TIDX) // Store the table number + + // Call GNOT for CEVT = 1 = hotkey, notify value = 0 + + Return(GNOT(1, 0)) // Return stats from GNOT +} + + +/************************************************************************; +;* +;* Name: GLID +;* +;* Description: Handle a lid event (performs the Notify(GFX0, 0), but not the +;* lid notify). +;* +;* Usage: This method must be called when a lid event occurs. A +;* Notify(LID0, 0x80) must follow the call to this method. +;* +;* Input: Arg0 = Lid state: +;* 0 = All closed +;* 1 = internal LFP lid open +;* 2 = external lid open +;* 3 = both external and internal open +;* +;* Output: Returns 0=success, 1=failure. +;* CLID and CEVT are indirect outputs. +;* +;* References: CLID, GNOT +;* +;************************************************************************/ + +Method(GLID, 1) +{ + + If (LEqual(Arg0,1)) + { + Store(3,CLID) + } + Else + { + Store(Arg0, CLID) + } + + //Store(Arg0, CLID) // Store the current lid state + + // Call GNOT for CEVT=2=Lid, notify value = 0 + + if (GNOT(2, 0)) { + Or (CLID, 0x80000000, CLID) + Return (1) // Return Fail + } + + Return (0) // Return Pass +} + + +/************************************************************************; +;* +;* Name: GDCK +;* +;* Description: Handle a docking event by updating the current docking status +;* and doing a notification. +;* +;* Usage: This method must be called when a docking event occurs. +;* +;* Input: Arg0 = Docking state: +;* 0 = Undocked +;* 1 = Docked +;* +;* Output: Returns 0=success, 1=failure. +;* CDCK and CEVT are indirect outputs. +;* +;* References: CDCK, GNOT +;* +;************************************************************************/ + +Method(GDCK, 1) +{ + Store(Arg0, CDCK) // Store the current dock state + + // Call GNOT for CEVT=4=Dock, notify value = 0 + + Return(GNOT(4, 0)) // Return stats from GNOT +} + + +/************************************************************************; +;* ASLE Interrupt Methods +;************************************************************************/ + + +/************************************************************************; +;* +;* Name: PARD +;* +;* Description: Check if the driver is ready to handle ASLE interrupts +;* generate by the system BIOS. +;* +;* Usage: This method must be called before generating each ASLE +;* interrupt. +;* +;* Input: None +;* +;* Output: Returns 0 = success, 1 = failure. +;* +;* References: ARDY (Driver readiness), ASLP (Driver recommended sleep +;* timeout value) +;* +;************************************************************************/ + +Method(PARD) +{ + If(LNot(ARDY)) + { + + // Sleep for ASLP milliseconds if the driver is not ready. + + Sleep(ASLP) + } + + // If ARDY is clear, the driver is not ready. If the return value is + // !=0, do not generate the ASLE interrupt. + + Return(LNot(ARDY)) +} + +// +// Intel Ultrabook Event Handler. Arg0 represents the Ultrabook Event Bit # to pass +// to the Intel Graphics Driver. Note that this is a serialized method, meaning +// sumultaneous events are not allowed. +// + +Method(IUEH,1,Serialized) +{ + And(IUER,0xC0,IUER) // Clear all button events on entry. + XOr(IUER,Shiftleft(1,Arg0),IUER) // Toggle status. + + If(LLessEqual(Arg0,4)) // Button Event? + { + Return(AINT(5,0)) // Generate event and return status. + + } + Else // Indicator Event. + { + Return(AINT(Arg0,0)) // Generate event and return status. + } +} + +/************************************************************************; +;* +;* Name: AINT +;* +;* Description: Call the appropriate methods to generate an ASLE interrupt. +;* This process includes ensuring the graphics driver is ready +;* to process the interrupt, ensuring the driver supports the +;* interrupt of interest, and passing information about the event +;* to the graphics driver. +;* +;* Usage: This method must called to generate an ASLE interrupt. +;* +;* Input: Arg0 = ASLE command function code: +;* 0 = Set ALS illuminance +;* 1 = Set backlight brightness +;* 2 = Do Panel Fitting +;* 4 = Reserved +;* 5 = Button Indicator Event +;* 6 = Convertible Indicator Event +;* 7 = Docking Indicator Event +;* Arg1 = If Arg0 = 0, current ALS reading: +;* 0 = Reading below sensor range +;* 1-0xFFFE = Current sensor reading +;* 0xFFFF = Reading above sensor range +;* Arg1 = If Arg0 = 1, requested backlight percentage +;* +;* Output: Returns 0 = success, 1 = failure +;* +;* References: PARD method. +;* +;************************************************************************/ + +Method(AINT, 2) +{ + + // Return failure if the requested feature is not supported by the + // driver. + + If(LNot(And(TCHE, ShiftLeft(1, Arg0)))) + { + Return(0x1) + } + + // Return failure if the driver is not ready to handle an ASLE + // interrupt. + + If(PARD()) + { + Return(0x1) + } + + // Handle Intel Ultrabook Events. + + If(LAnd(LGreaterEqual(Arg0,5),LLessEqual(Arg0,7))) + { + Store(ShiftLeft(1,Arg0), ASLC) // Set Ultrbook Event [6:4]. + Store(0x01, ASLE) // Generate ASLE interrupt + + Store(0,Local2) // Use Local2 as a timeout counter. Intialize to zero. + + While(LAnd(LLess(Local2,250),LNotEqual(ASLC,0))) // Wait 1 second or until Driver ACKs a success. + { + Sleep(4) // Delay 4 ms. + Increment(Local2) // Increment Timeout. + } + + Return(0) // Return success + } + + // Evaluate the first argument (Panel fitting, backlight brightness, or ALS). + + If(LEqual(Arg0, 2)) // Arg0 = 2, so request a panel fitting mode change. + { + If(CPFM) // If current mode field is non-zero use it. + { + And(CPFM, 0x0F, Local0) // Create variables without reserved + And(EPFM, 0x0F, Local1) // or valid bits. + + If(LEqual(Local0, 1)) // If current mode is centered, + { + If(And(Local1, 6)) // and if stretched is enabled, + { + Store(6, PFIT) // request stretched. + } + Else // Otherwise, + { + If(And(Local1, 8)) // if aspect ratio is enabled, + { + Store(8, PFIT) // request aspect ratio. + } + Else // Only centered mode is enabled + { + Store(1, PFIT) // so request centered. (No change.) + } + } + } + If(LEqual(Local0, 6)) // If current mode is stretched, + { + If(And(Local1, 8)) // and if aspect ratio is enabled, + { + Store(8, PFIT) // request aspect ratio. + } + Else // Otherwise, + { + If(And(Local1, 1)) // if centered is enabled, + { + Store(1, PFIT) // request centered. + } + Else // Only stretched mode is enabled + { + Store(6, PFIT) // so request stretched. (No change.) + } + } + } + If(LEqual(Local0, 8)) // If current mode is aspect ratio, + { + If(And(Local1, 1)) // and if centered is enabled, + { + Store(1, PFIT) // request centered. + } + Else // Otherwise, + { + If(And(Local1, 6)) // if stretched is enabled, + { + Store(6, PFIT) // request stretched. + } + Else // Only aspect ratio mode is enabled + { + Store(8, PFIT) // so request aspect ratio. (No change.) + } + } + } + } + + // The following code for panel fitting (within the Else condition) is retained for backward compatiblity. + + Else // If CFPM field is zero use PFIT and toggle the + { + Xor(PFIT,7,PFIT) // mode setting between stretched and centered only. + } + + Or(PFIT,0x80000000,PFIT) // Set the valid bit for all cases. + + Store(4, ASLC) // Store "Panel fitting event" to ASLC[31:1] + } + Else + { + If(LEqual(Arg0, 1)) // Arg0=1, so set the backlight brightness. + { + Store(Divide(Multiply(Arg1, 255), 100), BCLP) // Convert from percent to 0-255. + + Or(BCLP, 0x80000000, BCLP) // Set the valid bit. + + Store(2, ASLC) // Store "Backlight control event" to ASLC[31:1] + } + Else + { + If(LEqual(Arg0, 0)) // Arg0=0, so set the ALS illuminace + { + Store(Arg1, ALSI) + + Store(1, ASLC) // Store "ALS event" to ASLC[31:1] + } + Else + { + Return(0x1) // Unsupported function + } + } + } + + Store(0x01, ASLE) // Generate ASLE interrupt + Return(0x0) // Return success +} + + +/************************************************************************; +;* +;* Name: SCIP +;* +;* Description: Checks the presence of the OpRegion and SCI +;* +;* Usage: This method is called before other OpRegion methods. The +;* former "GSMI True/False is not always valid. This method +;* checks if the OpRegion Version is non-zero and if non-zero, +;* (present and readable) then checks the GSMI flag. +;* +;* Input: None +;* +;* Output: Boolean True = SCI present. +;* +;* References: None +;* +;************************************************************************/ + +Method(SCIP) +{ + If(LNotEqual(OVER,0)) // If OpRegion Version not 0. + { + Return(LNot(GSMI)) // Return True if SCI. + } + + Return(0) // Else Return False. +} diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOSBCB.ASL b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOSBCB.ASL new file mode 100644 index 0000000..9cb0db6 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOSBCB.ASL @@ -0,0 +1,335 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + + +Module Name: + + IgdOSBCB.ASL + +Abstract: + + This file contains the system BIOS call back functionality for the + OpRegion/Software SCI mechanism. + +--*/ + + +Method (SBCB, 0, Serialized) +{ + + // Supported Callbacks: Sub-function 0 + + If (LEqual(GESF, 0x0)) + { + + //<TODO> An OEM may support the driver->SBIOS status callbacks, but + // the supported callbacks value must be modified. The code that is + // executed upon reception of the callbacks must be also be updated + // to perform the desired functionality. + + Store(0x00000000, PARM) // No callbacks supported + //Store(0x000787FD, PARM) // Used for Intel test implementaion + + // <NOTSAMPLECODE> + + Store(0x000F87DD, PARM) + + // </NOTSAMPLECODE> + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // "Success" + } + + // BIOS POST Completion: Sub-function 1 + + If (LEqual(GESF, 1)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Pre-Hires Set Mode: Sub-function 3 + + If (LEqual(GESF, 3)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Post-Hires Set Mode: Sub-function 4 + + If (LEqual(GESF, 4)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Display Switch: Sub-function 5 + + If (LEqual(GESF, 5)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Adapter Power State: Sub-function 7 + + If (LEqual(GESF, 7)) + { + // + // Handle Low Power S0 Idle Capability if enabled + // + If(LEqual(S0ID, One)){ + // + // Call GUAM to trigger CS Entry + // If Adapter Power State Notification = D1 (PARM[7:0]=0x01) + // + If (LEqual (And(PARM,0xFF), 0x01)) { + // GUAM - Global User Absent Mode Notification Method + \GUAM(One) // 0x01 - Power State Standby (CS Entry) + } + } + + // Upon notification from driver that the Adapter Power State = D0, + // check if previous lid event failed. If it did, retry the lid + // event here. + If(LEqual(PARM, 0)) + { + Store(CLID, Local0) + If(And(0x80000000,Local0)) + { + And(CLID, 0x0000000F, CLID) + GLID(CLID) + } + } + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Display Power State: Sub-function 8 + + If (LEqual(GESF, 8)) + { + // + // Handle Low Power S0 Idle Capability if enabled + // + If(LEqual(S0ID, One)){ + // Bits [15:8] - Power State + // 00h = On + // 01h = Standby + // 02h = Suspend + // 04h = Off + // 08h = Reduced On + Store(And(ShiftRight(PARM, 8), 0xFF), Local0) + // + // Call GUAM + // If Display Turn ON Notification (PARM [15:8] == 0) for CS Exit + // + If (LEqual (Local0, 0)) { + // GUAM - Global User Absent Mode Notification Method + \GUAM(Zero) // 0x00 - Power State On (CS Exit) + } + } + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Set Boot Display: Sub-function 9 + + If (LEqual(GESF, 9)) + { + + //<TODO> An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is Intel + // validated implementation. + + And(PARM, 0xFF, IBTT) // Save the boot display to NVS + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Reserved, "Critical failure" + } + + // Set Panel Details: Sub-function 10 (0Ah) + + If (LEqual(GESF, 10)) + { + + //<TODO> An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is Intel + // validated implementation. + + // Set the panel-related NVRAM variables based the input from the driver. + + And(PARM, 0xFF, IPSC) + + // Change panel type if a change is requested by the driver (Change if + // panel type input is non-zero). Zero=No change requested. + + If(And(ShiftRight(PARM, 8), 0xFF)) + { + And(ShiftRight(PARM, 8), 0xFF, IPAT) + Decrement(IPAT) // 0 = no change, so fit to CMOS map + } + And(ShiftRight(PARM, 20), 0x7, IBIA) + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Success + } + + // Set Internal Graphics: Sub-function 11 (0Bh) + + If (LEqual(GESF, 11)) + { + + //<TODO> An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is Intel + // validated implementation. + + And(ShiftRight(PARM, 1), 1, IF1E) // Program the function 1 option + + If(And(PARM, ShiftLeft(0xF, 13))) // Use fixed memory if fixed size != 0 + { + + // Fixed memory + + And(ShiftRight(PARM, 13), 0xF, IDMS) // Program fixed memory size + } + Else + { + + // DVMT memory + + And(ShiftRight(PARM, 17), 0xF, IDMS) // Program fixed memory size + } + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Success + } + + // Post-Hires to DOS FS: Sub-function 16 (10h) + + If (LEqual(GESF, 16)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // APM Complete: Sub-function 17 (11h) + + If (LEqual(GESF, 17)) + { + + Store(ShiftLeft(LIDS, 8), PARM) // Report the lid state + Add(PARM, 0x100, PARM) // Adjust the lid state, 0 = Unknown + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Not supported, but no failure + } + + // Set Spread Spectrum Clocks: Sub-function 18 (12h) + + If (LEqual(GESF, 18)) + { + + //<TODO> An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is Intel + // validated implementation. + + If(And(PARM, 1)) + { + If(LEqual(ShiftRight(PARM, 1), 1)) + { + Store(1, ISSC) // Enable HW SSC, only for clock 1 + } + Else + { + Store(Zero, GESF) + Return(CRIT) // Failure, as the SSC clock must be 1 + } + } + Else + { + Store(0, ISSC) // Disable SSC + } + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Success + } + + // Post VBE/PM Callback: Sub-function 19 (13h) + + If (LEqual(GESF, 19)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + + // Set PAVP Data: Sub-function 20 (14h) + + If (LEqual(GESF, 20)) + { + And(PARM, 0xF, PAVP) // Store PAVP info + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Success + } + + // Enable/Disable Audio: Sub-function 21 (15h) + + If (LEqual(GESF, 21)) + { + If(LEqual(PARM,1)) + { + OR (\_SB.PCI0.AUDE, 0x20,\_SB.PCI0.AUDE) + \_SB.PCI0.B0D3.ABWA (1) + \_SB.PCI0.B0D3.ARST () + \_SB.PCI0.B0D3.ASTR () + \_SB.PCI0.B0D3.AINI () + \_SB.PCI0.B0D3.CXDC () + \_SB.PCI0.B0D3.ABWA (0) + Notify(\_SB.PCI0,0) + } + If(LEqual(PARM,0)) + { + AND (\_SB.PCI0.AUDE, 0xDF,\_SB.PCI0.AUDE) + Notify(\_SB.PCI0,0) + } + Store(Zero, GESF) + Store(Zero, PARM) + Return(SUCC) + } + + // A call to a reserved "System BIOS callbacks" function was received + + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Reserved, "Critical failure" +} diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOpRn.ASL b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOpRn.ASL new file mode 100644 index 0000000..56d3f71 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/IgdOpRn.ASL @@ -0,0 +1,342 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + + +Module Name: + + IgdOpRn.ASL + +Abstract: + + IGD OpRegion/Software SCI Reference Code. + This file contains the interrupt handler code for the Integrated + Graphics Device (IGD) OpRegion/Software SCI mechanism. + +--*/ + + +//NOTES: +// +// (1) The code contained in this file inherits the scope in which it +// was included. So BIOS developers must be sure to include this +// file in the scope associated with the graphics device +// (ex. \_SB.PCI0.GFX0). +// (2) Create a _L06 method under the GPE scope to handle the event +// generated by the graphics driver. The _L06 method must call +// the GSCI method in this file. +// (3) The MCHP operation region assumes that _ADR and _BBN names +// corresponding to bus 0, device0, function 0 have been declared +// under the PCI0 scope. +// (4) Before the first execution of the GSCI method, the base address +// of the GMCH SCI OpRegion must be programmed where the driver can +// access it. A 32bit scratch register at 0xFC in the IGD PCI +// configuration space (B0/D2/F0/R0FCh) is used for this purpose. + +// Define an OperationRegion to cover the GMCH PCI configuration space as +// described in the IGD OpRegion specificiation. + +Scope(\_SB.PCI0) +{ + OperationRegion(MCHP, PCI_Config, 0x40, 0xC0) + Field(MCHP, AnyAcc, NoLock, Preserve) + { + Offset(0x14), + AUDE, 8, + + Offset(0x60), // Top of Memory register + TASM, 10, // Total system memory (64MB gran) + , 6, + } +} + +// Define an OperationRegion to cover the IGD PCI configuration space as +// described in the IGD OpRegion specificiation. + +OperationRegion(IGDP, PCI_Config, 0x40, 0xC0) +Field(IGDP, AnyAcc, NoLock, Preserve) +{ + Offset(0x12), // Mirror of gfx control reg + , 1, + GIVD, 1, // IGD VGA disable bit + , 2, + GUMA, 3, // Stolen memory size + , 9, + Offset(0x14), + , 4, + GMFN, 1, // Gfx function 1 enable + , 27, + Offset(0xA4), + ASLE, 8, // Reg 0xE4, ASLE interrupt register + , 24, // Only use first byte of ASLE reg + Offset(0xA8), // Reg 0xE8, SWSCI control register + GSSE, 1, // Graphics SCI event (1=event pending) + GSSB, 14, // Graphics SCI scratchpad bits + GSES, 1, // Graphics event select (1=SCI) + Offset(0xB0), // Gfx Clk Frequency and Gating Control + , 12, + CDVL, 1, // Core display clock value + , 3, // Graphics Core Display Clock Select + Offset(0xB5), + LBPC, 8, // Legacy brightness control + Offset(0xBC), + ASLS, 32, // Reg 0xFC, Address of the IGD OpRegion +} + +// Define an OperationRegion to cover the IGD OpRegion layout. + +OperationRegion(IGDM, SystemMemory, ASLB, 0x2000) +Field(IGDM, AnyAcc, NoLock, Preserve) +{ + + // OpRegion Header + + SIGN, 128, // Signature-"IntelGraphicsMem" + SIZE, 32, // OpRegion Size + OVER, 32, // OpRegion Version + SVER, 256, // System BIOS Version + VVER, 128, // VBIOS Version + GVER, 128, // Driver version + MBOX, 32, // Mailboxes supported + DMOD, 32, // Driver Model + PCON, 32, // Platform Configuration + DVER, 64, // GOP Version + // OpRegion Mailbox 1 (Public ACPI Methods) + // Note: Mailbox 1 is normally reserved for desktop platforms. + + Offset(0x100), + DRDY, 32, // Driver readiness (ACPI notification) + CSTS, 32, // Notification status + CEVT, 32, // Current event + Offset(0x120), + DIDL, 32, // Supported display device ID list + DDL2, 32, // Allows for 8 devices + DDL3, 32, + DDL4, 32, + DDL5, 32, + DDL6, 32, + DDL7, 32, + DDL8, 32, + CPDL, 32, // Currently present display list + CPL2, 32, // Allows for 8 devices + CPL3, 32, + CPL4, 32, + CPL5, 32, + CPL6, 32, + CPL7, 32, + CPL8, 32, + CADL, 32, // Currently active display list + CAL2, 32, // Allows for 8 devices + CAL3, 32, + CAL4, 32, + CAL5, 32, + CAL6, 32, + CAL7, 32, + CAL8, 32, + NADL, 32, // Next active display list + NDL2, 32, // Allows for 8 devices + NDL3, 32, + NDL4, 32, + NDL5, 32, + NDL6, 32, + NDL7, 32, + NDL8, 32, + ASLP, 32, // ASL sleep timeout + TIDX, 32, // Toggle table index + CHPD, 32, // Current hot plug enable indicator + CLID, 32, // Current lid state indicator + CDCK, 32, // Current docking state indicator + SXSW, 32, // Display switch notify on resume + EVTS, 32, // Events supported by ASL (diag only) + CNOT, 32, // Current OS notifications (diag only) + NRDY, 32, + // Extended DIDL list + DDL9, 32, + DD10, 32, + DD11, 32, + DD12, 32, + DD13, 32, + DD14, 32, + DD15, 32, + //Extended Currently attached Display Device List CPD2 + CPL9, 32, + CP10, 32, + CP11, 32, + CP12, 32, + CP13, 32, + CP14, 32, + CP15, 32, + // OpRegion Mailbox 2 (Software SCI Interface) + + Offset(0x200), // SCIC + SCIE, 1, // SCI entry bit (1=call unserviced) + GEFC, 4, // Entry function code + GXFC, 3, // Exit result + GESF, 8, // Entry/exit sub-function/parameter + , 16, // SCIC[31:16] reserved + Offset(0x204), // PARM + PARM, 32, // PARM register (extra parameters) + DSLP, 32, // Driver sleep time out + + // OpRegion Mailbox 3 (BIOS to Driver Notification) + // Note: Mailbox 3 is normally reserved for desktop platforms. + + Offset(0x300), + ARDY, 32, // Driver readiness (power conservation) + ASLC, 32, // ASLE interrupt command/status + TCHE, 32, // Technology enabled indicator + ALSI, 32, // Current ALS illuminance reading + BCLP, 32, // Backlight brightness + PFIT, 32, // Panel fitting state or request + CBLV, 32, // Current brightness level + BCLM, 320, // Backlight brightness level duty cycle mapping table + CPFM, 32, // Current panel fitting mode + EPFM, 32, // Enabled panel fitting modes + PLUT, 592, // Optional. 74-byte Panel LUT Table + PFMB, 32, // Optional. PWM Frequency and Minimum Brightness + CCDV, 32, // Optional. Gamma, Brightness, Contrast values. + PCFT, 32, // Optional. Power Conservation Features + SROT, 32, // Supported rotation angle. + IUER, 32, // Optional. Intel Ultrabook Event Register. + FDSP, 64, // Optional. FFS Display Physical address + FDSS, 32, // Optional. FFS Display Size + STAT, 32, // State Indicator + + // OpRegion Mailbox 4 (VBT) + + Offset(0x400), + GVD1, 0xC000, // 6K bytes maximum VBT image + + // OpRegion Mailbox 5 (BIOS to Driver Notification Extension) + + Offset(0x1C00), + PHED, 32, // Panel Header + BDDC, 2048, // Panel EDID (Max 256 bytes) + +} + +// Define an OperationRegion to cover the ICH TCO I/O space region for use in +// clearing the MCH SCI status bit. + +/* Defined already by main ASL code, but shown below for reference. + +OperationRegion(TCOI,SystemIO,0x1060,0x8) +Field(TCOI,WordAcc, NoLock, Preserve) +{ + Offset(0x04), // TCO status register + , 9, + SCIS, 1, // TCO DMI SCI status + , 6, +}*/ + +// Convert boot display type into a port mask. + +Name (DBTB, Package() +{ + 0x0000, // Automatic + 0x0007, // Port-0 : Integrated CRT + 0x0038, // Port-1 : DVO-A, or Integrated LVDS + 0x01C0, // Port-2 : SDVO-B, or SDVO-B/C + 0x0E00, // Port-3 : SDVO-C + 0x003F, // [CRT + DVO-A / Integrated LVDS] + 0x01C7, // [CRT + SDVO-B] or [CRT + SDVO-B/C] + 0x0E07, // [CRT + SDVO-C] + 0x01F8, // [DVO-A / Integrated LVDS + SDVO-B] + 0x0E38, // [DVO-A / Integrated LVDS + SDVO-C] + 0x0FC0, // [SDVO-B + SDVO-C] + 0x0000, // Reserved + 0x0000, // Reserved + 0x0000, // Reserved + 0x0000, // Reserved + 0x0000, // Reserved + 0x7000, // Port-4: Integrated TV + 0x7007, // [Integrated TV + CRT] + 0x7038, // [Integrated TV + LVDS] + 0x71C0, // [Integrated TV + DVOB] + 0x7E00 // [Integrated TV + DVOC] +}) + +// Core display clock value table. + +Name (CDCT, Package() +{ + Package() {228, 320}, + Package() {222, 333}, + Package() {222, 333}, + Package() { 0, 0}, + Package() {222, 333}, +}) + +// Defined exit result values: + +Name (SUCC, 1) // Exit result: Success +Name (NVLD, 2) // Exit result: Invalid parameter +Name (CRIT, 4) // Exit result: Critical failure +Name (NCRT, 6) // Exit result: Non-critical failure + + +/************************************************************************; +;* +;* Name: GSCI +;* +;* Description: Handles an SCI generated by the graphics driver. The +;* PARM and SCIC input fields are parsed to determine the +;* functionality requested by the driver. GBDA or SBCB +;* is called based on the input data in SCIC. +;* +;* Usage: The method must be called in response to a GPE 06 event +;* which will be generated by the graphics driver. +;* Ex: Method(\_GPE._L06) {Return(\_SB.PCI0.GFX0.GSCI())} +;* +;* Input: PARM and SCIC are indirect inputs +;* +;* Output: PARM and SIC are indirect outputs +;* +;* References: GBDA (Get BIOS Data method), SBCB (System BIOS Callback +;* method) +;* +;************************************************************************/ + +Method (GSCI, 0, Serialized) +{ + Include("IgdOGbda.asl") // "Get BIOS Data" Functions + Include("IgdOSbcb.asl") // "System BIOS CallBacks" + + If (LEqual(GEFC, 4)) + { + Store(GBDA(), GXFC) // Process Get BIOS Data functions + } + + If (LEqual(GEFC, 6)) + { + Store(SBCB(), GXFC) // Process BIOS Callback functions + } + + Store(0, GEFC) // Wipe out the entry function code + Store(1, SCIS) // Clear the MCH SCI status bit in ICH TCO I/O space. + Store(0, GSSE) // Clear the SCI generation bit in PCI space. + Store(0, SCIE) // Clr SCI serviced bit to signal completion + + Return(Zero) +} + +// Include MOBLFEAT.ASL for mobile systems only. Remove for desktop. + +Include("IgdOMobF.asl") // IGD SCI mobile features + diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/Sa.asl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/Sa.asl new file mode 100644 index 0000000..a8f4ee0 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/Sa.asl @@ -0,0 +1,495 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + + +Module Name: + + Sa.ASL + +Abstract: + + Devices definition of SystemAgent ACPI reference code. + +--*/ +//AMI_OVERRIDE -->> +#if !defined(ASL_Remove_SaSsdt_Data_To_Dsdt) || (ASL_Remove_SaSsdt_Data_To_Dsdt == 0) +#if defined(ASL_RC_PEG_0) && (ASL_RC_PEG_0 == 1) +External(AR02) +External(PR02) +#endif +#if defined(ASL_RC_PEG_1) && (ASL_RC_PEG_1 == 1) +External(AR0A) +External(PR0A) +#endif +#if defined(ASL_RC_PEG_2) && (ASL_RC_PEG_2 == 1) +External(AR0B) +External(PR0B) +#endif +External(PICM) +External(\GPRW, MethodObj) +External(\_SB.PCI0, DeviceObj) +#endif +//AMI_OVERRIDE --<< + +Scope (\_SB.PCI0) { + Name(LTRS, 0) + Name(OBFS, 0) +//AMI_OVERRIDE -->> +#if defined(ASL_RC_PEG_0) && (ASL_RC_PEG_0 == 1) + Device(PEG0) { // P.E.G. Root Port D1F0 + Name(_ADR, 0x00010000) + OperationRegion(PEGR,PCI_Config,0xC0,0x30) + Field(PEGR,DWordAcc,NoLock,Preserve) + { + ,16, + PSTS, 1, // PME Status + offset (44), + GENG, 1, // General Message GPE Enable + ,1, // Reserved + PMEG, 1, // PME GPE Enable + } + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + + Method(_PSW,1) + { + If(Arg0) + { + Store(1,GENG) + Store(1,PMEG) + } + Else + { + Store(0,GENG) + Store(0,PMEG) + } + } + Method(HPME,0,Serialized) + { + // + // Clear PME status bit + // + Store(1,PSTS) + } + Method(_PRT,0) { + If(PICM) { Return(AR02) }// APIC mode + Return (PR02) // PIC Mode + } // end _PRT + // + // Pass LTRx to LTRS so SaPcieDsm.asl can be reused for PEGs. + // + Method(_INI) + { + Store (LTRA, LTRS) + Store (OBFA, OBFS) + } + include("SaPcieDsm.ASL") + + Device(PEGP) { // P.E.G. Port Slot x16 + Name(_ADR, 0x00000000) + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "P.E.G. Port Slot x16" + + } // end "P.E.G. Root Port D1F0" +#endif +#if defined(ASL_RC_PEG_1) && (ASL_RC_PEG_1 == 1) + Device(PEG1) { // P.E.G. Root Port D1F1 + Name(_ADR, 0x00010001) + OperationRegion(PEGR,PCI_Config,0xC0,0x30) + Field(PEGR,DWordAcc,NoLock,Preserve) + { + ,16, + PSTS, 1, // PME Status + offset (44), + GENG, 1, // General Message GPE Enable + ,1, // Reserved + PMEG, 1, // PME GPE Enable + } + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + + Method(_PSW,1) + { + If(Arg0) + { + Store(1,GENG) + Store(1,PMEG) + } + Else + { + Store(0,GENG) + Store(0,PMEG) + } + } + Method(HPME,0,Serialized) + { + // + // Clear PME status bit + // + Store(1,PSTS) + } + Method(_PRT,0) { + If(PICM) { Return(AR0A) }// APIC mode + Return (PR0A) // PIC Mode + } // end _PRT + + Method(_INI) + { + Store (LTRB, LTRS) + Store (OBFB, OBFS) + } + include("SaPcieDsm.ASL") + } // end "P.E.G. Root Port D1F1" +#endif +#if defined(ASL_RC_PEG_2) && (ASL_RC_PEG_2 == 1) + Device(PEG2) { // P.E.G. Root Port D1F2 + Name(_ADR, 0x00010002) + OperationRegion(PEGR,PCI_Config,0xC0,0x30) + Field(PEGR,DWordAcc,NoLock,Preserve) + { + ,16, + PSTS, 1, // PME Status + offset (44), + GENG, 1, // General Message GPE Enable + ,1, // Reserved + PMEG, 1, // PME GPE Enable + } + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + + Method(_PSW,1) + { + If(Arg0) + { + Store(1,GENG) + Store(1,PMEG) + } + Else + { + Store(0,GENG) + Store(0,PMEG) + } + } + Method(HPME,0,Serialized) + { + // + // Clear PME status bit + // + Store(1,PSTS) + } + Method(_PRT,0) { + If(PICM) { Return(AR0B) }// APIC mode + Return (PR0B) // PIC Mode + } // end _PRT + + Method(_INI) + { + Store (LTRC, LTRS) + Store (OBFC, OBFS) + } + include("SaPcieDsm.ASL") + } // end "P.E.G. Root Port D1F2" +#endif +//AMI_OVERRIDE --<< + Device(B0D3) { // SA Audio Device + Name(_ADR, 0x00030000) + Name (BARA, 0x80000000) + Name (TBAR, 0x0) + Name (TCMD, 0x0) + Name (MODB, 0x0) + Name (MODC, 0x0) + + Method(_STA,0) + { + If(LNotEqual(AUVD, 0xFFFF)) + { + Return(0xF) // then enabled + } + Return(0) // then disabled + } + + Method(_INI) { + // + // Save a valid Audio BAR for the ABWA W/A + // + If (LAnd (LNotEqual (And(ABAR, 0xFFFFC004), 0xFFFFC004), LNotEqual (And (ABAR, 0xFFFFC000), 0))) { + Store (ABAR, BARA) + } + } + + OperationRegion(RPCS,SystemMemory,\XBAS,0x18040) + Field(RPCS,AnyAcc,NoLock,Preserve) + { + Offset (0x18004), + ACMD, 8, + Offset (0x18010), + ABAR, 32, + } + + OperationRegion(RPCZ,PCI_Config,0x00,0x40) + Field(RPCZ,DWordAcc,Lock,Preserve) + { + AUVD, 16, + } + + /// + /// Restore Audio WAs + /// + Method (ASTR, 0, Serialized) { + + If (LAnd (LNotEqual (And(ABAR, 0xFFFFC004), 0xFFFFC004), LNotEqual (And (ABAR, 0xFFFFC000), 0))) { + And (ABAR, 0xFFFFFFF0, BBAR) + Add (BBAR, 0x1000, BBAR) + OperationRegion(RPCY,SystemMemory,BBAR, 0x25) + Field(RPCY,DWordAcc,NoLock,Preserve) + { + Offset(0xC), + EM4W, 32, + Offset(0x10), + EMWA, 32, + Offset(0x1C), + ADWA, 32, + } + + Store(AUDA, EMWA) + Store(AUDB, ADWA) + Store(AUDC, EM4W) + } + + } + + /// + /// Send the command to the codec via the Immediate Command + /// + Method (VSTR, 1, Serialized) { + + Name (CONT, 1000) + Name (ADDR, 0x80000000) + + Store (Arg0, ADDR) + OperationRegion(CCDC,SystemMemory,ADDR,4) + Field(CCDC,ByteAcc,NoLock,Preserve) + { + Offset(0x0), + CDEC, 32, + } + + If (LAnd (LNotEqual (And(ABAR, 0xFFFFC004), 0xFFFFC004), LNotEqual (And (ABAR, 0xFFFFC000), 0))) { + If (LNotEqual (CDEC, 0)) { + And (ABAR, 0xFFFFFFF0, BBAR) + + OperationRegion(IPCV,SystemMemory,BBAR,0x70) + Field(IPCV,DWordAcc,NoLock,Preserve) + { + Offset(0x60), + AVIC, 32, + Offset(0x68), + AIRS, 16, + } + + Store (1000, CONT) + While (LAnd (LEqual(And(AIRS, 0x1), 1), LNotEqual(CONT,0))) + { + Stall(1) + Decrement(CONT) + } + Or (AIRS, 2, AIRS) + Store (CDEC, AVIC) + Or (AIRS, 1, AIRS) + + Store (1000, CONT) + While (LAnd (LEqual(And(AIRS, 0x1), 1), LNotEqual(CONT,0))) + { + Stall(1) + Decrement(CONT) + } + } + } + } + + /// + /// Restore Verb Table + /// + Method (CXDC, 0, Serialized) + { + Name(IDDX, 0x80000000) +//AMI_OVERRIDE --- Change name from CADR to CCSA to fix that the system has BsOD issue. It is due to the name(CADR) is conflict with AMI Aptio definition name. >> + If (LAnd (LNotEqual (CCSA, 0), LNotEqual (CCNT, 0))) { + Store (CCSA, IDDX) + While (LLess (IDDX, Add (CCSA, Multiply (CCNT, 4)))) +// If (LAnd (LNotEqual (CADR, 0), LNotEqual (CCNT, 0))) { +// Store (CADR, IDDX) +// While (LLess (IDDX, Add (CADR, Multiply (CCNT, 4)))) +//AMI_OVERRIDE --- << + { + VSTR (IDDX) + Add (IDDX, 4, IDDX) + } + } + } + + /// + /// Reset Audio Controller + /// + Method (ARST, 0, Serialized) + { + If (LAnd (LNotEqual (And(ABAR, 0xFFFFC004), 0xFFFFC004), LNotEqual (And (ABAR, 0xFFFFC000), 0))) { + And (ABAR, 0xFFFFFFF0, BBAR) + OperationRegion(IPCV,SystemMemory,BBAR,0xBF) + Field(IPCV,AnyAcc,NoLock,Preserve) + { + Offset(0x08), + CRST, 32, + Offset(0x4C), + CORB, 32, + Offset(0x5C), + RIRB, 32, + Offset(0x80), + OSD1, 32, + Offset(0xA0), + OSD2, 32, + } + AND (CORB, 0xFFFFFFFD, CORB) + AND (RIRB, 0xFFFFFFFD, RIRB) + AND (OSD1, 0xFFFFFFFD, OSD1) + AND (OSD2, 0xFFFFFFFD, OSD2) + AND (CRST, 0xFFFFFFFE, CRST) + } + } + + /// + /// Codec Initialization Programming Sequence + /// + Method (AINI, 0, Serialized) + { + Name (CONT, 1000) + + If (LAnd (LNotEqual (And(ABAR, 0xFFFFC004), 0xFFFFC004), LNotEqual (And (ABAR, 0xFFFFC000), 0))) { + And (ABAR, 0xFFFFFFF0, BBAR) + + OperationRegion(IPCV,SystemMemory,BBAR,0x70) + Field(IPCV,DWordAcc,NoLock,Preserve) + { + Offset(0x0), + GCAP, 16, + Offset(0x08), + GCTL, 32, + Offset(0x0E), + SSTS, 8, + Offset(0x60), + AVIC, 32, + Offset(0x68), + AIRS, 16, + } + + /// + /// Step1/2:Reset Controller and wait for reset complete + /// + Or (GCTL, 1, GCTL) + Store (1000, CONT) + While (LAnd (LEqual (And (GCTL , 1), 0), LNotEqual (CONT, 0))) + { + Stall (1) + Decrement (CONT) + } + + /// + /// Step3: + /// Read GCAP and write the same value back to + /// the register once after Controller Reset# bit is set + /// + And (GCAP, 0xFFFF, GCAP) + + /// + /// Step4: + /// Clear the "State Change Status Register" STATESTS bits for + /// each of the "SDIN Stat Change Status Flag" + /// + Or (SSTS, 0xF, SSTS) + + /// + /// Step5: + /// Turn off the link and poll RESET# bit until it reads back + /// as 0 to get hardware reset report + /// + And (GCTL, 0xFFFFFFFE, GCTL) + + Store (1000, CONT) + While (LAnd (LEqual(And(GCTL,1), 1), LNotEqual(CONT,0))) + { + Stall (1) + Decrement (CONT) + } + + /// + /// Step6: + /// Turn on the link and poll RESET# bit until it reads back as 1 + /// + Or (GCTL, 1, GCTL) + Store (1000, CONT) + While (LAnd (LEqual(And(GCTL,1), 0), LNotEqual(CONT,0))) + { + Stall (1) + Decrement (CONT) + } + } + } + /// + /// W/A for Audio CdClk restore issue with HDMI hotplug after S3/S4 resume + /// Store ABAR temporarily and restore it at the end of Call Back SF 21h + /// + Method (ABWA, 1, Serialized) + { + If (Arg0) { + If (LOr (LEqual (And(ABAR, 0xFFFFC004), 0xFFFFC004), LEqual (And (ABAR, 0xFFFFC000), 0))) { + /// + /// if Audio BAR does not have a valid value + /// + If (LNotEqual (BARA, 0x80000000)) { // but a vaid value has been saved by the _INI or _WAK earlier + Store (ABAR, TBAR) // temporarily assign Audio Bar to restore mmio registers + Store (ACMD, TCMD) + Store (BARA, ABAR) + Store (0x06, ACMD) + Store (0x01, MODB) + } + } Else { // Audio BAR has a valid value + If (LNotEqual (And (ACMD, 0x06), 0x06)) { // but CMD register is not set to allow writes to mmio registers + Store (ACMD, TCMD) // temporarily set CMD register to allow mmio writes + Store (0x06, ACMD) + Store (0x01, MODC) + } + } + } Else { // Restore the original Audio Bar and Cmd Register + If (MODB) { + If(LEqual(ABAR, BARA)) { + Store (TBAR, ABAR) + Store (TCMD, ACMD) + } + } + If (MODC) { // Restore only the Cmd Register + Store (TCMD, ACMD) + } + } + } + } // end "SA Audio Device" + + Device(GFX0) { // I.G.D + Name(_ADR, 0x00020000) + include("IntelGfx.ASL") + } // end I.G.D + +} diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaPcieDsm.asl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaPcieDsm.asl new file mode 100644 index 0000000..613138c --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaPcieDsm.asl @@ -0,0 +1,119 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - ACPI Reference Code for the Haswell *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + + Name(LTRV, Package(){0,0,0,0}) + Name(OPTS, 0) // SA SETUP options for LTR and OBFF + + // + // _DSM Device Specific Method + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index (0 = Return Supported Functions) + // Arg3: Package Parameters + Method(_DSM, 4, Serialized) { + // + // Switch based on which unique function identifier was passed in + // + Switch(ToInteger(Arg0)) { + // + // _DSM Definitions for Latency Tolerance Reporting + // + // Arguments: + // Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D + // Arg1: Revision ID: 2 + // Arg2: Function Index: 6 + // Arg3: Empty Package + // + // Return: + // A Package of four integers corresponding with the LTR encoding defined + // in the PCI Express Base Specification, as follows: + // Integer 0: Maximum Snoop Latency Scale + // Integer 1: Maximum Snoop Latency Value + // Integer 2: Maximum No-Snoop Latency Scale + // Integer 3: Maximum No-Snoop Latency Value + // These values correspond directly to the LTR Extended Capability Structure + // fields described in the PCI Express Base Specification. + // + Case(ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")) { + // + // Switch by function index + // + Switch(ToInteger(Arg2)) { + // + // Function Index:0 + // Standard query - A bitmask of functions supported + // + Case (0) + { + if (LEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2 + Store(1, OPTS) // function 0 + if (LTRS){ + Or(OPTS,0x40,OPTS) // function 6 + } + if (OBFS){ + Or(OPTS,0x10,OPTS) // function 4 + } + Return (OPTS) // bitmask of supported functions: 6, 4, 0. + } else { + Return (0) + } + } + // + // Function Index: 4 + // + Case(4) { + if (LEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2 + if (OBFS){ + Return (Buffer () {0,0,0,0,0,0,0,0,0,0,0,8,0,0,0,0}) // OBFF capable, offset 4[08h] + } else { + Return (Buffer () {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}) + } + } + } + // + // Function Index: 6 + // LTR Extended Capability Structure + // + Case(6) { + if (LEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2 + if (LTRS){ + Store(And(ShiftRight(SMSL,10),7), Index(LTRV, 0)) + Store(And(SMSL,0x3FF), Index(LTRV, 1)) + Store(And(ShiftRight(SNSL,10),7), Index(LTRV, 2)) + Store(And(SNSL,0x3FF), Index(LTRV, 3)) + return (LTRV) + } else { + Return (0) + } + } + } + } // End of switch(Arg2) + } // End of case(ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")) + } // End of switch(Arg0) + return (Buffer() {0x00}) + } // End of _DSM diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt.asl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt.asl new file mode 100644 index 0000000..0650178 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt.asl @@ -0,0 +1,172 @@ +/*++ + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +/*++ + +Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +Module Name: + + SaSsdt.asl + +Abstract: + + SA SSDT Table ASL code + +--*/ + + +DefinitionBlock ( + "SaSsdt.aml", + "SSDT", + 0x01, + "SaSsdt", + "SaSsdt ", + 0x3000 + ) +{ + + OperationRegion(SANV,SystemMemory,0xFFFF0000,0xAA55) + Field(SANV,AnyAcc,Lock,Preserve) + { + SARV, 32, /// (000) SA RC Revision + ASLB, 32, /// (004) IGD OpRegion base address + IMON, 8, /// (008) IMON Current Value + IGDS, 8, /// (009) IGD State (Primary Display = 1) + CADL, 8, /// (010) Current Attached Device List + PADL, 8, /// (011) Previous Attached Device List + CSTE, 16, /// (012) Current Display State + NSTE, 16, /// (014) Next Display State + DID9, 32, /// (016) Device Id 9 + DIDA, 32, /// (020) Device Id 10 + DIDB, 32, /// (024) Device Id 11 + IBTT, 8, /// (028) IGD Boot Display Device + IPAT, 8, /// (029) IGD Panel Type CMOs option + IPSC, 8, /// (030) IGD Panel Scaling + IBLC, 8, /// (031) IGD BLC Configuration + IBIA, 8, /// (032) IGD BIA Configuration + ISSC, 8, /// (033) IGD SSC Configuration + IPCF, 8, /// (034) IGD Power Conservation Feature Flag + IDMS, 8, /// (035) IGD DVMT Memory Size + IF1E, 8, /// (036) IGD Function 1 Enable + HVCO, 8, /// (037) HPLL VCO + NXD1, 32, /// (038) Next state DID1 for _DGS + NXD2, 32, /// (042) Next state DID2 for _DGS + NXD3, 32, /// (046) Next state DID3 for _DGS + NXD4, 32, /// (050) Next state DID4 for _DGS + NXD5, 32, /// (054) Next state DID5 for _DGS + NXD6, 32, /// (058) Next state DID6 for _DGS + NXD7, 32, /// (062) Next state DID7 for _DGS + NXD8, 32, /// (066) Next state DID8 for _DGS + GSMI, 8, /// (070) GMCH SMI/SCI mode (0=SCI) + PAVP, 8, /// (071) IGD PAVP data + LIDS, 8, /// (072) Lid State (Lid Open = 1) + KSV0, 32, /// (073) First four bytes of AKSV (mannufacturing mode) + KSV1, 8, /// (077) Fifth byte of AKSV (mannufacturing mode) + BBAR, 32, /// (078) IGFX Audio (D3F0) MMIO BAR Address + BLCS, 8, /// (082) Backlight Control Support + BRTL, 8, /// (083) Brightness Level Percentage + ALSE, 8, /// (084) ALS Enable + ALAF, 8, /// (085) Ambient Light Adjusment Factor + LLOW, 8, /// (086) LUX Low Value + LHIH, 8, /// (087) LUX High Value + ALFP, 8, /// (088) Active LFP + AUDA, 32, /// (089) Audio MMIO WA 1 + AUDB, 32, /// (093) Audio MMIO WA 2 + AUDC, 32, /// (097) Audio MMIO WA 3 + DIDC, 32, /// (101) Device Id 12 + DIDD, 32, /// (105) Device Id 13 + DIDE, 32, /// (109) Device Id 14 + DIDF, 32, /// (113) Device Id 15 +//AMI_OVERRIDE --- Change name from CADR to CCSA to fix that the system has BsOD issue. It is due to the name(CADR) is conflict with AMI Aptio definition name. >> + CCSA, 32, /// (117) Codec Save Address + CCNT, 32, /// (121) Codec Save Count +//CADR, 32, /// (117) Codec Save Address +//CCNT, 8, /// (121) Codec Save Count +//AMI_OVERRIDE --- << + /// + /// Switchable Graphics Info + /// + Offset(200), + SGMD, 8, /// (200) SG Mode (0=Disabled, 1=SG Muxed, 2=SG Muxless, 3=DGPU Only) + SGFL, 8, /// (201) SG Feature List + PWOK, 8, /// (202) dGPU PWROK GPIO assigned + HLRS, 8, /// (203) dGPU HLD RST GPIO assigned + PWEN, 8, /// (204) dGPU PWR Enable GPIO assigned + PRST, 8, /// (205) dGPU Present Detect GPIO assigned + CPSP, 32, /// (206) PEG Endpoint Capability Structure Presence (Bit 0: Virtual Channel Capability) + EECP, 8, /// (210) PEG Endpoint PCIe Capability Structure Offset + EVCP, 16, /// (211) PEG Endpoint Virtual Channel Capability Structure Offset + XBAS, 32, /// (213) Any Device's PCIe Config Space Base Address + GBAS, 16, /// (217) GPIO Base Address + SGGP, 8, /// (219) SG GPIO Support + NVGA, 32, /// (220) NVIG opregion address + NVHA, 32, /// (224) NVHM opregion address + AMDA, 32, /// (228) AMDA opregion address + NDID, 8, /// (232) Number of Valid Device IDs + DID1, 32, /// (233) Device ID 1 + DID2, 32, /// (237) Device ID 2 + DID3, 32, /// (241) Device ID 3 + DID4, 32, /// (245) Device ID 4 + DID5, 32, /// (249) Device ID 5 + DID6, 32, /// (253) Device ID 6 + DID7, 32, /// (257) Device ID 7 + DID8, 32, /// (261) Device ID 8 + OBS1, 32, /// (265) Occupied Buses - from 0 to 31 + OBS2, 32, /// (269) Occupied Buses - from 32 to 63 + OBS3, 32, /// (273) Occupied Buses - from 64 to 95 + OBS4, 32, /// (277) Occupied Buses - from 96 to 127 + OBS5, 32, /// (281) Occupied Buses - from 128 to 159 + OBS6, 32, /// (285) Occupied Buses - from 160 to 191 + OBS7, 32, /// (289) Occupied Buses - from 192 to 223 + OBS8, 32, /// (293) Occupied Buses - from 224 to 255 + LTRA, 8, /// (297) Latency Tolerance Reporting Enable + OBFA, 8, /// (298) Optimized Buffer Flush and Fill + LTRB, 8, /// (299) Latency Tolerance Reporting Enable + OBFB, 8, /// (300) Optimized Buffer Flush and Fill + LTRC, 8, /// (301) Latency Tolerance Reporting Enable + OBFC, 8, /// (302) Optimized Buffer Flush and Fill + SMSL, 16, /// (303) SA Peg Latency Tolerance Reporting Max Snoop Latency + SNSL, 16, /// (305) SA Peg Latency Tolerance Reporting Max No Snoop Latency + P0UB, 8, /// (307) Peg0 Unused Bundle Control + P1UB, 8, /// (308) Peg1 Unused Bundle Control + P2UB, 8, /// (309) Peg2 Unused Bundle Control + EDPV, 8, /// (310) Check for eDP display device + NXDX, 32, /// (311) Next state DID for eDP + DIDX, 32, /// (315) Device ID for eDP device + PCSL, 8, /// (319) The lowest C-state for the package + SC7A, 8, /// (316) Run-time C7 Allowed feature (0=Disabled, 1=Enabled) +// AMI_OVERRIDE... + DSEL, 8, /// (319) dGPU Display Select GPIO assigned + ESEL, 8, /// (320) dGPU EDID Select GPIO assigned + PSEL, 8, /// (321) dGPU PWM Select GPIO assigned + MXD1, 32, /// (322) DID1 Mux Setting + MXD2, 32, /// (326) DID2 Mux Setting + MXD3, 32, /// (330) DID3 Mux Setting + MXD4, 32, /// (334) DID4 Mux Setting + MXD5, 32, /// (338) DID5 Mux Setting + MXD6, 32, /// (342) DID6 Mux Setting + MXD7, 32, /// (346) DID7 Mux Setting + MXD8, 32, /// (350) DID8 Mux Setting + PXFD, 8, /// (354) ATI 5.0 Fixed/Dynamic ATI 5.0 Fixed/Dynamic + EBAS, 32, /// (355) Endpoint PCIe Base Address + HYSS, 32, /// (359) dGPU SSID for MSHyBrid restore +// AMI_OVERRIDE...end. + } +#if !defined(ASL_Remove_SaSsdt_Data_To_Dsdt) || (ASL_Remove_SaSsdt_Data_To_Dsdt == 0) + include ("Sa.asl") +#endif // AMI_OVERRIDE +}
\ No newline at end of file diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf new file mode 100644 index 0000000..e97e019 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf @@ -0,0 +1,69 @@ +## @file +# Component description file for the ACPI tables +# +#@copyright +# Copyright (c) 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# + + +[defines] +BASE_NAME = SaSsdt +FILE_GUID = AAA99A23-13B6-4C31-BB8B-299E8EC04FA4 +COMPONENT_TYPE = ACPITABLE +FFS_EXT = .ffs + +[sources.common] + SaSsdt.ASL + +[libraries.common] + +[includes.common] + . + $(EFI_SOURCE) + $(EFI_SOURCE)/Include + $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EFI_SOURCE)/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework +# +# Typically the sample code referenced will be available in the code base already +# So keep this include at the end to defer to the source base definition +# and only use the sample code definition if source base does not include these files. +# +# $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode/Include + +# +# Edk II Glue Library, some hearder are included by R9 header so have to include +# + + $(EFI_SOURCE) + $(EFI_SOURCE)/Framework + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + +[nmake.common] diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.cif b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.cif new file mode 100644 index 0000000..ef4ae0c --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.cif @@ -0,0 +1,19 @@ +<component> + name = "SaSsdtTables" + category = ModulePart + LocalRoot = "ReferenceCode\Chipset\SystemAgent\AcpiTables\SaSsdt\" + RefName = "SaSsdtTables" +[files] +"IgdOGBDA.ASL" +"IgdOMOBF.ASL" +"IgdOpRn.ASL" +"IgdOSBCB.ASL" +"INTELGFX.ASL" +"Sa.asl" +"SaPcieDsm.asl" +"SaSsdt.asl" +"SaSsdt.inf" +"SaSsdt_Edk.inf" +"SaSsdtTables.mak" +"SaSsdtTables.sdl" +<endComponent> diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.mak b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.mak new file mode 100644 index 0000000..e44f223 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.mak @@ -0,0 +1,57 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: SgAcpiTables.mak +# +# Description: MAK file for the ModulePart:SgAcpiTables +# +# +#<AMI_FHDR_END> +#************************************************************************* +all : BuildSaSsdt + +BuildSaSsdt : $(BUILD_DIR)\SaSsdt.ffs + +#----------------------------------------------------------------------- +# ASL compiler definition +#----------------------------------------------------------------------- +IASL = $(SILENT)iasl4.exe +#----------------------------------------------------------------------- +$(BUILD_DIR)\SaSsdt.aml : $(INTEL_SASSDT_ASL_FILE) + $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_IgdOGBDA_ASL_FILE) > $(BUILD_DIR)\IgdOGBDA.asl + $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_IgdOMOBF_ASL_FILE) > $(BUILD_DIR)\IgdOMOBF.asl + $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_IgdOPRN_ASL_FILE) > $(BUILD_DIR)\IgdOPRN.asl + $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_IgdOSBCB_ASL_FILE) > $(BUILD_DIR)\IgdOSBCB.asl + $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_INTELGFX_ASL_FILE) > $(BUILD_DIR)\INTELGFX.asl + $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_SA_ASL_FILE) > $(BUILD_DIR)\SA.asl + $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_SAPCIEDSM_ASL_FILE) > $(BUILD_DIR)\SAPCIEDSM.asl + $(CP) /FI$(BUILD_DIR)\tokenasl.h $(INTEL_SASSDT_ASL_FILE) > $(BUILD_DIR)\SASSDT.asl + $(ASLEXPANDER) $(BUILD_DIR)\SASSDT.asl $(BUILD_DIR)\SASSDT_BUILD.asl $(BUILD_DIR) + $(IASL) -p $(BUILD_DIR)\SaSsdt.aml $(BUILD_DIR)\SASSDT_BUILD.asl + + +$(BUILD_DIR)\SaSsdt.sec: $(BUILD_DIR)\SaSsdt.aml + $(GENSECTION) -I $*.aml -O $@ -S EFI_SECTION_RAW + +$(BUILD_DIR)\SaSsdt.ffs: $(BUILD_DIR)\SaSsdt.sec $(SaSsdtTables_DIR)\SaSsdtTables.mak + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=AAA99A23-13B6-4C31-BB8B-299E8EC04FA4\ + TYPE=EFI_FV_FILETYPE_FREEFORM \ + FFS_CHECKSUM=1\ + RAWFILE=$(BUILD_DIR)\SaSsdt.sec FFSFILE=$(BUILD_DIR)\SaSsdt.ffs COMPRESS=0 NAME=SaSsdt + diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.sdl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.sdl new file mode 100644 index 0000000..6e0c223 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdtTables.sdl @@ -0,0 +1,104 @@ +TOKEN + Name = "SaSsdtTables_SUPPORT" + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable SaSsdtTables support in Project" +End + +TOKEN + Name = "Remove_SaSsdt_Data_To_Dsdt" + Value = "0" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Help = "Remove related SaSsdt acpi data to DSDT" +End + +ELINK + Name = "/D Remove_SaSsdt_Data_To_Dsdt" + Parent = "INTEL_SA_RC_FLAGS" + Token = "Remove_SaSsdt_Data_To_Dsdt" "=" "1" + InvokeOrder = AfterParent +End + +MODULE + Help = "Includes SgAcpiTables.mak to Project" + File = "SaSsdtTables.mak" +End + +PATH + Name = "SaSsdtTables_DIR" +End + +ELINK + Name = "$(SaSsdtTables_DIR)\Sa.asl" + Parent = "INTEL_GENERIC_ASL" + Token = "Remove_SaSsdt_Data_To_Dsdt" "=" "1" + InvokeOrder = AfterParent +End + +TOKEN + Name = "INTEL_IgdOGBDA_ASL_FILE" + Value = "$(SaSsdtTables_DIR)\IgdOGBDA.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_IgdOMOBF_ASL_FILE" + Value = "$(SaSsdtTables_DIR)\IgdOMOBF.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_IgdOPRN_ASL_FILE" + Value = "$(SaSsdtTables_DIR)\IgdOPRN.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_IgdOSBCB_ASL_FILE" + Value = "$(SaSsdtTables_DIR)\IgdOSBCB.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_INTELGFX_ASL_FILE" + Value = "$(SaSsdtTables_DIR)\INTELGFX.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_SA_ASL_FILE" + Value = "$(SaSsdtTables_DIR)\SA.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_SAPCIEDSM_ASL_FILE" + Value = "$(SaSsdtTables_DIR)\SAPCIEDSM.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_SASSDT_ASL_FILE" + Value = "$(SaSsdtTables_DIR)\SASSDT.asl" + TokenType = Expression + TargetMAK = Yes +End + +ELINK + Name = "$(BUILD_DIR)\SaSsdt.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt_Edk.inf b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt_Edk.inf new file mode 100644 index 0000000..4ef6ff6 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SaSsdt/SaSsdt_Edk.inf @@ -0,0 +1,76 @@ +## @file +# Component description file for the ACPI tables (for EDK1117) +# +#@copyright +# Copyright (c) 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# + + +[defines] +BASE_NAME = SaSsdt +FILE_GUID = AAA99A23-13B6-4C31-BB8B-299E8EC04FA4 +COMPONENT_TYPE = SA_SSDT_ACPITABLE +FFS_EXT = .ffs + +[sources.common] + SaSsdt.ASL + Sa.asl + IntelGfx.asl + IgdOpRn.asl + IgdOGBDA.asl + IgdOMOBF.asl + IgdOSBCB.asl + SaPcieDsm.asl + +[libraries.common] + +[includes.common] + . + $(EFI_SOURCE) + $(EFI_SOURCE)/Include + $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EFI_SOURCE)/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework +# +# Typically the sample code referenced will be available in the code base already +# So keep this include at the end to defer to the source base definition +# and only use the sample code definition if source base does not include these files. +# +# $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode/Include + +# +# Edk II Glue Library, some hearder are included by R9 header so have to include +# + + $(EFI_SOURCE) + $(EFI_SOURCE)/Framework + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + +[nmake.common] diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.cif b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.cif new file mode 100644 index 0000000..55ed596 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.cif @@ -0,0 +1,12 @@ +<component> + name = "SgAcpiTablesPch" + category = ModulePart + LocalRoot = "ReferenceCode\Chipset\SystemAgent\AcpiTables\SwitchableGraphics\Pch\" + RefName = "SgAcpiTablesPch" +[files] +"SgAcpiTablesPch.sdl" +"SgAcpiTablesPch.mak" +"SgAcpiTablesPch.inf" +"SgDgpuPch.asl" +"SgSsdtPch.asl" +<endComponent> diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.inf b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.inf new file mode 100644 index 0000000..5fdc0ea --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.inf @@ -0,0 +1,69 @@ +## @file +# Component description file for the ACPI tables +# +#@copyright +# Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# + + +[defines] +BASE_NAME = SgAcpiTablesPch +FILE_GUID = CBCB3817-81E6-497e-87FF-C8FA8F24EC28 +COMPONENT_TYPE = ACPITABLE +FFS_EXT = .ffs + +[sources.common] + SgSsdtPch.ASL + +[libraries.common] + +[includes.common] + . + $(EFI_SOURCE) + $(EFI_SOURCE)/Include + $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EFI_SOURCE)/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework +# +# Typically the sample code referenced will be available in the code base already +# So keep this include at the end to defer to the source base definition +# and only use the sample code definition if source base does not include these files. +# + $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode/Include + +# +# Edk II Glue Library, some hearder are included by R9 header so have to include +# + + $(EFI_SOURCE) + $(EFI_SOURCE)/Framework + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + +[nmake.common] diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.mak b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.mak new file mode 100644 index 0000000..4f84b21 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.mak @@ -0,0 +1,62 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: SgAcpiTablesPch.mak +# +# Description: MAK file for the ModulePart:SgAcpiTablesPch +# +# +#<AMI_FHDR_END> +#************************************************************************* +EDK: SGPCHASL + +SGPCHASL: $(BUILD_DIR)\SGACPIPCH.ffs + +ALLSGPCHSEC = $(BUILD_DIR)\SGACPIPCH.sec + +!IFNDEF IASL +IASL = iasl4.exe # Intel ASL compiler. Supports extended ACPI 2.0 asl objects +!ENDIF + +#-----------------------------------------------------------------------# +# Process SGPCH asl files +#-----------------------------------------------------------------------# + +$(BUILD_DIR)\SgSsdtPch.asl : $(SGACPIPCH_DIR)\SgSsdtPch.ASL \ + $(SGACPIPCH_DIR)\SgDgpuPch.ASL + $(CP) /I$(SGACPIPCH_DIR) /FItoken.h /C $(SGACPIPCH_DIR)\$(@F) > $@ +# include the token.h if needed to check for SDL flags +# /FItoken.h + +SgAcpiTablesPch_Includes = \ + $(SGACPIPCH_DIR)\ + +$(BUILD_DIR)\SgSsdtPch.aml: $(BUILD_DIR)\SgSsdtPch.asl + $(SILENT)$(IASL) -I $(SgAcpiTablesPch_Includes) -p $@ $** + +$(ALLSGPCHSEC): $(BUILD_DIR)\SgSsdtPch.aml + $(GENSECTION) -I $** -O $@ -S EFI_SECTION_RAW + +$(BUILD_DIR)\SGACPIPCH.ffs: $(ALLSGPCHSEC) $(SGACPIPCH_DIR)\SgAcpiTablesPch.mak + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=CBCB3817-81E6-497e-87FF-C8FA8F24EC28\ + TYPE=EFI_FV_FILETYPE_FREEFORM \ + FFS_CHECKSUM=1\ + RAWFILE=$(ALLSGPCHSEC) FFSFILE=$(BUILD_DIR)\SGACPIPCH.ffs COMPRESS=0 NAME=SGACPIPCH + + diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.sdl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.sdl new file mode 100644 index 0000000..94ec922 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgAcpiTablesPch.sdl @@ -0,0 +1,113 @@ +TOKEN + Name = SgAcpiTablesPch_SUPPORT + Value = 1 + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable SgAcpiTablesPch support in Project" + Token = "SwitchableGraphics_SUPPORT" "=" "1" +End + +TOKEN + Name = "SG_ULT_RPNum" + Value = "1" + TokenType = Expression + TargetMak = Yes + TargetH = Yes + Token = "SG_ULT_PORT_FUNC" "=" "0" + Lock = Yes +End + +TOKEN + Name = "SG_ULT_RPNum" + Value = "2" + TokenType = Expression + TargetMak = Yes + TargetH = Yes + Token = "SG_ULT_PORT_FUNC" "=" "1" + Lock = Yes +End + +TOKEN + Name = "SG_ULT_RPNum" + Value = "3" + TokenType = Expression + TargetMak = Yes + TargetH = Yes + Token = "SG_ULT_PORT_FUNC" "=" "2" + Lock = Yes +End + +TOKEN + Name = "SG_ULT_RPNum" + Value = "4" + TokenType = Expression + TargetMak = Yes + TargetH = Yes + Token = "SG_ULT_PORT_FUNC" "=" "3" + Lock = Yes +End + +TOKEN + Name = "SG_ULT_RPNum" + Value = "5" + TokenType = Expression + TargetMak = Yes + TargetH = Yes + Token = "SG_ULT_PORT_FUNC" "=" "4" + Lock = Yes +End + +TOKEN + Name = "SG_ULT_RPNum" + Value = "6" + TokenType = Expression + TargetMak = Yes + TargetH = Yes + Token = "SG_ULT_PORT_FUNC" "=" "5" + Lock = Yes +End + +TOKEN + Name = "SG_ULT_RPNum" + Value = "7" + TokenType = Expression + TargetMak = Yes + TargetH = Yes + Token = "SG_ULT_PORT_FUNC" "=" "6" + Lock = Yes +End + +TOKEN + Name = "SG_ULT_RPNum" + Value = "8" + TokenType = Expression + TargetMak = Yes + TargetH = Yes + Token = "SG_ULT_PORT_FUNC" "=" "7" + Lock =Yes +End + +TOKEN + Name = "SG_ULT_RP_NUM" + Value = "\_SB.PCI0.RP0$(SG_ULT_RPNum)" + TokenType = Expression + TargetH = Yes + Lock = Yes +End + +MODULE + Help = "Includes SgAcpiTablesPch.mak to Project" + File = "SgAcpiTablesPch.mak" +End + +PATH + Name = "SGACPIPCH_DIR" +End + +ELINK + Name = "$(BUILD_DIR)\SGACPIPCH.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgDgpuPch.asl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgDgpuPch.asl new file mode 100644 index 0000000..76a9a0e --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgDgpuPch.asl @@ -0,0 +1,847 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - SG Reference Code *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2010 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +External(\_SB.PCI0.GFX0._DOD, MethodObj) +External(\_SB.PCI0.GFX0.DD01._ADR, MethodObj) +External(\_SB.PCI0.GFX0.DD02._ADR, MethodObj) +External(\_SB.PCI0.GFX0.DD03._ADR, MethodObj) +External(\_SB.PCI0.GFX0.DD04._ADR, MethodObj) +External(\_SB.PCI0.GFX0.DD05._ADR, MethodObj) +External(\_SB.PCI0.GFX0.DD06._ADR, MethodObj) +External(\_SB.PCI0.GFX0.DD07._ADR, MethodObj) +External(\_SB.PCI0.GFX0.DD08._ADR, MethodObj) + +External(\_SB.PCI0.GFX0.DD01._DGS, MethodObj) +External(\_SB.PCI0.GFX0.DD02._DGS, MethodObj) +External(\_SB.PCI0.GFX0.DD03._DGS, MethodObj) +External(\_SB.PCI0.GFX0.DD04._DGS, MethodObj) +External(\_SB.PCI0.GFX0.DD05._DGS, MethodObj) +External(\_SB.PCI0.GFX0.DD06._DGS, MethodObj) +External(\_SB.PCI0.GFX0.DD07._DGS, MethodObj) +External(\_SB.PCI0.GFX0.DD08._DGS, MethodObj) + +External(\_SB.PCI0.GFX0.DD02._DCS, MethodObj) + +External(\_SB.PCI0.GFX0.DD02._BCL, MethodObj) +External(\_SB.PCI0.GFX0.DD02._BQC, MethodObj) +External(\_SB.PCI0.GFX0.DD02._BCM, MethodObj) +//AMI override begin +External(SG_ULT_RP_NUM, DeviceObj) +//External(\_SB.PCI0.RP05, DeviceObj) +//AMI override end +External(\RPA4) +External(\EECP) +External(\XBAS) +External(\GBAS) +External(\HLRS) +External(\PWEN) +External(\SGMD) +External(\SGGP) +//AMI override begin +External(\EBAS) +External(\HYSS) +//AMI override end +//AMI override begin +Scope(SG_ULT_RP_NUM) +//Scope(\_SB.PCI0.RP05) +//AMI override end +{ + OperationRegion (MSID, SystemMemory, EBAS, 0x50) + Field(MSID, DWordAcc, Lock, Preserve) + { + VEID, 16, + Offset(0x40), + NVID, 32, + offset(0x4c), + ATID, 32, + } + // Define a Memory Region that will allow access to the PCH root port + // Register Block. + // +// OperationRegion(RPCI,PCI_Config,0x00,0xF0) +// Field(RPCI,DWordAcc,Lock,Preserve) +// { +// } + + OperationRegion(RPCX,SystemMemory,Add(Add(\XBAS,0xE0000), ShiftLeft(And(\RPA4,0xF),12)),0x1000) + Field(RPCX,DWordAcc,NoLock,Preserve) + { + Offset(0), + PVID, 16, + PDID, 16, +// AMI_OVERRIDE >>> + Offset(0x4), + CMDR, 8, +// AMI_OVERRIDE >>> + Offset(0x50), // LCTL - Link Control Register of (PCI Express* -> B00:D28:F04) + ASPM, 2, // 1:0, ASPM //Not referenced in code + , 2, + LNKD, 1, // Link Disable + // AMI_OVERRIDE >>> + Offset(0xA4), + D0ST, 2, +// AMI_OVERRIDE >>> + Offset(0x328), //PCIESTS1 - PCI Express Status 1 + , 19, + LNKS, 4, //Link Status (LNKSTAT) {22:19} + } + + //----------------------------------------- + // Runtime Device Power Management - Begin + //----------------------------------------- + // Note: + // Runtime Device Power Management can be achieved by using _PRx or _PSx or both + + // + // Name: PC05 + // Description: Declare a PowerResource object for RP05 slot device + // + PowerResource(PC05, 0, 0) + { + Name(_STA, One) + + Method(_ON, 0, Serialized) + { + +// AMI_OVERRIDE >>> +// \_SB.PCI0.RP05.PEGP.HGON() + \_SB.PCI0.RP05.PEGP.SGON() + Store(0x07, CMDR) + Store(0, D0ST) + + If(LEqual(VEID,0x10DE)) + { + Store(HYSS, NVID) + } + If(LEqual(VEID,0x1002)) + { + Store(HYSS, ATID) + } +// AMI_OVERRIDE <<< + Store(One, _STA) + } + + Method(_OFF, 0, Serialized) + { + +// AMI_OVERRIDE >>> +// \_SB.PCI0.RP05.PEGP.HGOF() + \_SB.PCI0.RP05.PEGP.SGOF() +// AMI_OVERRIDE <<< + Store(Zero, _STA) + } + } //End of PowerResource(PC05, 0, 0) + + Name(_PR0,Package(){PC05}) + Name(_PR2,Package(){PC05}) + Name(_PR3,Package(){PC05}) + +// // +// // Name: _PS0 +// // Description: D0 Method for RP05 slot device +// // Input: Nothing +// // Return: Nothing +// // +// Method(_PS0, 0, Serialized) +// { +// +// \_SB.PCI0.RP05.PEGP.HGON() +// } +// +// // +// // Name: _PS3 +// // Description: D3 Method for RP05 slot device +// // Input: Nothing +// // Return: Nothing +// // +// Method(_PS3, 0, Serialized) +// { +// +// \_SB.PCI0.RP05.PEGP.HGOF() +// } + + Method(_S0W, 0) + { + Return(4) //D3cold is supported + } + + //----------------------------------------- + // Runtime Device Power Management - End + //----------------------------------------- + + Device(PEGP) { // (PCI Express* -> B00:D28:F04) Slot Device D0F0 + Name(_ADR, 0x00000000) + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // (PCI Express* -> B00:D28:F04) Slot Device D0F0 + + Device(PEGA) { // (PCI Express* -> B00:D28:F04) Slot Device D0F1 + Name(_ADR, 0x00000001) + + OperationRegion(ACAP, PCI_Config, \EECP,0x14) + Field(ACAP,DWordAcc, NoLock,Preserve) + { + Offset(0x10), + LCT1, 16, // Link Control register + } + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // (PCI Express* -> B00:D28:F04) Slot Device D0F1 +} +//AMI override begin +Scope(SG_ULT_RP_NUM.PEGP) +//Scope(\_SB.PCI0.RP05.PEGP) +//AMI override end +{ + Name (ONOF, 0x1) //Endpoint On-Off flag status. Assume Endpoint is ON by default {1-ON, 0-OFF} + Name (IVID, 0xFFFF) //Invalid Vendor ID + Name (ELCT, 0x00000000) + Name (HVID, 0x0000) + Name (HDID, 0x0000) + + OperationRegion (PCIS, PCI_Config, 0x00, 0xF0) + Field(PCIS, AnyAcc, Lock, Preserve) + { + Offset(0x0), + DVID, 16, + Offset(0xB), + CBCC, 8, + Offset(0x2C), + SVID, 16, + SDID, 16, + Offset(0x4C), + WVID, 16, + WDID, 16, + } + + OperationRegion(PCAP, PCI_Config, \EECP,0x14) + Field(PCAP,DWordAcc, NoLock,Preserve) + { + Offset(0x10), + LCTL, 16, // Link Control register + } + + Method (_INI) + { + //AMI override begin + Store (0x0, SG_ULT_RP_NUM.PEGP._ADR) + //Store (0x0, \_SB.PCI0.RP05.PEGP._ADR) + //AMI override end + } + +// AMI CHANGE BEGIN. + Method(SGON,0,Serialized) +// Method(HGON,0,Serialized) +// AMI CHANGE END. + { + + //AMI override begin + Store("SG_ULT_RP_NUM.PEGP._ON", Debug) + //Store("\_SB.PCI0.RP05.PEGP._ON", Debug) + //AMI override end + If (LEqual(CCHK(1), 0)) + { + Return () + } + + Store(1, ONOF) //Indicate Endpoint is in ON state + + //ACTION TODO: + //........................................................................................ + //While powering up the slot again, the only requirement is that the Reset# should be + //de-asserted 100ms after the power to slot is up (Standard requirement as per PCIe spec). + + //Note: + //Before power enable, and for 100ms after power enable, the reset should be in hold condition. + //The 100 ms time is given for power rails and clocks to become stable. + //So during this period, reset must not be released. + //........................................................................................ + + //Power on the dGPU card + SGPO(HLRS, 1) //Assert dGPU_HOLD_RST# {Hold the dGPU Reset} + SGPO(PWEN, 1) //Assert dGPU_PWR_EN# {Power on the dGPU} + + Sleep(300) // Wait for 300ms if dGPU_PWROK has h/w issues + + SGPO(HLRS, 0) //Deassert dGPU_HOLD_RST# {Release the dGPU Reset} + Sleep(100) // Wait for 100ms + + //Enable x4 Link + //This bit should already be set to 0 in the _Off method. But do it anyway. + Store(0,LNKD) + + //wait until link has trained to x4. Verify + While(LLess(LNKS,7)) + { + Sleep(1) + } + + // Re-store the DGPU SSID + Store(HVID,WVID) + Store(HDID,WDID) + + // Re-store the Link Control register - Common Clock Control and ASPM + Or(And(ELCT,0x0043),And(LCTL,0xFFBC),LCTL) +//AMI override begin + Or(And(ELCT,0x0043),And(SG_ULT_RP_NUM.PEGA.LCT1,0xFFBC),SG_ULT_RP_NUM.PEGA.LCT1) + //Or(And(ELCT,0x0043),And(\_SB.PCI0.RP05.PEGA.LCT1,0xFFBC),\_SB.PCI0.RP05.PEGA.LCT1) + +// Return () +// } + +// Method(_ON,0,Serialized) +// { + +// HGON() +//AMI override end + //Ask OS to do a PnP rescan +// AMI CHANGE BEGIN. +// Notify(SG_ULT_RP_NUM,0) +// AMI CHANGE END. + +// AMI CHANGE BEGIN. + Return (1) +// AMI CHANGE END. + } + +// AMI CHANGE BEGIN. +// Method(HGOF,0,Serialized) + Method(SGOF,0,Serialized) +// AMI CHANGE END. + { + + If (LEqual(CCHK(0), 0)) + { + Return () + } + + Store(0, ONOF) //Indicate Endpoint is in OFF state + + //ACTION TODO: + //........................................................................................ + //To turn off the power to the slot, all you would need to do is assert the RESET# + //and then take off the power using the power enable GPIO. + //Once the power goes off, the clock request from the slot to the PCH is also turned off, + //so no clocks will be going to the PCIe slot anymore. + //........................................................................................ + + // Save the Link Control register + Store(LCTL,ELCT) + + // Save the DGPU SSID + Store(SVID,HVID) + Store(SDID,HDID) + + //Force disable the x4 link + Store(1, LNKD) + + //Wait till link is actually in disabled state + While(LNotEqual(LNKS,0)) + { + Sleep(1) + } + + //Power-off the dGPU card + SGPO(HLRS, 1) // Assert dGPU_HOLD_RST# (PERST#) {Hold the dGPU Reset} + SGPO(PWEN, 0) // Deassert dGPU_PWR_EN# {Power off the dGPU} +// AMI CHANGE BEGIN. +// Return () +// } +// +// Method(_OFF,0,Serialized) +// { +// +// HGOF() +// AMI CHANGE END. + //Ask OS to do a PnP rescan +// AMI CHANGE BEGIN. +// Notify(SG_ULT_RP_NUM,0) +// AMI CHANGE END. + +// AMI CHANGE BEGIN. + Return (0) +// AMI CHANGE END. + } + + Method(EPON, 0, Serialized) + { + Store(1, ONOF) //Indicate Endpoint is in ON state + + Return () + } + +// AMI CHANGE BEGIN. +// Method(_STA,0,Serialized) + Method(SGST,0,Serialized) +// AMI CHANGE END. + { + // + // Check SGMode and dGPU Present Detect GPIO for SG system + // + If(And(SGMD,0x0F)) + { + If(LNotEqual(SGGP,0x01)) + { + Return(0x0F) + } + + // To detect dGPU: Check Device is present and which belongs to display controllers type also. + If(LNotEqual(DVID,0xFFFF)) + { + If(LEqual(CBCC,0x3)) // Base Class Code 03h which is referring all types of display controllers + { + Return(0x0F) + } + } + + Return(0x00) + } + + // + // For non-SG system check for valid Vendor Id + // + If(LNotEqual(DVID,0xFFFF)) + { + Return(0x0F) + } + Return(0x00) + } + + + Method(_DOD,0) + { + Return (\_SB.PCI0.GFX0._DOD()) + } + + + Device(DD01) + { + Method(_ADR,0,Serialized) + { + Return(\_SB.PCI0.GFX0.DD01._ADR()) + } + + // Device Current State. + Method(_DCS,0) + { + + } + + // Device Get State. + + Method(_DGS,0) + { + // Return the Next State. + Return(\_SB.PCI0.GFX0.DD01._DGS()) + } + + // Device Set State. + + // _DSS Table: + // + // BIT31 BIT30 Execution + // 0 0 Don't implement. + // 0 1 Cache change. Nothing to Implement. + // 1 0 Don't Implement. + // 1 1 Display Switch Complete. Implement. + + Method(_DSS,1) + { + // Do nothing here in the OpRegion model. OEMs may choose to + // update internal state if necessary. + } + } + + Device(DD02) + { + Method(_ADR,0,Serialized) + { + Return(\_SB.PCI0.GFX0.DD02._ADR()) + } + + // Device Current State. + + Method(_DCS,0) + { + // Get the Current Display State. + Return(\_SB.PCI0.GFX0.DD02._DCS()) + } + + // Device Get State. + + Method(_DGS,0) + { + // Return the Next State. + Return(\_SB.PCI0.GFX0.DD02._DGS()) + } + + // Device Set State. + + Method(_DSS,1) + { + // Do nothing here in the OpRegion model. OEMs may choose to + // update internal state if necessary. + } + +/* + Method(_DDC,1) + { + If(Lor(LEqual(\_SB.PCI0.GFX0.PHED,1),LEqual(\_SB.PCI0.GFX0.PHED,2))) + { + Name(DDC2,Buffer (256) {0x0}) + Store(\_SB.PCI0.GFX0.BDDC,DDC2) + Return(DDC2) + } + Return(Buffer(256){0x0}) + } +*/ + Method(_BCL,0) + { + Return(\_SB.PCI0.GFX0.DD02._BCL()) + } + + Method(_BQC,0) + { + Return(\_SB.PCI0.GFX0.DD02._BQC()) + } + + Method(_BCM,1) + { + Return(\_SB.PCI0.GFX0.DD02._BCM(Arg0)) + } + + } + + Device(DD03) + { + Method(_ADR,0,Serialized) + { + Return(\_SB.PCI0.GFX0.DD03._ADR()) + } + + // Device Current State. + + Method(_DCS,0) + { + // Get the Current Display State. + } + + // Device Get State. + + Method(_DGS,0) + { + // Return the Next State. + Return(\_SB.PCI0.GFX0.DD03._DGS()) + } + + // Device Set State. + + Method(_DSS,1) + { + // Do nothing here in the OpRegion model. OEMs may choose to + // update internal state if necessary. + } + } + + Device(DD04) + { + Method(_ADR,0,Serialized) + { + Return(\_SB.PCI0.GFX0.DD04._ADR()) + } + + // Device Current State. + + Method(_DCS,0) + { + // Get the Current Display State. + } + + // Device Get State. + + Method(_DGS,0) + { + // Return the Next State. + Return(\_SB.PCI0.GFX0.DD04._DGS()) + } + + // Device Set State. + + Method(_DSS,1) + { + // Do nothing here in the OpRegion model. OEMs may choose to + // update internal state if necessary. + } + + } + + Device(DD05) + { + Method(_ADR,0,Serialized) + { + Return(\_SB.PCI0.GFX0.DD05._ADR()) + } + + // Device Current State. + + Method(_DCS,0) + { + // Get the Current Display State. + } + + // Device Get State. + + Method(_DGS,0) + { + // Return the Next State. + Return(\_SB.PCI0.GFX0.DD05._DGS()) + } + + // Device Set State. + + Method(_DSS,1) + { + // Do nothing here in the OpRegion model. OEMs may choose to + // update internal state if necessary. + } + } + + Device(DD06) + { + Method(_ADR,0,Serialized) + { + Return(\_SB.PCI0.GFX0.DD06._ADR()) + } + + // Device Current State. + + Method(_DCS,0) + { + // Get the Current Display State. + } + + // Device Get State. + + Method(_DGS,0) + { + // Return the Next State. + Return(\_SB.PCI0.GFX0.DD06._DGS()) + } + + // Device Set State. + + Method(_DSS,1) + { + // Do nothing here in the OpRegion model. OEMs may choose to + // update internal state if necessary. + } + } + + Device(DD07) + { + Method(_ADR,0,Serialized) + { + Return(\_SB.PCI0.GFX0.DD07._ADR()) + } + + // Device Current State. + + Method(_DCS,0) + { + // Get the Current Display State. + } + + // Device Get State. + + Method(_DGS,0) + { + // Return the Next State. + Return(\_SB.PCI0.GFX0.DD07._DGS()) + } + + // Device Set State. + + Method(_DSS,1) + { + // Do nothing here in the OpRegion model. OEMs may choose to + // update internal state if necessary. + } + } + + Device(DD08) + { + Method(_ADR,0,Serialized) + { + Return(\_SB.PCI0.GFX0.DD08._ADR()) + } + + // Device Current State. + + Method(_DCS,0) + { + // Get the Current Display State. + } + + // Device Get State. + + Method(_DGS,0) + { + // Return the Next State. + Return(\_SB.PCI0.GFX0.DD08._DGS()) + } + + // Device Set State. + + Method(_DSS,1) + { + // Do nothing here in the OpRegion model. OEMs may choose to + // update internal state if necessary. + } + } + + + // GPIO Read + // Arg0 = GPIO No + GPIO active info. {BIT7 => (1:Active, 0: Not active), BIT6:0 => GPIO No} + Method (SGPI,1,Serialized) + { + If(And(SGMD,0x0F)) + { + If(LEqual(SGGP,0x01)) + { + ShiftRight (Arg0, 7, Local1) //GPIO active info + And(Arg0, 0x7F, Arg0) //GPIO No + + // Read the GPIO [GPI_LVL] + // Arg0 - GPIO Pin number to read + If(LLessEqual(Arg0, 94)){ + Store( Add(Add(\GBAS,0x100) , Multiply(Arg0,0x08)),Local0 ) + OperationRegion(LGPI, SystemIo, Local0, 8) + Field(LGPI, ByteAcc, NoLock, Preserve) { + Offset(0x0), + , 30, + TEMP, 1 + } + + Store(TEMP, Local2) + } + + // + // Check if Active Low + // + If (LEqual(Local1,0)) + { + Not(Local2, Local2) + } + + Return(And(Local2,0x01)) + } + } + + Return(0) + } + + + // GPIO Write + // Arg0 = GPIO No + GPIO active info. {BIT7 => (1:Active, 0: Not active), BIT6:0 => GPIO No} + // Arg1 = Value (0/1) + Method (SGPO,2,Serialized) + { + If(And(SGMD,0x0F)) + { + If(LEqual(SGGP,0x01)) + { + ShiftRight (Arg0, 7, Local1) //GPIO active info + And(Arg0, 0x7F, Arg0) //GPIO No + + // + // Check if Active Low + // + If (LEqual(Local1,0)) + { + Not(Arg1, Arg1) + } + + And (Arg1, 0x01, Arg1) + + // Program the GPIO [GPO_LVL] + // Arg0 - GPIO Pin number to write + // Arg1 - Value to be written + If(LLessEqual(Arg0, 94)){ + Store( Add(Add(\GBAS,0x100) , Multiply(Arg0,0x08)),Local0 ) + OperationRegion(LGPI, SystemIo, Local0, 8) + Field(LGPI, ByteAcc, NoLock, Preserve) { + Offset(0x0), + , 31, + TEMP, 1 + } + + Store(Arg1,TEMP) + } + } + } + } + + // + // Name: CCHK + // Description: Function to check whether _ON/_OFF sequence is allowed to execute for the given RP05 controller or not + // Input: Arg0 -> 0 means _OFF sequence, 1 means _ON sequence + // Return: 0 - Don't execute the flow, 1 - Execute the flow + // + Method(CCHK,1) + { + + //Check for RP05 controller presence + If(LEqual(PVID, IVID)) + { + + Return(0) + } + + //If Endpoint is not present[already disabled] before executing _OFF then don't call the _OFF method + //If Endpoint is present[already enabled] before executing _ON then don't call the _ON method + If(LEqual(Arg0, 0)) + { + //_OFF sequence condition check + If(LEqual(ONOF, 0)) + { + + Return(0) + } + } + ElseIf(LEqual(Arg0, 1)) + { + //_ON sequence condition check + If(LEqual(ONOF, 1)) + { + + Return(0) + } + } + + + Return(1) + } // End of Method(CCHK,1) + +} diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgSsdtPch.asl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgSsdtPch.asl new file mode 100644 index 0000000..e65777c --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Pch/SgSsdtPch.asl @@ -0,0 +1,43 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - SG Reference Code *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +DefinitionBlock ( + "Sg.aml", + "SSDT", + 1, + "SgRef", + "SgPch", + 0x1000 + ) +{ + External(P8XH, MethodObj) + External(GPRW, MethodObj) + //AMI override begin + //Include("SgDgpuPch.ASL") + #include <SgDgpuPch.ASL> + //AMI override end +} diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTables.inf b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTables.inf new file mode 100644 index 0000000..0aaad00 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTables.inf @@ -0,0 +1,69 @@ +## @file +# Component description file for the ACPI tables +# +#@copyright +# Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# + + +[defines] +BASE_NAME = SgAcpiTables +FILE_GUID = CACB3817-81E6-497e-87FF-C8FA8F24EC28 +COMPONENT_TYPE = ACPITABLE +FFS_EXT = .ffs + +[sources.common] + SgSsdt.ASL + +[libraries.common] + +[includes.common] + . + $(EFI_SOURCE) + $(EFI_SOURCE)/Include + $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EFI_SOURCE)/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework +# +# Typically the sample code referenced will be available in the code base already +# So keep this include at the end to defer to the source base definition +# and only use the sample code definition if source base does not include these files. +# + $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode/Include + +# +# Edk II Glue Library, some hearder are included by R9 header so have to include +# + + $(EFI_SOURCE) + $(EFI_SOURCE)/Framework + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + +[nmake.common] diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTablesPeg.cif b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTablesPeg.cif new file mode 100644 index 0000000..85524cd --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTablesPeg.cif @@ -0,0 +1,12 @@ +<component> + name = "SgAcpiTablesPeg" + category = ModulePart + LocalRoot = "ReferenceCode\Chipset\SystemAgent\AcpiTables\SwitchableGraphics\Peg\" + RefName = "SgAcpiTablesPeg" +[files] +"SgAcpiTablesPeg.sdl" +"SgAcpiTablesPeg.mak" +"SgAcpiTables.inf" +"SgDgpu.asl" +"SgSsdt.asl" +<endComponent> diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTablesPeg.mak b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTablesPeg.mak new file mode 100644 index 0000000..e67f4a0 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTablesPeg.mak @@ -0,0 +1,63 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: SgAcpiTables.mak +# +# Description: MAK file for the ModulePart:SgAcpiTables +# +# +#<AMI_FHDR_END> +#************************************************************************* +EDK: SGPEGASL + +SGPEGASL: $(BUILD_DIR)\SGACPIPEG.ffs + +ALLSGPEGSEC = $(BUILD_DIR)\SGACPIPEG.sec + +!IF "$(ACPIPLATFORM_ASL_COMPILER)"=="" +!ERROR It is an invalid path, please check your ASL compiler path. +!ENDIF + +IASL = $(ACPIPLATFORM_ASL_COMPILER) + +#-----------------------------------------------------------------------# +# Process SG asl files +#-----------------------------------------------------------------------# + +$(BUILD_DIR)\SgSsdt.asl : $(SGACPIPEG_DIR)\SgSsdt.ASL \ + $(SGACPIPEG_DIR)\SgDgpu.ASL + $(CP) /I$(SGACPIPEG_DIR) /C $(SGACPIPEG_DIR)\$(@F) > $@ +# include the token.h if needed to check for SDL flags +# /FItoken.h + +SGAcpiTablesPeg_Includes = \ + $(SGACPIPEG_DIR)\ + +$(BUILD_DIR)\SgSsdt.aml: $(BUILD_DIR)\SgSsdt.asl + $(SILENT)$(IASL) -I $(SGAcpiTablesPeg_Includes) -p $@ $** + +$(ALLSGPEGSEC): $(BUILD_DIR)\SgSsdt.aml + $(GENSECTION) -I $** -O $@ -S EFI_SECTION_RAW + +$(BUILD_DIR)\SGACPIPEG.ffs: $(ALLSGPEGSEC) $(SGACPIPEG_DIR)\SgAcpiTablesPeg.mak + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=CACB3817-81E6-497e-87FF-C8FA8F24EC28\ + TYPE=EFI_FV_FILETYPE_FREEFORM \ + FFS_CHECKSUM=1\ + RAWFILE=$(ALLSGPEGSEC) FFSFILE=$(BUILD_DIR)\SGACPIPEG.ffs COMPRESS=0 NAME=SGACPIPEG + diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTablesPeg.sdl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTablesPeg.sdl new file mode 100644 index 0000000..1f2c571 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgAcpiTablesPeg.sdl @@ -0,0 +1,25 @@ +TOKEN + Name = "SgAcpiTablesPeg_SUPPORT" + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Help = "Main switch to enable SgAcpiTablesPeg support in Project" + Token = "SwitchableGraphics_SUPPORT" "=" "1" +End + +MODULE + Help = "Includes SgAcpiTablesPeg.mak to Project" + File = "SgAcpiTablesPeg.mak" +End + +PATH + Name = "SGACPIPEG_DIR" +End + +ELINK + Name = "$(BUILD_DIR)\SGACPIPEG.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgDgpu.asl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgDgpu.asl new file mode 100644 index 0000000..1e63dc4 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgDgpu.asl @@ -0,0 +1,1693 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - SG Reference Code *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2010 - 2013 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +External(\_SB.PCI0.GFX0._DOD, MethodObj) +External(\_SB.PCI0.GFX0.DD01._ADR, MethodObj) +External(\_SB.PCI0.GFX0.DD02._ADR, MethodObj) +External(\_SB.PCI0.GFX0.DD03._ADR, MethodObj) +External(\_SB.PCI0.GFX0.DD04._ADR, MethodObj) +External(\_SB.PCI0.GFX0.DD05._ADR, MethodObj) +External(\_SB.PCI0.GFX0.DD06._ADR, MethodObj) +External(\_SB.PCI0.GFX0.DD07._ADR, MethodObj) +External(\_SB.PCI0.GFX0.DD08._ADR, MethodObj) + +External(\_SB.PCI0.GFX0.DD01._DGS, MethodObj) +External(\_SB.PCI0.GFX0.DD02._DGS, MethodObj) +External(\_SB.PCI0.GFX0.DD03._DGS, MethodObj) +External(\_SB.PCI0.GFX0.DD04._DGS, MethodObj) +External(\_SB.PCI0.GFX0.DD05._DGS, MethodObj) +External(\_SB.PCI0.GFX0.DD06._DGS, MethodObj) +External(\_SB.PCI0.GFX0.DD07._DGS, MethodObj) +External(\_SB.PCI0.GFX0.DD08._DGS, MethodObj) + +External(\_SB.PCI0.GFX0.DD02._DCS, MethodObj) + +External(\_SB.PCI0.GFX0.DD02._BCL, MethodObj) +External(\_SB.PCI0.GFX0.DD02._BQC, MethodObj) +External(\_SB.PCI0.GFX0.DD02._BCM, MethodObj) +External(\_SB.PCI0.PEG0, DeviceObj) +External(\_SB.PCI0.PEG0.PEGP, DeviceObj) +External(\_SB.PCI0.PEG0.PEGP._ADR) +External(\EECP) +External(\XBAS) +External(\GBAS) +External(\HLRS) +External(\PWEN) +External(\PWOK) +External(\SGMD) +External(\SGGP) +External(PNHM, IntObj) +External(P0UB, IntObj) +External(PCSL, IntObj) +External(SC7A, IntObj) +//AMI override begin + +External(\EBAS) +External(\HYSS) +//AMI override begin end +Scope(\_SB.PCI0.PEG0) +//AMI override begin +{ + OperationRegion (MSID, SystemMemory, EBAS, 0x50) + Field(MSID, DWordAcc, Lock, Preserve) + { + VEID, 16, + Offset(0x40), + NVID, 32, + offset(0x4c), + ATID, 32, + } +//AMI override begin end + // Define a Memory Region that will allow access to the PEG root port + // Register Block. + // + //OperationRegion(RPCI,PCI_Config,0x00,0xF0) + //Field(RPCI,DWordAcc,Lock,Preserve) + //{ + //} + + OperationRegion(RPCX,SystemMemory,Add(\XBAS,0x8000),0x1000) + Field(RPCX,ByteAcc,NoLock,Preserve) + { + Offset(0), + PVID, 16, + PDID, 16, +// AMI_OVERRIDE >>> + Offset(0x4), + CMDR, 8, + Offset(0x84), + D0ST, 2, +// AMI_OVERRIDE >>> + Offset(0xAC), // LCAP - Link Capabilities Register + , 4, + CMLW, 6, // 9:4, Max Link Width + Offset(0xB0), // LCTL - Link Control Register + ASPM, 2, // 1:0, ASPM //Not referenced in code + , 2, + LNKD, 1, // Link Disable + Offset(0x11A), + , 1, + VCNP, 1, //VC0RSTS.VC0NP + Offset(0x214), + , 16, + LNKS, 4, //PEGSTS.LKS + Offset(0x504), + , 16, + PCFG, 2, //FUSESCMN.PEG1CFGSEL + Offset(0x508), + TREN, 1, //TRNEN.TREN + Offset(0x91C), + , 31, + BSP1, 1, + Offset(0x93C), + , 31, + BSP2, 1, + Offset(0x95C), + , 31, + BSP3, 1, + Offset(0x97C), + , 31, + BSP4, 1, + Offset(0x99C), + , 31, + BSP5, 1, + Offset(0x9BC), + , 31, + BSP6, 1, + Offset(0x9DC), + , 31, + BSP7, 1, + Offset(0x9FC), + , 31, + BSP8, 1, + Offset(0xC20), + , 4, + AFES, 2, //AFEOVR.RXSQDETOVR + Offset(0xD0C), + , 20, + LREV, 1, //PEGTST.LANEREVSTS + } + + Method(RBP0,1) // ReadBytePEG0 + { + // Function to read pcie byte of Peg0 [0x00/0x01/0x00] + // + // Arg0 : The offset of pcie config space to be read + // + Store( Add(Add(\XBAS,0x8000), Arg0) ,Local7) + OperationRegion(PCI0, SystemMemory, Local7, 1) + Field(PCI0, ByteAcc,NoLock,Preserve) + { + TEMP, 8 + } + Return(TEMP) + } // End of Method(RBP0,1) + + Method(WBP0,2) // WriteBytePEG0 + { + // Function to write pcie byte of Peg0 [0x00/0x01/0x00] + // + // Arg0 : The offset of pcie config space to be written + // Arg1 : Value to be written + // + Store( Add(Add(\XBAS,0x8000), Arg0) ,Local7) + OperationRegion(PCI0, SystemMemory, Local7, 1) + Field(PCI0, ByteAcc,NoLock,Preserve) + { + TEMP, 8 + } + Store(Arg1,TEMP) + Return(TEMP) + } // End of Method(WBP0,2) + +// Method(BSPR,2) +// { + // Function to set/reset powerdown the bundles + // + // Arg0 : The zero based bundle number + // Arg1 : Value to be written + // +// Store( Add(Add(Add(\XBAS,0x8000), 0x91C) , Multiply(Arg0,0x20)),Local7) +// OperationRegion(PCI0, SystemMemory, Local7, 4) +// Field(PCI0, DWordAcc,NoLock,Preserve) +// { +// Offset(0x0), +// ,31, +// TEMP, 1 +// } +// Store(Arg1,TEMP) +// } // End of Method(BSPR,2) + + Method(C7OK,1) + { + // Function to set/reset C7 Allowed + // + // Arg0 : Value to be written + // + + // + // Memory window to the Host Bus registers + // + OperationRegion(MWHB,SystemMemory,\XBAS,0x1000) + Field(MWHB,DWordAcc,NoLock,Preserve) + { + Offset(0x48), // MCHBAR (0:0:0:48) + MHEN, 1, // Enable + , 14, + MHBR, 17, // MCHBAR [31:15] + } + + // + // Memory window to the registers starting at MCHBAR+5000h. + // + OperationRegion (MBAR, SystemMemory, Add(ShiftLeft(MHBR,15),0x5000), 0x1000) + Field (MBAR, ByteAcc, NoLock, Preserve) + { + Offset (0xDA8), // BIOS_RESET_CPL (MCHBAR+0x5da8) + , 2, // + C7AD, 1, // C7 Allowed [2:2] + } + + Store(Arg0,C7AD) + } // End of Method(C7OK,1) + + //----------------------------------------- + // Runtime Device Power Management - Begin + //----------------------------------------- + // Note: + // Runtime Device Power Management can be achieved by using _PRx or _PSx or both + + // + // Name: PG00 + // Description: Declare a PowerResource object for PEG0 slot device + // + PowerResource(PG00, 0, 0) + { + Name(_STA, One) + + Method(_ON, 0, Serialized) + { + // + // SA:InternalOnlyBegin + // + Store("\_SB.PCI0.PEG0.PG00._ON", Debug) + // + // SA:InternalOnlyEnd + // + +// AMI_OVERRIDE >>> +// \_SB.PCI0.PEG0.PEGP._ON() + \_SB.PCI0.PEG0.PEGP.SGON() + Store(0x07, CMDR) + Store(0, D0ST) + + If(LEqual(VEID,0x10DE)) + { + Store(HYSS, NVID) + } + If(LEqual(VEID,0x1002)) + { + Store(HYSS, ATID) + } +// AMI_OVERRIDE >>> + Store(One, _STA) + } + + Method(_OFF, 0, Serialized) + { + // + // SA:InternalOnlyBegin + // + Store("\_SB.PCI0.PEG0.PG00._OFF", Debug) + // + // SA:InternalOnlyEnd + // +// AMI_OVERRIDE >>> +// \_SB.PCI0.PEG0.PEGP.HGOF() + \_SB.PCI0.PEG0.PEGP.SGOF() +// AMI_OVERRIDE >>> + Store(Zero, _STA) + } + } //End of PowerResource(PG00, 0, 0) + + Name(_PR0,Package(){PG00}) + Name(_PR2,Package(){PG00}) + Name(_PR3,Package(){PG00}) + +// // +// // Name: _PS0 +// // Description: D0 Method for PEG0 slot device +// // Input: Nothing +// // Return: Nothing +// // +// Method(_PS0, 0, Serialized) +// { +// // +// // SA:InternalOnlyBegin +// // +// Store("\_SB.PCI0.PEG0._PS0", Debug) +// // +// // SA:InternalOnlyEnd +// // +// +// \_SB.PCI0.PEG0.PEGP.HGON() +// } +// +// // +// // Name: _PS3 +// // Description: D3 Method for PEG0 slot device +// // Input: Nothing +// // Return: Nothing +// // +// Method(_PS3, 0, Serialized) +// { +// // +// // SA:InternalOnlyBegin +// // +// Store("\_SB.PCI0.PEG0._PS3", Debug) +// // +// // SA:InternalOnlyEnd +// // +// +// \_SB.PCI0.PEG0.PEGP.HGOF() +// } + + Method(_S0W, 0) + { + Return(4) //D3cold is supported + } + + //----------------------------------------- + // Runtime Device Power Management - End + //----------------------------------------- + + Device(PEGA) { // P.E.G. Device D0F1 + Name(_ADR, 0x00000001) + + OperationRegion(ACAP, PCI_Config, \EECP,0x14) + Field(ACAP,DWordAcc, NoLock,Preserve) + { + Offset(0x10), + LCT1, 16, // Link Control register + } + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "P.E.G. Device D0F1" +} + +Scope(\_SB.PCI0.PEG0.PEGP) +{ + Name (ONOF, 0x1) //Endpoint On-Off flag status. Assume Endpoint is ON by default {1-ON, 0-OFF} + Name (IVID, 0xFFFF) //Invalid Vendor ID + Name (TCNT, 0) + Name (LDLY, 100) //100 ms + Name (ELCT, 0x00000000) + Name (HVID, 0x0000) + Name (HDID, 0x0000) + Name (FBDL, 0x0) //BndlPwrdnFirst + Name (MBDL, 0x0) //MaxBndlPwrdnCount + Name (CBDL, 0x0) //BndlPwrdnCount + Name (HSTR, 0x0) //HwStrap + Name (UULN, 0x0) //UnusedLanes + Name (INDX, 0x0) + Name (POFF, 0x0) + Name (PLEN, 0x0) + Name (PDAT, 0x0) + Name (WLSB, 0x0) + Name (WMSB, 0x0) + Name (DMLW, 0x0) + Name (DAT0, Buffer() { + //Offset Length Data + + //Save-Restore Any Controller fields + 0xD8,0x0D, 0x4, 0x00,0x00,0x00,0x00, + 0x00,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x04,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x08,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x0C,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x10,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x0C,0x08, 0x4, 0x00,0x00,0x00,0x00, + 0x20,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x24,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x28,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x2C,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x30,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x2C,0x08, 0x4, 0x00,0x00,0x00,0x00, + 0x40,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x44,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x48,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x4C,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x50,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x4C,0x08, 0x4, 0x00,0x00,0x00,0x00, + 0x60,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x64,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x68,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x6C,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x70,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x6C,0x08, 0x4, 0x00,0x00,0x00,0x00, + 0x80,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x84,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x88,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x8C,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x90,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x8C,0x08, 0x4, 0x00,0x00,0x00,0x00, + 0xA0,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0xA4,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0xA8,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0xAC,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0xB0,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0xAC,0x08, 0x4, 0x00,0x00,0x00,0x00, + 0xC0,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0xC4,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0xC8,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0xCC,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0xD0,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0xCC,0x08, 0x4, 0x00,0x00,0x00,0x00, + 0xE0,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0xE4,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0xE8,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0xEC,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0xF0,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0xEC,0x08, 0x4, 0x00,0x00,0x00,0x00, + 0x30,0x0C, 0x4, 0x00,0x00,0x00,0x00, + 0x00,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x04,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x08,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x0C,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xA0,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xA4,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xA8,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xAC,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xB0,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xB4,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xB8,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xBC,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xC0,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xC4,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xC8,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xCC,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xD0,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xD4,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xD8,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xDC,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xE0,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xE4,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xE8,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xEC,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xF0,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xF4,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xF8,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0xFC,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x10,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x14,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x18,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x1C,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x20,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x24,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x28,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x2C,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x30,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x34,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x38,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x3C,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x40,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x44,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x48,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x4C,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x50,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x54,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x58,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x5C,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x60,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x64,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x68,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x6C,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x70,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x74,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x78,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x7C,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x80,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x84,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x88,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x8C,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x90,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x94,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x98,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x9C,0x0A, 0x4, 0x00,0x00,0x00,0x00, + 0x18,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x38,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x58,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x78,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0x98,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0xB8,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0xD8,0x09, 0x4, 0x00,0x00,0x00,0x00, + 0xF8,0x09, 0x4, 0x00,0x00,0x00,0x00, + + //Save-Restore Appropriate Controller fields + 0x24,0x02, 0x4, 0x00,0x00,0x00,0x00, + 0xf8,0x01, 0x4, 0x00,0x00,0x00,0x00, + 0x60,0x02, 0x4, 0x00,0x00,0x00,0x00, + 0x28,0x0C, 0x4, 0x00,0x00,0x00,0x00, + 0x38,0x0C, 0x4, 0x00,0x00,0x00,0x00, + 0x14,0x0D, 0x4, 0x00,0x00,0x00,0x00, + 0x0C,0x00, 0x1, 0x00, + 0x19,0x00, 0x1, 0x00, + 0x1A,0x00, 0x1, 0x00, + 0x1C,0x00, 0x1, 0x00, + 0x1D,0x00, 0x1, 0x00, + 0x20,0x00, 0x2, 0x00,0x00, + 0x22,0x00, 0x2, 0x00,0x00, + 0x24,0x00, 0x2, 0x00,0x00, + 0x26,0x00, 0x2, 0x00,0x00, + 0x28,0x00, 0x4, 0x00,0x00,0x00,0x00, + 0x2C,0x00, 0x4, 0x00,0x00,0x00,0x00, + 0x3C,0x00, 0x1, 0x00, + 0x3D,0x00, 0x1, 0x00, + 0x3E,0x00, 0x2, 0x00,0x00, + 0x84,0x00, 0x4, 0x00,0x00,0x00,0x00, + 0x8C,0x00, 0x4, 0x00,0x00,0x00,0x00, + 0x92,0x00, 0x2, 0x00,0x00, + 0x94,0x00, 0x4, 0x00,0x00,0x00,0x00, + 0x98,0x00, 0x2, 0x00,0x00, + 0xA2,0x00, 0x2, 0x00,0x00, + 0xA8,0x00, 0x2, 0x00,0x00, + 0xAC,0x00, 0x4, 0x00,0x00,0x00,0x00, + 0xB0,0x00, 0x2, 0x00,0x00, + 0xB4,0x00, 0x4, 0x00,0x00,0x00,0x00, + 0xBC,0x00, 0x2, 0x00,0x00, + 0xC8,0x00, 0x2, 0x00,0x00, + 0xD0,0x00, 0x2, 0x00,0x00, + 0xEC,0x00, 0x4, 0x00,0x00,0x00,0x00, + 0x14,0x01, 0x4, 0x00,0x00,0x00,0x00, + 0x44,0x01, 0x4, 0x00,0x00,0x00,0x00, + 0x50,0x01, 0x4, 0x00,0x00,0x00,0x00, + 0x58,0x01, 0x4, 0x00,0x00,0x00,0x00, + 0x5C,0x01, 0x4, 0x00,0x00,0x00,0x00, + 0xFC,0x01, 0x4, 0x00,0x00,0x00,0x00, + 0x00,0x02, 0x4, 0x00,0x00,0x00,0x00, + 0x04,0x02, 0x4, 0x00,0x00,0x00,0x00, + 0x08,0x02, 0x4, 0x00,0x00,0x00,0x00, + 0x28,0x02, 0x4, 0x00,0x00,0x00,0x00, + 0x2C,0x02, 0x4, 0x00,0x00,0x00,0x00, + 0x38,0x02, 0x4, 0x00,0x00,0x00,0x00, + 0x40,0x02, 0x4, 0x00,0x00,0x00,0x00, + 0x44,0x02, 0x4, 0x00,0x00,0x00,0x00, + 0x50,0x02, 0x4, 0x00,0x00,0x00,0x00, + 0x58,0x02, 0x4, 0x00,0x00,0x00,0x00, + 0x5C,0x02, 0x4, 0x00,0x00,0x00,0x00, + 0xD0,0x0C, 0x4, 0x00,0x00,0x00,0x00, + 0x34,0x0D, 0x4, 0x00,0x00,0x00,0x00, + 0xF4,0x00, 0x4, 0x00,0x00,0x00,0x00, + 0xA0,0x0D, 0x4, 0x00,0x00,0x00,0x00, + 0xA4,0x0D, 0x4, 0x00,0x00,0x00,0x00, + 0xA8,0x0D, 0x4, 0x00,0x00,0x00,0x00, + 0xAC,0x0D, 0x4, 0x00,0x00,0x00,0x00, + 0xB0,0x0D, 0x4, 0x00,0x00,0x00,0x00, + 0xB4,0x0D, 0x4, 0x00,0x00,0x00,0x00, + 0xB8,0x0D, 0x4, 0x00,0x00,0x00,0x00, + 0xBC,0x0D, 0x4, 0x00,0x00,0x00,0x00, + 0xCC,0x01, 0x4, 0x00,0x00,0x00,0x00, + 0x04,0x00, 0x2, 0x00,0x00, + + //Final field + 0xFF,0xFF, 0x4, 0xFF,0xFF,0xFF,0xFF //Last data + }) + + Name (DAT1, Buffer() { + //Offset Length Data + + //Save-Restore Any Controller fields + 0x06,0x00, 0x2, 0xFF,0xFF, + 0x1E,0x00, 0x2, 0xFF,0xFF, + 0xAA,0x00, 0x2, 0xFF,0xFF, + 0xC0,0x00, 0x4, 0xFF,0xFF,0xFF,0xFF, + 0xD2,0x00, 0x2, 0xFF,0xFF, + 0xC4,0x01, 0x4, 0xFF,0xFF,0xFF,0xFF, + 0xD0,0x01, 0x4, 0xFF,0xFF,0xFF,0xFF, + 0xF0,0x01, 0x4, 0xFF,0xFF,0xFF,0xFF, + 0x9C,0x0D, 0x4, 0xFF,0xFF,0xFF,0xFF, + 0xB2,0x00, 0x2, 0xFF,0xFF, + + //Final field + 0xFF,0xFF, 0x4, 0xFF,0xFF,0xFF,0xFF //Last data + }) + + OperationRegion (PCIS, PCI_Config, 0x00, 0xF0) + Field(PCIS, DWordAcc, Lock, Preserve) + { + Offset(0x0), + DVID, 16, + Offset(0x2C), + SVID, 16, + SDID, 16, + Offset(0x4C), + WVID, 16, + WDID, 16, + } + + OperationRegion( GPR, SystemIO, \GBAS, 0x60 ) + Field( GPR, ByteAcc, Lock, Preserve ) + { + Offset(0x0C), // GPIO, Level, Bank 0 + LVL0, 32, + Offset(0x38), // GPIO, Level, Bank 1 + LVL1, 32, + Offset(0x48), // GPIO, Level, Bank 2 + LVL2, 32, + } + + OperationRegion(PCAP, PCI_Config, \EECP,0x14) + Field(PCAP,DWordAcc, NoLock,Preserve) + { + Offset(0x0C), // Link Capabilities Register + , 4, + EMLW, 6, // 9:4, Max Link Width + Offset(0x10), + LCTL, 16, // Link Control register + } + + Method (_INI) + { + Store (0x0, \_SB.PCI0.PEG0.PEGP._ADR) + } + + //GetMaxBundles + Method(GMXB,0) + { + Store (PCFG, HSTR) //HwStrap + If (LEqual(HSTR, 3)) //SA_PEG_x16_x0_x0 + { + Store (8, Local0) + } + Else + { + Store (4, Local0) + } + + Return(Local0) + } + + //PowerUpAllBundles + Method(PUAB,0) + { + Store (0, FBDL) //BndlPwrdnFirst + Store (0, CBDL) //BndlPwrdnCount + Store (PCFG, HSTR) //HwStrap + If (LEqual(HSTR, 3)) //SA_PEG_x16_x0_x0 + { + Store (0, FBDL) + Store (8, CBDL) + } + Else + { + If(LEqual(LREV,0)) + { + Store (0, FBDL) + Store (4, CBDL) + } + Else + { + Store (4, FBDL) + Store (4, CBDL) + } + } + + Store (1, INDX) + If (LNotEqual(CBDL,0)) + { + While(LLessEqual(INDX, CBDL)) + { + If(LEqual(FBDL,0)) + { + Store (0, BSP1) + } + If(LEqual(FBDL,1)) + { + Store (0, BSP2) + } + If(LEqual(FBDL,2)) + { + Store (0, BSP3) + } + If(LEqual(FBDL,3)) + { + Store (0, BSP4) + } + If(LEqual(FBDL,4)) + { + Store (0, BSP5) + } + If(LEqual(FBDL,5)) + { + Store (0, BSP6) + } + If(LEqual(FBDL,6)) + { + Store (0, BSP7) + } + If(LEqual(FBDL,7)) + { + Store (0, BSP8) + } + Increment (FBDL) + Increment (INDX) + } + } + } // End of Method(PUAB,0) + + // PowerDownUnusedBundles + // Arg0 = BndlPwrdnCount + Method(PDUB,1) + { + Store (0, FBDL) //BndlPwrdnFirst + Store (Arg0, CBDL) //BndlPwrdnCount + If (LEqual(CBDL,0)) + { + // All lanes are used. Do nothing + Return + } + + If (LEqual(HSTR, 3)) //SA_PEG_x16_x0_x0 + { + If(LEqual(LREV,0)) + { + Store (Subtract(8, CBDL), FBDL) //8 - (UnusedLanes / 2) + } + Else + { + Store (0, FBDL) + } + } + Else + { + If(LEqual(LREV,0)) + { + Store (Subtract(4, CBDL), FBDL) //4 - (UnusedLanes / 2) + } + Else + { + Store (4, FBDL) + } + } + + Store (1, INDX) + While(LLessEqual(INDX, CBDL)) //< Check that bundles need to be powered down + { + If(LEqual(FBDL,0)) + { + Store (1, BSP1) + } + If(LEqual(FBDL,1)) + { + Store (1, BSP2) + } + If(LEqual(FBDL,2)) + { + Store (1, BSP3) + } + If(LEqual(FBDL,3)) + { + Store (1, BSP4) + } + If(LEqual(FBDL,4)) + { + Store (1, BSP5) + } + If(LEqual(FBDL,5)) + { + Store (1, BSP6) + } + If(LEqual(FBDL,6)) + { + Store (1, BSP7) + } + If(LEqual(FBDL,7)) + { + Store (1, BSP8) + } + Increment (FBDL) + Increment (INDX) + } + } // End of Method(PDUB,0) + + Method(SPP0,0) + { + Store (0, INDX) + While (1) + { + Store (DerefOf (Index(DAT0, INDX)), WLSB) + Increment (INDX) //Offset is 2 bytes long <First byte-LSB> + Store (DerefOf (Index(DAT0, INDX)), WMSB) + Increment (INDX) //Offset is 2 bytes long <Second byte-MSB> + Store (Or (ShiftLeft (WMSB, 8), WLSB), POFF) + Store (DerefOf (Index(DAT0, INDX)), PLEN) + Increment (INDX) //Length is 1 byte long + + If(LEqual(POFF,0xFFFF)) + { + Break + } + + While (LGreater(PLEN, 0)) + { + Store(RBP0(POFF), Index(DAT0, INDX)) + Increment (INDX) + Increment (POFF) + Decrement (PLEN) + } + } + } // End of Method(SPP0,0) + + Method(RPP0,0) + { + Store (0, INDX) + While (1) + { + Store (DerefOf (Index(DAT0, INDX)), WLSB) + Increment (INDX) //Offset is 2 bytes long <First byte-LSB> + Store (DerefOf (Index(DAT0, INDX)), WMSB) + Increment (INDX) //Offset is 2 bytes long <Second byte-MSB> + Store (Or (ShiftLeft (WMSB, 8), WLSB), POFF) + Store (DerefOf (Index(DAT0, INDX)), PLEN) + Increment (INDX) //Length is 1 byte long + + If(LEqual(POFF,0xFFFF)) + { + Break + } + + While (LGreater(PLEN, 0)) + { + WBP0(POFF, DerefOf (Index(DAT0, INDX))) + Increment (INDX) + Increment (POFF) + Decrement (PLEN) + } + } + } // End of Method(RPP0,0) + + Method(CLP0,0) + { + Store (0, INDX) + While (1) + { + Store (DerefOf (Index(DAT1, INDX)), WLSB) + Increment (INDX) //Offset is 2 bytes long <First byte-LSB> + Store (DerefOf (Index(DAT1, INDX)), WMSB) + Increment (INDX) //Offset is 2 bytes long <Second byte-MSB> + Store (Or (ShiftLeft (WMSB, 8), WLSB), POFF) + Store (DerefOf (Index(DAT1, INDX)), PLEN) + Increment (INDX) //Length is 1 byte long + + If(LEqual(POFF,0xFFFF)) + { + Break + } + + While (LGreater(PLEN, 0)) + { + WBP0(POFF, DerefOf (Index(DAT1, INDX))) + Increment (INDX) + Increment (POFF) + Decrement (PLEN) + } + } + } // End of Method(CLP0,0) + +// AMI CHANGE BEGIN. + Method(SGON,0,Serialized) +// Method(HGON,0,Serialized) +// AMI CHANGE END. + { + // + // SA:InternalOnlyBegin + // + P8XH(0,0xD6) + P8XH(1,0x00) + Store("\_SB.PCI0.PEG0.PEGP.HGON", Debug) + // + // SA:InternalOnlyEnd + // + + If (LEqual(CCHK(1), 0)) + { + // + // SA:InternalOnlyBegin + // + P8XH(0,0xD6) + P8XH(1,0xC0) + Store("\_SB.PCI0.PEG0.PEGP.HGON is not allowed to execute ", Debug) + // + // SA:InternalOnlyEnd + // + Return () + } + + Store(1, ONOF) //Indicate Endpoint is in ON state + + //Power on the dGPU card + SGPO(HLRS, 1) //Assert dGPU_HOLD_RST# + SGPO(PWEN, 1) //Assert dGPU_PWR_EN# + +// While(LNotEqual(SGPI(PWOK),1)) //Wait until dGPU_PWROK=1 +// { +// Sleep(1) +// } + + Sleep(300) // Wait for 300ms if dGPU_PWROK has h/w issues + + SGPO(HLRS, 0) //Deassert dGPU_HOLD_RST# + Sleep(100) // Wait for 100ms + + // Software clears BIOS_RESET_CPL.C7_ALLOWED + If (LGreaterEqual(PCSL, 4)) //C7 or above + { + If (LEqual(SC7A, 0x01)) //Run-time C7 Allowed feature setup value = Enabled + { + C7OK(0) + + // Restore the PEG0 PCIE registers + RPP0() + + // Clear the PEG0 errors + CLP0() + } + } + + //Program AFEOVR.RXSQDETOVR + //PCIe link disable for Switchable GFx + //Additional Power savings: Set 0:1:0 0xc20 BIT4 = 0 & BIT5 = 0 + Store(0, AFES) + + //Program BND*SPARE.BNDL_PWRDN + //PowerOff unused bundles for PEGs + //SA:RestrictedContent Ref: HSW_PCIe_HAS_1.0.docx [Table 15 - Bifurcation and reversal port and pin mappings] + If (LGreaterEqual(And(PNHM, 0xF), 0x3)) //(CpuSteppingId >= EnumHswC0) + { + If (LNotEqual(P0UB, 0x00)) + { + //PowerUpAllBundles + PUAB() + + //Get BndlPwrdnCount + If (LEqual (P0UB, 0xFF)) //AUTO + { + If (LGreater(CMLW, DMLW)) + { + Subtract (CMLW, DMLW, UULN) //UnusedLanes + } + Else + { + Store (0, UULN) //UnusedLanes + } + Store (Divide(UULN,2), CBDL) //BndlPwrdnCount + } + ElseIf (LNotEqual (P0UB, 0x00)) //1...8 bundles + { + Store (P0UB, CBDL) //BndlPwrdnCount + } + + //Get MaxBndlPwrdnCount + Store(GMXB(), MBDL) + + If (LGreater(CBDL, MBDL)) + { + Store(MBDL, CBDL) + } + + //PowerDownUnusedBundles + PDUB(CBDL) + } + } + +// AMI CHANGE BEGIN. + // Enable controller initial training + Store(1, TREN) +// AMI CHANGE END. + //Enable x16 Link + //This bit should already be set to 0 in the _Off method. But do it anyway. + Store(0,LNKD) +//AMI_OVERRIDE -->> When runnign a long run test (S3,S4,or _on/_off) with SG on two chips platform, it may happen to BSOD 0x9F. It got different fail rate on different platform. + //wait until link has trained to x16. Verify + While(LLess(LNKS,7)) + { + Sleep(1) + } +//AMI_OVERRIDE --<< When runnign a long run test (S3,S4,or _on/_off) with SG on two chips platform, it may happen to BSOD 0x9F. It got different fail rate on different platform. + +// AMI CHANGE BEGIN. + // Enable controller initial training + //Store(1, TREN) +// AMI CHANGE END. +//AMI_OVERRIDE -->> When runnign a long run test (S3,S4,or _on/_off) with SG on two chips platform, it may happen to BSOD 0x9F. It got different fail rate on different platform. +// // Wait until the VC negotiation is complete +// Store(0, TCNT) +// While(LLess(TCNT, LDLY)) +// { +// If(LEqual(VCNP,0)) +// { +// Break +// } +// +// Sleep(16) //In some OS one tick is equal to 1/64 second (15.625ms) +// Add(TCNT, 16, TCNT) +// } +//AMI_OVERRIDE --<< When runnign a long run test (S3,S4,or _on/_off) with SG on two chips platform, it may happen to BSOD 0x9F. It got different fail rate on different platform. + + // Re-store the DGPU SSID + Store(HVID,WVID) + Store(HDID,WDID) + + // Re-store the Link Control register - Common Clock Control and ASPM + Or(And(ELCT,0x0043),And(LCTL,0xFFBC),LCTL) + Or(And(ELCT,0x0043),And(\_SB.PCI0.PEG0.PEGA.LCT1,0xFFBC),\_SB.PCI0.PEG0.PEGA.LCT1) +// AMI CHANGE BEGIN. +// Return () +// } +// +// Method(_ON,0,Serialized) +// { + // + // SA:InternalOnlyBegin + // + Store("\_SB.PCI0.PEG0.PEGP._ON", Debug) + // + // SA:InternalOnlyEnd + // + +// HGON() +// AMI CHANGE END + //Ask OS to do a PnP rescan +// AMI CHANGE BEGIN. +// Notify(\_SB.PCI0.PEG0,0) +// AMI CHANGE END. + +// AMI CHANGE BEGIN. + Return (1) +// AMI CHANGE END. + } + +// AMI CHANGE BEGIN. +// Method(HGOF,0,Serialized) + Method(SGOF,0,Serialized) +// AMI CHANGE END. + { + // + // SA:InternalOnlyBegin + // + P8XH(0,0xD6) + P8XH(1,0x0F) + Store("\_SB.PCI0.PEG0.PEGP.HGOF", Debug) + // + // SA:InternalOnlyEnd + // + + If (LEqual(CCHK(0), 0)) + { + // + // SA:InternalOnlyBegin + // + P8XH(0,0xD6) + P8XH(1,0xCF) + Store("\_SB.PCI0.PEG0.PEGP.HGOF is not allowed to execute ", Debug) + // + // SA:InternalOnlyEnd + // + Return () + } + + Store(0, ONOF) //Indicate Endpoint is in OFF state + + // Save the Link Control register + Store(LCTL,ELCT) + + // Save the DGPU SSID + Store(SVID,HVID) + Store(SDID,HDID) + + // Save the Endpoint Max Link Width + Store(EMLW,DMLW) + + // Software sets BIOS_RESET_CPL.C7_ALLOWED + If (LGreaterEqual(PCSL, 4)) //C7 or above + { + If (LEqual(SC7A, 0x01)) //Run-time C7 Allowed feature setup value = Enabled + { + // Save the PEG0 PCIE registers + SPP0() + } + } + + //Force disable the x16 link + Store(1, LNKD) + + //Wait till link is actually in disabled state + Store(0, TCNT) + While(LLess(TCNT, LDLY)) + { + If(LEqual(LNKS,0)) + { + Break + } + + Sleep(16) //In some OS one tick is equal to 1/64 second (15.625ms) + Add(TCNT, 16, TCNT) + } +//AMI_OVERRIDE -->> When runnign a long run test (S3,S4,or _on/_off) with SG on two chips platform, it may happen to BSOD 0x9F. It got different fail rate on different platform. + While(LNotEqual(LNKS,0)) + { + Sleep(1) + } +//AMI_OVERRIDE --<< When runnign a long run test (S3,S4,or _on/_off) with SG on two chips platform, it may happen to BSOD 0x9F. It got different fail rate on different platform. + + //Program AFEOVR.RXSQDETOVR + //PCIe link disable for Switchable GFx + //Additional Power savings: Set 0:1:0 0xc20 BIT4 = 0 & BIT5 = 1 + Store(2, AFES) + + // PowerOff all bundles for PEGs + // Program BND*SPARE.BNDL_PWRDN + // SA:RestrictedContent Ref: HSW_PCIe_HAS_1.0.docx [Table 15 - Bifurcation and reversal port and pin mappings] + If (LGreaterEqual(And(PNHM, 0xF), 0x3)) //(CpuSteppingId >= EnumHswC0) + { + If (LNotEqual(P0UB, 0x00)) + { + //Get MaxBndlPwrdnCount + Store(GMXB(), MBDL) + + //PowerDownUnusedBundles + PDUB(MBDL) + } + } + + // Software sets BIOS_RESET_CPL.C7_ALLOWED + If (LGreaterEqual(PCSL, 4)) //C7 or above + { + If (LEqual(SC7A, 0x01)) //Run-time C7 Allowed feature setup value = Enabled + { + C7OK(1) + } + } + + //Power-off the dGPU card + SGPO(HLRS, 1) // Assert dGPU_HOLD_RST# (PERST#) + SGPO(PWEN, 0) // Deassert dGPU_PWR_EN# +// AMI CHANGE BEGIN. +// Return () +// } +// +// Method(_OFF,0,Serialized) +// { + // + // SA:InternalOnlyBegin + // + Store("\_SB.PCI0.PEG0.PEGP._OFF", Debug) + // + // SA:InternalOnlyEnd + // + +// HGOF() +// +// AMI CHANGE BEGIN. + //Ask OS to do a PnP rescan +// AMI CHANGE BEGIN. +// Notify(\_SB.PCI0.PEG0,0) +// AMI CHANGE END. + +// AMI CHANGE BEGIN + Return (0) +// AMI CHANGE END. + } + + Method(EPON, 0, Serialized) + { + Store(1, ONOF) //Indicate Endpoint is in ON state + + Return () + } + +// AMI CHANGE BEGIN. +// Method(_STA,0,Serialized) + Method(SGST,0,Serialized) +// AMI CHANGE END. + { + // + // Check SGMode and dGPU Present Detect GPIO for SG system + // + If(And(SGMD,0x0F)) + { + If(LNotEqual(SGGP,0x01)) + { + Return(0x0F) + } + // Check dGPU_PWROK to detect dGPU. + If(LEqual(SGPI(PWOK),1)) + { + Return(0x0F) + } + Return(0x00) + } + + // + // For non-SG system check for valid Vendor Id + // + If(LNotEqual(DVID,0xFFFF)) + { + Return(0x0F) + } + Return(0x00) + } + + + Method(_DOD,0) + { + Return (\_SB.PCI0.GFX0._DOD()) + } + + + Device(DD01) + { + Method(_ADR,0,Serialized) + { + Return(\_SB.PCI0.GFX0.DD01._ADR()) + } + + // Device Current State. + Method(_DCS,0) + { + + } + + // Device Get State. + + Method(_DGS,0) + { + // Return the Next State. + Return(\_SB.PCI0.GFX0.DD01._DGS()) + } + + // Device Set State. + + // _DSS Table: + // + // BIT31 BIT30 Execution + // 0 0 Don't implement. + // 0 1 Cache change. Nothing to Implement. + // 1 0 Don't Implement. + // 1 1 Display Switch Complete. Implement. + + Method(_DSS,1) + { + // Do nothing here in the OpRegion model. OEMs may choose to + // update internal state if necessary. + } + } + + Device(DD02) + { + Method(_ADR,0,Serialized) + { + Return(\_SB.PCI0.GFX0.DD02._ADR()) + } + + // Device Current State. + + Method(_DCS,0) + { + // Get the Current Display State. + Return(\_SB.PCI0.GFX0.DD02._DCS()) + } + + // Device Get State. + + Method(_DGS,0) + { + // Return the Next State. + Return(\_SB.PCI0.GFX0.DD02._DGS()) + } + + // Device Set State. + + Method(_DSS,1) + { + // Do nothing here in the OpRegion model. OEMs may choose to + // update internal state if necessary. + } + +/* + Method(_DDC,1) + { + If(Lor(LEqual(\_SB.PCI0.GFX0.PHED,1),LEqual(\_SB.PCI0.GFX0.PHED,2))) + { + Name(DDC2,Buffer (256) {0x0}) + Store(\_SB.PCI0.GFX0.BDDC,DDC2) + Return(DDC2) + } + Return(Buffer(256){0x0}) + } +*/ + Method(_BCL,0) + { + Return(\_SB.PCI0.GFX0.DD02._BCL()) + } + + Method(_BQC,0) + { + Return(\_SB.PCI0.GFX0.DD02._BQC()) + } + + Method(_BCM,1) + { + Return(\_SB.PCI0.GFX0.DD02._BCM(Arg0)) + } + + } + + Device(DD03) + { + Method(_ADR,0,Serialized) + { + Return(\_SB.PCI0.GFX0.DD03._ADR()) + } + + // Device Current State. + + Method(_DCS,0) + { + // Get the Current Display State. + } + + // Device Get State. + + Method(_DGS,0) + { + // Return the Next State. + Return(\_SB.PCI0.GFX0.DD03._DGS()) + } + + // Device Set State. + + Method(_DSS,1) + { + // Do nothing here in the OpRegion model. OEMs may choose to + // update internal state if necessary. + } + } + + Device(DD04) + { + Method(_ADR,0,Serialized) + { + Return(\_SB.PCI0.GFX0.DD04._ADR()) + } + + // Device Current State. + + Method(_DCS,0) + { + // Get the Current Display State. + } + + // Device Get State. + + Method(_DGS,0) + { + // Return the Next State. + Return(\_SB.PCI0.GFX0.DD04._DGS()) + } + + // Device Set State. + + Method(_DSS,1) + { + // Do nothing here in the OpRegion model. OEMs may choose to + // update internal state if necessary. + } + + } + + Device(DD05) + { + Method(_ADR,0,Serialized) + { + Return(\_SB.PCI0.GFX0.DD05._ADR()) + } + + // Device Current State. + + Method(_DCS,0) + { + // Get the Current Display State. + } + + // Device Get State. + + Method(_DGS,0) + { + // Return the Next State. + Return(\_SB.PCI0.GFX0.DD05._DGS()) + } + + // Device Set State. + + Method(_DSS,1) + { + // Do nothing here in the OpRegion model. OEMs may choose to + // update internal state if necessary. + } + } + + Device(DD06) + { + Method(_ADR,0,Serialized) + { + Return(\_SB.PCI0.GFX0.DD06._ADR()) + } + + // Device Current State. + + Method(_DCS,0) + { + // Get the Current Display State. + } + + // Device Get State. + + Method(_DGS,0) + { + // Return the Next State. + Return(\_SB.PCI0.GFX0.DD06._DGS()) + } + + // Device Set State. + + Method(_DSS,1) + { + // Do nothing here in the OpRegion model. OEMs may choose to + // update internal state if necessary. + } + } + + Device(DD07) + { + Method(_ADR,0,Serialized) + { + Return(\_SB.PCI0.GFX0.DD07._ADR()) + } + + // Device Current State. + + Method(_DCS,0) + { + // Get the Current Display State. + } + + // Device Get State. + + Method(_DGS,0) + { + // Return the Next State. + Return(\_SB.PCI0.GFX0.DD07._DGS()) + } + + // Device Set State. + + Method(_DSS,1) + { + // Do nothing here in the OpRegion model. OEMs may choose to + // update internal state if necessary. + } + } + + Device(DD08) + { + Method(_ADR,0,Serialized) + { + Return(\_SB.PCI0.GFX0.DD08._ADR()) + } + + // Device Current State. + + Method(_DCS,0) + { + // Get the Current Display State. + } + + // Device Get State. + + Method(_DGS,0) + { + // Return the Next State. + Return(\_SB.PCI0.GFX0.DD08._DGS()) + } + + // Device Set State. + + Method(_DSS,1) + { + // Do nothing here in the OpRegion model. OEMs may choose to + // update internal state if necessary. + } + } + // GPIO Read + // Arg0 = GPIO No. + Method (SGPI,1,Serialized) + { + If(And(SGMD,0x0F)) + { + If(LEqual(SGGP,0x01)) + { + ShiftRight (Arg0, 7, Local1) + And(Arg0, 0x7F, Arg0) + + If (LLess(Arg0,0x20)) + { + Store(\_SB.PCI0.PEG0.PEGP.LVL0, Local0) + ShiftRight(Local0, Arg0, Local0) + } + ElseIf (LLess(Arg0,0x40)) + { + Store(\_SB.PCI0.PEG0.PEGP.LVL1, Local0) + ShiftRight(Local0, Subtract(Arg0,0x20), Local0) + } + Else + { + Store(\_SB.PCI0.PEG0.PEGP.LVL2, Local0) + ShiftRight(Local0, Subtract(Arg0,0x40), Local0) + } + + // + // Check if Active Low + // + If (LEqual(Local1,0)) + { + Not(Local0, Local0) + } + + Return(And(Local0,0x01)) + } + } + + Return(0) + } + + // GPIO Write + // Arg0 = GPIO No. + // Arg1 = Value (0/1) + Method (SGPO,2,Serialized) + { + If(And(SGMD,0x0F)) + { + If(LEqual(SGGP,0x01)) + { + ShiftRight (Arg0, 7, Local3) + And(Arg0, 0x7F, Arg0) + + // + // Check if Active Low + // + If (LEqual(Local3,0)) + { + Not (Arg1, Local3) + And (Local3, 0x01, Local3) + } + Else + { + And (Arg1, 0x01, Local3) + } + If (LLess(Arg0,0x20)) + { + ShiftLeft(Local3, Arg0, Local0) + ShiftLeft(0x00000001, Arg0, Local1) + And(\_SB.PCI0.PEG0.PEGP.LVL0, Not(Local1), Local2) + Or(Local2, Local0, \_SB.PCI0.PEG0.PEGP.LVL0) + } + ElseIf (LLess(Arg0,0x40)) + { + ShiftLeft(Local3, Subtract(Arg0,0x20), Local0) + ShiftLeft(0x00000001, Subtract(Arg0,0x20), Local1) + And(\_SB.PCI0.PEG0.PEGP.LVL1, Not(Local1), Local2) + Or(Local2, Local0, \_SB.PCI0.PEG0.PEGP.LVL1) + } + Else + { + ShiftLeft(Local3, Subtract(Arg0,0x40), Local0) + ShiftLeft(0x00000001, Subtract(Arg0,0x40), Local1) + And(\_SB.PCI0.PEG0.PEGP.LVL2, Not(Local1), Local2) + Or(Local2, Local0, \_SB.PCI0.PEG0.PEGP.LVL2) + } + Return(1) + } + } + + Return(1) + } + + // + // Name: CCHK + // Description: Function to check whether _ON/_OFF sequence is allowed to execute for the given PEG0 controller or not + // Input: Arg0 -> 0 means _OFF sequence, 1 means _ON sequence + // Return: 0 - Don't execute the flow, 1 - Execute the flow + // + Method(CCHK,1) + { + // + // SA:InternalOnlyBegin + // + Store("CCHK : ", Debug) + If(LEqual(Arg0, 0)) + { + Store("_OFF sequence condition check : ", Debug) + } + ElseIf(LEqual(Arg0, 1)) + { + Store("_ON sequence condition check : ", Debug) + } + // + // SA:InternalOnlyEnd + // + + //Check for PEG0 controller presence + If(LEqual(PVID, IVID)) + { + // + // SA:InternalOnlyBegin + // + Store("Don't execut the flow. Failed criteria: PEG0 controller is not present", Debug) + // + // SA:InternalOnlyEnd + // + + Return(0) + } + + //If Endpoint is not present[already disabled] before executing _OFF then don't call the _OFF method + //If Endpoint is present[already enabled] before executing _ON then don't call the _ON method + If(LEqual(Arg0, 0)) + { + //_OFF sequence condition check + If(LEqual(ONOF, 0)) + { + // + // SA:InternalOnlyBegin + // + Store("Don't execut the flow. Failed criteria: Endpoint is not present[already disabled]", Debug) + // + // SA:InternalOnlyEnd + // + + Return(0) + } + } + ElseIf(LEqual(Arg0, 1)) + { + //_ON sequence condition check + If(LEqual(ONOF, 1)) + { + // + // SA:InternalOnlyBegin + // + Store("Don't execut the flow. Failed criteria: Endpoint is present[already enabled]", Debug) + // + // SA:InternalOnlyEnd + // + + Return(0) + } + } + + // + // SA:InternalOnlyBegin + // + Store("Execute the flow", Debug) + // + // SA:InternalOnlyEnd + // + + Return(1) + } // End of Method(CCHK,1) + +} diff --git a/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgSsdt.asl b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgSsdt.asl new file mode 100644 index 0000000..9d4e1d1 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/AcpiTables/SwitchableGraphics/Peg/SgSsdt.asl @@ -0,0 +1,45 @@ +/**************************************************************************; +;* *; +;* Intel Confidential *; +;* *; +;* Intel Corporation - SG Reference Code *; +;* Family of Customer Reference Boards. *; +;* *; +;* *; +;* Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved *; +;* This software and associated documentation (if any) is furnished *; +;* under a license and may only be used or copied in accordance *; +;* with the terms of the license. Except as permitted by such *; +;* license, no part of this software or documentation may be *; +;* reproduced, stored in a retrieval system, or transmitted in any *; +;* form or by any means without the express written consent of *; +;* Intel Corporation. *; +;* *; +;* *; +;**************************************************************************/ +/*++ + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +--*/ + +DefinitionBlock ( + "Sg.aml", + "SSDT", + 1, + "SgRef", + "SgPeg", + 0x1000 + ) +{ + External(P8XH, MethodObj) + External(GPRW, MethodObj) + +// AMI MODIFY BEGIN +// Include("SgIgpu.ASL") +// Include("SgDgpu.ASL") +#include <SgDgpu.ASL> +// AMI MODIFY END +} |