diff options
Diffstat (limited to 'ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration')
10 files changed, 3526 insertions, 0 deletions
diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcAddressDecodeConfiguration.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcAddressDecodeConfiguration.c new file mode 100644 index 0000000..e4d17ee --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcAddressDecodeConfiguration.c @@ -0,0 +1,368 @@ +/** @file + This module configures the memory controller address decoder. +@copyright + Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved. + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. + +**/ +#include "MrcAddressDecodeConfiguration.h" + +#if (MAX_CHANNEL > 2) +#error This module only supports a maximum of 2 channels. +#endif +#if (MAX_DIMMS_IN_CHANNEL > 2) +#error This module only supports a maximum of 2 DIMMs per channel. +#endif + +/** +@brief + This function configures the zone configuration registers MAD-CR and MAD-ZR-CR. + + @param[in, out] MrcData - Include all MRC global data. + + @retval Nothing. +**/ +void +ZoneConfiguration ( + IN OUT MrcParameters *const MrcData +) +{ + MrcInput *Inputs; + MrcOutput *Outputs; + MrcDebug *Debug; + MrcControllerOut *ControllerOut; + MrcChannelOut *ChannelOut; + MrcChannelOut *ChannelOut0; + MrcChannelOut *ChannelOut1; + MCDECS_CR_MAD_CHNL_MCMAIN_STRUCT MadChnl; + MCDECS_CR_MAD_ZR_MCMAIN_STRUCT MadZr; + MCDECS_CR_CHANNEL_HASH_MCMAIN_STRUCT ChannelHash; + U32 ChannelSizeMin; + U32 ChannelSizeBC; + U32 ChannelSize2BC; + U32 ChannelSize[MAX_CHANNEL]; + U8 Channel; + U8 Dimm; + + MadChnl.Data = 0; + MadZr.Data = 0; + ChannelHash.Data = 0; + Inputs = &MrcData->SysIn.Inputs; + Debug = &Inputs->Debug; + Outputs = &MrcData->SysOut.Outputs; + ControllerOut = &MrcData->SysOut.Outputs.Controller[0]; + + // + // Add up the amount of memory in each channel. + // + for (Channel = 0; Channel < MAX_CHANNEL; Channel++) { + ChannelOut = &ControllerOut->Channel[Channel]; + ChannelSize[Channel] = 0; + if (ChannelOut->Status == CHANNEL_PRESENT) { + for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) { + if(ChannelOut->Dimm[Dimm].Status == DIMM_PRESENT) { + ChannelSize[Channel] += ChannelOut->Dimm[Dimm].DimmCapacity; + } + } + } + } + // + // Define MAD_ZR register: + // MAD-ZR-CR [29:24] = channel C size: ch_c_size + // MAD-ZR-CR [23:16] = (channel C size) * 3: ch_3c_size + // MAD-ZR-CR [15:8] = (channel B size) * 2 + (channel C size): ch_b_2c_size + // MAD-ZR-CR [7:0] = (channel B size) + (channel C size): ch_b_c_size + // + ChannelOut0 = &ControllerOut->Channel[cCHANNEL0]; + ChannelOut1 = &ControllerOut->Channel[cCHANNEL1]; + if (ChannelSize[cCHANNEL1] <= ChannelSize[cCHANNEL0]) { + MadChnl.Bits.CH_A = 0; + MadChnl.Bits.CH_B = 1; + + // + // Set the virtual channel type according to the address decoding decision. + // + ChannelOut0->VirtualChannel = vcA; + ChannelOut1->VirtualChannel = vcB; + + ChannelSizeMin = ChannelSize[cCHANNEL1]; + } else { + // + // ChannelSize0 < ChannelSize1 + // + MadChnl.Bits.CH_A = 1; + MadChnl.Bits.CH_B = 0; + + // + // Set the virtual channel type according to the address decoding decision. + // + ChannelOut0->VirtualChannel = vcB; + ChannelOut1->VirtualChannel = vcA; + + ChannelSizeMin = ChannelSize[cCHANNEL0]; + } + // + // Divided by 256 because the channel size is in 256 MB units. + // + ChannelSizeBC = ChannelSizeMin / 256; + ChannelSize2BC = ChannelSizeBC << 1; + MadZr.Bits.BandC = MIN (ChannelSizeBC, MCDECS_CR_MAD_ZR_MCMAIN_BandC_MAX); + MadZr.Bits.TwoBandC = MIN (ChannelSize2BC, MCDECS_CR_MAD_ZR_MCMAIN_TwoBandC_MAX); + MadChnl.Bits.CH_C = 2; + +#ifdef ULT_FLAG + MadChnl.Bits.LPDDR = (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) ? 1 : 0; +#endif + // + // Interleaved mode + // Check for any Channel hash support + // + if (Inputs->ChHashEnable) { + ChannelHash.Bits.Mask = MIN (Inputs->ChHashMask, MCDECS_CR_CHANNEL_HASH_MCMAIN_Mask_MAX); + ChannelHash.Bits.LSB_mask_bit = MIN (Inputs->ChHashInterleaveBit, MCDECS_CR_CHANNEL_HASH_MCMAIN_LSB_mask_bit_MAX); + ChannelHash.Bits.Enable = 1; + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel HASH Enabled\n"); + } + + if (Inputs->MemoryTrace) { + if (ChannelSize[cCHANNEL0] == ChannelSize[cCHANNEL1]) { + // + // Enable the Stacked Mode for memory tracing + // + MadChnl.Bits.STKD_MODE = 1; + MadChnl.Bits.STKD_MODE_CH_BITS = MrcLog2 (ChannelSizeMin) - 9; + ChannelHash.Bits.Enable = 1; + MRC_DEBUG_MSG ( + Debug, + MSG_LEVEL_NOTE, + "Enabling Stacked Mode for Memory Trace, Stacked Mode Ch bit = %u (%u MB per channel)\n", + MadChnl.Bits.STKD_MODE_CH_BITS + 28, + ChannelSizeMin + ); + } else { + Inputs->MemoryTrace = 0; + MRC_DEBUG_MSG (Debug, MSG_LEVEL_ERROR, "Channels are not equal in size, cannot enable Memory Trace !\n"); + } + } + + MRC_DEBUG_MSG ( + Debug, + MSG_LEVEL_NOTE, + "CHANNEL_HASH = 0x%08X\nMAD_CHNL = 0x%08X\nMAD_ZR = 0x%08X\n", + ChannelHash.Data, + MadChnl.Data, + MadZr.Data + ); + MrcWriteCR (MrcData, MCDECS_CR_CHANNEL_HASH_MCMAIN_REG, ChannelHash.Data); + MrcWriteCR (MrcData, MCDECS_CR_MAD_CHNL_MCMAIN_REG, MadChnl.Data); + MrcWriteCR (MrcData, MCDECS_CR_MAD_ZR_MCMAIN_REG, MadZr.Data); + return; +} + +/** +@brief + This function configures the MAD_DIMM_CH0/1 register. + + @param[in] MrcData - Include all MRC global data. + @param[in] ChannelIndex - Channel index + + @retval Nothing. +**/ +void +ChannelAddressDecodeConfiguration ( + IN MrcParameters *const MrcData, + IN const U32 ChannelIndex +) +{ + const MrcInput *Inputs; + MrcOutput *Outputs; + MrcChannelOut *ChannelOut; + MrcDimmOut *DimmA; + MrcDimmOut *DimmB; + MCDECS_CR_MAD_DIMM_CH0_MCMAIN_STRUCT MadDimm; + U32 DimmCapacity; + U32 Dimm0Capacity; + U32 Dimm1Capacity; + U32 Scratch; +#ifdef ULT_FLAG + MCHBAR_CH0_CR_LPDDR_MR_PARAMS_STRUCT LpddrMrParams; +#endif //ULT_FLAG + + Inputs = &MrcData->SysIn.Inputs; + Outputs = &MrcData->SysOut.Outputs; + ChannelOut = &Outputs->Controller[0].Channel[ChannelIndex]; + MadDimm.Data = 0; + if (ChannelOut->Dimm[dDIMM0].Status == DIMM_PRESENT) { + Dimm0Capacity = ChannelOut->Dimm[dDIMM0].DimmCapacity; + } else { + Dimm0Capacity = 0; + } + + if (ChannelOut->Dimm[dDIMM1].Status == DIMM_PRESENT) { + Dimm1Capacity = (MAX_DIMMS_IN_CHANNEL > 1) ? ChannelOut->Dimm[dDIMM1].DimmCapacity : 0; + } else { + Dimm1Capacity = 0; + } + + // + // larger dimm will be located to Dimm A and small dimm will be located to dimm B + // + if (Dimm1Capacity <= Dimm0Capacity) { + DimmA = &ChannelOut->Dimm[dDIMM0]; + DimmB = &ChannelOut->Dimm[dDIMM1]; + // + // larger DIMM in capacity 0 - DIMM 0 or 1 - DIMM 1 + // + MadDimm.Bits.DAS = 0; + } else { + DimmA = &ChannelOut->Dimm[dDIMM1]; + DimmB = &ChannelOut->Dimm[dDIMM0]; + // + // larger DIMM in capacity 0 - DIMM 0 or 1 - DIMM 1 + // + MadDimm.Bits.DAS = 1; + } + // + // Dimm A + // + if ((0 < DimmA->RankInDIMM) && (DimmA->Status == DIMM_PRESENT)) { + DimmCapacity = DimmA->DimmCapacity / 256; + MadDimm.Bits.DIMM_A_Size = MIN (DimmCapacity, MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_A_Size_MAX); + // + // RankInDIMM must be 1 or 2, we test the case that the value is 0 + // + Scratch = DimmA->RankInDIMM - 1; + MadDimm.Bits.DANOR = MIN (Scratch, MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DANOR_MAX); + // + // SDRAM width x8 or x32 set to 0, x16 set to 1 + // + MadDimm.Bits.DAW = (DimmA->SdramWidth == 16) ? 1 : 0; + } + // + // Dimm B + // + if ((MAX_DIMMS_IN_CHANNEL > 1) && (0 < DimmB->RankInDIMM) && (DimmB->Status == DIMM_PRESENT)) { + DimmCapacity = DimmB->DimmCapacity / 256; + MadDimm.Bits.DIMM_B_Size = MIN (DimmCapacity, MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DIMM_B_Size_MAX); + // + // RankInDIMM must be 1 or 2, we test the case that this value is 0. + // + Scratch = DimmB->RankInDIMM - 1; + MadDimm.Bits.DBNOR = MIN (Scratch, MCDECS_CR_MAD_DIMM_CH0_MCMAIN_DBNOR_MAX); + + // + // SDRAM width x8 or x32 set to 0, x16 set to 1 + // + MadDimm.Bits.DBW = (DimmB->SdramWidth == 16) ? 1 : 0; + } + +#ifdef ULT_FLAG + if (Inputs->CpuModel == cmHSW_ULT) { + // + // On HSW-ULT only 1DPC is supported, and DBW should have the same value as DAW + // + MadDimm.Bits.DBW = MadDimm.Bits.DAW; + } +#endif + + if (Inputs->RankInterleave) { + MadDimm.Bits.RI = MRC_DIMM_RANK_INTERLEAVE; + } + if (Inputs->EnhancedInterleave) { + MadDimm.Bits.Enh_Interleave = MRC_ENHANCED_INTERLEAVE_MODE; + } + + MRC_DEBUG_MSG (&Inputs->Debug, MSG_LEVEL_NOTE, "MAD_DIMM_CH%u = 0x%08X\n", ChannelIndex, MadDimm.Data); + MrcWriteCR ( + MrcData, + MCDECS_CR_MAD_DIMM_CH0_MCMAIN_REG + + (ChannelIndex * (MCDECS_CR_MAD_DIMM_CH1_MCMAIN_REG - MCDECS_CR_MAD_DIMM_CH0_MCMAIN_REG)), + MadDimm.Data + ); + +#ifdef ULT_FLAG + if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) { + LpddrMrParams.Data = 0; + LpddrMrParams.Bits.MR4_PERIOD = 0x200D; + + if (DimmA->SdramWidth == 32) { + LpddrMrParams.Bits.Rank_0_x32 = 1; + LpddrMrParams.Bits.Rank_1_x32 = 1; + } + + MrcWriteCR ( + MrcData, + MCHBAR_CH0_CR_LPDDR_MR_PARAMS_REG + + (ChannelIndex * (MCHBAR_CH1_CR_LPDDR_MR_PARAMS_REG - MCHBAR_CH0_CR_LPDDR_MR_PARAMS_REG)), + LpddrMrParams.Data + ); + } +#endif // ULT_FLAG + return; +} + +/** +@brief + This function is the main address decoding configuration function. + + @param[in] MrcData - Include all MRC global data. + + @retval Nothing. +**/ +void +MrcAdConfiguration ( + IN MrcParameters *const MrcData +) +{ + MrcOutput *Outputs; + MrcChannelOut *ChannelOut; + MrcControllerOut *ControllerOut; + MrcDimmOut *DimmOut; + U8 Controller; + U8 Channel; + U8 Dimm; + + ZoneConfiguration (MrcData); + + Outputs = &MrcData->SysOut.Outputs; + for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) { + ControllerOut = &Outputs->Controller[Controller]; + for (Channel = 0; Channel < MAX_CHANNEL; Channel++) { + if (!MrcChannelExist (Outputs, Channel)) { + continue; + } + ChannelOut = &ControllerOut->Channel[Channel]; + + ChannelAddressDecodeConfiguration (MrcData, Channel); + + for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; ++Dimm) { + DimmOut = &ChannelOut->Dimm[Dimm]; + if (DimmOut->Status == DIMM_PRESENT) { + MRC_DEBUG_MSG ( + &MrcData->SysIn.Inputs.Debug, + MSG_LEVEL_NOTE, + "Channel: %u, Dimm %d Rank in DIMM is: %u\n", + Channel, + Dimm, + DimmOut->RankInDIMM + ); + } + } // for Dimm + } // for Channel + } // for Controller + + return; +} diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcAddressDecodeConfiguration.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcAddressDecodeConfiguration.h new file mode 100644 index 0000000..b502ec6 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcAddressDecodeConfiguration.h @@ -0,0 +1,78 @@ +/** @file + This module configures the memory controller address decoder. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved. + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +*/ +#ifndef _MrcAddressConfiguration_h_ +#define _MrcAddressConfiguration_h_ + +#include "MrcTypes.h" +#include "MrcGlobal.h" +#include "MrcApi.h" +#include "McAddress.h" +#include "MrcCommon.h" +#include "MrcOem.h" +#include "MrcCommon.h" +#include "MrcOemDebugPrint.h" + +/** +@brief + This function is the main address decoding configuration function. + + @param[in] MrcData - Include all MRC global data. + + @retval Nothing. + +**/ +extern +void +MrcAdConfiguration ( + IN MrcParameters *const MrcData + ); + +/** +@brief + This function configures the zone configuration registers MAD-CR and MAD-ZR-CR. + + @param[in, out] MrcData - Include all MRC global data. + + @retval Nothing. +**/ +extern +void +ZoneConfiguration ( + IN OUT MrcParameters *const MrcData + ); + +/** +@brief + This function configures the MAD_DIMM_CH0/1 register. + + @param[in] MrcData - Include all MRC global data. + @param[in] ChannelIndex - Channel index + + @retval Nothing. +**/ +extern +void +ChannelAddressDecodeConfiguration ( + IN MrcParameters *const MrcData, + IN const U32 ChannelIndex + ); + +#endif diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcPowerModes.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcPowerModes.c new file mode 100644 index 0000000..9c06a65 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcPowerModes.c @@ -0,0 +1,1034 @@ +/** @file + This module configures the memory controller power modes. + +@copyright + Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved. + + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. + +**/ + +/// +/// Include files +/// +#include "MrcPowerModes.h" +#include "MrcOemDebugPrint.h" +#include "MrcSpdProcessing.h" + +const Ddr3PowerWeightEntry Ddr3PowerWeightTable[] = { + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x6A, 0xCA, 0x82, 0x9, 0x10, 0x08}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 3, 0x34, 0x89, 0x40, 0x5, 0x07, 0x0B}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x78, 0xD6, 0x86, 0xB, 0x13, 0x09}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 3, 0x3B, 0x8F, 0x42, 0x6, 0x09, 0x0E}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x5B, 0xB0, 0x7C, 0x5, 0x0B, 0x07}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x58, 0xF7, 0x7A, 0x5, 0x09, 0x09}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x66, 0xB9, 0x81, 0x6, 0x0D, 0x08}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 3, 0x32, 0x80, 0x40, 0x3, 0x05, 0x09}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x9F, 0xCA, 0x40, 0x5, 0x07, 0x11}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x9E, 0xCA, 0x3F, 0x5, 0x07, 0x18}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0xA6, 0xD0, 0x42, 0x6, 0x09, 0x13}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0xA5, 0xD0, 0x41, 0x6, 0x08, 0x1A}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x98, 0xBD, 0x3D, 0x3, 0x05, 0x0F}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x97, 0xBD, 0x3D, 0x3, 0x04, 0x12}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0x9D, 0xC2, 0x40, 0x3, 0x06, 0x10}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0x9C, 0xC1, 0x3F, 0x3, 0x05, 0x14}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x66, 0xB3, 0x88, 0x8, 0x0E, 0x0A}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x64, 0xB1, 0x86, 0x8, 0x0C, 0x0D}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x74, 0xBF, 0x8B, 0xA, 0x11, 0x0B}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x72, 0xBD, 0x89, 0xA, 0x0F, 0x0F}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x57, 0x9A, 0x7C, 0x4, 0x0A, 0x08}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x55, 0x98, 0x7A, 0x4, 0x08, 0x0A}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x62, 0xA3, 0x80, 0x5, 0x0B, 0x09}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x60, 0xA1, 0x7E, 0x5, 0x09, 0x0B}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x88, 0xAB, 0x43, 0x4, 0x07, 0x14}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x87, 0xAA, 0x43, 0x4, 0x06, 0x1A}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x8F, 0xB1, 0x45, 0x5, 0x08, 0x15}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x8F, 0xB0, 0x44, 0x5, 0x07, 0x1D}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x81, 0x9E, 0x3D, 0x2, 0x04, 0x10}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x80, 0x9E, 0x3D, 0x2, 0x04, 0x15}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x86, 0xA3, 0x3F, 0x3, 0x05, 0x11}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x85, 0xA2, 0x3F, 0x3, 0x04, 0x15}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x72, 0xFD, 0x90, 0x7, 0x0D, 0x0C}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x71, 0xFB, 0x8E, 0x7, 0x0B, 0x0F}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 3, 0x40, 0x85, 0x4A, 0x5, 0x08, 0x0E}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 3, 0x3F, 0x84, 0x49, 0x5, 0x07, 0x12}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x62, 0xE4, 0x7E, 0x4, 0x09, 0x0A}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x61, 0xE3, 0x7C, 0x4, 0x07, 0x0C}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x6C, 0xED, 0x82, 0x5, 0x0A, 0x0B}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x6B, 0xEB, 0x80, 0x5, 0x08, 0x0D}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x8E, 0xCE, 0x47, 0x4, 0x06, 0x17}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x8E, 0xCD, 0x47, 0x4, 0x06, 0x20}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x95, 0xD4, 0x49, 0x5, 0x07, 0x19}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x95, 0xD3, 0x48, 0x5, 0x07, 0x23}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x86, 0xC1, 0x3E, 0x2, 0x04, 0x13}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x86, 0xC1, 0x3E, 0x2, 0x03, 0x16}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x8C, 0xC6, 0x40, 0x3, 0x04, 0x14}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x8B, 0xC5, 0x40, 0x3, 0x04, 0x1A}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x6F, 0xE6, 0x9C, 0x7, 0x0C, 0x0E}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x6D, 0xE4, 0x9B, 0x7, 0x0B, 0x12}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x7C, 0xF1, 0x9F, 0x8, 0x0E, 0x0F}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x7B, 0xF0, 0x9D, 0x8, 0x0D, 0x14}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x5F, 0xCE, 0x83, 0x4, 0x08, 0x0B}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x5E, 0xCC, 0x82, 0x4, 0x06, 0x0D}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x69, 0xD6, 0x87, 0x5, 0x09, 0x0C}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x68, 0xD5, 0x86, 0x5, 0x07, 0x0E}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x81, 0xB7, 0x4E, 0x4, 0x06, 0x1A}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x80, 0xB6, 0x4D, 0x4, 0x05, 0x21}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x87, 0xBD, 0x4F, 0x4, 0x07, 0x1C}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x87, 0xBC, 0x4F, 0x4, 0x06, 0x25}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x79, 0xAB, 0x41, 0x2, 0x04, 0x15}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x78, 0xAA, 0x41, 0x2, 0x03, 0x19}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x7E, 0xAF, 0x43, 0x3, 0x04, 0x16}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x7D, 0xAF, 0x43, 0x3, 0x04, 0x1D}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x6C, 0xD4, 0xA6, 0x6, 0x0B, 0x0F}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x6B, 0xD3, 0xA4, 0x6, 0x0A, 0x13}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x7A, 0xE0, 0xA8, 0x8, 0x0D, 0x11}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x79, 0xDE, 0xA7, 0x8, 0x0C, 0x16}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x5C, 0xBD, 0x87, 0x3, 0x07, 0x0C}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x5B, 0xBB, 0x85, 0x3, 0x06, 0x0E}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x66, 0xC5, 0x8A, 0x4, 0x08, 0x0D}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x65, 0xC3, 0x89, 0x4, 0x07, 0x10}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x76, 0xA6, 0x52, 0x3, 0x05, 0x1A}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x76, 0xA5, 0x52, 0x3, 0x05, 0x24}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x7D, 0xAB, 0x54, 0x4, 0x06, 0x1D}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x7D, 0xAB, 0x53, 0x4, 0x06, 0x29}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x6E, 0x9A, 0x43, 0x2, 0x03, 0x15}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x6E, 0x9A, 0x43, 0x2, 0x03, 0x1B}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x73, 0x9E, 0x45, 0x2, 0x04, 0x18}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x73, 0x9D, 0x44, 0x2, 0x03, 0x1C}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x77, 0xC9, 0x82, 0x9, 0x10, 0x09}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x75, 0xC7, 0x7F, 0x9, 0x0E, 0x0C}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x85, 0xD6, 0x86, 0xB, 0x13, 0x0A}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x83, 0xD3, 0x83, 0xB, 0x11, 0x0D}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x68, 0xB0, 0x7C, 0x5, 0x0B, 0x07}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x66, 0xAE, 0x7A, 0x5, 0x09, 0x09}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x73, 0xB9, 0x81, 0x6, 0x0D, 0x08}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x71, 0xB7, 0x7E, 0x6, 0x0A, 0x0A}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0xBD, 0xE8, 0x40, 0x5, 0x07, 0x13}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0xBD, 0xE8, 0x3F, 0x5, 0x07, 0x1A}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0xC4, 0xEF, 0x42, 0x6, 0x09, 0x15}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0xC3, 0xEE, 0x41, 0x6, 0x08, 0x1C}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0xB6, 0xDC, 0x3D, 0x3, 0x05, 0x11}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0xB5, 0xDB, 0x3D, 0x3, 0x04, 0x14}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0xBB, 0xE0, 0x40, 0x3, 0x06, 0x12}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0xBB, 0xDF, 0x3F, 0x3, 0x05, 0x16}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x71, 0xB2, 0x88, 0x8, 0x0E, 0x0A}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x6F, 0xB1, 0x86, 0x8, 0x0C, 0x0D}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x7F, 0xBF, 0x8B, 0xA, 0x11, 0x0B}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x7D, 0xBD, 0x89, 0xA, 0x0F, 0x0F}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x62, 0x9A, 0x7C, 0x4, 0x0A, 0x08}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x60, 0x98, 0x7A, 0x4, 0x08, 0x0A}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x6D, 0xA3, 0x80, 0x5, 0x0B, 0x09}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x6B, 0xA1, 0x7E, 0x5, 0x09, 0x0B}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0xA0, 0xC3, 0x43, 0x4, 0x07, 0x15}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0xA0, 0xC2, 0x43, 0x4, 0x06, 0x1C}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0xA7, 0xC9, 0x45, 0x5, 0x08, 0x17}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0xA7, 0xC8, 0x44, 0x5, 0x07, 0x1F}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x99, 0xB6, 0x3D, 0x2, 0x04, 0x11}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x98, 0xB6, 0x3D, 0x2, 0x04, 0x16}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x9E, 0xBB, 0x3F, 0x3, 0x05, 0x13}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x9E, 0xBA, 0x3F, 0x3, 0x04, 0x17}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x79, 0xD2, 0x90, 0x7, 0x0D, 0x0C}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x77, 0xD0, 0x8E, 0x7, 0x0B, 0x0F}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x87, 0xDE, 0x93, 0x9, 0x0F, 0x0D}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x85, 0xDC, 0x91, 0x9, 0x0D, 0x11}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x69, 0xBA, 0x7E, 0x4, 0x08, 0x0A}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x67, 0xB8, 0x7C, 0x4, 0x07, 0x0C}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x73, 0xC2, 0x81, 0x5, 0x0A, 0x0B}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x72, 0xC0, 0x80, 0x5, 0x08, 0x0D}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x8E, 0xBA, 0x47, 0x4, 0x06, 0x17}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x8E, 0xBA, 0x47, 0x4, 0x06, 0x20}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x95, 0xC0, 0x49, 0x5, 0x07, 0x19}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x94, 0xC0, 0x48, 0x5, 0x07, 0x23}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x86, 0xAE, 0x3E, 0x2, 0x04, 0x13}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x86, 0xAE, 0x3E, 0x2, 0x03, 0x16}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x8B, 0xB2, 0x40, 0x3, 0x04, 0x14}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x8B, 0xB2, 0x40, 0x3, 0x04, 0x1A}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x75, 0xC1, 0x9C, 0x7, 0x0C, 0x0E}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x73, 0xBF, 0x9B, 0x7, 0x0B, 0x12}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x82, 0xCC, 0x9F, 0x8, 0x0E, 0x0F}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x81, 0xCB, 0x9D, 0x8, 0x0C, 0x14}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x65, 0xA9, 0x83, 0x4, 0x08, 0x0B}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x64, 0xA8, 0x82, 0x4, 0x06, 0x0D}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x6F, 0xB1, 0x87, 0x5, 0x09, 0x0C}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x6E, 0xB0, 0x86, 0x5, 0x07, 0x0E}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x80, 0xA6, 0x4E, 0x4, 0x06, 0x1A}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x80, 0xA6, 0x4D, 0x4, 0x05, 0x21}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x87, 0xAC, 0x4F, 0x4, 0x07, 0x1C}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x87, 0xAB, 0x4F, 0x4, 0x06, 0x25}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x78, 0x9A, 0x41, 0x2, 0x04, 0x15}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x78, 0x9A, 0x41, 0x2, 0x03, 0x19}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x7D, 0x9E, 0x43, 0x3, 0x04, 0x16}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x7D, 0x9E, 0x43, 0x3, 0x04, 0x1D}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x72, 0xB4, 0xA5, 0x6, 0x0B, 0x0F}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x70, 0xB3, 0xA4, 0x6, 0x0A, 0x14}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x7F, 0xC0, 0xA8, 0x8, 0x0D, 0x11}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x7E, 0xBE, 0xA7, 0x8, 0x0C, 0x16}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x61, 0x9D, 0x87, 0x3, 0x07, 0x0C}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x60, 0x9B, 0x85, 0x3, 0x06, 0x0E}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x6B, 0xA4, 0x8A, 0x4, 0x08, 0x0D}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x6A, 0xA3, 0x89, 0x4, 0x07, 0x10}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x76, 0x97, 0x52, 0x3, 0x05, 0x1A}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x76, 0x97, 0x52, 0x3, 0x05, 0x24}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x7D, 0x9D, 0x54, 0x4, 0x06, 0x1D}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x7C, 0x9C, 0x53, 0x4, 0x06, 0x29}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x6E, 0x8B, 0x43, 0x2, 0x03, 0x15}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x6D, 0x8B, 0x43, 0x2, 0x03, 0x1B}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x73, 0x8F, 0x45, 0x2, 0x04, 0x18}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x72, 0x8F, 0x44, 0x2, 0x03, 0x1C}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x85, 0xE2, 0x91, 0xA, 0x12, 0x08}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x83, 0xDF, 0x8F, 0xA, 0x0F, 0x0B}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x95, 0xF0, 0x96, 0xD, 0x15, 0x09}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x92, 0xED, 0x93, 0xD, 0x13, 0x0D}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x7E, 0xCF, 0x9A, 0x6, 0x0C, 0x06}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x7B, 0xCC, 0x98, 0x6, 0x0A, 0x08}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x8B, 0xDA, 0xA0, 0x7, 0x0E, 0x07}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x89, 0xD7, 0x9D, 0x7, 0x0C, 0x0A}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 2, 0x77, 0x8C, 0x24, 0x3, 0x04, 0x0F}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 2, 0x76, 0x8C, 0x24, 0x3, 0x04, 0x17}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 2, 0x7B, 0x90, 0x25, 0x4, 0x05, 0x11}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 2, 0x7A, 0x8F, 0x25, 0x4, 0x05, 0x1B}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 2, 0x75, 0x87, 0x26, 0x2, 0x03, 0x0D}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 2, 0x74, 0x87, 0x26, 0x2, 0x03, 0x13}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 2, 0x78, 0x8A, 0x28, 0x2, 0x03, 0x0D}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 2, 0x78, 0x8A, 0x27, 0x2, 0x03, 0x13}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x7E, 0xC8, 0x98, 0x9, 0x10, 0x09}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x7C, 0xC6, 0x96, 0x9, 0x0E, 0x0D}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x8E, 0xD6, 0x9C, 0xB, 0x12, 0x0A}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x8C, 0xD4, 0x9A, 0xB, 0x10, 0x0E}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x77, 0xB6, 0x9A, 0x5, 0x0B, 0x07}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x75, 0xB4, 0x98, 0x5, 0x09, 0x0A}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x84, 0xC0, 0x9F, 0x7, 0x0C, 0x08}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x82, 0xBE, 0x9D, 0x7, 0x0A, 0x0A}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 2, 0x83, 0x92, 0x26, 0x3, 0x04, 0x13}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 2, 0x82, 0x92, 0x26, 0x3, 0x04, 0x1D}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 2, 0x87, 0x96, 0x27, 0x3, 0x05, 0x16}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 2, 0x86, 0x95, 0x27, 0x3, 0x04, 0x1D}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 2, 0x81, 0x8E, 0x26, 0x2, 0x03, 0x11}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 2, 0x80, 0x8D, 0x26, 0x2, 0x02, 0x13}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 2, 0x84, 0x90, 0x28, 0x2, 0x03, 0x11}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 2, 0x84, 0x90, 0x27, 0x2, 0x03, 0x18}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x7A, 0xB8, 0xA1, 0x8, 0x0E, 0x0A}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x79, 0xB6, 0xA0, 0x8, 0x0C, 0x0E}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x8A, 0xC5, 0xA5, 0xA, 0x10, 0x0B}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x88, 0xC4, 0xA3, 0xA, 0x0F, 0x10}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x71, 0xA6, 0x9C, 0x5, 0x0A, 0x08}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x70, 0xA4, 0x9A, 0x5, 0x08, 0x0B}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x7E, 0xB0, 0xA1, 0x6, 0x0B, 0x09}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x7C, 0xAE, 0x9F, 0x6, 0x09, 0x0C}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0xE2, 0xFC, 0x50, 0x4, 0x07, 0x14}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0xE1, 0xFB, 0x50, 0x4, 0x06, 0x1C}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 2, 0x75, 0x82, 0x29, 0x3, 0x04, 0x16}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 2, 0x75, 0x81, 0x29, 0x3, 0x04, 0x22}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0xDD, 0xF3, 0x4E, 0x3, 0x04, 0x10}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0xDD, 0xF2, 0x4D, 0x3, 0x04, 0x16}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0xE4, 0xF8, 0x50, 0x3, 0x05, 0x12}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0xE3, 0xF7, 0x50, 0x3, 0x05, 0x19}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x77, 0xAC, 0xAF, 0x7, 0x0D, 0x0B}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x76, 0xAB, 0xAE, 0x7, 0x0C, 0x10}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x86, 0xB9, 0xB2, 0x9, 0x0F, 0x0D}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x85, 0xB8, 0xB1, 0x9, 0x0E, 0x12}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x6F, 0x9A, 0xA3, 0x4, 0x09, 0x09}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x6D, 0x99, 0xA2, 0x4, 0x07, 0x0C}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x7B, 0xA5, 0xA8, 0x5, 0x0A, 0x0A}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x7A, 0xA3, 0xA7, 0x5, 0x09, 0x0E}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0xC9, 0xDF, 0x57, 0x4, 0x06, 0x15}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0xC8, 0xDF, 0x57, 0x4, 0x06, 0x20}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0xD0, 0xE6, 0x59, 0x5, 0x07, 0x17}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0xD0, 0xE5, 0x58, 0x5, 0x07, 0x24}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0xC5, 0xD6, 0x51, 0x2, 0x04, 0x12}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0xC4, 0xD6, 0x51, 0x2, 0x04, 0x19}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0xCB, 0xDB, 0x54, 0x3, 0x05, 0x14}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0xCB, 0xDB, 0x53, 0x3, 0x04, 0x19}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x75, 0xA4, 0xBA, 0x7, 0x0C, 0x0D}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x74, 0xA2, 0xB9, 0x7, 0x0B, 0x12}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x84, 0xB0, 0xBC, 0x9, 0x0E, 0x0E}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x83, 0xAF, 0xBB, 0x9, 0x0D, 0x14}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x6C, 0x92, 0xA7, 0x4, 0x08, 0x0A}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x6A, 0x91, 0xA6, 0x4, 0x07, 0x0D}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x78, 0x9C, 0xAC, 0x5, 0x09, 0x0B}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x77, 0x9B, 0xAB, 0x5, 0x08, 0x0E}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0xB6, 0xCA, 0x5D, 0x4, 0x06, 0x18}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0xB6, 0xC9, 0x5C, 0x4, 0x06, 0x24}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0xBE, 0xD0, 0x5E, 0x5, 0x07, 0x1A}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0xBD, 0xD0, 0x5E, 0x5, 0x06, 0x24}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0xB1, 0xC1, 0x53, 0x2, 0x04, 0x13}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0xB1, 0xC1, 0x53, 0x2, 0x03, 0x17}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0xB8, 0xC6, 0x56, 0x3, 0x04, 0x14}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0xB7, 0xC6, 0x55, 0x3, 0x04, 0x1C}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x56, 0xA3, 0x69, 0x7, 0x0D, 0x07}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x54, 0xDD, 0x67, 0x7, 0x0B, 0x09}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x61, 0xAD, 0x6C, 0x9, 0x10, 0x08}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x5F, 0xE7, 0x6A, 0x9, 0x0E, 0x0B}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x4A, 0x8F, 0x65, 0x4, 0x09, 0x06}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x48, 0xC9, 0x63, 0x4, 0x07, 0x07}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x53, 0x96, 0x69, 0x5, 0x0A, 0x06}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x51, 0xD0, 0x67, 0x5, 0x08, 0x08}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x81, 0xA4, 0x34, 0x4, 0x06, 0x0E}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x80, 0xA3, 0x33, 0x4, 0x06, 0x14}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0x87, 0xA9, 0x36, 0x5, 0x07, 0x10}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0x86, 0xA8, 0x35, 0x5, 0x07, 0x16}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x7B, 0x9A, 0x32, 0x2, 0x04, 0x0C}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x7A, 0x99, 0x31, 0x2, 0x03, 0x0E}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0x7F, 0x9D, 0x34, 0x3, 0x05, 0x0D}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0x7F, 0x9D, 0x33, 0x3, 0x04, 0x10}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x53, 0x91, 0x6E, 0x6, 0x0C, 0x08}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x51, 0x8F, 0x6D, 0x6, 0x0A, 0x0B}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x5E, 0x9B, 0x71, 0x8, 0x0E, 0x09}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x5C, 0x99, 0x6F, 0x8, 0x0C, 0x0C}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 5, 0x8D, 0xF9, 0xC9, 0x7, 0x0F, 0x06}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 5, 0x8A, 0xF6, 0xC5, 0x7, 0x0C, 0x08}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x4F, 0x84, 0x68, 0x4, 0x09, 0x07}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x4E, 0x82, 0x66, 0x4, 0x07, 0x09}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x6E, 0x8A, 0x37, 0x3, 0x05, 0x0F}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x6E, 0x8A, 0x36, 0x3, 0x05, 0x16}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x74, 0x8F, 0x38, 0x4, 0x06, 0x11}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x74, 0x8F, 0x38, 0x4, 0x06, 0x18}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x68, 0x80, 0x32, 0x2, 0x04, 0x0E}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 4, 0xCF, 0xFF, 0x62, 0x4, 0x06, 0x10}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x6D, 0x84, 0x34, 0x2, 0x04, 0x0E}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x6C, 0x83, 0x33, 0x2, 0x04, 0x13}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x5D, 0xCD, 0x75, 0x6, 0x0B, 0x0A}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x5B, 0xCB, 0x73, 0x6, 0x09, 0x0D}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x68, 0xD6, 0x77, 0x7, 0x0C, 0x0B}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x66, 0xD5, 0x76, 0x7, 0x0B, 0x0E}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x50, 0xB9, 0x66, 0x3, 0x07, 0x08}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x4E, 0xB8, 0x65, 0x3, 0x06, 0x0A}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x58, 0xC0, 0x69, 0x4, 0x08, 0x09}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x57, 0xBE, 0x68, 0x4, 0x07, 0x0B}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x73, 0xA7, 0x3A, 0x3, 0x05, 0x13}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x73, 0xA6, 0x3A, 0x3, 0x05, 0x1A}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x79, 0xAB, 0x3B, 0x4, 0x06, 0x15}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x79, 0xAB, 0x3B, 0x4, 0x05, 0x1B}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x6D, 0x9D, 0x33, 0x2, 0x03, 0x0F}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x6D, 0x9C, 0x32, 0x2, 0x03, 0x14}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x71, 0xA0, 0x34, 0x2, 0x04, 0x11}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x71, 0xA0, 0x34, 0x2, 0x03, 0x14}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x5A, 0xBA, 0x7F, 0x5, 0x0A, 0x0B}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x59, 0xB9, 0x7E, 0x5, 0x09, 0x0F}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x65, 0xC3, 0x81, 0x7, 0x0B, 0x0C}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x64, 0xC2, 0x80, 0x7, 0x0A, 0x10}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x4D, 0xA7, 0x6B, 0x3, 0x06, 0x09}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x4C, 0xA6, 0x69, 0x3, 0x05, 0x0A}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x55, 0xAD, 0x6E, 0x4, 0x07, 0x09}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x54, 0xAC, 0x6C, 0x4, 0x06, 0x0C}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x68, 0x94, 0x3F, 0x3, 0x05, 0x15}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x68, 0x94, 0x3F, 0x3, 0x04, 0x1B}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x6E, 0x99, 0x40, 0x4, 0x05, 0x16}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x6D, 0x98, 0x40, 0x4, 0x05, 0x1E}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x62, 0x8A, 0x35, 0x2, 0x03, 0x11}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x62, 0x8A, 0x35, 0x2, 0x03, 0x16}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x66, 0x8E, 0x37, 0x2, 0x03, 0x11}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x66, 0x8D, 0x36, 0x2, 0x03, 0x17}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x58, 0xAC, 0x86, 0x5, 0x09, 0x0C}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x57, 0xAB, 0x85, 0x5, 0x08, 0x10}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x63, 0xB5, 0x88, 0x6, 0x0B, 0x0E}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x62, 0xB4, 0x87, 0x6, 0x0A, 0x12}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x4A, 0x99, 0x6D, 0x3, 0x06, 0x0A}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x49, 0x98, 0x6C, 0x3, 0x05, 0x0C}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x53, 0x9F, 0x70, 0x4, 0x07, 0x0B}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x52, 0x9E, 0x6F, 0x4, 0x06, 0x0D}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x60, 0x86, 0x43, 0x3, 0x04, 0x16}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x60, 0x86, 0x43, 0x3, 0x04, 0x1D}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x65, 0x8B, 0x44, 0x3, 0x05, 0x18}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x65, 0x8B, 0x44, 0x3, 0x05, 0x22}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 4, 0xB2, 0xF9, 0x6C, 0x3, 0x05, 0x11}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 4, 0xB1, 0xF8, 0x6C, 0x3, 0x05, 0x16}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 4, 0xBA, 0xFF, 0x6F, 0x4, 0x06, 0x13}, + {{{VDD_135, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 4, 0xB9, 0xFF, 0x6F, 0x4, 0x05, 0x17}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x63, 0xA3, 0x69, 0x7, 0x0D, 0x07}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x61, 0xA1, 0x67, 0x7, 0x0B, 0x09}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x6E, 0xAD, 0x6C, 0x9, 0x10, 0x08}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x6C, 0xAB, 0x6A, 0x9, 0x0E, 0x0B}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x57, 0x8F, 0x65, 0x4, 0x09, 0x06}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x55, 0x8D, 0x63, 0x4, 0x07, 0x07}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x5F, 0x96, 0x68, 0x5, 0x0A, 0x06}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x5D, 0x94, 0x67, 0x5, 0x08, 0x08}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x99, 0xBC, 0x34, 0x4, 0x06, 0x10}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x99, 0xBC, 0x33, 0x4, 0x06, 0x16}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0x9F, 0xC1, 0x36, 0x5, 0x07, 0x11}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0x9E, 0xC1, 0x35, 0x5, 0x07, 0x18}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x93, 0xB2, 0x32, 0x2, 0x04, 0x0D}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0x93, 0xB1, 0x31, 0x2, 0x03, 0x0F}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0x98, 0xB6, 0x34, 0x3, 0x05, 0x0F}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0x97, 0xB5, 0x33, 0x3, 0x04, 0x12}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x5D, 0x91, 0x6E, 0x6, 0x0C, 0x08}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x5B, 0x8F, 0x6D, 0x6, 0x0A, 0x0B}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x68, 0x9B, 0x71, 0x8, 0x0E, 0x09}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x67, 0x99, 0x6F, 0x8, 0x0C, 0x0D}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 5, 0xA2, 0xF9, 0xC8, 0x7, 0x0F, 0x07}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 5, 0x9E, 0xF6, 0xC5, 0x7, 0x0C, 0x08}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x5A, 0x84, 0x68, 0x4, 0x09, 0x07}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x58, 0x82, 0x66, 0x4, 0x07, 0x09}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x82, 0x9E, 0x37, 0x3, 0x05, 0x11}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x81, 0x9D, 0x36, 0x3, 0x05, 0x17}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x88, 0xA3, 0x38, 0x4, 0x06, 0x12}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x87, 0xA2, 0x38, 0x4, 0x06, 0x1A}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x7C, 0x94, 0x32, 0x2, 0x03, 0x0E}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0x7B, 0x93, 0x31, 0x2, 0x03, 0x12}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x80, 0x97, 0x34, 0x2, 0x04, 0x0F}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0x80, 0x97, 0x33, 0x2, 0x04, 0x14}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x63, 0xAA, 0x74, 0x6, 0x0B, 0x0A}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x62, 0xA9, 0x73, 0x6, 0x09, 0x0D}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x6F, 0xB4, 0x77, 0x7, 0x0C, 0x0B}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x6D, 0xB2, 0x76, 0x7, 0x0B, 0x0F}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x56, 0x96, 0x66, 0x3, 0x07, 0x08}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x55, 0x95, 0x64, 0x3, 0x06, 0x0A}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x5F, 0x9D, 0x69, 0x4, 0x08, 0x09}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x5D, 0x9C, 0x68, 0x4, 0x07, 0x0B}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x73, 0x97, 0x3A, 0x3, 0x05, 0x13}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x73, 0x96, 0x3A, 0x3, 0x05, 0x1A}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x79, 0x9C, 0x3B, 0x4, 0x06, 0x15}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x78, 0x9B, 0x3B, 0x4, 0x05, 0x1B}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x6D, 0x8D, 0x33, 0x2, 0x03, 0x0F}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0x6C, 0x8D, 0x32, 0x2, 0x03, 0x14}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x71, 0x90, 0x34, 0x2, 0x04, 0x11}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0x70, 0x90, 0x34, 0x2, 0x03, 0x14}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x60, 0x9C, 0x7F, 0x5, 0x0A, 0x0B}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x5F, 0x9B, 0x7E, 0x5, 0x09, 0x0F}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x6B, 0xA6, 0x81, 0x7, 0x0B, 0x0C}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x6A, 0xA5, 0x80, 0x7, 0x0A, 0x10}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x53, 0x89, 0x6A, 0x3, 0x06, 0x09}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x52, 0x88, 0x69, 0x3, 0x05, 0x0B}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x5B, 0x90, 0x6D, 0x4, 0x07, 0x0A}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x5A, 0x8F, 0x6C, 0x4, 0x06, 0x0C}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x68, 0x87, 0x3F, 0x3, 0x05, 0x15}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x68, 0x86, 0x3F, 0x3, 0x04, 0x1A}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x6D, 0x8B, 0x40, 0x4, 0x05, 0x16}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x6D, 0x8B, 0x40, 0x4, 0x05, 0x1E}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 4, 0xC3, 0xF9, 0x6A, 0x3, 0x05, 0x10}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 4, 0xC2, 0xF9, 0x69, 0x3, 0x05, 0x14}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0x66, 0x80, 0x37, 0x2, 0x03, 0x11}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 4, 0xCA, 0xFF, 0x6C, 0x4, 0x06, 0x16}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x5D, 0x92, 0x86, 0x5, 0x09, 0x0C}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x5C, 0x91, 0x85, 0x5, 0x08, 0x10}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x68, 0x9B, 0x88, 0x6, 0x0B, 0x0E}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x67, 0x9A, 0x87, 0x6, 0x0A, 0x12}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 5, 0x9F, 0xFD, 0xDA, 0x5, 0x0B, 0x0A}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 5, 0x9D, 0xFB, 0xD8, 0x5, 0x09, 0x0B}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x58, 0x85, 0x70, 0x4, 0x07, 0x0B}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x57, 0x84, 0x6F, 0x4, 0x06, 0x0D}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 4, 0xBF, 0xF4, 0x85, 0x5, 0x08, 0x15}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 4, 0xBE, 0xF4, 0x85, 0x5, 0x08, 0x1D}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 4, 0xCA, 0xFE, 0x87, 0x6, 0x0A, 0x18}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 4, 0xC9, 0xFD, 0x87, 0x6, 0x09, 0x20}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 4, 0xB1, 0xE1, 0x6C, 0x3, 0x05, 0x11}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 4, 0xB1, 0xE1, 0x6C, 0x3, 0x05, 0x16}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 4, 0xB9, 0xE8, 0x6F, 0x4, 0x06, 0x13}, + {{{VDD_135, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 4, 0xB9, 0xE7, 0x6F, 0x4, 0x05, 0x17}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x6E, 0xB7, 0x76, 0x8, 0x0E, 0x06}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x6C, 0xB5, 0x74, 0x8, 0x0C, 0x09}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x7B, 0xC2, 0x79, 0xA, 0x11, 0x07}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x79, 0xC0, 0x77, 0xA, 0x0F, 0x0A}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x68, 0xA7, 0x7D, 0x5, 0x0A, 0x05}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_2, 0}}, 4, 0x66, 0xA5, 0x7B, 0x5, 0x08, 0x07}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x73, 0xB0, 0x81, 0x6, 0x0C, 0x06}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_4, 0}}, 4, 0x71, 0xAF, 0x7F, 0x6, 0x0A, 0x08}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0xC0, 0xE3, 0x3A, 0x4, 0x07, 0x0D}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0xBF, 0xE2, 0x3A, 0x4, 0x06, 0x12}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0xC6, 0xE8, 0x3C, 0x5, 0x08, 0x0E}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0xC6, 0xE8, 0x3B, 0x5, 0x07, 0x14}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0xBD, 0xDB, 0x3E, 0x3, 0x04, 0x0A}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_2, 0}}, 3, 0xBC, 0xDA, 0x3D, 0x3, 0x04, 0x0E}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0xC2, 0xDF, 0x40, 0x3, 0x05, 0x0B}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_4, 0}}, 3, 0xC2, 0xDF, 0x40, 0x3, 0x05, 0x10}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x68, 0xA2, 0x7B, 0x7, 0x0D, 0x07}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x66, 0xA1, 0x7A, 0x7, 0x0B, 0x0A}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x75, 0xAE, 0x7E, 0x9, 0x0F, 0x08}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x73, 0xAC, 0x7D, 0x9, 0x0D, 0x0C}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x62, 0x93, 0x7D, 0x4, 0x09, 0x06}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_2, 0}}, 4, 0x61, 0x92, 0x7B, 0x4, 0x07, 0x08}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x6D, 0x9C, 0x81, 0x5, 0x0A, 0x07}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_4, 0}}, 4, 0x6B, 0x9A, 0x7F, 0x5, 0x08, 0x09}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0xD3, 0xED, 0x3D, 0x4, 0x06, 0x0F}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0xD3, 0xEC, 0x3D, 0x4, 0x05, 0x14}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0xDA, 0xF2, 0x3F, 0x5, 0x07, 0x10}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0xD9, 0xF2, 0x3E, 0x5, 0x07, 0x19}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0xD0, 0xE5, 0x3E, 0x2, 0x04, 0x0D}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_2, 0}}, 3, 0xD0, 0xE5, 0x3D, 0x2, 0x04, 0x11}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0xD6, 0xE9, 0x40, 0x3, 0x05, 0x0E}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_4, 0}}, 3, 0xD5, 0xE9, 0x40, 0x3, 0x04, 0x12}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x64, 0x95, 0x83, 0x6, 0x0B, 0x08}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x63, 0x94, 0x81, 0x6, 0x0A, 0x0B}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x71, 0xA0, 0x85, 0x8, 0x0D, 0x09}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x70, 0x9F, 0x84, 0x8, 0x0C, 0x0D}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x5D, 0x86, 0x7E, 0x4, 0x08, 0x07}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_2, 0}}, 4, 0x5C, 0x85, 0x7D, 0x4, 0x07, 0x09}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x68, 0x8F, 0x82, 0x5, 0x09, 0x07}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_4, 0}}, 4, 0x66, 0x8D, 0x81, 0x5, 0x08, 0x0A}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0xB7, 0xCC, 0x41, 0x3, 0x05, 0x10}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0xB7, 0xCC, 0x41, 0x3, 0x05, 0x17}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0xBD, 0xD2, 0x42, 0x4, 0x06, 0x11}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0xBD, 0xD1, 0x42, 0x4, 0x06, 0x1A}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0xB3, 0xC5, 0x3F, 0x2, 0x04, 0x0E}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_2, 0}}, 3, 0xB3, 0xC4, 0x3F, 0x2, 0x03, 0x11}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0xB9, 0xC9, 0x41, 0x3, 0x04, 0x0E}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_4, 0}}, 3, 0xB8, 0xC9, 0x41, 0x3, 0x04, 0x14}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x62, 0x8C, 0x8E, 0x6, 0x0B, 0x0A}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x61, 0x8A, 0x8D, 0x6, 0x0A, 0x0D}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x6E, 0x96, 0x90, 0x8, 0x0C, 0x0A}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x6D, 0x95, 0x8F, 0x8, 0x0B, 0x0F}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x5B, 0x7D, 0x84, 0x4, 0x07, 0x08}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_2, 0}}, 4, 0x5A, 0x7C, 0x83, 0x4, 0x06, 0x0A}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x65, 0x85, 0x88, 0x5, 0x08, 0x08}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1867, DENSITY_4, 0}}, 4, 0x64, 0x84, 0x87, 0x5, 0x07, 0x0B}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0xA3, 0xB5, 0x47, 0x3, 0x05, 0x12}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0xA2, 0xB5, 0x47, 0x3, 0x05, 0x1A}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0xA9, 0xBA, 0x48, 0x4, 0x06, 0x14}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0xA9, 0xBA, 0x48, 0x4, 0x06, 0x1E}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x9F, 0xAE, 0x42, 0x2, 0x03, 0x0E}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_2, 0}}, 3, 0x9F, 0xAD, 0x42, 0x2, 0x03, 0x13}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0xA4, 0xB2, 0x44, 0x3, 0x04, 0x10}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1867, DENSITY_4, 0}}, 3, 0xA4, 0xB2, 0x44, 0x3, 0x04, 0x17}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x60, 0x85, 0x97, 0x6, 0x0A, 0x0B}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x5F, 0x84, 0x96, 0x6, 0x09, 0x0E}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x6C, 0x8F, 0x99, 0x7, 0x0C, 0x0C}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x6B, 0x8E, 0x98, 0x7, 0x0B, 0x11}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x58, 0x76, 0x88, 0x3, 0x07, 0x09}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_2, 0}}, 4, 0x57, 0x75, 0x87, 0x3, 0x06, 0x0B}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x62, 0x7E, 0x8B, 0x4, 0x08, 0x09}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_2133, DENSITY_4, 0}}, 4, 0x61, 0x7D, 0x8A, 0x4, 0x07, 0x0C}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x94, 0xA4, 0x4B, 0x3, 0x05, 0x14}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x93, 0xA3, 0x4B, 0x3, 0x05, 0x1E}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x9A, 0xA9, 0x4C, 0x4, 0x06, 0x16}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x99, 0xA8, 0x4C, 0x4, 0x05, 0x1E}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x90, 0x9C, 0x44, 0x2, 0x03, 0x0F}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_2, 0}}, 3, 0x8F, 0x9C, 0x43, 0x2, 0x03, 0x15}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x95, 0xA0, 0x45, 0x2, 0x04, 0x11}, + {{{VDD_135, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_2133, DENSITY_4, 0}}, 3, 0x95, 0xA0, 0x45, 0x2, 0x03, 0x16}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1067, DENSITY_1, 0}}, 3, 0x5A, 0xAD, 0xCC, 0x8, 0x0E, 0x17}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1067, DENSITY_1, 0}}, 3, 0x5B, 0x8A, 0xCD, 0x8, 0x10, 0x11}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1067, DENSITY_1, 0}}, 3, 0xC5, 0xEE, 0xCB, 0x8, 0x0E, 0x2B}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1067, DENSITY_1, 0}}, 3, 0xC5, 0xEF, 0xCC, 0x8, 0x0F, 0x1E}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1067, DENSITY_1, 0}}, 3, 0x61, 0x88, 0xCC, 0x8, 0x0E, 0x17}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1067, DENSITY_1, 0}}, 3, 0x62, 0x8A, 0xCD, 0x8, 0x10, 0x11}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1067, DENSITY_1, 0}}, 2, 0x72, 0x86, 0x66, 0x4, 0x07, 0x2C}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1067, DENSITY_1, 0}}, 2, 0x72, 0x87, 0x66, 0x4, 0x08, 0x20}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1067, DENSITY_1, 0}}, 3, 0x6D, 0x99, 0xE5, 0x9, 0x10, 0x17}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1067, DENSITY_1, 0}}, 3, 0x6E, 0x9A, 0xE6, 0x9, 0x11, 0x10}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1067, DENSITY_1, 0}}, 2, 0x8C, 0xA0, 0x73, 0x5, 0x08, 0x2B}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1067, DENSITY_1, 0}}, 2, 0x8C, 0xA1, 0x73, 0x5, 0x08, 0x1B}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_1, 0}}, 3, 0x40, 0x97, 0x62, 0x5, 0x08, 0x0E}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_1, 0}}, 4, 0x83, 0xE7, 0xC5, 0x9, 0x12, 0x0A}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_1, 0}}, 3, 0xAB, 0xD8, 0x61, 0x5, 0x08, 0x1B}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_1, 0}}, 3, 0xAC, 0xD9, 0x62, 0x5, 0x08, 0x14}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_1, 0}}, 4, 0x8E, 0xE4, 0xC3, 0x9, 0x10, 0x0E}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_1, 0}}, 4, 0x90, 0xE6, 0xC5, 0x9, 0x12, 0x0B}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_1, 0}}, 3, 0xC9, 0xF6, 0x61, 0x5, 0x08, 0x1D}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_1, 0}}, 3, 0xCA, 0xF7, 0x62, 0x5, 0x08, 0x15}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1067, DENSITY_1, 0}}, 3, 0x57, 0x88, 0x7A, 0x6, 0x0A, 0x0F}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1067, DENSITY_1, 0}}, 3, 0x58, 0x8A, 0x7B, 0x6, 0x0B, 0x0A}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1067, DENSITY_1, 0}}, 2, 0x81, 0x98, 0x3D, 0x3, 0x05, 0x1C}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1067, DENSITY_1, 0}}, 2, 0x81, 0x98, 0x3D, 0x3, 0x05, 0x12}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1333, DENSITY_1, 0}}, 3, 0x58, 0x76, 0xA8, 0x8, 0x0D, 0x1A}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1333, DENSITY_1, 0}}, 3, 0x59, 0x77, 0xA9, 0x8, 0x0E, 0x13}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1333, DENSITY_1, 0}}, 3, 0xAD, 0xC8, 0xA8, 0x8, 0x0C, 0x2E}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1333, DENSITY_1, 0}}, 3, 0xAD, 0xC8, 0xA9, 0x8, 0x0D, 0x20}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1333, DENSITY_1, 0}}, 3, 0x5D, 0x76, 0xA8, 0x8, 0x0D, 0x1A}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1333, DENSITY_1, 0}}, 3, 0x5E, 0x77, 0xA9, 0x8, 0x0E, 0x13}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1333, DENSITY_1, 0}}, 3, 0xC5, 0xE0, 0xA8, 0x8, 0x0C, 0x2F}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1333, DENSITY_1, 0}}, 3, 0xC5, 0xE0, 0xA9, 0x8, 0x0D, 0x22}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1333, DENSITY_1, 0}}, 3, 0x68, 0x85, 0xBD, 0x8, 0x0E, 0x19}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1333, DENSITY_1, 0}}, 3, 0x69, 0x86, 0xBE, 0x8, 0x0F, 0x11}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1333, DENSITY_1, 0}}, 2, 0x97, 0xA3, 0x5F, 0x4, 0x07, 0x30}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1333, DENSITY_1, 0}}, 2, 0x98, 0xA3, 0x5F, 0x4, 0x07, 0x1E}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_1, 0}}, 4, 0x83, 0xCA, 0xC7, 0x8, 0x0E, 0x10}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_1, 0}}, 4, 0x85, 0xCC, 0xC9, 0x8, 0x10, 0x0C}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_1, 0}}, 3, 0x97, 0xB6, 0x63, 0x4, 0x07, 0x1E}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_1, 0}}, 3, 0x97, 0xB7, 0x64, 0x4, 0x07, 0x16}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_1, 0}}, 4, 0x8E, 0xCA, 0xC7, 0x8, 0x0E, 0x10}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_1, 0}}, 4, 0x8F, 0xCB, 0xC9, 0x8, 0x10, 0x0C}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_1, 0}}, 3, 0xAF, 0xCF, 0x63, 0x4, 0x07, 0x20}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_1, 0}}, 3, 0xB0, 0xCF, 0x64, 0x4, 0x07, 0x17}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1333, DENSITY_1, 0}}, 4, 0xAE, 0xF2, 0xF8, 0x9, 0x10, 0x10}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1333, DENSITY_1, 0}}, 4, 0xB0, 0xF4, 0xFA, 0x9, 0x12, 0x0C}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1333, DENSITY_1, 0}}, 2, 0x8F, 0x9D, 0x3E, 0x3, 0x04, 0x1F}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1333, DENSITY_1, 0}}, 2, 0x8F, 0x9D, 0x3F, 0x3, 0x05, 0x17}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1600, DENSITY_1, 0}}, 3, 0x5D, 0x97, 0x94, 0x6, 0x0B, 0x1C}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1600, DENSITY_1, 0}}, 3, 0x5E, 0x98, 0x95, 0x6, 0x0C, 0x15}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1600, DENSITY_1, 0}}, 3, 0xB2, 0xE7, 0x93, 0x6, 0x0B, 0x34}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1600, DENSITY_1, 0}}, 3, 0xB3, 0xE7, 0x94, 0x6, 0x0B, 0x23}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1600, DENSITY_1, 0}}, 3, 0x60, 0x82, 0x94, 0x6, 0x0B, 0x1D}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1600, DENSITY_1, 0}}, 3, 0x61, 0x83, 0x95, 0x6, 0x0C, 0x15}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1600, DENSITY_1, 0}}, 3, 0xB2, 0xD3, 0x93, 0x6, 0x0B, 0x34}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1600, DENSITY_1, 0}}, 3, 0xB2, 0xD4, 0x94, 0x6, 0x0B, 0x23}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_1, FREQ_1600, DENSITY_1, 0}}, 3, 0x65, 0x78, 0xA6, 0x7, 0x0C, 0x1A}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_1, FREQ_1600, DENSITY_1, 0}}, 3, 0x66, 0x79, 0xA7, 0x7, 0x0D, 0x12}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_2, DPC_2, FREQ_1600, DENSITY_1, 0}}, 2, 0x85, 0x8C, 0x53, 0x4, 0x06, 0x31}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_8, RANKS_1, DPC_2, FREQ_1600, DENSITY_1, 0}}, 2, 0x86, 0x8C, 0x53, 0x4, 0x06, 0x1F}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_1, 0}}, 3, 0x47, 0x88, 0x60, 0x4, 0x06, 0x12}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_1, 0}}, 3, 0x48, 0x89, 0x61, 0x4, 0x07, 0x0E}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_1, 0}}, 3, 0x9C, 0xD8, 0x60, 0x4, 0x06, 0x22}, + {{{VDD_150, ECC_F, TYPE_SODIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_1, 0}}, 3, 0x9D, 0xD8, 0x60, 0x4, 0x06, 0x19}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_1, 0}}, 4, 0x94, 0xE5, 0xC0, 0x7, 0x0C, 0x12}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_1, 0}}, 4, 0x96, 0xE7, 0xC1, 0x7, 0x0E, 0x0E}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_1, 0}}, 3, 0x9C, 0xC4, 0x60, 0x4, 0x06, 0x22}, + {{{VDD_150, ECC_F, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_1, 0}}, 3, 0x9C, 0xC5, 0x60, 0x4, 0x06, 0x19}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_1, FREQ_1600, DENSITY_1, 0}}, 4, 0xA7, 0xDD, 0xEF, 0x8, 0x0E, 0x11}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_1, FREQ_1600, DENSITY_1, 0}}, 4, 0xA9, 0xDE, 0xF0, 0x8, 0x10, 0x0D}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_2, DPC_2, FREQ_1600, DENSITY_1, 0}}, 2, 0x7D, 0x88, 0x3C, 0x2, 0x04, 0x24}, + {{{VDD_150, ECC_T, TYPE_UDIMM, WIDTH_16, RANKS_1, DPC_2, FREQ_1600, DENSITY_1, 0}}, 2, 0x7D, 0x88, 0x3C, 0x2, 0x04, 0x18} +}; +const Ddr3PowerWeightEntry Ddr3WcPowerWeightTable[] = { + {{{VDD_135, ECC_F, TYPE_SODIMM, 0 , 0 , 0 , 0 , 0 , 0}}, 3, 0x87, 0xAB, 0x44, 0x5, 0x08, 0x22}, + {{{VDD_135, ECC_F, TYPE_UDIMM, 0 , 0 , 0 , 0 , 0 , 0}}, 3, 0x9F, 0xC1, 0x44, 0x5, 0x08, 0x20}, + {{{VDD_135, ECC_T, TYPE_UDIMM, 0 , 0 , 0 , 0 , 0 , 0}}, 3, 0xDA, 0xF2, 0x4D, 0x5, 0x09, 0x1E}, + {{{VDD_150, ECC_F, TYPE_SODIMM, 0 , 0 , 0 , 0 , 0 , 0}}, 3, 0xC5, 0xEF, 0xCD, 0x8, 0x10, 0x34}, + {{{VDD_150, ECC_F, TYPE_UDIMM, 0 , 0 , 0 , 0 , 0 , 0}}, 2, 0x72, 0x87, 0x67, 0x4, 0x08, 0x34}, + {{{VDD_150, ECC_T, TYPE_UDIMM, 0 , 0 , 0 , 0 , 0 , 0}}, 2, 0x98, 0xA3, 0x73, 0x5, 0x09, 0x31}, + {{{0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0}}, 2, 0x98, 0xA3, 0x73, 0x5, 0x09, 0x34} +}; + +const Lpddr3PowerWeightEntry Lpddr3PowerWeightTable[] = { + {{{VDD_120, 0, 0, WIDTH_32, RANKS_2, 0, FREQ_1333, DENSITY_4, 0}}, 5, 0xA9, 0x84, 0xEE, 0x2, 0x4, 0x6, 0x3}, + {{{VDD_120, 0, 0, WIDTH_32, RANKS_1, 0, FREQ_1333, DENSITY_4, 0}}, 5, 0x91, 0x4C, 0xEE, 0x2, 0x4, 0x5, 0x3}, + {{{VDD_120, 0, 0, WIDTH_32, RANKS_2, 0, FREQ_1600, DENSITY_4, 0}}, 5, 0xA3, 0x79, 0xE9, 0x2, 0x3, 0x7, 0x4}, + {{{VDD_120, 0, 0, WIDTH_32, RANKS_1, 0, FREQ_1600, DENSITY_4, 0}}, 5, 0x8B, 0x4A, 0xE9, 0x2, 0x3, 0x6, 0x3}, + {{{VDD_120, 0, 0, WIDTH_16, RANKS_2, 0, FREQ_1333, DENSITY_4, 0}}, 4, 0x6B, 0x56, 0xE0, 0x2, 0x3, 0x9, 0x5}, + {{{VDD_120, 0, 0, WIDTH_16, RANKS_1, 0, FREQ_1333, DENSITY_4, 0}}, 4, 0x5F, 0x3D, 0xE0, 0x2, 0x3, 0x8, 0x4}, + {{{VDD_120, 0, 0, WIDTH_16, RANKS_2, 0, FREQ_1600, DENSITY_4, 0}}, 4, 0x67, 0x4F, 0xDB, 0x2, 0x3, 0xA, 0x6}, + {{{VDD_120, 0, 0, WIDTH_16, RANKS_1, 0, FREQ_1600, DENSITY_4, 0}}, 4, 0x5B, 0x38, 0xDB, 0x2, 0x3, 0x9, 0x5} +}; +const Lpddr3PowerWeightEntry Lpddr3WcPowerWeightTable[] = { + {{{0 , 0, 0, 0 , 0 , 0, 0 , 0 , 0}}, 4, 0x6B, 0x56, 0xE0, 0x2, 0x3, 0xA, 0x6} +}; + +/** +@brief + This function configure the MC power register post training after normal mode before PCU start working. + + @param[in, out] MrcData - Include all MRC global data. + + @retval Nothing. +**/ +void +MrcPowerModesPostTraining ( + IN OUT MrcParameters *const MrcData + ) +{ + const MrcInput *Inputs; + MrcOutput *Outputs; + MrcControllerOut *ControllerOut; + MrcChannelOut *ChannelOut; + MCHBAR_CH0_CR_TC_BANK_RANK_D_STRUCT TcBankRankD; + MCDECS_CR_MCDECS_CBIT_MCMAIN_STRUCT McdecsCbit; + U32 Offset; + U8 Controller; + U8 Channel; + + Inputs = &MrcData->SysIn.Inputs; + Outputs = &MrcData->SysOut.Outputs; + for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) { + ControllerOut = &Outputs->Controller[Controller]; + for (Channel = 0; Channel < MAX_CHANNEL; Channel++) { + if (MrcChannelExist (Outputs, Channel)) { + ChannelOut = &ControllerOut->Channel[Channel]; + // + // Configure Tcpded and Tprpden + // + TcBankRankD.Data = ChannelOut->MchbarBANKRANKD; + if (Outputs->Frequency >= f1867) { + TcBankRankD.Bits.tCPDED = 2; + } + + if (Outputs->Frequency >= f2133) { + TcBankRankD.Bits.tPRPDEN = 2; + } + + Offset = MCHBAR_CH0_CR_TC_BANK_RANK_D_REG + + ((MCHBAR_CH1_CR_TC_BANK_RANK_D_REG - MCHBAR_CH0_CR_TC_BANK_RANK_D_REG) * Channel); + MrcWriteCR (MrcData, Offset, TcBankRankD.Data); + + // + // Save in MrcData structure + // + ChannelOut->MchbarBANKRANKD = TcBankRankD.Data; + } + } + } + // + // Configure Power Down CR + // + MrcPowerDownConfig (MrcData); + + // + // Initialize McDecs_CBIT + // + McdecsCbit.Data = MCDECS_CBIT_DEFAULT; + if (!Inputs->WeaklockEn) { + McdecsCbit.Bits.dis_msg_clk_gate = 1; + } + MrcWriteCrMulticast (MrcData, MCDECS_CR_MCDECS_CBIT_MCMAIN_REG, McdecsCbit.Data); + + return; +} + +/** +@brief + This function configures the power down control register. + + @param[in] - MrcData - The MRC global data. + + @retval - Nothing +**/ +void +MrcPowerDownConfig ( + IN MrcParameters *const MrcData + ) +{ + const MrcInput *Inputs; + MrcOutput *Outputs; + U32 PowerDownMode; + MCSCHEDS_CR_PM_PDWN_CONFIG_STRUCT PmPdwnConfig; + + Inputs = &MrcData->SysIn.Inputs; + Outputs = &MrcData->SysOut.Outputs; + + PmPdwnConfig.Data = 0; + PmPdwnConfig.Bits.PDWN_idle_counter = PDWN_IDLE_COUNTER; + + if (Inputs->PwdwnIdleCounter) { + PmPdwnConfig.Bits.PDWN_idle_counter = Inputs->PwdwnIdleCounter; + } + + if ((Inputs->PowerDownMode == pdmNoPowerDown) || + (Inputs->PowerDownMode == pdmAPD) || + (Inputs->PowerDownMode == pdmPPDDLLOFF) + ) { + PowerDownMode = Inputs->PowerDownMode; + } else { + PowerDownMode = pdmPPDDLLOFF; +#ifdef ULT_FLAG + if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) { + PowerDownMode = pdmPPD; + } +#endif // ULT_FLAG + } + + PmPdwnConfig.Bits.PDWN_mode = PowerDownMode; + MrcWriteCR (MrcData, MCSCHEDS_CR_PM_PDWN_CONFIG_REG, PmPdwnConfig.Data); + + return; +} + +/** +@brief + This functions sets power weight, scale factor and Channel + Power Floor values from lookup table based on DIMMs present in + the system. + + @param[in] MrcData - Include all MRC global data. + + @retval MrcStatus - mrcSuccess or reason for failure. +**/ +MrcStatus +MrcPowerWeight ( + IN MrcParameters *const MrcData + ) +{ + const MrcInput *Inputs; + const MrcControllerIn *ControllerIn; + const MrcDimmIn *DimmIn; + const MrcSpd *Spd; + const MrcDebug *Debug; + MrcOutput *Outputs; + MrcControllerOut *ControllerOut; + MrcDimmOut *DimmOut; + U8 Controller; + U8 Channel; + U8 Dimm; + const Ddr3PowerWeightEntry *Ddr3Pwt[2]; + const Lpddr3PowerWeightEntry *Lpddr3Pwt[2]; + U16 PwtSize[2]; + PowerWeightInputs DimmPwt; + U8 i; + U16 j; + BOOL DimmEntryFound; + BOOL EnterWc; + U8 SfDiff; + U8 MinScaleFactor; + U8 ScaleFactor[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; + U8 ChPwrFloor[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; + U32 Offset; + MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_STRUCT PmDimmRdEnergy[MAX_CHANNEL]; + MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_STRUCT PmDimmWrEnergy[MAX_CHANNEL]; + MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_STRUCT PmDimmActEnergy[MAX_CHANNEL]; + MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_STRUCT PmDimmPdEnergy[MAX_CHANNEL]; + MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_STRUCT PmDimmIdleEnergy[MAX_CHANNEL]; + PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_STRUCT DdrRaplChannelPowerFloor; + + Inputs = &MrcData->SysIn.Inputs; + Debug = &MrcData->SysIn.Inputs.Debug; + Outputs = &MrcData->SysOut.Outputs; + MinScaleFactor = (U8) ~0; + Ddr3Pwt[0] = Ddr3PowerWeightTable; + Ddr3Pwt[1] = Ddr3WcPowerWeightTable; + Lpddr3Pwt[0] = Lpddr3PowerWeightTable; + Lpddr3Pwt[1] = Lpddr3WcPowerWeightTable; + DdrRaplChannelPowerFloor.Data = 0; + + MrcOemMemorySet((U8 *) PmDimmRdEnergy, 0, sizeof (PmDimmRdEnergy)); + MrcOemMemorySet((U8 *) PmDimmWrEnergy, 0, sizeof (PmDimmWrEnergy)); + MrcOemMemorySet((U8 *) PmDimmActEnergy, 0, sizeof (PmDimmActEnergy)); + MrcOemMemorySet((U8 *) PmDimmPdEnergy, 0, sizeof (PmDimmPdEnergy)); + MrcOemMemorySet((U8 *) PmDimmIdleEnergy, 0, sizeof (PmDimmIdleEnergy)); + MrcOemMemorySet((U8 *) ScaleFactor, (U32) ~0, sizeof (ScaleFactor)); + MrcOemMemorySet((U8 *) ChPwrFloor, (U32) 0, sizeof (ChPwrFloor)); + + if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) { + PwtSize[0] = sizeof (Lpddr3PowerWeightTable) / sizeof (Lpddr3PowerWeightEntry); + PwtSize[1] = sizeof (Lpddr3WcPowerWeightTable) / sizeof (Lpddr3PowerWeightEntry); + } else { + PwtSize[0] = sizeof (Ddr3PowerWeightTable) / sizeof (Ddr3PowerWeightEntry); + PwtSize[1] = sizeof (Ddr3WcPowerWeightTable) / sizeof (Ddr3PowerWeightEntry); + } + + if (Inputs->MemoryProfile != USER_PROFILE) { + for (Controller = 0; Controller < MAX_CONTROLLERS; Controller++) { + ControllerOut = &Outputs->Controller[Controller]; + ControllerIn = &Inputs->Controller[Controller]; + for (Channel = 0; Channel < MAX_CHANNEL; Channel++) { + if (MrcChannelExist (Outputs, Channel)) { + // + // Collect Channel level data for lookup + // + for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) { + DimmOut = &ControllerOut->Channel[Channel].Dimm[Dimm]; + DimmIn = &ControllerIn->Channel[Channel].Dimm[Dimm]; + if (DimmOut->Status == DIMM_PRESENT) { + EnterWc = FALSE; + DimmPwt.Data = 0; + // + // Collect DIMM level data for lookup + // + + Spd = &DimmIn->Spd; + + switch (Outputs->VddVoltage[Inputs->MemoryProfile]) { + case VDD_1_20: + DimmPwt.Bits.Vddq = VDD_120; + break; + + case VDD_1_35: + DimmPwt.Bits.Vddq = VDD_135; + break; + + case VDD_1_50: + DimmPwt.Bits.Vddq = VDD_150; + break; + + default: + DimmPwt.Bits.Vddq = VDD_OTHER; + EnterWc = TRUE; + break; + } + + DimmPwt.Bits.Ecc = DimmOut->EccSupport; + DimmPwt.Bits.DimmType = DimmOut->ModuleType; + DimmPwt.Bits.DeviceWidth = DimmOut->SdramWidthIndex; + DimmPwt.Bits.NumOfRanks = DimmOut->RankInDIMM; + DimmPwt.Bits.Dpc = ControllerOut->Channel[Channel].DimmCount; + + switch (Outputs->Frequency) { + case f1067: + DimmPwt.Bits.Frequency = FREQ_1067; + break; + + case f1333: + DimmPwt.Bits.Frequency = FREQ_1333; + break; + + case f1600: + DimmPwt.Bits.Frequency = FREQ_1600; + break; + + case f1867: + DimmPwt.Bits.Frequency = FREQ_1867; + break; + + case f2133: + DimmPwt.Bits.Frequency = FREQ_2133; + break; + + default: + EnterWc = TRUE; + break; + } + + DimmPwt.Bits.DramDensity = DimmOut->DensityIndex; + + if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) { + DimmPwt.Bits.Ecc = 0; + DimmPwt.Bits.DimmType = 0; + DimmPwt.Bits.Dpc = 0; + } + + // + // Search lookup table for DIMM entry + // + DimmEntryFound = FALSE; + for (i = 0; i < sizeof (PwtSize) / sizeof (PwtSize[0]); i++) { + if (i == 0) { + if (EnterWc) { + continue; + } + } else if (i == 1) { + if (!DimmEntryFound) { + DimmPwt.Bits.DeviceWidth = 0; + DimmPwt.Bits.NumOfRanks = 0; + DimmPwt.Bits.Dpc = 0; + DimmPwt.Bits.Frequency = 0; + DimmPwt.Bits.DramDensity = 0; + } else { + continue; + } + } + for (j = 0; j < PwtSize[i]; j++) { + if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) { + if (DimmPwt.Data == Lpddr3Pwt[i][j].PwInput.Data || + (i == 1 && j == PwtSize[i] - 1)) { + PmDimmRdEnergy[Channel].Data8[Dimm] = Lpddr3Pwt[i][j].RdCr; + PmDimmWrEnergy[Channel].Data8[Dimm] = Lpddr3Pwt[i][j].WrCr; + PmDimmActEnergy[Channel].Data8[Dimm] = Lpddr3Pwt[i][j].ActCr; + PmDimmPdEnergy[Channel].Data8[Dimm] = Lpddr3Pwt[i][j].CkeL; + PmDimmIdleEnergy[Channel].Data8[Dimm] = Lpddr3Pwt[i][j].CkeH; + ScaleFactor[Channel][Dimm] = Lpddr3Pwt[i][j].ScaleFactor; + ChPwrFloor[Channel][Dimm] = (ControllerOut->ChannelCount == 1) + ? Lpddr3Pwt[i][j].OneChPwrFloor + : Lpddr3Pwt[i][j].TwoChPwrFloor; + MinScaleFactor = MIN (MinScaleFactor, ScaleFactor[Channel][Dimm]); + DimmEntryFound = TRUE; + break; + } + } else { + if (DimmPwt.Data == Ddr3Pwt[i][j].PwInput.Data || + (i == 1 && j == PwtSize[i] - 1)) { + PmDimmRdEnergy[Channel].Data8[Dimm] = Ddr3Pwt[i][j].RdCr; + PmDimmWrEnergy[Channel].Data8[Dimm] = Ddr3Pwt[i][j].WrCr; + PmDimmActEnergy[Channel].Data8[Dimm] = Ddr3Pwt[i][j].ActCr; + PmDimmPdEnergy[Channel].Data8[Dimm] = Ddr3Pwt[i][j].CkeL; + PmDimmIdleEnergy[Channel].Data8[Dimm] = Ddr3Pwt[i][j].CkeH; + ScaleFactor[Channel][Dimm] = Ddr3Pwt[i][j].ScaleFactor; + ChPwrFloor[Channel][Dimm] = Ddr3Pwt[i][j].ChPwrFloor; + MinScaleFactor = MIN (MinScaleFactor, ScaleFactor[Channel][Dimm]); + DimmEntryFound = TRUE; + break; + } + } + } + } + } + } + } + } + } + + for (Channel = 0; Channel < MAX_CHANNEL; Channel++) { + if (MrcChannelExist (Outputs, Channel)) { + for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) { + DimmOut = &Outputs->Controller->Channel[Channel].Dimm[Dimm]; + if (DimmOut->Status == DIMM_PRESENT) { + // + // Set Scale Factor of all DIMMs to lowest Scale Factor and adjust weights accordingly. + // + if ((SfDiff = ScaleFactor[Channel][Dimm] - MinScaleFactor) > 0) { + PmDimmRdEnergy[Channel].Data8[Dimm] = (PmDimmRdEnergy[Channel].Data8[Dimm] + 1) >> SfDiff; + PmDimmWrEnergy[Channel].Data8[Dimm] = (PmDimmWrEnergy[Channel].Data8[Dimm] + 1) >> SfDiff; + PmDimmActEnergy[Channel].Data8[Dimm] = (PmDimmActEnergy[Channel].Data8[Dimm] + 1) >> SfDiff; + PmDimmPdEnergy[Channel].Data8[Dimm] = (PmDimmPdEnergy[Channel].Data8[Dimm] + 1) >> SfDiff; + PmDimmIdleEnergy[Channel].Data8[Dimm] = (PmDimmIdleEnergy[Channel].Data8[Dimm] + 1) >> SfDiff; + } + } + } + // + // Set RAPL Channel Power Floor to average of DIMMs rounded up to nearest integer multiple of 0.125W (which is + // going to be a multiple of 8 for Channel Power Floor Register). + // + if (Outputs->Controller->Channel[Channel].DimmCount > 1) { + if (ChPwrFloor[Channel][0] != ChPwrFloor[Channel][1]) { + ChPwrFloor[Channel][0] = (ChPwrFloor[Channel][0] + ChPwrFloor[Channel][1] + 1) / 2; + if (ChPwrFloor[Channel][0] < 0xF8) { + if ((ChPwrFloor[Channel][0] % 8) != 0) { + ChPwrFloor[Channel][0] = ChPwrFloor[Channel][0] + (8 - (ChPwrFloor[Channel][0] % 8)); + } + } else { // No more 8-bit mulitples of 8 after 0xF8, must round down. + ChPwrFloor[Channel][0] = 0xF8; + } + } + } else { + for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) { + ChPwrFloor[Channel][0] = MAX (ChPwrFloor[Channel][0], ChPwrFloor[Channel][Dimm]); + } + } + + // + // Apply power weights + // + Offset = MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_REG + + (MCHBAR_CH1_CR_PM_DIMM_RD_ENERGY_REG - MCHBAR_CH0_CR_PM_DIMM_RD_ENERGY_REG) * Channel; + MrcWriteCR (MrcData, Offset, PmDimmRdEnergy[Channel].Data); + Offset = MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_REG + + (MCHBAR_CH1_CR_PM_DIMM_WR_ENERGY_REG - MCHBAR_CH0_CR_PM_DIMM_WR_ENERGY_REG) * Channel; + MrcWriteCR (MrcData, Offset, PmDimmWrEnergy[Channel].Data); + Offset = MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_REG + + (MCHBAR_CH1_CR_PM_DIMM_ACT_ENERGY_REG - MCHBAR_CH0_CR_PM_DIMM_ACT_ENERGY_REG) * Channel; + MrcWriteCR (MrcData, Offset, PmDimmActEnergy[Channel].Data); + Offset = MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_REG + + (MCHBAR_CH1_CR_PM_DIMM_PD_ENERGY_REG - MCHBAR_CH0_CR_PM_DIMM_PD_ENERGY_REG) * Channel; + MrcWriteCR (MrcData, Offset, PmDimmPdEnergy[Channel].Data); + Offset = MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_REG + + (MCHBAR_CH1_CR_PM_DIMM_IDLE_ENERGY_REG - MCHBAR_CH0_CR_PM_DIMM_IDLE_ENERGY_REG) * Channel; + MrcWriteCR (MrcData, Offset, PmDimmIdleEnergy[Channel].Data); + } + } + DdrRaplChannelPowerFloor.Bits.CH0 = ChPwrFloor[0][0]; + DdrRaplChannelPowerFloor.Bits.CH1 = ChPwrFloor[1][0]; + MrcWriteCR (MrcData, PCU_CR_DDR_RAPL_CHANNEL_POWER_FLOOR_PCU_REG, DdrRaplChannelPowerFloor.Data); + MrcWriteCR (MrcData, PCU_CR_DDR_ENERGY_SCALEFACTOR_PCU_REG, (U32) MinScaleFactor); + +#ifdef MRC_DEBUG_PRINT + MRC_DEBUG_MSG ( + Debug, + MSG_LEVEL_NOTE, + "Applied Power Weights:\n\tSclFctr\tRdCr\tWrCr\tActCr\tCkeL\tCkeH\tChPwrFloor\n" + ); + for (Channel = 0; Channel < MAX_CHANNEL; Channel++) { + if (MrcChannelExist (Outputs, Channel)) { + for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) { + DimmOut = &Outputs->Controller->Channel[Channel].Dimm[Dimm]; + if (DimmOut->Status == DIMM_PRESENT) { + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "C%dD%d:\t", Channel, Dimm); + MRC_DEBUG_MSG ( + Debug, + MSG_LEVEL_NOTE, + "%d\t%2Xh\t%2Xh\t%2Xh\t%Xh\t%2Xh\t%2Xh\n", + MinScaleFactor, + PmDimmRdEnergy[Channel].Data8[Dimm], + PmDimmWrEnergy[Channel].Data8[Dimm], + PmDimmActEnergy[Channel].Data8[Dimm], + PmDimmPdEnergy[Channel].Data8[Dimm], + PmDimmIdleEnergy[Channel].Data8[Dimm], + ChPwrFloor[Channel][0] + ); + } + } + } + } +#endif + } + + return mrcSuccess; +} diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcPowerModes.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcPowerModes.h new file mode 100644 index 0000000..1242276 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcPowerModes.h @@ -0,0 +1,174 @@ +/** @file + This module includes the power modes definitions. + +@Copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved. + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. +**/ +#ifndef _MrcPowerModes_h_ +#define _MrcPowerModes_h_ +#pragma pack(push, 1) + +#include "McAddress.h" +#include "MrcTypes.h" +#include "MrcCommon.h" +#include "MrcGlobal.h" + +// +// Lookup table definitions +// +#define GEN_DDR3 1 +#define GEN_DDR4 2 +#define VDD_120 1 +#define VDD_135 2 +#define VDD_150 3 +#define VDD_OTHER 4 +#define ECC_F 0 +#define ECC_T 1 +#define TYPE_SODIMM 3 +#define TYPE_UDIMM 2 +#define WIDTH_8 1 +#define WIDTH_16 2 +#define WIDTH_32 3 +#define RANKS_1 1 +#define RANKS_2 2 +#define DPC_1 1 +#define DPC_2 2 +#define FREQ_800 1 +#define FREQ_1000 2 +#define FREQ_1067 3 +#define FREQ_1200 4 +#define FREQ_1333 5 +#define FREQ_1400 6 +#define FREQ_1600 7 +#define FREQ_1800 8 +#define FREQ_1867 9 +#define FREQ_2000 10 +#define FREQ_2133 11 +#define FREQ_2200 12 +#define FREQ_2400 13 +#define FREQ_2600 14 +#define FREQ_2667 15 +#define DENSITY_1 2 +#define DENSITY_2 3 +#define DENSITY_4 4 + +typedef enum { + tsmNoThermalSensing = 0, ///< No thermal sensing in MC + tsmThermalSensor, ///< Thermal Sensor (on DIMM) - when set thermal sense is active + tsmBwEstimation, ///< BW estimation - when set, PM_SUM_PC_CxRy of this DIMM accumulates command power estimation + tsmBoth ///< Both (1) and (2) +} ThermalSensorModes; + +/// +/// Power Down mode +/// +typedef enum { + pdmNoPowerDown = 0, + pdmAPD = 1, + pdmPPD = 2, + pdmPPDDLLOFF = 6, + pdmAuto = 0xFF, +} MrcPowerDownMode; + +typedef union { + struct { + U32 Vddq : 4; + U32 Ecc : 1; + U32 DimmType : 4; + U32 DeviceWidth : 3; + U32 NumOfRanks : 3; + U32 Dpc : 2; + U32 Frequency : 4; + U32 DramDensity : 3; + U32 Spare : 8; + } Bits; + U32 Data; + U16 Data16[2]; + U8 Data8[4]; +} PowerWeightInputs; + +typedef struct { + PowerWeightInputs PwInput; + U8 ScaleFactor; + U8 RdCr; + U8 WrCr; + U8 ActCr; + U8 CkeL; + U8 CkeH; + U8 ChPwrFloor; +} Ddr3PowerWeightEntry; + +typedef struct { + PowerWeightInputs PwInput; + U8 ScaleFactor; + U8 RdCr; + U8 WrCr; + U8 ActCr; + U8 CkeL; + U8 CkeH; + U8 OneChPwrFloor; + U8 TwoChPwrFloor; +} Lpddr3PowerWeightEntry; + +#define PDWN_IDLE_COUNTER (0x80) + +#define MCDECS_CBIT_DEFAULT (0x00000000) + +/** +@brief + This function configure the MC power register post training after normal mode before PCU start working. + + @param[in, out] MrcData - Include all MRC global data. + + @retval Nothing. +**/ +extern +void +MrcPowerModesPostTraining ( + IN OUT MrcParameters *const MrcData + ); + +/** +@brief + This function configures the power down control register. + + @param[in] - MrcData - The MRC global data. + + @retval - Nothing +**/ +extern +void +MrcPowerDownConfig ( + IN MrcParameters *const MrcData + ); + +/** +@brief + This functions applies power weight values from lookup table to every DIMM in the system. + + @param[in] MrcData - Include all MRC global data. + + @retval MrcStatus - mrcSuccess or reason for failure. +**/ +extern +MrcStatus +MrcPowerWeight ( + MrcParameters * const MrcData +); + +#pragma pack(pop) +#endif // _MrcPowerModes_h_ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcRefreshConfiguration.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcRefreshConfiguration.c new file mode 100644 index 0000000..ae958d2 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcRefreshConfiguration.c @@ -0,0 +1,453 @@ +/** @file + This module sets the memory controller refresh parameters. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved. + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. +**/ + +/// +/// Include files +/// +#include "MrcRefreshConfiguration.h" + +/** +@brief + This function returns the tXS offset. + tXS-offset: tXS = tRFC+10ns. Setup of tXS-offset is # of cycles for 10 ns. + + @param[in] Frequency - The memory frequency. + + @retval tXS-offset value. +**/ +static +U32 +tXsOffset ( + IN const MrcFrequency Frequency + ) +{ + U32 tXSOffset; + + if (Frequency <= f800) { + tXSOffset = Offset_10nsec_800; + } else if (Frequency <= f1067) { + tXSOffset = Offset_10nsec_1067; + } else if (Frequency <= f1333) { + tXSOffset = Offset_10nsec_1333; + } else if (Frequency <= f1600) { + tXSOffset = Offset_10nsec_1600; + } else if (Frequency <= f1867) { + tXSOffset = Offset_10nsec_1867; + } else if (Frequency <= f2133) { + tXSOffset = Offset_10nsec_2133; + } else if (Frequency <= f2400) { + tXSOffset = Offset_10nsec_2400; + } else { + tXSOffset = Offset_10nsec_2667; + } + + return tXSOffset; +} + +/** +@brief + This function configures the TC-RFTP register and its fields 9tREFI, tRFC, tREFI. + + @param[in] MrcData - Include all MRC global data. + @param[in] ChannelIndex - Channel to work on. + + @retval Nothing. +**/ +static +void +SetTcRftpReg ( + IN MrcParameters *const MrcData, + IN const U32 ChannelIndex + ) +{ + MrcTiming *TimingOut; + MCHBAR_CH0_CR_TC_RFTP_STRUCT TcRftp; + MrcProfile Profile; + U32 tRefix9; + U32 Offset; + U16 tREFI_MAX; + + Profile = MrcData->SysIn.Inputs.MemoryProfile; + TimingOut = &MrcData->SysOut.Outputs.Controller[0].Channel[ChannelIndex].Timing[Profile]; + tRefix9 = (TimingOut->tREFI * 89) / (1024 * 10); + TcRftp.Data = 0; + tREFI_MAX = MCHBAR_CH0_CR_TC_RFTP_tREFI_MAX; + TcRftp.Bits.tREFI = MIN (tREFI_MAX, TimingOut->tREFI); + TcRftp.Bits.tRFC = MIN (MCHBAR_CH0_CR_TC_RFTP_tRFC_MAX, TimingOut->tRFC); + TcRftp.Bits.tREFIx9 = MIN (MCHBAR_CH0_CR_TC_RFTP_tREFIx9_MAX, tRefix9); + Offset = MCHBAR_CH0_CR_TC_RFTP_REG + + ((MCHBAR_CH1_CR_TC_RFTP_REG - MCHBAR_CH0_CR_TC_RFTP_REG) * ChannelIndex); + MrcWriteCR (MrcData, Offset, TcRftp.Data); + MRC_DEBUG_MSG ( + &MrcData->SysIn.Inputs.Debug, + MSG_LEVEL_NOTE, + "TC-RFTP Channel %u register value = %Xh\n", + ChannelIndex, + TcRftp.Data + ); + return; +} + +/** +@brief + This function configures the TC-SRFTP register and its fields tZQOPER, tXS-offset, tXSDLL. + + @param[in] MrcData - Include all MRC global data. + @param[in] ChannelIndex - Channel to work on. + + @retval Nothing. +**/ +static +void +SetTcSrftpReg ( + IN MrcParameters *const MrcData, + IN const U32 ChannelIndex + ) +{ + const MrcInput *Inputs; + MrcFrequency Frequency; + U32 tZQOPER; + U32 tXS_offset; + U32 tMod; + U32 Offset; + MCHBAR_CH0_CR_TC_SRFTP_STRUCT CrTcSrftp; + + Inputs = &MrcData->SysIn.Inputs; + Frequency = MrcData->SysOut.Outputs.Frequency; + tZQOPER = tZQOPERGet (MrcData, Frequency); + tXS_offset = tXsOffset (Frequency); + tMod = tMODGet (Frequency) - 8; + + CrTcSrftp.Data = 0; + CrTcSrftp.Bits.tXSDLL = MIN (MCHBAR_CH0_CR_TC_SRFTP_tXSDLL_MAX, tDLLK_VALUE); + CrTcSrftp.Bits.tXS_offset = MIN (MCHBAR_CH0_CR_TC_SRFTP_tXS_offset_MAX, tXS_offset); + CrTcSrftp.Bits.tZQOPER = MIN (MCHBAR_CH0_CR_TC_SRFTP_tZQOPER_MAX, tZQOPER); + CrTcSrftp.Bits.tMOD = MIN (MCHBAR_CH0_CR_TC_SRFTP_tMOD_MAX, tMod); + Offset = MCHBAR_CH0_CR_TC_SRFTP_REG + + ((MCHBAR_CH1_CR_TC_SRFTP_REG - MCHBAR_CH0_CR_TC_SRFTP_REG) * ChannelIndex); + MrcWriteCR (MrcData, Offset, CrTcSrftp.Data); + MRC_DEBUG_MSG ( + &Inputs->Debug, + MSG_LEVEL_NOTE, + "Ch%u: TC_SRFTP = %Xh\n tXSDLL = %u\n tXS_offset = %u\n tZQOPER = %u\n tMOD = %u\n", + ChannelIndex, + CrTcSrftp.Data, + CrTcSrftp.Bits.tXSDLL, + CrTcSrftp.Bits.tXS_offset, + CrTcSrftp.Bits.tZQOPER, + CrTcSrftp.Bits.tMOD + ); + return; +} + +/** +@brief + This function returns the tZQOPER value. + tZQOPER = Defines the period required for ZQCL after SR exit. + + @param[in] MrcData - Include all MRC global data. + @param[in] Frequency - The memory frequency. + + @retval The tZQOPER value. +**/ +U32 +tZQOPERGet ( + IN MrcParameters *const MrcData, + IN const MrcFrequency Frequency + ) +{ + U32 tZQOPER; +#ifdef ULT_FLAG + MrcDdrType DdrType; + + DdrType = MrcData->SysOut.Outputs.DdrType; + if (DdrType == MRC_DDR_TYPE_LPDDR3) { + tZQOPER = tZQCL_MIN / (MrcData->SysOut.Outputs.Qclkps * 2); + } else +#endif // ULT_FLAG + { + if (Frequency <= f1600) { + /// + /// All frequencies below 1600 uses the same value + /// + tZQOPER = tZQOPER_1600; + } else if (Frequency <= f1867) { + tZQOPER = tZQOPER_1867; + } else if (Frequency <= f2133) { + tZQOPER = tZQOPER_2133; + } else if (Frequency <= f2400) { + tZQOPER = tZQOPER_2400; + } else { + tZQOPER = tZQOPER_2667; + } + } + + return tZQOPER; +} + +/** +@brief + This function returns the tMOD value. + tMOD = max(12nCK, 15ns) nCK change by the frequency. + + @param[in] Frequency - The memory frequency. + + @retval The tMOD value. +**/ +U32 +tMODGet ( + IN const MrcFrequency Frequency + ) +{ + U32 tMOD; + + if (Frequency <= f800) { + tMOD = tMOD_800; + } else if (Frequency <= f1067) { + tMOD = tMOD_1067; + } else if (Frequency <= f1333) { + tMOD = tMOD_1333; + } else if (Frequency <= f1600) { + tMOD = tMOD_1600; + } else if (Frequency <= f1867) { + tMOD = tMOD_1867; + } else if (Frequency <= f2133) { + tMOD = tMOD_2133; + } else if (Frequency <= f2400) { + tMOD = tMOD_2400; + } else { + tMOD = tMOD_2667; + } + + return tMOD; +} + +/** +@brief + This function configures the TC-ZQCAL register and its fields tZQCS and tZQCS_PERIOD. + + @param[in] MrcData - Include all MRC global data. + @param[in] ChannelIndex - Channel to work on. + + @retval Nothing. +**/ +static +void +SetTcZqCalReg ( + IN MrcParameters *const MrcData, + IN const U32 ChannelIndex + ) +{ + MCHBAR_CH0_CR_TC_ZQCAL_STRUCT ZqCal; + U32 ZQCS_period; + U32 tZQCS; + U32 Offset; + MrcCpuModel CpuModel; +#ifdef ULT_FLAG + MrcDdrType DdrType; +#endif // ULT_FLAG + + CpuModel = MrcData->SysIn.Inputs.CpuModel; + + Offset = MCHBAR_CH0_CR_TC_ZQCAL_REG + (MCHBAR_CH1_CR_TC_ZQCAL_REG - MCHBAR_CH0_CR_TC_ZQCAL_REG) * ChannelIndex; + + ZqCal.Data = 0; + tZQCS = tZQCSGet (MrcData, MrcData->SysOut.Outputs.Frequency); + ZQCS_period = ZQCS_PERIOD_DDR3; + +#ifdef ULT_FLAG + DdrType = MrcData->SysOut.Outputs.DdrType; + if (CpuModel == cmHSW_ULT) { + if (DdrType == MRC_DDR_TYPE_LPDDR3) { + ZQCS_period = ZQCS_PERIOD_LPDDR3; + } + ZqCal.UltBits.ZQCS_period = MIN (MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_Ult_MAX, ZQCS_period); + ZqCal.UltBits.tZQCS = MIN (MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_Ult_MAX, tZQCS); + } else +#endif // ULT_FLAG + { + ZqCal.Bits.ZQCS_period = MIN (MCHBAR_CH0_CR_TC_ZQCAL_ZQCS_period_MAX, ZQCS_period); + ZqCal.Bits.tZQCS = MIN (MCHBAR_CH0_CR_TC_ZQCAL_tZQCS_MAX, tZQCS); + } + MrcWriteCR (MrcData, Offset, ZqCal.Data); + +#ifdef ULT_FLAG + if (CpuModel == cmHSW_ULT) { + ZQCS_period = ZqCal.UltBits.ZQCS_period; + tZQCS = ZqCal.UltBits.tZQCS; + } else +#endif //ULT_FLAG + { + ZQCS_period = ZqCal.Bits.ZQCS_period; + tZQCS = ZqCal.Bits.tZQCS; + } + + MRC_DEBUG_MSG ( + &MrcData->SysIn.Inputs.Debug, + MSG_LEVEL_NOTE, + "Ch%u: TC_ZQCAL = %Xh\n ZQCS_period = %u\n tZQCS = %u\n", + ChannelIndex, + ZqCal.Data, + ZQCS_period, + tZQCS + ); + + return; +} + +/** +@brief + This function returns the tZQCS value. + + @param[in] MrcData - Include all MRC global data. + @param[in] Frequency - The memory frequency. + + @retval The tZQCS value. +**/ +U32 +tZQCSGet ( + IN MrcParameters *const MrcData, + IN const MrcFrequency Frequency + ) +{ + U32 tZQCS; +#ifdef ULT_FLAG + MrcDdrType DdrType; + + DdrType = MrcData->SysOut.Outputs.DdrType; + if (DdrType == MRC_DDR_TYPE_LPDDR3) { + tZQCS = tZQCS_MIN / (MrcData->SysOut.Outputs.Qclkps * 2); + } else +#endif // ULT_FLAG + { + if (Frequency <= f1600) { + // + // All frequencies below 1600 uses the same value + // + tZQCS = tZQCS_1600; + } else if (Frequency <= f1867) { + tZQCS = tZQCS_1867; + } else if (Frequency <= f2133) { + tZQCS = tZQCS_2133; + } else if (Frequency <= f2400) { + tZQCS = tZQCS_2400; + } else { + tZQCS = tZQCS_2667; + } + } + return tZQCS; +} + +/** +@brief + This function configures the TC_MR2_SHADDOW register and its fields. + + @param[in] MrcData - Include all MRC global data. + @param[in] Channel - Channel to work on. + @param[in] Dimm - Dimm to work on. + @param[in] Mr2Value - The value of MR2 to setup. + + @retval Nothing. +**/ +void +SetTcMr2ShadowReg ( + IN MrcParameters *const MrcData, + IN const U32 Channel, + IN const U32 Dimm, + IN U32 Mr2Value + ) +{ + MrcDimmOut *DimmOut; + MCHBAR_CH0_CR_TC_MR2_SHADDOW_STRUCT TcMr2Shaddow; + U32 Offset; + + Offset = MCHBAR_CH0_CR_TC_MR2_SHADDOW_REG + + ((MCHBAR_CH1_CR_TC_MR2_SHADDOW_REG - MCHBAR_CH0_CR_TC_MR2_SHADDOW_REG) * Channel); + TcMr2Shaddow.Data = MrcReadCR (MrcData, Offset); + TcMr2Shaddow.Bits.MR2_sh_high = 0; + TcMr2Shaddow.Bits.MR2_sh_low = 0; + + DimmOut = &MrcData->SysOut.Outputs.Controller[0].Channel[Channel].Dimm[Dimm]; + if ((DimmOut->SelfRefreshTemp) == TRUE) { + TcMr2Shaddow.Bits.SRT_avail |= MRC_BIT0 << Dimm; + } + ((MCHBAR_CH0_CR_TC_MR2_SHADDOW_STRUCT *) (&Mr2Value))->Bits.SRT_avail = 0; + TcMr2Shaddow.Data |= Mr2Value; + + // + // Set address bit swizzle according to the DIMM number. + // + if (DimmOut->AddressMirrored == TRUE) { + TcMr2Shaddow.Bits.Addr_bit_swizzle |= MRC_BIT0 << Dimm; + } + + MrcWriteCR (MrcData, Offset, TcMr2Shaddow.Data); + // + // MRC_DEBUG_MSG (&MrcData->Inputs.Debug, MSG_LEVEL_NOTE, "TC-MR2_SHADOW Channel %u register value = %Xh\n", Channel, TcMr2Shaddow.Data); + // + return; +} + +/** +@brief + This function executes the refresh configuration process. + + @param[in] MrcData - Include all MRC global data. + + @retval Nothing. +**/ +void +MrcRefreshConfiguration ( + IN MrcParameters *const MrcData + ) +{ + MCMNTS_CR_TC_RFP_STRUCT TcRFP; + U32 Offset; + U8 Channel; + + for (Channel = 0; Channel < MAX_CHANNEL; Channel++) { + if (MrcChannelExist (&MrcData->SysOut.Outputs, Channel)) { + SetTcRftpReg (MrcData, Channel); + SetTcSrftpReg (MrcData, Channel); + SetTcZqCalReg (MrcData, Channel); + + // + // set LP0 WM and OREF_RI to support high memory BW traffic + // + Offset = MCHBAR_CH0_CR_TC_RFP_REG + + ((MCHBAR_CH1_CR_TC_RFP_REG - MCHBAR_CH0_CR_TC_RFP_REG) * Channel); + TcRFP.Data = MrcReadCR (MrcData, Offset); + TcRFP.Bits.OREF_RI = 0xFF; + MrcWriteCR (MrcData, Offset, TcRFP.Data); + TcRFP.Data = MrcReadCR (MrcData, Offset); + MRC_DEBUG_MSG ( + &MrcData->SysIn.Inputs.Debug, + MSG_LEVEL_NOTE, + "Ch%u: TC_RFP = %Xh\n OREF_RI = %u\n", + Channel, + TcRFP.Data, + TcRFP.Bits.OREF_RI + ); + } + } + + return; +} diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcRefreshConfiguration.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcRefreshConfiguration.h new file mode 100644 index 0000000..9909dcd --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcRefreshConfiguration.h @@ -0,0 +1,173 @@ +/** @file + This module include MRC_RefreshConfiguration external data + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved. + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _MrcRefreshConfiguration_h_ +#define _MrcRefreshConfiguration_h_ + +#include "MrcTypes.h" +#include "MrcApi.h" +#include "McAddress.h" +#include "MrcCommon.h" +#include "MrcDdr3.h" +#include "MrcOem.h" +#include "MrcGlobal.h" + +/// +/// tDLLK values +/// +#define tDLLK_VALUE 512 + +/// +/// tXSOffset values +/// +#define Offset_10nsec_800 4 +#define Offset_10nsec_1067 6 +#define Offset_10nsec_1333 7 +#define Offset_10nsec_1600 8 +#define Offset_10nsec_1867 10 +#define Offset_10nsec_2133 11 +#define Offset_10nsec_2400 12 +#define Offset_10nsec_2667 14 + +/// +/// tMOD values. max(12nCK,15ns) +/// +#define tMOD_800 12 +#define tMOD_1067 12 +#define tMOD_1333 12 +#define tMOD_1600 12 +#define tMOD_1867 14 +#define tMOD_2133 16 +#define tMOD_2400 18 +#define tMOD_2667 20 + +/// +/// tZQOPER values. +/// +#define tZQOPER_1600 256 +#define tZQOPER_1867 299 +#define tZQOPER_2133 342 +#define tZQOPER_2400 384 +#define tZQOPER_2667 427 + +// +// ZQCL and ZQCS values for LPDDR3, in [ps] +// +#define tZQCL_MIN 360000 +#define tZQCS_MIN 90000 + +/// +/// tZQCS values. +/// +#define tZQCS_1600 64 +#define tZQCS_1867 75 +#define tZQCS_2133 86 +#define tZQCS_2400 96 +#define tZQCS_2667 107 + +// +// ZQCS period values, in (tREFI * 128) units +// +#define ZQCS_PERIOD_DDR3 128 // tREFI * 128 = 7.8 us * 128 = 1ms +#define ZQCS_PERIOD_LPDDR3 256 // tREFI * 128 = 3.9 us * 128 = 0.5ms + +/** +@brief + This function returns the tZQOPER value. + tZQOPER = Defines the period required for ZQCL after SR exit. + + @param[in] MrcData - Include all MRC global data. + @param[in] Frequency - The memory frequency. + + @retval The tZQOPER value. +**/ +extern +U32 +tZQOPERGet ( + IN MrcParameters *const MrcData, + IN const MrcFrequency Frequency + ); + +/** +@brief + This function returns the tMOD value. + tMOD = max(12nCK, 15ns) nCK change by the frequency. + + @param[in] Frequency - The memory frequency. + + @retval The tMOD value. +**/ +extern +U32 +tMODGet ( + IN const MrcFrequency Frequency + ); + +/** +@brief + This function returns the tZQCS value. + + @param[in] MrcData - Include all MRC global data. + @param[in] Frequency - The memory frequency. + + @retval The tZQCS value. +**/ +extern +U32 +tZQCSGet ( + IN MrcParameters *const MrcData, + IN const MrcFrequency Frequency + ); + +/** +@brief + This function configures the TC_MR2_SHADDOW register and its fields. + + @param[in] MrcData - Include all MRC global data. + @param[in] Channel - Channel to work on. + @param[in] Dimm - Dimm to work on. + @param[in] Mr2Value - The value of MR2 to setup. + + @retval Nothing. +**/ +extern +void +SetTcMr2ShadowReg ( + IN MrcParameters *const MrcData, + IN const U32 Channel, + IN const U32 Dimm, + IN U32 Mr2Value + ); + +/** +@brief + This function executes the refresh configuration process. + + @param[in] MrcData - Include all MRC global data. + + @retval Nothing. +**/ +extern +void +MrcRefreshConfiguration ( + IN MrcParameters *const MrcData + ); + +#endif diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcSchedulerParameters.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcSchedulerParameters.c new file mode 100644 index 0000000..58d5e77 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcSchedulerParameters.c @@ -0,0 +1,109 @@ +/** @file + This module configures the memory controller scheduler. + +@copyright + Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved. + + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. +**/ + +// +// Include files +// +#include "MrcSchedulerParameters.h" + +/** +@brief + This function configures the memory controller scheduler. + + @param[in] MrcData - Include all MRC global data. + + @retval Nothing. +**/ +void +MrcSchedulerParametersConfig ( + IN MrcParameters *const MrcData + ) +{ + const MrcInput *Inputs; + MrcOutput *Outputs; + MCSCHEDS_CR_SCHED_CBIT_STRUCT SchedCbit; + MCSCHEDS_CR_SCHED_SECOND_CBIT_STRUCT SchedSecondCbit; + U8 Channel; + U32 Offset; +#ifdef ULT_FLAG + MCHBAR_CH0_CR_CMD_RATE_STRUCT CmdRate; +#endif // ULT_FLAG + + Inputs = &MrcData->SysIn.Inputs; + Outputs = &MrcData->SysOut.Outputs; + Channel = 0; + Offset = 0; + if ((Inputs->CpuModel == cmHSW) && (Inputs->CpuStepping == csHswA0)) { + SchedCbit.Data = SCHED_CBIT_DEFAULT; + } else { + SchedCbit.Data = SCHED_CBIT_DEFAULT_B0; + } +#ifdef ULT_FLAG + if (Inputs->CpuModel == cmHSW_ULT) { + SchedCbit.Bits.dis_odt = 1; + if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) { + // + // LPDDR3 DDP and QDP (multi-die) packages share the same ZQ pin, + // so we need to serialize the ZQ calibration for different ranks. + // + SchedCbit.Bits.Serialize_ZQ = 1; + + if (Inputs->LpddrDramOdt) { + // + // DRAM ODT is used + // + SchedCbit.Bits.dis_odt = 0; + } + } + } +#endif + + MrcWriteCrMulticast (MrcData, MCSCHEDS_CR_SCHED_CBIT_REG, SchedCbit.Data); + + MrcWriteCrMulticast (MrcData, MCMNTS_CR_SC_WDBWM_REG, SC_WDBWM_DEFAULT); + + if (Outputs->AsyncOdtDis) { + SchedSecondCbit.Data = 0; + SchedSecondCbit.Bits.dis_async_odt = 1; + MrcWriteCR8 (MrcData, MCSCHEDS_CR_SCHED_SECOND_CBIT_REG + 1, SchedSecondCbit.Data8[1]); + } + +#ifdef ULT_FLAG + // + // For LPDDR3, set Command Rate Limit to 3 + // + if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) { + for (Channel = 0; Channel < MAX_CHANNEL; Channel++) { + if (MrcChannelExist (Outputs, Channel)) { + Offset = MCHBAR_CH0_CR_CMD_RATE_REG + ((MCHBAR_CH1_CR_CMD_RATE_REG - MCHBAR_CH0_CR_CMD_RATE_REG) * Channel); + CmdRate.Data = MrcReadCR (MrcData, Offset); + CmdRate.Bits.enable_cmd_rate_limit = 1; + CmdRate.Bits.cmd_rate_limit = 3; + MrcWriteCR (MrcData, Offset, CmdRate.Data); + } + } + } +#endif + + + return; +} diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcSchedulerParameters.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcSchedulerParameters.h new file mode 100644 index 0000000..75dca03 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcSchedulerParameters.h @@ -0,0 +1,49 @@ +/** @file + This module includes the memory controller scheduler parameters. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved. + + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. +**/ +#ifndef _MrcSchedulerParameters_h_ +#define _MrcSchedulerParameters_h_ + +#include "McAddress.h" +#include "MrcTypes.h" +#include "MrcApi.h" +#include "MrcCommon.h" +#include "MrcGlobal.h" + +#define SCHED_CBIT_DEFAULT (0x00100030) +#define SCHED_CBIT_DEFAULT_B0 (0x00100000) + +#define SC_WDBWM_DEFAULT (0x553C3038) + +/** +@brief + This function configures the memory controller scheduler. + + @param[in] MrcData - Include all MRC global data. + + @retval Nothing. +**/ +void +MrcSchedulerParametersConfig ( + IN MrcParameters *const MrcData + ); + +#endif // _MrcSchedulerParameters_h_ diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcTimingConfiguration.c b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcTimingConfiguration.c new file mode 100644 index 0000000..8f98dd2 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcTimingConfiguration.c @@ -0,0 +1,921 @@ +/** @file + This module configures the memory controller timing parameters. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. + +**/ +#include "MrcTimingConfiguration.h" + +/** +@brief + This function returns the tCKE value for the specified frequency. + + @param[in] DdrType - DDR type + @param[in] Frequency - The memory frequency. + + @retval The tCKE value for the specified frequency. +**/ +static +U32 +tCKEValue ( + IN MrcDdrType DdrType, + IN const MrcFrequency Frequency + ) +{ + U32 tCKE; + +#if (SUPPORT_LPDDR3 == SUPPORT) + if (DdrType == MRC_DDR_TYPE_LPDDR3) { + if (Frequency <= f1067) { + tCKE = tCKE_LPDDR_1067; + } else if (Frequency <= f1333) { + tCKE = tCKE_LPDDR_1333; + } else { + tCKE = tCKE_LPDDR_1600; + } + return tCKE; + } +#endif // SUPPORT_LPDDR3 + + if (Frequency <= f800) { + tCKE = TCKE_800; + } else if (Frequency <= f1067) { + tCKE = TCKE_1067; + } else if (Frequency <= f1333) { + tCKE = TCKE_1333; + } else if (Frequency <= f1600) { + tCKE = TCKE_1600; + } else if (Frequency <= f1867) { + tCKE = TCKE_1867; + } else if (Frequency <= f2133) { + tCKE = TCKE_2133; + } else if (Frequency <= f2400) { + tCKE = TCKE_2400; + } else { + tCKE = TCKE_2667; + } + + return tCKE; +} + +/** +@brief + This function returns the tXPDLL value for the specified frequency. + + @param[in] Frequency - The memory frequency. + + @retval The tXPDLL value for the specified frequency. +**/ +static +U32 +tXPDLLValue ( + IN const MrcFrequency Frequency + ) +{ + U32 tXPDLL; + + if (Frequency <= f800) { + tXPDLL = TXPDLL_800; + } else if (Frequency <= f1067) { + tXPDLL = TXPDLL_1067; + } else if (Frequency <= f1333) { + tXPDLL = TXPDLL_1333; + } else if (Frequency <= f1600) { + tXPDLL = TXPDLL_1600; + } else if (Frequency <= f1867) { + tXPDLL = TXPDLL_1867; + } else if (Frequency <= f2133) { + tXPDLL = TXPDLL_2133; + } else if (Frequency <= f2400) { + tXPDLL = TXPDLL_2400; + } else { + tXPDLL = TXPDLL_2667; + } + + return tXPDLL; +} + +/** +@brief + This function returns the tXP value for the specified frequency. + + @param[in] DdrType - DDR type + @param[in] Frequency - The memory frequency. + @param[in] NMode - Command mode to lookup. + + @retval The tXP value for the specified frequency. +**/ +U32 +tXPValue ( + IN MrcDdrType DdrType, + IN const MrcFrequency Frequency, + IN U8 NMode + ) +{ + U32 tXP; + +#if (SUPPORT_LPDDR3 == SUPPORT) + if (DdrType == MRC_DDR_TYPE_LPDDR3) { + if (Frequency <= f1333) { + tXP = tXP_LPDDR_1333; + } else { + tXP = tXP_LPDDR_1600; + } + } else +#endif // SUPPORT_LPDDR3 + { + if (Frequency <= f1600) { + tXP = ((MC_tXP_1600_1N - 1) + NMode); + } else if (Frequency <= f1867) { + tXP = ((NMode <= 2) ? MC_tXP_1867_2N : MC_tXP_1867_3N); + } else if (Frequency <= f2133) { + tXP = (MC_tXP_2133_1N); + } else { + tXP = MC_tXP_MAX; + } + } + return (tXP); +} + +/** +@brief + This function returns the tAONPD value for the specified frequency. + + @param[in] Frequency - The memory frequency. + + @retval The tAONPD value for the specified frequency. +**/ +static +U32 +tAONPDValue ( + IN const MrcFrequency Frequency + ) +{ + U32 tAONPD; + + if (Frequency <= f800) { + tAONPD = TAONPD_800; + } else if (Frequency <= f1067) { + tAONPD = TAONPD_1067; + } else if (Frequency <= f1333) { + tAONPD = TAONPD_1333; + } else if (Frequency <= f1600) { + tAONPD = TAONPD_1600; + } else if (Frequency <= f1867) { + tAONPD = TAONPD_1867; + } else if (Frequency <= f2133) { + tAONPD = TAONPD_2133; + } else if (Frequency <= f2400) { + tAONPD = TAONPD_2400; + } else { + tAONPD = TAONPD_2667; + } + + return tAONPD; +} + +/** +@brief + This function sets up the TC-BANK register, + which includes the tRCD, tRP, tRAS, tRDPRE, tRTP, tWRPRE, and tRRD values. + + @param[in, out] MrcData - Include all MRC global data. + @param[in] Channel - Channel select. + + @retval Nothing. +**/ +static +void +SetTcBankReg ( + IN OUT MrcParameters *const MrcData, + IN const U32 Channel + ) +{ + const MrcInput *Inputs; + const MrcDebug *Debug; + MrcOutput *Outputs; + MrcChannelOut *ChannelOut; + MrcTiming *Timing; + MCHBAR_CH0_CR_TC_BANK_STRUCT CrTcBank; + U32 tWRPRE; + + Inputs = &MrcData->SysIn.Inputs; + Debug = &Inputs->Debug; + Outputs = &MrcData->SysOut.Outputs; + ChannelOut = &Outputs->Controller[0].Channel[Channel]; + Timing = &ChannelOut->Timing[Inputs->MemoryProfile]; + + // + // tWRPRE is = 4tCK + tWR + tWL = 4DCLK + tWR + tWL + // + tWRPRE = 4 + Timing->tCWL + Timing->tWR; + + CrTcBank.Data = 0; + CrTcBank.Bits.tRCD = MIN (MCHBAR_CH0_CR_TC_BANK_tRCD_MAX, Timing->tRCD); + CrTcBank.Bits.tRP = MIN (MCHBAR_CH0_CR_TC_BANK_tRP_MAX, Timing->tRP); + CrTcBank.Bits.tRAS = MIN (MCHBAR_CH0_CR_TC_BANK_tRAS_MAX, Timing->tRAS); + CrTcBank.Bits.tRDPRE = MIN (MCHBAR_CH0_CR_TC_BANK_tRDPRE_MAX, Timing->tRTP); + CrTcBank.Bits.tWRPRE = MIN (MCHBAR_CH0_CR_TC_BANK_tWRPRE_MAX, tWRPRE); + CrTcBank.Bits.tRRD = MIN (MCHBAR_CH0_CR_TC_BANK_tRRD_MAX, Timing->tRRD); +#ifdef ULT_FLAG + if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) { + CrTcBank.Bits.tRPab_ext = MIN (MCHBAR_CH0_CR_TC_BANK_tRPab_ext_MAX, Timing->tRPab - Timing->tRP); + } +#endif + MrcWriteCR ( + MrcData, + MCHBAR_CH0_CR_TC_BANK_REG + ((MCHBAR_CH1_CR_TC_BANK_REG - MCHBAR_CH0_CR_TC_BANK_REG) * Channel), + CrTcBank.Data + ); + + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %u:\n tRCD = %u\n", Channel, CrTcBank.Bits.tRCD); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRP = %u\n", CrTcBank.Bits.tRP); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRAS = %u\n", CrTcBank.Bits.tRAS); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRDPRE = %u\n", CrTcBank.Bits.tRDPRE); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tWRPRE = %u\n", CrTcBank.Bits.tWRPRE); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRRD = %u\n", CrTcBank.Bits.tRRD); +#ifdef ULT_FLAG + if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) { + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRPab_ext = %u\n", CrTcBank.Bits.tRPab_ext); + } +#endif + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " TC_BANK = %Xh\n", CrTcBank.Data); + + // + // Save in MrcData structure + // + ChannelOut->MchbarBANK = CrTcBank.Data; + + return; +} + +/** +@brief + This function sets up the TC_BANK_RANK_D register, + which includes the tCL and tWCL values. + + @param[in, out] MrcData - Include all MRC global data. + @param[in] Channel - Channel select. + + @retval Nothing. +**/ +static +void +SetTcBankRankDReg ( + IN OUT MrcParameters *const MrcData, + IN const U32 Channel + ) +{ + const MrcInput *Inputs; + const MrcDebug *Debug; + MrcOutput *Outputs; + MrcChannelOut *ChannelOut; + MrcTiming *Timing; + MCHBAR_CH0_CR_TC_BANK_RANK_D_STRUCT TcBankRankD; + U32 OdtReadDelay; +#ifdef ULT_FLAG + U32 OdtWriteDelay; + U32 OdtWriteDuration; + U32 DclkPs; +#endif // ULT_FLAG + + Inputs = &MrcData->SysIn.Inputs; + Outputs = &MrcData->SysOut.Outputs; + Debug = &Inputs->Debug; + ChannelOut = &MrcData->SysOut.Outputs.Controller[0].Channel[Channel]; + Timing = &ChannelOut->Timing[Inputs->MemoryProfile]; + + // + // @todo: Need to make sure this value, after power on, follows the restrictions in the XML description. + // + OdtReadDelay = Timing->tCL - Timing->tCWL; + + TcBankRankD.Data = 0; + TcBankRankD.Bits.tWCL = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_D_tWCL_MAX, Timing->tCWL); + TcBankRankD.Bits.tCL = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_D_tCL_MAX, Timing->tCL); + TcBankRankD.Bits.tCPDED = MCHBAR_CH0_CR_TC_BANK_RANK_D_tCPDED_DEF; + TcBankRankD.Bits.tPRPDEN = MCHBAR_CH0_CR_TC_BANK_RANK_D_tPRPDEN_DEF; + TcBankRankD.Bits.Odt_Read_Delay = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Read_Delay_MAX, OdtReadDelay); + +#ifdef ULT_FLAG + if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) { + if (Inputs->LpddrDramOdt) { + // + // Only ODT[0] is used in ULT, need to use it for both ranks + // + TcBankRankD.UltBits.Odt_Always_Rank0 = 1; + } + + // + // Timing->tCWL has 1 extra clock because of tDQSS - subtract it here. + // + TcBankRankD.Bits.tWCL--; + + // + // JEDEC Spec requires tCPDED should be 2 clocks for all LPDDR3 frequencies + // + TcBankRankD.Bits.tCPDED = 2; + + DclkPs = Outputs->Qclkps * 2; + + // + // Odt_Write_Delay = WL - 1 - RU(tODTon(max)) + // + OdtWriteDelay = Timing->tCWL - 1 - (tODT_ON_MAX + DclkPs - 1) / DclkPs; + + // + // Odt_Write_Duration = 6 + RU(tODTon(max)-tODToff(min)) - 6 + 1 + // + OdtWriteDuration = 1 + (tODT_ON_MAX - tODT_OFF_MIN + DclkPs - 1) / DclkPs; + + TcBankRankD.UltBits.Odt_Write_Delay = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Delay_Ult_MAX, OdtWriteDelay); + TcBankRankD.UltBits.Odt_Write_Duration = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_D_Odt_Write_Duration_Ult_MAX, OdtWriteDuration); + } +#endif // ULT_FLAG + + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %u:\n tCL = %u\n", Channel, TcBankRankD.Bits.tCL); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tWCL = %u\n", TcBankRankD.Bits.tWCL); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tCPDED = %u\n", TcBankRankD.Bits.tCPDED); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tPRPDEN = %u\n", TcBankRankD.Bits.tPRPDEN); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Odt_Read_Delay = %u\n", TcBankRankD.Bits.Odt_Read_Delay); +#ifdef ULT_FLAG + if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) { + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Odt_Write_Delay = %u\n", TcBankRankD.UltBits.Odt_Write_Delay); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Odt_Write_Duration = %u\n", TcBankRankD.UltBits.Odt_Write_Duration); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Odt_Always_Rank0 = %u\n", TcBankRankD.UltBits.Odt_Always_Rank0); + } +#endif // ULT_FLAG + + MrcWriteCR ( + MrcData, + MCHBAR_CH0_CR_TC_BANK_RANK_D_REG + ((MCHBAR_CH1_CR_TC_BANK_RANK_D_REG - MCHBAR_CH0_CR_TC_BANK_RANK_D_REG) * Channel), + TcBankRankD.Data + ); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " TC_BANK_RANK_D = %Xh\n", TcBankRankD.Data); + + // + // Save in MrcData structure + // + ChannelOut->MchbarBANKRANKD = TcBankRankD.Data; + + return; +} + +/** +@brief + This function sets up the TC_BANK_RANK_A register. + which includes the tCKE, tFAW, tRDRD, tRDRD_dr, tRDRD_dd, tRDPDEN, and command rate mode. + + @param[in, out] MrcData - Include all MRC global data. + @param[in] Channel - Channel select. + + @retval Nothing. +**/ +static +void +SetTcBankRankAReg ( + IN OUT MrcParameters *const MrcData, + IN const U32 Channel + ) +{ + const MrcInput *Inputs; + const MrcDebug *Debug; + MrcOutput *Outputs; + MrcTiming *Timing; + MrcDdrType DdrType; + MCHBAR_CH0_CR_TC_BANK_RANK_A_STRUCT TcBankRankA; + U32 CRValue; + + Inputs = &MrcData->SysIn.Inputs; + Debug = &Inputs->Debug; + Outputs = &MrcData->SysOut.Outputs; + Timing = &Outputs->Controller[0].Channel[Channel].Timing[Inputs->MemoryProfile]; + DdrType = Outputs->DdrType; + TcBankRankA.Data = 0; + + // + // Get the tCKE value. + // + CRValue = tCKEValue (DdrType, Outputs->Frequency); + TcBankRankA.Bits.tCKE = MIN (MCHBAR_CH1_CR_TC_BANK_RANK_A_tCKE_MAX, CRValue); + + // + // Get the command rate mode value. + // Use 3N mode during training steps + // +#ifdef ULT_FLAG + if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) { + // + // Need to use 1N mode for LPDDR + // + TcBankRankA.Bits.CMD_stretch = 0; + } else +#endif // ULT_FLAG + { + TcBankRankA.Bits.CMD_stretch = MIN (MCHBAR_CH1_CR_TC_BANK_RANK_A_CMD_stretch_MAX, 3); + } + // + // Program tFAW value + // + TcBankRankA.Bits.tFAW = MIN (MCHBAR_CH1_CR_TC_BANK_RANK_A_tFAW_MAX, Timing->tFAW); + + // + // Calculate tRDRD + // + TcBankRankA.Bits.tRDRD = MIN (MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_MAX, TCCD_ALL_FREQ); + + // + // Calculate tRDRD_dr = BL/2 + max(tRTR, ODT(R,R,DR)) + tRPRE + // + CRValue = 4 + 1 + TRPRE_ALL_FREQ; + +#ifdef ULT_FLAG + if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) { + // + // Increase tRDRD_dr from 6 to 7 DCLKs on LPDDR3 + // + CRValue++; + } +#endif // ULT_FLAG + + TcBankRankA.Bits.tRDRD_dr = MIN (MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dr_MAX, CRValue); + + // + // Calculate tRDRD_dd = BL/2 + max(tRTR, ODT(R,R,DD)) + tRPRE + // + TcBankRankA.Bits.tRDRD_dd = MIN (MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDRD_dd_MAX, CRValue); + + // + // Calculate tRDPDEN = tCL + BL/2 +1 + // + CRValue = Timing->tCL + 5; + TcBankRankA.Bits.tRDPDEN = MIN (MCHBAR_CH1_CR_TC_BANK_RANK_A_tRDPDEN_MAX, CRValue); + + // + // Disable command tri state before training. + // + TcBankRankA.Bits.CMD_3st = 1; + + MrcWriteCR ( + MrcData, + MCHBAR_CH0_CR_TC_BANK_RANK_A_REG + ((MCHBAR_CH1_CR_TC_BANK_RANK_A_REG - MCHBAR_CH0_CR_TC_BANK_RANK_A_REG) * Channel), + TcBankRankA.Data + ); + + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %u:\n tCKE = %u\n", Channel, TcBankRankA.Bits.tCKE); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " NMode = %u\n", TcBankRankA.Bits.CMD_stretch); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tFAW = %u\n", TcBankRankA.Bits.tFAW); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRDRD = %u\n", TcBankRankA.Bits.tRDRD); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRDRD_dr = %u\n", TcBankRankA.Bits.tRDRD_dr); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRDRD_dd = %u\n", TcBankRankA.Bits.tRDRD_dd); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRDPDEN = %u\n", TcBankRankA.Bits.tRDPDEN); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " CMD_3st = %u\n", TcBankRankA.Bits.CMD_3st); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " TC_BANK_RANK_A = %Xh\n", TcBankRankA.Data); + + // + // Save in MrcData structure + // + Outputs->Controller[0].Channel[Channel].MchbarBANKRANKA = TcBankRankA.Data; + + return; +} + +/** +@brief + This function sets up the TC_BANK_RANK_B register, which includes + Dec_WRD, tWRPDEN, tWRWR_dd, tWRWR_dr, tWRWR, tWRRD_dd, tWRRD_dr and tWRRD. + + @param[in, out] MrcData - Include all MRC global data. + @param[in] Channel - Channel select. + + @retval Nothing. +**/ +static +void +SetTcBankRankBReg ( + IN OUT MrcParameters *const MrcData, + IN const U32 Channel + ) +{ + const MrcInput *Inputs; + const MrcDebug *Debug; + MrcOutput *Outputs; + MrcTiming *Timing; + MCHBAR_CH0_CR_TC_BANK_RANK_B_STRUCT TcBankRankB; + MCHBAR_CH0_CR_TC_BANK_RANK_D_STRUCT TcBankRankD; + MCHBAR_CH0_CR_SC_WR_ADD_DELAY_STRUCT ScWrAddDelay; + U32 CRValue; + U32 tWRRD_dr; + U32 tWRWR_dr; + U32 Offset; + + Inputs = &MrcData->SysIn.Inputs; + Debug = &Inputs->Debug; + Outputs = &MrcData->SysOut.Outputs; + Timing = &Outputs->Controller[0].Channel[Channel].Timing[Inputs->MemoryProfile]; + TcBankRankB.Data = 0; + + // + // Calculate tWRRD = tCCD + tCWL + tWTR + max(tWrCAS2RdCAS_sr,ODT(W,R,SR)). + // + CRValue = TCCD_ALL_FREQ + Timing->tCWL + Timing->tWTR + 2; + TcBankRankB.Bits.tWRRD = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_MAX, CRValue); + + // + // Calculate tWRRD_dr = tCWL-tCL + BL/2 + max(tWRDRDD,ODT(W,R,DR)) + tRPRE + // + tWRRD_dr = Timing->tCWL - Timing->tCL + 4 + 2 + TRPRE_ALL_FREQ; + +#ifdef ULT_FLAG + if (Outputs->DdrType == MRC_DDR_TYPE_LPDDR3) { + // + // tWRRD_dr is 8 for all LPDDR bins + // + tWRRD_dr = 8; + } +#endif // ULT_FLAG + + TcBankRankB.Bits.tWRRD_dr = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dr_MAX, tWRRD_dr); + + // + // Calculate tWRRD_dd = tCWL-tCL + BL/2 + max(tWRDRDD,ODT(W,R,DR)) + tRPRE + // + TcBankRankB.Bits.tWRRD_dd = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRRD_dd_MAX, tWRRD_dr); + + // + // Calculate tWRWR + // + TcBankRankB.Bits.tWRWR = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_MAX, TCCD_ALL_FREQ); + + // + // Calculate tWRWR_dr = BL/2 + max(tWWDR,ODT(W,W,DR)) + tWPRE + // + tWRWR_dr = 4 + 2 + TWPRE_ALL_FREQ; + TcBankRankB.Bits.tWRWR_dr = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dr_MAX, tWRWR_dr); + + // + // Calculate tWRWR_dd = BL/2 + max(tWWDD,ODT(W,W,DR)) + tWPRE + // + TcBankRankB.Bits.tWRWR_dd = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRWR_dd_MAX, tWRWR_dr); + + // + // Calculate tWRPDEN = tWR+tWL+BL/2 + // + CRValue = Timing->tWR + Timing->tCWL + 4; + TcBankRankB.Bits.tWRPDEN = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_B_tWRPDEN_MAX, CRValue); + + // + // Set Dec_WRD. + // Can be set to 1 only if tWCL is 6 or more. + // + Offset = MCHBAR_CH0_CR_TC_BANK_RANK_D_REG + + (MCHBAR_CH1_CR_TC_BANK_RANK_D_REG - MCHBAR_CH0_CR_TC_BANK_RANK_D_REG) * Channel; + TcBankRankD.Data = MrcReadCR (MrcData, Offset); + if (TcBankRankD.Bits.tWCL >= 6) { + TcBankRankB.Bits.Dec_WRD = 1; + } else { + TcBankRankB.Bits.Dec_WRD = 0; + } + + MrcWriteCR ( + MrcData, + MCHBAR_CH0_CR_TC_BANK_RANK_B_REG + ((MCHBAR_CH1_CR_TC_BANK_RANK_B_REG - MCHBAR_CH0_CR_TC_BANK_RANK_B_REG) * Channel), + TcBankRankB.Data + ); + + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %u:\n tWRRD = %u\n", Channel, TcBankRankB.Bits.tWRRD); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tWRRD_dr = %u\n", TcBankRankB.Bits.tWRRD_dr); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tWRRD_dd = %u\n", TcBankRankB.Bits.tWRRD_dd); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tWRWR = %u\n", TcBankRankB.Bits.tWRWR); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tWRWR_dr = %u\n", TcBankRankB.Bits.tWRWR_dr); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tWRWR_dd = %u\n", TcBankRankB.Bits.tWRWR_dd); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tWRPDEN = %u\n", TcBankRankB.Bits.tWRPDEN); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " Dec_WRD = %u\n", TcBankRankB.Bits.Dec_WRD); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " TC_BANK_RANK_B = %Xh\n", TcBankRankB.Data); + + // + // Save in MrcData structure + // + Outputs->Controller[0].Channel[Channel].MchbarBANKRANKB = TcBankRankB.Data; + + // + // Set sc_wr_add_delay accordingly = 1 + Dec_WRD + // + CRValue = TcBankRankB.Bits.Dec_WRD + 1; + ScWrAddDelay.Data = 0; + ScWrAddDelay.Bits.D1R1 = MIN (MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R1_MAX, CRValue); + ScWrAddDelay.Bits.D1R0 = MIN (MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D1R0_MAX, CRValue); + ScWrAddDelay.Bits.D0R1 = MIN (MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R1_MAX, CRValue); + ScWrAddDelay.Bits.D0R0 = MIN (MCHBAR_CH0_CR_SC_WR_ADD_DELAY_D0R0_MAX, CRValue); + MrcWriteCR8 ( + MrcData, + MCHBAR_CH0_CR_SC_WR_ADD_DELAY_REG + + ((MCHBAR_CH1_CR_SC_WR_ADD_DELAY_REG - MCHBAR_CH0_CR_SC_WR_ADD_DELAY_REG) * Channel), + (U8) ScWrAddDelay.Data + ); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " SC_WR_ADD_Delay = %Xh\n", ScWrAddDelay.Data); + + return; +} + +/** +@brief + This function sets up the TC_BANK_RANK_C register, which includes + TAONPD, tXP, tXPDLL, tRDWR, tRDWR_dr, and tRDWR_dd. + + @param[in, out] MrcData - Include all MRC global data. + @param[in] Channel - Channel select. + + @retval Nothing. +**/ +static +void +SetTcBankRankCReg ( + IN OUT MrcParameters *const MrcData, + IN const U32 Channel + ) +{ + const MrcInput *Inputs; + const MrcDebug *Debug; + MrcOutput *Outputs; + MrcTiming *Timing; + MrcDdrType DdrType; + MCHBAR_CH0_CR_TC_BANK_RANK_C_STRUCT TcBankRankC; + U32 Value; + U32 DclkPs; + + Inputs = &MrcData->SysIn.Inputs; + Debug = &Inputs->Debug; + Outputs = &MrcData->SysOut.Outputs; + Timing = &Outputs->Controller[0].Channel[Channel].Timing[Inputs->MemoryProfile]; + DdrType = Outputs->DdrType; + TcBankRankC.Data = 0; + + Value = tXPDLLValue (Outputs->Frequency); + TcBankRankC.Bits.tXPDLL = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_C_tXPDLL_MAX, Value); + + Value = tXPValue (DdrType, Outputs->Frequency, 3); + TcBankRankC.Bits.tXP = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_C_tXP_MAX, Value); + + Value = tAONPDValue (Outputs->Frequency); + TcBankRankC.Bits.TAONPD = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_C_TAONPD_MAX, Value); + + // + // Calculate tRDWR = tCL-tCWL+tCCD+tWPRE+max(tRWSR,ODT(R,W,SR)) + // tWPRE - Write Preamble + // + Value = Timing->tCL - Timing->tCWL + TCCD_ALL_FREQ + TWPRE_ALL_FREQ + 2; + // + // Add 1 for frequencies above 1333. + // + if (Outputs->Frequency > f1333) { + Value++; + } + + DclkPs = Outputs->Qclkps * 2; + +#ifdef ULT_FLAG + if (DdrType == MRC_DDR_TYPE_LPDDR3) { + // + // tRDWR = tCL - tCWL + tDQSCK_max + tCCD + tWPRE + ElectricalTurnaround + // + Value = Timing->tCL - Timing->tCWL + (tDQSCK_MAX + DclkPs - 1) / DclkPs + + TCCD_ALL_FREQ + TWPRE_ALL_FREQ + 1; + } +#endif // ULT_FLAG + + TcBankRankC.Bits.tRDWR = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_MAX, Value); + + // + // Calculate tRDWR_dr = tCL-tCWL+tCCD+tWPRE+max(tRWSR,ODT(R,W,SR)) + // + TcBankRankC.Bits.tRDWR_dr = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dr_MAX, Value); + + // + // Calculate tRDWR_dd = tCL-tCWL+tCCD+tWPRE+max(tRWSR,ODT(R,W,SR)) + // + TcBankRankC.Bits.tRDWR_dd = MIN (MCHBAR_CH0_CR_TC_BANK_RANK_C_tRDWR_dd_MAX, Value); + + MrcWriteCR ( + MrcData, + MCHBAR_CH0_CR_TC_BANK_RANK_C_REG + ((MCHBAR_CH1_CR_TC_BANK_RANK_C_REG - MCHBAR_CH0_CR_TC_BANK_RANK_C_REG) * Channel), + TcBankRankC.Data + ); + + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Channel %u:\n tXPDLL = %u\n", Channel, TcBankRankC.Bits.tXPDLL); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tXP = %u\n", TcBankRankC.Bits.tXP); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tAONPD = %u\n", TcBankRankC.Bits.TAONPD); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRDWR = %u\n", TcBankRankC.Bits.tRDWR); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRDWR_dr = %u\n", TcBankRankC.Bits.tRDWR_dr); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " tRDWR_dd = %u\n", TcBankRankC.Bits.tRDWR_dd); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, " TC_BANK_RANK_C = %Xh\n", TcBankRankC.Data); + + // + // Save in MrcData structure + // + Outputs->Controller[0].Channel[Channel].MchbarBANKRANKC = TcBankRankC.Data; + + return; +} + +/** +@brief + This function configures the memory controller timings. + + @param[in] MrcData - Include all MRC global data. + + @retval Nothing. +**/ +void +MrcTimingConfiguration ( + IN MrcParameters *const MrcData + ) +{ + U8 Channel; + + for (Channel = 0; Channel < MAX_CHANNEL; Channel++) { + if (MrcChannelExist (&MrcData->SysOut.Outputs, Channel)) { + // + // setup TC-BANK register + // + SetTcBankReg (MrcData, Channel); + + // + // setup TC-BANK_RANK_D register + // + SetTcBankRankDReg (MrcData, Channel); + + // + // setup TC-BANK_RANK_A register + // + SetTcBankRankAReg (MrcData, Channel); + + // + // setup TC-BANK_RANK_B register + // + SetTcBankRankBReg (MrcData, Channel); + + // + // setup TC-BANK_RANK_C register + // + SetTcBankRankCReg (MrcData, Channel); + } + } + + // + // Check RawCard Types and adjust Read ODT if needed + // + RdOdtStretch (MrcData); + + return; +} + +/** +@brief + This function sets up the Read ODTD values based on RawCard types and adjusts the tDRRD2RD, tDDRD2RD, tDRRD2WR and tDDRD2WR + + @param[in, out] MrcData - Include all MRC global data. + + @retval Nothing. +**/ +void +RdOdtStretch ( + IN OUT MrcParameters *const MrcData + ) +{ + const MrcDebug *Debug; + const MrcInput *Inputs; + MrcControllerOut *ControllerOut; + MrcChannelOut *ChannelOut; + U8 Channel; + U8 ChBitMask; + U8 RankMaskCh; + S8 OdtStretch; +#if SUPPORT_SODIMM == SUPPORT + MrcDimmOut *DimmOut; + BOOL SoDimm; + U8 Value; + U8 Dimm; + U8 DimmRawCardType[MAX_DIMMS_IN_CHANNEL]; + MCHBAR_CH0_CR_TC_BANK_RANK_A_STRUCT TcBankRankA; + MCHBAR_CH0_CR_TC_BANK_RANK_C_STRUCT TcBankRankC; +#endif //SUPPORT_SODIMM == SUPPORT + + Inputs = &MrcData->SysIn.Inputs; + Debug = &Inputs->Debug; + ControllerOut = &MrcData->SysOut.Outputs.Controller[0]; + + ChBitMask = 0; + + for (Channel = 0; Channel < MAX_CHANNEL; Channel++) { + ChannelOut = &ControllerOut->Channel[Channel]; + if (ChannelOut->ValidRankBitMask && (ChannelOut->DimmCount == 2)) { + ChBitMask |= (MRC_BIT0 << Channel); + } + } + + for (Channel = 0; Channel < MAX_CHANNEL; Channel++) { + if (!((MRC_BIT0 << Channel) & ChBitMask)) { + // + // Skip any channels that do not have 2 DIMMs populated + // + continue; + } + + ChannelOut = &ControllerOut->Channel[Channel]; + RankMaskCh = ChannelOut->ValidRankBitMask; + // + // Start with the most aggressive setting + // + OdtStretch = 6; + +#if SUPPORT_SODIMM == SUPPORT + SoDimm = FALSE; + for (Dimm = 0; Dimm < MAX_DIMMS_IN_CHANNEL; Dimm++) { + DimmOut = &ChannelOut->Dimm[Dimm]; + if (((DimmOut->ModuleType == MRC_MODULE_TYPE_SODIMM) || (DimmOut->ModuleType == MRC_MODULE_72B_SO_UDIMM)) + && (SoDimm == FALSE)) { + SoDimm = TRUE; + } + if (SoDimm) { + DimmRawCardType[Dimm] = DimmOut->ReferenceRawCard; + } + } + + if (SoDimm) { + if ((DimmRawCardType[0] == rcF || DimmRawCardType[1] == rcF) + && (DimmRawCardType[0] != DimmRawCardType[1])) { + OdtStretch = 7; + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE,"Rd Odt Stretch F\n"); + } + } +#endif //SUPPORT_SODIMM == SUPPORT + // + // Program Rdodtd value + // + UpdateTAParamOffset (MrcData, Channel, 0, rdodtd, OdtStretch, 1, 1, RankMaskCh); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Selected RdOdtD Offset for channel %d is = %d\n", Channel, OdtStretch); + +#if SUPPORT_SODIMM == SUPPORT + if (OdtStretch > 6) { + TcBankRankA.Data = ChannelOut->MchbarBANKRANKA; + Value = (U8)(TcBankRankA.Bits.tRDRD_dr); + Value += OdtStretch - 6; + // + // Program Different Rank RD 2 RD value + // + UpdateTAParamOffset (MrcData, Channel, 0, drrd2rd, Value, 1, 1, RankMaskCh); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Selected DR RD2RD Offset for channel %d is = %d\n", Channel, Value); + + Value = (U8)(TcBankRankA.Bits.tRDRD_dd); + Value += OdtStretch - 6; + // + // Program Different DIMM RD 2 RD value + // + UpdateTAParamOffset (MrcData, Channel, 0, ddrd2rd, Value, 1, 1, RankMaskCh); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Selected DD RD2RD Offset for channel %d is = %d\n", Channel, Value); + + TcBankRankC.Data = ChannelOut->MchbarBANKRANKC; + Value = (U8)(TcBankRankC.Bits.tRDWR_dr); + Value += OdtStretch - 6; + // + // Program Different Rank RD 2 WR value + // + UpdateTAParamOffset (MrcData, Channel, 0, drrd2wr, Value, 1, 1, RankMaskCh); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Selected DR RD2WR Offset for channel %d is = %d\n", Channel, Value); + + Value = (U8)(TcBankRankC.Bits.tRDWR_dd); + Value += OdtStretch - 6; + // + // Program Different DIMM RD 2 WR value + // + UpdateTAParamOffset (MrcData, Channel, 0, ddrd2wr, Value, 1, 1, RankMaskCh); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Selected DD RD2WR Offset for channel %d is = %d\n", Channel, Value); + + Value = (U8)(TcBankRankC.Bits.tRDWR); + Value += OdtStretch - 6; + // + // Program Same Rank RD 2 WR value + // + UpdateTAParamOffset (MrcData, Channel, 0, srrd2wr, Value, 1, 1, RankMaskCh); + MRC_DEBUG_MSG (Debug, MSG_LEVEL_NOTE, "Selected SR RD2WR Offset for channel %d is = %d\n", Channel, Value); + } +#endif //SUPPORT_SODIMM == SUPPORT + } + +} diff --git a/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcTimingConfiguration.h b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcTimingConfiguration.h new file mode 100644 index 0000000..c9bb6c3 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/MemoryInit/Pei/Source/McConfiguration/MrcTimingConfiguration.h @@ -0,0 +1,167 @@ +/** @file + This module configures the memory controller timing parameters. + +@Copyright + Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved. + + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement. +**/ +#ifndef _MrcTimingConfiguration_h_ +#define _MrcTimingConfiguration_h_ + +#include "MrcTypes.h" +#include "MrcApi.h" +#include "McAddress.h" +#include "MrcCommon.h" +#include "MrcDdr3.h" +#include "MrcGlobal.h" +#include "MrcOem.h" +#if SUPPORT_SODIMM == SUPPORT +#include "MrcSpdProcessing.h" +#endif //SUPPORT_SODIMM == SUPPORT + +/// +/// tCCD values. +/// +#define TCCD_ALL_FREQ (4) ///< tCCD is = 4 DCLK for all frequencies up to 1600. +/// +/// tWPRE values. +/// +#define TWPRE_ALL_FREQ (1) ///< tWPRE is = 1 DCLK for all frequencies up to 1600. +/// +/// tRPRE values. +/// +#define TRPRE_ALL_FREQ (1) ///< tRPRE is = 1 DCLK for all frequencies up to 1600. +/// +/// tCKE values. +/// +#define TCKE_800 (3) +#define TCKE_1067 (3) +#define TCKE_1333 (4) +#define TCKE_1600 (4) +#define TCKE_1867 (5) +#define TCKE_2133 (6) +#define TCKE_2400 (6) +#define TCKE_2667 (7) + +/// +/// tCKE values for LPDDR: max(7.5ns, 3nCK) +/// +#define tCKE_LPDDR_1067 (4) +#define tCKE_LPDDR_1333 (5) +#define tCKE_LPDDR_1600 (6) + +/// +/// tXP values for LPDDR: max(7.5ns, 3nCK) +/// +#define tXP_LPDDR_1333 (5) +#define tXP_LPDDR_1600 (6) + +/// +/// tXPDLL values. +/// +#define TXPDLL_800 (10) +#define TXPDLL_1067 (13) +#define TXPDLL_1333 (16) +#define TXPDLL_1600 (20) +#define TXPDLL_1867 (23) +#define TXPDLL_2133 (26) +#define TXPDLL_2400 (29) +#define TXPDLL_2667 (32) + +/// +/// tAONPD values. +/// +#define TAONPD_800 (4) +#define TAONPD_1067 (5) +#define TAONPD_1333 (6) +#define TAONPD_1600 (7) ///< SNB had 8 +#define TAONPD_1867 (8) +#define TAONPD_2133 (10) +#define TAONPD_2400 (11) +#define TAONPD_2667 (12) + +#define MC_tXP_1600_1N (5) +#define MC_tXP_1867_2N (6) +#define MC_tXP_1867_3N (7) +#define MC_tXP_2133_1N (7) +#define MC_tXP_MAX (8) ///< The maximum value that the MC supports. + +/// +/// tODTon / tODToff values, in [ps] +/// +#define tODT_ON_MIN 1750 +#define tODT_ON_MAX 3500 +#define tODT_OFF_MIN 1750 +#define tODT_OFF_MAX 3500 + +/// +/// tDQSCK values, in [ps] +/// +#define tDQSCK_MIN 2500 +#define tDQSCK_MAX 5500 +/// +/// Specified in PI-Ticks. 64 == 1 QClk +/// +#define tDQSCK_DRIFT 64 + +/** +@brief + This function configures the memory controller timings. + + @param[in] MrcData - Include all MRC global data. + + @retval Nothing. +**/ +extern +void +MrcTimingConfiguration ( + IN MrcParameters *const MrcData + ); + +/** +@brief + This function returns the tXP value for the specified frequency. + + @param[in] DdrType - DDR type + @param[in] Frequency - The memory frequency. + @param[in] NMode - Command mode to lookup. + + @retval The tXP value for the specified frequency. +**/ +extern +U32 +tXPValue ( + IN MrcDdrType DdrType, + IN const MrcFrequency Frequency, + IN U8 NMode + ); + +/** +@brief + This function sets up the Read ODTD values based on RawCard types and adjusts the tDRRD2RD, tDDRD2RD, tDRRD2WR and tDDRD2WR + + @param[in, out] MrcData - Include all MRC global data. + + @retval Nothing. +**/ +extern +void +RdOdtStretch ( + IN OUT MrcParameters *const MrcData + ); + +#endif // _MrcTimingConfiguration_h_ |