diff options
Diffstat (limited to 'ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi')
12 files changed, 649 insertions, 0 deletions
diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/Capsule/Capsule.c b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/Capsule/Capsule.c new file mode 100644 index 0000000..4b1ea89 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/Capsule/Capsule.c @@ -0,0 +1,27 @@ +/** @file + Capsule PPI GUID declaration. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains 'Framework Code' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may not be modified, except as allowed by + additional terms of your license agreement. +**/ + +#include "Tiano.h" +#include "PeiBind.h" +#include "PeiApi.h" +#include EFI_PPI_DEFINITION (Capsule) + +EFI_GUID gPeiCapsulePpiGuid = PEI_CAPSULE_PPI_GUID; + +EFI_GUID_STRING(&gPeiCapsulePpiGuid, "Capsule", "Capsule Update PPI"); diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/Capsule/Capsule.h b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/Capsule/Capsule.h new file mode 100644 index 0000000..200e7f5 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/Capsule/Capsule.h @@ -0,0 +1,60 @@ +/** @file + Capsule PPI definitions. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains 'Framework Code' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may not be modified, except as allowed by + additional terms of your license agreement. +**/ + +#ifndef _PEI_CAPSULE_PPI_H_ +#define _PEI_CAPSULE_PPI_H_ + +#define PEI_CAPSULE_PPI_GUID \ + { \ + 0x3acf33ee, 0xd892, 0x40f4, 0xa2, 0xfc, 0x38, 0x54, 0xd2, 0xe1, 0x32, 0x3d \ + } + +EFI_FORWARD_DECLARATION (PEI_CAPSULE_PPI); + +typedef +EFI_STATUS +(EFIAPI *PEI_CAPSULE_COALESCE) ( + IN EFI_PEI_SERVICES **PeiServices, + IN OUT VOID **MemoryBase, + IN OUT UINTN *MemSize + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_CAPSULE_CREATE_STATE) ( + IN EFI_PEI_SERVICES **PeiServices, + IN VOID *CapsuleBase, /// returned from coalesce + IN UINTN CapsuleSize /// returned from coalesce + ); + +typedef +EFI_STATUS +(EFIAPI *PEI_CAPSULE_CHECK_CAPSULE_UPDATE) ( + IN EFI_PEI_SERVICES **PeiServices + ); + +struct _PEI_CAPSULE_PPI { + PEI_CAPSULE_COALESCE Coalesce; + PEI_CAPSULE_CHECK_CAPSULE_UPDATE CheckCapsuleUpdate; + PEI_CAPSULE_CREATE_STATE CreateState; +}; + +extern EFI_GUID gPeiCapsulePpiGuid; + +#endif /// #ifndef _PEI_CAPSULE_PPI_H_ diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.cif b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.cif new file mode 100644 index 0000000..e8e28a4 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.cif @@ -0,0 +1,18 @@ +<component> + name = "IntelSaSampleCodePpiLib" + category = ModulePart + LocalRoot = "ReferenceCode\Chipset\SystemAgent\SampleCode\Ppi" + RefName = "IntelSaSampleCodePpiLib" +[files] +"IntelSaSampleCodePpiLib.sdl" +"IntelSaSampleCodePpiLib.mak" +"IntelSaSampleCodePpiLib.inf" +"PlatformMemoryRange\PlatformMemoryRange.c" +"PlatformMemoryRange\PlatformMemoryRange.h" +"PlatformMemorySize\PlatformMemorySize.c" +"PlatformMemorySize\PlatformMemorySize.h" +"Capsule\Capsule.c" +"Capsule\Capsule.h" +"SmmAccess\SmmAccess.c" +"SmmAccess\SmmAccess.h" +<endComponent> diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.inf b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.inf new file mode 100644 index 0000000..ce3a918 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.inf @@ -0,0 +1,51 @@ +## @file +# Component description file for the PEI protocol library +# +#@copyright +# Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# + + +[defines] +BASE_NAME = IntelSaSampleCodePpiLib +COMPONENT_TYPE = LIBRARY + +[sources.common] + Capsule/Capsule.h + Capsule/Capsule.c + PlatformMemorySize/PlatformMemorySize.h + PlatformMemorySize/PlatformMemorySize.c + PlatformMemoryRange/PlatformMemoryRange.h + PlatformMemoryRange/PlatformMemoryRange.c + SmmAccess/SmmAccess.c + SmmAccess/SmmAccess.h + +[includes.common] + $(EFI_SOURCE) + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Framework/Include + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Pei/Include + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EFI_SOURCE)/$(PROJECT_SA_ROOT) + $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/SampleCode + +[nmake.common] +C_STD_INCLUDE= diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.mak b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.mak new file mode 100644 index 0000000..c94e324 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.mak @@ -0,0 +1,64 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Refcode/SaSampleCode/IntelSaSampleCodePpiLib/IntelSaSampleCodePpiLib.mak 1 2/08/12 4:53a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 4:53a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Refcode/SaSampleCode/IntelSaSampleCodePpiLib/IntelSaSampleCodePpiLib.mak $ +# +# 1 2/08/12 4:53a Yurenlai +# Intel Haswell/NB eChipset initially releases. +# +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: IntelSaSampleCodePpiLib_LIB.mak +# +# Description: +# +#<AMI_FHDR_END> +#********************************************************************** +all : IntelSaSampleCodePpiLib + +$(BUILD_DIR)\IntelSaSampleCodePpiLib.lib : IntelSaSampleCodePpiLib + +IntelSaSampleCodePpiLib : $(BUILD_DIR)\IntelSaSampleCodePpiLib.mak IntelSaSampleCodePpiLibBin + +$(BUILD_DIR)\IntelSaSampleCodePpiLib.mak : $(IntelSaSampleCodePpiLib_DIR)\$(@B).cif $(IntelSaSampleCodePpiLib_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(IntelSaSampleCodePpiLib_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +IntelSaSampleCodePpiLibBin : + $(MAKE) /$(MAKEFLAGS) $(EDK_DEFAULTS)\ + /f $(BUILD_DIR)\IntelSaSampleCodePpiLib.mak all\ + "MY_INCLUDES=$(EDK_INCLUDES) $(INTEL_MCH_INCLUDES) /I$(INTEL_SYSTEM_AGENT_DIR)\SampleCode" \ + TYPE=PEI_LIBRARY \ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.sdl b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.sdl new file mode 100644 index 0000000..02bda23 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/IntelSaSampleCodePpiLib.sdl @@ -0,0 +1,28 @@ +TOKEN + Name = "IntelSaSampleCodePpiLib_SUPPORT" + Value = "1" + Help = "Main switch to enable FrameworkPpiLib support in Project" + TokenType = Boolean + TargetMAK = Yes + Master = Yes +End + +PATH + Name = "IntelSaSampleCodePpiLib_DIR" +End + +MODULE + Help = "Includes IntelSaSampleCodePpiLib.mak to Project" + File = "IntelSaSampleCodePpiLib.mak" +End + +ELINK + Name = "IntelSaSampleCodePpiLib_LIB" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "$(BUILD_DIR)\IntelSaSampleCodePpiLib.lib" + Parent = "IntelSaSampleCodePpiLib_LIB" + InvokeOrder = AfterParent +End diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemoryRange/PlatformMemoryRange.c b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemoryRange/PlatformMemoryRange.c new file mode 100644 index 0000000..c3c1d75 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemoryRange/PlatformMemoryRange.c @@ -0,0 +1,25 @@ +/** @file + Platform Memory Range PPI GUID as defined in EFI 2.0 + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains 'Framework Code' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may not be modified, except as allowed by + additional terms of your license agreement. +**/ +#include "Tiano.h" +#include "Pei.h" +#include EFI_PPI_DEFINITION (PlatformMemoryRange) + +EFI_GUID gPeiPlatformMemoryRangePpiGuid = PEI_PLATFORM_MEMORY_RANGE_PPI_GUID; + +EFI_GUID_STRING(&gPeiPlatformMemoryRangePpiGuid, "PlatformMemoryRange", "Platform Memory Range PPI"); diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemoryRange/PlatformMemoryRange.h b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemoryRange/PlatformMemoryRange.h new file mode 100644 index 0000000..a9a2b3e --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemoryRange/PlatformMemoryRange.h @@ -0,0 +1,145 @@ +/** @file + Platform Memory Range PPI as defined in EFI 2.0 + PPI for reserving special purpose memory ranges. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains 'Framework Code' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may not be modified, except as allowed by + additional terms of your license agreement. +**/ +#ifndef _PEI_PLATFORM_MEMORY_RANGE_H_ +#define _PEI_PLATFORM_MEMORY_RANGE_H_ + +#define PEI_PLATFORM_MEMORY_RANGE_PPI_GUID \ + { \ + 0x30eb2979, 0xb0f7, 0x4d60, 0xb2, 0xdc, 0x1a, 0x2c, 0x96, 0xce, 0xb1, 0xf4 \ + } + +EFI_FORWARD_DECLARATION (PEI_PLATFORM_MEMORY_RANGE_PPI); + +#define PEI_MEMORY_RANGE_OPTION_ROM UINT32 + +#define PEI_MR_OPTION_ROM_ALL 0xFFFFFFFF +#define PEI_MR_OPTION_ROM_NONE 0x00000000 +#define PEI_MR_OPTION_ROM_C0000_16K 0x00000001 +#define PEI_MR_OPTION_ROM_C4000_16K 0x00000002 +#define PEI_MR_OPTION_ROM_C8000_16K 0x00000004 +#define PEI_MR_OPTION_ROM_CC000_16K 0x00000008 +#define PEI_MR_OPTION_ROM_D0000_16K 0x00000010 +#define PEI_MR_OPTION_ROM_D4000_16K 0x00000020 +#define PEI_MR_OPTION_ROM_D8000_16K 0x00000040 +#define PEI_MR_OPTION_ROM_DC000_16K 0x00000080 +#define PEI_MR_OPTION_ROM_E0000_16K 0x00000100 +#define PEI_MR_OPTION_ROM_E4000_16K 0x00000200 +#define PEI_MR_OPTION_ROM_E8000_16K 0x00000400 +#define PEI_MR_OPTION_ROM_EC000_16K 0x00000800 +#define PEI_MR_OPTION_ROM_F0000_16K 0x00001000 +#define PEI_MR_OPTION_ROM_F4000_16K 0x00002000 +#define PEI_MR_OPTION_ROM_F8000_16K 0x00004000 +#define PEI_MR_OPTION_ROM_FC000_16K 0x00008000 + +/// +/// SMRAM Memory Range +/// +#define PEI_MEMORY_RANGE_SMRAM UINT32 +#define PEI_MR_SMRAM_ALL 0xFFFFFFFF +#define PEI_MR_SMRAM_NONE 0x00000000 +#define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000 +#define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000 +#define PEI_MR_SMRAM_ABSEG_MASK 0x00010000 +#define PEI_MR_SMRAM_HSEG_MASK 0x00020000 +#define PEI_MR_SMRAM_TSEG_MASK 0x00040000 +/// +/// If adding additional entries, SMRAM Size +/// is a multiple of 128KB. +/// +#define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF +#define PEI_MR_SMRAM_SIZE_128K_MASK 0x00000001 +#define PEI_MR_SMRAM_SIZE_256K_MASK 0x00000002 +#define PEI_MR_SMRAM_SIZE_512K_MASK 0x00000004 +#define PEI_MR_SMRAM_SIZE_1024K_MASK 0x00000008 +#define PEI_MR_SMRAM_SIZE_2048K_MASK 0x00000010 +#define PEI_MR_SMRAM_SIZE_4096K_MASK 0x00000020 +#define PEI_MR_SMRAM_SIZE_8192K_MASK 0x00000040 +#define PEI_MR_SMRAM_SIZE_16384K_MASK 0x00000080 +#define PEI_MR_SMRAM_SIZE_32768K_MASK 0x00000100 +#define PEI_MR_SMRAM_SIZE_65536K_MASK 0x00000200 + +#define PEI_MR_SMRAM_ABSEG_128K_NOCACHE 0x00010001 +#define PEI_MR_SMRAM_HSEG_128K_CACHE 0x80020001 +#define PEI_MR_SMRAM_HSEG_128K_NOCACHE 0x00020001 +#define PEI_MR_SMRAM_TSEG_128K_CACHE 0x80040001 +#define PEI_MR_SMRAM_TSEG_128K_NOCACHE 0x00040001 +#define PEI_MR_SMRAM_TSEG_256K_CACHE 0x80040002 +#define PEI_MR_SMRAM_TSEG_256K_NOCACHE 0x00040002 +#define PEI_MR_SMRAM_TSEG_512K_CACHE 0x80040004 +#define PEI_MR_SMRAM_TSEG_512K_NOCACHE 0x00040004 +#define PEI_MR_SMRAM_TSEG_1024K_CACHE 0x80040008 +#define PEI_MR_SMRAM_TSEG_1024K_NOCACHE 0x00040008 + +/// +/// Graphics Memory Range +/// +#define PEI_MEMORY_RANGE_GRAPHICS_MEMORY UINT32 +#define PEI_MR_GRAPHICS_MEMORY_ALL 0xFFFFFFFF +#define PEI_MR_GRAPHICS_MEMORY_NONE 0x00000000 +#define PEI_MR_GRAPHICS_MEMORY_CACHEABLE 0x80000000 +/// +/// If adding additional entries, Graphics Memory Size +/// is a multiple of 512KB. +/// +#define PEI_MR_GRAPHICS_MEMORY_SIZE_MASK 0x0000FFFF +#define PEI_MR_GRAPHICS_MEMORY_512K_NOCACHE 0x00000001 +#define PEI_MR_GRAPHICS_MEMORY_512K_CACHE 0x80000001 +#define PEI_MR_GRAPHICS_MEMORY_1M_NOCACHE 0x00000002 +#define PEI_MR_GRAPHICS_MEMORY_1M_CACHE 0x80000002 +#define PEI_MR_GRAPHICS_MEMORY_4M_NOCACHE 0x00000008 +#define PEI_MR_GRAPHICS_MEMORY_4M_CACHE 0x80000008 +#define PEI_MR_GRAPHICS_MEMORY_8M_NOCACHE 0x00000010 +#define PEI_MR_GRAPHICS_MEMORY_8M_CACHE 0x80000010 +#define PEI_MR_GRAPHICS_MEMORY_16M_NOCACHE 0x00000020 +#define PEI_MR_GRAPHICS_MEMORY_16M_CACHE 0x80000020 +#define PEI_MR_GRAPHICS_MEMORY_32M_NOCACHE 0x00000040 +#define PEI_MR_GRAPHICS_MEMORY_32M_CACHE 0x80000040 +#define PEI_MR_GRAPHICS_MEMORY_48M_NOCACHE 0x00000060 +#define PEI_MR_GRAPHICS_MEMORY_48M_CACHE 0x80000060 +#define PEI_MR_GRAPHICS_MEMORY_64M_NOCACHE 0x00000080 +#define PEI_MR_GRAPHICS_MEMORY_64M_CACHE 0x80000080 +#define PEI_MR_GRAPHICS_MEMORY_128M_NOCACHE 0x00000100 +#define PEI_MR_GRAPHICS_MEMORY_128M_CACHE 0x80000100 +#define PEI_MR_GRAPHICS_MEMORY_256M_NOCACHE 0x00000200 +#define PEI_MR_GRAPHICS_MEMORY_256M_CACHE 0x80000200 +/// +/// Pci Memory Hole +/// +#define PEI_MEMORY_RANGE_PCI_MEMORY UINT32 +#define PEI_MR_PCI_MEMORY_SIZE_512M_MASK 0x00000001 + +typedef +EFI_STATUS +(EFIAPI *PEI_CHOOSE_RANGES) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_PLATFORM_MEMORY_RANGE_PPI * This, + IN OUT PEI_MEMORY_RANGE_OPTION_ROM * OptionRomMask, + IN OUT PEI_MEMORY_RANGE_SMRAM * SmramMask, + IN OUT PEI_MEMORY_RANGE_GRAPHICS_MEMORY * GraphicsMemoryMask, + IN OUT PEI_MEMORY_RANGE_PCI_MEMORY * PciMemoryMask + ); + +struct _PEI_PLATFORM_MEMORY_RANGE_PPI { + PEI_CHOOSE_RANGES ChooseRanges; +}; + +extern EFI_GUID gPeiPlatformMemoryRangePpiGuid; + +#endif diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemorySize/PlatformMemorySize.c b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemorySize/PlatformMemorySize.c new file mode 100644 index 0000000..4a6c6ea --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemorySize/PlatformMemorySize.c @@ -0,0 +1,25 @@ +/** @file + Platform Memory Size PPI GUID as defined in Tiano + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains 'Framework Code' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may not be modified, except as allowed by + additional terms of your license agreement. +**/ +#include "Tiano.h" +#include "Pei.h" +#include EFI_PPI_DEFINITION (PlatformMemorySize) + +EFI_GUID gPeiPlatformMemorySizePpiGuid = PEI_PLATFORM_MEMORY_SIZE_PPI_GUID; + +EFI_GUID_STRING(&gPeiPlatformMemorySizePpiGuid, "PlatformMemorySize", "Platform Memory Size PPI"); diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemorySize/PlatformMemorySize.h b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemorySize/PlatformMemorySize.h new file mode 100644 index 0000000..0c11041 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/PlatformMemorySize/PlatformMemorySize.h @@ -0,0 +1,45 @@ +/** @file + Platform Memory Size PPI as defined in Tiano + PPI for describing the minimum platform memory size in order to successfully + pass control into DXE + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains 'Framework Code' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may not be modified, except as allowed by + additional terms of your license agreement. +**/ +#ifndef _PEI_PLATFORM_MEMORY_SIZE_H_ +#define _PEI_PLATFORM_MEMORY_SIZE_H_ + +#define PEI_PLATFORM_MEMORY_SIZE_PPI_GUID \ + { \ + 0x9a7ef41e, 0xc140, 0x4bd1, 0xb8, 0x84, 0x1e, 0x11, 0x24, 0xb, 0x4c, 0xe6 \ + } + +EFI_FORWARD_DECLARATION (PEI_PLATFORM_MEMORY_SIZE_PPI); + +typedef +EFI_STATUS +(EFIAPI *PEI_GET_MINIMUM_PLATFORM_MEMORY_SIZE) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_PLATFORM_MEMORY_SIZE_PPI * This, + IN OUT UINT64 *MemorySize + ); + +struct _PEI_PLATFORM_MEMORY_SIZE_PPI { + PEI_GET_MINIMUM_PLATFORM_MEMORY_SIZE GetPlatformMemorySize; +}; + +extern EFI_GUID gPeiPlatformMemorySizePpiGuid; + +#endif diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/SmmAccess/SmmAccess.c b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/SmmAccess/SmmAccess.c new file mode 100644 index 0000000..9dc4695 --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/SmmAccess/SmmAccess.c @@ -0,0 +1,25 @@ +/** @file + SmmAccess PPI GUID + +@copyright + Copyright (c) 2009 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains 'Framework Code' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may not be modified, except as allowed by + additional terms of your license agreement. +**/ +#include "Tiano.h" +#include "Pei.h" +#include EFI_PPI_DEFINITION (SmmAccess) + +EFI_GUID gPeiSmmAccessPpiGuid = PEI_SMM_ACCESS_PPI_GUID; + +EFI_GUID_STRING(&gPeiSmmAccessPpiGuid, "SmmAccess", "SMM Access PPI"); diff --git a/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/SmmAccess/SmmAccess.h b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/SmmAccess/SmmAccess.h new file mode 100644 index 0000000..8ff077f --- /dev/null +++ b/ReferenceCode/Chipset/SystemAgent/SampleCode/Ppi/SmmAccess/SmmAccess.h @@ -0,0 +1,136 @@ +/** @file + This code abstracts the PEI core to provide SmmAccess services. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains 'Framework Code' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may not be modified, except as allowed by + additional terms of your license agreement. +**/ +#ifndef _PEI_SMM_ACCESS_PPI_H_ +#define _PEI_SMM_ACCESS_PPI_H_ + +#include EFI_GUID_DEFINITION (SmramMemoryReserve) + +#define PEI_SMM_ACCESS_PPI_GUID \ + { \ + 0x268f33a9, 0xcccd, 0x48be, 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 \ + } + +EFI_FORWARD_DECLARATION (PEI_SMM_ACCESS_PPI); + +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_OPEN) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_ACCESS_PPI * This, + IN UINTN DescriptorIndex + ) +/** + This routine accepts a request to "open" a region of SMRAM. The + region could be legacy ABSEG, HSEG, or TSEG near top of physical memory. + The use of "open" means that the memory is visible from all PEIM + and SMM agents. + + @param[in] This - Pointer to the SMM Access Interface. + @param[in] DescriptorIndex - Region of SMRAM to Open. + + @retval EFI_SUCCESS - The region was successfully opened. + @retval EFI_DEVICE_ERROR - The region could not be opened because locked by + chipset. + @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds. +**/ +; + +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_CLOSE) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_ACCESS_PPI * This, + IN UINTN DescriptorIndex + ) +/** + This routine accepts a request to "close" a region of SMRAM. The + region could be legacy AB or TSEG near top of physical memory. + The use of "close" means that the memory is only visible from SMM agents, + not from PEIM. + + @param[in] This - Pointer to the SMM Access Interface. + @param[in] DescriptorIndex - Region of SMRAM to Close. + + @retval EFI_SUCCESS - The region was successfully closed. + @retval EFI_DEVICE_ERROR - The region could not be closed because locked by + chipset. + @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds. +**/ +; + +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_LOCK) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_ACCESS_PPI * This, + IN UINTN DescriptorIndex + ) +/** + This routine accepts a request to "lock" SMRAM. The + region could be legacy AB or TSEG near top of physical memory. + The use of "lock" means that the memory can no longer be opened + to PEIM. + + @param[in] This - Pointer to the SMM Access Interface. + @param[in] DescriptorIndex - Region of SMRAM to Lock. + + @retval EFI_SUCCESS - The region was successfully locked. + @retval EFI_DEVICE_ERROR - The region could not be locked because at least + one range is still open. + @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds. +**/ +; + +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_CAPABILITIES) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_ACCESS_PPI * This, + IN OUT UINTN *SmramMapSize, + IN OUT EFI_SMRAM_DESCRIPTOR * SmramMap + ) +/** + This routine services a user request to discover the SMRAM + capabilities of this platform. This will report the possible + ranges that are possible for SMRAM access, based upon the + memory controller capabilities. + + @param[in] This - Pointer to the SMRAM Access Interface. + @param[in] SmramMapSize - Pointer to the variable containing size of the + buffer to contain the description information. + @param[in] SmramMap - Buffer containing the data describing the Smram + region descriptors. + + @retval EFI_BUFFER_TOO_SMALL - The user did not provide a sufficient buffer. + @retval EFI_SUCCESS - The user provided a sufficiently-sized buffer. +**/ +; + +struct _PEI_SMM_ACCESS_PPI { + PEI_SMM_OPEN Open; + PEI_SMM_CLOSE Close; + PEI_SMM_LOCK Lock; + PEI_SMM_CAPABILITIES GetCapabilities; + BOOLEAN LockState; + BOOLEAN OpenState; +}; + +extern EFI_GUID gPeiSmmAccessPpiGuid; + +#endif |