diff options
Diffstat (limited to 'ReferenceCode/Haswell/CpuInit/Pei')
| -rw-r--r-- | ReferenceCode/Haswell/CpuInit/Pei/BootGuardInit.c | 111 | ||||
| -rw-r--r-- | ReferenceCode/Haswell/CpuInit/Pei/CachePeim.c | 1045 | ||||
| -rw-r--r-- | ReferenceCode/Haswell/CpuInit/Pei/CpuInitPei.cif | 20 | ||||
| -rw-r--r-- | ReferenceCode/Haswell/CpuInit/Pei/CpuInitPei.mak | 76 | ||||
| -rw-r--r-- | ReferenceCode/Haswell/CpuInit/Pei/CpuInitPei.sdl | 37 | ||||
| -rw-r--r-- | ReferenceCode/Haswell/CpuInit/Pei/CpuInitPeim.c | 1404 | ||||
| -rw-r--r-- | ReferenceCode/Haswell/CpuInit/Pei/CpuInitPeim.dxs | 42 | ||||
| -rw-r--r-- | ReferenceCode/Haswell/CpuInit/Pei/CpuInitPeim.h | 212 | ||||
| -rw-r--r-- | ReferenceCode/Haswell/CpuInit/Pei/CpuInitPeim.inf | 124 | ||||
| -rw-r--r-- | ReferenceCode/Haswell/CpuInit/Pei/CpuOcInit.c | 292 | ||||
| -rw-r--r-- | ReferenceCode/Haswell/CpuInit/Pei/CpuOcInit.h | 55 | ||||
| -rw-r--r-- | ReferenceCode/Haswell/CpuInit/Pei/Ia32/Cpu.asm | 77 | ||||
| -rw-r--r-- | ReferenceCode/Haswell/CpuInit/Pei/PfatInit.c | 191 | ||||
| -rw-r--r-- | ReferenceCode/Haswell/CpuInit/Pei/PfatInit.h | 42 |
14 files changed, 3728 insertions, 0 deletions
diff --git a/ReferenceCode/Haswell/CpuInit/Pei/BootGuardInit.c b/ReferenceCode/Haswell/CpuInit/Pei/BootGuardInit.c new file mode 100644 index 0000000..f877784 --- /dev/null +++ b/ReferenceCode/Haswell/CpuInit/Pei/BootGuardInit.c @@ -0,0 +1,111 @@ +/** @file + EFI 2.0 PEIM to initialize the cache and load the BSP microcode + +@copyright + Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Pre-EFI Module' and is licensed + for Intel CPUs and Chipsets under the terms of your license + agreement with Intel or your vendor. This file may be + modified by the user, subject to additional terms of the + license agreement + +**/ + +/// +/// External include files do NOT need to be explicitly specified in real EDKII +/// environment +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGluePeim.h" +#include "CpuInitPeim.h" +#include "CpuAccess.h" +#include "BootGuardLibrary.h" +#include "MeAccess.h" +#include "HeciRegs.h" +#endif + +VOID +BootGuardInit ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CPU_PLATFORM_POLICY_PPI *CpuPlatformPolicyPpi + ) +/** + + Perform the platform spefific initializations. + + @param[in] PeiServices - Indirect reference to the PEI Services Table. + @param[in] CpuPlatformPolicyPpi - Platform Policy PPI + +**/ +{ + UINT32 MsrValue; + UINT32 MeFwSts4; + UINT32 BootGuardAcmStatus; + + if (CpuPlatformPolicyPpi->SecurityConfig->BootGuardConfig == NULL) { + return; + } + + /// + /// Check if System Supports Boot Guard + /// + if( IsBootGuardSupported() ) { + CpuPlatformPolicyPpi->SecurityConfig->BootGuardConfig->BootGuardSupport = TRUE; + + BootGuardAcmStatus = *(UINT32 *) (UINTN) (TXT_PUBLIC_BASE + R_CPU_BOOT_GUARD_ACM_STATUS); + DEBUG ((EFI_D_INFO, "Boot Guard ACM Status = %x\n", BootGuardAcmStatus)); + + /// + /// Check Bit 12 in ME FWSTS4 to check if TPM_DISCONNECT_ALL bit is set + /// or ENF Shutdown path is taken by ME FW. + /// Also Identify any failures in ACM + /// + MeFwSts4 = HeciPciRead32(R_ME_HFS_4); + DEBUG ((EFI_D_INFO, "ME FW STS 4 = %x\n", MeFwSts4)); + if((MeFwSts4 & (B_TPM_DISCONNECT | B_BOOT_GUARD_ENF_MASK)) || (BootGuardAcmStatus & B_BOOT_GUARD_ACM_ERRORCODE_MASK)) { + DEBUG ((EFI_D_INFO, "All TPM's on Platform are Disconnected\n")); + CpuPlatformPolicyPpi->SecurityConfig->BootGuardConfig->DisconnectAllTpms = TRUE; + } + CpuPlatformPolicyPpi->SecurityConfig->BootGuardConfig->BypassTpmInit = FALSE; + CpuPlatformPolicyPpi->SecurityConfig->BootGuardConfig->MeasuredBoot = FALSE; + + if(MeFwSts4 & BIT10) { + DEBUG ((EFI_D_INFO, "Sx Resume Type Identified - TPM Event Log not required for ACM Measurements\n")); + CpuPlatformPolicyPpi->SecurityConfig->BootGuardConfig->ByPassTpmEventLog = TRUE; + } + /// + /// Check bit 0 of BOOT_GUARD_SACM_INFO MSR if system is in Boot Guard boot mode + /// + MsrValue = (UINT32) AsmReadMsr64 (MSR_BOOT_GUARD_SACM_INFO); + DEBUG ((EFI_D_INFO, "MSR_BOOT_GUARD_SACM_INFO MSR = %x\n", MsrValue)); + if ( (MsrValue & B_NEM_INIT) == 0 ) { + DEBUG ((EFI_D_INFO, "NEM is not initiated by Boot Guard ACM\n")); + } + if (MsrValue & B_MEASURED) { + CpuPlatformPolicyPpi->SecurityConfig->BootGuardConfig->MeasuredBoot = TRUE; + /// + /// if measured bit is set, BIOS needs to bypass startup command + /// + if (MsrValue & B_TPM_SUCCESS) { + CpuPlatformPolicyPpi->SecurityConfig->BootGuardConfig->BypassTpmInit = TRUE; + } + /// + /// Read present TPM type + /// + CpuPlatformPolicyPpi->SecurityConfig->BootGuardConfig->TpmType = (TPM_TYPE) ( (MsrValue & V_TPM_PRESENT_MASK) >> 1 ); + DEBUG ((EFI_D_INFO, "TPM Type is %x\n", CpuPlatformPolicyPpi->SecurityConfig->BootGuardConfig->TpmType)); + } + } else { + CpuPlatformPolicyPpi->SecurityConfig->BootGuardConfig->BootGuardSupport = FALSE; + } + + return; +} diff --git a/ReferenceCode/Haswell/CpuInit/Pei/CachePeim.c b/ReferenceCode/Haswell/CpuInit/Pei/CachePeim.c new file mode 100644 index 0000000..959c58e --- /dev/null +++ b/ReferenceCode/Haswell/CpuInit/Pei/CachePeim.c @@ -0,0 +1,1045 @@ +/** @file + EFI 2.0 PEIM to initialize the cache and load the BSP microcode + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Pre-EFI Module' and is licensed + for Intel CPUs and Chipsets under the terms of your license + agreement with Intel or your vendor. This file may be + modified by the user, subject to additional terms of the + license agreement + +**/ +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGluePeim.h" +#include "CpuAccess.h" +#include "CpuInitPeim.h" +#include EFI_PPI_PRODUCER (Cache) +#define ALIGNED_SEED 0x01010101 +#endif + +INT8 +CheckDirection ( + IN UINT64 Input + ); + +UINT64 +PeiPower2MaxMemory ( + IN UINT64 MemoryLength + ); + +VOID +EfiDisableCacheMtrr ( + IN UINT64 *OldMtrr + ); + +VOID +EfiRecoverCacheMtrr ( + IN BOOLEAN EnableMtrr, + IN UINT64 OldMtrr + ); + +VOID +EfiProgramMtrr ( + IN PEI_CACHE_PPI *This, + IN UINTN MtrrNumber, + IN EFI_PHYSICAL_ADDRESS MemoryAddress, + IN UINT64 MemoryLength, + IN EFI_MEMORY_CACHE_TYPE MemoryCacheType, + IN UINT64 ValidMtrrAddressMask + ); + +EFI_STATUS +EFIAPI +PeiResetCacheAttributes ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CACHE_PPI *This + ); + +EFI_STATUS +EFIAPI +PeiActivateCache ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CACHE_PPI *This + ); + +EFI_STATUS +EFIAPI +PeiSetCacheAttributes ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CACHE_PPI *This, + IN EFI_PHYSICAL_ADDRESS MemoryAddress, + IN UINT64 MemoryLength, + IN EFI_MEMORY_CACHE_TYPE MemoryCacheType + ); + +EFI_STATUS +SearchForExactMtrr ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CACHE_PPI *This, + IN EFI_PHYSICAL_ADDRESS MemoryAddress, + IN UINT64 MemoryLength, + IN UINT64 ValidMtrrAddressMask, + OUT UINT32 *UsedMsrNum, + OUT EFI_MEMORY_CACHE_TYPE *MemoryCacheType + ); + +BOOLEAN +IsDefaultType ( + IN EFI_MEMORY_CACHE_TYPE MemoryCacheType + ); + +EFI_STATUS +DisableCacheAsRam ( + VOID + ); + +typedef struct _ALIGNED_DWORD { + UINT32 High; + UINT32 Low; +} ALIGNED_DWORD; + +typedef union _ALIGNED { + UINT64 AlignedQword; + ALIGNED_DWORD AlignedDword; +} ALIGNED; + +typedef struct { + UINT32 Msr; + UINT32 BaseAddress; + UINT32 Length; +} FIXED_MTRR; + +FIXED_MTRR mFixedMtrrTable[] = { + { + IA32_MTRR_FIX64K_00000, + 0, + 0x10000 + }, + { + IA32_MTRR_FIX16K_80000, + 0x80000, + 0x4000 + }, + { + IA32_MTRR_FIX16K_A0000, + 0xA0000, + 0x4000 + }, + { + IA32_MTRR_FIX4K_C0000, + 0xC0000, + 0x1000 + }, + { + IA32_MTRR_FIX4K_C8000, + 0xC8000, + 0x1000 + }, + { + IA32_MTRR_FIX4K_D0000, + 0xD0000, + 0x1000 + }, + { + IA32_MTRR_FIX4K_D8000, + 0xD8000, + 0x1000 + }, + { + IA32_MTRR_FIX4K_E0000, + 0xE0000, + 0x1000 + }, + { + IA32_MTRR_FIX4K_E8000, + 0xE8000, + 0x1000 + }, + { + IA32_MTRR_FIX4K_F0000, + 0xF0000, + 0x1000 + }, + { + IA32_MTRR_FIX4K_F8000, + 0xF8000, + 0x1000 + }, + { + 0, + 0x100000, + 0 + } +}; + +PEI_CACHE_PPI mCachePpi = { + PeiSetCacheAttributes, + PeiResetCacheAttributes, + PeiActivateCache +}; + +/** + Update MTRR setting to memory buffer + + @param[in] This - Current instance of Pei Cache PPI. + @param[in] MsrNum - offset 0-10 maps to Fixed MTRR table + offset above 0x200 maps to Variable MTRR table + @param[in] UpdateValue - MTRR setting + **/ +VOID +WriteMsrToBuffer ( + IN PEI_CACHE_PPI *This, + IN UINT32 MsrNum, + IN UINT64 UpdateValue + ) +{ + CACHE_PPI_INSTANCE *CachePpiInstance; + CachePpiInstance = PEI_CACHE_PPI_INSTANCE_FROM_THIS (This); + if (MsrNum >= CACHE_VARIABLE_MTRR_BASE) { + if ((MsrNum - CACHE_VARIABLE_MTRR_BASE) >= V_MAXIMUM_VARIABLE_MTRR_NUMBER * 2) { + ASSERT (FALSE); + return; + } + + CachePpiInstance->VariableMtrrChanged = TRUE; + CachePpiInstance->VariableMtrrValue[MsrNum - CACHE_VARIABLE_MTRR_BASE].Changed = TRUE; + CachePpiInstance->VariableMtrrValue[MsrNum - CACHE_VARIABLE_MTRR_BASE].MsrValue = UpdateValue; + } else { + if (MsrNum >= V_FIXED_MTRR_NUMBER) { + ASSERT (FALSE); + return; + } + + CachePpiInstance->FixedMtrrChanged = TRUE; + CachePpiInstance->FixedMtrrValue[MsrNum].Changed = TRUE; + CachePpiInstance->FixedMtrrValue[MsrNum].MsrValue = UpdateValue; + } +} + +/** + Read MTRR from Buffer. If buffer not ready, read from real MSR instead. + + @param[in] This - Current instance of Pei Cache PPI. + @param[in] MsrNum - offset 0-10 maps to Fixed MTRR table + offset above 0x200 maps to Variable MTRR table + + @retval Return MTRR setting + **/ +UINT64 +ReadMsrFromBuffer ( + IN PEI_CACHE_PPI *This, + IN UINT32 MsrNum + ) +{ + UINT64 MtrrVal; + CACHE_PPI_INSTANCE *CachePpiInstance; + CachePpiInstance = PEI_CACHE_PPI_INSTANCE_FROM_THIS (This); + if (MsrNum >= CACHE_VARIABLE_MTRR_BASE) { + if ((MsrNum - CACHE_VARIABLE_MTRR_BASE) >= V_MAXIMUM_VARIABLE_MTRR_NUMBER * 2) { + ASSERT (FALSE); + return 0; + } + + if (CachePpiInstance->VariableMtrrValue[MsrNum - CACHE_VARIABLE_MTRR_BASE].Changed) { + MtrrVal = CachePpiInstance->VariableMtrrValue[MsrNum - CACHE_VARIABLE_MTRR_BASE].MsrValue; + } else { + MtrrVal = AsmReadMsr64 (MsrNum); + } + } else { + if (MsrNum >= V_FIXED_MTRR_NUMBER) { + ASSERT (FALSE); + return 0; + } + + if (CachePpiInstance->FixedMtrrValue[MsrNum].Changed) { + MtrrVal = CachePpiInstance->FixedMtrrValue[MsrNum].MsrValue; + } else { + MtrrVal = AsmReadMsr64 (mFixedMtrrTable[MsrNum].Msr); + } + } + + return MtrrVal; +} + +/** + Disable cache and its mtrr + + @param[in] OldMtrr - To return the Old MTRR value +**/ +VOID +EfiDisableCacheMtrr ( + OUT UINT64 *OldMtrr + ) +{ + UINT64 TempQword; + + EfiDisableCache (); + + /// + /// Disable Cache MTRR + /// + *OldMtrr = AsmReadMsr64 (CACHE_IA32_MTRR_DEF_TYPE); + TempQword = (*OldMtrr) &~B_CACHE_MTRR_VALID &~B_CACHE_FIXED_MTRR_VALID; + AsmWriteMsr64 (CACHE_IA32_MTRR_DEF_TYPE, TempQword); + return; +} + +/** + Recover cache MTRR + + @param[in] EnableMtrr - Whether to enable the MTRR + @param[in] OldMtrr - The saved old MTRR value to restore when not to + enable the MTRR +**/ +VOID +EfiRecoverCacheMtrr ( + IN BOOLEAN EnableMtrr, + IN UINT64 OldMtrr + ) +{ + UINT64 TempQword; + + TempQword = 0; + + /// + /// Enable Cache MTRR + /// + if (EnableMtrr) { + TempQword = AsmReadMsr64 (CACHE_IA32_MTRR_DEF_TYPE); + TempQword |= (B_CACHE_MTRR_VALID | B_CACHE_FIXED_MTRR_VALID); + } else { + TempQword = OldMtrr; + } + + AsmWriteMsr64 (CACHE_IA32_MTRR_DEF_TYPE, TempQword); + + EfiEnableCache (); + return; +} + +/** + Programming MTRR according to Memory address, length, and type. + + @param[in] This - Pointer to PEI_CACHE_PPI + @param[in] MtrrNumber - the variable MTRR index number + @param[in] MemoryAddress - the address of target memory + @param[in] MemoryLength - the length of target memory + @param[in] MemoryCacheType - the cache type of target memory + @param[in] ValidMtrrAddressMask - the MTRR address mask +**/ +VOID +EfiProgramMtrr ( + IN PEI_CACHE_PPI *This, + IN UINT32 MtrrNumber, + IN EFI_PHYSICAL_ADDRESS MemoryAddress, + IN UINT64 MemoryLength, + IN EFI_MEMORY_CACHE_TYPE MemoryCacheType, + IN UINT64 ValidMtrrAddressMask + ) +{ + UINT64 TempQword; + + /// + /// MTRR Physical Base + /// + TempQword = (MemoryAddress & ValidMtrrAddressMask) | MemoryCacheType; + WriteMsrToBuffer (This, MtrrNumber, TempQword); + + /// + /// MTRR Physical Mask + /// + TempQword = ~(MemoryLength - 1); + WriteMsrToBuffer (This, MtrrNumber + 1, (TempQword & ValidMtrrAddressMask) | B_CACHE_MTRR_VALID); + + return; +} + +/** + Calculate max memory of power 2 + + @param[in] MemoryLength - Memory length that will be calculated + + @retval Max memory +**/ +UINT64 +PeiPower2MaxMemory ( + IN UINT64 MemoryLength + ) +{ + UINT64 Result; + UINT32 *ResultPointer; + UINT32 *MemoryLengthPointer; + MemoryLengthPointer = (UINT32 *) &MemoryLength; + ResultPointer = (UINT32 *) &Result; + Result = 0; + if (MemoryLengthPointer[1] != 0) { + ResultPointer[1] = GetPowerOfTwo32 (MemoryLengthPointer[1]); + } else { + ResultPointer[0] = GetPowerOfTwo32 (MemoryLengthPointer[0]); + } + + return Result; +} + +/** + Program the unaligned MTRR register. + + @param[in] This - Pointer to PEI_CACHE_PPI + @param[in] AlignedQword - The aligned 64-bit cache type. + @param[in] MsrNum - The index of current MTRR. + @param[in] UnalignedBase - Base Address of the current unaligned MTRR. + @param[in] UnalignedLimit - Limit Address of the current unaligned MTRR. + + @retval EFI_SUCCESS - The unaligned MTRR is set successfully. + @retval EFI_DEVICE_ERROR - The unaligned address is not the multiple of the basic length of MTRR. +**/ +EFI_STATUS +PeiProgramUnalignedMtrr ( + IN PEI_CACHE_PPI *This, + IN UINT64 AlignedQword, + IN UINTN MsrNum, + IN UINT32 UnalignedBase, + IN UINT32 UnalignedLimit + ) +{ + UINT32 UnalignedOffset; + UINT64 TempQword; + UINT64 Mask; + UINT8 ByteShift; + + UnalignedOffset = UnalignedBase - mFixedMtrrTable[MsrNum].BaseAddress; + if (UnalignedOffset % mFixedMtrrTable[MsrNum].Length != 0) { + return EFI_DEVICE_ERROR; + } + + ByteShift = (UINT8) (UnalignedOffset / mFixedMtrrTable[MsrNum].Length); + Mask = ~(LShiftU64 (1, ByteShift * 8) - 1); + + if (UnalignedLimit < mFixedMtrrTable[MsrNum + 1].BaseAddress) { + UnalignedOffset = UnalignedLimit - mFixedMtrrTable[MsrNum].BaseAddress; + if (UnalignedOffset % mFixedMtrrTable[MsrNum].Length != 0) { + return EFI_DEVICE_ERROR; + } + + ByteShift = (UINT8) (UnalignedOffset / mFixedMtrrTable[MsrNum].Length); + Mask &= LShiftU64 (1, ByteShift * 8) - 1; + } + + TempQword = ReadMsrFromBuffer (This, MsrNum) &~Mask; + TempQword |= AlignedQword & Mask; + WriteMsrToBuffer (This, MsrNum, TempQword); + return EFI_SUCCESS; +} + +/** + Given the low memory range ( <= 1MB) and cache type, program the MTRRs. + + @param[in] This - Current instance of Pei Cache PPI. + @param[in] MemoryCacheType - Cache Type. + @param[in] MemoryBase - Base Address of Memory to program MTRR. + @param[in] MemoryLimit - Limit Address of Memory to program MTRR. + + @retval EFI_SUCCESS - Low memory MTRR is set successfully. + @retval others - An error occurs when setting Low memory MTRR. +**/ +EFI_STATUS +PeiProgramLowMemoryMtrr ( + IN PEI_CACHE_PPI *This, + IN EFI_MEMORY_CACHE_TYPE MemoryCacheType, + IN UINT32 MemoryBase, + IN UINT32 MemoryLimit + ) +{ + EFI_STATUS Status; + ALIGNED Aligned; + UINTN MsrNum; + + Status = EFI_SUCCESS; + + Aligned.AlignedDword.High = MemoryCacheType * ALIGNED_SEED; + Aligned.AlignedDword.Low = Aligned.AlignedDword.High; + + for (MsrNum = 0; mFixedMtrrTable[MsrNum].BaseAddress < MemoryBase; MsrNum++) { + ; + } + + if (MemoryBase < mFixedMtrrTable[MsrNum].BaseAddress) { + Status = PeiProgramUnalignedMtrr (This, Aligned.AlignedQword, MsrNum - 1, MemoryBase, MemoryLimit); + if (EFI_ERROR (Status)) { + goto Done; + } + } + + while (MsrNum < V_FIXED_MTRR_NUMBER && MemoryLimit >= mFixedMtrrTable[MsrNum + 1].BaseAddress) { + /// + /// Program aligned MTRR + /// + WriteMsrToBuffer (This, MsrNum, Aligned.AlignedQword); + MsrNum++; + } + + if (MemoryLimit > mFixedMtrrTable[MsrNum].BaseAddress) { + Status = PeiProgramUnalignedMtrr ( + This, + Aligned.AlignedQword, + MsrNum, + mFixedMtrrTable[MsrNum].BaseAddress, + MemoryLimit + ); + } + +Done: + return Status; +} + +/** + Given the memory range and cache type, programs the MTRRs. + + @param[in] PeiServices - General purpose services available to every PEIM. + @param[in] This - Current instance of Pei Cache PPI. + @param[in] MemoryAddress - Base Address of Memory to program MTRR. + @param[in] MemoryLength - Length of Memory to program MTRR. + @param[in] MemoryCacheType - Cache Type. + + @retval EFI_SUCCESS - Mtrr are set successfully. + @retval EFI_LOAD_ERROR - No empty MTRRs to use. + @retval EFI_INVALID_PARAMETER - The input parameter is not valid. + @retval others - An error occurs when setting MTTR. +**/ +EFI_STATUS +EFIAPI +PeiSetCacheAttributes ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CACHE_PPI *This, + IN EFI_PHYSICAL_ADDRESS MemoryAddress, + IN UINT64 MemoryLength, + IN EFI_MEMORY_CACHE_TYPE MemoryCacheType + ) +{ + EFI_STATUS Status; + UINT32 MsrNum; + UINT64 TempQword; + UINT32 UsedMsrNum; + EFI_MEMORY_CACHE_TYPE UsedMemoryCacheType; + UINT64 ValidMtrrAddressMask; + EFI_CPUID_REGISTER FeatureInfo; + UINT64 Power2Length[8]; + UINT64 LengthArray[8]; + UINTN LengthSize; + UINTN Index; + UINTN Count; + UINT32 Remainder; + UINT32 VariableMtrrLimit; + UINT32 *TempQwordPointer; + UINT32 *Power2LengthPointer; + + TempQwordPointer = (UINT32 *) &TempQword; + + VariableMtrrLimit = (UINT32) (AsmReadMsr64 (IA32_MTRR_CAP) & B_IA32_MTRR_VARIABLE_SUPPORT); + if (VariableMtrrLimit > V_MAXIMUM_VARIABLE_MTRR_NUMBER) { + VariableMtrrLimit = V_MAXIMUM_VARIABLE_MTRR_NUMBER; + } + ValidMtrrAddressMask = 0x1000000000ULL; + + AsmCpuid ( + CPUID_EXTENDED_FUNCTION, + &FeatureInfo.RegEax, + &FeatureInfo.RegEbx, + &FeatureInfo.RegEcx, + &FeatureInfo.RegEdx + ); + if (FeatureInfo.RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) { + AsmCpuid ( + CPUID_VIR_PHY_ADDRESS_SIZE, + &FeatureInfo.RegEax, + &FeatureInfo.RegEbx, + &FeatureInfo.RegEcx, + &FeatureInfo.RegEdx + ); + ValidMtrrAddressMask = (LShiftU64 ((UINT64) 1, FeatureInfo.RegEax & 0xFF) - 1) & (~(UINT64) 0x0FFF); + } + + /// + /// Check for invalid parameter + /// + if ((MemoryAddress &~ValidMtrrAddressMask) != 0 || (MemoryLength &~ValidMtrrAddressMask) != 0) { + return EFI_INVALID_PARAMETER; + } + + switch (MemoryCacheType) { + case EfiCacheTypeUncacheable: + case EfiCacheTypeWriteCombining: + case EfiCacheTypeWriteThrough: + case EfiCacheTypeWriteProtected: + case EfiCacheTypeWriteBack: + break; + + default: + return EFI_INVALID_PARAMETER; + } + + /// + /// Check if Fixed MTRR + /// + if ((MemoryAddress + MemoryLength) <= (1 << 20)) { + Status = PeiProgramLowMemoryMtrr ( + This, + MemoryCacheType, + (UINT32) MemoryAddress, + (UINT32) (MemoryAddress + MemoryLength) + ); + return Status; + } + + /// + /// Special case for 1 MB base address + /// + if (MemoryAddress == 0x100000) { + MemoryAddress = 0; + MemoryLength += 0x100000; + } + + /// + /// Split MemoryLength into a sum of power of 2 + /// + ZeroMem (Power2Length, sizeof (Power2Length)); + LengthSize = 0; + TempQword = MemoryLength; + do { + Power2Length[LengthSize] = PeiPower2MaxMemory (TempQword); + TempQword -= Power2Length[LengthSize]; + LengthSize++; + } while (TempQword != 0 && LengthSize < 8); + if (TempQword != 0) { + return EFI_LOAD_ERROR; + } + + /// + /// Work out an order of splitted power of 2 + /// so that Base and Length are suitable for MTRR + /// setting constraints. + /// + Count = 0; + TempQword = MemoryAddress; + do { + for (Index = 0; Index < LengthSize; Index++) { + Power2LengthPointer = (UINT32 *) &Power2Length[Index]; + if (Power2Length[Index] != 0) { + if (Power2LengthPointer[1] != 0) { + Remainder = (UINT32) TempQword; + if (Remainder == 0) { + DivU64x32Remainder ( + TempQwordPointer[1], + Power2LengthPointer[1], + &Remainder + ); + } + } else { + DivU64x32Remainder (TempQword, (UINT32) Power2Length[Index], &Remainder); + } + + if (Remainder == 0) { + LengthArray[Count] = Power2Length[Index]; + TempQword += Power2Length[Index]; + Power2Length[Index] = 0; + Count++; + break; + } + } + } + + if (Index == LengthSize) { + return EFI_LOAD_ERROR; + } + } while (Count < LengthSize); + /// + /// Begin setting the MTRR according to the order + /// + for (Index = 0; Index < LengthSize; Index++, MemoryAddress += MemoryLength) { + MemoryLength = LengthArray[Index]; + /// + /// Search if the range attribute has been set before + /// + Status = SearchForExactMtrr ( + PeiServices, + This, + MemoryAddress, + MemoryLength, + ValidMtrrAddressMask, + &UsedMsrNum, + &UsedMemoryCacheType + ); + + if (!EFI_ERROR (Status)) { + /// + /// Compare if it has the same type as current setting + /// + if (UsedMemoryCacheType != MemoryCacheType) { + /// + /// Different type + /// + /// + /// Check if the set type is the same as default type + /// + if (IsDefaultType (MemoryCacheType)) { + /// + /// Clear the mtrr + /// + WriteMsrToBuffer (This, UsedMsrNum, 0); + WriteMsrToBuffer (This, UsedMsrNum + 1, 0); + + } else { + /// + /// Modify the mtrr type + /// + EfiProgramMtrr ( + This, + UsedMsrNum, + MemoryAddress, + MemoryLength, + MemoryCacheType, + ValidMtrrAddressMask + ); + } + } + + continue; + } + + /// + /// Find first unused MTRR + /// + for (MsrNum = CACHE_VARIABLE_MTRR_BASE; MsrNum < (CACHE_VARIABLE_MTRR_BASE + VariableMtrrLimit * 2); MsrNum += 2) { + if (ReadMsrFromBuffer (This, MsrNum + 1) == 0) { + break; + } + } + /// + /// Check if we ran out of variable-range MTRRs + /// + if (MsrNum >= (CACHE_VARIABLE_MTRR_BASE + VariableMtrrLimit * 2)) { + return EFI_LOAD_ERROR; + } + + EfiProgramMtrr ( + This, + MsrNum, + MemoryAddress, + MemoryLength, + MemoryCacheType, + ValidMtrrAddressMask + ); + } + + return EFI_SUCCESS; +} + +/** + Update MTRR setting from buffer to MSR. Disable NEM when NEM is not disabled yet. + + @param[in] PeiServices - General purpose services available to every PEIM. + @param[in] This - Current instance of Pei Cache PPI. + + @retval EFI_SUCCESS - Mtrr are set successfully. +**/ +EFI_STATUS +EFIAPI +PeiActivateCache ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CACHE_PPI *This + ) +{ + UINT32 VariableMtrrLimit; + UINT32 MsrNum; + UINT64 OldMtrr; + UINT16 Index; + CACHE_PPI_INSTANCE *CachePpiInstance; + CachePpiInstance = PEI_CACHE_PPI_INSTANCE_FROM_THIS (This); + + VariableMtrrLimit = (UINT32) (AsmReadMsr64 (IA32_MTRR_CAP) & B_IA32_MTRR_VARIABLE_SUPPORT); + if (VariableMtrrLimit > V_MAXIMUM_VARIABLE_MTRR_NUMBER) { + VariableMtrrLimit = V_MAXIMUM_VARIABLE_MTRR_NUMBER; + } + + /// + /// Disable NEM when NEM is not disabled yet + /// + if (!CachePpiInstance->NemDisabledDone) { + DisableCacheAsRam (); + CachePpiInstance->NemDisabledDone = TRUE; + } + + /// + /// Disable/Enable cache only when MTRR configuration is changed in MTRR buffer + /// + if (CachePpiInstance->FixedMtrrChanged || CachePpiInstance->VariableMtrrChanged) { + EfiDisableCacheMtrr (&OldMtrr); + if (CachePpiInstance->FixedMtrrChanged) { + for (Index = 0; Index < V_FIXED_MTRR_NUMBER; Index++) { + if (CachePpiInstance->FixedMtrrValue[Index].Changed) { + AsmWriteMsr64 (mFixedMtrrTable[Index].Msr, CachePpiInstance->FixedMtrrValue[Index].MsrValue); + CachePpiInstance->FixedMtrrValue[Index].Changed = FALSE; + } + } + + CachePpiInstance->FixedMtrrChanged = FALSE; + } + + if (CachePpiInstance->VariableMtrrChanged) { + for (MsrNum = CACHE_VARIABLE_MTRR_BASE; MsrNum < (CACHE_VARIABLE_MTRR_BASE + VariableMtrrLimit * 2); MsrNum++) { + if (CachePpiInstance->VariableMtrrValue[MsrNum - CACHE_VARIABLE_MTRR_BASE].Changed) { + AsmWriteMsr64 (MsrNum, CachePpiInstance->VariableMtrrValue[MsrNum - CACHE_VARIABLE_MTRR_BASE].MsrValue); + CachePpiInstance->VariableMtrrValue[MsrNum - CACHE_VARIABLE_MTRR_BASE].Changed = FALSE; + } + + CachePpiInstance->VariableMtrrChanged = FALSE; + } + } + + EfiRecoverCacheMtrr (TRUE, OldMtrr); + } + + return EFI_SUCCESS; +} + +/** + Reset all the MTRRs to a known state. + + @param[in] PeiServices - General purpose services available to every PEIM. + @param[in] This - Pointer to the instance of the PEI_CACHE_PPI. + + @retval EFI_SUCCESS - All MTRRs have been reset successfully. +**/ +EFI_STATUS +EFIAPI +PeiResetCacheAttributes ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CACHE_PPI *This + ) +{ + UINT32 MsrNum; + UINT16 Index; + UINT32 VariableMtrrLimit; + + VariableMtrrLimit = (UINT32) (AsmReadMsr64 (IA32_MTRR_CAP) & B_IA32_MTRR_VARIABLE_SUPPORT); + if (VariableMtrrLimit > V_MAXIMUM_VARIABLE_MTRR_NUMBER) { + VariableMtrrLimit = V_MAXIMUM_VARIABLE_MTRR_NUMBER; + } + + Index = 0; + + /// + /// Reset Fixed Mtrrs + /// + while (mFixedMtrrTable[Index].Msr != 0) { + WriteMsrToBuffer (This, Index, 0); + Index++; + } + + /// + /// Reset Variable Mtrrs + /// + for (MsrNum = CACHE_VARIABLE_MTRR_BASE; MsrNum < (CACHE_VARIABLE_MTRR_BASE + VariableMtrrLimit * 2); MsrNum++) { + WriteMsrToBuffer (This, MsrNum, 0); + } + + return EFI_SUCCESS; +} + +/** + Search the memory cache type for specific memory from MTRR. + + @param[in] PeiServices - General purpose services available to every PEIM. + @param[in] This - Current instance of Pei Cache PPI. + @param[in] MemoryAddress - the address of target memory + @param[in] MemoryLength - the length of target memory + @param[in] ValidMtrrAddressMask - the MTRR address mask + @param[in] UsedMsrNum - the used MSR number + @param[in] UsedMemoryCacheType - the cache type for the target memory + + @retval EFI_SUCCESS - The memory is found in MTRR and cache type is returned + @retval EFI_NOT_FOUND - The memory is not found in MTRR +**/ +EFI_STATUS +SearchForExactMtrr ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CACHE_PPI *This, + IN EFI_PHYSICAL_ADDRESS MemoryAddress, + IN UINT64 MemoryLength, + IN UINT64 ValidMtrrAddressMask, + OUT UINT32 *UsedMsrNum, + OUT EFI_MEMORY_CACHE_TYPE *UsedMemoryCacheType + ) +{ + UINT32 MsrNum; + UINT64 TempQword; + UINT32 VariableMtrrLimit; + + VariableMtrrLimit = (UINT32) (AsmReadMsr64 (IA32_MTRR_CAP) & B_IA32_MTRR_VARIABLE_SUPPORT); + if (VariableMtrrLimit > V_MAXIMUM_VARIABLE_MTRR_NUMBER) { + VariableMtrrLimit = V_MAXIMUM_VARIABLE_MTRR_NUMBER; + } + + for (MsrNum = CACHE_VARIABLE_MTRR_BASE; MsrNum < (CACHE_VARIABLE_MTRR_BASE + VariableMtrrLimit * 2 - 1); MsrNum += 2) { + + TempQword = ReadMsrFromBuffer (This, MsrNum + 1); + + if ((TempQword & B_CACHE_MTRR_VALID) == 0) { + continue; + } + + if ((TempQword & ValidMtrrAddressMask) != ((~(MemoryLength - 1)) & ValidMtrrAddressMask)) { + continue; + } + + TempQword = ReadMsrFromBuffer (This, MsrNum); + + if ((TempQword & ValidMtrrAddressMask) != (MemoryAddress & ValidMtrrAddressMask)) { + continue; + } + + *UsedMemoryCacheType = (EFI_MEMORY_CACHE_TYPE) (TempQword & 0xFF); + *UsedMsrNum = MsrNum; + + return EFI_SUCCESS; + + } + + return EFI_NOT_FOUND; +} + +/** + Compares provided Cache type to default type + + @param[in] MemoryCacheType - Memory type for testing + + @retval TRUE - Memory type instance is the default type + @retval FALSE - Memory type instance is not the default type +**/ +BOOLEAN +IsDefaultType ( + IN EFI_MEMORY_CACHE_TYPE MemoryCacheType + ) +{ + + if ((AsmReadMsr64 (CACHE_IA32_MTRR_DEF_TYPE) & 0xFF) != MemoryCacheType) { + return FALSE; + } else { + return TRUE; + } +} + +/** + Install CacheInitPpi + + @retval EFI_OUT_OF_RESOURCES - failed to allocate required pool +**/ +EFI_STATUS +CacheInitPpiInit ( + VOID + ) +{ + EFI_STATUS Status; + CACHE_PPI_INSTANCE *CachePpiInstance; + + CachePpiInstance = AllocateZeroPool (sizeof (CACHE_PPI_INSTANCE)); + ASSERT (CachePpiInstance != NULL); + if (CachePpiInstance == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + CachePpiInstance->Ppi.SetCache = PeiSetCacheAttributes; + CachePpiInstance->Ppi.ResetCache = PeiResetCacheAttributes; + CachePpiInstance->Ppi.ActivateCache = PeiActivateCache; + + CachePpiInstance->PpiDesc.Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + CachePpiInstance->PpiDesc.Guid = &gPeiCachePpiGuid; + CachePpiInstance->PpiDesc.Ppi = &CachePpiInstance->Ppi; + + /// + /// Install PPI + /// + Status = PeiServicesInstallPpi (&CachePpiInstance->PpiDesc); + ASSERT_EFI_ERROR (Status); + return Status; +} + +VOID +CacheInvd ( + VOID + ); + +/** + Disable NEM (cache-as-ram) + + @retval EFI_SUCCESS - always return success +**/ +EFI_STATUS +DisableCacheAsRam ( + VOID + ) +{ + UINT64 CacheAsRamMsr; + UINT64 McStatus; + UINT32 McIndex; + UINT32 McCounter; + UINT64 TempQword; + UINT64 OldMtrr; + + CacheAsRamMsr = AsmReadMsr64 (NO_EVICT_MODE); + + /// + /// Check if CAR has already been disabled. We should not + /// execute CacheInvd() after cache has been enabled. This + /// check will avoid that. + /// + if ((CacheAsRamMsr & B_NO_EVICT_MODE_RUN) == 0) { + return EFI_SUCCESS; + } + + CacheInvd (); + + /// + /// Step 3: Disable No-Eviction Mode Run State by clearing + /// NO_EVICT_MODE MSR 2E0h bit [1] = 0 + /// + CacheAsRamMsr &= ~B_NO_EVICT_MODE_RUN; + AsmWriteMsr64 (NO_EVICT_MODE, CacheAsRamMsr); + + /// + /// Step 4: Disable No-Eviction Mode Setup State by clearing + /// NO_EVICT_MODE MSR 2E0h bit [0] = 0 + /// + CacheAsRamMsr &= ~B_NO_EVICT_MODE_SETUP; + AsmWriteMsr64 (NO_EVICT_MODE, CacheAsRamMsr); + + /// + /// Disable Cache MTRR by cleaning IA32_MTRR_DEF_TYPE.E or IA32_MTRR_DEF_TYPE.GE + /// + OldMtrr = AsmReadMsr64 (CACHE_IA32_MTRR_DEF_TYPE); + TempQword = OldMtrr &~B_CACHE_MTRR_VALID; + AsmWriteMsr64 (CACHE_IA32_MTRR_DEF_TYPE, TempQword); + + /// + /// After NEM is disabled, BIOS must clear any Machine Check Bank 5-8 errors that may + /// have occurred as the result of ... MLC to to LLC Evictions. + /// + McStatus = 0; + McCounter = (UINT32) (AsmReadMsr64 (IA32_MCG_CAP) & 0x0f); + for (McIndex = 5; McIndex < McCounter; McIndex++) { + if (McIndex <= 8) { + AsmWriteMsr64 (IA32_MC0_STATUS + McIndex * 4, McStatus); + } + } + + return EFI_SUCCESS; +} diff --git a/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPei.cif b/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPei.cif new file mode 100644 index 0000000..f69c12f --- /dev/null +++ b/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPei.cif @@ -0,0 +1,20 @@ +<component> + name = "CpuInitPei" + category = ModulePart + LocalRoot = "ReferenceCode\Haswell\CpuInit\Pei" + RefName = "CpuInitPei" +[files] +"CpuInitPeim.c" +"CachePeim.c" +"CpuInitPeim.h" +"PfatInit.c" +"PfatInit.h" +"CpuOcInit.c" +"CpuOcInit.h" +"CpuInitPeim.dxs" +"CpuInitPeim.inf" +"CpuInitPei.mak" +"CpuInitPei.sdl" +"Ia32\Cpu.asm" +"BootGuardInit.c" +<endComponent> diff --git a/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPei.mak b/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPei.mak new file mode 100644 index 0000000..7258a7c --- /dev/null +++ b/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPei.mak @@ -0,0 +1,76 @@ +# MAK file for the eModule:PowerManagement + +EDK : CpuInitPei + +BUILD_CpuInitPei_DIR = $(BUILD_DIR)\$(CpuInitPei_DIR) + +$(BUILD_DIR)\CpuInitPei.mak : $(CpuInitPei_DIR)\CpuInitPei.cif $(BUILD_RULES) + $(CIF2MAK) $(CpuInitPei_DIR)\CpuInitPei.cif $(CIF2MAK_DEFAULTS) + +CpuInitPei : $(BUILD_DIR)\CpuInitPei.MAK CpuInitPeiBin + +CpuInitPei_OBJECTS = \ + $(BUILD_CpuInitPei_DIR)\CpuInitPeim.obj \ + $(BUILD_CpuInitPei_DIR)\CachePeim.obj \ + $(BUILD_CpuInitPei_DIR)\CpuOcInit.obj \ + $(BUILD_CpuInitPei_DIR)\PfatInit.obj \ + $(BUILD_CpuInitPei_DIR)\ia32\Cpu.obj \ + $(BUILD_CpuInitPei_DIR)\BootGuardInit.obj + +CpuInitPei_MY_INCLUDES= \ + $(EDK_INCLUDES)\ + $(PROJECT_CPU_INCLUDES)\ + $(INTEL_MCH_INCLUDES)\ + $(ME_INCLUDES)\ + $(INTEL_PCH_INCLUDES) + +CpuInitPei_DEFINES = $(MY_DEFINES)\ + /D"__EDKII_GLUE_MODULE_ENTRY_POINT__=PeimInitializeCpu"\ + /D __EDKII_GLUE_BASE_LIB__ \ + /D __EDKII_GLUE_PEI_MEMORY_ALLOCATION_LIB__ \ + /D __EDKII_GLUE_BASE_PCI_LIB_PCI_EXPRESS__ \ + /D __EDKII_GLUE_PEI_SERVICES_TABLE_POINTER_LIB_MM7__ \ + +CpuInitPei_LIBS =\ + $(CPU_PPI_LIB)\ + $(CPUIA32LIB)\ + $(EdkIIGluePeiServicesLib_LIB) \ + $(EdkIIGluePeiReportStatusCodeLib_LIB) \ + $(EfiRuntimeLib_LIB)\ + $(INTEL_PCH_PROTOCOL_LIB)\ + $(EFIRUNTIMELIB)\ + $(EDKFRAMEWORKPPILIB) \ + $(EdkIIGluePeiMemoryAllocationLib_LIB)\ + $(EdkIIGluePeiDebugLibReportStatusCode_LIB)\ + $(BUILD_DIR)\IA32\EdkIIGlueBaseLib.lib\ + $(IntelPchPpiLib_LIB)\ + $(EdkIIGlueBaseLibIA32_LIB)\ + $(EdkIIGluePeiHobLib_LIB) \ + $(CpuGuidLib_LIB) \ + $(PEIHOBLIB) \ + $(EdkIIGlueBaseIoLibIntrinsic_LIB)\ + $(EdkIIGlueBasePciLibPciExpress_LIB) \ + $(EdkIIGlueBasePciExpressLib_LIB)\ + $(PchPlatformPeiLib_LIB)\ + $(CpuPlatformLib_LIB)\ + $(OcPlatformLib_LIB)\ + $(MeLibPpi_LIB)\ + $(BootGuardLib_LIB)\ + $(EFISCRIPTLIB) + +CpuInitPeiBin : $(CpuInitPei_LIBS) $(HeciPei_LIBS) + $(MAKE) /$(MAKEFLAGS) $(EDKIIGLUE_DEFAULTS)\ + /f $(BUILD_DIR)\CpuInitPei.mak all\ + NAME=CpuInitPei\ + MAKEFILE=$(BUILD_DIR)\CpuInitPei.mak \ + "MY_INCLUDES=$(CpuInitPei_MY_INCLUDES)" \ + "MY_DEFINES=$(CpuInitPei_DEFINES)"\ + OBJECTS="$(CpuInitPei_OBJECTS)" \ + GUID=01359D99-9446-456d-ADA4-50A711C03ADA\ + ENTRY_POINT=_ModuleEntryPoint \ + TYPE=PEIM \ + EDKIIModule=PEIM\ + DEPEX1=$(CpuInitPei_DIR)\CpuInitPeim.DXS \ + DEPEX1_TYPE=EFI_SECTION_PEI_DEPEX \ + COMPRESS=0 +#----------------------------------------------------------------------- diff --git a/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPei.sdl b/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPei.sdl new file mode 100644 index 0000000..a1abd10 --- /dev/null +++ b/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPei.sdl @@ -0,0 +1,37 @@ +TOKEN + Name = "CpuInitPei_SUPPORT" + Value = "1" + Help = "Main switch to enable Cpu Pei init support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Master = Yes +End + +PATH + Name = "CpuInitPei_DIR" +End + +MODULE + Help = "Includes CpuInitPei.mak to Project" + File = "CpuInitPei.mak" +End + +ELINK + Name = "CpuInitPei_INCLUDES" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "/I$(CpuInitPei_DIR)" + Parent = "CpuInitPei_INCLUDES" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(BUILD_DIR)\CpuInitPei.ffs" + Parent = "FV_BB" + InvokeOrder = AfterParent +End + diff --git a/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPeim.c b/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPeim.c new file mode 100644 index 0000000..739e043 --- /dev/null +++ b/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPeim.c @@ -0,0 +1,1404 @@ +/** @file + EFI 2.0 PEIM to initialize the cache and program for unlock processor + +Revision History + +@copyright + Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Pre-EFI Module' and is licensed + for Intel CPUs and Chipsets under the terms of your license + agreement with Intel or your vendor. This file may be + modified by the user, subject to additional terms of the + license agreement + +**/ + +/// +/// External include files do NOT need to be explicitly specified in real EDKII +/// environment +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGluePeim.h" +#include "CpuAccess.h" +#include "CpuInitPeim.h" +#include "PchAccess.h" +#include "SaAccess.h" +#include "PfatInit.h" +#include "CpuOcInit.h" +#include "CpuPlatformLib.h" + +#include EFI_PPI_DEFINITION (BootMode) +#include EFI_PPI_DEFINITION (PchInit) +#include EFI_PPI_CONSUMER (PchReset) +#endif + +#include EFI_PPI_CONSUMER (SecPlatformInformation) +#include EFI_GUID_DEFINITION (HtBistHob) + +/** + This fuction compare Setup Options of ActiveCores & HyperThreading against the CPU Strap + and in case of mismatch requests reset + + @param[in] PeiServices - For printouts + @param[in] CpuStrapSet - Strap current setting + @param[in] CpuPlatformPolicyPpi - Platform Policy PPI + + @retval CPU_RESET_TYPE + @retval CPU_ONLY_RESET - if reset is needed + @retval NO_RESET - otherwise +**/ +CPU_RESET_TYPE +SetActiveCoresAndSmtEnableDisable ( + IN EFI_PEI_SERVICES **PeiServices, + IN CPU_STRAP_SET *CpuStrapSet, + IN PEI_CPU_PLATFORM_POLICY_PPI *CpuPlatformPolicyPpi + ) +{ + CPU_RESET_TYPE ResetType; + UINT16 TotalThreadsPerCore; + UINT32 Data32; + UINT32 NumberOfActiveCores; + UINT32 NumberOfActiveThreads; + EFI_CPUID_REGISTER Cpuid0B = { 0, 0, 0, 0 }; + + ResetType = NO_RESET; + + /// + /// Read CPUID(0xB) with ECX=0 for number of logical processors per Core. + /// This value does NOT change based on Intel HT Technology disable and core disables. + /// + Cpuid0B.RegEcx = 0; + AsmCpuidEx (CPUID_PROCESSOR_TOPOLOGY, 0, NULL, &Cpuid0B.RegEbx, NULL, NULL); + TotalThreadsPerCore = (UINT16) Cpuid0B.RegEbx; + + /// + /// CORE_THREAD_COUNT - msr 0x35 + /// Symbol Name MSB:LSB Description + /// CoreCount CoreCount 31:16 The Core Count reflects the enabled cores based + /// on the above thread count and the value of threads_ + /// available (to determine if HT is on) at reset time. + /// + /// ThreadCount ThreadCount 15:0 The Thread Count reflects the enabled threads based + /// on the factory-configured thread count and the value + /// of the CSR_DESIRED_CORES register at reset time. + /// + /// + /// Read MSR for Active Core and Thread Count. + /// + Data32 = (UINT32) AsmReadMsr64 (MSR_CORE_THREAD_COUNT); + NumberOfActiveCores = (UINT32) ((Data32 >> 16) & 0xFFFF); + NumberOfActiveThreads = (UINT32) (Data32 & 0xFFFF); + + DEBUG ((EFI_D_INFO, "Number of Active Cores / Threads = %x / %x\n", NumberOfActiveCores, NumberOfActiveThreads)); + + if (TotalThreadsPerCore > 1) { + /// + /// SMT is supported + /// + DEBUG ((EFI_D_INFO, "SMT is supported\n")); + /// + /// Check if the configuration of SMT matches the BIOS Setup option. + /// + if (CpuStrapSet->HtDisabled == CpuPlatformPolicyPpi->CpuConfig->HyperThreading) { + /// + /// SMT configuration doesn't match BIOS Setup option; update the Strap Set Data and Issue a Warm reset + /// + DEBUG ((EFI_D_INFO, "SMT configuration doesn't match the setup value\n")); + CpuStrapSet->HtDisabled = !CpuPlatformPolicyPpi->CpuConfig->HyperThreading; + ResetType |= WARM_RESET; + } + } else { + /// + /// SMT is not supported by default fusing. + /// + DEBUG ((EFI_D_WARN, "SMT is NOT supported\n")); + CpuStrapSet->HtDisabled = 1; + CpuPlatformPolicyPpi->CpuConfig->HyperThreading = CPU_FEATURE_DISABLE; + } + /// + /// Check if the configuration of "Active Core" matches the BIOS Setup option. + /// + if (CpuStrapSet->NumberOfActiveCores != CpuPlatformPolicyPpi->CpuConfig->ActiveCoreCount) { + DEBUG ( + (EFI_D_INFO, + "NumberOfActiveCores doesn't match the value from Setup = %x / %x\n", + CpuStrapSet->NumberOfActiveCores, + CpuPlatformPolicyPpi->CpuConfig->ActiveCoreCount) + ); + CpuStrapSet->NumberOfActiveCores = CpuPlatformPolicyPpi->CpuConfig->ActiveCoreCount; + /// + /// Haswell CPU doesnt require COLD reset to set number of active cores + /// + ResetType |= WARM_RESET; + } + + return ResetType; +} + +/** + This fuction compare Setup Options of BIST against the CPU Strap + and in case of mismatch requests reset + + @param[in] PeiServices - For printouts + @param[in] CpuStrapSet - Strap current setting + @param[in] CpuPlatformPolicyPpi - Platform Policy PPI + + @retval CPU_RESET_TYPE + @retval CPU_ONLY_RESET - if reset is needed + @retval NO_RESET - otherwise +**/ +CPU_RESET_TYPE +BistEnableDisable ( + IN EFI_PEI_SERVICES **PeiServices, + IN CPU_STRAP_SET *CpuStrapSet, + IN PEI_CPU_PLATFORM_POLICY_PPI *CpuPlatformPolicyPpi + ) +{ + if (CpuStrapSet->Bist == CpuPlatformPolicyPpi->CpuConfig->BistOnReset) { + return NO_RESET; + } else { + CpuStrapSet->Bist = CpuPlatformPolicyPpi->CpuConfig->BistOnReset; + DEBUG ((EFI_D_INFO, "BIST configuration doesn't match the setup value\n")); + return WARM_RESET; + } +} + +/** + This fuction compare Setup Options of Processor Flex Multiplier against the CPU Strap + and in case of mismatch requests reset + + @param[in] PeiServices - For printouts + @param[in] CpuStrapSet - Strap current setting + @param[in] CpuPlatformPolicyPpi - Platform Policy PPI + + @retval CPU_RESET_TYPE + @retval CPU_ONLY_RESET - if reset is needed + @retval NO_RESET - otherwise +**/ +CPU_RESET_TYPE +ProgramProcessorFlexMultiplier ( + IN EFI_PEI_SERVICES **PeiServices, + IN CPU_STRAP_SET *CpuStrapSet, + IN PEI_CPU_PLATFORM_POLICY_PPI *CpuPlatformPolicyPpi + ) +{ + UINT64 FlexRatioData; + UINT64 CurrentClockFlexRatio; + UINT64 MsrData; + CPU_RESET_TYPE ResetType; + + ResetType = NO_RESET; + + /// + /// Perform Flex Ratio if enabled by user in Setup screen + /// + if (CpuPlatformPolicyPpi->CpuConfig->CpuRatioOverride) { + FlexRatioData = (UINT64) (CpuPlatformPolicyPpi->CpuConfig->CpuRatio); + } else { + /// + /// Flex Ratio was set to disable. Reset to Max Non-Turbo Ratio + /// + FlexRatioData = 0x0; + } + DEBUG ((EFI_D_INFO, "Setup Ratio is 0x%X\n", FlexRatioData)); + + /// + /// Read and save current Flex Ratio data; disregard enable bit (MSR 194h [15:8]) + /// + MsrData = AsmReadMsr64 (MSR_FLEX_RATIO); + CurrentClockFlexRatio = ((RShiftU64 (MsrData, N_FLEX_RATIO)) & 0xFF); + DEBUG ((EFI_D_INFO, "Current Flex Ratio from MSR is 0x%X\n", CurrentClockFlexRatio)); + DEBUG ((EFI_D_INFO, "Current Flex Ratio from CPU Strap: 0x%X\n", CpuStrapSet->FlexRatio)); + /// + /// Check and set Flex Ratio to requested ratio if possible + /// + if (FlexRatioData == CpuStrapSet->FlexRatio) { + /// + /// Do nothing, ratio is already set to requested value and enabled + /// + DEBUG ((EFI_D_INFO, "No need to set Flex Ratio.\n")); + } else { + /// + /// Set Flex Ratio to user selected value + /// + /// Write new data to Flex Ratio register + /// First clear MSR of any previous value + /// + MsrData &= RATIO_FLEX_CLEAR_MASK; + + /// + /// Enter the new data + /// + MsrData |= (LShiftU64 ((FlexRatioData & 0xFF), N_FLEX_RATIO)); + MsrData |= B_FLEX_EN; + AsmWriteMsr64 (MSR_FLEX_RATIO, MsrData); + + /// + /// Set Soft Reset Data for Flex Ratio + /// + CpuStrapSet->FlexRatio = (UINT32) FlexRatioData; + + /// + /// Set RESET flag + /// + DEBUG ((EFI_D_INFO, "Setting Flex Ratio to 0x%X\n", CpuStrapSet->FlexRatio)); + ResetType |= WARM_RESET; + } + + return ResetType; +} + +static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = { + { + EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK, + &gPchInitPpiGuid, + SetCpuStrap + }, + { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiMasterBootModePpiGuid, + BuildBistHob + } +}; + +/** + Check if VT is fused and disabled by Setup Option so reset is needed + + @param[in] CpuPlatformPolicyPpi - Platform Policy PPI + + @retval CPU_RESET_TYPE + @retval NO_RESET - If no reset is needed + @retval COLDRESET - otherwise +**/ +CPU_RESET_TYPE +CheckVmxIfNeedReset ( + IN PEI_CPU_PLATFORM_POLICY_PPI *CpuPlatformPolicyPpi + ) +{ + UINT64 MsrIa32FeatureControl; + BOOLEAN CurrentVmxState; + EFI_CPUID_REGISTER Cpuid01 = { 0, 0, 0, 0 }; + + AsmCpuid (CPUID_VERSION_INFO, &Cpuid01.RegEax, &Cpuid01.RegEbx, &Cpuid01.RegEcx, &Cpuid01.RegEdx); + + /// + /// Check if VMX is supported + /// + if ((Cpuid01.RegEcx & B_CPUID_VERSION_INFO_ECX_VME) == 0) { + return NO_RESET; + } + + MsrIa32FeatureControl = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL); + + /// + /// If unlocked, no reset needed. + /// + if ((MsrIa32FeatureControl & B_MSR_IA32_FEATURE_CONTROL_LOCK) == 0) { + return NO_RESET; + } + + CurrentVmxState = (BOOLEAN) ((MsrIa32FeatureControl & B_MSR_IA32_FEATURE_CONTROL_EVT) != 0); + + /// + /// Need to reset only if locked and VMX state has to be changed. + /// + if ((CurrentVmxState == (CpuPlatformPolicyPpi->CpuConfig->VmxEnable)) == CPU_FEATURE_ENABLE) { + return NO_RESET; + } + /// + /// We need a power good reset to unlock MSR_IA32_FEATURE_CONTROL. + /// + return COLDRESET; +} + +/** + Set CPU strap setting for feature change + + @param[in] PeiServices - Indirect reference to the PEI Services Table. + @param[in] NotifyDescriptor - Address of the notification descriptor data structure. Type + EFI_PEI_NOTIFY_DESCRIPTOR is defined above. + @param[in] Ppi - Address of the PPI that was installed. + + @retval EFI_SUCCESS - Function completed successfully +**/ +EFI_STATUS +EFIAPI +SetCpuStrap ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + CPU_STRAP_SET CpuStrapSet = { 0 }; + UINT16 CpuStrapSetData; + volatile CPU_RESET_TYPE ResetType; + PCH_INIT_PPI *PchInitPpi; + PEI_CPU_PLATFORM_POLICY_PPI *CpuPlatformPolicyPpi; + UINT8 Data; + + ResetType = NO_RESET; + CpuStrapSetData = 0; + Data = 0; + + Status = PeiServicesLocatePpi ( + &gPeiCpuPlatformPolicyPpiGuid, + 0, + NULL, + (VOID **) &CpuPlatformPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Locate PchInit Ppi + /// + Status = PeiServicesLocatePpi ( + &gPchInitPpiGuid, + 0, + NULL, + (VOID **) &PchInitPpi + ); + if (Status == EFI_SUCCESS) { + /// + /// Get Cpu Strap Set Data + /// + DEBUG ((EFI_D_INFO, "Set PCH CPU Straps \n")); + Status = PchInitPpi->CpuStrapSet (PeiServices, GetCpuStrapSetData, &CpuStrapSetData); + *((UINT16 *) (&CpuStrapSet)) = CpuStrapSetData; + DEBUG ((EFI_D_INFO, "Current CPU Strap Data = 0x%04X\n", CpuStrapSetData)); + + if (Status == EFI_SUCCESS) { + ResetType |= SetActiveCoresAndSmtEnableDisable (PeiServices, &CpuStrapSet, CpuPlatformPolicyPpi); + ResetType |= BistEnableDisable (PeiServices, &CpuStrapSet, CpuPlatformPolicyPpi); + + /// + /// Perform Flex Ratio if processor is fused to perform Flex Ratio + /// + if ((AsmReadMsr64 (MSR_FLEX_RATIO) & B_FLEX_EN) == B_FLEX_EN) { + ResetType |= ProgramProcessorFlexMultiplier (PeiServices, &CpuStrapSet, CpuPlatformPolicyPpi); + } + + if (ResetType != NO_RESET) { + CpuStrapSetData = *((UINT16 *) (&CpuStrapSet)); + DEBUG ((EFI_D_INFO, "New CPU Strap Data = 0x%04X\n", CpuStrapSetData)); + Status = PchInitPpi->CpuStrapSet ( + PeiServices, + SetCpuStrapSetData, + &CpuStrapSetData + ); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_INFO, "NO Reset\n")); + ResetType = NO_RESET; + } + } + } + } + + ResetType |= CheckVmxIfNeedReset (CpuPlatformPolicyPpi); + + if (ResetType != NO_RESET) { + /// + /// Perform Warm or Cold Reset + /// + DEBUG ( + (EFI_D_INFO, + "Reset Required. Performing Cold/Warm Reset to read the new strap values - ResetType = %x\n", + ResetType) + ); + PerformWarmORColdReset (PeiServices, ResetType); + } + + Status = PchInitPpi->CpuStrapSet ( + PeiServices, + LockCpuStrapSetData, + &CpuStrapSetData + ); + DEBUG ((EFI_D_INFO, "No Reset Required\n")); + + return EFI_SUCCESS; +} + +/** + Initialize prefetcher settings + + @param[in] MlcStreamerprefecterEnabled - Enable/Disable MLC streamer prefetcher + @param[in] MlcSpatialPrefetcherEnabled - Enable/Disable MLC spatial prefetcher +**/ +VOID +ProcessorsPrefetcherInitialization ( + IN UINTN MlcStreamerprefecterEnabled, + IN UINTN MlcSpatialPrefetcherEnabled + ) +{ + UINT64 MsrValue; + MsrValue = AsmReadMsr64 (MISC_FEATURE_CONTROL); + + if (MlcStreamerprefecterEnabled == CPU_FEATURE_DISABLE) { + MsrValue |= B_MISC_FEATURE_CONTROL_MLC_STRP; + } + + if (MlcSpatialPrefetcherEnabled == CPU_FEATURE_DISABLE) { + MsrValue |= B_MISC_FEATURE_CONTROL_MLC_SPAP; + } + + if ((MsrValue & (B_MISC_FEATURE_CONTROL_MLC_STRP | B_MISC_FEATURE_CONTROL_MLC_SPAP)) != 0) { + AsmWriteMsr64 (MISC_FEATURE_CONTROL, MsrValue); + } + + return; +} + +/** + Based on ResetType, perform warm or cold reset using PCH Reset PPI + + @param[in] PeiServices - Indirect reference to the PEI Services Table. + @param[in] ResetType - CPU_RESET_TYPE to indicate which reset shoudl be performed. + + @exception EFI_UNSUPPORTED - Reset type unsupported + @retval EFI_SUCCESS - function successfully (system should already reset) +**/ +EFI_STATUS +PerformWarmORColdReset ( + IN EFI_PEI_SERVICES **PeiServices, + IN CPU_RESET_TYPE ResetType + ) +{ + PCH_RESET_PPI *PchResetPpi; + EFI_STATUS Status; + + /// + /// Loccate Reset PPI + /// + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gPchResetPpiGuid, + 0, + NULL, + (VOID **) &PchResetPpi + ); + + ASSERT_EFI_ERROR (Status); + + /// + /// Perfrom the requested reset using PCH reset PPI + /// + Status = EFI_SUCCESS; + switch (ResetType) { + case WARM_RESET: + PchResetPpi->Reset (PchResetPpi, RESET_PPI_WARM_RESET); + break; + + case COLDRESET: + PchResetPpi->Reset (PchResetPpi, RESET_PPI_COLD_RESET); + break; + + default: + DEBUG ((EFI_D_ERROR, "CpuInitPeim: PerformWarmORColdReset - ResetType %d not supported: \n", ResetType)); + Status = EFI_UNSUPPORTED; + ASSERT_EFI_ERROR (Status); + } + + return Status; +} + +/** + Initializes XE OR Overclocking support in the processor. + + @param[in] PowerMgmtConfig Pointer to Policy protocol instance + + @retval EFI_SUCCESS +**/ +EFI_STATUS +XeInit ( + IN OUT POWER_MGMT_CONFIG_PPI *PowerMgmtConfig, + IN OUT OVERCLOCKING_CONFIG_PPI *OcConfig + ) +{ + MSR_REGISTER TurboRatioLimit; + MSR_REGISTER FlexRatioMsr; + MSR_REGISTER TempMsr; + MSR_REGISTER RingRatioMsr; + UINT8 CoreCount; + UINT8 OverclockingBins; + UINT8 OneCoreRatioLimit; + UINT8 TwoCoreRatioLimit; + UINT8 ThreeCoreRatioLimit; + UINT8 FourCoreRatioLimit; + UINT8 RatioLimitProgrammble; + UINT16 MaxBusRatio; + + if ((PowerMgmtConfig->Xe == 0)) { + /// + /// XE is disabled + /// + return EFI_SUCCESS; + } + + TurboRatioLimit.Qword = AsmReadMsr64 (MSR_TURBO_RATIO_LIMIT); + OneCoreRatioLimit = (UINT8) (TurboRatioLimit.Dwords.Low & B_MSR_TURBO_RATIO_LIMIT_1C); + TwoCoreRatioLimit = (UINT8) RShiftU64 ( + (TurboRatioLimit.Dwords.Low & B_MSR_TURBO_RATIO_LIMIT_2C), + N_MSR_TURBO_RATIO_LIMIT_2C + ); + ThreeCoreRatioLimit = (UINT8) RShiftU64 ( + (TurboRatioLimit.Dwords.Low & B_MSR_TURBO_RATIO_LIMIT_3C), + N_MSR_TURBO_RATIO_LIMIT_3C + ); + FourCoreRatioLimit = (UINT8) RShiftU64 ( + (TurboRatioLimit.Dwords.Low & B_MSR_TURBO_RATIO_LIMIT_4C), + N_MSR_TURBO_RATIO_LIMIT_4C + ); + + /// + /// Check if XE capable + /// + FlexRatioMsr.Qword = AsmReadMsr64 (MSR_FLEX_RATIO); + + /// + /// Overclocking availablity + /// + OverclockingBins = (UINT8) RShiftU64 ((FlexRatioMsr.Dwords.Low & B_OVERCLOCKING_BINS), N_OVERCLOCKING_BINS); + + /// + /// Check if Turbo Ratio Limit is programmable + /// Platform Info MSR (0xCE) [28] + /// + TempMsr.Qword = AsmReadMsr64 (MSR_PLATFORM_INFO); + RatioLimitProgrammble = (UINT8) RShiftU64 ( + (TempMsr.Qword & B_PLATFORM_INFO_RATIO_LIMIT), + N_PLATFORM_INFO_RATIO_LIMIT + ); + /// + /// Get Maximum Non-Turbo bus ratio (HFM) from Platform Info MSR Bits[15:8] + /// + MaxBusRatio = TempMsr.Bytes.SecondByte; + + /// + /// Check if processor turbo-ratio can be overriden: + /// BWG Section 14.14.2 + /// If PLATFORM INFO MSR [28] == 1 and FLEX_RATIO MSR [19:17] != 0 + /// Processor with capability to override turbo-ratio detected (either XE or Overclocking part detected) + /// + if ((RatioLimitProgrammble == 0) || (OverclockingBins == 0)) { + /// + /// Neither XE nor Overclocking Capable processor. + /// + DEBUG ((EFI_D_WARN, "WARNING: Trying to configure XE params on a non-XE processor\n")); + return EFI_SUCCESS; + } + /// + /// For Overclocking parts, verify ratio overide is within the allowable limits + /// + if ((RatioLimitProgrammble) && (OverclockingBins < MAX_OVERCLOCKING_BINS)) { + if (PowerMgmtConfig->RatioLimit[0] > (OneCoreRatioLimit + OverclockingBins)) { + PowerMgmtConfig->RatioLimit[0] = OneCoreRatioLimit + OverclockingBins; + } + + if (PowerMgmtConfig->RatioLimit[1] > (TwoCoreRatioLimit + OverclockingBins)) { + PowerMgmtConfig->RatioLimit[1] = TwoCoreRatioLimit + OverclockingBins; + } + + if (PowerMgmtConfig->RatioLimit[2] > (ThreeCoreRatioLimit + OverclockingBins)) { + PowerMgmtConfig->RatioLimit[2] = ThreeCoreRatioLimit + OverclockingBins; + } + + if (PowerMgmtConfig->RatioLimit[3] > (FourCoreRatioLimit + OverclockingBins)) { + PowerMgmtConfig->RatioLimit[3] = FourCoreRatioLimit + OverclockingBins; + } + } + + if ((RatioLimitProgrammble)) { + /// + /// Now initialize turbo ratio limit MSR + /// Find the number of active cores and initialize the ratio limits only if they are available. + /// Also program the VID value for the new max Turbo ratio by programming Flex Ratio MSR. + /// + TempMsr.Qword = AsmReadMsr64 (MSR_CORE_THREAD_COUNT); + CoreCount = (UINT8) RShiftU64 (TempMsr.Dwords.Low, N_CORE_COUNT_OFFSET); + + if (PowerMgmtConfig->RatioLimit[0] >= PowerMgmtConfig->RatioLimit[1] && + PowerMgmtConfig->RatioLimit[0] >= PowerMgmtConfig->RatioLimit[2] && + PowerMgmtConfig->RatioLimit[0] >= PowerMgmtConfig->RatioLimit[3] && + PowerMgmtConfig->RatioLimit[1] >= MaxBusRatio && + PowerMgmtConfig->RatioLimit[2] >= MaxBusRatio && + PowerMgmtConfig->RatioLimit[3] >= MaxBusRatio + ) { + if (CoreCount >= 1) { + TurboRatioLimit.Dwords.Low &= ~B_MSR_TURBO_RATIO_LIMIT_1C; + TurboRatioLimit.Dwords.Low |= PowerMgmtConfig->RatioLimit[0]; + } + + if (CoreCount >= 2) { + TurboRatioLimit.Dwords.Low &= ~B_MSR_TURBO_RATIO_LIMIT_2C; + TurboRatioLimit.Dwords.Low |= LShiftU64 (PowerMgmtConfig->RatioLimit[1], 8); + } + + if (CoreCount >= 3) { + TurboRatioLimit.Dwords.Low &= ~B_MSR_TURBO_RATIO_LIMIT_3C; + TurboRatioLimit.Dwords.Low |= LShiftU64 (PowerMgmtConfig->RatioLimit[2], 16); + } + + if (CoreCount >= 4) { + TurboRatioLimit.Dwords.Low &= ~B_MSR_TURBO_RATIO_LIMIT_4C; + TurboRatioLimit.Dwords.Low |= LShiftU64 (PowerMgmtConfig->RatioLimit[3], 24); + } + + AsmWriteMsr64 (MSR_TURBO_RATIO_LIMIT, TurboRatioLimit.Qword); + } + } + + /// + /// For Overclocking parts, if a non-default ring ratio is specificed, we need to + /// update the ring ratio limit MSR's max limit + /// + if ((OverclockingBins != 0) && (OcConfig->ClrMaxOcTurboRatio != 0)) { + RingRatioMsr.Qword = AsmReadMsr64 (MSR_RING_RATIO_LIMIT); + RingRatioMsr.Bytes.FirstByte &= ~MSR_MAX_RING_RATIO_LIMIT_MASK; + RingRatioMsr.Bytes.FirstByte |= OcConfig->ClrMaxOcTurboRatio & MSR_MAX_RING_RATIO_LIMIT_MASK; + AsmWriteMsr64 (MSR_RING_RATIO_LIMIT, RingRatioMsr.Qword); + } + return EFI_SUCCESS; +} + +/** + Initialize performance and power management features + + @param[in] CpuPlatformPolicyPpi - The CPU Platform Policy PPI instance +**/ +VOID +ProcessorsPerfPowerInit ( + IN OUT PEI_CPU_PLATFORM_POLICY_PPI *CpuPlatformPolicyPpi + ) +{ + EFI_CPUID_REGISTER Cpuid = { 0, 0, 0, 0 }; + MSR_REGISTER TempMsr; + UINT8 TccActivationOffsetProgrammable; + UINT16 MaxBusRatio; + UINT16 MinBusRatio; + UINT32 Remainder; + POWER_MGMT_CONFIG_PPI *PowerMgmtConfig; + MSR_REGISTER TurboRatioLimit; + UINT8 OneCoreRatioLimit; + MSR_REGISTER Ia32MiscEnable; + CPU_FAMILY CpuFamilyId; + CPU_STEPPING CpuStepping; + UINT8 TccActivationOffsetMask; + UINT32 WriteFivrSpreadCmd; + UINT32 ReadFivrSpreadCmd; + UINT32 ReadFivrSpreadData; + UINT32 WriteFivrSpreadData; + UINT32 MailboxStatus; + + PowerMgmtConfig = CpuPlatformPolicyPpi->PowerMgmtConfig; + CpuFamilyId = GetCpuFamily(); + CpuStepping = GetCpuStepping(); + + /// + /// Initializes Processor Prefetcher + /// + ProcessorsPrefetcherInitialization ( + CpuPlatformPolicyPpi->CpuConfig->MlcStreamerPrefetcher, + CpuPlatformPolicyPpi->CpuConfig->MlcSpatialPrefetcher + ); + + TempMsr.Qword = AsmReadMsr64 (MSR_PLATFORM_INFO); + + /// + /// Get Tcc Activation Offset Programmable Setting from Platform Info MSR Bits[30] + /// + TccActivationOffsetProgrammable = (UINT8) RShiftU64 ( + (TempMsr.Qword & B_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET), + N_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET + ); + /// + /// Get Maximum Non-Turbo bus ratio (HFM) from Platform Info MSR Bits[15:8] + /// + MaxBusRatio = TempMsr.Bytes.SecondByte; + /// + /// Get Maximum Efficiency bus ratio (LFM) from Platform Info MSR Bits[47:40] + /// + MinBusRatio = TempMsr.Bytes.SixthByte; + /// + /// Tcc activation offset in temperature target MSR changes from 4 bits [27:24] to 6 bits [29:24] on ULT C step onwards + /// + if ((CpuFamilyId == EnumCpuHswUlt) && (CpuStepping >= EnumHswUltC0)) { + TccActivationOffsetMask = 0x3F; + } else { + TccActivationOffsetMask = 0xF; + } + /// + /// If User slects TccActivationOffset greater than supported progam max supported. + /// + if(PowerMgmtConfig->TccActivationOffset > TccActivationOffsetMask){ + PowerMgmtConfig->TccActivationOffset = TccActivationOffsetMask; + } + /// + /// First check if TCC Activation Offset is programmable PLATFORM INFO MSR [30] + /// If TCC Activation Offset is programable, program the TCC Activation offset value + /// from Policy, and the Tcc activation offset programming should be dependency on RESET_CPL done. + /// + if (TccActivationOffsetProgrammable) { + TempMsr.Qword = AsmReadMsr64 (MSR_TEMPERATURE_TARGET); + TempMsr.Dwords.Low &= ~(TccActivationOffsetMask << N_MSR_TEMPERATURE_TARGET_TCC_OFFSET_LIMIT); + PowerMgmtConfig->TccActivationOffset &= TccActivationOffsetMask; + TempMsr.Dwords.Low |= LShiftU64 (PowerMgmtConfig->TccActivationOffset, N_MSR_TEMPERATURE_TARGET_TCC_OFFSET_LIMIT); + AsmWriteMsr64 (MSR_TEMPERATURE_TARGET, TempMsr.Qword); + } + /// + /// Program Voltage regulator Current Limit's + /// + TempMsr.Qword = AsmReadMsr64 (MSR_VR_CURRENT_CONFIG); + TempMsr.Dwords.High &= ~PSIX_THRESHOLD_MASK; + if (CpuPlatformPolicyPpi->Revision >= PEI_CPU_PLATFORM_POLICY_PPI_REVISION_5) { + TempMsr.Dwords.High |= ((PowerMgmtConfig->Psi3Threshold << 20) | (PowerMgmtConfig->Psi2Threshold << 10) | PowerMgmtConfig->Psi1Threshold ); + if ((CpuFamilyId == EnumCpuHswUlt) && (PowerMgmtConfig->VrPSI4enable)) { + TempMsr.Dwords.High |= (0x1 << 30); + } + } + if (PowerMgmtConfig->VrCurrentLimit != 0) { + /// + /// Check the VR_CURRENT_LOCK bit + /// + if ((TempMsr.Dwords.Low & B_CURRENT_LIMIT_LOCK) == 0) { + TempMsr.Dwords.Low &= ~B_CURRENT_LIMIT_MASK; + TempMsr.Dwords.Low |= PowerMgmtConfig->VrCurrentLimit; + } else { + DEBUG ((EFI_D_INFO, "PPM:: VR Current Limit in MSR_VR_CURRENT_CONFIG is locked\n")); + } + } + /// + /// Set CURRENT_LIMIT_LOCK bit in VR_Config_MSR + /// + if (PowerMgmtConfig->VrCurrentLimitLock) { + TempMsr.Dwords.Low |= B_CURRENT_LIMIT_LOCK; + } + + AsmWriteMsr64 (MSR_VR_CURRENT_CONFIG, TempMsr.Qword); + + if (CpuPlatformPolicyPpi->Revision >= PEI_CPU_PLATFORM_POLICY_PPI_REVISION_4) { + TempMsr.Qword = AsmReadMsr64 (MSR_VR_MISC_CONFIG); + TempMsr.Dwords.High = RRotU32 (TempMsr.Dwords.High, 8); + if (PowerMgmtConfig->VrMiscIoutSlope <= 1023) { + /// + /// Update IOUT_SLOPE [49:40] + /// Must be 0 to 0x3FF (1023 decimal) + /// + TempMsr.Dwords.High &= ~0x3FF; + TempMsr.Dwords.High |= PowerMgmtConfig->VrMiscIoutSlope; + } + TempMsr.Dwords.High = LRotU32 (TempMsr.Dwords.High, 8); + if ((PowerMgmtConfig->VrMiscIoutOffset != 0) && (PowerMgmtConfig->VrMiscIoutOffset <= 625)) { + /// + /// Update IOUT_OFFSET[39:32] + /// MSR encoding = int(value*2^8+0.0625) for positive offsets + /// inv(int(value*2^8+0.0625))+1 for negative offsets + /// +0.0625 could be ignored + /// + PowerMgmtConfig->VrMiscIoutOffset = (UINT16) DivU64x32Remainder ( + (UINT64) MultU64x32 (PowerMgmtConfig->VrMiscIoutOffset, (UINT32) LShiftU64 (1, 8)), + 10000, + &Remainder + ); + if (Remainder >= 5000) { + PowerMgmtConfig->VrMiscIoutOffset += 1; + } + if (PowerMgmtConfig->VrMiscIoutOffsetSign == 1) { + /// + /// This is negative offset + /// + PowerMgmtConfig->VrMiscIoutOffset = (UINT8) (~PowerMgmtConfig->VrMiscIoutOffset + 1); + } + TempMsr.Dwords.High &= ~0xFF; + TempMsr.Dwords.High |= PowerMgmtConfig->VrMiscIoutOffset; + } + AsmWriteMsr64 (MSR_VR_MISC_CONFIG, TempMsr.Qword); + } + + if (CpuPlatformPolicyPpi->Revision >= PEI_CPU_PLATFORM_POLICY_PPI_REVISION_3) { + TempMsr.Qword = AsmReadMsr64 (MSR_VR_MISC_CONFIG); + TempMsr.Dwords.Low = RRotU32 (TempMsr.Dwords.Low, N_MSR_VR_MISC_CONFIG_MIN_VID_OFFSET); + /// + /// Update MIN_VID [31:24] + /// Must be 0 to 0xFF (255 decimal) resolution 10mV + /// 0 equal to 0mV; 0xFF (255 decimal) equal to 2550mV + /// + TempMsr.Dwords.Low &= ~B_MSR_VR_MISC_CONFIG_MIN_VID_MASK; + TempMsr.Dwords.Low |= PowerMgmtConfig->VrMiscMinVid; + TempMsr.Dwords.Low = LRotU32 (TempMsr.Dwords.Low, N_MSR_VR_MISC_CONFIG_MIN_VID_OFFSET); + + /// + /// Update IDLE_EXIT_RAMP_RATE[50] + /// + TempMsr.Qword &= ~B_MSR_VR_MISC_CONFIG_IDLE_EXIT_RAMP_RATE; + if (PowerMgmtConfig->VrMiscIdleExitRampRate) { + TempMsr.Qword |= B_MSR_VR_MISC_CONFIG_IDLE_EXIT_RAMP_RATE; + } + + /// + /// Update IDLE_ENTRY_RAMP_RATE[51] + /// + TempMsr.Qword &= ~B_MSR_VR_MISC_CONFIG_IDLE_ENTRY_RAMP_RATE; + if (PowerMgmtConfig->VrMiscIdleEntryRampRate) { + TempMsr.Qword |= B_MSR_VR_MISC_CONFIG_IDLE_ENTRY_RAMP_RATE; + } + + /// + /// Update IDLE_ENTRY_DECAY_ENABLE[52] + /// + TempMsr.Qword &= ~B_MSR_VR_MISC_CONFIG_IDLE_ENTRY_DECAY_ENABLE; + if (PowerMgmtConfig->VrMiscIdleEntryDecayEnable) { + TempMsr.Qword |= B_MSR_VR_MISC_CONFIG_IDLE_ENTRY_DECAY_ENABLE; + } + + if (CpuFamilyId == EnumCpuHswUlt) { + /// + /// Update IDLE_ENTRY_DECAY_ENABLE[52] + /// + TempMsr.Qword &= ~B_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_MASK; + switch (PowerMgmtConfig->VrMiscSlowSlewRateConfig) { + case 1: + TempMsr.Qword |= V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_FAST_4; + break; + case 2: + TempMsr.Qword |= V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_FAST_8; + break; + case 3: + TempMsr.Qword |= V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_FAST_16; + break; + case 0: + default: + TempMsr.Qword |= V_MSR_VR_MISC_CONFIG_SLOW_SLEW_RATE_CONFIG_FAST_2; + break; + } + } + AsmWriteMsr64 (MSR_VR_MISC_CONFIG, TempMsr.Qword); + + if (CpuFamilyId == EnumCpuHswUlt) { + TempMsr.Qword = AsmReadMsr64 (MSR_VR_MISC_CONFIG2); + /// + /// Update FAST_RAMP_VOLTAGE [7:0] + /// Must be 0 to 0xFF (255 decimal) resolution 10mV + /// 0 equal to 0mV; 0xFF (255 decimal) equal to 2550mV + /// + TempMsr.Bytes.FirstByte &= ~B_MSR_VR_MISC_CONFIG2_FAST_RAMP_VOLTAGE_MASK; + TempMsr.Bytes.FirstByte |= PowerMgmtConfig->VrMisc2FastRampVoltage; + + /// + /// Update MIN_C8_VOLTAGE [15:8] + /// Must be 0 to 0xFF (255 decimal) resolution 10mV + /// 0 equal to 0mV; 0xFF (255 decimal) equal to 2550mV + /// + TempMsr.Bytes.SecondByte &= ~B_MSR_VR_MISC_CONFIG2_MIN_C8_VOLTAGE_MASK; + TempMsr.Bytes.SecondByte |= PowerMgmtConfig->VrMisc2MinC8Voltage; + + AsmWriteMsr64 (MSR_VR_MISC_CONFIG2, TempMsr.Qword); + } + } + /// + /// Initializes XE OR Overclocking support + /// + XeInit (CpuPlatformPolicyPpi->PowerMgmtConfig, CpuPlatformPolicyPpi->OverclockingConfig); + + /// + /// Set processor P state to HFM, LFM or TURBO + /// + AsmCpuid (CPUID_VERSION_INFO, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEcx, &Cpuid.RegEdx); + /// + /// Check to see if CPU is GV3 capable - GV3 is fused Enabled + /// + if ((Cpuid.RegEcx & B_CPUID_VERSION_INFO_ECX_EIST) == B_CPUID_VERSION_INFO_ECX_EIST) { + Ia32MiscEnable.Qword = AsmReadMsr64 (MSR_IA32_MISC_ENABLE); + Ia32MiscEnable.Qword |= B_MSR_IA32_MISC_ENABLE_EIST; + AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Ia32MiscEnable.Qword); + + TempMsr.Qword = AsmReadMsr64 (MSR_IA32_PERF_CTRL); + TempMsr.Qword &= ~B_IA32_PERF_CTRLP_STATE_TARGET; + + if ((CpuPlatformPolicyPpi->Revision >= PEI_CPU_PLATFORM_POLICY_PPI_REVISION_3) && (PowerMgmtConfig->BootInLfm == 2)) { + /// + /// Set processor P state as TURBO_RATIO_LIMIT_1C if available + /// + AsmCpuid (CPUID_POWER_MANAGEMENT_PARAMS, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEcx, &Cpuid.RegEdx); + if (((Cpuid.RegEax & B_CPUID_POWER_MANAGEMENT_EAX_TURBO) == B_CPUID_POWER_MANAGEMENT_EAX_TURBO) || + ((Ia32MiscEnable.Qword & B_MSR_IA32_MISC_DISABLE_TURBO) == B_MSR_IA32_MISC_DISABLE_TURBO)) { + /// + /// Temporarily enable Turbo and it will be reset in DXE phase + /// + Ia32MiscEnable.Qword &= ~B_MSR_IA32_MISC_DISABLE_TURBO; + AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Ia32MiscEnable.Qword); + /// + /// Set processor P state as TURBO_RATIO_LIMIT_1C + /// + TurboRatioLimit.Qword = AsmReadMsr64 (MSR_TURBO_RATIO_LIMIT); + OneCoreRatioLimit = (UINT8) (TurboRatioLimit.Dwords.Low & B_MSR_TURBO_RATIO_LIMIT_1C); + TempMsr.Qword |= LShiftU64 (OneCoreRatioLimit, N_IA32_PERF_CTRLP_STATE_TARGET); + } else { + /// + /// Turbo is not available, down to HFM + /// + DEBUG ((EFI_D_INFO, "CPU: Turbo mode is not available, down to HFM mode.\n")); + TempMsr.Qword |= LShiftU64 (MaxBusRatio, N_IA32_PERF_CTRLP_STATE_TARGET); + } + } else if (PowerMgmtConfig->BootInLfm == CPU_FEATURE_DISABLE) { + /// + /// Set processor P state as HFM + /// + TempMsr.Qword |= LShiftU64 (MaxBusRatio, N_IA32_PERF_CTRLP_STATE_TARGET); + } else { + /// + /// Set processor P state as LFM + /// + TempMsr.Qword |= LShiftU64 (MinBusRatio, N_IA32_PERF_CTRLP_STATE_TARGET); + } + + AsmWriteMsr64 (MSR_IA32_PERF_CTRL, TempMsr.Qword); + } + + /// + /// FIVR Spread Spectrum control is available on C0 steppings onward for all CPU families + /// + if ((CpuFamilyId == EnumCpuHswUlt && CpuStepping >= EnumHswUltC0) || + (CpuFamilyId == EnumCpuHsw && CpuStepping >= EnumHswC0) || + (CpuFamilyId == EnumCpuCrw && CpuStepping >= EnumCrwC0)){ + + /// + /// FivrSscPercent is specified in 1/10th percent increments. Range is 0-249. + /// + if (PowerMgmtConfig->FivrSscPercent > MAX_FIVR_SSC_PERCENT) { + PowerMgmtConfig->FivrSscPercent = MAX_FIVR_SSC_PERCENT; + } + + /// + /// Read current FIVR SSC Spread percentage + /// + ReadFivrSpreadCmd = 0x8000000E; + ReadFivrSpreadData = 0; + MailboxRead(MAILBOX_TYPE_PCODE, ReadFivrSpreadCmd, &ReadFivrSpreadData, &MailboxStatus); + +//(AMI_CHG)> + { + UINT32 i = 0; + while (MailboxStatus == PCODE_MAILBOX_CC_VR_INTERFACE_LOCKED) { + MailboxRead(MAILBOX_TYPE_PCODE, ReadFivrSpreadCmd, &ReadFivrSpreadData, &MailboxStatus); + i++; + if (i == 100) break; + } + } +//<(AMI_CHG) + + if (PowerMgmtConfig->FivrSscEnable) { + WriteFivrSpreadData = ( ((PowerMgmtConfig->FivrSscPercent)*1024)/NUM_TENTHS_TO_PERCENTAGE) | FIVR_SSC_LOCK_BIT; + } + else { + /// + /// If disabling FIVR SSC, send 0% spread and lock interface + /// + + WriteFivrSpreadData = FIVR_SSC_LOCK_BIT; + } + + DEBUG ((EFI_D_INFO, "FIVR: Read FIVR Spread = %X, Write FIVR Spread = %X\n", ReadFivrSpreadData, WriteFivrSpreadData)); + /// + /// Only update SSC percentage if needed + /// + if (ReadFivrSpreadData != WriteFivrSpreadData) { + DEBUG ((EFI_D_INFO, "FIVR: Update FIVR Spread = %X\n", WriteFivrSpreadData)); + + WriteFivrSpreadCmd = 0x8000000F; + MailboxWrite(MAILBOX_TYPE_PCODE, WriteFivrSpreadCmd, WriteFivrSpreadData, &MailboxStatus); + +//(AMI_CHG)> + { + UINT32 i = 0; + while (MailboxStatus == PCODE_MAILBOX_CC_VR_INTERFACE_LOCKED) { + MailboxWrite(MAILBOX_TYPE_PCODE, WriteFivrSpreadCmd, WriteFivrSpreadData, &MailboxStatus); + i++; + if (i == 100) break; + } + } +//<(AMI_CHG) + + if (MailboxStatus != PCODE_MAILBOX_CC_SUCCESS) { + DEBUG ((EFI_D_ERROR, "FIVR: Error updating FIVR Spread. Mailbox Status = %X\n", MailboxStatus)); + } + } + } + else { + DEBUG ((EFI_D_ERROR, "FIVR: FIVR Spread adjustment requires C0 stepping or greater. Bypassing FIVR Spread flow.\n")); + } + + return; +} + +/** + Loads the Processor Microcode & Install the Cache PPI + + @param[in] FfsHeader - Pointer to an alleged FFS file. + @param[in] PeiServices - General purpose services available to every PEIM. + + @retval EFI_STATUS - the status code returned from any sub-routine +**/ +EFI_STATUS +PeimInitializeCpu ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + PEI_CPU_PLATFORM_POLICY_PPI *CpuPlatformPolicyPpi; + + Status = PeiServicesLocatePpi ( + &gPeiCpuPlatformPolicyPpiGuid, + 0, + NULL, + (VOID **) &CpuPlatformPolicyPpi + ); + if (EFI_ERROR (Status)) { + return Status; + + } + + // + // Dump Cpu Platform Policy + // + CpuPeiPolicyDump(CpuPlatformPolicyPpi); + + /// + /// Install Cache PPI + /// + Status = CacheInitPpiInit (); + ASSERT_EFI_ERROR (Status); + + /// + /// Install Notify + /// + Status = PeiServicesNotifyPpi (&mNotifyList[0]); + ASSERT_EFI_ERROR (Status); + + /// + /// Initializes Overclocking support + /// + CpuOcInit(PeiServices, CpuPlatformPolicyPpi); + + /// + /// Initializes Performance and Power Settings + /// + ProcessorsPerfPowerInit (CpuPlatformPolicyPpi); + + /// + /// Init XMM support + /// + XmmInit (); + + /// + /// Pfat Initialization + /// + PfatInit (PeiServices, CpuPlatformPolicyPpi); + + /// + /// Boot Guard Initializatoin + /// + BootGuardInit (PeiServices, CpuPlatformPolicyPpi); + + return Status; +} + +/** + Build BIST HOB + + @param[in] PeiServices - Indirect reference to the PEI Services Table. + @param[in] NotifyDescriptor - Address of the notification descriptor data structure. Type + EFI_PEI_NOTIFY_DESCRIPTOR is defined above. + @param[in] Ppi - Address of the PPI that was installed. + + @retval EFI_SUCCESS - Hob built or not necessary +**/ +EFI_STATUS +EFIAPI +BuildBistHob ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + EFI_SEC_PLATFORM_INFORMATION_PPI *SecPlatformInformationPpi; + UINT64 InformationSize; + SEC_PLATFORM_INFORMATION_RECORD *SecPlatformInformation; + VOID *Hob; + + Status = (**PeiServices).GetBootMode (PeiServices, &BootMode); + if (!EFI_ERROR (Status) && (BootMode == BOOT_ON_S3_RESUME)) { + return EFI_SUCCESS; + } + + Status = PeiServicesLocatePpi ( + &gEfiSecPlatformInformationPpiGuid, ///< GUID + 0, ///< INSTANCE + NULL, ///< EFI_PEI_PPI_DESCRIPTOR + (VOID ** ) &SecPlatformInformationPpi ///< PPI + ); + + if (Status == EFI_NOT_FOUND) { + return EFI_SUCCESS; + } + + if (EFI_ERROR (Status)) { + return Status; + } + + InformationSize = 0; + SecPlatformInformation = NULL; + Status = SecPlatformInformationPpi->PlatformInformation ( + PeiServices, + &InformationSize, + SecPlatformInformation + ); + if (Status == EFI_BUFFER_TOO_SMALL) { + Status = PeiServicesAllocatePool ( + (UINTN) InformationSize, + (VOID **) &SecPlatformInformation + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + Status = SecPlatformInformationPpi->PlatformInformation ( + PeiServices, + &InformationSize, + SecPlatformInformation + ); + } + + if (EFI_ERROR (Status)) { + return Status; + } + + Hob = BuildGuidDataHob ( + &gEfiHtBistHobGuid, + SecPlatformInformation, + (UINTN) InformationSize + ); + ASSERT (Hob != NULL); + + return Status; +} + +/** + Dump RC CPU and PPM platform policies + + @param[in] CpuPlatformPolicyPpi - Address of the cpu platform policy ppi. +**/ +VOID +CpuPeiPolicyDump ( + IN PEI_CPU_PLATFORM_POLICY_PPI *CpuPlatformPolicyPpi + ) +{ +#ifdef EFI_DEBUG + UINTN Index; + CPU_CONFIG_PPI *CpuConfig; + POWER_MGMT_CONFIG_PPI *PowerMgmtConfig; + SECURITY_CONFIG_PPI *SecurityConfig; + OVERCLOCKING_CONFIG_PPI *OverclockingConfig; + + CpuConfig = CpuPlatformPolicyPpi->CpuConfig; + PowerMgmtConfig = CpuPlatformPolicyPpi->PowerMgmtConfig; + SecurityConfig = CpuPlatformPolicyPpi->SecurityConfig; + OverclockingConfig = CpuPlatformPolicyPpi->OverclockingConfig; + + DEBUG ((EFI_D_INFO, "\n------------------------ CpuPlatformPolicyPpi Dump Begin -----------------\n")); + // + // CPU_CONFIG + // + DEBUG ((EFI_D_INFO, " CPU:: BistOnReset : 0x%X\n", CpuConfig->BistOnReset)); + DEBUG ((EFI_D_INFO, " CPU:: HyperThreading : 0x%X\n", CpuConfig->HyperThreading)); + DEBUG ((EFI_D_INFO, " CPU:: CpuRatioOverride : 0x%X\n", CpuConfig->CpuRatioOverride)); + DEBUG ((EFI_D_INFO, " CPU:: VmxEnable : 0x%X\n", CpuConfig->VmxEnable)); + DEBUG ((EFI_D_INFO, " CPU:: Pfat Feature: 0x%X\n", CpuConfig->Pfat)); + DEBUG ((EFI_D_INFO, " CPU:: MlcStreamerPrefetcher : 0x%X\n", CpuConfig->MlcStreamerPrefetcher)); + DEBUG ((EFI_D_INFO, " CPU:: MlcSpatialPrefetcher : 0x%X\n", CpuConfig->MlcSpatialPrefetcher)); + DEBUG ((EFI_D_INFO, " CPU:: ActiveCoreCount : 0x%X\n", CpuConfig->ActiveCoreCount)); + DEBUG ((EFI_D_INFO, " CPU:: CpuRatio : 0x%X\n", CpuConfig->CpuRatio)); + DEBUG ((EFI_D_INFO, " CPU:: MaxNonTurboRatio : 0x%X\n", CpuConfig->CpuMaxNonTurboRatio)); + // + // POWER_MGMT_CONFIG + // + DEBUG ((EFI_D_INFO, " PPM:: BootInLfm : 0x%X\n", PowerMgmtConfig->BootInLfm)); + DEBUG ((EFI_D_INFO, " PPM:: TccActivationOffset : 0x%X\n", PowerMgmtConfig->TccActivationOffset)); + DEBUG ((EFI_D_INFO, " PPM:: VrCurrentLimit : 0x%X\n", PowerMgmtConfig->VrCurrentLimit)); + DEBUG ((EFI_D_INFO, " PPM:: VrCurrentLimitLock : 0x%X\n", PowerMgmtConfig->VrCurrentLimitLock)); + DEBUG ((EFI_D_INFO, " PPM:: Xe : 0x%X\n", PowerMgmtConfig->Xe)); + DEBUG ((EFI_D_INFO, " PPM:: RatioLimit[4] : 0x%X , 0x%X , 0x%X , 0x%X \n", PowerMgmtConfig->RatioLimit[0], \ + PowerMgmtConfig->RatioLimit[1], \ + PowerMgmtConfig->RatioLimit[2], \ + PowerMgmtConfig->RatioLimit[3])); + DEBUG ((EFI_D_INFO, " PPM:: VrMiscIoutSlope : 0x%X\n", PowerMgmtConfig->VrMiscIoutSlope)); + DEBUG ((EFI_D_INFO, " PPM:: VrMiscIoutOffsetSign : 0x%X\n", PowerMgmtConfig->VrMiscIoutOffsetSign)); + DEBUG ((EFI_D_INFO, " PPM:: VrMiscIoutOffset : 0x%X\n", PowerMgmtConfig->VrMiscIoutOffset)); + DEBUG ((EFI_D_INFO, " PPM:: VrMiscMinVid : 0x%X\n", PowerMgmtConfig->VrMiscMinVid)); + DEBUG ((EFI_D_INFO, " PPM:: VrMiscIdleExitRampRate : 0x%X\n", PowerMgmtConfig->VrMiscIdleExitRampRate)); + DEBUG ((EFI_D_INFO, " PPM:: VrMiscIdleEntryRampRate : 0x%X\n", PowerMgmtConfig->VrMiscIdleEntryRampRate)); + DEBUG ((EFI_D_INFO, " PPM:: VrMiscIdleEntryDecayEnable : 0x%X\n", PowerMgmtConfig->VrMiscIdleEntryDecayEnable)); + DEBUG ((EFI_D_INFO, " PPM:: VrMiscSlowSlewRateConfig : 0x%X\n", PowerMgmtConfig->VrMiscSlowSlewRateConfig)); + DEBUG ((EFI_D_INFO, " PPM:: VrMisc2FastRampVoltage : 0x%X\n", PowerMgmtConfig->VrMisc2FastRampVoltage)); + DEBUG ((EFI_D_INFO, " PPM:: VrMisc2MinC8Voltage : 0x%X\n", PowerMgmtConfig->VrMisc2MinC8Voltage)); + DEBUG ((EFI_D_INFO, " PPM:: FivrSscEnable : 0x%X\n", PowerMgmtConfig->FivrSscEnable)); + DEBUG ((EFI_D_INFO, " PPM:: FivrSscPercent : 0x%X\n", PowerMgmtConfig->FivrSscPercent)); + + // + // SECURITY_CONFIG : PFAT_CONFIG + // + DEBUG ((EFI_D_INFO, " PFAT:: PUP_HEADER : Version : 0x%X\n", SecurityConfig->PfatConfig->PupHeader.Version)); + DEBUG ((EFI_D_INFO, " PFAT:: PUP_HEADER : PlatId[16] :\n")); + for (Index = 0; Index < 16; Index++) { + if (Index == 15) { + DEBUG ((EFI_D_INFO, " 0x%X\n", SecurityConfig->PfatConfig->Ppdt.PlatId[Index])); + } else { + DEBUG ((EFI_D_INFO, " 0x%X ,", SecurityConfig->PfatConfig->Ppdt.PlatId[Index])); + } + } + DEBUG ((EFI_D_INFO, " \n")); + DEBUG ((EFI_D_INFO, " PFAT:: PUP_HEADER : PkgAttributes : 0x%X\n", SecurityConfig->PfatConfig->PupHeader.PkgAttributes)); + DEBUG ((EFI_D_INFO, " PFAT:: PUP_HEADER : PslMajorVer : 0x%X\n", SecurityConfig->PfatConfig->PupHeader.PslMajorVer)); + DEBUG ((EFI_D_INFO, " PFAT:: PUP_HEADER : PslMinorVer : 0x%X\n", SecurityConfig->PfatConfig->PupHeader.PslMinorVer)); + DEBUG ((EFI_D_INFO, " PFAT:: PUP_HEADER : ScriptSectionSize : 0x%X\n", SecurityConfig->PfatConfig->PupHeader.ScriptSectionSize)); + DEBUG ((EFI_D_INFO, " PFAT:: PUP_HEADER : DataSectionSize : 0x%X\n", SecurityConfig->PfatConfig->PupHeader.DataSectionSize)); + DEBUG ((EFI_D_INFO, " PFAT:: PUP_HEADER : BiosSvn : 0x%X\n", SecurityConfig->PfatConfig->PupHeader.BiosSvn)); + DEBUG ((EFI_D_INFO, " PFAT:: PUP_HEADER : EcSvn : 0x%X\n", SecurityConfig->PfatConfig->PupHeader.EcSvn)); + DEBUG ((EFI_D_INFO, " PFAT:: PUP_HEADER : VendorSpecific : 0x%X\n", SecurityConfig->PfatConfig->PupHeader.VendorSpecific)); + DEBUG ((EFI_D_INFO, " PFAT:: PPDT : PpdtSize : 0x%X\n", SecurityConfig->PfatConfig->Ppdt.PpdtSize)); + DEBUG ((EFI_D_INFO, " PFAT:: PPDT : PpdtMajVer : 0x%X\n", SecurityConfig->PfatConfig->Ppdt.PpdtMajVer)); + DEBUG ((EFI_D_INFO, " PFAT:: PPDT : PpdtMinVer : 0x%X\n", SecurityConfig->PfatConfig->Ppdt.PpdtMinVer)); + DEBUG ((EFI_D_INFO, " PFAT:: PPDT : PlatId[16] :\n")); + for (Index = 0; Index < 16; Index++) { + if (Index == 15) { + DEBUG ((EFI_D_INFO, " 0x%X\n", SecurityConfig->PfatConfig->Ppdt.PlatId[Index])); + } else { + DEBUG ((EFI_D_INFO, " 0x%X ,", SecurityConfig->PfatConfig->Ppdt.PlatId[Index])); + } + } + DEBUG ((EFI_D_INFO, " \n")); + DEBUG ((EFI_D_INFO, " PFAT:: PPDT : PkeySlot0[32] :\n")); + for (Index = 0; Index < 32; Index++) { + if ((Index == 15) || (Index == 31)) { + DEBUG ((EFI_D_INFO, " 0x%X\n", SecurityConfig->PfatConfig->Ppdt.PkeySlot0[Index])); + } else { + DEBUG ((EFI_D_INFO, " 0x%X ,", SecurityConfig->PfatConfig->Ppdt.PkeySlot0[Index])); + } + } + DEBUG ((EFI_D_INFO, " \n")); + DEBUG ((EFI_D_INFO, " PFAT:: PPDT : PkeySlot1[32] :\n")); + for (Index = 0; Index < 32; Index++) { + if ((Index == 15) || (Index == 31)) { + DEBUG ((EFI_D_INFO, " 0x%X\n", SecurityConfig->PfatConfig->Ppdt.PkeySlot1[Index])); + } else { + DEBUG ((EFI_D_INFO, " 0x%X ,", SecurityConfig->PfatConfig->Ppdt.PkeySlot1[Index])); + } + } + DEBUG ((EFI_D_INFO, " \n")); + DEBUG ((EFI_D_INFO, " PFAT:: PPDT : PkeySlot2[32] :\n")); + for (Index = 0; Index < 32; Index++) { + if ((Index == 15)|| (Index == 31)) { + DEBUG ((EFI_D_INFO, " 0x%X\n", SecurityConfig->PfatConfig->Ppdt.PkeySlot2[Index])); + } else { + DEBUG ((EFI_D_INFO, " 0x%X ,", SecurityConfig->PfatConfig->Ppdt.PkeySlot2[Index])); + } + } + DEBUG ((EFI_D_INFO, " \n")); + DEBUG ((EFI_D_INFO, " PFAT:: PPDT : PfatModSvn : 0x%X\n", SecurityConfig->PfatConfig->Ppdt.PfatModSvn)); + DEBUG ((EFI_D_INFO, " PFAT:: PPDT : BiosSvn : 0x%X\n", SecurityConfig->PfatConfig->Ppdt.BiosSvn)); + DEBUG ((EFI_D_INFO, " PFAT:: PPDT : ExecLim : 0x%X\n", SecurityConfig->PfatConfig->Ppdt.ExecLim)); + DEBUG ((EFI_D_INFO, " PFAT:: PPDT : PlatAttr : 0x%X\n", SecurityConfig->PfatConfig->Ppdt.PlatAttr)); + DEBUG ((EFI_D_INFO, " PFAT:: PPDT : EcCmd : 0x%X\n", SecurityConfig->PfatConfig->Ppdt.EcCmd)); + DEBUG ((EFI_D_INFO, " PFAT:: PPDT : EcData : 0x%X\n", SecurityConfig->PfatConfig->Ppdt.EcData)); + DEBUG ((EFI_D_INFO, " PFAT:: PPDT : EcCmdGetSvn : 0x%X\n", SecurityConfig->PfatConfig->Ppdt.EcCmdGetSvn)); + DEBUG ((EFI_D_INFO, " PFAT:: PPDT : EcCmdOpen : 0x%X\n", SecurityConfig->PfatConfig->Ppdt.EcCmdOpen)); + DEBUG ((EFI_D_INFO, " PFAT:: PPDT : EcCmdClose : 0x%X\n", SecurityConfig->PfatConfig->Ppdt.EcCmdClose)); + DEBUG ((EFI_D_INFO, " PFAT:: PPDT : EcCmdPortTest : 0x%X\n", SecurityConfig->PfatConfig->Ppdt.EcCmdPortTest)); + DEBUG ((EFI_D_INFO, " PFAT:: PPDT : LastSfam : 0x%X\n", SecurityConfig->PfatConfig->Ppdt.LastSfam)); + DEBUG ((EFI_D_INFO, " PFAT:: PPDT : SfamData[64] :\n")); + // + // Change the array size according to MAX_SFAM_COUNT + // + for (Index = 0; Index < 64; Index++) { + if ((Index == 15) || (Index == 31) || (Index == 47) || (Index == 63) ) { + DEBUG ((EFI_D_INFO, " 0x%X\n", SecurityConfig->PfatConfig->Ppdt.SfamData[Index])); + } else { + DEBUG ((EFI_D_INFO, " 0x%X ,", SecurityConfig->PfatConfig->Ppdt.SfamData[Index])); + } + } + DEBUG ((EFI_D_INFO, " \n")); + DEBUG ((EFI_D_INFO, " PFAT:: PpdtHash[4] : 0x%lX , 0x%lX , 0x%lX , 0x%lX \n", SecurityConfig->PfatConfig->PpdtHash[0], \ + SecurityConfig->PfatConfig->PpdtHash[1], \ + SecurityConfig->PfatConfig->PpdtHash[2], \ + SecurityConfig->PfatConfig->PpdtHash[3])); + + DEBUG ((EFI_D_INFO, " PFAT:: NumSpiComponents : 0x%x\n", SecurityConfig->PfatConfig->NumSpiComponents)); + DEBUG ((EFI_D_INFO, " PFAT:: PPDT : ComponentSize[8] :\n")); + for (Index = 0; Index < SecurityConfig->PfatConfig->NumSpiComponents; Index++) { + if (Index == 7) { + DEBUG ((EFI_D_INFO, " 0x%X\n", SecurityConfig->PfatConfig->ComponentSize[Index])); + } else { + DEBUG ((EFI_D_INFO, " 0x%X ,", SecurityConfig->PfatConfig->ComponentSize[Index])); + } + } + DEBUG ((EFI_D_INFO, " \n")); + DEBUG ((EFI_D_INFO, " PFAT:: PfatMemSize : 0x%X\n", SecurityConfig->PfatConfig->PfatMemSize)); + DEBUG ((EFI_D_INFO, " PFAT:: EcCmdDiscovery : 0x%X\n", SecurityConfig->PfatConfig->EcCmdDiscovery)); + DEBUG ((EFI_D_INFO, " PFAT:: EcCmdProvisionEav : 0x%X\n", SecurityConfig->PfatConfig->EcCmdProvisionEav)); + DEBUG ((EFI_D_INFO, " PFAT:: EcCmdLock : 0x%X\n", SecurityConfig->PfatConfig->EcCmdLock)); + DEBUG ((EFI_D_INFO, " PFAT:: PFATLOG:: Version : 0x%X\n", SecurityConfig->PfatConfig->PfatLog.Version)); + DEBUG ((EFI_D_INFO, " PFAT:: PFATLOG:: LastPage : 0x%X\n", SecurityConfig->PfatConfig->PfatLog.LastPage)); + DEBUG ((EFI_D_INFO, " PFAT:: PFATLOG:: LoggingOptions : 0x%X\n", SecurityConfig->PfatConfig->PfatLog.LoggingOptions)); + DEBUG ((EFI_D_INFO, " PFAT:: PFATLOG:: PfatModSvn : 0x%X\n", SecurityConfig->PfatConfig->PfatLog.PfatModSvn)); + DEBUG ((EFI_D_INFO, " PFAT:: PFATLOG:: NumOfEntriesInLog : 0x%X\n", SecurityConfig->PfatConfig->PfatLog.NumOfEntriesInLog)); + // + // SECURITY_CONFIG : TXT_CONFIG + // +#if defined(TXT_SUPPORT_FLAG) && (TXT_SUPPORT_FLAG == 1) + DEBUG ((EFI_D_INFO, " TXT:: SinitMemorySize : 0x%lX\n", SecurityConfig->TxtConfig->SinitMemorySize)); + DEBUG ((EFI_D_INFO, " TXT:: TxtHeapMemorySize : 0x%lX\n", SecurityConfig->TxtConfig->TxtHeapMemorySize)); + DEBUG ((EFI_D_INFO, " TXT:: TxtDprMemoryBase : 0x%lX\n", SecurityConfig->TxtConfig->TxtDprMemoryBase)); + DEBUG ((EFI_D_INFO, " TXT:: TxtDprMemorySize : 0x%lX\n", SecurityConfig->TxtConfig->TxtDprMemorySize)); + DEBUG ((EFI_D_INFO, " TXT:: BiosAcmBase : 0x%lX\n", SecurityConfig->TxtConfig->BiosAcmBase)); + DEBUG ((EFI_D_INFO, " TXT:: BiosAcmSize : 0x%lX\n", SecurityConfig->TxtConfig->BiosAcmSize)); + DEBUG ((EFI_D_INFO, " TXT:: McuUpdateDataAddr : 0x%lX\n", SecurityConfig->TxtConfig->McuUpdateDataAddr)); + DEBUG ((EFI_D_INFO, " TXT:: TgaSize : 0x%lX\n", SecurityConfig->TxtConfig->TgaSize)); + DEBUG ((EFI_D_INFO, " TXT:: TxtLcpPdBase : 0x%lX\n", SecurityConfig->TxtConfig->TxtLcpPdBase)); + DEBUG ((EFI_D_INFO, " TXT:: TxtLcpPdSize : 0x%lX\n", SecurityConfig->TxtConfig->TxtLcpPdSize)); +#else + DEBUG ((EFI_D_INFO, " TXT CONFIG:: UNSUPPORTED \n")); +#endif + + // + // OVERCLOCKING_CONFIG + // + DEBUG ((EFI_D_INFO, " OC:: CoreVoltageOffset : 0x%X\n", OverclockingConfig->CoreVoltageOffset)); + DEBUG ((EFI_D_INFO, " OC:: CoreVoltageOverride : 0x%X\n", OverclockingConfig->CoreVoltageOverride)); + DEBUG ((EFI_D_INFO, " OC:: CoreExtraTurboVoltage : 0x%X\n", OverclockingConfig->CoreExtraTurboVoltage)); + DEBUG ((EFI_D_INFO, " OC:: CoreMaxOcTurboRatio : 0x%X\n", OverclockingConfig->CoreMaxOcTurboRatio)); + DEBUG ((EFI_D_INFO, " OC:: ClrVoltageOffset : 0x%X\n", OverclockingConfig->ClrVoltageOffset)); + DEBUG ((EFI_D_INFO, " OC:: ClrVoltageOverride : 0x%X\n", OverclockingConfig->ClrVoltageOverride)); + DEBUG ((EFI_D_INFO, " OC:: ClrExtraTurboVoltage : 0x%X\n", OverclockingConfig->ClrExtraTurboVoltage)); + DEBUG ((EFI_D_INFO, " OC:: ClrMaxOcTurboRatio : 0x%X\n", OverclockingConfig->ClrMaxOcTurboRatio)); + DEBUG ((EFI_D_INFO, " OC:: SvidVoltageOverride : 0x%X\n", OverclockingConfig->SvidVoltageOverride)); + DEBUG ((EFI_D_INFO, " OC:: SvidEnable : 0x%X\n", OverclockingConfig->SvidEnable)); + DEBUG ((EFI_D_INFO, " OC:: FivrFaultsEnable : 0x%X\n", OverclockingConfig->FivrFaultsEnable)); + DEBUG ((EFI_D_INFO, " OC:: FivrEfficiencyEnable : 0x%X\n", OverclockingConfig->FivrEfficiencyEnable)); + DEBUG ((EFI_D_INFO, " OC:: CoreVoltageMode : 0x%X\n", OverclockingConfig->CoreVoltageMode)); + DEBUG ((EFI_D_INFO, " OC:: ClrVoltageMode : 0x%X\n", OverclockingConfig->ClrVoltageMode)); + DEBUG ((EFI_D_INFO, " OC:: OcSupport : 0x%X\n", OverclockingConfig->OcSupport)); + + DEBUG ((EFI_D_INFO, "\n------------------------ CpuPlatformPolicyPpi Dump End -----------------\n\n")); +#endif +} diff --git a/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPeim.dxs b/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPeim.dxs new file mode 100644 index 0000000..62f855b --- /dev/null +++ b/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPeim.dxs @@ -0,0 +1,42 @@ +/** @file + Dependency expression source file. + +@copyright + Copyright (c) 2004 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains a 'Sample Driver' and is licensed as such + under the terms of your license agreement with Intel or your + vendor. This file may be modified by the user, subject to + the additional terms of the license agreement + +**/ + + +// +// Common for R8 and R9 codebase +// +#include "AutoGen.h" +#include "PeimDepex.h" + +// +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are both "defined" in R8 codebase; +// BUILD_WITH_EDKII_GLUE_LIB is defined in Edk-Dev-Snapshot-20070228 and later version +// BUILD_WITH_GLUELIB and BUILD_WITH_EDKII_GLUE_LIB are "not defined" in R9 codebase. +// +#if defined (BUILD_WITH_GLUELIB) || defined (BUILD_WITH_EDKII_GLUE_LIB) +#include "EfiDepex.h" +#include EFI_PPI_DEFINITION (CpuPlatformPolicy) +#endif + +DEPENDENCY_START + + PEI_CPU_PLATFORM_POLICY_PPI_GUID + +DEPENDENCY_END diff --git a/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPeim.h b/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPeim.h new file mode 100644 index 0000000..9d6fac5 --- /dev/null +++ b/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPeim.h @@ -0,0 +1,212 @@ +/** @file + Describes the functions visible to the rest of the CpuPeim. + +@copyright + Copyright (c) 2010 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Pre-EFI Module' and is licensed + for Intel CPUs and Chipsets under the terms of your license + agreement with Intel or your vendor. This file may be + modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _CPU_INIT_PEIM_H_ +#define _CPU_INIT_PEIM_H_ + +#include EFI_PPI_PRODUCER (Cache) +#include EFI_PPI_DEFINITION (CpuPlatformPolicy) +#include "CpuRegs.h" + +typedef struct { + UINT32 HtDisabled : 1; + UINT32 NumberOfActiveCores : 2; + UINT32 Reserved0 : 2; + UINT32 Bist : 1; + UINT32 FlexRatio : 6; + UINT32 Reserved1 : 4; + UINT32 Reserved2 : 16; +} CPU_STRAP_SET; + +typedef UINT32 CPU_RESET_TYPE; + +typedef struct { + UINT64 MsrValue; + BOOLEAN Changed; +} MTRR_VALUE; + +typedef struct { + PEI_CACHE_PPI Ppi; + EFI_PEI_PPI_DESCRIPTOR PpiDesc; + MTRR_VALUE FixedMtrrValue[V_FIXED_MTRR_NUMBER]; + MTRR_VALUE VariableMtrrValue[V_MAXIMUM_VARIABLE_MTRR_NUMBER * 2]; + BOOLEAN FixedMtrrChanged; + BOOLEAN VariableMtrrChanged; + BOOLEAN NemDisabledDone; +} CACHE_PPI_INSTANCE; + +#define PEI_CACHE_PPI_INSTANCE_FROM_THIS(a) _CR (a, CACHE_PPI_INSTANCE, Ppi) + +/// +/// Breaking UINT64 MSR into DWORDs/BYTEs +/// +#pragma pack(1) +typedef union _MSR_REGISTER { + UINT64 Qword; + + struct _DWORDS { + UINT32 Low; + UINT32 High; + } Dwords; + + struct _BYTES { + UINT8 FirstByte; + UINT8 SecondByte; + UINT8 ThirdByte; + UINT8 FouthByte; + UINT8 FifthByte; + UINT8 SixthByte; + UINT8 SeventhByte; + UINT8 EighthByte; + } Bytes; + +} MSR_REGISTER; +#pragma pack() +#define NO_RESET 0 +#define CPU_ONLY_RESET 1 +#define WARM_RESET 2 +#define COLDRESET 3 + +#define RESET_PPI_WARM_RESET 0 +#define RESET_PPI_COLD_RESET 3 + +#define RESET_PORT 0x0CF9 +#define CLEAR_RESET_BITS 0x0F1 +#define PSIX_THRESHOLD_MASK 0x3FFFFFFF ///< Bits 61:32 - Mask value respect to Dword.High +#define PSI1_THRESHOLD_VALUE 0x14 +#define PSI2_THRESHOLD_VALUE 0x05 +#define PSI3_THRESHOLD_VALUE 0x01 + +#define MAX_OVERCLOCKING_BINS 0x7 + +/** + Set up flags in CR4 for XMM instruction enabling +**/ +VOID +XmmInit ( + VOID + ); + +/** + Loads the Processor Microcode & Install the Cache PPI + + @param[in] FfsHeader - Pointer to an alleged FFS file. + @param[in] PeiServices - General purpose services available to every PEIM. + + @retval EFI_STATUS - the status code returned from any sub-routine +**/ +EFI_STATUS +PeimInitializeCpu ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices + ); + +/** + Install CacheInitPpi + + @retval EFI_OUT_OF_RESOURCES - failed to allocate required pool +**/ +EFI_STATUS +CacheInitPpiInit ( + VOID + ); + +/** + Set CPU strap setting for feature change + + @param[in] PeiServices - Indirect reference to the PEI Services Table. + @param[in] NotifyDescriptor - Address of the notification descriptor data structure. Type + EFI_PEI_NOTIFY_DESCRIPTOR is defined above. + @param[in] Ppi - Address of the PPI that was installed. + + @retval EFI_SUCCESS - Function completed successfully +**/ +EFI_STATUS +EFIAPI +SetCpuStrap ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ); + +/** + Based on ResetType, perform warm or cold reset using PCH Reset PPI + + @param[in] PeiServices - Indirect reference to the PEI Services Table. + @param[in] ResetType - CPU_RESET_TYPE to indicate which reset shoudl be performed. + + @exception EFI_UNSUPPORTED - Reset type unsupported + @retval EFI_SUCCESS - function successfully (system should already reset) +**/ +EFI_STATUS +PerformWarmORColdReset ( + IN EFI_PEI_SERVICES **PeiServices, + IN CPU_RESET_TYPE ResetType + ); + +/** + Based on ResetType, perform warm or cold reset using PCH Reset PPI + + @param[in] PeiServices + @param[in] CPU_RESET_TYPE + + @retval EFI_STATUS + + Build BIST HOB + + @param[in] PeiServices - Indirect reference to the PEI Services Table. + @param[in] NotifyDescriptor - Address of the notification descriptor data structure. Type + EFI_PEI_NOTIFY_DESCRIPTOR is defined above. + @param[in] Ppi - Address of the PPI that was installed. + + @retval EFI_SUCCESS - Hob built or not necessary +**/ +EFI_STATUS +EFIAPI +BuildBistHob ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ); + +/** + Dump RC CPU and PPM platform policies + + @param[in] CpuPlatformPolicyPpi - Address of the cpu platform policy ppi. +**/ +VOID +CpuPeiPolicyDump( + IN PEI_CPU_PLATFORM_POLICY_PPI *CpuPlatformPolicyPpi + ); + +/** + + Perform the platform spefific initializations. + + @param[in] PeiServices - Indirect reference to the PEI Services Table. + @param[in] CpuPlatformPolicyPpi - Platform Policy PPI + +**/ +VOID +BootGuardInit ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CPU_PLATFORM_POLICY_PPI *CpuPlatformPolicyPpi + ); + +#endif diff --git a/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPeim.inf b/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPeim.inf new file mode 100644 index 0000000..6110b72 --- /dev/null +++ b/ReferenceCode/Haswell/CpuInit/Pei/CpuInitPeim.inf @@ -0,0 +1,124 @@ +# +# This file contains an 'Intel Pre-EFI Module' and is licensed +# for Intel CPUs and Chipsets under the terms of your license +# agreement with Intel or your vendor. This file may be +# modified by the user, subject to additional terms of the +# license agreement +# +#/*++ +# +# Copyright (c) 2007 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. + +# +# Module Name: +# +# CpuInitPeim.inf +# +# Abstract: +# +# Component description file for CPU module +# +# +#--*/ + +[defines] +BASE_NAME = CpuInitPeim +FILE_GUID = 01359D99-9446-456d-ADA4-50A711C03ADA +COMPONENT_TYPE = PE32_PEIM + +[sources.common] + CpuInitPeim.c + CachePeim.c + PfatInit.c + CpuOcInit.c + BootGuardInit.c + +# +# Edk II Glue Driver Entry Point +# + EdkIIGluePeimEntryPoint.c + +[sources.ia32] + Ia32/Cpu.asm + +[includes.common] + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Efi + $(EDK_SOURCE)/Foundation/Include + $(EDK_SOURCE)/Foundation/Efi/Include + $(EDK_SOURCE)/Foundation/Framework/Include + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Pei/Include + $(EDK_SOURCE)/Foundation/Cpu/Pentium/Include + $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include +# +# Edk II Glue Library, some hearder are included by R9 header so have to include +# + $(EFI_SOURCE) + $(EFI_SOURCE)/Framework + $(EDK_SOURCE)/Foundation + $(EDK_SOURCE)/Foundation/Framework + $(EDK_SOURCE)/Foundation/Include/IndustryStandard + $(EDK_SOURCE)/Foundation/Core/Dxe + $(EDK_SOURCE)/Foundation/Include/Pei + $(EDK_SOURCE)/Foundation/Library/Dxe/Include + $(EDK_SOURCE)/Foundation/Library/EdkIIGlueLib/Include + $(EFI_SOURCE)/$(PROJECT_CPU_ROOT) + $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Library/OverclockingLib + $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include + $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/Include/Library + $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/SampleCode + $(EFI_SOURCE)/$(PROJECT_CPU_ROOT)/SampleCode/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT) + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include + $(EFI_SOURCE)/$(PROJECT_PCH_ROOT)/Include/Library + $(EFI_SOURCE)/$(PROJECT_SA_ROOT) + $(EFI_SOURCE)/$(PROJECT_SA_ROOT)/Include + $(EFI_SOURCE)/$(PROJECT_ME_ROOT)/Library/MeKernel/Include + $(EFI_SOURCE)/$(PROJECT_ME_ROOT)/Heci/Include + +[libraries.common] + EdkFrameworkPpiLib + EdkIIGlueBaseLib + EdkIIGlueBaseMemoryLib + EdkIIGluePeiDebugLibReportStatusCode + EdkIIGluePeiReportStatusCodeLib + EdkIIGluePeiServicesLib + EdkIIGluePeiMemoryAllocationLib + EdkIIGluePeiHobLib + EdkPpiLib + CpuPpiLib + CpuGuidLib + $(PROJECT_PCH_FAMILY)PpiLib + PeiKscLib + CpuPlatformLib + OverclockingLib + BootGuardLib + +[libraries.ia32] + CpuIA32Lib + +[nmake.common] + IMAGE_ENTRY_POINT = _ModuleEntryPoint + DPX_SOURCE = CpuInitPeim.dxs + +# +# Module Entry Point +# + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_MODULE_ENTRY_POINT__=PeimInitializeCpu + C_FLAGS = $(C_FLAGS) -D __EDKII_GLUE_BASE_LIB__ \ + -D __EDKII_GLUE_BASE_MEMORY_LIB__ \ + -D __EDKII_GLUE_PEI_DEBUG_LIB_REPORT_STATUS_CODE__ \ + -D __EDKII_GLUE_PEI_REPORT_STATUS_CODE_LIB__ \ + -D __EDKII_GLUE_PEI_SERVICES_LIB__ diff --git a/ReferenceCode/Haswell/CpuInit/Pei/CpuOcInit.c b/ReferenceCode/Haswell/CpuInit/Pei/CpuOcInit.c new file mode 100644 index 0000000..8aa7cd7 --- /dev/null +++ b/ReferenceCode/Haswell/CpuInit/Pei/CpuOcInit.c @@ -0,0 +1,292 @@ +/** @file + OC CPU Early Post initializations. + +@copyright + Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement + +**/ + +/// +/// External include files do NOT need to be explicitly specified in real EDKII +/// environment +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGluePeim.h" +#include "CpuInitPeim.h" +#include "CpuAccess.h" +#include "OverclockingLibrary.h" +#include "CpuOcInit.h" +#endif + +/** + Initializes Overclocking settings in the processor. + + @param[in] PeiServices - General purpose services available to every PEIM. + @param[in] OverclockingtConfig Pointer to Policy protocol instance + + @retval EFI_SUCCESS +**/ +EFI_STATUS +CpuOcInit ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CPU_PLATFORM_POLICY_PPI *CpuPlatformPolicyPpi + ) +{ + EFI_STATUS Status; + OC_CAPABILITIES_ITEM OcCaps; + VOLTAGE_FREQUENCY_ITEM CurrentVfItem; + VOLTAGE_FREQUENCY_ITEM RequestedVfItem; + GLOBAL_CONFIG_ITEM CurrentFivrItem; + GLOBAL_CONFIG_ITEM RequestedFivrItem; + SVID_CONFIG_ITEM CurrentSvidItem; + SVID_CONFIG_ITEM RequestedSvidItem; + UINT32 LibStatus; + UINT8 DomainId; + UINT8 ResetRequired; + WDT_PPI *gWdtPei; + + LibStatus = 0; //DEBUG + ResetRequired = FALSE; + if (CpuPlatformPolicyPpi->OverclockingConfig->OcSupport == 0) { + /// + /// Overclocking is disabled + /// + DEBUG ((EFI_D_ERROR, "(OC) Overclocking is disabled. Bypassing CPU core overclocking flow.\n")); + return EFI_SUCCESS; + } + + Status = EFI_SUCCESS; + ZeroMem(&CurrentFivrItem,sizeof(CurrentFivrItem)); + ZeroMem(&RequestedFivrItem,sizeof(RequestedFivrItem)); + ZeroMem(&CurrentSvidItem,sizeof(CurrentSvidItem)); + ZeroMem(&RequestedSvidItem,sizeof(RequestedSvidItem)); + + // + // Locate WDT_PPI (ICC WDT PPI) + // + Status = PeiServicesLocatePpi ( + &gWdtPpiGuid, + 0, + NULL, + (VOID **) &gWdtPei + ); + ASSERT_EFI_ERROR (Status); + + /// + /// We will loop on the CPU domains to manage the voltage/frequency settings + /// + for (DomainId = OC_LIB_DOMAIN_ID_IA_CORE; DomainId < OC_LIB_DOMAIN_ID_UNCORE; DomainId++) { + /// + /// Only IA_CORE and CLR are valid for CPU Core + /// + if ((DomainId == OC_LIB_DOMAIN_ID_IA_CORE) || (DomainId == OC_LIB_DOMAIN_ID_CLR)) { + + /// + /// Get OC Capabilities of the domain + /// + ZeroMem(&OcCaps,sizeof(OcCaps)); + OcCaps.DomainId = DomainId; + Status = GetOcCapabilities(&OcCaps,&LibStatus); + + if (LibStatus == OC_LIB_COMPLETION_CODE_SUCCESS) { + /// + /// If any OC is supported on this domain, then proceed + /// + if (OcCaps.RatioOcSupported || OcCaps.VoltageOverridesSupported || OcCaps.VoltageOffsetSupported) { + /// + /// Need to populate the user requested settings from the platform policy + /// to determine if OC changes are desired. + /// + ZeroMem(&CurrentVfItem,sizeof(CurrentVfItem)); + CurrentVfItem.DomainId = DomainId; + + /// + /// Get a copy of the current domain VfSettings from the Mailbox Library + /// + Status = GetVoltageFrequencyItem(&CurrentVfItem,&LibStatus); + if ((Status != EFI_SUCCESS) || (LibStatus != OC_LIB_COMPLETION_CODE_SUCCESS)) { + continue; + } + + /// + /// Populate the user requested VfSettings struct + /// + ZeroMem(&RequestedVfItem,sizeof(RequestedVfItem)); + RequestedVfItem.DomainId = DomainId; + if (DomainId == OC_LIB_DOMAIN_ID_IA_CORE) { + RequestedVfItem.VfSettings.MaxOcRatio = (UINT8) CpuPlatformPolicyPpi->OverclockingConfig->CoreMaxOcTurboRatio; + } else if (DomainId == OC_LIB_DOMAIN_ID_CLR) { + RequestedVfItem.VfSettings.MaxOcRatio = (UINT8) CpuPlatformPolicyPpi->OverclockingConfig->ClrMaxOcTurboRatio; + } + + /// + /// VoltageTarget has 2 uses and we need to update the target based + /// on the voltagemode requested + /// + if (DomainId == OC_LIB_DOMAIN_ID_IA_CORE) { + RequestedVfItem.VfSettings.VoltageTargetMode = CpuPlatformPolicyPpi->OverclockingConfig->CoreVoltageMode; + if (RequestedVfItem.VfSettings.VoltageTargetMode == OC_LIB_OFFSET_ADAPTIVE) { + RequestedVfItem.VfSettings.VoltageTarget = CpuPlatformPolicyPpi->OverclockingConfig->CoreExtraTurboVoltage; + } else { + RequestedVfItem.VfSettings.VoltageTarget = CpuPlatformPolicyPpi->OverclockingConfig->CoreVoltageOverride; + } + RequestedVfItem.VfSettings.VoltageOffset = CpuPlatformPolicyPpi->OverclockingConfig->CoreVoltageOffset; + } else if (DomainId == OC_LIB_DOMAIN_ID_CLR) { + RequestedVfItem.VfSettings.VoltageTargetMode = CpuPlatformPolicyPpi->OverclockingConfig->ClrVoltageMode; + if (RequestedVfItem.VfSettings.VoltageTargetMode == OC_LIB_OFFSET_ADAPTIVE) { + RequestedVfItem.VfSettings.VoltageTarget = CpuPlatformPolicyPpi->OverclockingConfig->ClrExtraTurboVoltage; + } else { + RequestedVfItem.VfSettings.VoltageTarget = CpuPlatformPolicyPpi->OverclockingConfig->ClrVoltageOverride; + } + RequestedVfItem.VfSettings.VoltageOffset = CpuPlatformPolicyPpi->OverclockingConfig->ClrVoltageOffset; + } + + /// + /// Compare current settings with user requested settings to see if changes are needed + /// + if (CompareMem((VOID *)&RequestedVfItem,(VOID *)&CurrentVfItem,sizeof(VOLTAGE_FREQUENCY_ITEM))) { + /// + /// Arm watchdog timer for OC changes + /// + Status = gWdtPei->ReloadAndStart (WDT_TIMEOUT_BETWEEN_PEI_DXE); + + /// + /// Need to update the requested voltage/frequency values + /// + DEBUG ((EFI_D_INFO, "(OC) Set Voltage Frequency for Domain = %X\n", DomainId)); + DEBUG ((EFI_D_INFO, "(OC) RequestedVfItem.VfSettings.MaxOcRatio = %X\n", RequestedVfItem.VfSettings.MaxOcRatio)); + DEBUG ((EFI_D_INFO, "(OC) RequestedVfItem.VfSettings.TargetMode = %X\n", RequestedVfItem.VfSettings.VoltageTargetMode)); + DEBUG ((EFI_D_INFO, "(OC) RequestedVfItem.VfSettings.VoltageTarget = %X\n", RequestedVfItem.VfSettings.VoltageTarget)); + DEBUG ((EFI_D_INFO, "(OC) RequestedVfItem.VfSettings.VoltageOffset = %X\n", RequestedVfItem.VfSettings.VoltageOffset)); + DEBUG ((EFI_D_INFO, "(OC) CurrentVfItem.VfSettings.MaxOcRatio = %X\n", CurrentVfItem.VfSettings.MaxOcRatio)); + DEBUG ((EFI_D_INFO, "(OC) CurrentVfItem.VfSettings.TargetMode = %X\n", CurrentVfItem.VfSettings.VoltageTargetMode)); + DEBUG ((EFI_D_INFO, "(OC) CurrentVfItem.VfSettings.VoltageTarget = %X\n", CurrentVfItem.VfSettings.VoltageTarget)); + DEBUG ((EFI_D_INFO, "(OC) CurrentVfItem.VfSettings.VoltageOffset = %X\n", CurrentVfItem.VfSettings.VoltageOffset)); + Status = SetVoltageFrequencyItem(RequestedVfItem,&LibStatus); + if ((Status != EFI_SUCCESS) || (LibStatus != OC_LIB_COMPLETION_CODE_SUCCESS)) { + DEBUG ((EFI_D_ERROR, "(OC) Set Voltage Frequency failed. EFI Status = %X, Library Status = %X\n", Status, LibStatus)); + } + } + } + } else { + DEBUG ((EFI_D_ERROR, "(OC) GetOcCapabilities message failed. Library Status = %X, Domain = %X\n", LibStatus, DomainId)); + } + } + } + + /// + /// Detect changes to global FIVR settings + /// + Status = GetFivrConfig(&CurrentFivrItem,&LibStatus); + + if (LibStatus == OC_LIB_COMPLETION_CODE_SUCCESS) { + /// + /// Populate the requested FIVR settings from platform policy. The platform policy defines + /// these bits as 0-Disabled, 1-Enabled. The Mailbox uses the reverse encoding. Need to convert + /// the platform policy data to match the mailbox input. + /// + RequestedFivrItem.DisableFivrFaults = (~CpuPlatformPolicyPpi->OverclockingConfig->FivrFaultsEnable) & BIT0_MASK; + RequestedFivrItem.DisableFivrEfficiency = (~CpuPlatformPolicyPpi->OverclockingConfig->FivrEfficiencyEnable) & BIT0_MASK; + + /// + /// Compare current FIVR settings with requested FIVR settings to see if changes are needed + /// + if (CompareMem((VOID *)&RequestedFivrItem,(VOID *)&CurrentFivrItem,sizeof(GLOBAL_CONFIG_ITEM))) { + /// + /// Arm watchdog timer for OC changes + /// + Status = gWdtPei->ReloadAndStart (8); + + /// + /// Need to update the requested FIVR values + /// + DEBUG ((EFI_D_INFO, "(OC) Set FIVR Config for Domain = %X\n", DomainId)); + Status = SetFivrConfig(RequestedFivrItem, &LibStatus); + if ((Status != EFI_SUCCESS) || (LibStatus != OC_LIB_COMPLETION_CODE_SUCCESS)) { + DEBUG ((EFI_D_ERROR, "(OC) Set FIVR Config failed. EFI Status = %X, Library Status = %X\n", Status, LibStatus)); + } + else { + /// + /// If Re-enabling Fivr Faults, system needs to perform a cold reset for hardware to take effect + /// + if ((CurrentFivrItem.DisableFivrFaults == 1) && (RequestedFivrItem.DisableFivrFaults == 0)) { + DEBUG ((EFI_D_ERROR, "(OC) FIVR Faults enable detected. Cold Reset required.\n")); + ResetRequired = TRUE; + } + } + } + } + else { + DEBUG ((EFI_D_ERROR, "(OC) Get FIVR Config message failed. Library Status = %X\n", LibStatus)); + } + + /// + /// Detect changes to SVID settings + /// + Status = GetSvidConfig(&CurrentSvidItem,&LibStatus); + + if (LibStatus == OC_LIB_COMPLETION_CODE_SUCCESS) { + /// + /// Populate the requested SVID settings from platform policy. SvidDisable uses a + /// reverse encoding from the platform policy defintion and will need to be converted. + /// + RequestedSvidItem.VoltageTarget = CpuPlatformPolicyPpi->OverclockingConfig->SvidVoltageOverride; + RequestedSvidItem.SvidDisable = ~(CpuPlatformPolicyPpi->OverclockingConfig->SvidEnable) & BIT0_MASK; + + /// + /// Compare current SVID settings with requested SVID settings to see if changes are needed + /// + if (CompareMem((VOID *)&RequestedSvidItem,(VOID *)&CurrentSvidItem,sizeof(SVID_CONFIG_ITEM))) { + /// + /// Arm watchdog timer for OC changes + /// + Status = gWdtPei->ReloadAndStart (8); + + /// + /// If Re-enabling SVID, system needs to perform a cold reset for hardware to take effect. No write to mailbox needed. + /// + if ((CurrentSvidItem.SvidDisable == 1) && (RequestedSvidItem.SvidDisable == 0)) { + DEBUG ((EFI_D_ERROR, "(OC) SVID Enable detected. Cold Reset required.\n")); + ResetRequired = TRUE; + } + else { + /// + /// Need to update the requested SVID values + /// + DEBUG ((EFI_D_INFO, "(OC) Set SVID Config for Domain = %X\n", DomainId)); + Status = SetSvidConfig(RequestedSvidItem, &LibStatus); + if ((Status != EFI_SUCCESS) || (LibStatus != OC_LIB_COMPLETION_CODE_SUCCESS)) { + DEBUG ((EFI_D_ERROR, "(OC) Set SVID Config failed. EFI Status = %X, Library Status = %X\n", Status, LibStatus)); + } + } + } + } else { + DEBUG ((EFI_D_ERROR, "(OC) GetFivrConfig message failed. Library Status = %X\n", LibStatus)); + } + + /// + /// Command was successful and SVID config has changed. CPU must perform a reset + /// for SVID settings to take effect. + /// + if (ResetRequired) { + DEBUG ((EFI_D_ERROR, "(OC) Perform Cold Reset\n")); + PerformWarmORColdReset (PeiServices, COLDRESET); + } + + return Status; +} + diff --git a/ReferenceCode/Haswell/CpuInit/Pei/CpuOcInit.h b/ReferenceCode/Haswell/CpuInit/Pei/CpuOcInit.h new file mode 100644 index 0000000..652c67e --- /dev/null +++ b/ReferenceCode/Haswell/CpuInit/Pei/CpuOcInit.h @@ -0,0 +1,55 @@ +/** @file + Describes the functions visible to the rest of the OcInit. + +@copyright + Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _OC_INIT_H_ +#define _OC_INIT_H_ + +#include "OverclockingLibrary.h" +#include EFI_PPI_DEFINITION (CpuPlatformPolicy) +#include EFI_PPI_CONSUMER (Wdt) + +#ifdef USE_WDT_IN_DEBUG_BIOS +// +// MRC takes a lot of time to execute in debug mode +// +#define WDT_TIMEOUT_BETWEEN_PEI_DXE 120 +#else +#define WDT_TIMEOUT_BETWEEN_PEI_DXE 60 +#endif + +/// +/// Function Prototypes +/// +/** + Initializes Overclocking settings in the processor. + + @param[in] PeiServices - General purpose services available to every PEIM. + @param[in] OverclockingtConfig Pointer to Policy protocol instance + + @retval EFI_SUCCESS +**/ +EFI_STATUS +CpuOcInit ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CPU_PLATFORM_POLICY_PPI *CpuPlatformPolicyPpi + ); + +#endif + diff --git a/ReferenceCode/Haswell/CpuInit/Pei/Ia32/Cpu.asm b/ReferenceCode/Haswell/CpuInit/Pei/Ia32/Cpu.asm new file mode 100644 index 0000000..e7c812a --- /dev/null +++ b/ReferenceCode/Haswell/CpuInit/Pei/Ia32/Cpu.asm @@ -0,0 +1,77 @@ +; +; This file contains an 'Intel Pre-EFI Module' and is licensed +; for Intel CPUs and Chipsets under the terms of your license +; agreement with Intel or your vendor. This file may be +; modified by the user, subject to additional terms of the +; license agreement +; +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2012 Intel Corporation. All rights reserved +; This software and associated documentation (if any) is furnished +; under a license and may only be used or copied in accordance +; with the terms of the license. Except as permitted by such +; license, no part of this software or documentation may be +; reproduced, stored in a retrieval system, or transmitted in any +; form or by any means without the express written consent of +; Intel Corporation. +; +; +; Module Name: +; +; Cpu.asm +; +; Abstract: +; +; Assembly code of Cpu +; +;------------------------------------------------------------------------------ + + .686p + .model flat + .xmm + +IA32_CR4_OSFXSR equ 200h +IA32_CR4_OSXMMEXCPT equ 400h +IA32_CR0_MP equ 2h + +IA32_CPUID_SSE2 equ 02000000h +IA32_CPUID_SSE2_B equ 26 + + .code + +;------------------------------------------------------------------------------ +; Set up flags in CR4 for XMM instruction enabling +;------------------------------------------------------------------------------ +XmmInit PROC C PUBLIC + push ebx + + ; Check whether SSE2 is supported + mov eax, 1 + cpuid + bt edx, IA32_CPUID_SSE2_B + jnc @F + + ; Enable XMM + mov eax, cr0 + or eax, IA32_CR0_MP + mov cr0, eax + mov eax, cr4 + or eax, IA32_CR4_OSFXSR OR IA32_CR4_OSXMMEXCPT + mov cr4, eax + +@@: + pop ebx + ret +XmmInit ENDP + + +;------------------------------------------------------------------------------ +; Invalidate cache +;------------------------------------------------------------------------------ +CacheInvd PROC C PUBLIC + invd + ret +CacheInvd ENDP + + END diff --git a/ReferenceCode/Haswell/CpuInit/Pei/PfatInit.c b/ReferenceCode/Haswell/CpuInit/Pei/PfatInit.c new file mode 100644 index 0000000..8eff986 --- /dev/null +++ b/ReferenceCode/Haswell/CpuInit/Pei/PfatInit.c @@ -0,0 +1,191 @@ +/** @file + PFAT EarlyPost initializations. + +@copyright + Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ + +/// +/// External include files do NOT need to be explicitly specified in real EDKII +/// environment +/// +#if !defined(EDK_RELEASE_VERSION) || (EDK_RELEASE_VERSION < 0x00020000) +#include "EdkIIGluePeim.h" +#include "CpuInitPeim.h" +#include "CpuAccess.h" +#include "PfatInit.h" +#ifdef PFAT_EC_FLAG +#include EFI_PPI_DEPENDENCY (CpuIo) +#include EFI_PPI_PRODUCER (Stall) +#include "PeiKscLib.h" +#endif //PFAT_EC_FLAG +#endif + +#ifdef PFAT_EC_FLAG +/** + Gets CPU's random number generator. + + @param[out] UINT32 - Random value +**/ +UINT32 +RandomNumber ( + void + ) +{ + UINT32 Random = 0; + + /// + /// Assembly instruction to read CPU's random number generator + /// Instruction is only available 100k cycles after reset + /// + __asm { +tryAgain: + ; rdrand eax + ; db 0Fh, 0C7h, 0F0h + + _emit 0x0F + _emit 0xC7 + _emit 0xF0 + + mov Random, eax + jnc tryAgain; CF will be set is valid number was generated + } + + return (Random); +} +#endif //PFAT_EC_FLAG + +/** + Perform the platform spefific initializations. + + @param[in] PeiServices - Indirect reference to the PEI Services Table. + @param[in] CpuPlatformPolicyPpi - Platform Policy PPI +**/ +VOID +PfatInit ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CPU_PLATFORM_POLICY_PPI *CpuPlatformPolicyPpi + ) +{ + EFI_STATUS Status; + UINT64 MsrValue; + BOOLEAN ResetRequired; + PFAT_HOB *PfatHobPtr; + EFI_GUID PfatHobGuid = PFAT_HOB_GUID; + UINT8 i; + PFAT_CONFIG *PfatConfig; +#ifdef PFAT_EC_FLAG + volatile UINT32 EphemeralAuthValue; + UINT8 EcStatus; + PEI_STALL_PPI *StallPpi; + PEI_CPU_IO_PPI *CpuIo; +#endif //PFAT_EC_FLAG + + DEBUG ((EFI_D_INFO, "PfatInit\n")); + + ResetRequired = FALSE; + MsrValue = AsmReadMsr64 (MSR_PLATFORM_INFO); + if (!(MsrValue & B_MSR_PLATFORM_INFO_PFAT_AVAIL)) { + DEBUG ((EFI_D_INFO, "PFAT Feature is not supported\n")); + return; + } + + if (CpuPlatformPolicyPpi->CpuConfig->Pfat) { + DEBUG ((EFI_D_INFO, "PFAT Module is Enable\n")); + PfatConfig = CpuPlatformPolicyPpi->SecurityConfig->PfatConfig; + /// + /// Read PFAT Control Register + /// + MsrValue = AsmReadMsr64 (MSR_PLAT_FRMW_PROT_CTRL); + if (MsrValue & B_MSR_PLAT_FRMW_PROT_CTRL_LK) { + if (!(MsrValue & B_MSR_PLAT_FRMW_PROT_CTRL_EN)) { + /// + /// Reset required as the PFAT CTRL MSR is locked and needs to be toggled + /// + ResetRequired = TRUE; + } + } else { +#ifdef PFAT_EC_FLAG + if ((PfatConfig->Ppdt.PlatAttr & EC_PRESENT) && (PfatConfig->Ppdt.PlatAttr & EC_PFAT_PROTECTED)) { + DEBUG ((EFI_D_INFO, "EC is Present and EC FW supports PFAT\n")); + CpuIo = (**PeiServices).CpuIo; + Status = (*PeiServices)->LocatePpi (PeiServices, &gPeiStallPpiGuid, 0, NULL, &StallPpi); + ASSERT_PEI_ERROR (PeiServices, Status); + Status = SendKscCommand (PeiServices, CpuIo, StallPpi, PfatConfig->EcCmdProvisionEav); + if (Status == EFI_SUCCESS) { + EphemeralAuthValue = RandomNumber (); + for (i = 0; (i < (sizeof (EphemeralAuthValue))); i++) { + Status = SendKscData (PeiServices, CpuIo, StallPpi, (UINT8) ((EphemeralAuthValue >> (i * 8)) & 0xFF)); + } + Status = ReceiveKscData (PeiServices, CpuIo, StallPpi, &EcStatus); + if (EcStatus != 0) { + ResetRequired = TRUE; + } + AsmWriteMsr32 (MSR_PLAT_FRMW_PROT_PASSWD, EphemeralAuthValue); + EphemeralAuthValue = 0; + Status = SendKscCommand (PeiServices, CpuIo, StallPpi, PfatConfig->EcCmdLock); + } + } +#endif //PFAT_EC_FLAG + AsmWriteMsr64 (MSR_PLAT_FRMW_PROT_HASH_0, PfatConfig->PpdtHash[0]); + AsmWriteMsr64 (MSR_PLAT_FRMW_PROT_HASH_1, PfatConfig->PpdtHash[1]); + AsmWriteMsr64 (MSR_PLAT_FRMW_PROT_HASH_2, PfatConfig->PpdtHash[2]); + AsmWriteMsr64 (MSR_PLAT_FRMW_PROT_HASH_3, PfatConfig->PpdtHash[3]); + MsrValue |= (B_MSR_PLAT_FRMW_PROT_CTRL_LK | B_MSR_PLAT_FRMW_PROT_CTRL_EN); + AsmWriteMsr64 (MSR_PLAT_FRMW_PROT_CTRL, MsrValue); + } + /// + /// Create PFAT HOB + /// + if (!ResetRequired) { + Status = (*PeiServices)->CreateHob (PeiServices, EFI_HOB_TYPE_GUID_EXTENSION, sizeof (PFAT_HOB), (VOID **) &PfatHobPtr); + PfatHobPtr->EfiHobGuidType.Name = PfatHobGuid; + CopyMem (&PfatHobPtr->Ppdt, &PfatConfig->Ppdt, PfatConfig->Ppdt.PpdtSize); + CopyMem (&PfatHobPtr->PupHeader, &PfatConfig->PupHeader, sizeof (PUP_HEADER)); + CopyMem (&PfatHobPtr->PfatLog, &PfatConfig->PfatLog, sizeof (PFAT_LOG)); + PfatHobPtr->NumSpiComponents = PfatConfig->NumSpiComponents; + for (i = 0; i < PfatConfig->NumSpiComponents; i++) { + PfatHobPtr->ComponentSize[i] = PfatConfig->ComponentSize[i]; + } + } + } else { + DEBUG ((EFI_D_INFO, "PFAT Module is Disabled\n")); + MsrValue = AsmReadMsr64 (MSR_PLAT_FRMW_PROT_CTRL); + if (MsrValue & B_MSR_PLAT_FRMW_PROT_CTRL_LK) { + if (MsrValue & B_MSR_PLAT_FRMW_PROT_CTRL_EN) { + /// + /// Reset required as the PFAT CTRL MSR is locked and needs to be toggled + /// + ResetRequired = TRUE; + } + } else { + MsrValue &= ~B_MSR_PLAT_FRMW_PROT_CTRL_EN; + MsrValue |= B_MSR_PLAT_FRMW_PROT_CTRL_LK; + AsmWriteMsr64 (MSR_PLAT_FRMW_PROT_CTRL, MsrValue); + } + } + + if (ResetRequired) { + /// + /// Perform Cold Reset + /// + DEBUG ((EFI_D_INFO, "Reset Required. Performing Cold Reset to unlock PFAT CONTROL MSR\n")); + PerformWarmORColdReset (PeiServices, COLDRESET); + } + + return; +} diff --git a/ReferenceCode/Haswell/CpuInit/Pei/PfatInit.h b/ReferenceCode/Haswell/CpuInit/Pei/PfatInit.h new file mode 100644 index 0000000..22e807f --- /dev/null +++ b/ReferenceCode/Haswell/CpuInit/Pei/PfatInit.h @@ -0,0 +1,42 @@ +/** @file + Describes the functions visible to the rest of the PfatInit. + +@copyright + Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _PFAT_INIT_H_ +#define _PFAT_INIT_H_ + +#include "PfatDefinitions.h" +#include EFI_PPI_DEFINITION (CpuPlatformPolicy) + +/// +/// Function Prototypes +/// +/** + Execute Early-Post initialization of PFAT specific MSRs + + @param[in] PeiServices - Indirect reference to the PEI Services Table. + @param[in] CpuPlatformPolicyPpi - Platform Policy PPI +**/ +VOID +PfatInit ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CPU_PLATFORM_POLICY_PPI *CpuPlatformPolicyPpi + ); + +#endif |