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Diffstat (limited to 'ReferenceCode/Haswell/Protocol/CpuPlatformPolicy')
3 files changed, 657 insertions, 0 deletions
diff --git a/ReferenceCode/Haswell/Protocol/CpuPlatformPolicy/CpuPlatformPolicy.c b/ReferenceCode/Haswell/Protocol/CpuPlatformPolicy/CpuPlatformPolicy.c new file mode 100644 index 0000000..906c2e5 --- /dev/null +++ b/ReferenceCode/Haswell/Protocol/CpuPlatformPolicy/CpuPlatformPolicy.c @@ -0,0 +1,26 @@ +/** @file + Protocol used for specifying platform related CPU information and policy setting. + +@copyright + Copyright (c) 1999 - 2012 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#include "Tiano.h" +#include EFI_PROTOCOL_DEFINITION (CpuPlatformPolicy) + +EFI_GUID gDxeCpuPlatformPolicyProtocolGuid = DXE_CPU_PLATFORM_POLICY_PROTOCOL_GUID; + +EFI_GUID_STRING + (&gDxeCpuPlatformPolicyProtocolGuid, "CPU Platform Policy", "Platform related CPU information and policy settings"); diff --git a/ReferenceCode/Haswell/Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h b/ReferenceCode/Haswell/Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h new file mode 100644 index 0000000..37fe5a1 --- /dev/null +++ b/ReferenceCode/Haswell/Protocol/CpuPlatformPolicy/CpuPlatformPolicy.h @@ -0,0 +1,329 @@ +/** @file + Protocol used for specifying platform related CPU information and policy setting. + +@copyright + Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _CPU_PLATFORM_POLICY_H_ +#define _CPU_PLATFORM_POLICY_H_ + +#include "CpuPmConfig.h" + +#include EFI_PROTOCOL_DEFINITION (MpService) +#include EFI_GUID_DEFINITION (DataHubRecords) + +#if (EFI_SPECIFICATION_VERSION >= 0x2000A) +#include EFI_PROTOCOL_DEFINITION (HiiDatabase) +#else +#include EFI_PROTOCOL_DEFINITION (Hii) +#endif + +EFI_FORWARD_DECLARATION (DXE_CPU_PLATFORM_POLICY_PROTOCOL_GUID); +#define DXE_CPU_PLATFORM_POLICY_PROTOCOL_GUID \ + { \ + 0x1279e288, 0x24cd, 0x47e9, 0x96, 0xba, 0xd7, 0xa3, 0x8c, 0x17, 0xbd, 0x64 \ + } + +/// +/// Protocol revision number +/// Any backwards compatible changes to this protocol will result in an update in the revision number +/// Major changes will require publication of a new protocol +/// + +/// +/// Revision 1: Initial version +/// +#define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_1 1 +/// +/// Revision 2: Added CPU_CONFIG.DebugInterfaceEnable +/// Added CPU_CONFIG.DebugInterfaceLockEnable +/// +#define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_2 2 +/// +/// Revision 3: Added CPU_CONFIG.ApIdleManner +/// Added CPU_CONFIG.ApHandoffManner +/// +#define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_3 3 + +/// +/// Revision 4: Added POWER_MGMT_CONFIG.THERM_FUNCTION_ENABLES.Pl1ThermalControl +/// +#define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_4 4 +/// +/// Revision 5: Added POWER_MGMT_CONFIG.PPM_TURBO_SETTINGS.PowerLimit3 +/// POWER_MGMT_CONFIG.PPM_TURBO_SETTINGS.PowerLimit3Time +/// POWER_MGMT_CONFIG.PPM_TURBO_SETTINGS.PowerLimit3DutyCycle +/// POWER_MGMT_CONFIG.PPM_TURBO_SETTINGS.PowerLimit3Lock +/// +#define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_5 5 + +/// +/// Revision 6: Added POWER_MGMT_CONFIG.CustomPowerUnit .Support for user to configuration custom Power Limts in milli watts +/// Default Power Unit for follwing Items changes to MilliWatts +/// POWER_MGMT_CONFIG.PPM_TURBO_SETTINGS +/// PowerLimit1 +/// PowerLimit2 +/// PowerLimit3 +/// POWER_MGMT_CONFIG.PPM_CUSTOM_CTDP +/// CustomPowerLimit1 +/// CustomPowerLimit2 +/// +/// + +#define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_6 6 + +/// +/// Revision 7: Added POWER_MGMT_CONFIG.THERM_FUNCTION_ENABLES.Pl1ThermalControlFloor. Changed definition of +/// POWER_MGMT_CONFIG.THERM_FUNCTION_ENABLES.Pl1ThermalControl from 1 (enable) to 1 (enable/manual) +/// POWER_MGMT_CONFIG.THERM_FUNCTION_ENABLES.Pl1ThermalControlFloor +/// + +#define DXE_PLATFORM_CPU_POLICY_PROTOCOL_REVISION_7 7 + + +extern EFI_GUID gDxeCpuPlatformPolicyProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _DXE_CPU_PLATFORM_POLICY_PROTOCOL DXE_CPU_PLATFORM_POLICY_PROTOCOL; + +// +// Prototypes for the Platform CPU Protocol +// + +/// +/// This function is for platform code to provide Microcode location since different BIOS has different flash layout. +/// Platform code need to provide a function for CPU code to call to get the Microcode location in flash or memory. +/// +typedef +EFI_STATUS +(EFIAPI *PLATFORM_CPU_RETRIEVE_MICROCODE)( + IN DXE_CPU_PLATFORM_POLICY_PROTOCOL *This, + OUT UINT8 **MicrocodeData + ); + +typedef struct { + UINT32 Package; + UINT32 Die; + UINT32 Core; + UINT32 Thread; +} CPU_PHYSICAL_LOCATION; + +/// +/// The platform category, Server, Desktop and Mobile are defined. +/// +typedef enum { + CpuPlatformUnknown= 0, + CpuPlatformDesktop, + CpuPlatformMobile, + CpuPlatformServer, + CpuPlatformMax +} CPU_PLATFORM_CATEGORY; + +/// +/// The reason for changing the state of the processor Only applies to Disabling processors. +/// In future, we can add add/remove support +/// +#define CPU_CAUSE_NOT_DISABLED 0x0000 +#define CPU_CAUSE_INTERNAL_ERROR 0x0001 +#define CPU_CAUSE_THERMAL_ERROR 0x0002 +#define CPU_CAUSE_SELFTEST_FAILURE 0x0004 +#define CPU_CAUSE_PREBOOT_TIMEOUT 0x0008 +#define CPU_CAUSE_FAILED_TO_START 0x0010 +#define CPU_CAUSE_CONFIG_ERROR 0x0020 +#define CPU_CAUSE_USER_SELECTION 0x0080 +#define CPU_CAUSE_BY_ASSOCIATION 0x0100 +#define CPU_CAUSE_UNSPECIFIED 0x8000 + +typedef UINT32 CPU_STATE_CHANGE_CAUSE; + +typedef struct { + EFI_MP_PROC_CONTEXT *Context; + EFI_EXP_BASE10_DATA CoreFreq; + EFI_EXP_BASE10_DATA BusFreq; + EFI_EXP_BASE2_DATA CacheSize[EFI_CACHE_LMAX]; + EFI_PROCESSOR_ID_DATA CpuId; + EFI_PROCESSOR_MICROCODE_REVISION_DATA MuData; + EFI_PROCESSOR_STATUS_DATA Status; +} EFI_DETAILED_CPU_INFO; + +/// +/// Platform Specific Processor Information +/// +typedef struct { + UINT64 ApicID; ///< APIC ID + STRING_REF ReferenceString; ///< Reference String + EFI_PROCESSOR_SOCKET_TYPE_DATA SocketType; ///< Socket Type + EFI_PROCESSOR_SOCKET_NAME_DATA SocketName; ///< Socket Name + EFI_PROCESSOR_MAX_CORE_FREQUENCY_DATA MaxCoreFrequency; ///< Maximum Core Frequency + EFI_PROCESSOR_MAX_FSB_FREQUENCY_DATA MaxFsbFrequency; ///< Maximum FSB Frequency + EFI_PROCESSOR_CORE_FREQUENCY_LIST_DATA PlatformCoreFrequencyList; ///< Platform Core Frequency List + EFI_PROCESSOR_FSB_FREQUENCY_LIST_DATA PlatformFsbFrequencyList; ///< Platform FSB Frequency List + STRING_REF AssetTag; ///< Asset Tag + EFI_HII_HANDLE StringHandle; ///< String Handle + STRING_REF SerialNumber; ///< Serial Number + STRING_REF PartNumber; ///< Part Number +} PLATFORM_CPU_INFORMATION; + +/// +/// This interface is for platform to provide processor support layout, such as how many packages we want +/// processor code to support. If return EFI_UNSUPPORTED, processor code will assume MAXIMUM_CPU_NUMBER and +/// allocate MAX memory for all APs. +/// +typedef +EFI_STATUS +(EFIAPI *PLATFORM_CPU_GET_MAX_COUNT)( + IN DXE_CPU_PLATFORM_POLICY_PROTOCOL *This, + OUT UINT32 *MaxThreadsPerCore, + OUT UINT32 *MaxCoresPerDie, + OUT UINT32 *MaxDiesPerPackage, + OUT UINT32 *MaxPackages + ); + +/// +/// Platform code can provide platform specific processor information, such as processor socket Name on board, +/// processor Socket Type, and so on for SMBIOS table creation. +/// +typedef +EFI_STATUS +(EFIAPI *PLATFORM_CPU_GET_CPU_INFO)( + IN DXE_CPU_PLATFORM_POLICY_PROTOCOL *This, + IN CPU_PHYSICAL_LOCATION *Location, + IN OUT PLATFORM_CPU_INFORMATION *PlatformCpuInfo + ); + +// +// Generic definitions for device enabling/disabling used by CPU code +// +#define CPU_FEATURE_ENABLE 1 +#define CPU_FEATURE_DISABLE 0 + +// +// Generic definitions for DTS +// +#define DTS_OUT_OF_SPEC_ONLY 2 +#define DTS_OUT_OF_SPEC_OCCURRED 3 + +/// +/// General CPU feature Configuration for all processor features enabling bit definitions are in this field. +/// Platform code can enable/disable features thru this field. +/// +typedef struct { + // + // Byte 0, bit definition for functionality enable/disable + // + UINT8 HtState : 1; ///< Enable or Disable Hyper Threading State; 0: Disable; 1: Enable + UINT8 LimitCpuidMaximumValue : 1; ///< Enable or Disable Limit Cpuid Maximum Value; 0: Disable; 1: Enable + UINT8 DcaState : 1; ///< @deprecated Deprecated for Client (Server specific) + UINT8 ExecuteDisableBit : 1; ///< Enable or Disable Execute Disable Bit; 0: Disable; 1: Enable + UINT8 VmxEnable : 1; ///< Enable or Disable VMX; 0: Disable; 1: Enable + UINT8 SmxEnable : 1; ///< Enable or Disable SMX; 0: Disable; 1: Enable + UINT8 FastString : 1; ///< @deprecated + UINT8 MachineCheckEnable : 1; ///< Enable or Disable Machine Check; 0: Disable; 1: Enable + // + // Byte 1, bit definition for functionality enable/disable + // + UINT8 MonitorMwaitEnable : 1; ///< Enable or Disable Monitor Mwait mode; 0: Disable; 1: Enable + UINT8 XapicEnable : 1; ///< Enable or Disable Xapic mode; 0: Disable; 1: Enable + UINT8 MachineCheckStatusClean : 1; ///< @deprecated + UINT8 IsColdReset : 1; ///< Check if is Cold Reset; 0: Not Cold Reset; 1: Cold Reset + UINT8 MlcStreamerPrefetcher : 1; ///< Enable or Disable MlcStreamerPrefetcher; 0: Disable; 1: Enable + UINT8 MlcSpatialPrefetcher : 1; ///< Enable or Disable MlcSpatialPrefetcher; 0: Disable; 1: Enable + UINT8 EnableDts : 2; ///< Enable or Disable DTS feature; 0=Disable; 1=Enable; 2=OUT_OF_SPEC; + // + // Byte 2, byte definition for addiional functionalities expected later + // + UINT8 FviReport : 1; ///< Enable or Disable FVI report; 0: Disable; 1: Enable + UINT8 AesEnable : 1; ///< Enable or Disable AES feature; 0: Disable; 1: Enable + UINT8 DebugInterfaceEnable : 1; ///< Enable or Disable Debug Interface; This policy must be disabled for production BIOS. <b>0: Disable</b>; 1: Enable + UINT8 DebugInterfaceLockEnable : 1; ///< Enable or Disable Debug Interface Lock; This policy must be enabled on production platforms. 0: Disable; <b>1: Enable</b> + UINT8 ApIdleManner : 2; ///< Settings for AP Threads Idle; 1: HALT 2:MWAIT 3:RUN + UINT8 ApHandoffManner : 2; ///< Settings for AP Handoff to OS; 1: HALT 2:MWAIT32 + // + // CPU feature configuration + // + UINT8 BspSelection; ///< Select BSP + UINT32 DcaPrefetchDelayValue; ///< @deprecated Deprecated for Client (Server specific) + UINT8 VirtualWireMode; ///< @deprecated + UINT8 SmmbaseSwSmiNumber; ///< SW SMI Number from Smbase. + // + // CPU Misc Config + // + UINT8 FviSmbiosType; ///< Create SMBIOS Table Type for FVI + // + // Functions provided by platform code + // + /// + /// Platform code can provide microcode location thru this function. + /// + PLATFORM_CPU_RETRIEVE_MICROCODE RetrieveMicrocode; + /// + /// Platform to provide the processor detail about Max Thread per Core, Max Cores per Die, Max Dies per + /// Package and Max packages. + /// + PLATFORM_CPU_GET_MAX_COUNT GetMaxCount; + /// + /// Platform code to provide platform specific processor information + /// + PLATFORM_CPU_GET_CPU_INFO GetCpuInfo; +} CPU_CONFIG; + +/// +/// TxT Platform Configuration +/// +typedef struct { + UINT8 ResetAux : 1; ///< Reset Auxiliary content when it is set "TRUE" + UINT8 Reserved : 7; ///< Reserved for future use + UINT8 ByetReserved[1]; ///< Reserved for future use +} TXT_FUNCTION_CONFIG; + + +/// +/// All processor security features enabling definitions are in this field. +/// Platform code can enable/disable features thru this field. +/// +typedef struct { + TXT_FUNCTION_CONFIG *TxtFunctionConfig; +} SECURITY_CONFIG; + +/// +/// The CPU platform policy protocol allows the platform code to publish a set of configuration information that the +/// CPU drivers will use to configure the processor. Platform code needs to provide the information for processor +/// drivers to finish the initialization. +/// +typedef struct _DXE_CPU_PLATFORM_POLICY_PROTOCOL { + /// + /// This member specifies the revision of the CPU Policy protocol. This field is used to indicate backwards + /// compatible changes to the protocol. Platform code that produces this protocol must fill with the correct revision + /// value for the PCH reference code to correctly interpret the content of the protocol fields. + /// + UINT8 Revision; + /// + /// Processor standard features configuration. + /// + CPU_CONFIG *CpuConfig; + /// + /// Processor power management features configuration. + /// + POWER_MGMT_CONFIG *PowerMgmtConfig; + /// + /// Processor security features configuration. + /// + SECURITY_CONFIG *SecurityConfig; +} DXE_CPU_PLATFORM_POLICY_PROTOCOL; + +#endif diff --git a/ReferenceCode/Haswell/Protocol/CpuPlatformPolicy/CpuPmConfig.h b/ReferenceCode/Haswell/Protocol/CpuPlatformPolicy/CpuPmConfig.h new file mode 100644 index 0000000..d84ccab --- /dev/null +++ b/ReferenceCode/Haswell/Protocol/CpuPlatformPolicy/CpuPmConfig.h @@ -0,0 +1,302 @@ +/** @file + Describes the defintions / functions visible to the rest of the PPM. + +@copyright + Copyright (c) 2011 - 2013 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by such + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + + This file contains an 'Intel Peripheral Driver' and uniquely + identified as "Intel Reference Module" and is + licensed for Intel CPUs and chipsets under the terms of your + license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the + license agreement +**/ +#ifndef _CPU_PM_CONFIG_H_ +#define _CPU_PM_CONFIG_H_ + +/// +/// Define maximum number of custom ratio states supported +/// +#define MAX_CUSTOM_RATIO_TABLE_ENTRIES 16 + +/// +/// Define maximum number of custom ConfigTdp entries supported +/// +#define MAX_CUSTOM_CTDP_ENTRIES 3 + +/// +/// This structure is used to describe the custom processor ratio table desired by the platform +/// +typedef struct { + /// + /// The number of custom ratio state entries, it must be a value from 2 to 16 for a valid custom ratio table. + /// + UINT8 NumberOfEntries; + UINT32 Cpuid; ///< The CPU ID for which this custom ratio table applies. + UINT16 MaxRatio; ///< The maximum ratio of the custom ratio table. + UINT16 StateRatio[MAX_CUSTOM_RATIO_TABLE_ENTRIES]; ///< The processor ratios in the custom ratio table. +} PPM_CUSTOM_RATIO_TABLE; + +/// +/// This structure is used to describe which of the PPM functions will be enabled by PPM implementation. +/// +typedef struct { + UINT32 Eist : 1; ///< Enable or Disable Intel SpeedStep Technology. + UINT32 Cx : 1; ///< Enable or Disable CPU power states (C-states). + UINT32 C1e : 1; ///< Enable or Disable Enhanced C-states. + UINT32 C3 : 1; ///< Enable or Disable C3. + UINT32 C6 : 1; ///< Enable or Disable C6. + UINT32 DeepCState : 3; ///< Enable or Disable C7/C7S. + UINT32 LongLatencyC6 : 1; ///< Enable or Disable C6 Long Latency. + UINT32 LongLatencyC7 : 1; ///< Enable or Disable C7 Long Latency. + UINT32 C8 : 1; ///< Enable or Disable C8. + UINT32 C9 : 1; ///< Enable or Disable C9. + UINT32 C10 : 1; ///< Enable or Disable C10. + UINT32 C1AutoDemotion : 1; ///< Enable or Disable C1 Auto Demotion. + UINT32 C3AutoDemotion : 1; ///< Enable or Disable C3 Auto Demotion. + UINT32 TurboMode : 1; ///< Enable or Disable long duration Turbo Mode. + UINT32 PowerLimit2 : 1; ///< Enable or Disable short duration Turbo Mode. + UINT32 EnergyEfficientPState : 1; ///< Enable or Disable Energy Efficient P-state will be applied in Turbo mode. + UINT32 BiProcHot : 1; ///< @deprecated in Powermgmt policy and moved to THERM_FUNCTION_ENABLES. + UINT32 TStates : 1; ///< @deprecated in Powermgmt policy and moved to THERM_FUNCTION_ENABLES. + UINT32 Xe : 1; ///< Enable or Disable Intel Extreme Edition support. + UINT32 C1UnDemotion : 1; ///< Enable or Disable C1UnDemotion. + UINT32 C3UnDemotion : 1; ///< Enable or Disable C3UnDemotion. + UINT32 PkgCStateDemotion : 1; ///< Enable or Disable Package Cstate Demotion. + UINT32 PkgCStateUnDemotion : 1; ///< Enable or Disable Package Cstate UnDemotion. + UINT32 DisableProcHotOut : 1; ///< @deprecated in Powermgmt policy and moved to THERM_FUNCTION_ENABLES. + UINT32 DisableVRThermalAlert : 1; ///< @deprecated in Powermgmt policy and moved to THERM_FUNCTION_ENABLES. + UINT32 ProcHotResponce : 1; ///< @deprecated in Powermgmt policy and moved to THERM_FUNCTION_ENABLES. + UINT32 AutoThermalReporting : 1; ///< @deprecated in Powermgmt policy and moved to THERM_FUNCTION_ENABLES. + UINT32 CStatePreWake : 1; ///< Enable or Disable CState-Pre wake. + UINT32 ThermalMonitor : 1; ///< @deprecated in Powermgmt policy and moved to THERM_FUNCTION_ENABLES. + UINT32 LakeTiny : 1; ///< Enable or Disable LakeTiny Support. + UINT32 TimedMwait : 1; ///< Enable or Disable TimedMwait Support. + UINT32 Reserved : 2; ///< Bits reserved for future use. +} PPM_FUNCTION_ENABLES; + +/// +/// This structure is used to describe various PPM turbo settings +/// +typedef struct _PPM_TURBO_SETTINGS { + UINT16 PowerLimit1; ///< Package Long duration turbo mode power limit in 125mw or watts. + UINT32 PowerLimit1Time; ///< Package Long duration turbo mode time window in seconds. + UINT16 PowerLimit2; ///< Package Short duration turbo mode power limit in 125mw or watts. + /// + /// Describes whether TURBO_POWER_LIMIT[63] should be set. Setting this bit will lock all Turbo settings. + /// + UINT8 TurboPowerLimitLock; + UINT16 DdrPowerLimit1; ///< @deprecated in Powermgmt policy + UINT32 DdrPowerLimit1Time; ///< @deprecated in Powermgmt policy + UINT16 DdrPowerLimit2; ///< @deprecated in Powermgmt policy + UINT8 DdrPowerLimitLock; ///< @deprecated in Powermgmt policy + /// + /// Configuration for boot TDP selection, value 0 describes TDP Nominal, value 1 describes TDP Down and + /// value 2 describes TDP Up. + /// + UINT8 ConfigTdpLevel; + /// + /// Configurable TDP Mode Lock can be sets the to Lock ConfigTdp mode settings from runtime change. + /// + UINT8 ConfigTdpLock; + UINT8 ConfigTdpBios; ///< Configuration whether load Configurable TDP SSDT. + UINT8 EnergyPolicy; ///< Describes the Energy efficiency policy to be set in MSR 0x1B0. + + // + // PL3 configuration + // + UINT16 PowerLimit3; ///< Package PL3 power limit in 125mw or watts. + UINT32 PowerLimit3Time; ///< Package PL3 time window in seconds. + UINT8 PowerLimit3DutyCycle; ///< Package PL3 Duty Cycle. + UINT8 PowerLimit3Lock; ///< Package PL3 MSR 615h lock. + +} PPM_TURBO_SETTINGS; + +/// +/// PPM Custom ConfigTdp Settings +/// +typedef struct _PPM_CUSTOM_CTDP_TABLE { + UINT16 CustomPowerLimit1; ///< Short term Power Limit value for custom cTDP level in 125mw or watts. + UINT16 CustomPowerLimit2; ///< Long term Power Limit value for custom cTDP level in 125mw or watts. + UINT8 CustomPowerLimit1Time; ///< Short term Power Limit time window value for custom cTDP level. + UINT8 CustomTurboActivationRatio; ///< Turbo Activation Ratio for custom cTDP level. + UINT8 CustomConfigTdpControl; ///< Config Tdp Control (0/1/2) value for custom cTDP level. +} PPM_CUSTOM_CTDP_TABLE; + +/// +/// This structure is used to configure custom ConfigTdp level settings. +/// +typedef struct _PPM_CUSTOM_CTDP { + UINT8 ConfigTdpCustom; ///< Describes whether or not Custom Config Tdp should be enabled. + UINT8 CustomTdpCount; ///< Describes the number of Custom Config Tdp levels required (1/2/3). + UINT8 CustomBootModeIndex; ///< Describes the Boot mode index selection from Custom Tdp levels.Index to CustomConfigTdpTable. valid values are 0,1,2. + /// + /// Describes the details of each Custom Config Tdp levels. This supports up to MAX_CUSTOM_CTDP_ENTRIES number + /// of Custom ConfigTdp levels. + /// + PPM_CUSTOM_CTDP_TABLE CustomConfigTdpTable[MAX_CUSTOM_CTDP_ENTRIES]; +} PPM_CUSTOM_CTDP; + +/// +/// This structure is used to control enabled / disabled various PPM MSR lock settings +/// +typedef struct _PPM_LOCK_ENABLES { + UINT32 PmgCstCfgCtrlLock : 1; ///< Setting this to 1 will set MSR 0xE2[15] + UINT32 OverclockingLock : 1; ///< Setting this to 1 will set MSR 0x194[20] + UINT32 ProcHotLock : 1; ///< Setting this to 1 will set MSR 0x1FC[23] + UINT32 Reserved : 29; ///< Bits reserved for future use. +} PPM_LOCK_ENABLES; +/// +/// PM Deep C State Limit +/// +typedef enum { + Disabled = 0, + DeepC7, + DeepC7S +} DEEP_C_STATE; +/// +/// PPM Package C State Limit +/// +typedef enum { + PkgC0C1 = 0, + PkgC2, + PkgC3, + PkgC6, + PkgC7, + PkgC7s, + PkgC8, + PkgC9, + PkgC10, + PkgCMax, + PkgCpuDefault = 254, + PkgAuto = 255 +} MAX_PKG_C_STATE; +/// +/// PPM Package C State Time Limit +/// +typedef enum { + TimeUnit1ns = 0, + TimeUnit32ns, + TimeUnit1024ns, + TimeUnit32768ns, + TimeUnit1048576ns, + TimeUnit33554432ns +} C_STATE_TIME_UNIT; +/// +/// Custom Power Uints.User can choose to enter in MilliWatts or Watts +/// +typedef enum { + PowerUnitWatts = 0, ///< in Watts + PowerUnit125MilliWatts, ///< in 125 Milli Watts. Example 11.250 W Value to use for Power limts 90 + PowerUnitMax +} CUSTOM_POWER_UNIT; + +typedef enum { + Percent5 = 242, + Percent10 = 229, + Percent15 = 217, + Percent20 = 204, + Percent25 = 191, + Percent30 = 178, + Percent35 = 166, + Percent40 = 153, + Percent45 = 140, + Percent50 = 127, + Percent55 = 115, + Percent60 = 102, + Percent65 = 89, + Percent70 = 76, + Percent75 = 64, + Percent80 = 51, + Percent85 = 38, + Percent90 = 25, + Percent95 = 13, + Percent100 = 0 +} PL1_THERMAL_THROTTLE_FLOOR_UNIT; + +typedef struct { + PL1_THERMAL_THROTTLE_FLOOR_UNIT FloorIA; /// < FLOOR_IA, Default: 0 (Percent100) + PL1_THERMAL_THROTTLE_FLOOR_UNIT FloorGT; /// < FLOOR_GT, Default: 0 (Percent100) + PL1_THERMAL_THROTTLE_FLOOR_UNIT FloorPCH; /// < FLOOR_PCH, Default: 0 (Percent100) +} PL1_THERMAL_CONTROL_FLOOR; + +/// +/// This structure is used to describe which of the Thermal functions will be enabled by Thermal implementation. +/// +typedef struct { + UINT16 BiProcHot : 1; ///< Enable or Disable Bi-Directional PROCHOT#. + UINT16 TStates : 1; ///< Enable or Disable T states. + UINT16 DisableProcHotOut : 1; ///< Enable or Disable PROCHOT# signal being driven externally. + UINT16 DisableVRThermalAlert : 1; ///< Enable or Disable VR Thermal Alert. + UINT16 ProcHotResponce : 1; ///< Enable or Disable PROCHOT# Responce. + UINT16 AutoThermalReporting : 1; ///< Enable or Disable Thermal Reporting through ACPI tables. + UINT16 ThermalMonitor : 1; ///< Enable or Disable Thermal Monitor. + UINT16 Pl1ThermalControl : 2; ///< Disable(0), Enable/Manual(1), Auto(2) PL1 thermal throttling features + UINT16 ThermReserved : 7; ///< Reserved + PL1_THERMAL_CONTROL_FLOOR Pl1ThermalControlFloor; ///< PL1 Floor Throttle Values +} THERM_FUNCTION_ENABLES; + +/// +/// Power management Configuration for all processor Power Management features enabling definitions are in this field. +/// Platform code can enable/disable features thru this field. +/// +typedef struct { + /// + /// This structure is used to describe which of the PPM functions should be enabled. For details of this structure, + /// please see Related Definitions. + /// + PPM_FUNCTION_ENABLES *pFunctionEnables; + /// + /// This structure is used to describe the custom CPU Frequency Table that should be used. For details of this + /// structure, please see Related Definitions. + /// + PPM_CUSTOM_RATIO_TABLE *pCustomRatioTable; + /// + /// This structure is used to describe long duration and short duration turbo settings. For details of this + /// structure, please see Related Definitions. + /// + PPM_TURBO_SETTINGS *pTurboSettings; + UINT8 S3RestoreMsrSwSmiNumber; ///< SW SMI number to restore the power Mgmt MSRs during S3 resume. + UINT8 *pRatioLimit; ///< This field is a pointer to Ratio Limit. + PPM_LOCK_ENABLES *pPpmLockEnables; ///< This field is a pointer to PPM_LOCK_ENABLES structure. + PPM_CUSTOM_CTDP *pCustomCtdpSettings; ///< This structure is used to describe the custom config TDP settings. + /// + /// This field is used to set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state. + /// + MAX_PKG_C_STATE PkgCStateLimit; + C_STATE_TIME_UNIT CstateLatencyControl0TimeUnit; ///< TimeUnit for Latency Control0 MSR 0x60A[12:10]. + C_STATE_TIME_UNIT CstateLatencyControl1TimeUnit; ///< TimeUnit for Latency Control1 MSR 0x60B[12:10]. + C_STATE_TIME_UNIT CstateLatencyControl2TimeUnit; ///< TimeUnit for Latency Control2 MSR 0x60C[12:10]. + C_STATE_TIME_UNIT CstateLatencyControl3TimeUnit; ///< TimeUnit for Latency Control3 MSR 0x633[12:10]. + C_STATE_TIME_UNIT CstateLatencyControl4TimeUnit; ///< TimeUnit for Latency Control4 MSR 0x634[12:10]. + C_STATE_TIME_UNIT CstateLatencyControl5TimeUnit; ///< TimeUnit for Latency Control5 MSR 0x635[12:10]. + UINT16 CstateLatencyControl0Irtl; ///< Interrupt Response Time Limit of LatencyContol0 MSR 0x60A[9:0]. + UINT16 CstateLatencyControl1Irtl; ///< Interrupt Response Time Limit of LatencyContol1 MSR 0x60B[9:0]. + UINT16 CstateLatencyControl2Irtl; ///< Interrupt Response Time Limit of LatencyContol2 MSR 0x60C[9:0]. + UINT16 CstateLatencyControl3Irtl; ///< Interrupt Response Time Limit of LatencyContol3 MSR 0x633[9:0]. + UINT16 CstateLatencyControl4Irtl; ///< Interrupt Response Time Limit of LatencyContol4 MSR 0x634[9:0]. + UINT16 CstateLatencyControl5Irtl; ///< Interrupt Response Time Limit of LatencyContol5 MSR 0x635[9:0]. + BOOLEAN RfiFreqTunningOffsetIsNegative; ///< Specify RfiFreqTunningOffset is Positive or Negative. + UINT8 RfiFreqTunningOffset; ///< specify the Target FIVR Frequency offset. + /// + /// Calibrate 24MHz BCLK support; 0: NO_CALIBRATE, 1: PCODE_CALIBRATE, 2: BIOS_CALIBRATE (Default :1) + /// + UINT8 PcodeCalibration; + BOOLEAN EnableRerunPcodeCalibration; ///< Calibrate C state 24MHz BCLK support. + /// + /// This structure is used to describe which of the Thermal functions should be enabled. For details of this + /// structure, please see Related Definitions. + /// + THERM_FUNCTION_ENABLES *ThermalFuncEnables; + CUSTOM_POWER_UNIT CustomPowerUnit; ///< Power Management Custom Power Limit Unit. + +} POWER_MGMT_CONFIG; + +#endif |