1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
|
/** @file
SwitchableGraphics Pei driver.
This Pei driver initialize GPIO programming
for the platform.
@copyright
Copyright (c) 2010 - 2012 Intel Corporation. All rights reserved
This software and associated documentation (if any) is furnished
under a license and may only be used or copied in accordance
with the terms of the license. Except as permitted by such
license, no part of this software or documentation may be
reproduced, stored in a retrieval system, or transmitted in any
form or by any means without the express written consent of
Intel Corporation.
This file contains an 'Intel Peripheral Driver' and uniquely
identified as "Intel Reference Module" and is
licensed for Intel CPUs and chipsets under the terms of your
license agreement with Intel or your vendor. This file may
be modified by the user, subject to additional terms of the
license agreement
**/
#include "SwitchableGraphicsInit.h"
#include EFI_GUID_DEFINITION (SaDataHob)
#ifdef SG_SUPPORT
/**
Initialize the SwitchableGraphics support (PEI).
@param[in] PeiServices - Pointer to the PEI services table
@param[in] SaPlatformPolicyPpi - SaPlatformPolicyPpi to access the GtConfig related information
**/
VOID
SwitchableGraphicsInit (
IN EFI_PEI_SERVICES **PeiServices,
IN SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi
)
{
EFI_STATUS Status;
PEI_STALL_PPI *StallPpi;
EFI_GUID StallPpiGuid = PEI_STALL_PPI_GUID;
UINT16 GpioAddress;
SA_DATA_HOB *SaDataHob;
BOOLEAN SgDgpuPrsntGpioIsValid = TRUE;
CPU_FAMILY CpuFamilyId;
CpuFamilyId = GetCpuFamily();
///
/// Get SaDataHob HOB
///
SaDataHob = NULL;
SaDataHob = (SA_DATA_HOB *) GetFirstGuidHob (&gSaDataHobGuid);
if (SaDataHob != NULL) {
SaDataHob->SgInfo.SgMode = SaPlatformPolicyPpi->PlatformData->SgMode;
SaDataHob->SgInfo.PXFixedDynamicMode = SaPlatformPolicyPpi->PlatformData->PXFixedDynamicMode; // AMI_OVERRIDE_FOR ATI 5.0 Fixed/Dynamic
///
/// GPIO Assigned from policy
///
SaDataHob->SgInfo.SgGpioSupport = SaPlatformPolicyPpi->SgGpioData->GpioSupport;
if (SaPlatformPolicyPpi->SgGpioData->GpioSupport == 1) {
///
/// Get GPIO Base Address
///
GpioAddress = MmPci16 (0, 0, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_GPIO_BASE) &~BIT0;
SaDataHob->SgInfo.SgDgpuPwrOK = SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrOK->Value;
SaDataHob->SgInfo.SgDgpuHoldRst = SaPlatformPolicyPpi->SgGpioData->SgDgpuHoldRst->Value;
SaDataHob->SgInfo.SgDgpuPwrEnable = SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrEnable->Value;
SaDataHob->SgInfo.SgDgpuPrsnt = SaPlatformPolicyPpi->SgGpioData->SgDgpuPrsnt->Value;
///
/// Set Bit7 as indicator for GPIO Active Low/High
///
SaDataHob->SgInfo.SgDgpuPwrOK |= (SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrOK->Active << 7);
SaDataHob->SgInfo.SgDgpuHoldRst |= (SaPlatformPolicyPpi->SgGpioData->SgDgpuHoldRst->Active << 7);
SaDataHob->SgInfo.SgDgpuPwrEnable |= (SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrEnable->Active << 7);
SaDataHob->SgInfo.SgDgpuPrsnt |= (SaPlatformPolicyPpi->SgGpioData->SgDgpuPrsnt->Active << 7);
if (CpuFamilyId == EnumCpuHswUlt) {
PEI_DEBUG ((PeiServices, EFI_D_INFO, "SgDgpuPrsntGpioIsValid = FALSE\n"));
SgDgpuPrsntGpioIsValid = FALSE;
}
///
/// Locate PPI stall service
///
Status = (**PeiServices).LocatePpi (
PeiServices,
&StallPpiGuid,
0,
NULL,
&StallPpi
);
if (!EFI_ERROR (Status)) {
///
/// if DGPU PRSNT is Disabled, it means that MXM card was not detected, and
/// DGPU HOLD RST must be driven high to allow the board to support a normal PEG card
///
if ( (SgDgpuPrsntGpioIsValid)
&& (GpioRead (PeiServices, CpuFamilyId, GpioAddress, SaDataHob->SgInfo.SgDgpuPrsnt) == GP_DISABLE)) {
GpioWrite (PeiServices, CpuFamilyId, GpioAddress, SaDataHob->SgInfo.SgDgpuHoldRst, GP_DISABLE);
///
/// Set SG mode as disabled
///
SaDataHob->SgInfo.SgMode = SgModeDisabled;
} else {
///
/// DGPU PRSNT Enabled. MXM is present.
/// If PEG Mode or SG Muxless
/// Power on MXM
/// Configure GPIOs to drive MXM in PEG mode or SG Muxless
/// else
/// Do Nothing
///
if ((SaPlatformPolicyPpi->PlatformData->SgMode == SgModeMuxless) ||
(SaPlatformPolicyPpi->PlatformData->SgMode == SgModeDgpu)) {
PEI_DEBUG ((PeiServices, EFI_D_INFO, "Configure GPIOs for driving the dGPU.\n"));
///
/// Drive DGPU HOLD RST Enable to make sure we hold reset
///
GpioWrite (PeiServices, CpuFamilyId, GpioAddress, SaDataHob->SgInfo.SgDgpuHoldRst, GP_ENABLE);
///
/// wait 100ms
///
StallPpi->Stall (
PeiServices,
StallPpi,
SG_DELAY_HOLD_RST
);
///
/// Drive DGPU PWR EN to Power On MXM
///
GpioWrite (PeiServices, CpuFamilyId, GpioAddress, SaDataHob->SgInfo.SgDgpuPwrEnable, GP_ENABLE);
///
/// wait 300ms
///
StallPpi->Stall (
PeiServices,
StallPpi,
SG_DELAY_PWR_ENABLE
);
///
/// Drive DGPU HOLD RST Disabled to remove reset
///
GpioWrite (PeiServices, CpuFamilyId, GpioAddress, SaDataHob->SgInfo.SgDgpuHoldRst, GP_DISABLE);
///
/// wait 100ms
///
StallPpi->Stall (
PeiServices,
StallPpi,
SG_DELAY_HOLD_RST
);
}
}
}
}
}
///
/// Program SubsystemID for IGFX
///
PEI_DEBUG ((PeiServices, EFI_D_INFO, "Program SDID [Subsystem ID] for IGFX: 0x%x\n", SaPlatformPolicyPpi->PlatformData->SgSubSystemId));
McD2PciCfg16Or (PCI_SID, SaPlatformPolicyPpi->PlatformData->SgSubSystemId);
}
/**
SG GPIO Read
@param[in] PeiServices - General purpose services available to every PEIM
@param[in] CpuFamilyId - Specifies the CPU family
@param[in] GpioAddress - GPIO base address
@param[in] Value - PCH GPIO number
@retval GPIO read value (0/1)
**/
BOOLEAN
GpioRead (
EFI_PEI_SERVICES **PeiServices,
CPU_FAMILY CpuFamilyId,
IN UINT16 GpioAddress,
IN UINT8 Value
)
{
BOOLEAN Active;
UINT16 BitOffset=0;
UINT32 Data;
Active = (BOOLEAN) (Value >> 7);
Value &= 0x7F;
ASSERT (GpioAddress != 0);
if (CpuFamilyId == EnumCpuHswUlt) {
GpioAddress += R_PCH_GP_N_CONFIG0 + (Value * 0x08);
BitOffset = 30; //GPI_LVL
} else {
if (Value < 0x20) {
GpioAddress += R_PCH_GPIO_LVL;
BitOffset = Value;
} else if (Value < 0x40) {
GpioAddress += R_PCH_GPIO_LVL2;
BitOffset = Value - 0x20;
} else {
GpioAddress += R_PCH_GPIO_LVL3;
BitOffset = Value - 0x40;
}
}
Data = IoRead32 (GpioAddress);
Data >>= BitOffset;
if (Active == 0) {
Data = ~Data;
}
return (BOOLEAN) (Data & 0x1);
}
/**
SG GPIO Write
@param[in] PeiServices - General purpose services available to every PEIM
@param[in] CpuFamilyId - Specifies the CPU family
@param[in] GpioAddress - GPIO base address
@param[in] Value - PCH GPIO number
@param[in] Level - Write SG GPIO value (0/1)
@retval none
**/
VOID
GpioWrite (
EFI_PEI_SERVICES **PeiServices,
CPU_FAMILY CpuFamilyId,
IN UINT16 GpioAddress,
IN UINT8 Value,
IN BOOLEAN Level
)
{
BOOLEAN Active;
UINT32 Data;
UINT16 BitOffset=0;
Active = (BOOLEAN) (Value >> 7);
Value &= 0x7F;
if (Active == 0) {
Level = (~Level) & 0x1;
}
ASSERT (GpioAddress != 0);
if (CpuFamilyId == EnumCpuHswUlt) {
GpioAddress += R_PCH_GP_N_CONFIG0 + (Value * 0x08);
BitOffset = 31; //GPO_LVL
} else {
if (Value < 0x20) {
GpioAddress += R_PCH_GPIO_LVL;
BitOffset = Value;
} else if (Value < 0x40) {
GpioAddress += R_PCH_GPIO_LVL2;
BitOffset = Value - 0x20;
} else {
GpioAddress += R_PCH_GPIO_LVL3;
BitOffset = Value - 0x40;
}
}
Data = IoRead32 (GpioAddress);
Data &= ~(0x1 << BitOffset);
Data |= (Level << BitOffset);
IoWrite32 (GpioAddress, Data);
return ;
}
#endif //SG_SUPPORT
|
