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| author | Ronald Cron <ronald.cron@arm.com> | 2014-08-19 13:29:52 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-08-19 13:29:52 +0000 |
| commit | 3402aac7d985bf8a9f9d3c639f3fe93609380513 (patch) | |
| tree | 67b11334dc45181581aaaac236243fe72c7f614c /ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm | |
| parent | 62d441fb17d59958bf00c4a1f3b52bf6a0b40b24 (diff) | |
| download | edk2-platforms-3402aac7d985bf8a9f9d3c639f3fe93609380513.tar.xz | |
ARM Packages: Removed trailing spaces
Trailing spaces create issue/warning when generating/applying patches.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm')
| -rw-r--r-- | ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm index 8c27093045..53283d1eea 100644 --- a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm +++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm @@ -1,4 +1,4 @@ -//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
@@ -43,12 +43,12 @@ XP_ON EQU ( 0x1:SHL:23 ) ArmInvalidateDataCacheEntryByMVA
- mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
+ mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
bx lr
ArmCleanDataCacheEntryByMVA
- mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
+ mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
bx lr
@@ -105,7 +105,7 @@ ArmEnableDataCache ORR R0,R0,R1 ;Set C bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
-
+
ArmDisableDataCache
LDR R1,=DC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
@@ -119,7 +119,7 @@ ArmEnableInstructionCache ORR R0,R0,R1 ;Set I bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
BX LR
-
+
ArmDisableInstructionCache
LDR R1,=IC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
@@ -141,17 +141,17 @@ ArmDisableBranchPrediction ASM_PFX(ArmDataMemoryBarrier):
mov R0, #0
- mcr P15, #0, R0, C7, C10, #5
+ mcr P15, #0, R0, C7, C10, #5
bx LR
-
+
ASM_PFX(ArmDataSyncronizationBarrier):
mov R0, #0
- mcr P15, #0, R0, C7, C10, #4
+ mcr P15, #0, R0, C7, C10, #4
bx LR
-
+
ASM_PFX(ArmInstructionSynchronizationBarrier):
MOV R0, #0
- MCR P15, #0, R0, C7, C5, #4
+ MCR P15, #0, R0, C7, C5, #4
bx LR
END
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